Dataram DTM65521A memory module
Contents
1. 3 De emphasis is disabled in the calibration state 4 Includes all sources of AC common mode noise 5 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition 6 Specified at the package pins into a voltage compliance test load Transmitters must meet both single ended and differential output E1 specifications 7 This specification considered with Vrx IDLE se DC implies a maximum 15mV single ended DC offset between Tx and Rx pins during the electrical idle condition This in turn allows a ground offset between adjacent FB DIMM agents of 26mV when worst case termination resistance matching is considered 8 The maximum value is specified to be at least VTX DIFFp p L 4 VTX CML VTX CM ACp p 2 9 This number does not include the effects of SSC or reference clock jitter 10 These timing specifications apply to resync mode only 11 Defined as the dual dirac deterministic jitter as described in Section 4 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 12 Pulse width measured at OV differential 13 The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 5 with regard to the average of the values measured at 100mV and at 400mV for that pin 14 Lane to Lane skew at the Transmitter pins for an end component 15 Lane to Lane skew at the Transmitter pins for an intermediate compo2. DTM65521A Le Ac Ze Sach MO Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 35 mm high Data Transfer Rate 5 3 Gigabytes sec Operating Voltage VDD 1 8 V 0 1 VCC 1 5V 0 1 SMBus interface to AMB for configuration register access MBIST and IBIST test functions Transparent mode for DDR2 SDRAM test support Full DIMM Heat Spreader High speed differential point to point link Fully ROHS Compliant Identification DTM65521A 256Mx72 2GB 2Rx8 PC2 5300F 555 11 B0 Performance range rhe beten ef A P 333MHz DDR2 667 5 5 5 Description The DTM65521A is a Dual Rank PC2 5300 Fully Buffered 256MX72 ECC DIMM that conforms to the JEDEC FB DIMM standard Each rank is comprised of nine Hynix 128Mx8 DDR2 DRAMs One IDT Rev C1 Advanced Memory Buffer AMB is used as the interface between the system memory bus and DIMM DRAMs One 2K bit EEPROM is used for Serial Presence Detect For improved thermal performance a Full DIMM Heat Spreader with thermal interface material TIM is attached to the front and back of the DIMM Clock Module Speed CL trco trp Pin Configurations Pin Names Front side Back side Pin Names Function 1 VDD 31 PN3 61 PN9 91 PS9 121 VDD 151 SN3 181 SN9 211 SS9 SCK SCK_ System Clock Input 2 VDD 32 PN3 62 VSS 92 VSS 122 VDD 152 SN3 182 VSS 212 VSS PN PN 13 0 Primary Northbound Data 3 VDD 33 VSS 63 PN10 93 PS5 123
3. a y 9 zy vo 9 a So Q Q n o y 2 SQ 3 8 Sag g 8 88 SERGE g g 88 a ax ii a ir DQ 31 24 o 1 0 7 0 1 0 7 0 DQ 63 56 O 1 0 7 0 1 O 7 0 DQS17 k DQS8 O k DQS8 O 3 8 8 28 3 8 8 28 scL gt wk SDA ea la a 0 gt o E e SPD CB 7 0 o I 0 7 0 1 0 7 0 WP TT SA0 SA1 SA2 PNO PN13 DQ0 DQ63 PNO PN13 CBO CB7 All address command control clock VW Vrt PSO PS9 DQS0 DQS17 PSO PS9 DQS0 DQS8 SNO SN13 A S0 gt CS DO D8 SN0 SN13 CKEO gt CKE DO D8 SS0 SS9 M S1 gt ICS D9 D17 VTT gt Terminators 1SS0 SS9 B CKE1 gt CKE D9 D17 See ODT gt ODT all SDRAMs VCC AMB X BAO BA2 all SDRAMs Y SA1 SA2 _ A0 A15 all SDRAMs sao A RAS all SDRAMs VDDSPD D SPD AMB CAS all SDRAMs L RESET ME all SDRAMs P SCK8 SCK CK amp CK all SDRAMs VDD DRAMS AMB VREF L DRAMS There are two physical copies of each address command control clock T vss de A A DRAMS SPD AMB Document 06054 Revision A 1 Aug 08 Dataram Corporation O 2008 Page 3 DTM65521A 2 GB 256Mx72 240 Pin FB DIMM DATARAM Absolute Maximum Ratings Parameter Symbol Rating Unit Note Temperature DDR2 DRAM Case Tcase 0 to 95 C 1 2 Temperature Storage Tste 55 to 100 C 1 Voltage on any pin relative to Vss Vin Vout 0 3 to 1 75 V 1 Voltage on Vcc relative to Vss Vec 0
4. 3 to 1 75 V 1 Voltage on Vpp relative to Vss Vop 0 5 to 2 3 V 1 Voltage on Ver relative to Vss Vit 0 5 to 2 3 V 1 Power Dissipation Pp 21 W 1 NOTES 1 Operation at or above absolute maximum rating can adversely affect device reliability 2 For85C lt Tcase lt 95 C treri 3 9 us max DC Operating Conditions Ta O to 70 C Voltage referenced to Vss OV Parameter Symbol Minimum Typical Maximum Unit Note AMB Supply Voltage Vcc 1 425 1 5 1 59 V DDR2 Supply Voltage Von 1 7 1 8 1 9 V Termination Voltage Vit 0 48 x VDD 0 50 x VDD 0 52 x VDD V EEPROM Supply Voltage SPD Vppspp 3 0 3 3 3 6 V Input High Voltage SPD ViHoc 2 1 Voppspp V 1 Input Low Voltage SPD Vioc 1 0 V 1 Input High Voltage RESET BFUNC ViHoc 1 0 V 2 Input Low Voltage RESET BFUNC Vit oc 0 5 V 1 Leakage Curent RESET BFUNC IL 90 90 yA 2 Leakage Curent Link I 5 5 UA Notes 1 Applies to SMB and SPD bus signals 2 Applies to AMB CMOS signal RESET Document 06054 Revision A 1 Aug 08 Dataram Corporation O 2008 Page 4 DTM65521A DATARAM Differential Transmitter Output Specification 2 GB 256Mx72 240 Pin FB DIMM Parameter Symbol MIN MAX Units Differential peak to peak output voltage for large voltage VTX DIFFp p_L 1 900 1300 mV swing VTX DIFFp p 2 VTX D VTX D Differential peak to peak output voltage for regular voltage
5. 7 DTM65521A HAAL 2GB 256mx72 240 Pin FB DIMM NOTES FOR RECEIVER INPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliant test setup Note that signal levels at the pad are lower than at the pin 2 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition Worst case margins are determined by comparing El levels with common mode levels during normal operation for the case with transmitter using small voltage swing see RX Single ended Electrical Idle Levels and RX Common Mode Levels 3 Multiple lanes need to detect the El condition before the device can act upon the El detection 4 Specified at the package pins into a timing and voltage compliance test setup 5 This specification considered with VTX IDLE SE DC implies a maximum 15mV single ended DC offset between TX and RX pins during the electrical idle condition This in turn allows a ground offset between adjacent FB DIMM of 26mV when worstcase termination resistance matching is considered 6 The single pulse mask provides sufficient symbol energy for reliable RX reception Each symbol complies with both the single pulse mask and the cumulative eye mask see RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Early and RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Late 7 The relative amplitude ratio limit between adjacent symbols prevents exce
6. 9 us 2 NOTES 1 For0 C lt Tcase 85 C 2 For85C lt Tcase 95 C Document 06054 Revision A 1 Aug 08 Dataram Corporation 2008 Page 12 DTM65521A DATARAM 2 GB 256Mx72 240 Pin FB DIMM SERIAL PRESENCE DETECT MATRIX For Reference Onl 176Bytes Number of Serial PD Bytes Written SPD Device Size CRC Coverage 256 Bytes Bytes 0 116 SPD Revision Key Byte DRAM Device Type Super Voltage Levels of this Assembly GEO ed SDRAM Addressing Ko N 1 2 3 Thickness 7 0 lt x lt 8 0 Height 30 lt x lt 35 Module Type Thickness FBDIMM 7 Module Organization 2 Rank x8 Fine Timebase Dividend and Divisor D Medium Timebase Dividend 0 25 ns 10 Medium Timebase Divisor 11 SDRAM Minimum Cycle Time tCKmin 12 SDRAM Maximum Cycle Time tCKmax 13 SDRAM CAS Latencies Supported 15n s Module Physical Attributes o ojojo gt o m m u Olalo ajajOo al 90 w0 nojojo a ar 14 15 ns 15 16 17 18 19 20 21 22 SDRAM Upper Nibbles fortRAS and tRC O 23 24 8 25 SDRAM Minimum Auto Refresh to Active Auto Refresh CMD Period tRFC LSB 127 5 ns 26 SDRAM Minimum Auto Refresh to Active Auto Refresh CMD Period tRFC MSB 27 28 29 SDRAM Burst Lengths Supported LH 30 31 SDRAM Average Refresh Interval tREFI Double Refresh mode bit High 7 8 us c Temperature 9H 2 33 Bits 7 4 Tcasemax Delta SDRAM case temperature difference between maximum 10 59 case 34 Thermal resistanc
7. In tbass 0 25 0 25 CLK Data In Setup Time to DQS In DQ amp DM tos 0 100 ns 7 Data In Hold Time to DQS In DQ amp DM ton 0 175 ns 7 NOTES 1 This calculation accounts for toaselmax the pulse width distortion of on chip and jitter For command address input slew rate gt 1 0V ns CK CK slew rates are gt 1 0V ns DARON guaranteed by design or tester correlation N For command address input slew rate gt 0 5V ns and lt 1 0V ns Data latched at both rising and falling edges of Data Strobes DQS Data sampled at the rising edges of the clock A0 A13 BAO BA2 CKE S 1 0 RAS CAS WE These Parameters guarantee device timing but they are not necessarily tested on each device and they may be Document 06054 Revision A 1 Aug 08 Dataram Corporation 2008 Page 11 DTM65521A DATARAM 2 GB 256Mx72 240 Pin FB DIMM AC Operating Conditions AC operating conditions unless otherwise noted Min Max F Parameter Symbol Unit Note Value Value DQ Input Pulse Width toipw 0 35 CLK Read DQS Preamble Time trPRE 0 9 1 1 CLK Read DQS Postamble Time trest 0 4 0 6 CLK Write DQS Preamble Hold Time twrre 0 35 CLK Write DQS Postamble Time twest 0 4 0 6 CLK Mode Register Set Delay turo 2 CLK Exit Self Refresh to Non Read Command txsnr tRFC 10 ns Exit Self Refresh to Read Command txsrp 200 CLK DS 7 8 us 1 Average Periodic Refresh Interval Ioer 3
8. VDD 153 VSS 183 SN10 213 SS5 PS PS 9 0 Primary Southbound Data 4 VSS 34 PN4 64 PN10 94 PS5 124 VSS 154 SN4 184 SN10 214 SS5 SN SN 13 0 Secondary Northbound Data 5 VDD 35 PN4 65 VSS 95 VSS 125 VDD 155 SN4 185 VSS 215 VSS SS SS 9 0 Secondary Southbound Data 6 VDD 36 VSS 66 PN11 96 PS6 126 VDD 156 VSS 186 SN11 216 SS6 SCL Serial Clock EEPROM 7 VDD 37 PN5 67 PN11 97 PS6 127 VDD 157 SN5 187 SN11 217 SS6 SDA Serial Data EEPROM 8 VSS 38 PN5 68 VSS 98 VSS 128 VSS 158 SN5 188 VSS 218 VSS RESET AMB Reset Signal 9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 VSS 189 VSS 219 SS7 VCC AMB Core Power and AMB Channel 10 VCC 40 PN13 70 PSO 100 PS7 130 VCC 160 SN13 190 SSO 220 SS7 nterface Power 1 5 V 11 VSS 41 PN13 171 PSO 101 VSS 131 VSS 161 SN13 191 SSO 221 VSS VDD DRAM Power and AMB DRAM UO 12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 192 VSS 222 SS8 Power 1 8 V 13 VCC 43 VSS 73 PS1 103 PS8 133 VCC 163 VSS 193 SS1 223 SS8 VTT DRAM Address Command Clock 14 VSS 44 RFU 74 IPS14 104 VSS 134 VSS 164 RFU1 194 SS1 224 VSS Termination Power VDD 2 15 VTT 45 RFU 75 VSS 105 RFU2 135 VTT 165 RFU1 195 VSS 225 RFU2 VDDSPD SPD Power 16 VID1 46 VSS 76 PS2 106 RFU2 136 VIDO 166 VSS 196 SS2 226 RFU2 VSS Ground 17 IRESET 47 VSS 77 1PS2 107 VSS 137 M_TEST 167 VSS 197 SS2 227 VSS RFU Reserved For Future Use 18 VSS 48 PN12 78 VSS 108 VDD 138 VSS 168 SN12 198 VSS 228 SCK DNU Do Not Use 19 RFU2 49 PN12 79 PS3 109 VDD 139 RFU2 169 SN12 1
9. VTX DIFFp p_R 1 800 Ss mV swing VTX DIFFp p 2 VTX D VTX D Differential peak to peak output voltage for small voltage VTX DIFFp p_S 1 520 mV swing VTX DIFFp p 2 VTX D VTX D DC common code output voltage for large voltage swing VTX CM_L 1 e 375 mV Defined as VTX CM DC avg of VTX D VTX D 2 DC common mode output voltage for small voltage swing VTX CM_S 1 135 280 mv Defined as VTX CM DC avg of VTX D VTX D 2 De emphasized differential output voltage ratio for 3 5 dB VTX DE 3 5 3 A dB de emphasis Ratio 1 2 3 De emphasized differential output voltage ratio for 6 dB de VTX DE 6 Ratio 1 2 3 E 7 dB emphasis AC peak to peak common mode output voltage for large VTX CM ACp p L 1 4 SC 90 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX D VTX D 2 AC peak to peak common mode output voltage for regular VTX CM ACp p R 1 4 SE 80 mv swing VTX CM AC Max VTX D VTX D 2 Min VTX D VTX D 2 AC peak to peak common mode output voltage for small VTX CM ACp p S 1 4 _ 70 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX D VTX D 2 Maximum single ended voltage in El condition DC AC VTX IDLE SE 5 6 2 50 mV Maximum single ended voltage in El condition DC only DON 20 mV Maximum peak to peak differential voltage in El condition VTX IDLE DIFFp p 6 40 mv Single ended voltage w r t VSS on D D VTX SE 1 7 75 750 mV Minimum TX eye width 3 2 and 4 Gb
10. quTIt A CC zoo pBQrrtt Document 06054 Revision A 1 Aug 08 Dataram Corporation O 2008 Page 10 DTM65521A DATARAM 2 GB 256Mx72 240 Pin FB DIMM DRAM AC Characteristics AC operating conditions unless otherwise noted Parameter Symbol di oo Unit Note Value Value Row Cycle Time tre 60 ns Auto Refresh Row Cycle Time trre 127 5 ns Row Active Time tras 45 70K ns Row Address to Column Address Delay trop 15 ns Row Active to row Active Delay trrD 7 5 ns Column Address to Column Address Delay teco 2 CLK Row Precharge time trp 15 ns Write Recovery Time twr 15 ns Auto Precharge Write Recovery Precharge Time toa Go FR Gel 7 di System Clock Cycle Time tck 3000 8000 ps Clock High Level Width Lou 0 48 0 52 CLK Clock Low Level Width teL 0 48 0 52 CLK DQ output access time from CK amp CK tac 0 450 0 450 ns DQS Out edge to Clock Edge skew toasck 0 400 0 400 ns DQS Out edge to Data out edge skew toasa 0 240 ns Data Out hold time from DQS Lon tup tons ns 1 Data hold skew factor tons 0 340 ns 1 Clock Half Period tur min tc tch ns 1 Input Setup Time fast slew rate tis 0 200 ns 2 3 5 6 Input Hold Time fast slew rate Du 0 275 ns 2 3 5 6 Input Pulse Width tipw 0 6 CLK 6 Write DQS High Level Width toasH 0 35 CLK Write DQS Low Level Width toast 0 35 CLK CLK to First Rising edge to DQS
11. 4 7 Maximum RX inherent timing error 3 2 and 4 Gb s TRX TJ MAX 4 8 9 0 4 UI Maximum RX inherent deterministic timing error 3 2 and 4 TRX DJ DD 4 8 9 10 SE 0 3 UI Gb s Single pulse width at zero voltage crossing TRX PW ZC 4 6 0 55 Ul Single pulse width at minimum level crossing TRX PW ML 4 6 0 2 SS Ul Ee RX input rise fall time given by 20 80 voltage TRX RISE TRX FALL 50 ps evels Common mode of the input voltage VRX CM 1 11 120 400 mV Defined as VRX CM DC avg of VRX D VRX D 1 2 AC peak to peak common mode of input voltage VRX CM VRX CM ACp p 1 E 270 mV AC Max VRX D VRX D 2 Min VRX D VRX D 2 Ratio of VRX CM ACp p to minimum VRX DIFFp p VRX CM EH Ratio 12 45 Differential return loss RLRX DIFF 9 dB Measured over 0 1 GHz to 2 4GHz Common mode return loss RLRX CM 6 dB Measured over 0 1 GHz to 2 4GHz RX termination resistance RRX 13 41 55 Q D D RX resistance difference RRX Match DC 4 RRX Match DC 2 RRX D RRX D RRX D RRX D Lane to lane PCB skew at RX LRX PCB SKEW 14 SE 6 UI Lane to Lane PCB skew at the Receiver that must be tolerated Minimum RX Drift Tolerance TRX DRIFT 15 400 ps Minimum data tracking 3dB bandwidth FTRK 16 0 2 a MHz Electrical idle entry detect time ee ES 60 ns Electrical idle exit detect time TEI EXIT DETECT as 30 ns Bit Error Ratio BER 18 Se 10 Document 06054 Revision A 1 Aug 08 Dataram Corporation 2008 Page
12. 6054 Revision A 1 Aug 08 Dataram Corporation 2008 Page 9 DTM65521A DATARAM 2 GB 256Mx72 240 Pin FB DIMM AMB Power Specification Ta O to 70 C Voltage referenced to Vss OV Parameter Symbol Test Condition y Value Unit idle Single or last FBDIMM LO state idle 0 BW primary channel 1 5V 2600 Current IDD_IDLE_O enabled secondary channel disabled CKE high command and mA address lines stable DDR2 SDRAM clock active 1 8V 700 Idle First FBDIMM LO state idle 0 BW primary and secondary 15V 3400 Current IDD_IDLE_1 channels enabled CKE high command and address lines mA stable DDR2 SDRAM clock active 18V 700 TDP BW Single or Last DIMM LO State TDP Channel 4 5 V 13000 Active IDD_TDP_0 BW 2 4GB s 667 67 READ 33 WRITE primary channel e Power enabled secondary channel disabled CKE high command and 18V 1300 de address lines stable DDR2 SDRAM clock active TDP BW First DIMM LO State TDP Channel 1 5V 3900 Active IDD TDP 1 BW 2 4GB s 667 DIMM BW 1 6GB s 667 67 READ 33 Power WRITE primary channel enabled secondary channel enabled mA CKE high command and address lines stable DDR2 SDRAM 1 8 V 1000 clock active IDD TRAINING Primary and secondary channels enabled 100 toggle on all 15V 4000 Training E channel lanes DDR2 SDRAM devices idle 0 BW CKE HIGH mA command and address lines stable DDR2 SDRAM clock active 1 8 V 0 7 SS y ya
13. 99 SS3 229 ISCK M_TEST Margin Test 20 RFU2 50 VSS 80 PS3 110 VSS 140 RFU2 170 VSS 200 SS3 230 VSS SA 2 0 Serial Address EEPROM 21 VSS 51 PNG 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD 22 PNO 52 PNG 82 PS4 112 VDD 142 SNO 172 ISN6 202 SS4 232 VDD 23 PNO 53 VSS 83 PS4 113 VDD 143 SNO 173 VSS 203 SS4 233 VDD 24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 SN7 204 VSS 234 VSS 25 PN1 55 PN7 85 VSS 115 VDD 145 SN1 175 SN7 205 VSS 235 VDD 26 PN1 56 VSS 86 RFU1 116 VDD 146 SN1 176 VSS 206 RFU1 236 VDD 27 VSS 57 PN8 87 RFU1 117 VTT 147 VSS 177 SN8 207 RFU1 237 VTT 28 PN2 58 PN8 amp 88 VSS 118 SA2 148 SN2 178 SN8 208 VSS 238 VDDSPD 29 PN2 59 VSS 89 VSS 119 SDA 149 SN2 179 VSS 209 VSS 239 SAO 30 VSS 60 PN9 90 PS9 120 SCL 150 VSS 180 SN9 210 SS9 240 SA1 NOTE M_TEST is not used Document 06054 Revision A 1 Aug 08 Dataram Corporation 2008 Page 1 DTM65521A DATARAM 2 GB 256Mx72 240 Pin FB DIMM Front view 133 35 e 5 250 3 00 0 118 30 35 1 191 E ve GE 518 67 00 I 51 00 D in 0 204 2 638 2 008 123 00 gt 4 843 Back view Side view 7 49 Max 10 295 Max w heatspreader 4 00 Min 0 157 Min 1 27 1 10 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches gt lt __a a ____ _ __ ____ _ gt
14. AM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06054 Revision A 1 Aug 08 Dataram Corporation 2008 Page 16
15. a yy tz E eee Document 06054 Revision A 1 Aug 08 Dataram Corporation O 2008 Page 2 DTM65521A HAAL 2GB 256mx72 240 Pin FB DIMM IEN o ISO o DQS9 o DQS13 o DQso o DQS4 Oo DQS0o O DQS4 O bd ao no N Sa Ka Ka YN z9 Ed Ka YN EK KA N N SQ g 8 58 g 8 88 g 8 888 g 8 S x x gt iv x DQR 7 0 O 1 0 DO 1 0 7 0 DQ 39 32 O 1 0 7 0 VO 7 0 DQS10 gt DQS14 O ke DQS1 o DQS5 o DQS1 O DQS5 O hd N N n z9 Q Q N Sa N N N z9 N N N z9 g g 28 g 8 3g g 8 838 g 8 8 38 8 a Se E DQ 15 8 O _ 1 0 7 0 VO 7 0 DQ 47 40 O 1 0 7 0 V O 7 0 Das11 o gt DQS15 O gt DQs2 o DQS6 O DQS2 O DQS6 O 1 KA N SQ no no N z9 non no z9 N 1 no SQ g 8 28g g 8 83g 88 258 g 8 S gt x x CS 13 gt x DQ 23 16 O 1 0 7 0 VO 7 0 DQ 55 48 O 1 0 7 0 VO 7 0 Das12 o DQS16 O k DQS3 O DQS7 O DQS3 O DQS7 O
16. cantly below the tracking capability of the receiver 16 This bandwidth number assumes the specified minimum data transition density Maximum jitter at 0 2MHz is 0 05UI 17 The specified time includes the time required to forward the El entry condition 18 BER per differential lane Document 06054 Revision A 1 Aug 08 Dataram Corporation 2008 Page 8 DTM65521A DATARAM 2 GB 256Mx72 240 Pin FB DIMM Advanced Memory Buffer FBD Timing Electrical Parameter Symbol MIN MAX Units El Assertion Pass Through Timing EI PROPAGATE 4 CLKs El Deassertion Pass Through Timing tEID tBitlock CLKs El Assertion Duration tEl 100 CLKs Bit Lock Interval tBITLOCK 119 Frames Frame Lock Interval tFRAMELOCK 154 Frames Advanced Memory Buffer Latency Parameters Parameter Symbol MIN MAX Units Notes CMD2DATA 0x40 Data Rate 667 tC2D_AMB 16 2 19 ns CMD2DATA 0x46 Data Rate 667 tC2D_AMB 17 7 20 5 ns Resample Delay 6 tRESAMPLE 0 9 1 4 ns 1 Resync Delay 7 8 9 tRESYNC 2 3 2 ns 2 NOTES 1 tRESAMPLE is the delay from the southbound input to the southbound output or the northbound input to the northbound output when in resample mode measured from the center of the data eye 2 tRESYNC is the delay from the southbound input to the southbound output or the northbound input to the northbound output when in resync mode measured from the center of the data eye SSS eee Document 0
17. e of SDRAM device package from top case to ambient Psi T A 7A 2 2 0 32 EN O7 A 3 20 A1 12 13 14 15 16 17 18 9 20 21 22 23 25 26 27 28 1 29 30 BECA Document 06054 Revision A 1 Aug 08 Dataram Corporation O 2008 Page 13 DTM65521A DATARAM 2 GB 256Mx72 240 Pin FB DIMM DTO Case temperature rise from ambient due to IDDO activate precharge operation minus DT2N DT2Q Case temperature rise from ambient due to IDD2N precharge standby operation DT2P Case temperature rise from ambient due to IDD2P precharge power down operation ES DT3N Case temperature rise from ambient due to IDD3N active standby operation 4 a o N y R 7 S O N al N T N o m Ol No Wa w w w o N N ojo O O N n gt in OAI O k lbuoc N N CO DT5B Case temperature rise from ambient due to IDD5B burst refresh operation DT7 Case temperature rise from ambient due to IDD7 bank interleave read mode operation DT4R Mode Bit Bits 7 1 Case temperature rise from ambient due to IDD4R page open 42 78 FBD ODT Definition DDR2 Base FB DIMM Channel Protocols Supported ECC Protocol Supported FB DIMM Channel Protocols Supported E Back to Back Access Turnaround Time ae AMB Read Access Time for DDR2 800 AMB LINKPARNXT 1 0 11 EN 82 83 84 85 i 86 1 0 Ka Thermal Resistance of AMB Package from top case to ambie
18. nent assuming zero Lane to Lane skew at the Receiver pins of the incoming PORT 16 This is a static skew A FB DIMM component is not allowed to change its lane to lane phase relationship after initialization 17 Measured from the reference clock edge to the center of the output eye This specification is met across specified voltage and temperature ranges for a single component Drift rate of change is significantly below the tracking capability of the receiver 18 BER per differential lane For a complete definition of Bit Error Ratio refer to JEDEC s Compliance Methodology section Document 06054 Revision A 1 Aug 08 Dataram Corporation 2008 Page 6 DTM65521A DATARAM Differential Receiver Input Specification 2 GB 256Mx72 240 Pin FB DIMM Parameter Symbol MIN MAX Units Differential peak to peak input voltage VRX DIFFp p_L 1 170 1300 mV VRX DIFFp p 2 VRX D VRX D Maximum single ended voltage for El condition DC AC VRX IDLE SE 2 3 4 ae 65 mV Maximum single ended voltage for El condition DC only Dee Ss 35 mV Single ended voltage w r t VSS on D D VRX SE 4 300 900 mV Single pulse peak differential input voltage VRX DIFF PULSE 4 6 85 mV Amplitude ratio between adjacent symbols VRX DIFF ADJ zm 3 1100mV lt VRX DIFFp p 1300mV RATIO HI 4 7 Amplitude ratio between adjacent symbols VRX DIFF ADJ Ee 4 VRX DIFFp p 1100mV RATIO
19. nt Psi T A SDRAM 21 C W 2A 88 E 89 2 90 J CS ve 92 E AMB Case Temperature Rise from Ambient due to AMB in LOs State Not Supported 94 97 35 36 37 38 39 0 1 79 81 82 83 84 85 87 88 91 92 93 98 AMB Junction Temperature Maximum Tjmax C 99 Category Byte E A Doo Doo AMB Personality Bytes Pre initialization IDT AMB Personality Bytes Post initialization AMB Manufacturer s JEDEC ID Code Document 06054 Revision A 1 Aug 08 Dataram Corporation 2008 Page 14 DTM65521A DATARAM 2 GB 256Mx72 240 Pin FB DIMM Module ID Module Manufacturer s JEDEC ID Code 119 Module ID Module Manufacturing Location 120 121 Module ID Module Manufacturing Date 122 125 Module ID Module Serial Number serial number Cyclical Redundancy Code CRC 128 131 Module Par Number SSCS SCS 1 Module Part Number LD 135 Module Part Number ORO 139 Module Part Number S 130 Module Part Number 145 Module Part Number OOOO SS 146 147 Module Revision Code OOO ooo o S SCS 148 149 SDRAM Manufacturers JEDEO 1D Coe o M 150 175 Manufacturer s Specific Deal O 176 255 Open for customer use o S S YL g e e LIN SR aR ga RINS Sl esd esa bea pea Document 06054 Revision A 1 Aug 08 Dataram Corporation 2008 Page 15 DTM65521A HAAL 266 256mx72 240 Pin FB DIMM DATARAM DATAR
20. s TTX Eye MIN 1 9 10 0 7 en Ul Maximum TX deterministic jitter 3 2 and 4 Gb s TTX DJ DD 1 9 10 11 on 0 2 UI Instantaneous pulse width TTX PULSE 12 0 85 UI Differential TX output rise fall time TTX RISE TTX 30 90 ps Given by 20 80 voltage levels FALL 1 Mismatch between rise and fall times TTX RF MISMATCH _ 20 ps Differential return loss RLTX DIFF 8 __ dB Measured over 0 1 GHz to 2 4GHz Common mode return loss RLTX CM 6 dB Measured over 0 1 GHz to 2 4GHz Transmitter termination resistance RTX 13 41 55 Q D D TX resistance difference RTX Match DC 4 RTX Match DC 2 RTX D RTX D RTX D RTX D Bounds are applied separately to high and low output voltage states Lane to lane skew at TX LTX SKEW 1 14 16 100 3UI ps Lane to lane skew at TX LTX SKEW 2 15 16 100 2UI ps e TTX DRIFT 240 s Maximum TX Drift resync mode RESYNC 17 p e TTX DRIFT 120 s Maximum TX Drift resample mode only RESAMPLE 17 p Bit Error Ratio BER 18 10 Document 06054 Revision A 1 Aug 08 Dataram Corporation 2008 Page 5 DTM65521A HAAL 2GB 256Mx72 240 Pin FB DIMM NOTES FOR TRANSMITTER OUTPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliance test load Common mode measurements to be performed using a 101010 pattern 2 This is the ratio of the VTX DIFFp p of the second and following bits after a transition divided by the VTx DIFFp p of the first bit after a transition
21. ssive inter symbol interference in the Rx Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols see RX Maximum Adjacent Symbol Amplitude 8 This number does not include the effects of SSC or reference clock jitter 9 This number includes setup and hold of the RX sampling flop 10 Defined as the dual dirac deterministic timing error as described in Section 4 2 2 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 11 Allows for 15mV DC offset between transmit and receive devices 12 The received differential signal satisfies both this ratio as well as the absolute maximum AC peak to peak common mode specification For example if VRx DIFFp p is 200mV the maximum AC peak to peak common mode is the lesser of 200 mV 0 45 90mV and VRx CM ACp p 13 The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 51 with regard to the average of the values measured at 100mV and at 400mV for that pin 14 This number represents the lane to lane skew between TX and RX pins and does not include the transmitter output skew from the component driving the signal to the receiver This is one component of the end to end channel skew in the AMB specification 15 Measured from the reference clock edge to the center of the input eye This specification is met across specified voltage and temperature ranges Drift rate of change is signifi
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