Dataram DTM64332A memory module
Contents
1. FTB Divisor 2 Bit 7 Bit 4 Fine Timebase FTB Dividend Medium Timebase MTB Dividend Medium Timebase MTB Divisor SDRAM Minimum Cycle Time tCKmin CAS Latencies Supported Least Significant Byte 4 Bit 1 5 Bit 2 CL 6 CL 7 Bit 4 CL 8 Bit5 CL 9 Bit 6 CL 10 Bit 7 CL 11 Module Memory Bus Width Bit 2 Primary bus width in bits Bit 4 Bit 3 Bus width extension in bits Bit 7 Bit 5 Reserved 1 0 125ns UNUSED 13 14 Document 06582 Revision A 21 May 10 Dataram Corporation 2010 Hex 0x92 0x10 OxOB 0x01 0x02 0 11 0 02 0 09 OxOB 0x52 0x01 0x08 OxOC 0x00 Ox3C Page 8 DIM64332A MM 2GB 240 2Rx8 Registered ECC LV DDR3 DIMM 15 CAS Latencies Supported Most Significant Byte 0x00 CL 12 CL 13 Bit 2 CL 714 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 7 Reserved Minimum CAS Latency Time tAAmin 13 125ns 0x69 Minimum Write Recovery Time tWRmin 0x78 Minimum RAS to CAS Delay Time tRCDmin 13 125ns 0x69 Minimum Row Active to Row Active Delay Time tRRDmin 0x30 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 1 Upper Nibbles for tRAS and tRC 0x11 Bit 3 tRAS Most Significant Nibble 1 B2. LCLK 1 0 RCLK 1 0 ul WW _O nie a Ga bu ILCLK 1 0 ov RCLK 1 0 c 7 0 O O CBR 7 0 PA BAIR A 15 0 A 15 0 R DQS 8 0 Q NN O DQSR 8 0 IRAS RASR DQS 8 0 O O DQSR 8 0 ICAS ICASR IWE WER 0 8 0 O WN O DMR 8 0 CKEO A CKEOR ee CKE1 um CKE1R DECOUPLING ODT1 Y ODT1R VDD All Devices PAR_IN ERR_OUT VREF DQ All SDRAMs GLOBAL SDRAM CONNECTS CKO L R CLK 1 0 g Vss All Devices 120 All 39 OHMS OHMS REF_CA All SDRAMs BA 2 0 R CKO L R CLK 1 0 V TT F A SDRAMs A 15 0 R RASR SDRAMS CASR oe MM EVENT pee e TEMPERATURE MONITOR ZQ SCL SERIAL PD CKE 1 0 R S VN ODT 1 0 R RS 1 0 VTT Vss Document 06582 Revision A 21 May 10 Dataram Corporation 2010 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM SA1 SA2 SAO Page 3 DATARAM DI M64332A AM 2GB 240 2Rx8 Registered ECC LV DDR3 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability Ambient Temperature Operating TA Oo 70 C DRAM Case Temperature Operating Tos 0 95 C Voltage on Vpp relative to Vss V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Operati
3. 107 108 109 110 144 112 113 114 115 116 117 118 119 120 Pin Configuration 0041 Vss DQS5 DQS5 Vss DQ42 DQ43 Vss 0048 0049 Vss DQS6 DQS6 Vss DQ50 DQ51 Vss DQ56 DQ57 Vss DQS7 DQS7 Vss DQ58 DQ59 Vss SAO SCL SA2 Vit Back Side 124 Vee 151 Vss 181 A1 122DQ4 152 182 Vas 123 DQ5 153 TDQS12 183 Vpp 124 Vcc 154 Vss 184 CKO 125DMO 155 DQ30 185 CKO 126 TDQS9 156 DQ31 186 Vpp 127 Ves 157 Vss 187 Event 128DQ6 158 4 188 AO 129007 159 CB5 189 130 Vss 160 Vss 190 BA1 1310012 161 DM8 191 Vos 1320013 162 TTDQS17 192 RAS 133 Vss 163 Vss 193 S0 134 DM1 164 CB6 194 Vpp 135 TDQS10 165 CB7 195 ODTO 136 Vss 166 Vss 196 A13 137DQ14 167 NC TEST 197 Vpp 138DQ15 168 198 S3 NC 139 Vss 169 CKE1 199 Vss 140DQ20 170 Voo 200 DQ36 141DQ21 171 A15 201 DQ37 142 Ves 172 A14 202 Ves 143DM2 173 Voo 203 DM4 144 ITDQS11 174 A12 BC 204 TQDS13 145 Vss 175 A9 205 Vss 1460022 176 Vpp 206 DQ38 147 DQ23 177 A8 207 DQ39 148 Vss 178 208 Vss 149 2028 179 209 0044 1500029 180 210 0045 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Identification DTM64332A 256Mx72 2GB 2Rx8 PC3L 10600R 9 10 BO Performance range Clock Module Speed CL trep trp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3
4. 21 May 10 Dataram Corporation 2010 Page 1 DATAPRAM DIM64332A El 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM Front view 133 35 5 250 A 9 50 0 374 30 00 1 181 17 30 0 681 l y y 5 00 A 0 197 ed 5 175 du phu 47 00 71 00 gt 0 204 1 850 2 795 123 00 e 4 843 Back view Side view 4 00Max 0 157 Max 4 00 Min 0 157 Min 1 27 10 J 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches see 2 Document 06582 Revision 21 May 10 Dataram Corporation 2010 Dy9DATARAM DIM64332A Optimizing Value and Performance IRS1O Lace EE CREME pn DQSRO IDQSR4 O e DMROO ann DMR4 Q lI DQR 7 0 O44 1 0 7 0 RANK 0 0 RANK 1 DQR 39 32 0 7 0 RANK 0 0 7 0 RANK 1 DQSR1O m ullum DQSR5 ml DQSR1O DQSR5O DMR1O DMR5O TDQSR100 TDQSR140 DQR 15 8 DQRI47 40 DQSR20 DQSR6 DQSR2 O DQSR6 DMR2O DMR6O TDQSR110 TDQSR15O DQR 23 16 DQR 55 48 DQSR3 DQSR7 DQSR3 DQSR7 DMR7O TDQSR120 TDQSR160 DQR 81 24 DQR 63 56 DQSR8O DQSR8 DMR8O TDQSR17 CBR 7 0 TO SDRAMS VDD VDD All All 39 OHMS 100 nF All 39 OHMS 100 nF 22 OHMS mE 15 OHMS
5. 6400 6 6 6 Description DTM64332A is a registered 256Mx72 memory module which conforms to JEDEC s DDR3L PC3L 10600 standard The assembly is Dual Rank Each Rank is comprised of nine 128Mx8 DDR3 Samsung SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Pin Description Function Vss CB 7 0 Data Check Bits DM5 DQ 63 0 Data Bits TDQS14 DQS 8 0 DQS 8 0 Differential Data Strobes Vss DM 8 0 Data Mask DQ46 TDQS 17 9 Termination Data Strobes DQ47 CK 1 0 CK 1 0 Differential Clock Inputs Vss CKE 1 0 Clock Enables DQ52 ICAS Column Address Strobe 0053 RAS Row Address Strobe Vss S 3 0 Chip Selects DM6 AVE Write Enable TDQS15 A 15 0 Address Inputs Vss BA 2 0 Bank Addresses DQ54 ODT 1 0 On Die Termination Inputs DQ55 SA 2 0 SPD Address Vss SCL SPD Clock Input DQ60 SDA SPD Data Input Output DQ61 Vss Ground Vss Power DM7 Vppspp SPD EEPROM Power TDQS16 VREFDQ Reference Voltage for DQ Vss VREFCA Reference Voltage for CA DQ62 Vit Termination Voltage DQ63 Event Temperature Sensing Vss NC No Connection VppbsPp SA1 SDA Vss Vit Document 06582 Revision A
6. ID PATARA EN Optimizing Value and Performance Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage VDD VDDQ 1 35V 1 283V to 1 45V Backward compatible to VDD VDDQ 1 5V 0 075V On board 12 temperature sensor with integrated serial presence detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec DIM64332A 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 and 9 a ior m DAI Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully ROHS Compliant Front Side VREFDOQ DQSO DQSO Vss DQ2 10 DQ3 11 Vas 12 DQ8 13 DQ9 14 Vas 15 DQS1 16 DQS1 12 Vs 18 DQ10 190011 20 Vss 210016 220017 23 Vss 24 10092 25 0082 26 Vss 27 0018 280019 29 Ves 30 0024 OMNOaARWD lt Nn n 31 DQ25 53 ErR_O UT 54 Vpp 55 A11 56 7 57 58 A5 59 A4 60 Vpp i Not used 61 62 63 64 65 66 67 68 69 70 71 72 79 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 VREFCA PAR 1 VDD A10 AP ICAS 151 ODT1 Vop 152 NC Vss DQ32 DQ33 Vss DQS4 DQS4 Vss DQ34 DQ35 Vss DQ40 91 92 93 94 95 96 98 99 100 101 102 103 104 105 106
7. it 7 Bit 4 tRC Most Significant Nibble 1 22 Minimum Active to Precharge Delay Time tRASmin Least 36 0ns 0x20 oignificant Byte 3 Minimum Active to Active Refresh Delay Time tRCmin Least 49 125ns 0x89 oignificant Byte 4 Minimum Refresh Recovery Delay Time tRFCmin Least 110 0ns 0x70 Significant Byte 5 Minimum Refresh Recovery Delay Time tRFCmin Most 110 0ns 0x03 Significant Byte tWTRmin tRTPmin Upper Nibble for tFAW 0x00 Bit 3 Bit 0 tFAW Most Significant Nibble Bit 7 Bit 4 Reserved 29 Minimum Four Activate Window Delay Time tFAWmin Least OxFO oignificant Byte 30 SDRAM Optional Features 0x83 Bit 0 RZQ 6 X Bit 1 RZQ 7 X Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support 31 SDRAM Drivers Supported 0x05 Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout NO NO NO NO NO NO NO Co N O Reserved Reserved Reserved Partial Array Self Refresh PASR 32 Module Thermal Sensor 0x80 Bit 6 Bit 0 Thermal Sensor Accuracy 0 Document 06582 Revision 21 May 10 Dataram Corporation 2010 Page 9 DATARAM DI M64332A AM 2GB 240 2Rx8 Registered ECC LV DDR3 DIMM Bit 7 Thermal Sensor With TS 33 SDRAM Device Type 0 00 Bit 6 N
8. n the rest in IDD2P slow exit All module ranks in this operation Document 06582 Revision A 21 May 10 Dataram Corporation 2010 Page 6 DITM64332A EE 2GB 240 2Rx8 Registered ECC LV DDR3 DIMM AC Operating Conditions Internal read command to first data ns CAS to CAS Command Delay 3 enn Clock High Level Width tox Clock Low Level Width tox Data Input Hold Time after DQS Strobe tu 65 o ps DQ Input Pulse Width tw 400 ps DQS Output Access Time from Clock ps Write DQS High Level Width tek avo Write DQS Low Level Width tox avg DQS Out Edge to Data Out Edge Skew was T m5 ps Data Input Setup Time Before DQS Strobe ts 30 DQS Falling Edge from Clock Hold Time ton 02 DGS Falling Edge to Clock Setup Time s o tck avg Address and Command Hold Time after Clock Fx y o ps Address and Command Setup Time before Clock tis B e ps Load Mode Command Cycle Time tw 04 e Active to Precharge Time ns Active to Active Auto Refresh Time amp 49125 n Average Periodic Refresh Interval 0 C lt Tcase lt 85 C phon 0 7 78 Us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C ter 0 07 39 Us Auto Refresh Row Cycle Time d wc 10 ns Row Precharge Time Ld ns Read DQS Preamble Time tere 09 tck avg Read DQS Postamble Time tck avg Row Active to Row Active Delay tko Max 4nCK 6ns
9. ns Internal Read to Precharge Command Delay tke Max 4nCK 7 5ns ns Write DQS Preamble Setup Time Write DQS Postamble Time NA REC Write Recovery Time p wa 15 n Internal Write to Read Command Delay lwTR 4 7 5ns ns Notes 1 maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06582 Revision A 21 May 10 Dataram Corporation 2010 Page 7 AM 2GB 240 2Rx8 Registered ECC LV DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Value Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 SPD Revision Key Byte DRAM Device Type Key Byte Module Type DDR3 SDRAM Bit 3 Module Type Bit 7 Bit 4 Reserved SDRAM Density and Banks Bit 3 Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 5 SDRAM Addressing Bit 2 Column Address Bits 10 Bit 5 Bit 3 Row Address Bits 14 Bit 7 6 Reserved Module Nominal Voltage VDD T Module Organization operable Bit 2 Bit 0 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved Fine Timebase FTB Dividend Divisor Bit 3 Fine Timebase
10. on Standard Device Description 0 Bit 7 SDRAM Device Std Mono 59 Module Nominal Height OxOF Bit 4 Module Nominal Height max in mm 29 lt h lt 30 Bit 7 Reserved 0 61 Module Maximum Thickness 0 11 Bit 3 Front in mm baseline thickness 1 mm 1 lt th lt 2 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 62 Reference Raw Card Used 0x01 Bit 4 Reference Raw Card Bit 6 Bit 5 Reference Raw Card Revision Bit 7 Reserved 63 Registered DIMM Module Attributes 0x05 Bit 1 of Registers used on RDIMM 1 Register Bit 3 Bit 2 of Rows of DRAMs on 1 Row Bit 7 Bit 4 Reserved 64 RDIMM Thermal Heat Spreader Solution 0x00 Bit 6 Heat Spreader Thermal Characteristics 0 Bit 7 Heat Spreader Solution No HS 65 Register Manufacturer ID Code Least Significant Byte UNUSED 0x00 Optional Register Manufacturer ID Code Most Significant Byte UNUSED 0x00 Optional Register Revision Number Optional OxFF Register Type 0x00 Bit 2 0 Support Device SSTE32882 Bit 7 3 Reserved 0 SSTE32882 RC1 MS Nibble RCO LS Nibble UNUSED 0x00 TO SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength 0x50 Command Address Bit 1 RC2 DA3 4 Value RESERVED Bit 3 Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DA4 3 value Command Address A Outputs Moderate Bit 7 Bi
11. on Typical Note Voltage Power Supply Voltage 1 35V 1 283 1 4500 I O Reference Voltage 1 35V VREFDQ 0 49 Vpp 0 50 Vpp 0 51 Vpp 15 15 I O Reference Voltage 135 135 VREFCA 15V 0 49 VDD 0 50 Vbpp 0 51 Vbpp Notes 1 For Reference Vpp 2 15 mV The value of VREF is expected to equal one half VDD and to track variations in the VDD DC level Peak to peak noise on VREF may not exceed 1 of its DC value For Reference VREF VDD 2 15 mV DC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to V 0 V Voltage Lm ese e 1 5V Vss Vner 0 1 AC Input Logic Levels Single Ended 0 to 70 C Voltage referenced to Vss 0 V Voltage veros 1 5V Vner 0 175 Document 06582 Revision A 21 May 10 Dataram Corporation 2010 Page 4 DTM64332A SME 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM Differential Input Logic Levels 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage relative to VDD 2 Vix 0 150 0 150 V Capacitance T4 25 C f 100 MHz 00163 0 CBI7 7 0058 0 DQS 8 0 oF Input Output Capacitance DM 8 0 TDQS 17 9 DC Characteristics T4 0 to 70 C Voltage referenced to Vss Input Leakage Current Le Any in
12. put 0 V VIN VDD lot 10 10 UA 2 3 Output Leakage Current OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06582 Revision A 21 May 10 Dataram Corporation 2010 Page 5 DTM64332A SME 2GB 240 Pin 2Rx8 Registered ECC LV DDR3 DIMM lbo Specifications and Conditions T4 0 to 70 C Voltage referenced to Vs 0 V PARAMETER Symbol Test Condition MS eer Operating One l Bank Active Operating current One bank ACTIVATE to PRECHARGE 1340 1385 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 1430 1475 mA Precharge Current Precharge Power Precharge power down current Slow exit Precharge Power Iap2P Precharge power down current Fast exit 880 970 mA Down Current Precharge Quiet Precharge quiet standby current Precharge Standby Precharge standby current Active Power Down Active power down current 1880 4660 mA Current Active Standby Active standby current Operating Burst Burst write operating current Operating Burst i Burst read operating current Burst Refresh Refresh current Self Refresh Self refresh temperature current MAX Tc 85 C 780 mA Current Operating Bank Interleave Read Ipp7 Current All bank interleaved read current 2420 2510 mA One module rank in this operatio
13. t 6 RC3 DBAO 1 value Command Address B Outputs Moderate 71 SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and 0 00 Clock Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Light Bit Bit 2 RCA DBAO 1 Control Signals B Outputs Light Bit 5 Bit 4 RC5 DAA 3 value Y1 Y1 and Y3 Y3 Clock Light Outputs Bit 7 Bit 6 RC5 DBAO 1 value YO YO and Y2 Y2 Clock Light Outputs SSTE32882 RC7 MS Nibble RC6 LS Nibble UNUSED 0x00 SSTE32882 RC9 MS Nibble RC8 LS Nibble UNUSED 0x00 SSTE32882 RC11 MS Nibble RC10 LS Nibble UNUSED 0x00 SSTE32882 RC13 MS Nibble RC12 LS Nibble UNUSED 0x00 Document 06582 Revision A 21 May 10 Dataram Corporation 2010 Page 10 MM 2GB 240 2Rx8 Registered ECC LV DDR3 DIMM SSTE32882 RC15 MS Nibble RC14 LS Nibble UNUSED 0x00 77 Module Specific Section UNUSED 0x00 112 UNUSED 0x00 114 Module Specific Section UNUSED 0x00 116 0x01 0x9 UNUSED 0x00 121 125 CRC OxE4 CRC 0x44 131 D 0x44 A ox T 0x54 0x4 R 0x52 137 A 0x4 M 0x4D 139 0x20 6 0x36 141 4 0x34 3 0x33 143 3 0x33 2 0x32 0x20 147 UNUSED 0x00 149 UNUSED 0x00 150 Manufacturer s Specific Data UNUSED 0 00 175 Open for customer use UNUSED 0x00 255 Document 06582 Revision A 21 May 10 Dataram Corporation 2010 Page 11 DTM64332A Em Optimizing Value and Performance 2GB 240 Pin 2Rx8 Regis
14. tered ECC LV DDR3 DIMM NP DATARAM ned ptimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06582 Revision A 21 May 10 Dataram Corporation 2010 Page 12
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