Dataram DTM64331A memory module
Contents
1. 76 SSTE32882 RC15 MS Nibble RC14 LS Nibble 77 112 Module Specific Section 113 Module Specific Section 114 116 Module Specific Section 117 Module Manufacturer ID Code Least Significant Byte POO 118 Module Manufacturer ID Code Most Significant Byte PSL x91 119 Module Manufacturing Location 120 121 Module Manufacturing Date 20 122 125 Module Serial Number 0x20 126 Cyclical Redundancy Code CRC 127 Cyclical Redundancy Code CRC 128 131 Module Part Number 0x20 132 Module Part Number D 0x44 133 Module Part Number 134 Module Part Number 135 Module Part Number 136 Module Part Number 137 Module Part Number 138 Module Part Number 139 Module Part Number 0x20 140 Module Part Number 6 0x36 141 Module Part Number 142 Module Part Number 3 143 Module Part Number 144 Module Part Number 145 Module Part Number 20 146 147 Module Revision Code To 148 DRAM Manufacturer ID Code Least Significant Byte 149 DRAM Manufacturer ID Code Most Significant Byte 150 175 Manufacturer s Specific Data 176 255 Open for customer use ee NNI Document 06581 Revision A 12 May 10 Dataram Corporation 2010 Page 11 yee DTM64331A 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM 77 8 BH Optimizing Value and Performance PYPDATARAM Meee BH Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 7992. O DOQSR 8 0 DQS 8 0 O O DQSR 8 0 DM 8 0 O O DMRI 8 0 TDQS 17 9 O VW O TDQSR 17 9 GLOBAL SDRAM CONNECTS All 39 OHMS BA 2 0 R A 15 0 R IRASR ICASR IWER VTT All 39 OHMS CKEOR ODTOR RSO VTT TO SDRAMS All 22 OHMS ISO W IRSO BA 2 0 AA I BA Z O R A 15 0 I A T5 0 R IRAS VW IRASR ICAS VW ICASR ME w 4 WER CKE0 w A CKEOR s opto w D ODTOR a PAR IN vww ERR OUT CKO L R CLK 1 0 120 OHMS ICKO I L R CLK 1 0 RESET reel SDRAMS All 240 OHMS ZQ SO Vss 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM DQSR4 O DQSR4 O DMR4O TDQSR13 0 2 z o O e DQR 39 32 O VO 7 0 RANK 0 DQSR5 O DQSR5 O DMR5O TDQSR140 DQR 47 40 O DQSR6 O DQSR6 O DMR6 O TDQSR15O DQR 55 48 O DQSR7 O DQSR7 O DMR7 O TDQSR16O DM 2 z TDQS TDQS ICS DQS DQS DQR 63 56 O 0 7 0 VDD All 39 OHMS 100 nF RCLKO E m RCLKO VDD All 39 OHMS 100 nF LCLKO MEE LCLKO DECOUPLING VDDSPD 4 Serial PD VDD All Devices VREF DQ All SDRAMs Vss All Devices VREF CA All SDRAMs VTT F All SDRAMs C EVENT TEMPERATURE MONITOR SDA Scr SERIAL PD SAO SA1 SA2 Document 06581 Revision A 12 May 10 Dataram Corporation 2010 Page 3 DTM64331A PDATARAM 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM Optimizing
3. Value and Performance Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsroRAGE 55 100 C Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TcasE 0 95 C Voltage on Vpp relative to Vss Vbp 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Operation Minimum Typical Maximum Unit Note Voltage Power Supply Voltage T 1 35V 1 283 1 35 1 4500 pp 1 5V 1 425 1 5 1 575 I O Reference Voltage 1 35V VREFDQ 0 49 Vpp 0 50 Vpp 0 51 Voo V 1 1 5V I O Reference Voltage 1 35V VREFCA 1 5V 0 49 Vpp 0 50 Vpp 0 51 Vpp V 1 Notes 1 For Reference Vpp 2 15 mV The value of VREF is expected to equal one half VDD and to track variations in the VDD DC level Peak to peak noise on VREF may not exceed 1 of its DC value For Reference VREF VDD 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Operation Minimum Maximum Unit Voltage Logical High Logic 1 Vin oc 1 35V Veer 0 09 Vop V 1 5V Vrer 0 1 Vpp Logical Low Logic 0 Vi
4. 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06581 Revision A 12 May 10 Dataram Corporation 2010 Page 12
5. CAS 104Vss 134 DM1 164 CB6 194 Vpp 224 DQ54 ODT 1 0 On Die Termination Inputs 15 DQS1 45 CB2 75 Vpp 105 DQ50 135 TDQS10 165 CB7 195 ODTO 225 DQ55 SA 2 0 SPD Address 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss SCL SPD Clock Input 17 Vss 47 Vss 77 opT1 107 Vss 137DQ14 167 NC TEST 197 Vbo 227 DQ60 SDA SPD Data Input Output 18 DQ10 48 Vr 78 Vpp 108 DQ56 f138 DQ15 168 RESET 198 S3 NC 228 DQ61 Vss Ground 19DQ11 49 Vr 79 82 NC 109 DQ57 139 Vss 169 CKE1 199 Vss 229 Vss Voo Power 20 Vss 50 CKEO 80 Vss 110Vss 140DQ20 170 Vpop 200 DQ36 230 DM7 Vopspp SPD EEPROM Power 21DQ16 51Vpp 81 DQ32 111 DQS7 141 DQ21 171 A15 201 DQ37 231 TDQS16 Vrerpa Reference Voltage for DQ 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172A14 202 Vss 232 Vss VREFCA Reference Voltage for CA 23 Vss 53 ErR_ Our 83 Vss 113Vss 143DM2 173 Voo 203 DM4 233 DQ62 Vor Termination Voltage 24 DQS2 54 Vpp 84 DQS4 114 DQ58 144 TDQS11 174 A12 BC 204 TQDS13 234 DQ63 Event Temperature Sensing 25 DQS2 55A11 85 DQS4 115 DQ59 145 Vss 175 A9 205 Vss 235 Vss NC No Connection 26 Vss 56 A7 86 Vss 116Vss 146DQ22 176 Vpop 206 DQ38 236 Vppspp 27 DQ18 57 Vbo 87 DQ34 117 SA0 147DQ23 177 A8 207 DQ39 237 SA1 28 DQ19 58 A5 88 DQ35 118 SCL 148 Vss 178 A6 208 Vss 238 SDA 29 Vss 59 A4 89 Vss 119SA2 149DQ28 179Vpp 209 DQ44 239 Vss 30 DQ24 60 Vpp 90 DQ40 120V1 150DQ29 180 A3 210 DQ45 240 Vit Not used Document 06581 Revision A 12 May 10 Dataram Corp
6. N 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM 15 CAS Latencies Supported Most Significant Byte 0x00 Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 214 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 16 Minimum CAS Latency Time tAAmin 0x69 17 Minimum Write Recovery Time tWRmin 0x78 18 Minimum RAS to CAS Delay Time tRCDmin 19 Minimum Row Active to Row Active Delay Time tRRDmin 0x30 20 Minimum Row Precharge Delay Time tRPmin 0x69 21 Upper Nibbles for tRAS and tRC 0x11 Bit 3 Bit 0 tRAS Most Significant Nibble 1 Bit 7 Bit 4 tRC Most Significant Nibble 1 22 Minimum Active to Precharge Delay Time tRASmin Least Significant Byte 23 Minimum Active to Active Refresh Delay Time tRCmin Least 0x89 Significant Byte 24 Minimum Refresh Recovery Delay Time tRFCmin Least 0x70 Significant Byte 25 Minimum Refresh Recovery Delay Time tRFCmin Most 0x03 Significant Byte 26 Minimum Internal Write to Read Command Delay Time Ox3C tWTRmin 27 Minimum Internal Read to Precharge Command Delay Time Ox3C tRTPmin 28 Upper Nibble for tFAW 0x00 Bit 3 Bit 0 tFAW Most Significant Nibble 0 Bit 7 Bit 4 Reserved 0 29 Minimum Four Activate Window Delay Time tFAWmin Least Significant Byte 30 SDRAM Optional Features 0x83 Bit 0 RZQ 6 X Bit 1 RZQ 7 X Bit 6 Bit 2 R
7. PD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 Key Byte DRAM Device Type DDR3 SDRAM Key Byte Module Type 0x01 Bit 3 Bit 0 Module Type RDIMM Bit 7 Bit 4 Reserved 4 SDRAM Density and Banks 0x02 Bit 3 Bit 0 Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved 0 5 SDRAM Addressing 0x11 Bit 2 Bit 0 Column Address Bits 10 Bit 5 Bit 3 Row Address Bits 14 Bit 7 6 Reserved 0 6 Module Nominal Voltage VDD 1 35 V operable 7 Module Organization 0x01 Bit 2 Bit 0 SDRAM Device Width 8 Bits Bit 5 Bit 3 Number of Ranks 1 Rank Bit 7 6 Reserved 0 8 Module Memory Bus Width 0x0B Bit 2 Bit 0 Primary bus width in bits 64 Bits Bit 4 Bit 3 Bus width extension in bits 8 Bits Bit 7 Bit 5 Reserved 0 9 Fine Timebase FTB Dividend Divisor 0x52 Bit 3 Bit 0 Fine Timebase FTB Divisor 2 Bit 7 Bit 4 Fine Timebase FTB Dividend 5 10 Medium Timebase MTB Dividend 1 MTB 0x01 0 125ns 11 Medium Timebase MTB Divisor 8 MTB 0x08 0 125ns 12 SDRAM Minimum Cycle Time tCKmin 13 Reserved UNUSED 14 ICAS Latencies Supported Least Significant Byte O0x3C Bit 0 CL 24 Bit 1 CL 5 Bit 2 CL 6 X Bit 3 CL 7 X Bit 4 CL 8 X Bit 5 CL 9 X Bit 6 CL 10 Bit 7 CL 11 Document 06581 Revision A 12 May 10 Dataram Corporation 2010 D DATARAM DTM64331A M
8. ating temperature of 95C Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully RoHS Compliant Pin Configuration Pin Description Back Side Function 121 Vss 151 Vss 181 A1 211 Vss CB 7 0 Data Check Bits Front Side Verba 31 DQ25 61A2 91 DQ41 1 2 Vss 32 Vss 62 Vpp 92 Vss 122DQ4 152 DM3 182 Vpp 212 DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 DQS95 123 DQ5 153 TDQS12 3183 Vpp 213 TDQS14 DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34DQS3 64 CK1 94 DQS5 124 Vss 154 Vss 184 CKO 214 Vss DM 8 0 Data Mask 5 Vss 35 Vss 65 Vpp 95 Vss 125 DMO 155 DQ30 185 CKO 215 DQ46 TDQS 17 9 Termination Data Strobes 6 DQSO 36 DQ26 66 Vpp 96 DQ42 126 TDQS9 156 DQ31 186 Vpp 216 DQ47 CK 1 0 CK 1 0 Differential Clock Inputs 7 DQSO 37 DQ27 67 VgercA 97 DQ43 127 Vss 157 Vss 187 Event 217 Vss CKE 1 0 Clock Enables 8 Vss 38 Vss 68 Pan Iu 98 Vss 128DQ6 158 CB4 188 A0 218 DQ52 ICAS Column Address Strobe 9 DQ2 39CBO 69 VDD 99 DQ48 129 DQ7 159 CB5 189 Vpp 219 DQ53 IRAS Row Address Strobe 10DQ3 40 CB1 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss S 3 0 Chip Selects 11 Vss 41 Vss 71 BAO 101Vsgs 131DQ12 161 DM8 amp 191 Voo 221 DM6 WE Write Enable 12DQ8 42 DQS8 72 Vpp 102 DQS0 132DQ13 162 TDQS17 192 RAS 222 TQDS15 A 15 0 Address Inputs 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 S0 223 Vss BA 2 0 Bank Addresses 14 Vss 44 Vss 74
9. eserved Bit 7 DLL Off Mode Support 31 SDRAM Drivers Supported 0x05 Extended Temperature Range X Extended Temperature Refresh Rate Auto Self Refresh ASR X On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Partial Array Self Refresh PASR 32 Module Thermal Sensor 0x80 Bit 6 Bit 0 Thermal Sensor Accuracy 0 Document 06581 Revision A 12 May 10 Dataram Corporation 2010 Page 9 D DATARAM DTM64331A NNNM 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM Bit 7 Thermal Sensor With TS 33 SDRAM Device Type 0x00 Bit 6 Bit 0 Non Standard Device Description 0 Bit 7 SDRAM Device Type Std Mono 34 59 Reserved UNUSED 60 Module Nominal Height OxOF Bit 4 Bit 0 Module Nominal Height max in mm 29 h 30 Bit 7 Bits Reserved 0 61 Module Maximum Thickness 0x11 Bit 3 Bit 0 Front in mm baseline thickness 1 mm 1 lt th lt 2 Bit 7 Bit 4 Back in mm baseline thickness 1 mm 1 lt th lt 2 62 Reference Raw Card Used 0x00 Bit 4 Bit 0 Reference Raw Card RICA Bit 6 Bit 5 Reference Raw Card Revision Rev 0 Bit 7 Reserved 0 63 Registered DIMM Module Attributes 0x05 Bit 1 Bit 0 of Registers used on RDIMM 1 Register Bit 3 Bit 2 of Rows of DRAMs on RDIMM 1 Row Bit 7 Bit 4 Reserved 0 64 RDIMM Thermal Heat Spreader Solution 0x00 Bit 6 Bit 0 Heat Spreader The
10. ess and Command Hold Time after Clock tin 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time tMRD 4 tck DQ to DQS Hold taH 0 38 tck avg Active to Precharge Time tras 36 O tREFI ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trep 13 125 ns Average Periodic Refresh Interval 0 C lt Tease lt 85 C tREFI 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C tREFI 3 9 us Auto Refresh Row Cycle Time treo 110 ns Row Precharge Time tre 13 125 ns Read DQS Preamble Time tRPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay trtp Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twPsT 0 3 ck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min The maximum postamble is bound by tHZDQS max Document 06581 Revision A 12 May 10 Dataram Corporation 2010 Page 7 D DATARAM DTM64331A eee 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte Function Hex 0 Number of Bytes Used Number of Bytes in SPD Device CRC Coverage 0x92 Bit 3 Bit 0 S
11. nt Write Current Ipp4W 1575 1665 mA Operating Burst Burst read operating current Read Current Ipp4R 1520 1610 mA Burst Refresh Refresh current Current Ipp5 1660 1705 mA Self Refresh Ibo Self refresh temperature current MAX Tc 85 C 690 690 mA Current Operating Bank Interleave Read Ipo7 All bank interleaved read current 2195 2285 mA Current Document 06581 Revision A 12 May 10 Dataram Corporation 2010 Page 6 JQDATARAM Optimizing Value and Performance AC Operating Conditions DTM64331A 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tccp 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width cL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe tou 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock tpasck 255 255 ps Write DQS High Level Width toasH 0 45 0 55 tcxiavg Write DQS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tek avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tup minimum of tcu or tci ns Addr
12. oc 1 35V Vss Vrer 0 09 V 1 5V Vss Vrer 0 1 AC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Operation Minimum Maximum Unit Voltage Logical High Logic 1 VitAC 1 35V Veer 0 160 g V 1 5V Vrer 0 175 Logical Low Logic 0 ViL AC 1 35V 2 Vner 0 160 V 1 5V E Veer 0 175 Bi HEP a s H JnU Lee Document 06581 Revision A 12 May 10 Dataram Corporation 2010 Page 4 JoDATARAM Optimizing Value and Performance DTM64331A 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High Vin piFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low ViL DiFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage E relative to VDD 2 Vix 9 150 29090 M Capacitance T4 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Cck 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control SO CKEO ODTO C 1 5 2 5 DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DM 8 0 TDQS 17 9 Cio 1 5 2 5 pF DC Cha
13. oration 2010 Page 1 J2 DATARAM DTM64331A NNNM 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM Front view 133 35 5 250 9 50 0 374 30 00 1 181 k 17 30 0 681 O 5 00 0 197 en 5 175 47 00 71 00 0 204 1 850 2 795 123 00 4 843 Back view Side view 3 94 Max 0 155 Max Wi 4 00 Min 0 157 Min O NAMNNNNNNNMNNNNNNANNNNNNMNNNNNNNNNNNNNNNNNNNNN NNNMNNN NNNMNNN O i 1 27 10 RT 0 0500 40 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches U IPRC PNE CRUEL c M Y Y a B esM H9 Page 2 Document 06581 Revision A 12 May 10 Dataram Corporation 2010 Optimizing Value and Performance IRS0 O DQSROO DQSRO O DMROO TDQSR9O 2 F7 z e a RANK 0 DQR 7 0 O O 7 0 DQSR1O DQSR1O DMR1O TDQSR100 DQR 15 8 O TDQSR110 DQR 23 16 O DQSR3 IDQSR3 DMR3 TDQSRI20 7 DMN SON NN zo GU OO a a aa EF S DQR 31 24 V O 7 0 DQSR8 O IDQSR8O DMR8O TDQSR170 CBR 7 0 O All 15 OHMS DQ 63 0 O O DQR 63 0 CB 7 0 O VW O CBR 7 0 DQS 8 0 O
14. racteristics T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 pA 1 2 Any input 0 V VIN VDD Output Leakage Current lo 10 10 pA 2 3 OV VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled a a eeee 7ee Document 06581 Revision A 12 May 10 Dataram Corporation 2010 Page 5 MN 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM lbo Specifications and Conditions T4 0 to 70 C Voltage referenced to Vss 0 V Max Val PARAMETER Symbol Test Condition ax Value Unit 1 35V 1 5V Operating One Bank Active pO Operating current One bank ACTIVATE to PRECHARGE 4115 1160 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 1205 1250 mA Precharge Current Precharge Power Precharge power down current Slow exit Down Current Ipp2P 700 700 mA Precharge Power Ioo2P Precharge power down current Fast exit 745 790 mA Down Current PD Precharge Quiet Precharge quiet standby current Standby Current Ipo2Q 840 885 mA Precharge Standby Precharge standby current Current Ipp2N 905 905 mA Active Power Down Active power down current Current Ipp3P 835 835 mA Active Standby Active standby current Current Ipp3N 1075 1125 mA Operating Burst Burst write operating curre
15. rmal Characteristics 0 Bit 7 Heat Spreader Solution No HS 65 Register Manufacturer ID Code Least Significant Byte UNUSED Optional 66 Register Manufacturer ID Code Most Significant Byte Optional UNUSED 0x00 67 Register Revision Number Optional o oxFF 68 Register Type 0x00 Bit 2 0 Support Device SSTE32882 Bit 7 3 Reserved 0 69 SSTE32882 RC1 MS Nibble RCO LS Nibble UNUSED 70 SSTE32882 RC3 MS Nibble RC2 LS Nibble Drive Strength 0x00 Command Address Bit 1 Bit 0 RC2 DA3 4 Value RESERVED Bit 3 Bit 2 RC2 DBAO 1 Value RESERVED Bit 5 Bit 4 RC3 DAA 3 value Command Address A Outputs Light Bit 7 Bit 6 RC3 DBAO 1 value Command Address B Outputs Light 71 SSTE32882 RC5 MS Nibble RC4 LS Nibble Drive Strength Control and 0x00 Clock Bit 1 Bit 0 RC4 DA3 4 Control Signals A Outputs Light Bit 3 Bit 2 RCA DBAO 1 Control Signals B Outputs Light Bit 5 Bit 4 RC5 DA4 3 value Y1 Y1 and Y3 Y3 Clock Outputs Light Bit 7 Bit 6 RC5 DBAO 1 value YO YO and Y2 Y2 Clock Light Outputs 72 SSTE32882 RC7 MS Nibble RC6 LS Nibble UNUSED 73 SSTE32882 RC9 MS Nibble RC8 LS Nibble UNUSED 0x00 74 SSTE32882 RC11 MS Nibble RC10 LS Nibble UNUSED 75 SSSTE32882 RC13 MS Nibble RC12 LS Nibble UNUSED 0x00 Document 06581 Revision A 12 May 10 Dataram Corporation 2010 Page 10 L y2DATARAM DTM64331A MN 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM
16. ye DTM64331A 7 ii lt l 1GB 240 Pin 1Rx8 Registered ECC LV DDR3 DIMM Identification DTM64331A 128Mx72 1GB 1Rx8 PC3L 10600R 9 10 A0 Performance range Clock Module Speed CL trep tre 667 MHz PC3L 10600 9 9 9 533 MHz PC3L 8500 8 8 8 533 MHz PC3L 8500 7 7 7 400 MHz PC3L 6400 6 6 6 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high DTM64331A is a registered 128Mx72 memory _ module which conforms to JEDEC s DDR3L PC3L Operating Voltage VDD VDDQ 1 35V 1 283V to 1 45V 10600 standard The assembly is Single Rank The Backward compatible to VDD VDDQ 1 5V 0 075V rank is comprised of nine 128Mx8 DDR3L Samsung SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination I O Type SSTL_15 On board I2C temperature sensor with integrated serial presence detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode impedance are programmable to maintain signal ZQ Calibration for Output Driver and On Die Termination ODT integrity o the MO signals inia Fly by topology N A thermal sensor accurately monitors the DIMM Programmable ODT Dynamic ODT during Writes module and can prevent exceeding the maximum Programmable CAS Latency 6 7 8 and 9 oper
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