Dataram DTM64312H memory module
Contents
1. Tee DTM64312H MM 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Identification DTM64312H 256Mx72 2GB 2Rx8 PC3 10600R 9 10 BO Performance range Clock Module Speed CL trep trp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 933 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Description DTM64312H is a registered 256Mx72 memory module which conforms to JEDEC s DDR3 PC3 10600 standard The assembly is Dual Rank Each Rank is comprised of nine 128Mx8 DDR3 1333 Hynix SDRAMs One 2K bit EEPROM is used for Serial Presence Detect and a combination register PLL with Address and Command Parity is also used Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals in a Fly by topology A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C Ua mimi Ei zm DM 1 se ALT El P a bop us zn D ug CEU TANI BF ies Ba AI KM TI LY WE dod Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm high Operating Voltage 1 5V x 0 075 Type SSTL 15 On board I2C temperature sensor with integrated serial presence detect SPD EEPROM Data Transfer Rate 10 6 Gigabytes sec Data Bursts 8 and burst chop 4 mode ZQ Calibration for Output Driver and On Die Termination ODT2. pen Self refresh temperature current MAX Tc 85 Operating Bank interleave Read lop7 All bank interleaved read current 1755 mA Current One module rank in this operation the rest in IDD2P slow exit All module ranks in this operation Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 Page 6 DTM64312H M 2GB 240 2Rx8 Registered ECC DDR3 DIMM AC Operating Conditions Internal read command to first data ns CAS to CAS Command Delay Clock High Level Width tox Clock Low Level Width tox Data Input Hold Time after DQS Strobe tu B ps DQ Input Pulse Width topw 400 ps DQS Output Access Time from Clock ps Write DQS High Level Width tek avo Write DQS Low Level Width tox avg DQS Out Edge to Data Out Edge Skew was T m5 ps Data Input Setup Time Before DQS Strobe ts 30 DQS Falling Edge from Clock Hold Time ton 02 DGS Falling Edge to Clock Setup Time es o tck avg Address and Command Hold Time after Clock ps Address and Command Setup Time before Clock tis OH ps Load Mode Command Cycle Time tw e Active to Precharge Time ns Active to Active Auto Refresh Time amp n Average Periodic Refresh Interval 0 C lt Tcase lt 85 C 0 7 78 Us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C otn 39 Us Auto Refresh Row Cycle Time 10 ns Row Precharg
3. Programmable ODT Dynamic ODT during Writes Programmable CAS Latency 6 7 8 and 9 Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully RoHS Compliant Pin Description Pin Configuration Front Side Back Side Function 1 Vnerpo 31 0025 61A2 91 DQ41 121 Vss 151 Vss 181A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32 Vss 62 Vpp 92 Vss 122004 152 DM3 182 Vpp 212 DM5 DQ 63 0 Data Bits 3 133 09 3 63 CK1 93 DQS5 123 DQ5 153 TDQS12 1183 Vpp 213 TDQS14 DQS 8 0 DQS 8 0 Differential Data Strobes 4 001 13400 3 64 CK1 94 DQS5 124 Vss 154 Vss 184 CKO 214 Vss DM 8 0 Data Mask 5 Vss 35 Vss 65 Vpp 95 Vss 125 DMO 155 DQ30 185 CKO 215 DQ46 TDQS 17 9 Termination Data Strobes 6 DQSO 36 DQ26 66 Vpp 96 0042 126 TDQS9 156 DQ31 186 Vpp 216 DQ47 CK 1 0 CK 1 0 Differential Clock Inputs 7 DQSO 37 DQ27 67 VngrcA 97 0043 127 Vss 157 Vss 187 Event 217 Vss CKE 1 0 Clock Enables 8 Vss 38 Vss 68 Par In 98 Vss 11280906 158 CB4 188 AO 218 DQ52 ICAS Column Address Strobe 9 DQ2 139 69 VDD 99 0048 129 007 159 5 189 Vpp 219 0053 RAS Row Address Strobe 10DQ3 40CB1 70 A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss S 3 0 Chip Selects 11 Vss 41 Vss 71 BAO 101 131 0912 161 DM8 191 Vpp 221 DM6 IWE Write Enable 12008 42 DQS8 72 102 DQS6 132 0013 162 TTDQS17 192 RAS 222 TDQS15 A 15 0 Address Inputs 13009 430058 73 WE 103 DQS6 133 Vss 163 Vss 193 S0 223 Vss BA 2 0 Bank Ad
4. 136 137 138 139 140 141 142 143 144 145 146 147 148 O N Module Nominal Height 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM UNUSED Bit 4 Bit 0 Module Nominal Height max in mm 29 lt h lt 30 Bit 7 Bitb Reserved Module Maximum Thickness 0 Bit 3 Bit Front in mm baseline thickness 1 mm Bit 7 Bit 4 Back in mm baseline thickness 1 mm Reference Raw Card Used Bit 4 Reference Raw Card Bit 6 Bit 5 Reference Raw Card Revision Bit 7 Reserved Address Mapping from Edge Connector to DRAM Bit 0 Rank 1 Mapping Registered DIMM Reserved tus Module Specific Section Register Revision Number Module Specific Section Module Specific Section Module Specific Section Module Specific Section Module Specific Section Module Manufacturer ID Code Least Significant Byte Module Manufacturer ID Code Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number Cyclical Redundancy Code Cyclical Redundancy Code Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Revision Code DRAM Manufacturer ID Cod
5. 2 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved Module Memory Bus Width Bit 2 Primary bus width in bits 8 Bits O 0 Bit 4 Bit 3 Bus width extension in bits Bit 7 Bit 5 Reserved Fine Timebase FTB Dividend Divisor Bit 3 Bit 0 Fine Timebase FTB Divisor Bit 7 Bit 4 Fine Timebase FTB Dividend 2 5 0 125ns 0 125ns i 14 CAS Latencies Supported Least Significant Byte 4 Bit 1 5 Bit 2 CL 6 Bit 3 CL 7 Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 0x92 0x10 0x01 0x02 0 11 0x00 0x09 OxOB 0x52 0x01 0x08 OxOC 0x00 Ox3C D gt lt Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 Page 8 DTM64312H Optimizing Value and Performance 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM 15 CAS Latencies Supported Most Significant Byte Bit 0 CL 12 CL 13 Bit 2 CL 14 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved 0x00 Minimum CAS Latency Time tAAmin 13 125ns Minimum Write Recovery Time tWRmin 15 0ns 0x78 Minimum RAS to CAS Delay Time tRCDmin 13 125ns Minimum Row Active to Row Active Delay Time tRRDmin 20 Minimum Row Precha
6. 6O TDQSR110 TDQSR15O DQR 23 16 DQR 55 48 DQSR3 DQSR7 DQSR3 DQSR7 DMR3O DMR7O TDQSR120 TDQSR160 DQR 31 24 56 63 DQSR8O DQSR8 DMR8O TDQSR17 CBR 7 0 TO SDRAMS VDD VDD All All 39 OHMS 100 nF All 39 OHMS 100 nF 22 OHMS mE 15 OHMS LCLK 1 0 RCLK 1 0 ul WW _O bu ILCLK 1 0 ov RCLK 1 0 c 7 0 O O CBR 7 0 PA BAIR 15 0 15 0 DQS 8 0 Q NN O DQSR 8 0 IRAS RASR DQS 8 0 O O DQSR 8 0 ICAS ICASR IWE WER 0 8 0 O WN O DMR 8 0 CKEO A CKEOR i CKE1 um CKE1R DECOUPLING ODT1 Y ODT1R VDD All Devices PAR_IN ERR_OUT VREF DQ All SDRAMs GLOBAL SDRAM CONNECTS CKO L R CLK 1 0 g Vss All Devices 120 All 39 OHMS OHMS REF_CA All SDRAMs BA 2 0 R CKO L R CLK 1 0 V TT 4 A SDRAMs A 15 0 R RESET RASR SDRAMS CASR oe EVENT e TEMPERATURE MONITOR ZQ SCL SERIAL PD CKE 1 0 R S VN ODT 1 0 R RS 1 0 VTT Vss Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM SA1 SA2 SAO Page 3 DATARAM DTM64312H ee 2GB 240 2Rx8 Registered ECC DDR3 DIMM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability Ambient Temperature Operating Oo 70 C DRA
7. M Case Temperature Operating Tos 0 HK C Voltage on Vpp relative to Vss V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note I O Reference Voltage 0 49 0 50 0 51 Voo 1 I O Reference Voltage VREFCA 0 49 Vpp 0 50 Vpp 0 51 Vpp 1 Notes 1 The value of Vrer is expected to equal one half Vpp and to track variations the Vpp DC level Peak to peak noise on Vrer may not exceed 1 of its DC value For Reference Vpp 2 15 mV DC Input Logic Levels Single Ended T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Unit Logical Low Logic 0 DC i 0 1 V AC Input Logic Levels Single Ended 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical Low Logic 0 Vner 0 175 V Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 Page 4 DTM64312H EE 2GB 240 2Rx8 Registered ECC DDR3 DIMM Differential Input Logic Levels 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low DC Vss AC Vss 0 4 0 200 V Differential Inpu
8. dresses 14 Vss 44 Vss 74 CAS 104Vss 134 DM1 164 CB6 194 Vpp 224 DQ54 ODT 1 0 On Die Termination Inputs 15 DQS1 45 CB2 75 105 DQ50 135 TDQS10 165 CB7 195 ODTO 225 DQ55 SA 2 0 SPD Address 16 0051 46 76 81 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss SCL SPD Clock Input 17 Vss 47 Vss 77 ODT1 107 Vss 11370014 167 NC TEST 197 Vpp 227 DQ60 SDA SPD Data Input Output 18 0010 8 Vit 78 Vpp 108 0056 138 0015 168 RESET 198 53 NC 228 0961 Event Temperature Sensing 190011 49 Vrt 79 82 109 0057 139 Vss 169 CKE1 199 Vss 229 Vss RESET Reset for register and DRAMs 20 Vss 50 CKEO 80 Vss 110Vss 140DQ20 170 Vpp 200 DQ36 230 DM7 PAR IN Parity bit for Addr Ctrl 210016 51 Vpp 81 DQ32 111 DQS7 141 DQ21 171 15 201 DQ37 231 TDQS16 ERR OUT Error bit for Parity Error 22DQ17 52 2 82 DQ33 112 DQS7 142 Vss 172 A14 202 Vss 232 Vss Vss Ground 23 Vss 53 Err Our 83 Vss 113 143DM2 173 Vpp 203 DM4 233 DQ62 2410052 54 Vpp 84 DQS4 114 0058 144 TDQS11 174 A12 BC 204 TQDS13 234 DQ63 Vopspp SPD EEPROM Power 25 0952 55 A11 85 DQS4 115 DQ59 145 Vss 175 A9 205 Vss 235 Vas VREFDO Reference Voltage for DQ 26 Vss 56 A7 86 Vss 116 146 DQ22 176 Vpp 206 0038 236 Vppspp Reference Voltage for CA 270018 157 Vpp 870034 117 11470023 177 207 0039 237 SA1 Termination Voltage 28 0019 58 A5 88 DQ35 118 SCL 1148 Vss 178 A6 208 Vss 238 SDA NC No Connection 29 Vss 59 A4 89 Vss 119 SA2 149 0028 179 Vb
9. e Least Significant Byte UJ N UJ AJ n lt Q UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED CRC RC O UNUSED 0x00 0 11 0 01 0x05 0x00 0x50 0x00 0x00 0x00 0x01 0x91 0x00 0x20 0x20 0x4F OxC3 0x20 0x44 0x41 0x54 0x41 0x52 0x41 0x4D 0x33 0x31 0x32 0x00 O CO O TI NIN w jN T O O Ijojo c 3 5 o as JJ lt o 5 gt ol o o D mp D e 3 5 N l Page 10 ee 240 2Rx8 Registered ECC DDR3 DIMM DRAM Manufacturer ID Code Most Significant Byte UNUSED 150 175 Manufacturer s Specific Data UNUSED 176 255 Open for customer use UNUSED Se EEE Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 Page 11 DTM6431 2H C 8 Optimizing Value and Performance 2 240 Pin 2Rx8 Registered ECC DDR3 DIMM DATARAM Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in t
10. e Time ae ns Read DQS Preamble Time tere 09 tck avg Read DQS Postamble Time tck avg Row Active to Row Active Delay Max 4nCK 6ns ns Internal Read to Precharge Command Delay tare Max 4nCK 7 5ns ns Write DQS Preamble Setup Time Write DQS Postamble Time Xe 0T tes Write Recovery Time p wa 15 n Internal Write to Read Command Delay lwTR 4 7 5ns ns Notes 1 maximum preamble is bound by tLZDQS min 2 The maximum postamble is bound by tHZDQS max Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 Page 7 Optimizing Value and Performance SERIAL PRESENCE DETECT MATRIX Byte Function 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Value Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage 1 2 3 Key Byte Module Type Bytes 0 116 Key Byte DRAM Device Type DDR3 SDRAM Bit 3 Bit 0 Module Type Bit 7 Bit 4 Reserved SDRAM Density and Banks Bit 3 Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved SDRAM Addressing 0 Bit 2 Bit 0 Column Address Bits Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved Reserved Module Organization UNUSED Bit
11. his document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 Page 12
12. p 209 DQ44 239 Vss 30 DQ24 60 Vpp 90 DQ40 120 11500029 1180 2100045 240 Vt Not used Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 Page 1 Optimizing Value and Performance 2GB 240 Pin 2Rx8 Registered ECC DDR3 DIMM Front view 133 35 5 250 9 50 0 374 30 00 1 181 17 30 0 681 Y 5 00 A 0 197 ed 5 175 phu 47 00 71 00 gt 0 204 1 850 2 795 123 00 4 843 Back view Side view 4 00Max 0 157 Max 4 00 Min 0 157 Min 1 27 10 J 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches l l l _ 2 Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 Dy9DATARAM DIM64312H Optimizing Value and Performance IRS1O Lace EE CREME pn DQSRO IDQSR4 O e DMROO ann DMR4 Q lI DQR 7 0 O44 1 0 7 0 RANK 0 7 0 RANK DQR 39 32 0 7 0 RANK 0 0 7 0 RANK DQSR1O m ullum DQSR5 ml DQSR1O DQSR5O DMR1O DMR5O TDQSR100 TDQSR140 DQR 15 8 DQRI47 40 DQSR20 DQSR6 DQSR2 DQSR6 DMR2O DMR
13. rge Delay Time tRPmin 21 Upper Nibbles for tRAS and tRC 13 125ns Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble 22 Minimum Active to Precharge Delay Time tRASmin Least Significant Byte 2 Minimum Active to Active Refresh Delay Time tRCmin Least Significant Byte 2 Minimum Refresh Recovery Delay Time tRFCmin Least Significant Byte Minimum Refresh Recovery Delay Time tRFCmin Most Significant Byte tWTRmin tRTPmin Upper Nibble for tFAW NO 26 2 28 1 1 Bit 3 Bit 0 tFAW Most Significant Nibble Bit 7 Bit 4 Reserved 29 Minimum Four Activate Window Delay Time tFAWmin Least 240 Significant Byte 30 SDRAM Optional Features Bit 0 RZQ 6 X Bit 1 RZQ 7 X Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support 31 SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Reserved z X 0x69 0 11 0 20 0x89 0x70 0x03 Ox3C Ox3C 0x00 OxFO 0x83 0x05 0x80 Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 Page 9 33 59 61 62 63 64 66 7 68 69 0 71 112 113 114 116 117 118 119 120 121 122 125 126 127 128 131 132 133 134 135
14. t Cross Point Voltage relative to VDD 2 Vix 0 150 0 150 V Capacitance T4 25 C f 100 MHz 00163 0 7 0058 0 DQS 8 0 pF Input Output Capacitance DM 8 0 TDQS 17 9 DC Characteristics T4 0 to 70 C Voltage referenced to Vss Input Leakage Current Le Any input 0 V VIN VDD lot 10 10 UA 2 3 Output Leakage Current OV lt VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled Document 06601 Revision A 10 Sep 10 Dataram Corporation 2010 Page 5 DTM64312H EE 2GB 240 2Rx8 Registered ECC DDR3 DIMM lbo Specifications and Conditions 0 to 70 C Voltage referenced to Vss alue Precharge Current Operating One Operating current One bank ACTIVATE to READ to Precharge Current Precharge Power T PCIE E ULLLLLL power down current Slow exit Ipp2P mA Down Current Precharge Power 2 power down current Fast exit Ipp2P mA Down Current Precharge Quiet o2Q Precharge quiet standby current EJ TA Standby Current Precharge Standby Precharge standby current EN WA Current Active Power Down xx Active power down current Ipp3P mA Current Active Standby Active standby current EE m Current Operating Burst Burst write operating current Operating Burst Iap4R Burst read operating current 1260 Y Read Current Burst Refresh Refresh current 2520 mA Current
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