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Dataram DTM64311F memory module

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1. Module Memory Bus Width Bit 2 Bit O Primary bus width in bits Bit 4 Bit 3 Bus width extension in bits Bit 7 Bit 5 Reserved Fine Timebase FTB Dividend Divisor Bit 3 Bit O Fine Timebase FTB Divisor Bit 7 Bit 4 Fine Timebase FTB Dividend Medium Timebase Dividend 1 MTB i 0x01 i MTB Medium Timebase MTB Divisor 8 MTB 0x0 0 125ns SDRAM Minimum Cycle Time tCKmin 0x0 UNUSED CAS Latencies Supported Least Significant Byte Bit 0 CL 4 Bit 1 CL 5 Bit 2 CL 6 1 Bit 3 CL 7 Bit 4 CL 8 Bit 5 CL 9 Bit 6 CL 10 Bit 7 CL 11 Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 2 3 4 5 7 10 11 12 13 4 Page 8 NNNM 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM CAS Latencies Supported Most Significant Byte 0x00 Bit 0 CL 12 Bit 1 CL 13 Bit 2 CL 14 15 Bit 3 CL 15 Bit 4 CL 16 Bit 5 CL 17 Bit 6 CL 18 Bit 7 Reserved E E 20 Minimum Row Precharge Delay Time tRPmin 13 125ns 0x69 Upper Nibbles for tRAS and tRC 21 Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble Minimum Active to Precharge Delay Time tRASmin Least Significant Byte Minimum Active to Active Refresh Delay Time tRCmin Least 0x89 Significant Byte Minimum Refresh Recovery Delay Time tRFCmin
2. Least 0x7 Significant Byte ERN Refresh Recovery Delay Time tRFCmin Most 0x0 Significant Byte 26 Minimum Internal Write to Read Command Delay Time 7 5ns 0x3 tWTRmin Minimum Internal Read to Precharge Command Delay Time 7 5ns 0x3 27 tRTPmin Upper Nibble for tFAW 28 Bit 3 Bit 0 tFAW Most Significant Nibble Bit 7 Bit 4 Reserved Minimum Four Activate Window Delay Time tFAWmin Least Significant Byte SDRAM Optional Features Bit 0 RZQ 6 Bit 1 RZQ 7 Bit 6 Bit 2 Reserved Bit 7 DLL Off Mode Support SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh ASR On die Thermal Sensor ODTS Readout Reserved Reserved Reserved Partial Array Self Refresh PASR Module Thermal Sensor ox80 Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 Page 9 NNNM 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Bit 6 Bit O Thermal Sensor Accuracy 9 SDRAM Device Type Bit 6 Bit O Non Standard Device Description Module Nominal Height Bit 4 Bit 0 Module Nominal Height max in mm Bit 7 Bits Reserved Module Maximum Thickness Bit 3 Bit 0 Front in mm baseline thickness 1 mm Bit 7 Bit 4 Back in mm baseline thickness 1 mm Reference Raw Card Used 62 Bit 4 Bit 0
3. DQS 8 0 O MA O DOQSR 8 0 DQS 8 0 O O DQSR 8 0 DM 8 0 O O DMRI 8 0 TDQS 17 9 O VW O TDQSR 17 9 GLOBAL SDRAM CONNECTS All 47 OHMS BA 2 0 R A 15 0 R IRASR ICASR IWER VTT All 47 OHMS CKEOR ODTOR RSO VTT TO SDRAMS All 22 OHMS 180 w IRSO 181 AM BA 2 0 ww BA 2 0 R A 15 0 MA I A 15 0 R IRAS WWw IRASR ICAS y ICASR NE w J INER CKE0 AM Q CKEOR opto w D ODTOR ad PAR IN AAN JERR OUT CKO L R CLK O 120 OHMS ICKO I L R CLK O RESET TE SDRAMS All 240 OHMS za iid Vss DQSR4 O DQSR4 O DMR4O TDQSR13 0 gt z o O e DQR 39 32 O VO 7 0 RANK 0 DQSR5 O DQSR5 O DMR5O TDQSR140 DQR 47 40 O DQSR6 O DQSR6 O DMR6 O TDQSR15O DQR 55 48 O DQSR7 O DQSR7 O DMR7 O TDQSR16O DM gt z TDQS TDQS ICS DQS DOS DQR 63 56 O I 0 7 0 VDD All 36 OHMS 100 nF RCLKO E zm RCLKO VDD All 36 OHMS 100 nF LCLKO cor LCLKO 75 OHMS CK1 O AAN O CK1 DECOUPLING VDDSPD Serial PD VDD All Devices VREF DQ All SDRAMs Vss All Devices VREF CA All SDRAMs VTT F All SDRAMs Do EVENT TEMPERATURE MONITOR SDA Scr SERIAL PD SAO SA1 SA2 Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 Page 3 JP DATARAM Optimizing Value and Performance Absolute Maximum Ratings Note Operation at or
4. 10 3 Fully RoHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 Vrerva 31 DQ25 61 A2 91 DQ41 121 Vss 151 Vss 181A1 211 Vss CB 7 0 Data Check Bits 2 Vss 32Vss 62 Voo 92 Vss 122D04 152DM3 182 Voo 212 DM5 DQ 63 0 Data Bits 3 DQO 33 DQS3 63 CK1 93 DQS5123DQ5 153 TDQS12 183 Voo 213 TDQS14 DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34DQS3 64 ICK1 94 DQSS5 124 Vss 154 Vss 184 CKO 214 Vss DM 8 0 Data Mask 5 Vos 35 Vss 65 Voo 95 Vs 125DM0 155DQ30 185 CKO 215DQ46 TDQS 17 9 Termination strobes 6 DQS036 DQ26 66 Voo o6 DQ42 126 TDQS9 156 DQ31 186 Voo 216DQ47 CK 1 0 CK 1 0 Differential Clock Inputs 7 DQSO 37 DQ27 67 Vrerca 97 DQ43 127 Vss 157 Vss 187 EVENT 217 Vss CKE 1 0 Clock Enables 8 Vss 38Vss 68Par In 98 Vss 128DQ6 158CB4 188 AO 218DQ52 CAS Column Address Strobe 9 DQ2 39CBO 69 VDD 99 DQ48 129DQ7 459CcB5 189 Voo 219DQ53 RAS Row Address Strobe 10DQ3 40CB1 70A10 AP 100 DQ49 130 Vss 160 Vss 190 BA1 220 Vss IS 3 0 Chip Selects 11Vss 141 Vss 71 BAO 101Vss 131DQ12 161DM8 191 Voo 221 DM6 NE Write Enable 12DQ8 42 DQS8 72 Vop 102 DQse i32DQ13 162 TDQS17 M92 RAS 222 TDQS15 A 15 0 Address Inputs 13DQ9 43 DQS8 73 WE 103 DQS6 133 Vss 163 Vss 193 SO 223 Vss BA 2 0 Bank Addresses 14Vss 44 Vas 74 ICAS 104Vss t34DM1 464CB6 194 Voo 224DQ54 ODT 1 0 On Die Termination Inputs 15 DQS1 45 CB2 75 Voo 105 DQ50 135 TDQS10 165 C
5. Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 Page 5 ne 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Test Condition yax Unit Operating One Bank Active pO Operating current One bank ACTIVATE to PRECHARGE 450 mA Precharge Current Operating One Operating current One bank ACTIVATE to READ to Bank Active Read Ipp1 PRECHARGE 585 mA Precharge Current Precharge Power Precharge power down current Slow exit Down Current lpp2P su mo Precharge Power Precharge power down current Fast exit Down Current loo2P also MA Precharge Quiet Precharge quiet standby current Standby Current Ipo2Q 315 mA Precharge Standby Precharge standby current Current Ipp2N 315 mA Active Power Down Active power down current Current Ipp3P 225 mA Active Standby Active standby current Current Ipp3N 360 mA Operating Burst Burst write operating current Write Current Ipo4W ic Ras Operating Burst Burst read operating current Read Current Ioo4R pane A Burst Refresh Refresh current Current Ipp5 1260 mA Self Refresh Inr6 Self refresh temperature current MAX Tc 85 C 90 mA Current a Operating Bank Interleave Read lan All bank interleaved read current 4440 mA Current Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 Page 6 Optimizing Value and Performance 1GB 24
6. used i E a ee E Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 Page 1 ee 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Front view 133 35 5 250 9 50 0 374 30 00 1 181 k 17 30 0 681 O 5 00 0 197 en 5 175 47 00 71 00 0 204 1 850 2 795 123 00 4 843 Back view Side view 3 94 Max 0 155 Max Wi 4 00 Min 0 157 Min O NAMNNNNNNNMNNNNNNANNNNNNMNNNNNNNNNNNNNNNNNNNNN pon O i 1 27 10 RT 0 0500 40 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches Dog uio PP FS o dina ui Se ee Page 2 Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Optimizing Value and Performance RSO O DQSRO O DQSRO O DMRO O TDQSR9O gt F7 z e a RANK 0 DQR 7 0 O O 7 0 DQSR1 O DQSR1O DMR1O TDQSR100 DQR 15 8 O TDQSR110 DQR 23 16 O DQSR3 IDQSR3 DMR3 ITDOSR120 DMN ZON Du zo GU OO a a aa EF S DQR 31 24 V O 7 0 DQSR8 O IDQSR8 O DMR8O TDQSR170 CBR 7 0 O All 15 OHMS DQ 63 0 O MA O DQR 63 0 CB 7 0 O VW O CBR 7 0
7. 0 Pin 1Rx8 Registered ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data taa 13 125 20 ns CAS to CAS Command Delay tccp 4 tck Clock High Level Width tcH avg 0 47 0 53 tck Clock Cycle Time tck 1 5 1 875 ns Clock Low Level Width cL avg 0 47 0 53 tck Data Input Hold Time after DQS Strobe tou 65 ps DQ Input Pulse Width toipw 400 ps DQS Output Access Time from Clock tpasck 255 255 ps Write DQS High Level Width tbasH 0 45 0 55 tck avg Write DOS Low Level Width toast 0 45 0 55 tck avg DQS Out Edge to Data Out Edge Skew toasa 125 ps Data Input Setup Time Before DQS Strobe tos 30 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tek avg DQS Falling Edge to Clock Setup Time toss 0 2 tck avg Clock Half Period tup minimum of tcu or tci ns Address and Command Hold Time after Clock tin 140 ps Address and Command Setup Time before Clock tis 65 ps Load Mode Command Cycle Time tMRD 4 tck DQ to DQS Hold ton 0 38 tcx avg Active to Precharge Time tras 36 9 treri ns Active to Active Auto Refresh Time tre 49 125 ns RAS to CAS Delay trep 13 125 ns Average Periodic Refresh Interval 0 C lt Tease lt 85 C treri 7 8 us Average Periodic Refresh Interval 0 C lt Tcase lt 95 C treri 3 9 us Auto Refresh Row Cycle Time trrc 110 ns Row Precharge Time tre 1
8. 3 125 ns Read DQS Preamble Time tRPRE 0 9 Note 1 tck avg Read DQS Postamble Time trest 0 3 Note 2 tck avg Row Active to Row Active Delay trRD Max 4nCK 6ns ns Internal Read to Precharge Command Delay trtp Max 4nCK 7 5ns ns Write DQS Preamble Setup Time twPRE 0 9 tck avg Write DQS Postamble Time twPsT 0 3 ck avg Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR Max 4nCK 7 5ns ns Notes 1 The maximum preamble is bound by tLZDQS min The maximum postamble is bound by tHZDQS max Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 Page 7 EE 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Number of Bytes Used Number of Bytes in SPD Device CRC Coverage Bit 3 Bit 0 SPD Bytes Used 176 Bit 6 Bit 4 SPD Bytes Total 256 Bit 7 CRC Coverage Bytes 0 116 1 SPD Revision 0x10 Key Byte DRAM Device Type DDR3 SDRAM Key Byte Module Type 0x01 Bit 3 Bit O Module Type Bit 7 Bit 4 Reserved SDRAM Density and Banks 0x02 Bit 3 Bit O Total SDRAM capacity in megabits 1Gb Bit 6 Bit 4 Bank Address Bits 8 banks Bit 7 Reserved SDRAM Addressing 0x11 Bit 2 Bit 0 Column Address Bits Bit 5 Bit 3 Row Address Bits Bit 7 6 Reserved UNUSED 0x00 Module Organization Bit 2 Bit 0 SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved
9. B7 195ODTO 225DQ55 SA 2 0 SPD Address 16 DQS1 46 CB3 76 S1 106 DQ51 136 Vss 166 Vss 196 A13 226 Vss SCL SPD Clock Input 17Vss 47 Vss 77 0pT1 to7Vss 137DQ14 167 NC TEST 197 Voo 227DQ60 SDA SPD Data Input Output 18 DQ10 48 Vr 78 Voo 108 DQ56 138DQ15 168 RESET 198 S3 NC 228DQ61 EVENT Temperature Sensing 19 DQ11 49 Vrr 79 82 NC 109 DQ57 139 Vss 169 CKE1 1199 Vss 229 Vss IRESET Reset for register and DRAMs 20Vss 50 CKEO 80 Vss 110Vss 140DQ20 170 Vpp 200DQ36 230 DM7 PAR_IN Parity bit for Addr Ctrl 21 DQ16 51 Voo 81 DQ32 111 DQS7 141DQ21 4171A15 201DQ37 231 TDQS16 ERR OUT Error bit for Parity Error 22 DQ17 52 BA2 82 DQ33 112 DQS7 142 Vss 172 A14 202 Vss 232 Vss A12 BC Combination input Addr12 Burst Chop 23Vss 53 En Our 83Vss 113Vsg 143DM2 173 Vpp 203 DM4 233DQ62 A10 AP Combination input Addr10 Auto precharge 24 IDQS2 54 Voo B4 DQS4 114 DQ58 144 TDQS11474 A12 BC 204 TDQS13 234DQ63 Vss Ground 25 DQS2 55 A11 85 DQS4 115 DQ59 145 Vss 175 AQ 205 Vss 235 Vss Voo Power 26Vss 56 A7 86 Vss 116Vss 146DQ22 176 Vpp 206DQ38 236 Vposro Vopsep SPD EEPROM Power 27 DQ18 57 Voo 87 DQ34 1177840 147DQ23 177A8 207 DQ39 237 SA1 VrerDa Reference Voltage for DQ s 28 DQ19 58 A5 88 DQ35 118SCL 148 Vss 178 A6 208 Vss 238 SDA VnEFCA Reference Voltage for CA 29Vss 59A4 89 Vss 119SA2 149DQ28 179 Vpp 209 DQ44 239 Vss Vir Termination Voltage 30 DQ24 60 Voo 90 DQ40 120Vm 150DQ29 180A3 210DQ45 240 Vrr NC No Connection Not
10. I7T5 1777771 DTM64311F ii 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Identification DTM64311F 128Mx72 1GB 1Rx8 PC3 10600R 9 10 A0 Performance range Clock Module Speed CL tncp trp 667 MHz PC3 10600 9 9 9 533 MHz PC3 8500 8 8 8 533 MHz PC3 8500 7 7 7 400 MHz PC3 6400 6 6 6 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 mm DTM64311F is a registered 128Mx72 memory module high which conforms to JEDEC s DDR3 PC3 10600 Operating Voltage 1 5V 0 075 standard The assembly is Single Rank The Rank is comprised of nine 128Mx8 DDR3 1333 Hynix SDRAMs VO Type setis One 2K bit EEPROM is used for Serial Presence On board I2C temperature sensor with integrated serial Detect and a combination register PLL with Address presence detect SPD EEPROM and Command Parity is also used Data Transfer Rate 10 6 Gigabytes sec Both output driver strength and input termination Data Bursts 8 and burst chop 4 mode impedance are programmable to maintain signal E integrity on the I O signals in a Fly by topology ZQ Calibration for Output Driver and On Die Termination ODT A thermal sensor accurately monitors the DIMM module Programmable ODT Dynamic ODT during Writes and can prevent exceeding the maximum operating t t f i Programmable CAS Latency 6 7 8 and 9 Bins Bi Directional Differential Data Strobe signals SDRAM Addressing Row Col Bank 14
11. Reference Raw Card Bit 6 Bit 5 Reference Raw Card Revision Bit 7 Reserved Address Mapping from Edge Connector to DRAM Bit 0 Rank 1 Mapping Registered DIMM Reserved Bit 7 Bit 1 Reserved 64 66 Module Specific Section Module Specific Section Module Specific Section Module Specific Section 14 116 Module Specific Section 117 Module Manufacturer ID Code Least Significant Byte 118 Module Manufacturer ID Code Most Significant Byte 119 Module Manufacturing Location 120 121 Module Manufacturing Date 22 125 Module Serial Number 126 Cyclical Redundancy Code CRC 127 Cyclical Redundancy Code CRC 28 131 Module Part Number 132 Module Part Number 133 Module Part Number 134 Module Part Number 135 Module Part Number 136 Module Part Number 137 Module Part Number 138 Module Part Number 139 Module Part Number 140 Module Part Number 141 Module Part Number 142 Module Part Number 143 Module Part Number 144 Module Part Number UNUSED UNUSED UNUSED UNUSED UNUSED O O Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 Page 10 NNNM 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM 145 Module Part Number 0x20 146 147 Module Revision Code 0x00 eae NEUTER Ss ss MR re Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 Page 11 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM 77 8 BH O
12. above Absolute Maximum Ratings can adversely affect module reliability DTM64311F 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TsroRAGE 55 100 C Ambient Temperature Operating TA 0 70 C DRAM Case Temperature Operating TcasE 0 95 C Voltage on Vpp relative to Vss Vbp 0 4 1 975 V Voltage on Any Pin relative to Vss Vin Vout 0 4 1 975 V Notes DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions Ta O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Typical Maximum Unit Note Power Supply Voltage Voo 1 425 1 5 1 575 V I O Reference Voltage VREFDQ 0 49 Vpp 0 50 Vpp 0 51 Vpp V 1 I O Reference Voltage VREFCA 0 49 Vpp 0 50 Vpp 0 51 Voo V 1 Notes For Reference Vpp 2 15 mV The value of VREF is expected to equal one half VDD and to track variations in the VDD DC level Peak to peak noise on VREF may not exceed 1 of its DC value For Reference VREF VDD 2 15 mV DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH Do Vrer 0 1 Vpp V Logical Low Logic 0 ViL DC Vss Vrer 0 1 V AC Input Logic Levels Single Ended T O to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logi
13. c 1 ViH AC Vrer 0 175 V Logical Low Logic 0 ViL AC Vrer 0 175 V E C E SS SS P SE ET e Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 Page 4 JP DATARAM Optimizing Value and Performance DTM64311F 1GB 240 Pin 1Rx8 Registered ECC DDR3 DIMM Differential Input Logic Levels T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Differential Input Logic High ViH DIFF 0 200 DC Vpp AC Vpp 0 4 V Differential Input Logic Low VIL DIFF DC Vss AC Vss 0 4 0 200 V Differential Input Cross Point Voltage E relative to VDD 2 Vix 9 150 29090 M Capacitance T4 25 C f 100 MHz PARAMETER Pin Symbol Minimum Maximum Unit Input Capacitance Clock CKO CKO Co 1 5 2 5 pF Input Capacitance Address BA 2 0 A 15 0 RAS CAS WE Ci 1 5 2 5 pF Input Capacitance Control SO CKEO ODTO C 1 5 2 5 E DQ 63 0 CB 7 0 DQS 8 0 DQS 8 0 Input Output Capacitance DM 8 0 TDQS 17 9 Cio 1 5 2 5 pF DC Characteristics T4 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current li 18 18 pA 1 2 Any input 0 V VIN VDD Output Leakage Current lo 10 10 pA 2 3 OV VOUT lt VDDQ Notes 1 All other pins not under test 0 V 2 Values are shown per pin 3 DQ DQS DQS and ODT are disabled eae a a dE Ss Ms AR CS e ct
14. ptimizing Value and Performance PIPDATARAM d BH Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06600 Revision A 10 Sep 10 Dataram Corporation 2010 Page 12

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