Dataram DTM63372A memory module
Contents
1. PARAMETER Symbol Minimum Maximum Unit Temperature non Operating TstTORAGE 55 100 C Ambient Temperature Operating Ta 0 70 C DRAM Case Temperature Operating Tcase 0 95 C Voltage on Vpp relative to Vss Vpp 0 5 2 3 V Voltage on Any Pin relative to Vss Vin Vout 0 5 2 3 V DRAM Operating Case Temperature above 85C requires 2X refresh Recommended DC Operating Conditions T 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Ea B r a Note Power Supply Voltage 1 O Reference Voltage Bus Termination Voltage Notes Veer 0 04 VREF Vrer 0 04 1 The value of Vrer is expected to equal one half Vpp and to track variations in the Vpp DC level Peak to peak noise on Veer may not exceed 1 of its DC value DC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 ViH DC Vrer 0 125 Vpop 0 300 V Logical Low Logic 0 ViL oc 0 300 Vrer 0 125 V AC Input Logic Levels Single Ended T 0 to 70 C Voltage referenced to Vs 0 V PARAMETER Symbol Minimum Maximum Unit Logical High Logic 1 Vin ac Vrer 0 250 V Logical Low Logic 0 Vilac x Vrer 0 250 V Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 4 DTM63372 DATARAM 1GB 128Mx64 240 Pin Unbuffered non ECC DDR2 DIMM Differential Input Logic Levels T 0 to 70 C Vol2. Degree C 5 DRAM Case Temperature Rise from Ambient due to Page Open Burst Ox4A Read DT4R4W Mode Bit DT4R DT4R4W Mode Bit Degree C Bit 0 0 if DT4W is greater than DT4R DTAR Bits 1 7 56 DRAM Case Temperature Rise from Ambient due to Burst 24 5 0x31 Refresh DT5B Degree C 57 DRAM Case Temperature Rise from Ambient due to Bank 0x35 Interleave Reads with Auto Precharge DT7 Degree C 58 Thermal Resistance of PLL Package from Top to Ambient UNUSED 0x00 Psi TA PLL C Watt Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 10 DTM63372 JANA ANUT 166 128mx64 240 Pin Unbuffered non ECC DDR2 Dimm 59 Thermal Resistance of Register Package from Top to Ambient UNUSED 0x00 Psi T A Register C Watt PLL Case Temperature Rise from Ambient due to PLL Active UNUSED 0x00 DT PLL Active Degree C Register Case Temperature Rise from Ambient due to Register Active Mode Bit DT Register Active Mode Bit Bit 0 If O Unit for Bits 2 7 is 0 75C 0 75 Bit 1 RFU Default 0 i Register Active Bits 2 7 a for Bytes 0 62 0x9D 7a90ModuePatNombeer J ow 96 Modde SerialNumber E Tas 1 o7 Module SerialNumber o f o R T oa 1 o8 Modde SerialNumber os 1 P Specific Data UNUSED 127 Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 11 DTM63372 DATARAM 1GB 128Mx64 240 Pin Unbuffered non ECC DDR2 DIMM D
3. 2009 S0 O DMRO DQSRO O DQSRO O IDAS DOS DARI7 0 OF 1 0 7 0 DMR10 DQSR10 DQSR10 DQS DOS CS DM DQR 15 8 O 1 017 0 DMR2 O DQSR20 DQSR20 DQS DOS CS DM DQR 23 16 O V O 7 0 DMR3 O DQSR3 O DQSR3 O DQS DAS CS DM DAR 31 24 O 1 0 7 0 DQ 63 0 O WA O DQR 63 0 DQS 7 0 O VAW O DQSR 7 0 IDQS 7 0 O VWA O DARS 7 0 DM 7 0 O VA O_ DMR 7 0 GLOBAL SDRAM CONNECTS BA 2 0 O WA O BA 2 0 R A 13 0 O WA O A 13 0 R IRAS O VWA IRASR ICAS O WA 0O _ CASR IWE O VW O WER CKEO CKEO Z 22 pF ODTO ODTO Z 22 pF SO SO 22 pF DTM63372 1GB 128Mx64 240 Pin Unbuffered non ECC DDR2 DIMM DMR4 DQSR4 O DQSR4 O DQR 39 32 O DMR5 O DQSR5 O DQSR5 O DQR 47 40 O DMR6 O DQSR6 O DQSR6 O DQR 55 48 O DMR7 O DQSR7 O DQSR7 O DQR 63 56 O 67 OHMS CKO O SDRAM X 2 CKO 67 OHMS CK1 SDRAM X 3 ICK1 67 OHMS CK2 SDRAM X 3 ICK2 DECOUPLING VDDSPD gt Serial PD VDD All Devices Vss All Devices BUF SERIAL PD SDA WP SAO SA1 SA2 Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 3 DTM63372 1GB 128Mx64 240 Pin Unbuffered non ECC DDR2 DIMM DATARAM Absolute Maximum Ratings Note Operation at or above Absolute Maximum Ratings can adversely affect module reliability
4. SDRAM Module Attributes Refer to Byte20 for DIMM type information 0x00 Number of active registers on the DIMM N A for UDIMM Number of PLL on the DIMM N A for UDIMM FET Switch External Enable TBD Analysis probe installed TBD SDRAM Device Attributes General 0x03 Includes Weak Driver Supports 50 ohm ODT Supports PASR Partial Array Self Refresh TBD TBD TBD TBD TB ee eee Clock Cycle Time at Reduced CAS Latency CL X Lee ee 27 fai Data Access Time tAC from Clock at CL X 1 ae ae 35 Mimu Minimum Clock Cycle Time at CL X 2 as TsO 26 al Data Access Time tAC from Clock at CL X 2 ae ae ar Minima Row Minimum Row Precharge Time tRP ns Time tRP ns 28 Minimum Row Active to Row Active Delay tRRD Fan Roe katie Na N fp tse 29 Minimum RAS to CAS Delay RCD n z 30 Minimum Active to Precharge Tine RASI _ om pares ard Conmand Setup Tre Belas Coa aa 33 Address and Command Hold Time me st xa C4 pala nat Seng Tine Bere Stobe Des 01 f oo 35 Data Input Hold Time ate Strobe DU z aa ST ema we to reed ommend sey WR e 78 ft Internal read to precharge command T PY 75 01E Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 9 DTM63372 YAU PAV ANUT 1GB 128mx64 240 Pin Unbuffered non ECC DDR2 Dimm 39 Memory Analysis Probe Characteristics UNUSED 40 Extension of Byte 41
5. Planar 5 Hex 0x80 0x08 0x08 Ox0E Ox0A 0x60 yee Se ee Lee f Module Height 30mm En 6 Moduie Data Widin UNUSED 8 Voltage Interface Level of this assembly SSTL 1 8V fa Cycle time Max Supported CAS Latency CL X 3 0 0x30 tCK ns 10 SDRAM Access from Clock Highest CAS latency tAC ns 11 DIMM configuration type Non parity Parity or ECC 0x00 Data Parity Data ECC Address Command Parity TBD TBD TBD TBD TBD 12 Refresh Rate Type us 7 8 SR 13 Primary SDRAM Width e f oa 14 Error Checking SDRAM Width UNUSED 15 Reserved UNUSED 16 SDRAM Device Attributes Burst Lengths Supported 0x0C TBD TBD Burst Length 4 Burst Length 8 TBD TBD TBD TBD 17 SDRAM Device Attributes Number of Banks on SDRAM 0x08 Device 18 SDRAM Device Attributes CAS Latency 0x30 TBD TBD Latency 2 Latency 3 Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 8 DTM63372 JAAN ANUT 1GB 128mx64 240 Pin Unbuffered non ECC DDR2 Dimm Latency 4 K Latency 5 K Latency 6 TBD DIMM Mechanical Characteristics Max module thickness K KANG 4 10 0x01 mm DIMM type information 0x02 Regular RDIMM 133 35mm Regular UDIMM 133 35mm SODIMM 67 6mm Micro DIMM 45 5mm Mini RDIMM 82 0mm Mini UDIMM 82 0mm TBD TBD
6. ATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 12
7. D 214 DQ46 DM 8 0 Data Mask 5 VSS 35 VSS 65 VSS 95 DQ42 125 DMO 155 DM3 185 CKO 215 DQ47 CK 2 0 CK 2 0 Differential Clock Inputs 6 DQSO_ 36 DQS3 66 VSS 96 DQ43 126 NC 156 NC 186 CKO 216 VSS CKE 1 0 Clock Enables 7 DQSO0 87 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52 ICAS Column Address Strobe 8 VSS 38 VSS 68 NC 98 DQ48 128 DQ6 158 DQ30 188 A0 218 DQ53 IRAS Row Address Strobe 9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS S 1 0 Chip Selects 10 DQ3 40 DQ27 70 A10 100 VSS 130 VSS 160 VSS 190 BA1 220 CK2 WE Write Enable 11 VSS 41 VSS 71 BAO 101 SA2 131 DQ12 161 CB4 NC 191 VDD 221 CK2 A 15 0 Address Inputs 12 DQ8 42 CBO NC 72 VDD 102 NC 132 DQ13 162 CB5 NC 192 RAS 222 VSS BA 2 0 Bank Addresses 13 DQ9 43 CB1 NC 73 WE 103 VSS 133 VSS 163 VSS 193 S0 223 DM6 ODT 1 0 On Die Termination Inputs 14 VSS 44 VSS 74 ICAS 104 DQS6 134 DM1 164 DM8 NC 194 VDD 224 NC SA 2 0 SPD Address 15 DQS1 45 DQS8 NC 75 VDD 105 DQS6 135 NC 165 NC 195 ODTO 225 VSS SCL SPD Clock Input 16 DQS1 46 DQS8 NC 76 S1 106 VSS 136 VSS 166 VSS 196 A13 226 DQ54 SDA SPD Data Input Output 17 VSS 47 VSS 77 ODT1 NC 107 DQ50 137 CK1 167 CB6 NC 197 VDD 227 DQ55 VSS Ground 18 NC 48 CB2 NC 78 VDD 108 DQ51 138 CK1 168 CB7 NC 198 VSS 228 VSS VDD Power 19 NC 49 CB3 NC 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60 VDDSPD SPD EEPROM Power 20 VSS 50 VSS 80 DQ32 110 DQ56 1140 DQ14 170 VDD 200 DQ37 230 DQ61 VREF Reference Voltage 21 DQ10 51 VD
8. D 81 DQ33 111 DQ57 141 DQ15 171 CKE1 NC 201 VSS 231 VSS NC No Connection 22 DQ11 52 CKEO 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4 232 DM7 23 VSS 53 VDD 83 DQS4 113 DQS7 143 DQ20 173 A15 203 NC 233 NC 24 DQ16 54 BA2 84 DQS4 114 DQS7 144 DQ21 174 A14 204 VSS 234 VSS 25 DQ17 55 NC 85 VSS 115 VSS 145 VSS 175 VDD 205 DQ38 235 DQ62 26 VSS 56 VDD 86 DQ34 116 DQ58 146 DM2 176 A12 206 DQ39 236 DQ63 27 DQS2 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 VSS 237 VSS 28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD 29 VSS 59 VDD 89 DQ40 119 SDA f149DQ22 179 A8 209 DQ45 239 SAD 30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1 Connected but not used C a a a a a g e E Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 1 DTM63372 1GB 128Mx64 240 Pin Unbuffered non ECC DDR2 DIMM Front view 133 35 5 250 10 00 a K 17 80 0 700 2 54 Min 0197 0 100 Min 5 18 k p 63 00 a 55 00 gt 2 480 2 165 be 123 00 a 4 843 Side view ma 2 67Max 0 105 Max Back view 4 00 Min 0 157 Min 1274 10 P 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches pe a Na a aa ai Na a a a LES Page 2 Document 06504 Revision A 10 Feb 09 Dataram Corporation
9. DQ loz 10 10 JA 2 Output Minimum Source DC Current lon 13 4 mA 3 Output Minimum Sink DC Current lot 13 4 mA 4 Notes 1 These values are guaranteed by design and are tested on a sample basis only 2 DQx and ODT are disabled and 0 V lt Vout lt Voo 3 Voo 1 7 V Vout 1420 mV Vour Voo lon must be less than 21 Ohms for values of Vout between Von and Vopn 280 mV 4 Vo 1 7 V Vout 280 mV Vour lo must be less than 21 Ohms for values of Vout between 0 V and 280 mV Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 5 DTM63372 DATARAM 1GB 128Mx64 240 Pin Unbuffered non ECC DDR2 DIMM lbo Specifications and Conditions Ta 0 to 70 C Voltage referenced to Vss 0 V as Max F PARAMETER Symbol Test Condition Value Unit Operating One CKE is HIGH CS is HIGH between valid commands Address BAN AGUNG po bus inputs are switching Data bus inputs are switching oe a Precharge Current i Operating One lour 0 mA BL 4 CL 5 AL 0 CKE is HIGH CS is HIGH Bank eee Read loo between valid commands Address bus inputs are switching 649 A Precharge Current i Precharge Power Ib 2P All banks idle CKE is LOW Other control and address bus inputs 80 mA Down Current Be are stable Data bus inputs are floating Precharge Quiet lpp2Q All banks idle CKE is HIGH CS is HIGH Other control and 240 mA Standby Current PD address bus inputs are stable Data bus inputs are float
10. DTM63372 1GB 128Mx64 240 Pin Unbuffered non ECC DDR2 DIMM Identification DTM63372 128Mx64 Performance range Clock Module Speed CL trep trp spa iit 333MHz DDR2 667 5 5 5 267MHz DDR2 533 4 4 4 Features Description 240 pin JEDEC compliant DIMM 133 35 mm wide by DTM63372 is an Unbuffered non ECC 128Mx64 30 mm high memory module which conforms to JEDEC s Operating Voltage 1 8 V 0 1 DDR2 PC2 5300 standard The assembly is i comprised of one Rank of eight 128Mx8 DDR2 VO Type Se Tie SDRAMs One 2K bit EEPROM is used for Serial Data Transfer Rate 5 3 Gigabytes sec Presence Detect Data Bursts 4 or 8 bits Sequential or Interleaved ordering Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I O signals Programmable I O driver strength OCD Programmable On Die Termination ODT Programmable CAS Latency 4 or 5 Differential Redundant Data Strobe signals SDRAM Addressing Row Col Bank 14 10 3 Fully ROHS Compliant Pin Configuration Pin Description Front Side Back Side Name Function 1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDD 211 DM5 CB 7 0 Data Check Bits 2 VSS 32 VSS 62 VDD 92 DQS5 122 DQ4 152 DQ28 182 A3 212 NC DQ 63 0 Data Bits 3 DQO 33 DQ24 63 A2 93 DQS5 123 DAH 153 DQ29 183 A1 213 VSS DQS 8 0 DQS 8 0 Differential Data Strobes 4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VD
11. ing Precharge Standby lon2N All banks idle CKE is HIGH CS is HIGH Other control and 320 mA Current uD address bus inputs are switching Data bus inputs are switching 7 All banks open CKE is LOW Other control and address bus Active PowerDown Ipp3P inputs are stable Data bus inputs are floating Fast Power down 200 mA Current exit Mode Register bit 12 0 Active Power Down All banks open CKE is LOW Other control and address bus Ipp3P inputs are stable Data bus inputs are floating Slow Power down 96 mA Current A 7 exit Mode Register bit 12 1 All banks open tras 70 ms CKE is HIGH CS is HIGH between patel Standby Ipp3N valid commands Other control and address bus inputs are 400 mA urrent Seite a i eee switching Data bus inputs are switching All banks open Continuous burst writes BL 4 CL 5 tcx Operating Burst lon4W AL 0 tras 70 ms CKE is HIGH CS is HIGH between valid 1200 mA Write Current RD commands Address bus inputs are switching Data bus inputs are switching All banks open Continuous burst reads lout 0 mA BL 4 CL 5 tck AL 0 tras 70 ms CKE is HIGH CS is HIGH Operating Burst Read Current IpodR between valid commands Address bus inputs are switching Data 1200 mA bus inputs are switching Burst Refresh Refresh command at every 75 ns CKE is HIGH CS is HIGH c lpp5 between valid commands Other control and address bus inputs 1400 mA urrent Peas P ara are
12. switching Data bus inputs are switching Self Refresh loo6 CK and CK at 0 V CKE lt 0 2 V Other control and address bus 80 A Current ae inputs are floating Data bus inputs are floating a All bank interleaving reads lout 0 mA BL 4 CL 5 tex es akah Sah loo AL 70 ns taro 7 5 ns CKE is HIGH CS is HIGH between adage ea valid commands Address bus inputs are stable during deselects Data bus inputs are switching Current Notes For all lbbX measurements tck 3 ns tre 60 ns trep 15 ns tras 45 ns and trp 15 ns unless otherwise specified All currents are based on DRAM absolute maximum values Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 6 DTM63372 DATARAM 1GB 128Mx64 240 Pin Unbuffered non ECC DDR2 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tac 450 450 ps CAS io CAS Command Delay tceco 2 tck Clock High Level Width tcH 0 45 0 55 tck Clock Cycle Time tck 3000 8000 ps Clock Low Level Width teL 0 45 0 55 tck Data Input Hold Time after DQS Strobe toH 175 ps DQ Input Pulse Width toipw 0 35 tck DQS Output Access Time from Clock toasck 400 400 ps Write DQS High Level Width toasH 0 35 tox Write DQS Low Level Width toast 0 35 tok DQS Out Edge to Data Out Edge Skew toasa 240 ps Data Input Set
13. tRC and Byte 42 tRFC ns Add this value to byte 41 Add this value to byte 42 lee Minimum Active to Active Auto Refresh Time 0x3C lee Ba Dace Minimum Auto Refresh to Active Auto Ox7F Refresh Command Period tRFC SDRAM Device Maximum Cycle Time tCK max ns 880 d ah Dev DQS DQ Skew for DQS amp DQ signals DOSA 0x18 fea SDRAM Device Read Data Hold Skew Factor tQHS 0 34 0x22 ns 46 PLL Relock Time us UNUSED 47 DRAM maximun Case Temperature Delta Degree C 0x51 DT4R4W Delta Bits 0 3 Tcasemax delta Bits 7 4 ad ese Resistance of DRAM Package from Top Case to oe Ambient Psi T A DRAM C Watt 49 DRAM Case Temperature Rise from Ambient due to Activate Precharge Mode Bits DTO Mode Bits Degree C Bit 0 If 0 DRAM does not support high temperature self refresh entry Bit 1 If 0 Do not need double refresh rate for the proper operation DTO Bits 2 7 50 DRAM Case Temperature Rise from Ambient due to 0x3C Precharge Quiet Standby DT2N DT2Q Degree C 51 DRAM Case Temperature Rise from Ambient due to 0x60 Precharge Power Down DT2P Degree C 52 DRAM Case Temperature Rise from Ambient due to Active Ox2E Standby DT3N Degree C DRAM Case temperature Rise from Ambient due to Active 0x58 Power Down with Fast PDN Exit DT3Pfast Degree C 54 DRAM Case temperature Rise from Ambient due to Active Power Down with Slow PDN Exit DT3Pslow
14. tage referenced to V 0 V PARAMETER Symbol Minimum Maximum Unit Note DC Input Signal Voltage Vinc 0 300 Voo 0 300 V 1 DC Differential Input Voltage Vipioc 0 250 Voo 0 600 V 2 AC Differential Input Voltage Vinac 0 500 Vpp 0 600 V 3 AC Differential Cross Point Voltage Vixac 0 50 Vpb 0 175 0 50 VDD 0 175 V 4 Notes 1 Vinoc specifies the allowable DC excursion of each input of a differential pair 2 Vipo specifies the input differential voltage i e the absolute value of the difference between the two voltages of a differential pair 3 Viac Specifies the input differential voltage required for switching 4 The typical value of Vixiac is expected to be 0 5 Voo and is expected to track variations in Vpp Capacitance T 25 C f 100 MHz Input Capacitance Clock CKO CKO CK1 CK1 CK2 CK2 cNi 6 12 pF Input Capacitance Address BA 2 0 A 13 0 SO RAS CAS ME and Control CKEO ODTO Cna 18 ee pF Input Output Capacitance DQ 63 0 DQS 7 0 DQS 7 0 DMI7 0 co 6 8 pF DC Characteristics Ta 0 to 70 C Voltage referenced to Vss 0 V PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address lu 80 80 yA 1 Input Leakage Current S 1 0 CKE 1 0 lu 40 40 JA 1 ODT 1 0 Input Leakage Current CK 2 0 CK 2 0 lu 30 30 JA 1 Input Leakage Current DM lu 10 10 yA 1 Output Leakage Current DQS
15. up Time Before DQS Strobe tos 100 ps DQS Falling Edge from Clock Hold Time tosH 0 2 tck DQS Falling Edge to Clock Setup Time toss 0 2 tck Clock Half Period tue minimum of tcy or teL ns Address and Command Hold Time after Clock tih 275 ps Address and Command Setup Time before Clock tis 200 ps Load Mode Command Cycle Time tMRD 2 tck DQ to DQS Hold ton tup tans Data Hold Skew Factor tans 400 ps Active to Precharge Time tras 45 70K ns Active to Active Auto Refresh Time tre 60 ns RAS to CAS Delay trop 15 ns Average Periodic Refresh Interval REFI 7 8 us Auto Refresh Row Cycle Time tRFC 127 5 ns Row Precharge Time tre 15 ns Read DQS Preamble Time RPRE 0 9 1 1 tox Read DQS Postamble Time test 0 4 0 6 tck Row Active to Row Active Delay RRD 7 5 ns Internal Read to Precharge Command Delay tRTP 7 5 ns Write DQS Preamble Setup Time twPRE 0 35 ps Write DQS Postamble Time twest 0 4 0 6 tox Write Recovery Time twr 15 ns Internal Write to Read Command Delay twTR 7 5 ns Exit Self Refresh to Non Read Command txsnr trec min 10 ns Exit Self Refresh to Read Command txsrp 200 tck Document 06504 Revision A 10 Feb 09 Dataram Corporation 2009 Page 7 DTM63372 JAVA ANUT 1GB 128mx64 240 Pin Unbuffered non ECC DDR2 DIMM SERIAL PRESENCE DETECT MATRIX Function Value a iman i Module Attributes Number of Ranks Package and Height of Ranks Card on Card No DRAM Package
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