Dataram DTM65526C memory module
Contents
1. 65526 Optimizing Value and Performance NN Features 240 pin JEDEC compliant DIMM 133 35 mm wide by 30 35 mm high Data Transfer Rate 5 3 Gigabytes sec Operating Voltage VDD 1 8 V 0 1 VCC 1 5V 0 1 SMBus interface to AMB for configuration register access MBIST and IBIST test functions Transparent mode for DDR2 SDRAM test support Full DIMM Heat Spreader High speed differential point to point link Fully RoHS Compliant Pin Configurations Front side Back side 1 GB 240 Pin DDR2 FB DIMM Identification DTM65526C 128Mx72 1GB 1Rx8 PC2 5300F 555 11 BO Performance range Clock Module Speed CL tncp trp 333MHz DDR2 667 5 5 5 267MHz DDR2 533 4 4 4 200MHz DDR2 400 3 3 3 d iud are Description The DTM65526C is a Single Rank PC2 5300 Fully Buffered 128MX72 ECC DIMM that conforms to the JEDEC FB DIMM standard The rank is comprised of nine Samsung 128Mx8 DDR2 DRAMs One IDT Rev C1 Advanced Memory Buffer AMB is used as the interface between the system memory bus and DIMM DRAMs One 2K bit EEPROM is used for Serial Presence Detect For improved thermal performance a Full DIMM Heat Spreader with thermal interface material TIM is attached to the front and back of the DIMM Pin Names Pin Names Function 1 VDD 31 PN3 61 PN9 91 PS9 121 VDD 151 VDD 32 62 VSS 92 VSS 122 VDD 152 3 VDD2. oer 15 _ Manufacturer s JEDECID Code Tor 116 AMB Manufacturer s Code oss 117 Module 10 Module Manufacturers JEDECID Code 118 Module 10 Module Manufacturers JEDEC ID Code Joor 119 Module 10 Module Manufacturing Location Joo 20 121 Module 1D Module Manufacturing Location Joo H22 125 ModueiD ModueSeralNumber foo 126 Cycical Redundancy Code O 427 OyicaRedundanyCode CRO Jor 7728 137 Module Part Number 1832 ModdePartNumer O O o Joa 186 ModdePartNumber O R Jo 189 Module Partnumber O Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 16 sri DTM65526C Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM 40 Moue Panom _ o 086 141 142 143 M4 ModlePatNumer M5 ModiePatNumber O O o 146 147 148 149 150 175 176 255 _ M H Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 17 65526 4 Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM IMI DATARAM 4 Optimizing Value and Performance DATARAM CORPORATION USA Corporate Headquarters P O Box 7528 Princeton NJ 08543 7528 Voice 609 799 0071 Fax
3. but they are not necessarily tested on each device and they may be Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 11 65526 Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM AC Operating Conditions AC operating conditions unless otherwise noted Min Max Symbol Unit Note Value Value DQ Input Pulse Width toipw 0 35 CLK Read DQS Preamble Time 0 9 1 1 CLK Read DQS Postamble Time trest 0 4 0 6 CLK Write DQS Preamble Hold Time twPRE 0 35 CLK Write DQS Postamble Time twPsT 0 4 0 6 CLK Mode Register Set Delay tMRD 2 CLK Exit Self Refresh to Non Read Command txsnr tRFC 10 ns Exit Self Refresh to Read Command 200 CLK 7 8 us Average Periodic Refresh Interval 3 9 Hs 2 NOTES 1 For0C lt Tease 5 85 C 2 For 85 lt Tcase 5 95 C Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 12 DTM65526C Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM SERIAL PRESENCE DETECT MATRIX Function Number of Serial PD Bytes Written SPD Device Size CRC Coverage Bit 3 Bit 0 SPD Bytes Used Bit 6 Bit 4 SPD Bytes Total Bit 7 CRC Coverage Bytes 0 116 8E co o NI X 2 Key Byte DRAM Device Type DDR2 FBDIMM Ox 3 Voltage Levels of this Assembly eo x N Bit 3
4. 008 123 00 4 843 Back view Side view 7 493 Max 0 295 Max w heatsprdr 4 00 Min 0 157 Min DEDE 1 27 10 4 0 0500 0 0040 Notes Tolerances on all dimensions except where otherwise indicated are 13 005 All dimensions are expressed millimeters inches p ean i Page 2 Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 150 DMO DQSO 19050 DQ 7 0 DM1 DQS1 DQS1 DQ 15 8 DM2 0952 10992 DQ 23 16 DM3 DQS3 DQS3 DQ 31 24 DM8 Dass DQS8 CB 7 0 PNO PN13 Optimizing Value and Performance DP DATARAM DTM65526C 1 GB 240 Pin DDR2 FB DIMM e i 0 e 668 8 a a c VO 7 0 0 4 e 6 T g VO 7 0 8 o s c 7 0 o d a a a Ns c VO 7 0 EE o N N o a a m c VO 7 0 PNO PN13 PSO PS9 50 59 DQ0 DQ63 CBO CB7 DQS0 DQS8 DQS0 DQS8 DMO DM8 w gt SCL SDA SA1 SA2 SAO RESET SCK amp SCK SNO SN13 SNO SN13 550 559 SS0 SS9 180 gt CS all SDRAMs CKEO g
5. 182 VSS 212 VSS PN PN 13 0 Primary Northbound Data 183 SN10 213 SS5 PS PS 9 0 Primary Southbound Data 184 SN10 214 SS5 SN SN 13 0 Secondary Northbound Data 185 VSS 215 VSS SS SS 9 0 Secondary Southbound Data 186 SN11 216 556 SCL Serial Clock EEPROM 187 SN11 217 SS6 SDA Serial Data EEPROM 188 VSS 218 VSS RESET AMB Reset Signal 189 VSS 219 SS7 vec AMB Core Power and AMB Channel 190 SSO 220 SS7 Interface Power 1 5 V 191 SSO 221 VSS USE DRAM Power and AMB DRAM 192 VSS 222 SS8 Power 1 8 V 193 SS1 223 SS8 VTT DRAM Address Command Clock 194 SS1 224 VSS Termination Power VDD 2 195 VSS 225 RFU2 VDDSPD SPD Power 196 SS2 226 RFU2 VSS Ground 197 SS2 227 VSS RFU Reserved For Future Use 198 VSS 228 SCK DNU Do Not Use 199 SS3 229 5 M_TEST Margin Test 200 SS3 230 VSS SA 2 0 Serial Address EEPROM 201 VSS 231 VDD 202 SS4 232 VDD 203 SS4 233 VDD 204 VSS 234 VSS 205 VSS 235 VDD 206 RFU1 236 VDD 207 RFU1 237 208 VSS 238 VDDSPD 209 VSS 239 SAO 210 SS9 240 SA1 Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 1 65526 Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM Front view 133 35 i 5 250 9 50 I Ms 0 374 n 4 95 EN k 17 30 1 0 681 Y 0 197 2 50 Min 518 67 00 51 00 0 098 Min 0 204 2 638 2
6. 33 VSS 63 PN10 93 PS5 123 VDD 153 4 VSS 34 64 PN10 94 PS5 124 VSS 154 5 VDD 35 PN4 65 VSS 95 VSS 125 VDD 155 6 VDD 36 VSS 66 PN11 96 PS6 126 VDD 156 7 VDD 37 PN5 67 11 97 PS6 127 VDD 157 8 VSS 38 PN5 68 VSS 98 VSS 128 VSS 158 9 VCC 39 VSS 69 VSS 99 PS7 129 VCC 159 10 VCC 40 PN13 70 50 100 PS7 130 VCC 160 11 VSS 41 PN13 71 PSO 101 VSS 131 VSS 161 12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 13 VCC 43 VSS 73 PS1 103 PS8 133 VCC 163 14 VSS 44 RFU 74 PS1 104 VSS 134 VSS 164 15 VTT 45 RFU 75 VSS 105 RFU2 135 VTT 165 16 VID1 46 VSS 76 PS2 106 RFU2 136 VIDO 166 17 RESET 47 VSS 77 PS2 107 VSS 137 M TEST 167 18 VSS 48 PN12 78 VSS 108 VDD 138 VSS 168 19 RFU2 49 PN12 79 PS3 109 VDD 139 RFU2 169 20 RFU2 50 VSS 80 PS3 110 VSS 140 RFU2 170 21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 22 PNO 52 PN6 82 PS4 112 VDD 142 SNO 172 23 53 VSS 83 54 113 VDD 143 SNO 173 24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 25 PN1 55 7 85 VSS 115 SN1 175 26 PN1 56 VSS 86 RFU1 116 VDD 146 SN1 176 27 VSS 57 PN8 87 RFU1 117 VTT 147 VSS 177 28 PN2 58 PN8 amp 88 VSS 118 SA2 148 SN2 178 29 PN2 59 VSS 89 VSS 119 SDA 149 SN2 179 30 VSS 60 PN9 90 PS9 120 SCL 150 VSS 180 22 lt S555S55 a NOTE M_TEST is not used SN3 ISN3 VSS SN4 ISN4 VSS SN5 18 5 VSS SN13 SN13 VSS VSS RFU1 RFU1 VSS VSS SN12 SN12 VSS SN6 SN6 VSS SN7 ISN7 VSS SN8 ISN8 VSS SN9 181 SN9 211 SS9 SCK SCK System Clock Input
7. Bit 0 Power Supply 1 Bit 7 Bit 4 Power Supply 2 4 SDRAM Addressing Bit 1 0 Number of Banks Bit 5 Bit 3 Column Address Bits Bit 7 Bit 5 Row Address Bits 5 Module Physical Attributes Bit 3 Bit 0 Module Thickness mm 7 lt lt 8 0 Bit 4 Bit 2 Module Height mm 30 lt x lt 35 Bit 7 6 Reserved 0 Module Type Bit 3 Bit 0 Module Type FB DIMM Bit 7 Bit 4 Reserved 7 Module Organization Bit 3 Bit SDRAM Device Width Bit 5 Bit 3 Number of Ranks Bit 7 6 Reserved Fine Timebase Dividend Divisor Bit 3 Bit 0 Fine Timebase Dividend Bit 7 Bit 4 Fine Timebase FTB Divisor 0 9 Medium Timebase Dividend 0 oxo 00 12 Maximum Cycle Time tCKmax SDRAM CAS Latencies Supported Bit 3 Bit 0 Minimum CL clocks Bit 7 Bit 4 CL Range clocks 14 SDRAM Minimum CAS Latency Time tAAmin Ox3C SDRAM Write Recovery Times Supported Bit 3 Bit 0 Minimum WR clocks Bit 7 Bit 4 WR Range clocks 16 SDRAM Write Recovery Time tWR Ox3C 17 SDRAM Write Latencies Supported Bit 3 Bit 0 Minimum WL clocks Bit 7 Bit 4 WL Range clocks 18 SDRAM Additive Latencies Supported 0x40 X eo o x T Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 13 65526 Optimizi
8. at the package pins into a timing and voltage compliance test load Common mode measurements to be performed using a 101010 pattern 2 This is the ratio of the VTX DIFFp p of the second and following bits after a transition divided by the VTx DIFFp p of the first bit after a transition 3 De emphasis is disabled in the calibration state 4 Includes all sources of AC common mode noise 5 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition 6 Specified at the package pins into a voltage compliance test load Transmitters must meet both single ended and differential output E1 specifications 7 This specification considered with Vnx ipLE se pc implies a maximum 15mV single ended DC offset between Tx and Rx pins during the electrical idle condition This in turn allows a ground offset between adjacent FB DIMM agents of 26mV when worst case termination resistance matching is considered 8 The maximum value is specified to be at least VTX DIFFp p L 4 L VTX CM ACp p 2 9 This number does not include the effects of SSC or reference clock jitter 10 These timing specifications apply to resync mode only 11 Defined as the dual dirac deterministic jitter as described in Section 4 of the JEDEC FB DIMM High Speed Differential PTP Link Draft Spec rev 0 8 12 Pulse width measured at OV differential 13 The termination small signal resistance t
9. 2 Data DRAM ODT Disabled Bit 3 Bit 2 Rank 2 Ecc DRAM ODT Disabled Bit 5 Bit 4 Rank Data DRAM ODT Disabled Bit 7 Bit 6 Rank 3 Ecc DRAM ODT Disabled FBD ODT Definition for Rank 0 and 1 Bit 1 BitO Rank 0 Data DRAM ODT 150 Ohms Bit 3 Bit 2 Rank 0 Ecc DRAM ODT Disabled Bit 5 Bit4 Rank 1 Data DRAM ODT Disabled Bit 7 Bit6 Rank 1 Ecc DRAM ODT Disabled UNUSED Channel Protocols Supported Least Significant Byte Bit 0 DDR2 Base Non ECC Protocol 0 Supported Bit 1 DDR2 Base ECC Protocol 1 Supported Bit 7 Bit 2 TBD 0 Channel Protocols Supported Most Significant Byte UNUSED 0x00 Back to back Turnaround Cycles Bit 1 Bit 0 Rank Read to Read 0 add l clock Bit 3 Bit 2 Write to Read add l clock Bit 5 Bit 4 Read to Write 1 add l clock Bit 7 Bit 6 TBD 0 AMB Read Access Time for DDR2 800 AMB LINKPARNXT 1 0 11 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK AMB Read Access Time for DDR2 667 AMB LINKPARNXT 1 0 10 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity OK AMB Read Access Time for DDR2 533 AMB LINKPARNXT 1 0 01 Bit 3 Bit 0 Read Access Fine Granularity UI Bit 7 Bit 4 Read Access Coarse Granularity tCK Thermal Resistance of AMB Package from Top Case to Ambient Psi AMB C W ANE Case Temper
10. 5 mV Single ended voltage w r t VSS on D D VRX SE 4 300 900 mV Single pulse peak differential input voltage VRX DIFF PULSE 4 6 85 mV Amplitude ratio between adjacent symbols VRX DIFF ADJ e 3 1100mV VRX DIFFp p lt 1300mV RATIO HI 4 7 Amplitude ratio between adjacent symbols VRX DIFF ADJ 4 VRX DIFFp p lt 1100 RATIO 4 7 Maximum RX inherent timing error 3 2 and 4 Gb s TRX TJ MAX 4 8 9 0 4 UI Maximum RX inherent deterministic timing error 3 2 and 4 TRX DJ DD 4 8 9 10 m 0 3 Ul Gb s Single pulse width at zero voltage crossing TRX PW ZC 4 6 0 55 UI Single pulse width at minimum level crossing TRX PW ML 4 6 0 2 Ul input rise fall time given by 20 80 voltage TRX RISE TRX FALL 50 _ ps 5 Common mode of the input voltage VRX CM 1 11 120 400 mV Defined as VRX CM DC avg of VRX D VRX D 2 AC peak to peak common mode of input voltage VRX CM VRX CM ACp p 1 DP 270 mV AC Max VRX D VRX D 2 Min VRX D VRX D 2 Ratio of VRX CM ACp p to minimum VRX DIFFp p VRX CM EH Ratio 12 __ 45 Differential return loss RLRX DIFF 9 dB Measured over 0 1 GHz to 2 4GHz Common mode return loss RLRX CM 6 dB Measured over 0 1 GHz to 2 4GHz RX termination resistance RRX 13 41 55 Q D D RX resistance difference RRX Match DC 4 RRX Match DC 2 RRX D RRX D RRX D RRX D Lane to lane PCB skew at RX LRX PCB SKEW 14 6 Ul Lane to Lane PCB skew at the Receiver th
11. 5 to 100 C 1 Voltage on any pin relative to Vss Vin Vout 0 3 to 1 75 V 1 Voltage on Vcc relative to Vss Vcc 0 3 to 1 75 V 1 Voltage on Vpp relative to Vss 0 5 to 2 3 V 1 Voltage on relative to Vss Vit 0 5 to 2 3 V 1 Power Dissipation Pp 21 1 NOTES 1 Operation at or above absolute maximum rating can adversely affect device reliability 2 For85C lt 5 95 C 3 9 us max DC Operating Conditions Ta 0 to 70 C Voltage referenced to Vss OV Parameter Symbol Minimum Typical Maximum Unit Note AMB Supply Voltage Vcc 1 425 1 5 1 59 V DDR2 Supply Voltage 1 7 1 8 1 9 V Termination Voltage Vit 0 48 x VDD 0 50 x 0 52 x VDD V EEPROM Supply Voltage SPD VppsPD 3 0 3 3 3 6 V Input High Voltage SPD Vinc 2 1 VppsPD V 1 Input Low Voltage SPD 1 0 V 1 Input High Voltage RESET BFUNC 1 0 V 2 Input Low Voltage RESET BFUNC 0 5 V 1 Leakage Curent RESET BFUNC IL 90 90 pA 2 Leakage Curent Link I 5 5 Notes 1 Applies to SMB and SPD bus signals 2 Applies to AMB CMOS signal RESET Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 4 65526 Optimizing Value and Performance Differential Transmitter Output Specification 1 GB 240 Pin DDR2 FB DIMM Parameter Symbol MIN MAX Uni
12. 609 799 6734 www dataram com All rights reserved The information contained in this document has been carefully checked and is believed to be reliable However Dataram assumes no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Dataram No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without prior written consent of Dataram Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 18
13. ESAMPLE 0 9 1 4 ns 1 Resync Delay 7 8 9 tRESYNC 2 3 2 ns 2 NOTES 1 tRESAMPLE is the delay from the southbound input to the southbound output or the northbound input to the northbound output when in resample mode measured from the center of the data eye 2 tRESYNC is the delay from the southbound input to the southbound output or the northbound input to the northbound output when in resync mode measured from the center of the data eye p BN NR Mc Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 9 DTM65526C Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM AMB Power Specification Ta 0 to 70 C Voltage referenced to Vss OV Parameter i Power Symbol Test Condition Supply Value Unit Idle Single or last FBDIMM LO state idle O BW primary channel 1 5V 2600 Current IDLE secondary channel disabled CKE high command and mA address lines stable DDR2 SDRAM clock active 1 8V 700 Idle First FBDIMM LO state idle 0 BW primary and secondary 1 5V 3400 Current IDD IDLE 1 channels enabled CKE high command and address lines mA stable DDR2 SDRAM clock active 1 8 V 700 TDP BW Single or Last DIMM LO State TDP Channel 45V 3000 Active IDD TDP 0 BW 2 4GB s 667 67 READ 3396 WRITE primary channel mA Power enabled
14. Precharge Write Recovery Precharge Time toa twn nes 7 us System Clock Cycle Time tck 3000 8000 ps Clock High Level Width 0 48 0 52 CLK Clock Low Level Width teL 0 48 0 52 CLK DQ output access time from CK amp CK tac 0 450 0 450 ns DQS Out edge to Clock Edge skew tpasck 0 400 0 400 ns DQS Out edge to Data out edge skew 0 240 ns Data Out hold time from DQS tau tup taus ns 1 Data hold skew factor tous 0 340 ns 1 Clock Half Period tup min tcu ns 1 Input Setup Time fast slew rate tis 0 200 ns 2 3 5 6 Input Hold Time fast slew rate 0 275 ns 2 3 5 6 Input Pulse Width tiew 0 6 CLK 6 Write DQS High Level Width tpasH 0 35 CLK Write DQS Low Level Width 0 35 CLK CLK to First Rising edge to DQS In tposs 0 25 0 25 CLK Data In Setup Time to DQS In DQ amp DM tps 0 100 ns Data In Hold Time to DQS In DQ amp DM 0 175 ns NOTES 1 This calculation accounts for tposo max the pulse width distortion of on chip and jitter 2 3 For command address input slew rate gt 1 0V ns 4 For command address input slew rate gt 0 5V ns and 1 0V ns 5 CK CK slew rates gt 1 0V ns 6 guaranteed by design or tester correlation T Data latched at both rising and falling edges of Data Strobes DQS Data sampled at the rising edges of the clock AO A13 BAO BA2 S 1 0 RAS CAS WE These Parameters guarantee device timing
15. at must be tolerated Minimum RX Drift Tolerance TRX DRIFT 15 400 ps Minimum data tracking 3dB bandwidth FTRK 16 0 2 2 MHz Electrical idle entry detect time a 60 ns Electrical idle exit detect time TEI EXIT DETECT as 30 ns Bit Error Ratio BER 18 10 Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 7 DIM65526C 4 Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM NOTES FOR RECEIVER INPUT SPECIFICATIONS 1 Specified at the package pins into a timing and voltage compliant test setup Note that signal levels at the pad are lower than at the pin 2 Single ended voltages below that value that are simultaneously detected on D and D are interpreted as the Electrical Idle condition Worst case margins are determined by comparing EI levels with common mode levels during normal operation for the case with transmitter using small voltage swing see RX Single ended Electrical Idle Levels and RX Common Mode Levels 3 Multiple lanes need to detect the El condition before the device can act upon the EI detection 4 Specified at the package pins into a timing and voltage compliance test setup 5 This specification considered with VTx IDLE SE Dc implies a maximum 15mV single ended DC offset between TX and RX pins during the electrical idle condition This in turn allows a ground offset between adjacent FB DIMM of 26mV when worstcase termination
16. ature Rise from Ambient due to AMB in Idle_0 State DT AMB Idle 0 C oO T Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 15 sr Ata DTM65526C Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM AMB Case Temperature Rise from Ambient due to AMB in Idle 1 107 0x6B State DT AMB 1 C Case Temperature Rise from Ambient due to AMB in Idle 2 92 0x5C State DT AMB Idle 2 C 91 AMB Case Temperature Rise from Ambient due to AMB in Active 1 145 0x91 State DT AMB Active 1 92 AMB Case Temperature Rise from Ambient due to AMB in Active 2 118 0x76 State DT AMB Active 2 C 93 AMB Case Temperature Rise from Ambient due to AMB in LOs UNUSED 0x00 State DT AMB LOs C 98 __ Junction Temperature Maximum Tmax 1 OxiF 99 0x04 101 AVBPersonallyBytesPredmWalzaon Joo 102 AMBPersonallyByes Preimiaigalon Joe 103 AMB Personality Bytes Pre intiaization oez 104 AMBPersonallyByes Preinaizaon Jo 105 AMB Personality Bytes Pre nitalizaton Jos 106 _ Personality Bytes Pre iniiaization Joo 7107 108 AMB Personality Bytes Postinitalization Joo 109 Personality Bytes Postinitializaton Jom 110 Personality Bytes Postinitializaton Jom 111 114 AMB Personality Bytes Postinitalization
17. his number represents the lane to lane skew between TX and RX pins and does not include the transmitter output skew from the component driving the signal to the receiver This is one component of the end to end channel skew in the AMB specification 15 Measured from the reference clock edge to the center of the input eye This specification is met across specified voltage and temperature ranges Drift rate of change is significantly below the tracking capability of the receiver 16 This bandwidth number assumes the specified minimum data transition density Maximum jitter at 0 2MHz is 0 05UI 17 The specified time includes the time required to forward the El entry condition 18 BER per differential lane Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 8 DTM65526C Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM Advanced Memory Buffer FBD Timing Electrical Parameter Symbol MIN MAX Units El Assertion Pass Through Timing PROPAGATE 4 CLKs El Deassertion Pass Through Timing tEID tBitlock CLKs El Assertion Duration tEl 100 CLKs Bit Lock Interval tBITLOCK 119 Frames Frame Lock Interval tFRAMELOCK 154 Frames Advanced Memory Buffer Latency Parameters Parameter Symbol MIN MAX Units Notes CMD2DATA 0x40 Data Rate 667 tC2D AMB 16 2 19 ns CMD2DATA 0x46 Data Rate 667 tC2D AMB 17 7 20 5 ns Resample Delay 6 tR
18. ition DC only Mr 20 mV Maximum peak to peak differential voltage in El condition VTX IDLE DIFFp p 6 _ 40 mV Single ended voltage w r t VSS on D D VTX SE 1 7 75 750 mV Minimum TX eye width 3 2 and 4 Gb s TTX Eye MIN 1 9 10 0 7 en Ul Maximum TX deterministic jitter 3 2 and 4 Gb s TTX DJ DD 1 9 10 11 S 0 2 Ul Instantaneous pulse width TTX PULSE 12 0 85 Ul Differential TX output rise fall time TTX RISE TTX 30 90 ps Given by 2096 8096 voltage levels FALL 1 Mismatch between rise and fall times TTX RF MISMATCH 20 ps Differential return loss RLTX DIFF 8 Measured over 0 1 GHz to 2 4GHz Common mode return loss RLTX CM 6 dB Measured over 0 1 GHz to 2 4GHz Transmitter termination resistance RTX 13 41 55 Q D D TX resistance difference RTX Match DC 4 RTX Match DC 2 RTX D RTX D RTX D RTX D Bounds are applied separately to high and low output voltage states Lane to lane skew at TX LTX SKEW 1 14 16 100 3UI ps Lane to lane skew at TX LTX SKEW 2 15 16 100 2UI ps TTX DRIFT 240 s Maximum TX Drift resync mode RESYNC 17 p TTX DRIFT 120 s Maximum TX Drift resample mode only RESAMPLE 17 p Bit Error Ratio BER 18 107 Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 5 65526 ZB Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM NOTES FOR TRANSMITTER OUTPUT SPECIFICATIONS 1 Specified
19. ng Value and Performance 1 GB 240 Pin DDR2 FB DIMM Bit 3 Bit 0 Minimum AL clocks 0 Bit 7 Bit 4 AL Range clocks 4 19 SDRAM Minimum RAS to CAS Delay tRCD 20 SDRAM Minimum Row Active to Row Active Delay tRRD 21 Minimum Row Precharge Time tRP 22 SDRAM Upper Nibbles for tRAS and 0x00 Bit 3 Bit 0 tRAS Most Significant Nibble Bit 7 Bit 4 tRC Most Significant Nibble 23 SDRAM Minimum Active to Precharge Time tRAS 24 SDRAM Minimum Active to Active Refresh Time tRC OxFO 25 SDRAM Minimum Refresh Recovery Time Delay tRFC LSB 127 5ns OxFE 26 SDRAM Minimum Refresh Recovery Time Delay tRFC MSB 127 5ns 0x01 27 SDRAM Minimum Internal Write to Read Command Delay tWTR Ox1E 28 SDRAM Minimum Internal Read to Precharge Command Delay 7 5ns Ox1E tRTP 29 SDRAM Burst Lengths Supported 0x03 Bit 0 BL 4 Bit 1 BL 8 Bit 6 Bit 2 TBD Bit 7 Burst Chop 30 SDRAM Terminations Supported 0x07 Bit 0 150 ohms ODT Bit 1 75 ohms ODT Bit 2 50 ohms ODT Bit 6 Bit 3 TBD 31 SDRAM Drivers Supported 0x01 Bit 0 Weak Driver Bit 7 Bit 1 TBD 32 SDRAM Average Refresh Interval Double Refresh mode bit High Temperature 0xC2 self refresh rate support indication Bit 0 Bit 3 Average Refresh Interval uS 7 8 Bit 5 Bit 4 TBD 0 Bit 6 High Temperature Self Ref
20. olerance across voltages from 100mV to 400mV shall not exceed 5 with regard to the average of the values measured at 100mV and at 400mv for that pin 14 Lane to Lane skew at the Transmitter pins for an end component 15 Lane to Lane skew at the Transmitter pins for an intermediate component assuming zero Lane to Lane skew at the Receiver pins of the incoming PORT 16 This is a static skew A FB DIMM component is not allowed to change its lane to lane phase relationship after initialization 17 Measured from the reference clock edge to the center of the output eye This specification is met across specified voltage and temperature ranges for a single component Drift rate of change is significantly below the tracking capability of the receiver 18 BER per differential lane For a complete definition of Bit Error Ratio refer to JEDEC s Compliance Methodology section Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 6 Optimizing Value and Performance Differential Receiver Input Specification DIM65526C 1 GB 240 Pin DDR2 FB DIMM Parameter Symbol MIN MAX Units Differential peak to peak input voltage VRX DIFFp p_L 1 170 1300 mV VRX DIFFp p 2 VRX D VRX D Maximum single ended voltage for El condition DC AC VRX IDLE SE 2 3 4 65 mV Maximum single ended voltage for El condition DC only EEA 4 3
21. resh 1 Required Bit 7 Double Refresh Requirement 1 Supported 33 Tcasemax Delta Bit 3 Bit 0 DTARAW Delta Subfield B 0 4 C Bit 7 Bit 4 Tcasemax Subfield A 2 C 34 Thermal Resistance of SDRAM Package C W 61 35 SDRAM Case Temperature Rise from Ambient due to Activate Precharge minus 2 8 0x50 offset temperature DTO C Bit 1 Bit 0 Reserved Bit 7 Bit 2 DTO 36 SDRAM Case Temperature Rise from Ambient due to 4 7 Ox2F Precharge Quiet Standby DT2N DT2Q C 37 SDRAM Case Temperature Rise from Ambient due to Precharge 0 585 0x27 Power Down DT2P C Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 14 65526 Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM Case Temperature Rise from Ambient due to Active Standby DT3N 39 SDRAM Case Temperature Rise from Ambient due to Page Open Burst Read DT4R4W Mode Bit DTAR DTARAW Mode Bit Bit 0 DTARAW Mode Bit Subfield B 0 4 C Bit 7 Bit 1 DT4R Subfield A 0 4 C SDRAM Case Temperature Rise from Ambient due to Burst 18 5 0x25 Refresh DT5B C SDRAM Case Temperature Rise from Ambient due to Bank 0x28 4274 Reseed Reads with Auto Precharge DT7 C aR 1 E 776 OR ODT contol Tor Rank O and rark T Reads andwites 000 ard 000000 86 FBD ODT Definition for Rank 2 and 3 Bit 1 BitO Rank
22. resistance matching is considered 6 The single pulse mask provides sufficient symbol energy for reliable RX reception Each symbol complies with both the single pulse mask and the cumulative eye mask see RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Early and RX Single Pulse Min Width and Amplitude Mask Pulse Shifted Late 7 The relative amplitude ratio limit between adjacent symbols prevents excessive inter symbol interference in the Rx Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent symbols see RX Maximum Adjacent Symbol Amplitude 8 This number does not include the effects of SSC or reference clock jitter 9 This number includes setup and hold of the RX sampling flop 10 Defined as the dual dirac deterministic timing error as described in Section 4 2 2 of the JEDEC FB DIMM High Speed Differential Link Draft Spec rev 0 8 11 Allows for 15mV DC offset between transmit and receive devices 12 The received differential signal satisfies both this ratio as well as the absolute maximum AC peak to peak common mode specification For example if VRX DIFFp p is 200mV the maximum AC peak to peak common mode is the lesser of 200 mV 0 45 90mV and VRX CM ACp p 13 The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed 5 with regard to the average of the values measured at 100mV and at 400mvV for that pin 14 T
23. secondary channel disabled CKE high command and 48V 1300 address lines stable DDR2 SDRAM clock active TDP BW First DIMM LO State TDP Channel Active IDD TDP 1 BW 2 4GB s 667 DIMM BW 1 6GB s 667 67 READ 33 WRITE primary channel enabled secondary channel enabled mA CKE high command and address lines stable DDR2 SDRAM 1 8V 1000 clock active IDD TRAINING Primary and secondary channels enabled 100 toggle on all 1 5V 4000 Training E channel lanes DDR2 SDRAM devices idle 0 BW CKE HIGH mA command and address lines stable DDR2 SDRAM clock active 1 8V 0 7 p H CHEER Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 10 2 DTM65526C 1 GB 240 Pin DDR2 FB DIMM Optimizing Value and Performance DRAM AC Characteristics AC operating conditions unless otherwise noted Parameter Symbol in i Unit Note Value Value Row Cycle Time 60 ns Auto Refresh Row Cycle Time 127 5 ns Row Active Time tras 45 70K ns Row Address to Column Address Delay trop 15 ns Row Active to row Active Delay tRRD 7 5 ns Column Address to Column Address Delay tccp 2 CLK Row Precharge time trp 15 ns Write Recovery Time twr 15 ns Auto
24. t CKE all SDRAMs ODT gt ODT all SDRAMs 2 all SDRAMs 15 all SDRAMs RAS all SDRAMs ICAS all SDRAMs ME all SDRAMs 8 all SDRAMs There are two physical copies of each address command control clock DM4 12054 0 4 DQ 39 33 o DM5 10095 O 4 DQ 47 40 0 4 DM6 O 10086 00 55 48 0 4 DM7 10097 0 4 DQ 63 56 SCL DQS4 o o g a a E VO 7 0 a pass 0 4 c VO 7 0 2 DQS6 0 4 N N T c VO 7 0 DQS7 N 8888 a a a VO 7 0 8 gt SDA SPD WP zm du SAO SA1 SA2 All address command control clock A Vit VTT VCC VDDSPD VDD VREF vss HH Terminators AMB SPD AMB SDRAMS AMB SDRAMS SDRAMS SPD AMB Document 06027 Revision A 29 Sep 08 Dataram Corporation 2010 Page 3 2 DTM65526C Optimizing Value and Performance 1 GB 240 Pin DDR2 FB DIMM Absolute Maximum Ratings Parameter Symbol Rating Unit Note Temperature DDR2 DRAM Case Tcase 0 to 95 C 1 2 Temperature Storage Tsrc 5
25. ts Differential peak to peak output voltage for large voltage VTX DIFFp p L 1 900 1300 mV swing VTX DIFFp p 72 VTX D VTX D Differential peak to peak output voltage for regular voltage VTX DIFFp p_R 1 800 mV swing VTX DIFFp p 2 VTX D VTX D Differential peak to peak output voltage for small voltage VTX DIFFp p_S 1 520 mV swing VTX DIFFp p 2 VTX D VTX D DC common code output voltage for large voltage swing VTX CM_L 1 375 mV Defined as VTX CM DC avg of VTX D VTX D 2 DC common mode output voltage for small voltage swing VTX CM S 1 135 280 mV Defined as VTX CM DC avg of VTX D VTX D 2 De emphasized differential output voltage ratio for 3 5 dB VTX DE 3 5 3 4 de emphasis Ratio 1 2 3 De emphasized differential output voltage ratio for 6 dB de VTX DE 6 Ratio 1 2 3 7 emphasis AC peak to peak common mode output voltage for large VTX CM ACp p L 1 4 RES 90 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX VTX D 2 AC peak to peak common mode output voltage for regular VTX CM ACp p R 1 4 _ 80 swing VTX CM AC VTX D VTX D 2 Min VTX VTX D 2 AC peak to peak common mode output voltage for small VTX CM ACp p S 1 4 _ 70 mV swing VTX CM AC Max VTX D VTX D 2 Min VTX VTX D 2 Maximum single ended voltage in El condition AC VTX IDLE SE 5 6 50 Maximum single ended voltage in El cond
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