Intel Atom Z670
Contents
1. an memes 25 Table 4 4 Voltage and Current Specifications 26 Table 4 5 Differential Clock DC 28 Table 4 6 AGTL CMOS and CMOS Open Drain Signal Group DC Specifications 28 Table 4 7 CMOS1 8 Signal Group DC 29 Table 4 8 LVDS Signal Group DC 29 Table 5 1 Thermal Design Power Specifications 31 Table 5 2 Support for PROCHOT THERMTRIP in Active and Idle States 34 Table 6 1 Processor Pinout Top View Columns 21 31 40 Table 6 2 Processor Pinout Top View Columns 11 20 41 Table 6 3 Processor Pinout Top View Columns 1 10 42 Table 6 4 Pinout Ordered by Signal 43 Datasheet Revision History Document Revision Description Number Number 325314 001 e Initial release Datasheet Revision Date April 2011 intel Introduction 1 1 1 Introduction The datasheet describes the architecture features buffers signal descriptions power management pin stat2. TI 7 91910191919191919191919 WE WE D Datasheet e Package Mechanical Specifications and Pin I nformation intel 6 2 Processor Pinout Assignment Table 6 1 Table 6 2 and Table 6 3 are graphic representations of the processor pinout assignments Table 6 4 lists the pinout by signal name Datasheet 39 tel Table 6 1 Proce CDVO TXDP WR DATAPO LA DATANO DATANO LA CLKN LA DATAP2 LA VBG gt 1 _ LA_CLKP gt LA_DATAN2 LA IBG AD RSVD gt 4 gt lt a zZz 3 lt lt Vecaso SM DQO SM DQ2 SM DQ1 SM DQ3 SM 0051 G SM_DQ9 w 40 Package Mechanical Specifications and Pin Information ssor Pinout Top View Columns 21 31 CDVO_TXST cavo CVRE CDVO TXST CDVO_TX4 TXO 8 evens T CDVO 7X5 CDMI_RXCH MPO CDVO_TX1 LA_DATAN3 Vecaiso LA DATAP3 Vecais RSVD9 Tis 1 SM_MA4 SM MA12 SM 590 SM MA3 SM DQ8 SM 0010 SM 0050 SM 0012 SM 0011 p sM DM1 SM MA10 E SM MAT SM DQ14 5 20 5 _0013 NI 23 CDVO RCO CDVO VBLA NK CDVO_RCO MP1 Vss Vss Vss Vss Vss Vss Vss Vss SM DQ15 23 CDMI RXSTB _EVEN CDMI RXSTB _ODD Vss
3. Symbol Parameter Min Typ Max Unit Notes Tj Junction Temperature 0 90 C HD Streaming Scenario Power 1 02 z W 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The is not the maximum theoretical power the processor can generate 2 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 31 intel Thermal Specifications and Design Considerations 5 1 5 2 32 3 Scenario Power examines a common use case may be more indicative of a more common power usage level as compared with the TDP Measurement configuration assumes LCD brightness 100nits LCD 1024x800 10 1 USB touch panel I C sensors SDIO WiFi on 2GB DDR2 7396 PMIC efficiency 9396 discrete VR efficiency Flash v10 2 4 720p YouTube Temperature Monitoring The processor incorporates two methods of monitoring die temperature e By Intel Thermal Monitor e By Digital Thermal Sensor DTS The Intel Thermal Monitor detailed in Section 5 2 must be used to determine when the maximum specified processor junction temperature has been reached Intel Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC Thermal Control Circuit when the processor silicon reaches its maximum operating temperature The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable Bu
4. TXSTB O CDMI TXSTB ODD Data strobe output Strobes for CDMI TX 7 0 and CDMI TXSTB EVEN Mos CDMI_TXCHAR Data input Quad Pump strobed data bus from PCH to com ale GMoS Intel Atom Processor Z670 Data control character input Quad pump strobed RXCHAR indication that CDMI RX 7 0 contains a control character CMOS instead of data Line wakeup for input Power enable from PCH Used to CDMI_RXDPWR CMOS enable Receivers on CDMI RX 7 0 CDMI RXCHAR and CDMI RXSTB ODD CDMI_RXSTB_ODD Data strobe input Strobes for CDMI_RX 7 0 CDMI_RXSTB_EVEN CMOS CDMI_RXCHAR Strobe Signals Reference Voltage for DMI Externally CDMI_GVREF Analo set by means of a passive voltage divider Voltage should be 9 1 2 when configured for CMOS Non Strobe Signals Reference Voltage for DMI CDMI_CVREF Ansa Externally set by means of a passive voltage divider 9 Voltage should be 1 2 VCCP when configured for CMOS 2 1 3 cDVO Interface Table 2 5 cDVO Interface Signals Direction CDVO_RCOMP Connected to high precision resistors on the motherboard Used for compensating pull up pull down impedances Data output Quad pump strobed data bus from Intel cDvo_TX 5 0 AGTL Atom Processor 2670 to PCH Datasheet 13 CDVO RCOMP 1 0 An NG intel Signal Descriptions CDVO_STALL T Stall Allows PCH to throttle the sending of display data Line wakeup for output When ass
5. E De SLP de asserted N DPSLP de asserted N DPRSTP de asserted Sleep STPCLK de asserted Snoop Snoop serviced occurs T Deeper Sleep includes the C4 and C6 states tt Sleep and Deep Sleep are not states directly supported by the processor but rather sub states of Silverthorne s C4 C6 19 Power Management 3 1 1 Cx State Definitions 20 State Full On This is the only state that runs software All clocks are running and the processor core is active The processor can service snoops and maintain cache coherency in this state All power management for interfaces clock gating are controlled at the unit level C1 State Auto Halt The first level of power reduction occurs when the core processor executes an Auto Halt instruction This stops the execution of the instruction stream and greatly reduces the core processor s power consumption The core processor can service snoops and maintain cache coherency in this state The Processor North Complex logic does not distinguish C1 from CO explicitly C2 State Stop Grant The next level of power reduction occurs when the core processor is placed into the Stop Grant state The core processor can service snoops and maintain cache coherency in this state The North Complex only supports receiving a single Stop Grant Entry into the C2 state will occur after the core processor requests C2 or deeper C2 state will be exited entering the
6. Not C4 C4E Ignored Optional Inactive Active Guaranteed Active C6 Ignored Optional Inactive Active Inactive Active 5 2 1 34 Digital Thermal Sensor The processor also contains an on die Digital Thermal Sensor DTS that is read using an MSR no 1 0 interface The processor has a unique digital thermal sensor that s temperature is accessible using the processor MSRs The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation using the Thermal Monitor The DTS is only valid while the processor is in the normal operating state the Normal package level low power state Datasheet e Thermal Specifications and Design Considerations intel 5 2 2 5 2 3 5 2 4 Datasheet Unlike traditional thermal devices the DTS outputs a temperature relative to the maximum supported operating temperature of the processor T max It is the responsibility of software to convert the relative temperature to an absolute temperature The temperature returned by the DTS will always be at or below T max Catastrophic temperature conditions are detectable using an Out of Specification status bit This bit is also part of the DTS MSR When this bit is set the processor is operating out of specification and immediate shutdown of the sy
7. Vcce Rcome Compensation resistor 27 73 27 5 27 78 Q 10 Ropt Termination resistor 55 Q 11 Vin GTL Input high voltage GTL signal GTLREF Voce Vccp V 3 6 0 10 0 10 Vit GTL Input low voltage GTL signal 0 10 0 GTLREF V 2 4 0 10 Vin CMOS Input high voltage CMOS signal CMREF Vecp Vece V 3 6 0 10 0 10 Vit CMOS Input low voltage CMOS signal 0 10 0 CMREF V 2 4 0 10 Output high voltage Vecp Vecp Vccp V 6 0 10 GTL Termination resistance 46 55 61 Q 7 Rr CMOS Termination resistance 46 55 61 Q 11 Ron GTL GTL buffer on resistance 21 25 29 Q 5 Ron CMOS CMOS buffer on resistance 42 50 55 Q 12 Ron CMOS common clock buffer on 42 50 58 Q 12 CMOS_C resistance lu Input leakage current 100 8 Crap Pad capacitance 1 6 2 1 2 55 pF 9 28 Datasheet Electrical Specifications NOTES 10 11 12 intel Unless otherwise noted all specifications in this table apply to all processor frequencies VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value VIH and VOH may experience excursions above VCCP However input signal drivers must comply with the signal quality specifications RON is the pull down driver resistance Refer to processor I O Buffer Models for I V characteristics Measured at 0 33 VCCP GTLREF and CMR
8. internal display of e 1366 x 768 18 bpp and 60 fps e Dot clock range from 20 83 MHz e Four differential signal pairs Three data pairs up to 581 Mbps on each data link and one clock pair e Supports 18 bpp packed and 18 bpp loosely packed pixel formats e Supports 24 bpp with a limited number of validated panels 1 3 Terminolog 8 Datasheet Introduction 1 4 Datasheet LVDS Low Voltage Differential Signaling a high speed low power data transmission standard used for display connections to LCD panels Model specific register NCTF Non Critical to Function NCTF locations are typically redundant ground or non critical reserved so the loss of solder joint continuity at end of life conditions will not affect the overall product functionality Non maskable interrupt North Processor unicore which processor memory controller Power Management Complex Unit and internal FSB Logic E On Die Termination Platform Controller Hub O Ema meme O Dm a Reference Documents Document Location Comments Intel Atom Processor Z6xx Series Specification Update For the 325309 001 Intel Atom Processor Z670 on 45 nm Process Technology Intel SM35 Express Chipset Datasheet 325308 001 Intel SM35 Express Chipset Specification Update 325307 001 http www intel com AP 485 Intel Processor Identification and the CPUID Instruction Assets PDF appnote 2 41618 pdf 9 Introduct
9. CO state when a break event is detected Processor must ensure that the DLLs are awake and the memory will be out of self refresh at this point C1E and C2E States and C2E states are transparent to the north complex logic The state is the same as the C1 state in that the core processor emits a HALT cycle when entering the state There are no other visible actions from the core processor The C2E state is the same as the C2 state in that the core processor emits a Stop Grant cycle when entering the state There are no other visible actions from the core processor C4 State Deeper Sleep In this state the core processor shuts down its PLL and cannot handle snoop requests The core processor voltage regulator is also told to reduce the processor s voltage During the C4 state the North Complex will continue to handle traffic to memory so long as this traffic does not require a snoop i e no coherent traffic requests are serviced The C4 state is entered by receiving a C4 request from the core processor OS The exit from C4 occurs when the North Complex detects a snoopable event or a break event which would cause it to wake up the core processor and initiate the CO sequence Datasheet Power Management intel Datasheet CAE The CAE state is essentially the same as the C4 state except that the core processor will transition to the Low Frequency Mode LFM frequency and voltage upon entry and exit of this st
10. Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Enhanced Halt State Typical AVID range is 0 70V to 1 15V for Vcc and 0 75V to 0 95V for Vin This specification corresponds to what value gets driven by the processor It is possible for firmware to override these values Voltage specification of 2 includes and DC variations The sum of AC noise and DC variations should not exceed 1 05V 29 Specified at the nominal Vcc Peak Sustained Current is defined as the maximum sustainable current measured as an RMS value over ius 27 i n tel Electrical Specifications 8 This is the sum of current on both rails 9 Specification based on LVDS panel configuration of 1024x600 resolution 60Hz refresh rate and 18bpp color depth Table 4 5 Differential Clock DC Specifications Symbol Parameter Min Typ Max Unit Notes Differential Clock BCLK Vin Input high voltage 1 15 Vit Input low voltage 0 3 Vcnoss Crossing voltage 0 3 0 55 AV cross Range of crossing points B 140 mv VswiNG Differential output swing 300 x mV lu Input leakage current 5 5 Crap Pad capacitance 1 2 1 45 2 0 pF Table 4 6 AGTL CMOS and CMOS Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes GTLREF GTL reference voltage 2 3 V Vecp CMREF CMOS reference voltage 1 2 B V
11. experience excursions above However input signal drivers must comply with the signal quality specifications LVDS Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes Vos Offset voltage 1 125 1 25 1 375 V AVos Change in offset voltage 50 mV Vop Differential output voltage 250 350 450 mV 29 30 Electrical Specifications Symbol Parameter Min Typ Max Unit Notes AVop Change in differential output 50 mv voltage Isc Short circuit current 12 mA Iscc Short circuit comment current 24 mA Leakage current 380 150 380 Dynamic offset B 150 mV Overshoot 50 70 90 mV Ringback 50 70 90 mV NOTE Unless otherwise noted all specifications in this table apply to all processor frequencies Datasheet e Thermal Specifications and Design Considerations intel 5 Note Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Table 4 3 Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system Maintaining the proper thermal environment is the key to reliable long term system operation A complete thermal solution includes both component and system level thermal management features Tradin
12. 10 Pin Information 10 1 xj ct Tm es ES ct Te r ct se Cel BEC e e e o e e 2 c e e KO o sos an sese v 0 eo o ToS pe IS E eem e seme sew sour 42 9 8 7 6 5 4 3 2 Datasheet Package Mechanical Specifications and Pin nformation Table 6 4 Datasheet Pinout Ordered by Signal Name Pin Name Pin Pin Name Pin Pin Name Pin BCLK P M2 CDMI_TXSTB_EVEN AK10 TP6 Y30 BCLK N N1 CDVO CVREF AL25 TP8 U30 BPMO AH9 CDVO_TXDPWR AK30 TP10 T30 BPM1 AL4 CDVO_GVREF AF20 TP3 AB31 BPM2 AL5 CDVO_RCOMPO AK24 TP5 AA31 BPM3 AK4 CDVO 1 AH23 TP7 V31 BSEL1 G4 CDVO_STALL AH27 TP9 T31 CVREF AL17 CDVO TXO AK27 RSVD8 Y28 RXDPWR 20 CDVO_TX1 AH24 PRDY AL7 CDMI_TXDPWR AL15 CDVO_TX2 AL28 PREQ AK6 CDMI_GVREF AK16 CDVO_TX3 AL29 PROCHOT AF1 CDMI_RCOMPO AK9 CDVO 4 AK28 PWRMODEO 1 1 AL8 CDVO_TX5 AH26 PWRMODE1 AE2 AK17 CDVO TXSTB ODD AL27 PWRMODE2 AD2 CDMI RX1 AL18 CDVO TXSTB EVEN AK26 SM ODT1 D8 RX2 AH17 CDVO VBLANK AK
13. 23 SM ODTO D9 RX3 AK19 GTLREFO AK7 RSVD7 E2 CDMI RX4 AL19 GTLREF1 D4 SM_BSO D26 CDMI_RX5 AH19 IERR AH10 SM_BS1 G28 CDMI_RX6 AL21 LA_CLKN AG30 SM_BS2 128 CDMI_RX7 AK20 LA_CLKP AH31 SM_CAS E4 CDMI_RXCHAR AL24 LA_DATANO AJ 30 SM_CKO D19 CDMI RXSTB ODD AK22 LA 1 AG28 SM_CKO D18 CDMI RXSTB EVEN 122 LA DATAN2 AF31 SM CKEO A19 CDMI TXO AH13 LA DATAN3 AF28 SM_CKE1 17 CDMI_TX1 AL11 LA_DATAPO AJ31 SM CS0 D5 TX2 AK12 LA DATAPI 28 SM_CS1 D7 CDMI_TX3 AL12 LA_DATAP2 AF30 SM DMO F30 TX4 AK13 LA DATAP3 AD28 SM DM1 A27 5 14 LA IBG AE31 SM DM2 B4 TX6 AL14 LA VBG AD30 SM DM3 A10 CDMI TX7 AK14 TP1 W30 SM DQO J30 CDMI_TXCHAR AH16 TP2 W31 SM DQ1 31 CDMI TXSTB ODD 19 TP4 AA30 SM DQ10 B28 43 44 Package Mechanical Specifications and Pin Information Pin Name Pin Pin Name Pin Pin Name Pin SM 0011 A29 SM MA2 F28 RSVD AG2 SM DQ12 B25 SM MA3 D25 RSVD AG4 SM_DQ13 A24 SM_MA4 D29 RSVD AH7 SM DQ14 B24 SM MA5 A16 THERMTRI P AE4 SM DQ15 A23 SM MA6 B18 TMS J2 SM DQ16 A6 SM MA7 D24 TRST 11 SM DQ17 B7 SM MA8 D22 AA10 SM_DQ18 A4 SM MA9 A20 AA12 SM_DQ19 B5 SM_MA10 A26 14 SM_DQ2 G30 SM MA11 B15 AA16 SM_DQ20 C1 SM MA12 D28 AA18 SM DQ21 B2 SM MA13 A14 VCC AA2 SM_DQ22 D1 SM_MA14 D14 VCC AA20 SM_D
14. 5 5 2 4 PROCHOT Signal eere GAGA GA HERR ERR ee ences 35 Tables Package Mechanical Specifications and Pin nformation 37 6 1 Package Mechanical Specifications 37 6 2 Processor Pinout 5510 ee eee eee eee nee 39 Figure 3 1 Thread Low Power 19 Figure 3 2 Package Low Power States 19 Figure 6 1 Package Mechanical Drawing sss emm 38 Table 2 1 Signal Typ6s uer ER 11 Table 2 2 Buffer TYPES ka aan ANG APA 11 Table 2 3 System Memory Interface Signals 11 Table 2 4 cDMI Interface 5 10 13 Table 2 5 cDVO Interface 510 anan GN ANAN ANAKAN ANAK 13 Table 2 6 LVDS Display Port Interface 14 Table 2 7 LGI LGle Legacy 510 5 neers 15 Table 2 8 Debug and Miscellaneous Signals 16 Table 2 9 Power Signals cor Gani evden ee E EE RE Rid x 17 Table 4 T VIDEN Encoding Kaka E entre kein expe Maha 23 4 2 VID jo PEE 24 Table 4 3 Absolute Maximum 0
15. 5 VSS AH29 VSS C26 VSS AC17 VSS AJ11 VSS C27 VSS 19 VSS AJ12 VSS C29 VSS AC21 VSS AJ14 VSS C3 VSS AC22 VSS AJ15 VSS C30 VSS AC25 VSS AJ 17 VSS C6 VSS AC3 VSS 18 vss C7 VSS AC9 vss AJ19 VSS C9 46 Datasheet Package Mechanical Specifications and Pin nformation Datasheet Pin Name Pin Pin Name Pin Pin Name Pin VSS D3 VSS K25 VSS T23 vss E12 vss K3 vss T28 VSS E14 VSS K9 VSS T8 VSS E18 VSS M11 VSS T9 VSS E20 VSS M13 VSS V11 VSS E24 VSS M15 VSS V13 VSS E26 VSS M17 VSS V15 VSS E29 VSS M19 VSS V17 VSS E6 VSS M21 VSS V19 VSS E8 VSS M23 VSS V2 VSS F3 VSS M3 VSS V21 VSS G11 VSS M8 VSS V23 VSS G13 VSS M9 VSS V29 VSS G15 VSS N3 VSS V4 VSS G17 VSS N7 VSS V8 VSS G19 VSS P11 VSS V9 VSS G21 VSS P13 VSS W29 VSS G23 VSS P15 VSS Y1 VSS G25 VSS P17 VSS Y11 VSS G29 VSS P19 VSS Y13 VSS G3 VSS P21 VSS Y15 VSS G5 VSS P23 VSS Y17 VSS G7 VSS P29 VSS Y19 VSS G9 VSS P3 VSS Y21 VSS H29 VSS P31 VSS Y23 VSS J29 VSS P8 VSS VSS J3 VSS P9 VSS Y6 VSS J4 VSS R2 VSS Y8 VSS K12 VSS R4 VSS Y9 VSS K13 VSS T11 VSS G1 VSS K14 VSS T13 VSSSENSE V6 vss K18 VSS T15 VSS K19 VSS T17 VSS K20 VSS T19 VSS K24 VSS T21 47
16. CDMI_RX6 Vcco 2 a a a S z Zo v G lt lt A m gt Vccpoor SM MA8 SM MAO 5 5 C 20 O an m o ZI S 2 1 c a 1 lt Datasheet Package Mechanical Specifications and Pin nformation Table 6 2 Processor Pinout Top View Columns 11 20 15 COMI aa CDMI TX6 COMITX7 ma 2 CDMI TX5 CDMI 20 UNE AG Vss x of R N rc amp Vccieo a wo Vss lt N 5 _ 9 Datasheet 19 CDMI_RX4 CDMI RX3 Vss CDMI RX5 Vss Vss Vss Vss Vss Vss Vss Vss Vss SM Vss SM RCOMP SM CKEO 19 18 CDMI RX1 Vccieo Vccieo _ 0 SM_MA6 CDMI_RX2 CDMI_GVREF mw TXCHA Veciso Veciso RSVD SM_MA14 SM_SREN SM SM DQ25 SM CKEl SM MAS SM MA13 SM DQ24 SM DQ26 17 16 15 14 13 12 11 SM RAS SM DQ27 SM WE SM DQS3 41 AL AK C lt lt m n cC T gt intel Package Mechanical Specifications and Table 6 3 Processor Pinout Top View Columns 1
17. EF should be generated from VCCP with a 196 tolerance resistor divider The VCCP referred to in these specifications is the instantaneous VCCP RTT is the on die termination resistance measured at VOL of the AGTL output driver Measured at 0 33 VCCP RTT is connected on die Refer to processor I O buffer models for I V characteristics Specified with on die RTT and RON are turned off VIN between 0 and VCCP CPAD includes die capacitance only No package parasitics are included This is the external resistor on the component pins On die termination resistance for CMOS is measured at 0 5 VCCP RON for CMOS pull down driver resistance Refer to processor O Buffer Models for I V characteristics Measured at 0 5 Vccp Table 4 7 CMOS1 8 Signal Group DC Specifications Table 4 8 Datasheet Symbol Parameter Min Typ Max Unit Notes Vin Input high voltage Vcciso 2 1 9 V 0 125 Vit Input low voltage 0 4 Veciso 2 V 0 125 Output high voltage 1 2 V 0 25 VoL Output low voltage Vcc180 2 V 0 25 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vu is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 Vin is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 Vi and may
18. Electrical Specifications sch essow 1 1125V 0 7125V 4 5 Absolute Maximum Ratings Table 4 3 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Table 4 3 Absolute Maximum Ratings eer n Vcc Processor core supply voltage core Processor core supply voltage voltage ve poo Complex
19. G RCOMP and power gating supply voltage Needed for most bus accesses Cannot be connected to Vcecpaoac during Standby or Self Refresh states V DDR DLL and logic supply voltage Required for memory bus accesses Requires a separate rail with noise isolation J TAG C6 SRAM supply voltage Needs to be on in Active or VccPAOAC PWR Standby N LVDS band gap supply voltage Needed for LVDS display M Vecp HPLL Analog PLL and thermal sensor supply voltage V LVDS analog supply voltage Needed for LVDS display Requires a di separate rail with noise isolation LVDS 1 O supply voltage Needed for LVDS display V DDR2 self refresh supply voltage Powered during Active GETBOSR Standby and Self Refresh states DDR2 1 O supply voltage Required for memory bus accesses Veciso Cannot be connected to Vccisosr during Standby or Self Refresh states 1 supply voltage vs PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Datasheet 17 3 1 18 Power Management Power Management Processor supports fine grain power management by having several partitions of voltage islands created through on die power switches The Intel Smart Power Technology Intel SPT software determines the most power efficient state for the platform at any given point in time and then provides guidance to turn ON or OFF different voltage islands on processor For the scenario where Intel SPT has directe
20. Gle Legacy 19 5 ee 15 2 1 6 Debug and Miscellaneous 16 2 1 7 asser 17 Power Management nanana ann NANANA BANNA un 18 3 1 Processor Core Low Power Features 18 3 1 1 Cx State Definitions 20 Electrical Specifications 22 4 1 Power and Ground Balls eere ise tee vi e A eda 22 4 2 Decoupling Guidelines sss memes 22 4 3 Voltage Rail Decoupling memes 22 4 4 Voltage Identification 10 eene nnns 23 4 4 1 VID Enable ER X 23 4 4 2 MIR 24 4 5 Absolute Maximum Ratings sss eee 25 4 6 DC Specificatioris i erbe dr dba E EE DRE ERR ru 26 Thermal Specifications and Design Considerations eee 31 5 1 Temperature Monitoring sss enemies 32 5 2 Intel Thermal 32 5 2 1 Digital Thermal 34 5 2 2 Out of Specification Detection mme 35 5 2 3 Catastrophic Thermal Protection 3
21. Intel Atom Processor Z6xx Series Datasheet For the Intel Atom Processor Z670 on 45 nm Process Technology April 2011 Revision 001 Document Number 325310 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this informa
22. Q23 D2 SM_RAS D12 AA22 SM_DQ24 1 SM_RCOMP B19 4 SM_DQ25 B14 SM_RCVENIN B21 AA7 SM_DQ26 12 SM_RCVENOUT B22 AA8 SM_DQ27 B12 SM_SREN B16 1 SM_DQ28 A9 SM WE D11 SM_DQ29 B9 TCK H2 U1 SM_DQ3 H31 TDI F1 010 SM_DQ30 A7 TDO H4 012 SM_DQ31 B8 RSVD D15 U14 SM_DQ4 D31 RSVD G2 VCC U16 SM_DQ5 E31 RSVD L2 VCC U18 SM_DQ6 C31 RSVD L4 U2 SM_DQ7 B31 RSVD KI VCC U20 SM DQ8 B29 RSVD M4 VCC U22 SM DQ9 A30 RSVD M1 VCC U24 SM_DQSO B26 RSVD P2 U3 SM_DQS1 G31 RSVD P4 U4 SM_DQS2 B3 RSVD U28 U7 SM_DQS3 B11 RSVD W28 VCC U8 SM_MAO D21 RSVD AK3 W1 SM MAI A21 RSVD AG1 W10 Datasheet Package Mechanical Specifications and Pin nformation Datasheet Pin Name Pin Pin Name Pin Pin Name Pin W12 VCCA T6 VIDO AH2 W14 VCCA180 AD24 VID1 AJ1 W16 VCCA180 AF24 VID2 AH4 W18 VCCD180 AD26 VID3 AH3 W2 VCCD180 AF26 VID4 AK2 VCC W20 VCCP K7 VID5 AH6 W22 VCCP AC28 VID6 AL2 W24 VCCP AC5 VIDENO AD4 W3 VCCP AD10 VIDEN1 AD1 W4 VCCP AD14 RSVD9 AA24 VCC W7 VCCP AD16 VNN AA26 VCC W8 VCCP AD20 VNN AD12 VCC180 F12 VCCP AD22 VNN AD18 VCC180 F14 VCCP AD8 VNN AD6 VCC180 F18 VCCP AF10 VNN AF12 VCC180 F20 VCCP AF14 VNN AF18 VCC180 F24 VCCP AF16 VNN AF6 VCC180 F26 VCCP AF22
23. S 01 VID Vec 10 VI D 11 RSVD Catastrophic Thermal Trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating O temperature to ensure that there are no false trips The THERMTRIPZ CMOS OD processor will stop all execution when the junction temperature exceeds approximately 120 C This condition is signaled to the system by the THERMTRI P Thermal Trip pin Processor hot As an output PROCHOT processor hot will go active when the processor temperature monitoring 1 0 sensor detects that the processor has reached its maximum O safe operating temperature This indicates that the processor PROCHOT CMOS OD Thermal Control Circuit TCC has been activated if enabled l CMOS As an input assertion of PROCHOT by the system will activate the TCC if enabled The TCC will remain active until the system de asserts PROCHOT VSSSENSE Voltage sense Connects to PMIC Voltage Regulator must VCCSENSE Analog connect feedback lines for Vcc Vss and Vin to these pins on VNNSENSE the package BSEL1 Selects external reference clock for DDR2 cDMI and cDVO frequencies BSEL1 CMOS 1 Reserved 0 100 MHz for cDVO DDR2 800MT s I ERR Internal error indication debug Positively asserted Asserted when the processor has had an internal error and may have unexpectedly stopped executing Assertion of IERR IERR is usually ac
24. This signal provides the clock CMOS input for the processor Test Bus also known as the Test Access Port Requires an external 51 resistor to Vss Processor JTAG test data input This signal transfers serial test data into the processor TDI provides the serial CMOS input needed for J TAG specification support Requires an external 51 resistor to Vccp Processor JTAG test data output This signal transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support Requires an external 51 resistor to Vccp Processor J TAG test mode select A J TAG specification CMOS support signal used by debug tools Requires an external 51 resistor to Vccp Processor JTAG test reset Asynchronously resets the Test Access Port TAP logic TRST must be driven asserted low during processor power on reset Processor has an internal 51 Q pull up to unlike the Pentium M processor the Intel Core 2 processor and the Intel Atom Z5xx processor The Processor pull up matches the Intel Pentium 4 processor and the IEEE specification These pins should be treated as no connection NC 16 Datasheet Signal Descriptions intel 2 1 7 Power Signals Table 2 9 Power Signals Processor core supply voltage Power supply is required for processor cycles M Vw North Complex logic and graphics supply voltage cDMI cDVO LGI LGle JTA
25. VNN L26 VCC180 F8 VCCP AF8 VNN M25 VCC180 H12 VCCP F6 VNN M29 VCC180 H14 VCCP H6 VNN M31 VCC180 H18 VCCP M6 VNN N10 VCC180 H20 VCCQ 1 AH12 VNN N12 VCC180 H24 VCCQ 2 AH22 VNN N14 VCC180 H26 VCCPAOAC ABA VNN N16 VCC180 H8 VCCPAOAC AA28 VNN N18 VCC180 K28 VCCPAOAC K5 VNN N20 VCC180 K30 VCCPAOAC P1 VNN N22 VCC180 L29 VCCPDDR F10 VNN N24 VCC180 L31 VCCPDDR F16 VNN N26 VCC180 M28 VCCPDDR F22 VNN N28 VCC180 M30 VCCPDDR H10 VNN N30 VCC180SR D16 VCCPDDR H16 VNN N8 VCCA P6 VCCPDDR H22 VNN 25 VCCA TI VCCSENSE T3 VNN P28 45 Package Mechanical Specifications and Pin Information Pin Name Pin Pin Name Pin Pin Name Pin VNN P30 vss AC30 vss AJ2 VNN R10 VSS AD29 VSS AJ21 VNN R12 VSS AD3 VSS AJ22 VNN R14 VSS AD31 VSS AJ24 VNN R16 VSS AE11 VSS 25 R18 vss AE13 VSS 27 R20 vss AE15 vss 29 VNN R22 vss AE17 VSS AJ4 VNN R24 VSS AE19 VSS 5 R26 vss AE21 vss 7 R29 vss AE23 VSS AJ8 VNN R31 VSS AE25 VSS AJ9 VNN R7 VSS AE29 VSS AL1 VNN R8 VSS AE5 VSS AL30 VNN T25 VSS AE7 VSS AL31 VNN U26 VSS AE9 VSS Bl VNN V25 VSS AF29 VSS C10 VNN W26 VSS AF3 VSS C12 VNN Y25 VSS AG10 VSS C13 VNNSENSE T29 VSS AG14 VSS C14 VSS A2 VSS AG16 VSS C16 VSS A31 VSS AG20 VSS C17 VSS AA29 VSS AG22 VSS C19 VSS AB2 VSS AG26 VSS C20 VSS AB29 VSS AG3 VSS C21 VSS 11 VSS AG5 VSS C23 VSS AC13 VSS AG8 VSS C24 VSS AC1
26. assertion of PROCHOT PROCHOT will not be asserted when the processor is in the Sleep Deep Sleep and Deeper Sleep low power states see Figure 3 2 If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification the system must initiate an orderly shutdown to prevent damage If the processor enters one of the above low power states with PROCHOT already asserted then PROCHOTZ will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point If the Intel Thermal Monitor automatic mode is disabled the processor will operate out of specification Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a potentially catastrophic temperature At this point the THERMTRI P2 signal will go active THERMTRIP activation is independent of processor activity and does not generate any bus cycles Table 5 2 Support for PROCHOT THERMTRI P in Active and Idle States PROCHOT Bidirectional THERMTRI P System Core Input Output State North North North Core Complex Core Complex Core Complex CO Supported Optional Active Active Active Active 1 1 Supported Optional Active Active Active Active C2 C2E Supported Optional Active Active Active Active
27. ate C6 Deep Power Down Prior to entering the C6 state the core processor will flush its cache and save its core context to a special on die SRAM on a different power plane Once the C6 entry sequence has completed the core processor s voltage can be completely shut off The key difference for the North Complex logic between the C4 state and the C6 state is that since the core processor s cache is empty there is no need to perform snoops on the internal FSB This means that bus master events which would cause a popup from the C4 state to the C2 state can be allowed to flow unimpeded during the C6 state However the core processor must still be returned to the CO state to service interrupts A residency counter is read by the core processor to enable an intelligent promotion demotion based on energy awareness of transitions and history of residencies transitions 21 n tel Electrical Specifications 4 4 1 4 2 Caution 4 3 22 Electrical Specifications This chapter contains signal group descriptions absolute maximum ratings voltage identification and power sequencing This chapter also includes DC specifications Power and Ground Balls The processor has Vcc and Vss ground inputs for on chip power distribution All power balls must be connected to their respective processor power planes while all Vss balls must be connected to the system ground plane Use of multiple power and ground planes is recommend
28. companied by a SHUTDOWN transaction internal CMOS to Processor which may result in assertion of NMI to the processor The processor will keep IERR asserted until the POWERMODE pins take Processor to reset or Processor receives a reset message over cDMI GTLREFO Voltage reference for BPM 3 0 2 3 Vccp by means of an Analog external voltage divider 1k Q to Vccp 2 KQ to Vss GTLREF1 Voltage reference 2 3 Vccp by means of external voltage Analog divider 1 KO to Vcce 2 KO to Vss Datasheet 15 intel Signal Descriptions Direction gap osoa iggen O pesen Power mode The chipset is expected to sequence Processor PWRMODE 2 0 CMOS through various states using the POWERMODE pins to facilitate cold reset and warm reset BCLK_P N CMOS Reference clock Differential 100 MHz 2 1 6 Debug and Miscellaneous Signals Table 2 8 Debug and Miscellaneous Signals Direction MT 1 0 Break perf monitor Various debug input and output Probe mode ready The processor s response to a PRDY 1 0 Maso ug E AGTL assertion This signal indicates that the processor is in probe mode Input is unused Probe mode request Assertion is a request for the 1 0 processor to enter probe mode Processor will respond with AGTL PRDY assertion once it has entered PREQ can be enabled to cause the processor to break from C4 and Internal 51 Q pull up so no external pull up required Processor J TAG test clock
29. d the processor to go into an Intel SIT idle mode the processor waits for all partitions with shared voltage to reach a safe point and then turns them off Processor Core Low Power Features When the processor core is idle low power idle states C states are used to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Figure 3 1 shows the thread low power states Figure 3 2 shows the package low power states Note STPCLK DPSLP and DPRSTP are internal signals only Datasheet Power Management intel Figure 3 1 Thread Low Power States STPCLK STPCLK asserted de asserted STPCLK STPCLK N de asserted STPCLK asserted de asserted STPCLK asserted Gore Siate HLTinstruction LM break MWAIT C1 Halt break P_LVL2 or Core State break Core state P_LVL4 or break P LvLe _ MWAIT C4 C6 halt break A20M transition INITZ INTR NMI PREQ RESET SMI or APIC interrupt core state break halt break OR Monitor event AND STPCLK high not asserted T STPCLK assertion and de assertion have no effect if a core is in C2 or C4 P LVL6 read is issued once the L2 cache is reduced to zero Figure 3 2 Package Low Power States Datasheet SLP asserted DPRSTP asserted STPCLK asserted P di DPSLP asserted Deep Sleep
30. d description of Processor signals The signals are arranged in functional groups according to their associated interface 2 1 1 System Memory Interface Table 2 3 System Memory Interface Signals Direction CMOS1 8 Differential DDR clock 51 8 Complementary differential DDR clock Datasheet 11 12 SM_SREN SM_CKE 1 0 SM_CS 1 0 SM_RAS SM_CAS SM_ODT 1 0 SM_BS 2 0 SM_MA 14 0 SM DQ 31 0 SM DQS 3 0 SM DMI3 0 SM RCVENIN SM RCVENOUT SM RCOMP Direction Type CMOS1 8 O CMOS1 8 CMOS1 8 CMOS1 8 CMOS1 8 O CMOS1 8 51 8 O CMOS1 8 1 0 CMOS1 8 1 0 CMOS1 8 CMOS1 8 CMOS1 8 O CMOS1 8 Analog Signal Descriptions Self refresh enable Signal from the chipset asserted after processor places DDR in self refresh Clock enable SM_CKE is used for power control of the DRAM devices There is one SM_CKE per rank Chip select These signals determine whether a command is valid in a given cycle for the devices connected to it There is one chip select signal for each rank Row address strobe This signal is used with SM_CAS and along with SM_CS to define commands Column address strobe This signal is used with SM WEZ CMOS1 8 SM RAS and SM_CS to define commands SM WE Write enable This signal is used with SM CAS SM_RAS and SM CS to define commands On Die Terminat
31. directional PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP With a properly designed and characterized thermal solution it is anticipated that bi directional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Datasheet e Package Mechanical Specifications and Pin I nformation intel 6 Package Mechanical Specifications and Pin I nformation This chapter describes the package specifications and pinout assignments 6 1 Package Mechanical Specifications The processor will be available in a 518 pin FCMB3 package The package dimensions are shown in Figure 6 1 Datasheet 37 intel Figure 6 1 Package Mechanical Drawing Package Mechanical Specifications and Pin Information 38 COMMENTS
32. e 1 47 1 5 1 53 V Vcca180 VccA180 supply voltage 1 746 1 8 1 854 V Vccp180 Vccp180 supply voltage 1 71 1 8 1 89 V supply voltage 1 71 1 8 1 89 V Veciso supply voltage 1 71 1 8 1 89 V Processor Core Frequency Number 2670 1 5 GHz 2 50 A 67 LFM 0 6 GHz vin Vyn Supply current 1 60 A 7 Vcce supply current 0 121 A 7 lvcco Vcco supply current 0 015 A 7 Supply current 0 150 A 7 Supply current 0 030 A 7 Supply current 0 010 A 7 vccA Vcca Supply current 0 150 A 7 vccaigo Vcca180 supply current xd 0 050 7 8 9 vccp180 1 Supply current A Vccisosr Supply current 0 010 A 7 lvcci80 Vcciso Supply current 0 400 A 7 NOTES 1 Maximum specifications are based on measurements done with currently existing workloads and test conditions These numbers are subject to change 2 Specified at 90 3 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event
33. ed to reduce I R drop The Vcc balls must be supplied with the voltage determined by the processor Voltage Identification VID signals Decoupling Guidelines Due to large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cpuix such as electrolytic capacitors supply current during longer lasting changes in current demand for example coming out of an idle condition Similarly capacitors act as a storage well for current when entering an idle condition from a running condition To keep voltages within specification output decoupling must be properly designed Design the board to ensure that the voltage provided to the processor remains within the specification Failure to do so can result in timing violations or reduced lifetime of the processor Voltage Rail Decoupling The voltage regulator solution needs to provide e Bulk capacitance with low effective series resistance ESR e A low path impedance from the regulator to the processor e Bulk decoupling to compensate for large current swings generated during power on or low power idle state entry exit The power delivery solution must ensure that the voltage and current specifications are met as defined in Table 4 4 Datasheet Electrical Specifica
34. ed using on demand mode If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1 the TCC will be activated immediately independent of the processor temperature When using on demand mode to activate the TCC the duty cycle of the clock modulation is programmable using bits 3 1 of the same ACPI Intel Thermal Monitor control register automatic mode the duty cycle is fixed at 5096 on 5096 off However in on demand mode the duty cycle can be programmed from 12 596 on 87 5 off to 87 596 on 12 5 off in 12 596 increments On demand mode may be used at the same time automatic mode is enabled however if the system tries to enable the TCC using on demand mode at the same time automatic mode is enabled and a high temperature condition exists automatic mode will take precedence 33 intel Thermal Specifications and Design Considerations An external signal PROCHOT processor hot is asserted when the processor detects that its temperature is above the thermal trip point Bus snooping and interrupt latching are also active while the TCC is active Besides the thermal sensor and thermal control circuit the Intel Thermal Monitor also includes one ACPI register one performance counter register three MSRs and one pin PROCHOT All are available to monitor and control the state of the Intel Thermal Monitor feature The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or de
35. elow the critical level the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point The I ntel Thermal Monitor automatic mode and Enhanced Intel SpeedStep Technology must be enabled through A 32 Firmware for the processor to be operating within specifications ntel recommends that TM1 and TM2 be enabled on the processors TM1 and TM2 can co exist within the processor If both TM1 and TM2 bits are enabled in the auto throttle MSR TM2 will take precedence over TM1 However if Force TM1 over TM2 is enabled in MSRs using 1 A 32 Firmware and 2 is not sufficient to cool the processor below the maximum operating temperature then 1 will also activate to help cool down the processor If a processor load based Enhanced Intel SpeedStep Technology transition through MSR write is initiated when a TM2 period is active there are two possible results e fthe processor load based Enhanced Intel SpeedStep Technology transition target frequency is higher than the TM2 transition based target frequency the processor load based transition will be deferred until the TM2 event has been completed e If the processor load based Enhanced Intel SpeedStep Technology transition target frequency is lower than the TM2 transition based target frequency the processor will transition to the processor load based Enhanced Intel SpeedStep Technology target frequency point The may also be activat
36. emperature is applicable to storage conditions only Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications 4 J JSTD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 5 Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by Tsusrainen and customer shelf life in applicable Intel box and bags 4 6 DC Specifications Table 4 4 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 1 2 VccHFM Vcc Q Highest Frequency Mode AVID 1 15 V 3 VccLFM Vcc Lowest Frequency Mode 0 7 AVID V 3 VecBOOT Default Vcc for initial power VccLFM V 4 Va Vyn V 4 Vyn Vyn supply voltage 0 75 0 95 V 3 Vcce supply voltage 0 9975 1 05 1 1025 V 4 Vcco Vcco supply voltage 0 9975 1 05 1 1025 V Vecpppr supply voltage 1 029 1 05 1 071 V 5 26 Datasheet Electrical Specifications Datasheet Symbol Parameter Min Typ Max Unit Notes 1 2 Vecpaoac Vecpaoac supply voltage 0 9975 1 05 1 1025 supply voltage 1 14 1 20 1 26 LVD_VBG LVDS band gap reference 1 225 1 25 1 275 V voltage Veca Vcca Supply voltag
37. erted the PCH will power up its receivers on CDVO TX 5 0 and CDVO TXSTB ODD CDVO TXSTB ODDZ CDVO_TXSTB_EVEN AGTL Data strobe output Strobes for CDVO_TX 5 0 CDVO_TXDPWR AG Vertical blank Indication from PCH indicating the start of ELON the vertical blank period Strobe signals reference voltage for CDVO Externally CDVO_GVREF Analog set by means of a passive voltage divider Voltage should be 2 3 Vcce when configured for GTL Non Strobe Signals Reference Voltage for CDVO CDVO_CVREF Analog Externally set by means of a passive voltage divider Voltage should be 2 3 Vcce when configured for GTL 2 1 4 LVDS Display Port I nterface Table 2 6 LVDS Display Port I nterface Signals om Pel LA CLKP Differential Clock Output Positive LA IBG External Voltage Ref BG Connected to high precision Analog resistor on motherboard to VSS External Voltage Ref BG Requires external 1 25 V 2 LA_VBG Analog supply 14 Datasheet Signal Descriptions inte 2 1 5 LGI LGI e Legacy Signals Table 2 7 LGI LGl e Legacy Signals Direction ati sonar PRR OO o Voltage ID Connects to PMIC Indicates a desired voltage VID 6 0 CMOS for either Vcc or Vy depending on the VIDEN pins Resolution of 12 5 mV Voltage I D enable Connects to PMIC Indicates which voltage is being specified on the VID pins 00 VID is invalid VIDEN 1 0 CMO
38. es operating parameters and specifications for the Intel Atom Processor 2670 Core Processor and North Complex Intel Atom Processor Z670 is the next generation low power A 32 processor that is based on the new re partitioning architecture targeted for tablets and sleek netbooks The main components of Intel Atom Processor 2670 are an IA compatible processor core derived from the Intel Atom processor a single channel 32 bit DDR2 memory controller a 3 D graphics engine video decode engines a 2 D display controller a cDMI interface link to the Intel SM35 Express Chipset and an LVDS interface to support a primary display interface link An additional cDVO interface is used for pixel data to the Intel SM35 Express Chipset Throughout this document the Intel Atom Processor Z670 is referred as the processor and Intel SM35 Express Chipset is referred to as the chipset Processor Features The following list provides some of the key features on this processor e Supports Intel Hyper Threading Technology e 2 wide instruction decode and in order execution e 512 KB 8 way L2 cache e Support for IA 32 bit architecture e FCMB3 packaging technology e Thermal management support using TM1 and TM2 e On die Digital Thermal Sensor DTS for thermal management support using Intel Thermal Monitor 1 TM1 and Intel Thermal Monitor 2 TM2 e Advanced power management features including Enhanced Intel SpeedS
39. g thermal solutions also involves trading performance To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature Tj specifications at the corresponding Thermal Design Power TDP value listed in Table 5 1 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system The maximum junction temperature is defined by an activation of the processor Intel Thermal Monitor Refer to Section 5 2 for more details Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the TDP indicated in Table 5 1 The Intel amp Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time For more details on the usage of this feature refer to Section 5 2 In all cases the Intel amp Thermal Monitor feature must be enabled for the processor to remain within specification Table 5 1 Thermal Design Power Specifications Datasheet Symbol Processor Core Frequency Thermal pasigi Unit Notes ror zom
40. ion Document Location Comments Intel 64 and 1 32 Architectures Software Developer s Manuals Volume 1 Basic Architecture Volume 2A Instruction Set Reference A M http www intel com products processor manuals index htm Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Volume 3B System Programming Guide NOTES 1 Contact your Intel representative for the latest revision and document number of this document 10 Datasheet Signal Descriptions intel 2 Signal Descriptions This chapter describes the processor signals They are arranged in functional groups according to their associated interface or category The following notations are used to describe the signal type Table 2 1 Signal Types O Bi directional I nput Output Pin Table 2 2 Buffer Types Assisted Gunning Transceiver Logic Plus CMOS open drain interface signals that require AGTET COVO EDMI termination Refer to the AGTL 1 0 Specification for complete details CMOS CMOS OD CMOS OD cDMI cDVO LGI LGIE 1 05 V CMOS buffer or CMOS open drain Analo Analog reference or output This may be used 9 as a threshold voltage or for buffer compensation avs LVDS Low voltage differential signal output buffers 1 8 V CMOS buffer These buffers can be CMOS TE DDR2 configured as Stub Series Termination Logic 2 1 Signal Description This section provides a detaile
41. ion Active Termination Control Bank select These signals define which banks are being addressed within each Rank Multiplexed address SM MA signals provide multiplexed row and column address to memory Data lines SM DQ signals interface to the DRAM data bus Data strobes These signals are used during writes and are centered with respect to data During reads these signals are driven by memory devices and are edge aligned with data written Data mask One bit per byte indicating which bytes should be Receive enable out Part of the feedback used to enable the Receive enable in This input enables the SM DQS input buffers during reads DQS input buffers during reads RCOMP Connected to high precision resistor on the motherboard Used to dynamically calibrate the driver strengths Datasheet Signal Descriptions intel 2 1 2 cDMI Interface Table 2 4 cDMI Interface Signal ti CDMI RCOMP Connected to high precision resistors on RCOMP 1 0 the motherboard Used for compensating cDMI pull up pull down impedances O Data output quad pump strobed data bus from CDMI_TX 7 0 CMOS Processor to PCH o Data control character data control character output CDMI_TXCHAR Quad Pump strobed indication that CDMI TX 7 0 CMOS a contains a control character instead of data o Line wakeup for output When asserted the PCH will CDMI TXDPWR CMOS power up its receivers on CDMI TX 7 0 and CDMI_TXCHAR and
42. logic and GFX supply EN eee Vc Vero cDVO LGl tGle cDVO LGI LGI e 1 05 V DDR2 DLL and logic supply Veccpoor _ Veo 1 05 1 05 V JTAG C6 SRAM C6 SRAM 0 LVD_ vo VBG 1 25 V LVDS band gap 1 25 V LVDS band gap supply voltage voltage 1 1 5 V HPLL analog PLL and thermal Vcca 1 575 sensor supply voltage eno Vemm 1 1 8 VLVDS analog supply voltage V LVDS 1 8 VLVDS analog supply voltage supply voltage Datasheet 25 Electrical Specifications 1 8 V LVDS 1 L8 VlVDS 1 0 supply voltage voltage 1 8 V DDR2 self refresh supply VccisosR ue have e IV 1 8 V DDR2 I O 1 8 DDR2 1 0 supply voltage voltage Tsustaneo The ambient storage temperature STORAGE limit in shipping media for a 5 40 C 4 sustained period of time RHsustaineo The maximum device storage relative STORAGE humidity for a sustained period of 60 24 4 5 time MEsustaine A prolonged or extended period of D STORAGE time typically associated with Months 5 customer shelf life As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum has been reached Refer to Section 5 2 for more details 2 Thelntel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 3 The storage t
43. s traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously The Intel Thermal Monitor controls the processor temperature by modulating starting and stopping the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature The Intel Thermal Monitor uses two modes to activate the TCC automatic mode and on demand mode If both modes are activated automatic mode takes precedence There are two automatic modes called the Intel Thermal Monitor 1 TM1 and the Intel Thermal Monitor 2 TM2 These modes are selected by writing values to the MSRs of the proce
44. ssor After the automatic mode is enabled the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation The Intel Thermal Monitor automatic mode must be enabled through 1 32 Firmware for the processor to be operating within specifications Intel recommends that the TM1 mode and the TM2 mode be enabled on the processor Datasheet e Thermal Specifications and Design Considerations intel Datasheet When the TM1 mode is enabled and a high temperature situation exists the clocks will be modulated by alternately turning the clocks off and on at a 50 percent duty cycle Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase Once the temperature has returned to a non critical level modulation ceases and TCC goes inactive A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near the trip point The duty cycle is factory configured and cannot be modified Also automatic mode does not require any additional hardware software drivers or interrupt handling routines Processor performance will be decreased by the same amount as the duty cycle when the TCC is active When the TM2 mode is enabled and a high temperature situation exists the processor will perform an Enhanced Intel SpeedStep Technology transition to the LFM When the processor temperature drops b
45. stem should occur The processor operation and code execution is not ensured once the activation of the Out of Specification status bit is set The DTS relative temperature readout corresponds to the Intel amp Thermal Monitor TM1 TM2 trigger point When the DTS indicates maximum processor core temperature has been reached the TM1 or TM2 hardware thermal control mechanism will activate The system designer is required to use the DTS to ensure proper operation of the processor within its temperature operating specifications Changes to the temperature can be detected using two programmable thresholds located in the processor MSRs These thresholds have the capability of generating interrupts using the core s local APIC Refer to the Intel 64 and 1 32 Architectures Software Developer s Manuals for specific register and programming details Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient This feature is intended for graceful shut down before the THERMTRI P2 is activated If the processor s 1 TM are triggered and the temperature remains high an Out Of Specification status and sticky bit are latched in the status MSR register and generates thermal interrupt Catastrophic Thermal Protection The processor supports the THERMTRIP signal for catastrophic thermal protection An external thermal sensor should also be used to protect the processor and the s
46. tep Technology e Supports 0 1 2 4 power states e Intel Deep Power Down Technology C6 Datasheet Introduction 1 2 1 2 1 1 2 2 1 2 3 Datasheet Interfaces System Memory Support One channel of DDR2 memory 32 bit data bus Memory DDR2 transfer rates of 800 MT s Supports 1 Gb and 2 Gb devices Supports total memory size of 1 GB and 2 GB Provides aggressive power management to reduce power consumption when idle Provides proactive page closing policies to close unused pages Display Controller Seven display planes Display Plane A Display Plane B Display C sprite Overlay Cursor A Cursor B and VGA Display Pipe A Supports LVDS display interface Display Pipe B Supports HDMI via chipset Maximum resolution LVDS display 1366 x 768 18 bpp and 60 fps Supports 18 bpp Supports Non Power of 2 Tiling Output pixel width 24 bit RGB Supports NV12 video data format Supports 3 x 3 panel fitter Dynamic Power Saving Technology DPST 3 0 Support 16 x 256 byte tile size Supports overlay Supports global constant alpha blending cDMI Peak raw BW of link per direction 400 MT s using a quad pumped 8 bit transmit and an 8 bit receive data bus Supports low power management schemes Supports CMOS interface intel Introduction 1 2 4 cDVO e Peak raw BW of 800MT s e Supports low power management schemes e Supports AGTL interface 1 2 5 LVDS e Maximum resolution
47. tion The Intel Atom Processor Z670 component may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request For Enhanced Intel SpeedStep Technology See the Processor Spec Finder at http ark intel com or contact your Intel representative for more information Intel Intel Atom and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2011 Intel Corporation All rights reserved 2 Datasheet Contents Datasheet Introduction 6 1 1 Processor Features ke n 6 1 2 Interfaces c Em 7 1 2 1 System Memory Support 00 cece ce kronika nenne menn nnn 7 1 2 2 Display Controlle serrin rer rer asi es ere aep P eR 7 1 2 3 cdam aud umi v O PA 7 1 2 4 ED MO siete EE 8 1 2 5 PUD AA AA AA Alan 8 1 3 EE RM 8 1 4 Reference DOCUMENTS creer aoreet ANAN AN ADA 9 Signal Descriptions 11 2 1 Signal Descriptio 11 2 1 1 System Memory 11 2 1 2 CDM laii 13 2 1 3 cDWO Iinterface ied muda pied dele Ge enced edad 13 2 1 4 LVDS Display Port Interface eene 14 2 1 5 LGI L
48. tions intel 4 4 4 4 1 Voltage Identification VI D The Vcc and Vpn voltage inputs use two encoding pins VIDEN 1 0 to enable the VID pin inputs and seven voltage identification pins VID 6 0 to select the power supply voltage The VID VIDEN pins for the processor are CMOS outputs driven by the processor VID circuitry Table 4 2 specifies the voltage level corresponding to the state of VID 6 0 A 1 in this refers to a high voltage level and a 0 refers to a low voltage level For more details about PMIC design to support the processor power supply requirements refer to the vendor s specification VI D Enable Both Vcc and Vyn are variable in Intel Atom Processor Z670 Processor implements a new VID mechanism that minimizes the number of required pins The VID for Vyn and Vcc are multiplexed on to the same set of pins and a separate 2 bit enable ID is defined to specify what the driven VID corresponds to One of the combinations is used to notify that the VID is invalid This is used when the processor is in C6 Standby to tri state the VID pins to save power Table 4 1 VIDEN Encoding Datasheet 01b VID for Vec 10b VID for VN 23 intel Electrical Specifications 4 4 2 VI D Table Note 1 Processor will not support the entire range of the voltages listed in the VID table grayed out 2 VID codes below 0 3 V are not supported for Vec Table 4 2 VID Table 06h 26h ach 24 Datasheet
49. ty to activate the TCC using PROCHOT can provide a means for thermal protection of system components Only a single PROCHOT pin exists at a package level of the processor When the core s thermal sensor trips the PROCHOT signal is driven by the processor package If only TM1 is enabled PROCHOT will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated If TM2 is enabled and the core is above TCC temperature trip point it will enter the lowest programmed TM2 performance state It is important to note that Intel recommends that both TM1 and TM2 be enabled When PROCHOT is driven by an external agent if only TM1 is enabled on the core then the processor core will have the clocks modulated If TM2 is enabled then the processor core will enter the lowest programmed TM2 performance state It should be noted that Force TM1 on TM2 enabled using 1 32 Firmware does not have any effect on external PROCHOT If PROCHOT is driven by an external agent when TM1 TM2 and Force 1 TM2 are all enabled then the processor will still apply only TM2 PROCHOT may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR will cool down as a result of reduced processor power consumption Bi
50. ystem against excessive temperatures Even with the activation of THERMTRIP which halts all processor internal clocks and activity leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor If the external thermal sensor detects a potentially catastrophic processor temperature or if the THERMTRIP signal is asserted by the processor the Vcc supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor THERMTRI P functionality is not ensured if the PWRGOOD signal is not asserted PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its maximum operating temperature If TM1 or TM2 is enabled then the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or deassertion of 35 Thermal Specifications and Design Considerations PROCHOT Refer to the Intel 64 and IA 32 Architectures Software Developer s Manuals The processor implements a bi directional PROCHOT capability to allow system designs to protect various components from overheating situations The PROCHOT signal is bi directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC The abili
Download Pdf Manuals
Related Search