Integral INSSD64GP25MXZ solid state drive
Contents
1. No Command Set Code FR SC SN DR HD LBA CFA Erase Sector s COh Y Y Y Y Y Y 2 CFA Request Extended Error O3h Y Code CFA Translate Sector 87h Y Y Y Y Y Y 4 CFA Write Multiple w o CDh Erase 5 CFA Write Sector w o Erase 38h Y Y Y Y Y Y 6 Check Power Mode E5h Y 7 Execute Device Diagnostic 90h Y 8 Identify Device ECh Y 9 Idle E3h Y Y 10 idle Immediate E1h Y 11 Initialize Device Parameters 91h Y Y Y 12 NOP 00h Y 13 Read Buffer E4h Y 14 Read DMA C8h Y Y Y Y Y Y 15 Read Multiple C4h Y Y Y Y Y Y 16 Read Sector s 20h Y Y Y Y Y Y 17 Read Verify Sector s 40h 18 70 Y Y Y Y Y 19 Set Features EFh Y Y 20 Set Multiple Mode C6h Y 21 Sleep E6h Y 22 Standby E2h Y 23 Standby Immediate EOh Y 24 Write Buffer E8h Y 25 Write DMA CAh Y Y Y Y Y Y 26 Write Multiple C5h Y Y Y Y Y Y 27 Write Sector s 30h Y Y Y Y Y Y Note FR Feature Register HD Head No of Drive Head Register SC Sector Count Register LBA LBA mode supported SN Sector Number Register Y Set up CY Cylinder Low High Registe2. Word Default Total Bytes Data Field Type Information Address Value Current capacity in sectors LBAs Word 57 57 58 xxxxh 4 LSW Word 58 MSW 59 0101h 2 Multiple sector setting is valid Total number of sectors addressable in LBA 60 61 xxxxh 4 Mode 62 0000h 2 Retired Multiword DMA mode 2 and below are 63 0007h 2 supported 64 0003h 2 Advance PIO transfer modes supported Minimum Multiword DMA transfer cycle time 65 0078h 2 120nsec Manufacturer s recommended Multiword DMA 66 0078h 2 transfer cycle time 120nsec Minimum PIO transfer cycle time without flow 67 0078h 2 control 120nsec Minimum PIO transfer cycle time with IORDY 68 0078h 2 flow control 120nsec 69 79 0000h 26 Reserved 80 0030h Major version number 81 0000h Reserved 82 7009h 2 Supports Security Mode feature set 83 5004h 2 Reserved 84 4000h 85 7009h Feature Setting 86 1004h Feature Setting 87 4000h Feature Setting Ultra DMA mode 5 and below are supported 88 203Fh 2 UDMA mode5 select 89 92 0000h 8 Reserved 93 xxxxh 94 128 0000h 2 Enhanced security erase supported 129 159 0000h 62 Reserved vendor unique bytes 160 255 0000h 192 Reserved Note 1 a Vender Specific Configuration 2 n Host Selectable Configuration 24 5 0 Physical Dimension 5 1 2 5 PATA SSD Top view Bottom view 7 20 0 20 100 00 0 20 Unit mm 25
3. Multiword DMA timing parameters Mode Mode Mode Note Ons 1ns 2 ns ty Cycle time 480 150 120 See min note to DIOR DIOW asserted pulse width 215 80 70 See min note te DIOR data access 150 60 50 max DIOR data hold 5 5 5 min te DIOR DIOW data setup 100 30 20 min tu DIOW data hold 20 15 10 min t DMACK to DIOR DIOW setup 0 0 0 min 1 DIOR DIOW to DMACK hold 20 5 5 min tkr DIOR negated pulse width 50 50 25 See min note tkw DIOW negated pulse width 215 50 25 See min note tir DIOR to DMACK delay 120 40 35 max tiy DIOW to DMACK delay 40 40 35 max tm CS 1 0 valid to DIOR DIOW 50 30 25 min ty CS 1 0 hold 15 10 10 min t DMACK to read data released 20 25 25 max Notes t is the minimum total cycle t is the minimum DIOR DIOW assertion time and LL Or tkw as appropriate is the minimum DIOR DIOW negation time A host shall lengthen t and or t to ensure that t is equal to the value reported in the devices IDENTIFY DEVICE data 14 3 3 3 Ultra DMA Data Transfer Ultra DMA data burst timing requirements in ns in ns Min 153 10 0 50 10 0 5 0 62 0 0 s Mode 3 in ns 5 57 lt ne 9 m o o aS gt A Slo SPIS th gt S 54 a e
4. 5 iS 29 eo NI ho co e EST I Es gt ics zs Hozes Hes ty uz tzan taes ru onpvz mark tack itss NOTES Mode 4 in ns Mode 5 in ns 40 5 Min Mode 6 Measurement location Max Sender Note 3 Sender Recipient Recipient Sender Sender Device Device Host Host Device Sender Device Note 4 Host Host Note 5 Host Device Host Sender Recipient Device Device Host Sender 1 All timing measurement switching points low to high and high to low shall be taken at 1 5 V 2 All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column transitions are measured at the sender connector For example in the case of ters both STROBE and DMARDY 3 The parameter shall be measured at the recipient s connector farthest from the sender 4 The parameter shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively Both the incoming signal and the outgoing response shall be measured at the same connector 5 The parameter taz shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus the allow for a bus turnaround 15 Ultra DMA data burs
5. 25 1 0 Block Diagram PATA Link Controller 1 1 Capacity Specification Density Total Bytes Cylinders Heads Sectors Total LBA 32GB 31 272 321 024 16383 16 63 61 078 752 64GB 62 545 158 144 16383 16 63 122 158 512 128GB 127 909 232 640 16383 16 63 249 822 720 2 0 Specification 2 1 Pin Assignments Pin 10 DD11 12 DD12 14 DD13 16 DD14 18 DD15 19 GND 20 KEY_PIN OPEN 21 DMARO 22 GND 23 DIOW STOP 24 GND 25 DIOR HDMARD Y HSTOBE 26 GND 27 IORDY DDMARD Y DSTROBE 28 CSEL 29 DMACK 30 GND 31 INTRO 32 01516 33 DA1 34 PDIAG CBLID 35 DAO 36 DA2 37 CSO 38 C51 39 DASP 40 GND 41 vcc 42 vcc 43 GND 44 NC Pin 43 Pin 1 2 2 Pin Description STOP Stop UDMA Burst Pin No Signal Description 01 RESET Hardware reset signal from the host 17 15 13 11 09 07 DDO DD15 Device 1 0 16 bit bi direction Data Bus 05 03 04 06 08 10 Data DD 7 0 are used for 8 bit 12 14 16 18 register transfers 21 DMARQ DMA Request For DMA data transfers Device will assert DMARO when the device is ready to transfer data to or from the host 23 DIOW I O Write This is the strobe signal used by the host to write to the device register or Data port The host asse
6. 60 00C0X 5 __ _ _ _ _ _ _ _ _ _ ____ _ _ 3 0 ELECTRICAL CHARACTERISTICS 3 1 ABSOLUTE MAXIMUM 00 3 2 DC CHARACTERISTICS 5 0V I O CELLS HOST 3 3 XLVLV V V gt 4 4 4 4 __ ___ _______ _ 3 3 1PIO Data Transfert toes 9 3 3 2Multiword DMA Data Transfer 11 3 3 3UItra DMA Data Transfer 15 3 4 POWER MANAGE 21 4 0 SOFTWARE 21 4 1 ATA TASK gt ____ ____ __ 21 4 2 COMMAND SETS eni nuni nad Aem eulos cedem onc ee iion ese 22 4 3 IDENTIFY DRIVE nnan 23 5 0 PHYSICAL 25 5 1 2 5 PATA SSD tenente
7. tack STOP DDMARDY device HSTROBE DAD DA1 DA2 C50 CS1 NOTES 1 See 8 14 1 Initiating an Ultra DMA data out burst 2 The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Initialing an Ultra DMA data out data burst HSTROBE at host DD 15 0 at host HSTROBE at device DD 15 0 d gt XXXXX XXXXXXX NOTES 1 See 9 14 2 The data out transfer 2 DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Sustained Ultra DMA data out burst 19 DMARQ device DMACK host gt 9 00 05 DOMARDY device HSTROB J s X 7 XXX tevs 00152 SKK KKK KKK KKK OR DAO DA1 DA2 CSO CS1 X X X NOTES 1 See 9 14 4 1 Host terminating an Ultra data out burst 2 The definitions for the STOP DOMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Host terminating an Ultra DMA data out burst OMARQ device DMACK host STOP host DDMARDY device HSTROBE host 00 15 0 host DAO DA1 DA2 CS0 CS1 NOTES 1 See 9 14 4 2 Device pausing an Ultra DMA data ou
8. Device O that Device 1 has completed diagnostics CBLID Cable assembly type identify 37 38 CSO CS1 Chip select I These signals are used to select the Command Block and Control Block registers When DMACK is asserted CsO and Cs1 shall be negated and transfers shall be 16 bit wide 39 DASP Device active 1 0 During the reset protocol DASP Device 1 present shall be asserted by Device 1 to indicate that the device is present 41 42 vcc P Power supply 02 19 22 24 GND Ground 26 30 40 43 Note yo up An input from the host system to the device An output from the device to the host system An input output bi direction common Power supply 3 0 Electrical Characteristics 3 1 Absolute Maximum Rating Ite Symbol Parameter MIN MAX Unit m 1 Vop Vss DC Power Supply 0 3 5 5 V 2 VIN Input Voltage Vss 0 3 Vppt 0 3 V 3 Ta Commercial Operating 0 70 C Temperature 4 Tst Commercial Storage 25 85 C Temperature 5 Ta Industrial Operating 40 85 C Temperature 6 Tst Industrial Storage 40 85 C Temperature Parameter Symbol MIN TYP MAX Unit Vpp Voltage 3 0 3 3 3 6 V 4 5 5 0 5 5 3 2 DC Characteristics of 5 0V I 0 Cells Host Interface Symbol Paramet
9. and IORDY DDMARDY DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Initialing an Ultra DMA data in burst OSTROBE at device DD 15 0 at device DSTROBE at host toe fos tonic tsiz C leac 2 gt XXKKK KK XXXXXXX at host NOTES 1 See 9 13 2 The data in transfer 2 DD 15 0 and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Sustained Ultra DMA data in burst 17 DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DAO DA1 DA2 CS0 CS1 NOTES 1 See 9 13 4 1 Device terminating an Ultra DMA data in burst 2 The definitions for the STOP HOMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Device terminating an Ultra DMA data in burst DMARQ device DMACK host STOP host HDMARDY host DAO DA1 DA2 50 51 NOTES 1 See 9 13 4 2 Host pausing an Ultra data in burst 2 The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Host terminating an Ultra DMA data in burst 18 DMARQ device tui DMACK host
10. der interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding ty is an unlimited interlock that has no maximum time value is a limited time out that has a defined minimum t is a limited time out that has a defined maximum 2 80 conductor cabling See 7 3 shall be required in order to meet setup tos tes and hold tox tc times in modes greater than 2 3 Timing for tous tova tevs and shall be met for lumped capacitive loads of 15 and 40 pf at the connector where the Data and STROBE signals have the same capacitive load value Due to reflections on the cable these timing measurements are not valid in a normally functioning system 4 For all modes the parameter tziorpy be greater than teny due to the fact that the host has a pull up on IORDY giving it a known state when released 5 The parameters tos and for mode 5 are defined for a recipient at the end of the cable only in a configuration with a single device located at the end of the cable This could result in the minimum values for tos and L for mode 5 at the middle connector being 3 0 and 3 9 ns respectively 16 DMARQ device DMACK host STOP host HDMARDY host DSTROBE device X15 FOO XXX 2XXX DAO DAT DA2 C50 CS1 NOTES 1 See 9 13 1 Initiating an Ultra DMA data in burst 2 The definitions for the DIOW STOP DIOR HDMARDY HSTROBE
11. er Conditions MIN TYP MAX Unit Vil Input Low Voltage TTL 5V 0 85 V Vih Input High Voltage 1 25 V Vil Input Low Voltage TTL 3 3V 1 05 V Vih Input High Voltage 1 75 V Vol Output Low Voltage II II 4 32 0 4 V mA Voh Output High Voltage llohl 4 32 2 8 V mA lin Input Leakage Current No pull up or 10 1 10 uA pull down loz Tri state Output 10 1 10 uA Leakage Current 3 3 AC Characteristics 3 3 1 PIO Data Transfer ADDR valid x YAYAYA See note 1 KAKA wes DIOR DIOW WRITE DD 15 0 DD 7 0 See note 2 READ DD 7 0 EE See note 2 ts lt IORDY See note 3 3 1 S IORDY MM X XX X MIX MX XXX AXI See note 3 3 2 te tro IORDY See note 3 3 3 5 1 Device address consists of signals 50 51 and DA 2 0 2 Data consists of DD 7 0 3 The negation of IORDY by the device is used to extend the register transfer cycle The determination of whether the cycle is to be extended is made by the host after ta from the assertion of DIOR or DIOW The assertion and negation of IORDY are described in the following three cases 3 1 Device never negates IORDY devices keeps IORDY released no wait is generated 3 2 Device negates IORDY before ta but causes IORDY to be asserted before ta IORDY is released prior to negation and may be asserted f
12. integral STORAGE A E DATAS Integral Z Series PATA 2 5 Inch Specification Version 1 1 Features e Standard 50pin 2 5 formfactor e Standard ATA IDE Bus Interface 512 Bytes Sector ATA command set compatible Selectable Master Slave Setting e Capacities Integral 2 Series MLC Flash 32GB 64GB 128GB Integral E Series SLC Flash 8GB 16GB 32GB 64GB Pls call for availability e Data Transfer mode Support Data Transfer up to PIO mode 6 Support Data Transfer up to Multiword DMA mode 2 Support Data Transfer up to Ultra DMA mode 5 Temperature Ranges WB Commercial Temperature 0 C to 70 C for operating 25 Cto 85 C for storage a Extensive Temperature 400 to 85 C for operating 40 C to 85 C for storage Operating Voltage 3 3V 5 0V e Intelligent ATA IDE Module Built in Embedded Flash File System Implements dynamic wear leveling algorithms and static wear leveling algorithms to increase endurance of flash media PS3016 P7 Built in ECC corrects up to 48 random bits error per 2K bytes e RoHS Compliance TABLE OF CONTENTS 1 0 BEOCK DIAGRAM nga e be HE e n Prediction 1 1 CAPACITY SPECIFICATION Pee eate dene 2 0 SPECIFICATION e cedere tet ey Ordo 2 1 PIN ASSIGNMENTS 1 rer nece eer eer iere E 2 2
13. ion of both CSO and 51 is not defined Initialing a Multiword DMA data burst 11 CS0 CS1 DMARQ DMACK DIOR DIOW Read DD 15 0 Write DD 15 0 Sustaining a Multiword DMA data burst CS0 CS1 b pa DMARQ See note DMACK DIOR DIOW Read DD 15 0 Write 000150 XXX XXXXXXXXXX KXXXXX NOTE To terminate the data burst the Device shall negate DMARQ within t of the assertion of the current DIOR or DIOW pulse The last data word for the burst shall then be transferred by the negation of the current DIOR or DIOW pulse If all data for the command has not been transferred the device shall reassert DMARQ again at any later time to resume the DMA operation as shown in figure 66 Device terminating a Multiword DMA data burst 12 CS0 CS1 ls DMARQ weee See note 2 DMACK See note 1 DIOR DIOW Read DD 15 0 Write DD 15 0 NOTE 1 To terminate the transmission of a data burst the host shall negate DMACK within t after DIOR or DIOW pulse No further DIOR or DIOW pulses shall be asserted for this burst 2 If the device is able to continue the transfer of data the device may leave DMARQ asserted and wait for the host to reassert DMACK or may negate at any time after detecting that DMACK has been negated Host terminating a Multiword DMA data burst 13
14. or no more than 5 ns before release no wait generated 3 3 Device negates IORDY before ta IORDY is released prior to negation and may be asserted for no more than 5 ns before release wait generated The cycle completes after IORDY is reasserted For cycles where a wait is generated and DIOR is asserted the device shall place read data on DD 7 0 for tsp before asserting IORDY 4 DMACK shall remain negated during a register transfer PIO timing parameters Mode Mode Mode Mode Mode Not Ons 1 ns 2 ns 3 ns 4 ns e Cycle time 600 383 240 180 120 1 4 min t Address valid to 70 50 30 30 25 DIOR DIOW setup min t DIOR DIOW 165 125 100 80 70 1 min DIOR DIOW recovery 70 25 1 time min t DIOW data setup 60 45 30 30 20 min t DIOW data hold 30 20 15 10 10 min DIOR data setup 50 35 20 20 20 min t DIOR data hold 5 5 5 5 5 min 15 DIOR data tristate 30 30 30 30 30 2 max DIOR DIOW to address 20 15 10 10 10 10 valid hold min tko Read Data Valid to 0 0 0 0 0 IORDY active if IORDY initially low after t min t IORDY Setup time 35 35 35 35 35 3 IORDY Pulse Width 1250 1250 1250 1250 1250 max 1 IORDY assertion to 5 5 5 5 5 release max Notes 1 t is minimum total cycle t is minimum DIOR DIOW assertion time and t is the minimum DIOR DIOW negation time A hos
15. r Not set up DR Drive bit of Drive Head register 22 4 3 Identify Drive Information The Identity Drive Command enables Host to receive parameter information from the device The parameter words in the buffer have the arrangement and meanings defined in below table All reserve bits or words are zero Word Default Total Bytes Data Field Type Information Address Value General configuration bit significant for Non removable device 1 xxxxh 2 Default number of cylinders 2 0000h 2 Reserved 3 xxxxh 2 Default number of heads 4 7E00h 2 Retired 5 0200h 2 Retired 6 xxxxh 2 Default number of sectors per track 7 8 xxxxh 4 Number of sectors per device 9 0000h 2 Retired 10 19 xxxxh 20 Serial Number in ASCII 20 0002h 2 Retired 21 0002h 2 Retired 25 anes Number of ECC Bytes passed on Read Write Long Commands 23 26 Aaaah 8 Firmware revision in ASCII 27 46 xxxxh 40 Model number in ASCII Maximum number of sector that shall be 47 8001h 2 transferred on Read Write Multiple commands 48 0000h 2 Reserved 49 2B00h 2 Capabilities LBA DMA Supported 50 4000h 2 Reserved 51 0200h 2 PIO data transfer cycle timing mode 2 52 0000h 2 Retired 53 0007h 2 Word 54 58 64 70 and 88 are valid 54 xxxxh 2 Current numbers of cylinders 55 xxxxh 2 Current numbers of heads 56 xxxxh 2 Current sectors per track 23
16. rt this signal during an UDMA burst to stop the DMA burst 25 IORDY I O channel ready DDMARDY UDMA ready DSTROBE UDMA data strobe This signal is used to temporarily stop the host register access read or write when the device is not ready to respond to a data transfer request The device will assert this signal to indicate that the device is ready to receive UDMA data out burst When UDMA mode DMA Read is active this signal is the data in strobe generated by the device 28 CSEL Cable select This pin is used to configure this device as Device O or Device 1 29 DMACK DMA acknowledge This signal is used by the host in respond to DMARO to initiate DMA transfer 31 INTRO Interrupt When this device is selected this signal is the active high Interrupt Request to the host Pin No Signal yo Description 32 101S16 During PIO transfer modeO 1or 2 this pin indicates to the host the 16 bit data port has been addressed and the device is prepared to send or receive a 16 bit data word When transferring in DMA mode the host must use a 16 bit DMA channel and this signal will not be asserted 35 33 36 DAO DA2 Device Address This is 3 bit binary coded Address Bus 34 PDIAG Passed diagnostics 1 0 This signal will be asserted by Device 1 to indicate to
17. t burst 2 The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer effect after and DMACK are negated Device terminating an Ultra DMA data out burst 20 3 4 Power Management System Power Consumption Ta 0 to 70 Symbol Parameter Conditions MIN TYP MAX Unit Iccr Read current 5V 130 mA Iccw Write current 5V 140 mA Power down current 5V 0 2 0 4 mA Iccr Read current 3 3V 200 mA Iccw Write current 3 3V 210 mA Power down current 3 3V 0 3 mA 4 0 Software Interface 4 1 ATA Task File Registers The 1 0 decoding of each register is as follows CS1 CSO 2 1 AO DIOR 0 DIOW 1 DIOW 0 DIOR 1 1 0 0 0 0 Data Read Data Write 1 0 0 0 1 Error Feature 1 0 0 1 0 Sector Count Sector Count 1 0 0 1 1 Sector Number LBA7 0 Sector Number LBA7 0 1 0 1 0 Cylinder Low LBA 15 8 Cylinder Low LBA 15 8 1 0 1 0 1 Cylinder High LBA Cylinder High LBA 23 16 23 16 1 0 1 1 0 Drive Head LBA 27 24 Drive Head LBA 27 24 1 0 1 1 1 Status Command 0 1 1 1 0 Alternate Status Device Control 0 1 1 1 1 Drive Address Reserved 21 4 2 Command Sets Below table summarizes the PATA 2 5 SSD command set with the paragraphs that follow describing the individual commands and task file for each command
18. t implementation shall lengthen t to ensure that t is equal to or greater than the value reported in the devices IDENTIFY DEVICE data A device implementation shall support any length host implementation 2 This parameter specifies the time from the negation edge of DIOR to the time that the data is released by the device 10 3 The delay from the activation of FIOR or DIOW until the state of IORDY is first sampled If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle is complete If the device is not driving IORDY negated at the t after the activation of DIOR or DIOW that t shall be met and t is not applicable If the device is driving IORDY negated at the time t after the activation of DIOR or DIOW then tRD shall be met and t is not applicable Mode may be selected at the highest mode for the device if CS 1 0 and DA 2 0 do not change between read or write cycle or selects at the highest mode supported by the slowest device if CS 1 0 and DA 2 0 do change between read or write cycles 3 3 2 Multiword DMA Data Transfer 50 51 See note 4 DMARQ See note lt lt DMACK DIOR DIOW Read DD 15 0 NOTE The host shall not assert DMACK or negate both CSO and CS1 until the assertion of DMARQ is detected The maximum time from the assertion of DMARQ to the assertion of DMACK or the negat
19. t timing descriptions Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edge Two cycle time allowing for clock variations from rising edge to next rising edge or from falling edge to next falling edge of STROBE Data setup time at recipient from data valid until STROBE edge See note 2 5 Data hold time at recipient from STROBE edge until data may become invalid See note 2 5 Data valid setup time at sender from data valid until STROBE edge See note 3 Data valid hold time at sender from STROBE edge until data may become invalid See note 3 ud nm 2 5 CRC word valid hold time at sender from DMACK negation until CRC may become invalid See note 3 Time from STROBE output released to driving until the first transition of critical timing Time from data output released to driving until the first transition of critical timing Es tu Interlock time with minimum See note 1 Unlimited interlock time See note 1 A Envelope time from to STOP and HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation 1 Hus tz tao v Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst gt tss NOTES 1 The parameters tyi in Figure 74 and Figure 75 and LI indicate sender to recipient or recipient to sen
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