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Elixir DDR3 1GB

1. Serial Presence Detect M2F X 2G64CB88B7N M2F X 2G64CB88BHN 2GB 1 Rank 256Mx8 DDR3 SDRAMs M Serial PD Data Entry Hex Byte Description x DG 0 CRC range EEPROM bytes bytes used 92 92 93 1 SPD revision 10 10 10 2 DRAM device type 0B 0B 0B 3 Module type form factor 02 02 02 4 SDRAM Device density and banks 03 03 03 5 SDRAM device row and column count 19 19 19 6 Module minimum nominal voltage 00 00 00 T Module ranks and device DQ count 01 01 01 8 ECC tag and module memory Bus width 03 03 03 9 Fine timebase dividend divisor in ps 52 52 52 10 Medium timebase dividend 01 01 01 11 Medium timebase divisor 08 08 08 12 Minimum SDRAM cycle time tCKmin OF 0 0 13 Reserved 00 00 00 14 CAS latencies supported 1 3C TE 15 CAS latencies supported 00 00 00 16 Minimum CAS latency time tAAmin 69 69 64 17 Minimum write recovery time tWRmin 78 78 78 18 Minimum CAS to CAS delay tRCDmin 69 69 64 19 Minimum Row Active to Row Active delay tRRDmin 3C 30 30 20 Minimum row Precharge delay tRPmin 69 69 64 21 Upper nibble for tRAS and tRC 11 11 11 22 Minimum Active to Precharge delay RASmin 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin 95 89 7C 24 Minimum refresh recovery delay tRFCmin LSB 00 00 00 25 Minimum refresh recovery delay tRFCmin MSB 05 05 05 26 Minimum internal Write to Read command delay tWTRmin 3C 3C 3C 27 Minimum in
2. o tals S 3 S S 8 m 2 alo Xx p 8 o N D o D Command Address hold time from CK referenced to Vih dc Vil dc levels Command and Address setup time to CK 125 150 referenced to Vih ac levels Control and Address Input pulse width for each input Calibration Timing Power up and RESET calibration time 512 256 D D 2 gt O B a 0 25 200 80 A Normal operation Full calibration time A Normal operation Short calibration time 2 n s NIN 5 8 2 2 tXPRmin max 5nCK tRFC min 1015 tXPRmax Exit Reset from CKE HIGH to a valid command i tXSmin max 5nCK tRFC min 10ns tXSmax XSDLLmin tDLLK min tXSDLLmax tCKESRmin tCKE min 1 nCK tCKESRmax tCKSREmin max 5 nCK 10 ns tCKSREmax tCKSRXmin max 5 nCK 10 ns tCKSRXmax tXPmin max 3nCK 7 5ns tXPmax Exit Self Refresh to commands not requiring a locked DLL A Exit Self Refresh to commands requiring a locked DLL Minimum CKE low width for Self Refresh entry to exit timing n o 2 p Er 8 D Valid Clock Requirement after Self Refresh Entry SRE or Power Down Entry PDE Valid Clock Requirement before Self Refresh Exit SRX or Power Down Exit PDX or Reset Exit
3. gt 00 07 p A1 4 gt SDA Vnerba ies 9 gt 00 07 gt gt A2 Vss e e gt 00 07 RENE VnerFCA gt DO D7 d 2 BAO BA2 SDRAMs 00 07 AO A13 p gt A0 A13 SDRAMs D0 D7 RAS p RAS SDRAMs 00 07 DDR3 CAS p CAS SDRAMs 00 07 SDRAM SDRAMs 00 07 A 13 0 WE p WE SDRAMs 00 07 Gare BA 0 Ww Vit ODT SDRAMs 00 07 CK SDRAMs D0 D7 DDRS CK SDRAMs Do D7 SDRAM RESET gt RESET SDRAMs D0 D7 F W Voo Notes 1 DQ to I O wiring is shown as recommended but may be changed 2 DQ DQS DQS ODT DM CKBE S relationships must be maintained as shown 3 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 2400 X196 4 One SPD exists per module 6 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3
4. 0 20 S lo 2 la s 3 B 3 3 gt o 5 5 o S g o o 5 5 3t 2 a 9 S S E E Q E jE D 2 aja 8 8 3 9 5 8 2 o 8 3 2 o A g DQS DQS low impedance time Referenced from RL 1 Referenced from RL BL 2 o e m o 3k eh 3 o S 3 o 3 o o ojoje w RIO ing edge setup NINN 5 S S amp 2 2 8 a 5 5 5 5 e z 5 8 gt 5 time to CK rising edge DOS DOSf falling edge hold time from CK CK rising edge bsn o2 jtcK avg 1 0 21 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 m s Unbuffered DDR3 SDRAM DIMM el IXIF Command and Address Timing Se ENEMY DLL locking time tDLLK prec tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE
5. m Serial PD Data Entry Hex Byte Description DG 0 CRC range EEPROM bytes bytes used 92 92 93 1 SPD revision 10 10 10 2 DRAM device type 0B 0B 0B 3 Module type form factor 02 02 02 4 SDRAM Device density and banks 03 03 03 5 SDRAM device row and column count 19 19 19 6 Module minimum nominal voltage 00 00 00 7 Module ranks and device DQ count 09 09 09 8 ECC tag and module memory Bus width 03 03 03 9 Fine timebase dividend divisor in ps 52 52 52 10 Medium timebase dividend 01 01 01 11 Medium timebase divisor 08 08 08 12 Minimum SDRAM cycle time tCKmin OF 0 0 13 Reserved 00 00 00 14 CAS latencies supported 1 3C TE 15 CAS latencies supported 00 00 00 16 Minimum CAS latency time tAAmin 69 69 64 17 Minimum write recovery time tWRmin 78 78 78 18 Minimum CAS to CAS delay tRCDmin 69 69 64 19 Minimum Row Active to Row Active delay tRRDmin 3C 30 30 20 Minimum row Precharge delay tRPmin 69 69 64 21 Upper nibble for tRAS and tRC 11 11 11 22 Minimum Active to Precharge delay 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin 95 89 7C 24 Minimum refresh recovery delay tRFCmin LSB 00 00 00 25 Minimum refresh recovery delay tRFCmin MSB 05 05 05 26 Minimum internal Write to Read command delay WTRmin 3C 3C 3 27 Minimum internal Read to Precharge command delay tRTPmin 3C 3C 3C 28 Minimum four active window delay tFAWmin LSB 01 00 00 29 Minimum four active window delay tFAW
6. Data setup time to DQS DQS referenced to Vih ac Vil ac levels Aiso tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 E tLZ DQS a ojo AA D 2 lt e i Note 19 Note 11 vg A lo 5 o 6 o 8 2228 o e amp 2 5 2 2 8 s 2 5 amp o 2 o 5 2 5 9 5 o 9 zi 0 0 S o o SEMEN E 8 lo o S 2 lt o o T m o 5 5 5 o 3 o ES lt e ES A lt e K a a lt o 2 m a o 3k 5 o o o o E 2 5 s a S S le 2 p p 5 2 aja x mim 18 2 3 9 8 8 2 amp do 3 g 2 g 3 3 225 Referenced from RL 1 Referenced from RL BL 2 o e m n 3k 3 o S 3 o 3 o tHZ DQS DQS DQS rising edge to CK CK rising edge 0 27 tCK avg DQS DQS falling edge setup time to CK CK rising edge loss fit fe tCK avg DQS DQS falling edge hold time from CK r
7. REV 1 0 20 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Celixir AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1333MHz DDR3 1333 Parameter Symbol Units Min Max Glock Timing __ P Minimum Clock Cycle Time DLL offmede Average Clock Period tag Refert Standard Speed Bins fps Average righ pulse width 0o Ke ___ Average low pulsewidth pow _______ __ te Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth Absolute clock LOW pulsewidth poes 049 ____ Clock Period siter __ __ 8 s Glock Period Jitter during DLL locking period mee o Cyce to Cycle Period siter two tos o Cycle to Cycle Period Jitter during DLL locking period Duty Cycle iter __ Min tCK avg min tJIT per min tERR 6per tERR 7per ____ tt je S o 0040 w w S e no 0 00088 va je I 088 0 e jp _ ____ pts S s o f w f
8. 8F 3 232 Maximum tREFI Time Average Periodic Refresh Interval LSB 37 3 233 Maximum tREFI Time Average Periodic Refresh Interval MSB 00 3 4 234 Minimum Refresh Recovery Time tRFCmin Least Significant Byte C0 34 235 Minimum Refresh Recovery Time tRFCmin Most Significant Byte ES 08 3 4 236 Minimum Internal Read to Precharge Command Delay Time tRTPmin 69 3 4 237 Minimum Row Active to Row Active Delay Time tRRDmin 54 3 4 238 Upper Nibble for tFAW 01 3 4 239 Minimum Four Activate Window Delay Time tFAWmin 4 3 4 240 Minimum Internal Write to Read Command Delay Time tWTRmin 69 3 241 Write to Read amp Read to Write CMD Turn around Time Pull in ES 00 3 242 Back to Back CMD Turn around Time Pull in 00 3 243 System ADD CMD Rate 1N or 2N mode 1C 3 244 Auto Self Refresh Performance Sub 1x Refresh and IDD6 Impacts ES 00 3 245 Memory Controller Voltage Level for Profile 2D 3 246 253 RSVD 3 254 Vendor Personality Byte for Profile 2 RSVD 3 1 Global Parameters used across all profiles 2 Utilized for Profile 1 Enthusiast Certified Settings 3 Utilized for Profile 2 Extreme Settings 4 Parameter utilized in the same fashion as the standard DDR3 SPD byte with the exception that it may exceed the DDRx SDRAM datasheet REV 1 0 11 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and spec
9. CL 9 M2F2G64CB88BHN BE DDR3 1066 8500 533MHz 1 875ns CL 7 M2F2G64CB88BHN CG DDR3 1333 10600 667MHz 1 5 CL 9 256Mx64 M2X2G64CB88BHN DG DDR3 1600 PC3 12800 800MHz 1 25ns CL 9 M2F4G64CB8HB9N BE DDR3 1066 PC3 8500 533MHz 1 875ns CL 7 M2F4G64CB8HB9N CG 3 1333 10600 667MHz 1 5ns CL 9 512Mx64 M2X4G64CB8HB9N DG DDR3 1600 12800 800MHz 1 25ns CL 9 Pin Description Pin Name Description Description CKO CK1 Clock Inputs positive line DQO0 DQ63 Data input output CKO CK1 Clock Inputs negative line DQS0 DQS8 Data strobes CKEO CKE1 Clock Enable DQS0 DQS8 Data strobes complement RAS Row Address Strobe Data Masks CAS Column Address Strobe EVENT Temperature event pin WE Write Enable RESET Reset pin 50 51 Chip Selects Vrerca Input Output Reference 9 A11 A13 A15 Address Inputs Vopspp SPD and Temp sensor power A10 AP Address Input Auto Precharge SAO SA1 Serial Presence Detect Address Inputs A12 BC Address Input Burst Chop Vtt Termination voltage BAO BA2 SDRAM Bank Address Inputs Vss Ground ODT1 Active termination control lines Vop Core and I O power SCL Serial Presence Detect Clock Input NC No Connect SDA Serial Presence Detect Data input output REV 1 0 2 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P
10. M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment elixir Pin Front Pin Back Front Front Pin Back Pin Front Pin Back 1 121 Vss 31 0025 151 Vss 61 A2 181 1 91 0041 21 DMS 2 Vs 122 DQ4 32 Va 152 62 182 Vp 92 212 00514 TDOS14 DES NC DOST a DQO 123 DQ5 33 Dass 153 0512 CK1 NC 183 V 93 DOSS 213 DOST TDQS12 00514 4 DQi 124 Vss 34 DQS3 154 Vss 64 184 CKO 94 0055 214 Vss 5 Vs 125 35 155 0030 65 185 95 Va 215 0046 6 DOST 126 d 36 26 156 0031 66 Vo 186 96 0042 216 0047 7 0050 127 Vss 37 0027 157 Vss 67 Vaerca 187 Eod gt 97 0043 217 Vss 8 Va 128 DQ6 38 158 CBANC 68 To 188 AO 98 218 DQ52 9 DQ2 129 DQ7 39 CBO NC 159 5 69 189 Vp 99 DQ48 219 0053 10 003 130 Vss 40 CB1 NC 160 Vss 70 A10 AP 190 100 DQ49 220 Vss DM6 11 1 Vss 131 DQ12 41 Vas 161 DM amp DQS17 74 491 101 Vas 221 00515 TDQS17 NC TDOSIS NN NC DOS17 ae NC 12 132 Dats 42 0058 162 72 192 RAS 102 0056 222 50545 TDOST TDQS15 13 133 Vss 43 0058 1
11. operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum case temperature shall not exceed the value specified in the component spec Absolute Maximum DC Ratings Symbol Parameter Rating Units Note VDD Voltage on VDD pins relative to Vss 0 4 V 1 975 V V 1 3 Vppa Voltage on VDDQ pins relative to Vss 0 4 V 1 975 V V 1 3 Vins Vout Voltage on I O pins relative to Vss 0 4 V 1 975 V V 1 TsrG Storage Temperature 55 to 100 C 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300 mV of each other at all times and VREF must be not greater Operating temperature Conditions Symbol Parameter Rating Units Normal Operating Temperature Range 0 to 85 1 2 TOPER Extended Temperature Range 85 to 95 C 1 3 Note 1 Operating Temperature TOPER is t
12. tCPDEDmin tPDmin tCKE min Command pass disable delay U Power Down Entry to Exit Timing REV 1 0 22 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 8500 10600 12800 Unbuffered DDR3 SDRAM DIMM el IXI r maxed tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDEN tACTPDENmax tPRPDENmin 1 Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmax tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entr tWRPDENmin WL 4 tCK av 1019 tWRPDEN ava BL8OTF BL8MRS 4 tWRPDENmax Timing of WRA command to Power Down entry IWRAPDENmin WL 4 WR 1 tWRAPDEN nCK BL8OTF BL8MRS 4 tWRAPDENmax Timing of WR command to Power Down entry BC4MRS tWRPDEN tWRPDENmin WL 2 tCK avg tWRPDENmax Timing of WRA command to Power Down entry tWRAPDENmin WL 2 WR 1 tWRAPDEN BC4MRS tWRAPDENmax tREFPDENmin 1 Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSP
13. x A A A a Es D o x m 2 Power Down Timings Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands tXPDLLmin max 10nCK 24ns tXPDLLmax tCKEmax tCPDEDmin n requiring a locked DLL CKE minimum pulse width Command pass disable delay X tPDmin tCKE min tPDmax 9 tREFI Timing of ACT command to Power Down entry tACTPDENmin 1 REV 1 0 19 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice Power Down Entry to Exit Timing gt U o m z CK CK M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 8500 10600 12800 swe Unbuffered DDR3 SDRAM DIMM el IXI r a a tPRPDENmin 1 Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmax tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entry tWRPDENmin WL 4 tWR tCK avg tWRPDEN nCK BL8OTF BL8MRS 4 tWRPDENmax Timing of WRA command to Power ntr IWRAPDENmin WL 4 WR 1 ae tWRAPDEN MS BL8OTF BL8MRS 4 tWRAPDENmax Timi
14. 12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 4GB 2 Ranks 256Mx8 DDR3 SDRAMs 51 50 DQSO 54 paso 0054 DMO I DM4 1 DM CS 0505 pas DM CS DOS Das DM CS 005 DOGS CS 005 905 Dao N VO 0 DQ32 N VO 0 pai N 1 VO 1 DQ33 01 VO 1 paz N vo2 Vo 2 102 2 N 03 03 D8 pass N 103 D4 D1i2 004 N 104 VO 4 pass N 04 4 005 05 Vo 5 DQ37 N 105 Vo 5 N 06 VO 6 pass 106 VO 6 DQ7 WN V O7 Vo7 za 0039 N vo7 zo Ex Vo7 za DQsi 0955 i past Dass DMI M t DM5 M t DM CS DOS Dos DM CS DOS Das DM CS DOGS DM CS Das Dos N 100 VO 0 N 00 VO 0 N 101 VO 1 DQ41 N 101 VO 1 DQ10 702 2 0042
15. 167 113 113 mA IDD7 Operating Bank Interleave Read Current 2826 3228 3318 mA REV 1 0 15 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 ee Unbuffered DDR3 SDRAM DIMM el Standard Speed Bins DDR3 1066MHz n 2 12 eae Parameter Symbol Min Min Max ACT to internal read or write delaytime IRCO 13 25 f ns IPREcommandperiod RP 13 125 ______ 15 000 ACTto commandperiod tRC_ 50625 5250 n EN EE ae CWL Supported CL Settings BB DDR3 1333MHz Speed Bin RBBB Parameter Symbol Min Max Min Max ACT to internal read or write delay time RCD _______ 12 000 13125 ns PRE command period RP 2000 8125 ns ACT to commandperiod 48000 49 125 ___ ACT to PRE command period a ole m L 5 WL 6 a ojo 1 875 eserved eserved WL 5 1 875 1 500 1 875 Supported CL Settings 5 6 7 8 9 6 7 8 9 nCK nCK if 1 Q iL a iL o ojojo nu o n n n n
16. 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 m s Unbuffered DDR3 SDRAM DIMM el IXIF Command and Address Timing re Se n DLL locking time prec f tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time wets Mode Register Set command cycle time 4 7 tMODmin max 12nCK 15ns tMODmax Mode Register Set command update delay R Ri CCD Q D CAS to CAS command delay O O CK RAS Standard Speed Bins RD max 4nCK 7 5ns tRRDmin max 4nCK 10ns tRRDmax i Purpose Register Recovery Time n min WR roundup tRP tCK avg nCK n z RRD tFAW 37 5 Four activate window for 2KB page size tFAW 5 1 Command and Address setup time to CK base ase referenced to Vih ac Vil ac levels Four activate window for 1KB page size gt gt gt gt 0 1 2 ajala a3ialxls 4 s le m mj m 5 gt E S jele S 3 5 gt gt m Ala 5 2 gt aye 2 23 98 2 2 Q o 3 3 9 g 3 8 3 5 5 18 3 El 5 lt o 3 2 2 2 2 o o o o
17. A0 A14 2GB 4GB and I O inputs BAO BA2 using the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard IIC protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 1 0 1 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 Cel PC3 8500 PC3 10600 PC3 12800 swe Unbuffered DDR3 SDRAM DIMM el IXI r Ordering Information Part Number Speed Organization Power Leads Note M2F1G64CBH4B5P BE DDR3 1066 PC3 8500 533MHz 1 875ns CL 7 M2F1G64CBH4B5P CG DDR3 1333 PC3 10600 667MHz 1 5ns CL 9 M2F2G64CB88B7N BE DDR3 1066 PC3 8500 533MHz 1 875ns CL 7 M2F2G64CB88B7N CG DDR3 1333 PC3 10600 667MHz 1 5ns CL 9 256Mx64 M2X2G64CB88B7N DG DDR3 1600 PC3 12800 800MHz 1 25 5 CL 9 M2F4G64CB8HB5N BE DDR3 1066 PC3 8500 533MHz 1 875ns 9 CL 7 M2F4G64CB8HB5N CG DDR3 1333 PC3 10600 667MHz 1 5ns CL 9 512Mx64 128Mx64 M2X4G64CB8HB5N DG DDR3 1600 PC3 12800 800MHz 1 25ns CL 9 is aid M2F1G64CBH4B9P BE DDR3 1066 8500 533MHz 1 875ns CL 7 M2F1G64CBH4B9P CG DDR3 1333 10600 667MHz 1 5ns
18. Ke ___ Average low pulsewidth pow _______ __ te Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth oos Ke Absolute clock LOW pulse width poes sev Clock Period siter __ __ o Clock Period Jitter during DLL locking period mee eoo o Cyce to Cycle Period siter o Cycle to Period Jitter during DLL locking 10 C __ _ __ _ Min tCK avg min tJIT per min Cumulative erroracross6cycles ________________ pos toss S oom 0 o 2 i 0 o o w Je s o f O o w 08 o 00089 e o Ww Cumulative error across 10 cycles te ow es S Cumulative error across 11 cycles _______ s Cumulative error across 12 cycles tRROe tERR nper tERR nper min 1 0 68In n tJIT per min tERR nper max 1 0 68In n tJIT per max D MM iia aed SL qu DOS DASH to DA skew per group per access ts tps S DQoutput hold tme rom DAS DOSE os ___ __ oo DQ low impedance time from CK CK tLZ DQ 450 225 DQ high impedance time from CK CK tHZ DQ 2 Cumulative error across 13 14 49 50 cycles a 2 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels AC175 tDS base
19. M2F1G64CBH4B9P 1GB 1 Rank 128Mx16 DDR3 SDRAMs FRONT 133 35 0 15 126 0 2 SIDE 4 30Max POPMA 4 25 00 0 2 30 00 0 5 0 15 5 175 1 274 0 07 0 1 L Detail A Detail B o 250 o e E 0 80 4 0 05 Li gt 000 0000 O0000 1 00 Pitch 1 50 0 10 3 8 Units Millimeters REV 1 0 28 05 2010 NANYA TECHNOLOGY CORPORATION notice NANYA reserves the right to change products and specifications without M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 AGB 512M x 64 8500 10600 12800 Unbuffered DDR3 SDRAM DIMM el IXI r Package Dimensions M2F X 2G64CB88B7N 268 1 Rank 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 gt SIDE E e 5 2 7 e d eo Detail A vote Detail B ae A 1 27 0 07 0 10 Detail A Detail B 250 0 80 0 05 oon eU M 1 00 Pitch 1 50 0 10 Units Millimeters REV 1 0 29 05 2010 NANYA TECHNOLOGY CORPORATION 5 notice NANYA reserves the r
20. N 1 04 DQ5 N 05 DQ37 0 5 N 106 1 06 DQ7 N 107 za DQ39 1 07 za 51 NIS DQS5 M past M Dass DM N DM5 N DM CS Das Das DM CS Das Das N 0040 N 100 JN 701 0041 N o1 W 02 0042 N o2 DQi1 03 D1 0043 W 103 05 paiz N 104 DQ44 N 4 DQ13 0 705 0045 5 pai4 6 0046 N 06 0015 7 DQ47 7 WH za H za DQS2 DQS6 JM DQS2 M Dase M T DM2 JMN 4 DM6 N 4 DM CS Das Das DM CS Das Das pais N 100 0048 100 DQ17 o1 DQ49 1 DQ18 N 702 DQ50 N 102 DQi9 N 03 D2 DQ51 W 103 D6 0020 N 1 04 0052 N 104 0021 105 0053 105 0022 N 0054 1 06 0023 107 za 0055 707 za gt AL AL DQS3 JM DQS7 DQS7 DM3 4 DM7 N 4 DM CS Das Das DM CS Das Das 0024 N 00 0056 N 00 0025 NWN 101 0057 N 101 0026 W 102 0058 W 102 DQ 27 N 03 D3 DQ59 D7 0028 04 N 04 0029 5 1 N 5 0030 106 0062 06 707 0063 707 za rn E SCL P SCL VopsPb 9 SPD Ao SPD k
21. o o 5 o O0 o o o 2 5 6 a 2 S B Q p p 5 2 aja s m pm U 8 9 5 9 a 8 2 8 do 3 2 g DQS DQS low impedance time Referenced from RL 1 Referenced from RL BL 2 o e m o 3k eh 3 o S 3 o 3 o tHZ DQS olojo NINN 36 x asies S S amp 2 zz is 9 o o on amp 5 5 la e z 5 8 amp 1ls 5 5 lo to DQS DQS fall ing edge setup time to CK CK rising edge DQS DQS falling edge hold time from CK CK rising edge u 05 2010 tERR nper min 1 0 68In n tJIT per min tERR nper max 1 0 68In n tJIT per max ____ ___ o pe 038 0 ps 3 00 m Note 19 11 ojo AA D 2 lt e vg A lt e tCK avg tCK avg K K 30 300 300 CK avg 055 0 25 025 02 0 18 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X
22. to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge Data Input Output pins Power supplies for core I O Serial Presence Detect Temp sensor and ground for the module Reference voltage for SSTL15 inputs This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor A resistor must be connected from the SDA bus line to on the system planar to act as a pull up This signal is used to clock data into and out of the SPD EEPROM and Temp sensor Address pins used to select the Serial Presence Detect and Temp sensor base address The EVENT pin is reserved for use to flag critical module temperature This signal resets the DDR3 SDRAM NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3
23. 0600 PC3 12800 swe Unbuffered DDR3 SDRAM DIMM el IXI r Revision Log Rev Date Modification 0 1 01 2010 Preliminary Release 0 5 05 2010 Preliminary Release 2 1 0 05 2010 Official Release Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd Kueishan Taoyuan 333 Taiwan R O C Tel 886 3 328 1688 Please visit our home page for more information http www elixir memory com Printed in Taiwan 2010 1 0 33 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
24. 20 23 Minimum Active to Active Refresh delay tRCmin 95 89 24 Minimum refresh recovery delay tRFCmin LSB 00 00 25 Minimum refresh recovery delay tRFCmin MSB 05 05 26 Minimum internal Write to Read command delay tWTRmin 3C 3C 27 Minimum internal Read to Precharge command delay tRTPmin 3C 3C 28 Minimum four active window delay tFAWmin LSB 01 01 29 Minimum four active window delay tFAWmin MSB 90 68 30 SDRAM device output drivers supported 83 83 31 SDRAM device thermal and refresh options 05 05 32 Module Thermal Sensor 00 00 33 SDRAM Device Type 00 00 60 Module height nominal 0 0 61 Module thickness Max 01 01 62 Raw Card ID reference 02 02 63 DRAM address mapping edge connector 00 00 117 Module manufacture ID 83 83 118 Module manufacture ID 0B 0B 119 121 Module manufacturer Information 126 CRC 73 oD 127 CRC F7 2E 128 145 Module part number 146 Module die revision 147 Module PCB revision 150 175 Manufacturer reserved 176 255 Intel Extreme Memory Profile XMP REV 1 0 8 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 ee Unbuffered DDR3 SDRAM DIMM el
25. 63 Vss 73 WE 193 S0 103 0056 223 Vss 14 134 44 164 CB6NC 74 CAS 194 Vw 104 Va 224 0054 15 DOSI 135 d 45 CB2 NC 165 CB7ZNC 75 V 195 105 DQ50 225 0055 16 DQS1 136 Vss 46 CB3 NC 166 Vss 76 SINC 196 A13 106 0051 226 Vss 17 137 Data 47 167 NC TEST 77 197 V 107 227 0060 18 0010 188 0015 48 168 RESET 78 Vp 198 S3 NC 108 0056 228 0061 19 DQ 139 Vss 49 169 CKEINC 79 S2NC 199 Vss 109 0057 229 Vss DM7 20 Vss 140 0020 50 170 Voo 80 200 DQ36 110 Ves 230 DASTE TDQS16 NC 21 paie 141 51 171 15 81 0032 201 DQ37 111 0057 231 50516 TDQS16 22 DQ17 142 Vss 52 2 172 A14 82 202 112 0057 232 Vss DM4 23 Va 143 53 Eng 173 Voo 83 203 00513 113 Vss 233 0062 NC TDQS13 Es NC DOS71 NO 24 0052 144 Vo 174 A2BC DOS 204 00513 114 0058 234 0068 TDQS13 25 0052 145 Vss 55 AM 175 A9 85 DQS4 205 Vs 115 DQ59 235 Vss 26 146 0022 56 7 176 Vas 86 Vas 206 0038 116 Vss 236 Vopseo 27 DQI8 147 57 177 A8 87 207 0039 117 SAO 237 SAI 28 DQI9 148 Vss 58 5 178 AG 88 DQ35 208 Vs 118 SCL 238 SDA 29 Vss 149 0028 59 4 179 Vi 89 Va 209 DO44 119 SA2 239 Vss 30 DQ24 150 29 60 V 180 A3 90 0040 210 0045 120 Vm 240 Vn Note CK1 CK1 CKE1 51 and ODT1 are for 428 modules only REV 1 0 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and spe
26. CU LAN CENE RN crossing to rising DQS DQS crossing _ _ _ _ crossing to rising CK crossing a ERI 1 0 26 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 8500 10600 12800 Unbuffered DDR3 SDRAM DIMM el IXI r Package Dimensions M2F1G64CBH4B5P 1GB 1 Rank 128Mx16 DDR3 SDRAMs FRONT 133 35 0 15 gt SIDE uy e 2 7 4 2 e d Pe Detail A Detail 1 27 0 07 0 10 Detail A Detail B 250 amp 0 80 0 05 gga 1 00 Pitch 1 50 0 10 Units Millimeters REV 1 0 27 05 2010 NANYA TECHNOLOGY CORPORATION 5 notice NANYA reserves the right to change products and specifications without M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 AGB 512M x 64 Cel PC3 8500 PC3 10600 PC3 12800 swe Unbuffered DDR3 SDRAM DIMM el IXI r Package Dimensions
27. CWL 5 ICKAVG ___________ Reserved ns CWL 5 JICKAVGO __________ _ Reserved ns uM Supported CL Settings Supported CWL Settings Optional REV 1 0 17 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Celixir AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1066MHz DDR3 1066 Parameter Symbol Units Min Max Glock Timing __ P Minimum Glock Cycle Time DLL oftmede ft DLLoFF __ e Average Clock Period tag _ Refert Standard Speed Bins des Average righ pulse width 04 te ___ Average low pulsewidth pow _______ __ te Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth os Ke Absolute clock LOW pulsewidth poes Clock Period siter uve o Clock Period Jitter during DLL locking period mee Cyce to Cycle Period iter 00 ___ tts o Cycle to Period Jitter during DLL locking period 160 Duty Cycle iter __ Min tCK a
28. Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time wets Mode Register Set command cycle time nck ____ tMODmin max 12nCK 15ns Mode Register Set command update delay CAS to CAS command delay tDAL min WR roundup tRP tCK avg i Purpose Register Recovery Time A Standard Speed Bins tRAS tRRDmin max 4nCK 6ns tRRD tRRDmax tRRDmin max 4nCK 7 5ns tRRDmax o Four activate window for 1KB size tFAW Four activate window for 2KB page size tFAW Command and Address setup time to CK CK tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK tlH base referenced to Vih dc Vil dc levels Command and Address setup time to CK CK uini tlS base AC150 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input Calibration Timing a gt gt gt gt d d 4 5 amp lt zle lg m m m 5 x E s 5 5 5 3 gt gt v m 5 2 5 D 3 2 a 3 e gt 5 o o o 2 Q ajo 3 3 o g 3 3 3 m 8 3 5 5 8 5 2 5 lt o o o 3 5 2 2 o g E
29. Cumulative error across 10 cycles tRROOen 2656 ps S Cumulative error across 11 cycles ERRO tos S Cumulative error across 12 cycles tRROZe ___ 25 z5 ps S Cumu tERR nper min 1 0 68In n tJIT per min tERR nper max 1 0 68In n tJIT per max SERE Orale Se p git PUN DOS DASH to DA skew per group per access hold rom DAS ko o oos oog 500 250 ps 2 tDS base ac levels AC175 levels tDS base Vi AC150 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 E tLZ DQS tHZ DQS 0 25 ms error across 13 14 49 50 cycles tERR nper olo z jo EX 3 8 lo Q jo 5 ala 2 85 a8 s 5 a lo A amp 50 o 5 o S m S 2 2 E E E E o 3 3 o e e o 5 S m S o a 19 Note 11 e 9 kl m o 5 9 o z 3 o 0 0 5 5 lo la 2 3 5 ig o o 2 s 9 5 amp o jo 2 E 2 5 9 5 5
30. DEN tMRSPDENmax ODT Timings F ODT high time without write command or ODTH4min 4 with write command and BC4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD Power Down with DLL frozen Asynchronous RTT turn off dela d y tAOFPD Power Down with DLL frozen RTT turn on tAON EE RTT Nom and RTT turn off time tAOF tCK avg from ODTLoff reference RTT dynamic change skew tADC aa tCK avg Write Leveling Timings a First DQS DQS rising edge after DOS DOSKdelayafterwrteleveing mode is programmed WIDOSEN CU MN CENE crossing to rising DQS DQS crossing mem _ _ crossing to rising CK crossing a ee pM REV 1 0 23 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Celixir AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1600MHz DDR3 1600 Parameter Symbol Units Min Max Glock Timing ____ Minimum Clock Cycle Time DLL rs Average Clock Period tag _ Refert Standard Speed Bins fps Average righ pulse width 0o
31. M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Celixir Based on DDR3 1066 1333 128Mx16 1GB and DDR3 1066 1333 1600 256Mx8 2GB 4GB SDRAM B Die Features Performance Speed Sort 8500 PC3 10600 PC3 12800 BE CG DG DIMM CAS Latency 7 9 9 fck Clock Frequency 533 667 800 tck Clock Cycle 1 875 1 5 1 25 fDQ DQ Burst Frequency 1066 1333 1600 240 Pin Dual In Line Memory Module UDIMM 128Mx64 1GB 256Mx64 2GB 512Mx64 4GB DDR3 Unbuffered DIMM based on 256Mx8 DDR3 SDRAM B Die devices Intended for 533MHz 667MHz 800MHz applications Inputs and outputs are SSTL 15 compatible Voo 1 5V 0 075V SDRAMs have 8 internal banks for concurrent operation Differential clock inputs Data is read or written on both clock edges DRAM DLL aligns DQ and 005 transitions with clock transitions Address and control signals are fully synchronous to positive clock edge Nominal and Dynamtic On Die Termination support Halogen free product Description Unit MHz ns Mbps Programmable Operation DIMM CAS Latency 6 7 8 9 Burst Type Sequential or Interleave Burst Length BC4 BL8 Operation Burst Read and Write Two different termination values Rtt Nom amp Rtt WR e 14 10 1 row co
32. N 102 2 11 N vos D1 Vo 3 D9 DQ43 N 103 D5 D13 12 N 104 VO 4 DQ44 N 104 V04 DQ13 VV 05 Vo 5 DQ45 105 5 DQi4 06 VO 6 DQ46 N 706 VO 6 DQ15 N 107 zo x 707 0947 N 07 zo x Vo7 za 52 E DQse d DQS2 M DQS6 M DM2 t DM6 DM CS 0605 Das DM CS 005 005 DM CS Das Das DM CS Das 005 DQ16 oo VO 0 DQ48 N 100 VO 0 17 N 1 VO 1 DQ49 01 VO 1 pais o2 o2 DQ50 N 102 Vo 2 N 03 D2 VOS D10 DQ51 N 103 D6 014 704 VO 4 DQ52 704 4 DQ21 05 Vo 5 0053 N 705 VO 5 Da22 06 VO 6 0054 N 1 06 VO 6 107 za Ex 707 0955 wv o7 zo vO7 EN 5 5057 Dass DQS7 DM3 t DM7 t DM CS DOS DOGS DM CS Das Das DM CS Das Das DM 65 Das 005 DQ24 oo VO 0 0056 N 00 VO 0 DQ25 o1 VO 1 DQ57 101 VO 1 pazs vo2 Vo 2 pass N 102 vo2 DQ27 03 D3 Di pass N 103 D7 015 Da28 104 4 N 1 04 VO 4 05 Vo 5 DQ61 705 Vo 5 06 VO 6 DQ62 N 1 06 VO 6 DQ31 107 z 707 za 0063 007 zo x VOo7 za DDR3 9 gt SPD SDRAM Voo Vooo EE 00 015 CKET 1 0 A 13 0 Vnerpa gt 00 015
33. RAS CAS WE N Vss e _ F gt 00 015 ODT 1 0 2 0 S 1 0 Vrerca gt 00 015 BA0 BA2 gt 2 SDRAMs 00 015 A0 A13 gt 13 SDRAMs 00 015 DDR3 RAS RAS SDRAMs 00 015 SDRAM CAS __________ CAS SDRAMs 00 015 1 LM Vos WE J WE SDRAMs 00 015 Ck CKEO p SDRAMs 00 07 SDRAMs 08 015 gt ODT SDRAMs 00 07 gt ODT SDRAMs 08 015 SCL gt 50 p CK SDRAMs D0 D7 3 del l gt SDA CKO SDRAMs 00 07 1 We gt CK SDRAMs 08 015 1 9 22 SDRAMs 08 015 RESET __ RESET SDRAMs 08 015 REV 1 0 05 2010 Notes 1 DQ to I O wiring is shown as recommended but may be changed wr resistor is 2400 1 4 One SPD exists per module DQ DQS DQS ODT DM CKBE S relationships must be maintained as shown For each DRAM a unique ZQ resistor is connected to ground The ZQ NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and speci
34. S s S 3 a 8 EN o o N N Power up and RESET calibration time NIN 0 g E A Normal operation Full calibration time Normal operation Short calibration time i tXPRmin max 5nCK tRFC min 10ns tXPRmax Exit Reset from CKE HIGH to a valid command tXSmin max 5nCK tRFC min 10ns tXSmax XSDLLmin tDLLK min tXSDLLmax tCKESRmin tCKE min 1 nCK tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Exit Self Refresh to commands not requiring a locked DLL LE ns ns ps E Exit Self Refresh to commands requiring a locked DLL 3 Minimum CKE low width for Self Refresh entry to exit timing grz e m e a 3 g al E 8 o Power Down Timings Exit Power Down with DLL on to any valid command tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands tXP tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands XPDLL tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax tCKEmin max 3nCK 5 625ns CKE minimum pulse width tCKE tCKEmax tCPDEDmin 1 nCK
35. SDRAM DIMM Functional Block Diagram 1GB 1 Rank 128Mx16 DDR3 SDRAMs REV 1 0 05 2010 lt BESESBEBS 240 DQS0 JN 4 LDQS 12196 0050 JN 4 1505 DMO N LDM DQ 0 7 DQ o 7 DO 0051 UDQS 0051 0005 DMI UDM 2 DQ 8 15 DQ 8 15 a 5 BEBESKS8s EE 240 2 LDQS 1 0052 1005 DM2 LDM DQ 16 23 0 7 Di DQS3 UDQS 0053 J 0095 a DM3 N 2 DQ 24 31 DQ 8 15 a eo BEBESBS8s Ltt 240 DQS4 LDOS 12196 0054 1005 Ar WE DM4 LDM DQ 32 39 DQ 0 7 D2 DQS5 M UDQS 0055 M 0095 Ww DM5 UDM 2 DQ 40 47 N Days 15 a K5 BEBESBS8s EE 240 Dase LDOS 1 Dase 1005 DM6 LDM 00 48 55 7 D3 DQS7 upas 0057 0095 T DM7 UDM 2 DQ 56 63 DQ 8 15 a eo n e uxr Y bS BBBESSSss vtt lt JH elixir SCL gt SCL A0 SPD DA 1 gt Ai S 0 A2 WP vt 9 gt Vit s SPD TS VnEFCA gt 00 07 gt 00 07 V
36. Settings 2D 3 4 221 SDRAM Minimum Cycle Time tCKmin 0 3 4 222 Minimum CAS Latency Time tAAmin A5 3 4 223 CAS Latencies Supported Least Significant Byte CL MASK 84 3 4 224 CAS Latencies Supported Most Significant Byte CL MASK 00 3 225 Minimum CAS Write Latency Time tCWLmin A5 3 4 226 Minimum Row Precharge Time tRPmin A5 3 4 227 Minimum RAS to CAS Delay Time tRCDmin A5 34 228 Minimum Write Recovery Time tWRmin 02 3 4 229 Upper Nibbles for RAS and tRC 21 3 4 230 Minimum Active to Precharge Time tRASmin Least Significant Byte 3 4 231 Minimum Active to Active Refresh Time tRCmin Least Significant Byte 8F 3 232 Maximum tREFI Time Average Periodic Refresh Interval LSB 37 8 233 Maximum tREFI Time Average Periodic Refresh Interval MSB 00 3 4 234 Minimum Refresh Recovery Time tRFCmin Least Significant Byte 3 4 235 Minimum Refresh Recovery Time tRFCmin Most Significant Byte 08 3 4 236 Minimum Internal Read to Precharge Command Delay Time tRTPmin 69 3 4 237 Minimum Row Active to Row Active Delay Time tRRDmin 54 3 4 238 Upper Nibble for tFAW 01 3 4 239 Minimum Four Activate Window Delay Time tFAWmin amp 3 4 240 Minimum Internal Write to Read Command Delay Time tWTRmin 69 3 241 Write to Read amp Read to Write CMD Turn around Time Pull in 00 3 242 Back to Back CMD Turn aroun
37. _ Intel Extreme Memory Profile ID String OC4A 178 Intel Extreme Memory Profile Organization Type 07 179 Intel Extreme Memory Profile Revision 12 180 Medium Timebase Dividend for Profile 1 01 1 181 Medium Timebase Divisor for Profile 1 08 1 182 Medium Timebase Dividend for Profile 2 01 1 183 Medium Timebase Divisor for Profile 2 0E 1 184 RSVD 1 00 1 185 Module VDD Voltage Level for Profile 1 Certified Settings 2D 1 186 SDRAM Minimum Cycle Time tCKmin 0 2 4 187 Minimum CAS Latency Time tAAmin 5A 24 188 CAS Latencies Supported Least Significant Byte CL MASK 24 24 189 CAS Latencies Supported Most Significant Byte CL MASK 00 2 4 190 Minimum CAS Write Latency Time tCWLmin 5A 2 191 Minimum Row Precharge Time tRPmin 5A 2 4 192 Minimum RAS to CAS Delay Time tRCDmin 5A 2 4 193 Minimum Write Recovery Time tWRmin 78 2 4 194 Upper Nibbles for tRAS and tRC 11 2 4 195 Minimum Active to Precharge Time tRASmin Least Significant Byte 18 2 4 196 Minimum Active to Active Refresh Time tRCmin Least Significant Byte T2 24 197 Maximum tREFI Time Average Periodic Refresh Interval LSB 20 2 198 Maximum tREFI Time Average Periodic Refresh Interval MSB 00 2 199 Minimum Refresh Recovery Time tRFCmin Least Significant Byte 00 2 4 200 Minimum Refresh Recovery Time tRFCmin Most Significant Byte 05 2 4 201 Minimu
38. and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 M Unbuffered DDR3 SDRAM DIMM el IXIr DC Electrical Characteristics and Operating Conditions VDD Supply Voltage 1 425 1 575 VDDQ Output Supply Voltage 1 425 1 5 1 575 V 12 Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Single Ended AC and DC Input Levels for Command and Address VIH CA DC Input Logic High MA 0 100 VDD Vref 0 100 VDD Vref 0 100 VDD V VIL CA DC Input Logic Low vss Vref 0 100 VSS Vref 0 100 VSS Vref 0 100 V 1 VIH CA AC Input Logic High Vref 40 175 _ Note2 Vref 0 175 Note2 Vref 0 175 Note2 V 1 VIL CA AC Input Logic Low Note2 0 175 2 Vref 0 175 Note2 Vref 0 175 V 1 VIH CA AC150 AC Input Logic High Vref 0 15 Note2 Vref 0 15 Note2 Vref 0 15 Note 2 V 1 VIL CA AC150 AC Input Logic Low Note 2 Vref 0 15 Note 2 Vref 0 15 Note 2 Vref 0 15 V 1 2 Reference Voltage for ADD 0 49x VDD 0 51xVDD 0 49x VDD 0 51xVDD 049xVDD 0 51xVDD V 3 4 VnetCA DC CMD Inputs Note 1 For input only pins except RESET Vref VrefCA DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef ma
39. cifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 268 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM elixir Input Output Functional Description Symbol CKO CK1 CKO Input CKEO CKE1 Input 50 51 Input RAS CAS WE Input ODTO ODT1 Input DM8 Input DQS0 2058 2050 0058 2 Input A0 A9 A10 AP A11 Input A12 BC A13 A15 DQO DQ63 Input Vss Supply Vrerpa VREFCA Supply SDA SCL Input SAO SA2 Input EVENT Output RESET Input REV 1 0 05 2010 Type Polarity Cross point Active High Active Low Active Low Active High Active High Cross point Function The system clock inputs All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of A Delay Locked Loop DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operat
40. d Time Pull in 00 3 243 System ADD CMD Rate 1N or 2N mode 1 3 244 Auto Self Refresh Performance Sub 1x Refresh and IDD6 Impacts 00 3 245 Memory Controller Voltage Level for Profile 2D 3 246 253 RSVD 3 254 Vendor Personality Byte for Profile 2 RSVD 3 1 Global Parameters used across all profiles 2 Utilized for Profile 1 Enthusiast Certified Settings 3 Utilized for Profile 2 Extreme Settings 4 Parameter utilized in the same fashion as the standard DDR3 SPD byte with the exception that it may exceed the DDRx SDRAM datasheet REV 1 0 12 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 Cel PC3 8500 PC3 10600 PC3 12800 swe Unbuffered DDR3 SDRAM DIMM el IXI r Environmental Requirements Symbol Parameter Rating Units Topr Module Operating Temperature Range ambient 0 to 55 C 3 Hopr Operating Humidity relative 10 to 90 1 TsrG Storage Temperature Plastic 55 to 100 1 Storage Humidity without condensation 5 to 95 1 Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a stress rating only and device functional
41. e Self Refresh Exit SRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Exit Self Refresh to commands not requiring a locked DLL LE ns ns ps E Exit Self Refresh to commands requiring a locked DLL 3 Minimum CKE low width for Self Refresh entry to exit timing grz e m 3 g al E 8 eo Power Down Timings Exit Power Down with DLL on to any valid command tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands tXP tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands XPDLL tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax m tCKEmin max 3nCK 5ns CKE minimum pulse width tCKE tCKEmax tCPDEDmin 1 tCPDEDmin tPDmin tCKE min Command pass disable delay U Power Down Entry to Exit Timing REV 1 0 25 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 8500 10600 12800 Unbuffered DDR3 SDRAM DIMM el IXI r tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDEN tACTPDENmax tPRPDENmin 1 Timing
42. echarge Time tRPmin 5A 2 4 192 Minimum RAS to CAS Delay Time tRCDmin 5A 2 4 193 Minimum Write Recovery Time tWRmin 78 2 4 194 Upper Nibbles for RAS and tRC 11 2 4 195 Minimum Active to Precharge Time tRASmin Least Significant Byte 18 2 4 196 Minimum Active to Active Refresh Time tRCmin Least Significant Byte 72 2 4 197 Maximum tREFI Time Average Periodic Refresh Interval LSB 20 2 198 Maximum tREFI Time Average Periodic Refresh Interval MSB 00 2 199 Minimum Refresh Recovery Time tRFCmin Least Significant Byte 00 2 4 200 Minimum Refresh Recovery Time tRFCmin Most Significant Byte 05 2 4 201 Minimum Internal Read to Precharge Command Delay Time tRTPmin 3C 24 202 Minimum Row Active to Row Active Delay Time tRRDmin 30 2 4 203 Upper Nibble for tFAW 00 2 4 204 Minimum Four Activate Window Delay Time tFAWmin FO 2 4 205 Minimum Internal Write to Read Command Delay Time tWTRmin 3C 24 206 Write to Read amp Read to Write CMD Turn around Time Pull in 00 2 207 Back to Back CMD Turn around Time Pull in 00 208 System ADD CMD Rate 1N or 2N mode 10 2 209 Auto Self Refresh Performance Sub 1x Refresh 1006 Impacts 00 2 210 Memory Controller Voltage Level for Profile 1 2D 2 211 218 _ RSVD 2 219 Vendor Personality Byte for Profile 1 RSVD 00 3 4 220 Module VDD Voltage Level for Profile 2 Extreme
43. fications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM elixir Serial Presence Detect M2F1G64CBH4B5 9 P 1GB 1 Rank 128Mx16 DDR3 SDRAMs S Serial PD Data Entry Hex Byte Description CG 0 CRC range EEPROM bytes bytes used 92 92 1 SPD revision 10 10 2 DRAM device type 0B 0B 3 Module type form factor 02 02 4 SDRAM Device density and banks 03 03 5 SDRAM device row and column count 11 11 6 Module minimum nominal voltage 00 00 7 Module ranks and device DQ count 02 02 8 ECC tag and module memory Bus width 03 03 9 Fine timebase dividend divisor in ps 52 52 10 Medium timebase dividend 01 01 11 Medium timebase divisor 08 08 12 Minimum SDRAM cycle time tCKmin OF 0 13 Reserved 00 00 14 CAS latencies supported 1 3C 15 CAS latencies supported 00 00 16 Minimum CAS latency time tAAmin 69 69 17 Minimum write recovery time tWRmin 78 78 18 Minimum CAS to CAS delay tRCDmin 69 69 19 Minimum Row Active to Row Active delay tRRDmin 50 3C 20 Minimum row Precharge delay tRPmin 69 69 21 Upper nibble for tRAS and tRC 11 11 22 Minimum Active to Precharge delay tRASmin 2C
44. he case surface temperature on the center top side of the DRAM For measurement conditions please refer to the document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case temperature must be maintained between 0 to 85 under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 and 95 case temperature Full specifications are supported in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh to 7 8 5 in the Extended Temperature Range Please refer to supplier data sheet and or the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 0b and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 Ob Please refer to the supplier data sheet and or the DIMM SPD for Auto Self Refresh option availability Extended Temperature Range support and tREFI requirements in the Extended Temperature Range REV 1 0 13 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products
45. ifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 68 _ Unbuffered DDR3 SDRAM DIMM el Serial Presence Detect M2X4G64CB8HBON M2X4G64CB8HBON 4GB 2 Ranks 256Mx8 DDR3 SDRAMs NS Serial PD Data Entry Hex Byte Description BE CG D i 176 177 Intel Extreme Memory Profile ID String 0C4A 178 Intel Extreme Memory Profile Organization Type 07 179 Intel Extreme Memory Profile Revision 12 180 Medium Timebase Dividend for Profile 1 01 1 181 Medium Timebase Divisor for Profile 1 08 1 182 Medium Timebase Dividend for Profile 2 01 1 183 Medium Timebase Divisor for Profile 2 0E 1 184 RSVD 1 00 1 185 Module VDD Voltage Level for Profile 1 Certified Settings 2D 1 186 SDRAM Minimum Cycle Time tCKmin 0 2 4 187 Minimum CAS Latency Time tAAmin 2 4 188 CAS Latencies Supported Least Significant Byte CL MASK 24 2 4 189 CAS Latencies Supported Most Significant Byte CL MASK 00 2 4 190 Minimum CAS Write Latency Time tCWLmin 5A 2 191 Minimum Row Pr
46. ight to change products and specifications without M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 AGB 512M x 64 Cel PC3 8500 PC3 10600 PC3 12800 swe Unbuffered DDR3 SDRAM DIMM el IXI r M2F X 2G64CB88BHN 2GB 1 Rank 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 126 0 2 SIDE 4 30Max Bosnie 25 00 0 2 30 00 0 5 0 15 5 175 1 27 0 07 0 1 L Detail A Detail B o 250 o 0 80 0 05 gt OUDE 110000 OMOU000 ES 1 00 Pitch 1 50 0 10 Units Millimeters REV 1 0 30 05 2010 NANYA TECHNOLOGY CORPORATION notice NANYA reserves the right to change products and specifications without M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 8500 10600 12800 Unbuffered DDR3 SDRAM DIMM el IXI r Package Dimensions M2F X 4G64CB8HBSN 4GB 2 Ranks 256Mx8 DDR3 SDRAMs FRONT 133 35 0 15 g
47. ions continue Rank 0 is selected by 50 Rank 1 is selected by 51 When sampled at the positive rising edge of CK and falling edge of CK signals RAS CAS WE define the operation to be executed by the SDRAM Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 SDRAM mode register The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect The data strobes associated with one data byte sourced with data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window DQS signals are complements and timing is relative to the cross point of respective DQS and DGS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board to Vss and DDR3 SDRAM mode registers programmed appropriately Selects which DDR3 SDRAM internal bank of four or eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK In addition
48. ising edge ____ tosu oas REV 1 0 24 05 2010 225 CK avg cag 0 55 o ojoje w RIO gio oio NIN oio Qo 3E o o TIT o 2 2 mm 5 5 5 la o 5 8 5 a NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 m s Unbuffered DDR3 SDRAM DIMM el IXIF Command and Address Timing Se ENEMY DLL locking time tDLLK prec tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time wets Mode Register Set command cycle time nck ____ tMODmin max 12nCK 15ns Mode Register Set command update delay CAS to CAS command delay tDAL min WR roundup tRP tCK avg i Purpose Register Recovery Time A Standard Speed Bins tRAS tRRDmin max 4nCK 6ns tRRD tRRDmax tRRDmin max 4nCK 7 5ns tRRDmax Four activate window for 1KB page size tFAW Four activate window fo
49. lumn rank Addressing for 1GB 15 10 1 row column rank Addressing for 2GB e 15 10 2 row column rank Addressing for 4GB Extended operating temperature rage Auto Self Refresh option Serial Presence Detect Gold contacts 1GB SDRAMs are in 96 ball BGA Package 2GB SDRAMs are in 78 ball BGA Package 4GB SDRAMs are in 78 ball BGA Package RoHS compliance M2F1G64CBH4B5 9 P M2F X 2G64CB88B7N M2F X 4G64CB8HB5N M2F X 2G64CB88BHN M2F X 4G64CB8HBS9N are 240 Double Data Rate 3 DDR3 Synchronous DRAM Unbuffered Dual In Line Memory Module UDIMM organized as one rank of 128Mx64 1GB 256Mx64 2GB and two ranks of 512Mx64 4GB high speed memory array Modules use four 128Mx16 1GB 96 ball BGA packaged devices eight 256Mx8 2GB 78 ball BGA packaged devices and sixteen 256Mx8 4GB 78 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SDRAM DIMMs provide a high performance flexible 8 byte interface in a 5 25 long space saving footprint The DIMM is intended for use in applications operating of 533MHz 667MHz 800MHz clock speeds and achieves high speed data transfer rates of 1066Mbps 1333Mbps 1600Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A13 1GB
50. m Internal Read to Precharge Command Delay Time tRTPmin 3C 24 202 Minimum Row Active to Row Active Delay Time tRRDmin 30 24 203 Upper Nibble for tFAW 00 2 4 204 Minimum Four Activate Window Delay Time tFAWmin F0 24 205 Minimum Internal Write to Read Command Delay Time tWTRmin 3C 24 206 Write to Read amp Read to Write CMD Turn around Time Pull in 00 2 207 Back to Back CMD Turn around Time Pull in 00 2 208 System ADD CMD Rate 1N or 2N mode 10 2 209 Auto Self Refresh Performance Sub 1x Refresh and IDD6 Impacts 00 2 210 Memory Controller Voltage Level for Profile 1 2D 2 211 218 _ RSVD 2 219 Vendor Personality Byte for Profile 1 RSVD 00 3 4 220 Module VDD Voltage Level for Profile 2 Extreme Settings 2D 34 221 SDRAM Minimum Cycle Time tCKmin 0 3 4 222 Minimum CAS Latency Time tAAmin A5 34 223 CAS Latencies Supported Least Significant Byte CL MASK 84 34 224 CAS Latencies Supported Most Significant Byte CL MASK 00 3 225 Minimum CAS Write Latency Time tCWLmin A5 34 226 Minimum Row Precharge Time tRPmin A5 3 4 227 Minimum RAS to CAS Delay Time tRCDmin A5 3 4 228 Minimum Write Recovery Time tWRmin ER 2 3 4 229 Upper Nibbles for RAS and tRC 21 3 4 230 Minimum Active to Precharge Time tRASmin Least Significant Byte EA 34 231 Minimum Active to Active Refresh Time tRCmin Least Significant Byte
51. min MSB 2C F0 F0 30 SDRAM device output drivers supported 83 83 83 31 SDRAM device thermal and refresh options 05 05 05 32 Module Thermal Sensor 00 00 00 33 SDRAM Device Type 00 00 00 60 Module height nominal OF OF OF 61 Module thickness Max 11 11 11 62 Raw ID reference 01 01 01 63 DRAM address mapping edge connector 01 01 01 117 Module manufacture ID 83 83 83 118 Module manufacture ID 0B 0B 0B 119 121 Module manufacturer Information 126 CRC 68 2A D4 127 CRC 59 FO 42 128 145 Module part number 146 Module die revision 3e 147 Module PCB revision 150 175 Manufacturer reserved 176 255 Intel Extreme Memory Profile XMP REV 1 0 10 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Intel Extreme Memory Profile definition elixir Serial Presence Detect M2X2G64CB88B7N M2X2G64CB88BHN 2GB 1 Rank 256Mx8 DDR3 SDRAMs T Serial PD Data Entry Hex Byte Description CEN DG Note 176 177
52. n n n n n n CL 10 S ns S S S S S S S S ns ns ns S ns m 1 o o o mu Optional REV 1 0 16 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 Cel PC3 8500 PC3 10600 PC3 12800 swe Unbuffered DDR3 SDRAM DIMM el IXI r DDR3 1600MHz Speed Bin DDR3 1600 CL nRCD nRP 9 9 9 DG Parameter O o 1 Symo Min ___ ACT to internal read or write delay time RCD ias e ns PRE command period o Re o 1125 Jn ACT to ACT REF to command _____________ 5____________ 8500 ____ jns CWL 5 JicCKAVGQ ___________2 500 3300 1 esr hei n ICKAVG Reserved Reserved __ ns CWL 5 ICKAVGQ j250 830 ___ jn ER 7 Te CWL 7 JICKAVG jReseved Reserved ns CWL 5 ICKAVG jReseved Reserved ns 7___________ ICKAVG Reserved Reserved ns CWL 5 JICKAVGQ ___________ Reserved ns
53. ng of WR command to Power Down entry BC4MRS tWRPDEN tWRPDENmin WL 2 tCK avg tWRPDENmax nck Timing of WRA command to Power Down entry tWRAPDENmin WL 2 WR 1 tWRAPDEN nCK BC4MRS tWRAPDENmax tREFPDENmin 1 Timing of REF command to Power Down entry tREFPDEN n tREFPDENmax tMRSPDENmin tMOD min tMRSPDENmax el ODT Timings po eS Se ER ODT high time without write command or ODTH4min 4 ODTH4 nCK with write command and BC4 ODTH4max ODT high ti ith Write d and BL8 ODTH8 CK me rite command an n ds ODTH8max Asynchronous RTT turn on delay tAONPD 2 Power Down with DLL frozen NEN ees o C Timing of MRS command to Power Down entry tMRSPDEN C Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on RTT_Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew Write Leveling Timings ai es First DQS DQS rising edge after tWLMRD nCK write leveling mode is programmed DOS DQS4 delay after write leveling mode is programmed 025 0 o ST Write levelin ime from rising CK ite leveling setup time from rising WLS 245 crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS tWLH 245 crossing to rising CK CK crossing Write leveling output delay WLO __ ls Write leveling output error Lo 3 1 2 Jd p
54. o F 3 9 00 07 Vss 9 D0 D7 SPD Temp sensor gt 00 03 gt D0 D3 04 07 p gt D4 D7 EVENT p Temp Sensor RESET p 00 07 Notes 1 DQ wiring may differ from that shown however DQ DM DQS and DQS relationships are maintained as shown NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 2GB 1 Rank 256Mx8 DDR3 SDRAMs REV 1 0 05 2010 elixir 50 paso M pas4 M DQSO M DQS4 M DMO N DM4 N DM CS Das 0505 DM CS Das Das Dao N DQ32 N 1 00 pai N VO 1 DQ33 N VO 1 N o2 N 102 N 103 0035 N 1 03 D4 DQ4 04 DQ36
55. of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmax tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entr tWRPDENmin WL 4 tCK av 1019 tWRPDEN ava BL8OTF BL8MRS 4 tWRPDENmax Timing of WRA command to Power Down entry IWRAPDENmin WL 4 WR 1 tWRAPDEN nCK BL8OTF BL8MRS 4 tWRAPDENmax Timing of WR command to Power Down entry BC4MRS tWRPDEN tWRPDENmin WL 2 tCK avg tWRPDENmax Timing of WRA command to Power Down entry tWRAPDENmin WL 2 WR 1 tWRAPDEN BC4MRS tWRAPDENmax tREFPDENmin 1 Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings F ODT high time without write command or ODTH4min 4 with write command and BC4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD Power Down with DLL frozen Asynchronous RTT turn off dela d y tAOFPD Power Down with DLL frozen RTT turn on tAON EE RTT Nom and RTT turn off time tAOF tCK avg from ODTLoff reference RTT dynamic change skew tADC aa tCK avg Write Leveling Timings a First DQS DQS rising edge after ee DOS DAS delay after write leveling mode is programmed
56. r 2KB page size tFAW Command and Address setup time to CK tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK tlH base referenced to Vih dc Vil dc levels Command and Address setup time to CK tlS base AC150 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input Calibration Timing gt gt gt gt d d 4 5 amp lt zle lg m m m 5 x E s 5 5 5 3 gt gt v m 5 2 5 D 3 2 a 3 e gt 5 o o o 2 Q ajo 3 3 o g 3 3 3 m 8 3 5 5 8 5 2 5 3 lt a o o o 3 5 2 2 o g E S s S 3 8 8 zb o o N N Power up and RESET calibration time A Normal operation Full calibration time NIN 5 8 Z 2 Normal operation Short calibration time 1 tXPRmin max 5nCK tRFC min 10ns tXPRmax Exit Reset from CKE HIGH to a valid command tXSmin max 5nCK tRFC min 10ns tXSmax XSDLLmin tDLLK min tXSDLLmax tCKESRmin tCKE min 1 nCK tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement befor
57. r Down Current Slow Exit 33 48 51 mA IDD2P1 Precharge Power Down Current Fast Exit 104 132 143 mA IDD2Q _ Quiet Standby Current 167 204 185 mA IDD2N Precharge Standby Current 182 220 243 mA IDD3P Active Power Down Current 114 144 158 mA IDD3N Active Standby Current 236 231 255 mA IDD4R Operating Burst Read Current 1011 1302 1510 mA IDDAW Operating Burst Write Current 1028 1239 1438 mA IDD5B Burst Refresh Current 1531 1507 1531 mA IDD6 Self Refresh Current Normal Temperature Range 83 56 56 mA IDD7 Operating Bank Interleave Read Current 2590 2997 3062 mA Operating Standby and Refresh Currents Toase 0 85 C Vona Voo 1 5V 0 075V 4GB 2 Ranks 256Mx8 DDR3 SDRAMs ET PC3 8500 PC3 10600 PC3 12800 Symbol Parameter Condition BE CG 06 Unit IDDO Operating One Bank Active Precharge Current 813 810 864 mA IDD1 Operating One Bank Active Read Precharge Current 961 980 1045 mA IDD2PO Precharge Power Down Current Slow Exit 66 95 102 mA IDD2P1 Precharge Power Down Current Fast Exit 209 264 285 mA IDD2Q Precharge Quiet Standby Current 333 408 370 mA IDD2N Precharge Standby Current 364 440 486 mA IDD3P Active Power Down Current 228 289 317 mA IDD3N Active Standby Current 472 461 510 mA IDD4R Operating Burst Read Current 1247 1533 1765 mA IDD4W Operating Burst Write Current 1264 1470 1693 mA IDD5B Burst Refresh Current 1767 1737 1786 mA IDD6 Self Refresh Current Normal Temperature Range
58. red DDR3 SDRAM DIMM el Operating Standby and Refresh Currents Tcase 0 C 85 C 1 5V 0 075V 1GB 1 Rank 128Mx16 DDR3 SDRAMs PC3 8500 10600 Symbol Parameter Condition BE Unit IDDO Operating One Bank Active Precharge Current 289 310 mA IDD1 Operating One Bank Active Read Precharge Current 424 456 mA IDD2P0 Precharge Power Down Current Slow Exit 21 21 mA IDD2P1 Precharge Power Down Current Fast Exit 62 69 mA DD2Q Precharge Quiet Standby Current 92 104 mA DD2N Precharge Standby Current 100 113 mA IDD3P Active Power Down Current 67 74 mA DD3N Active Standby Current 104 118 mA DD4R Operating Burst Read Current 759 922 mA DD4W Operating Burst Write Current 746 899 mA IDD5B Burst Refresh Current 732 746 mA IDD6 Self Refresh Current Normal Temperature Range 25 25 mA IDD7 Operating Bank Interleave Read Current 1148 1338 mA Operating Standby and Refresh Currents Toase 0 85 Voo 1 5V 0 075V 2GB 1 Rank 256Mx8 DDR3 SDRAMs an PC3 8500 PC3 10600 PC3 12800 5 Symbol Parameter Condition BE 66 06 Unit IDDO Operating One Bank Active Precharge Current 577 579 609 mA IDD1 Operating One Bank Active Read Precharge Current 725 750 790 mA IDD2PO Precharge Powe
59. t SIDE wo ee ij 4 00 B E 51 e E Detail A Ln Detail B Ue NT I 1 27 0 07 0 10 BACK Detail A Detail B 25b 0 80 0 05 Dec 1 00 Pitch 1 50 0 10 Units Millimeters Note Device position and scale are only for reference REV 1 0 31 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HB5N M2F X 4G64CB8HBON 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 M Unbuffered DDR3 SDRAM DIMM el M2F X 4G64CB8HB9N 4GB 2 Ranks 256 8 DDR3 SDRAMs FRONT 133 35 0 15 126 00 0 2 5 60 gt 25 00 0 2 30 00 0 5 0 15 1 274 0 07 Detail Detail 250 e S RE 0 80 0 05 4 00 10000 00 5 1 00 Pitch 1 50 4 0 10 Units Millimeters Co REV 1 0 32 05 2010 NANYA TECHNOLOGY CORPORATION notice NANYA reserves the right to change products and specifications without M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 Cel PC3 8500 PC3 1
60. ternal Read to Precharge command delay tRTPmin 3 3C 3C 28 Minimum four active window delay tFAWmin LSB 01 00 00 29 Minimum four active window delay tFAWmin MSB 2C F0 F0 30 SDRAM device output drivers supported 83 83 83 31 SDRAM device thermal and refresh options 05 05 05 32 Module Thermal Sensor 00 00 00 33 SDRAM Device Type 00 00 00 60 Module height nominal OF OF OF 61 Module thickness Max 01 01 01 62 Raw Card ID reference 01 01 01 63 DRAM address mapping edge connector 01 01 01 117 Module manufacture ID 83 83 83 118 Module manufacture ID 0B 0B 0B 119 121 Module manufacturer Information 126 CRC 47 05 FB 127 CRC 29 80 32 128 145 Module part number 146 Module die revision 147 Module PCB revision 150 175 Manufacturer reserved 176 255 Intel Extreme Memory Profile XMP REV 1 0 9 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 28 _ Unbuffered DDR3 SDRAM DIMM el Serial Presence Detect M2F X 4G64CB8HB5N M2F X 4G64CB8HB9N 4GB 2 Ranks 256 8 DDR3 SDRAMs
61. vg min tJIT per min tERR 6per 00 008 os S o oo ts es S L ge p m e _ ____ _ 0 0x pe Cumulative error aoross 7 oyoles __ tos S Cumulative error across 8 cycles ERR __27 rt Cumulative error across cycles 22 Cumulative error across 10 29 2 Cumulative error across 11 cycles ERR 287 27 s o Cumulative error across i2cydes errazen __ tees Cumulative error across n 13 14 49 50 cycles tERR nper olo z jo EX 3 8 lo Q jo 5 ala 2 85 a8 s 5 a lo A amp o 5 o S m S tDS base ac levels AC175 levels tDS base Vi AC150 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 E tLZ DQS 2 2 E E E E o 3 3 o e e o 5 S m S o T m o 5 5 5 o 3 o olo lo 560 91919 a 2228 lo e e 315 12 3 I3 a 5 5 BE o 2 olo z simip sible 5 5 0 0 o 5 3 2 3 3 gt o 5 5 o o g o
62. y not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Single Ended AC and DC Input Levels for E a DM VIH DQ DC DC Input Logic High Vref 0 100 VDD Vref 0 100 VDD Vref 0 100 VDD V VIL DQ DC DC Input Logic Low vss Vref 0 100 vss Vref 0 100 vss Vref 0 100 V 1 VIH DQ AC AC Input Logic High Vref 0 175 Note2 Vref 0 15 2 Vref 4 0 15 Note2 V 1 2 5 VIL DQ AC Input Logic Low Note2 0 175 2 Vref 0 15 Note2 0 15 V 1 2 5 Lr Voltage for DQ DM 0 49x VDD 0 51 xVDD 0 49xVDD 0 51 x VDD 0 49xVDD O 51xVDD V 3 4 Note 1 For input only pins except RESET Vref VrefDQ DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 Single ended swing requirement for DQS DQS is 350 mV peak to peak Differential swing requirement for DQS DQS is 700 mV peak to peak REV 1 0 14 05 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5P M2F1G64CBH4B9P M2F X 2G64CB88B7N M2F X 2G64CB88BHN M2F X 4G64CB8HBSN M2F X 4G64CB8HB9N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 68 _ Unbuffe

Elixir DDR3 1GB

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