Elixir M2F4G64CB8HB5N-CG memory module
Contents
1. DM CS DGS Das DM CS Das 095 N woo voo N o1 VO 1 vo2 O2 N vos DO VO 3 08 N 04 4 WH 5 5 N 0 06 VO 6 NM voz zi VO7 za 7 DM CS 5 bas DM CS DOS DOS N oo voo N voi VO 1 o2 VO 2 N vos D1 D9 N 04 O 4 N 05 5 N voe N 1 07 Vo 7 zi 7 DM CS 098 DM CS DOGS DAS N roo N voi VO 1 M VO 2 O2 N vos D2 D10 N 04 VO 4 N 05 yo 5 O6 VO 6 N 07 Vo 7 M T DM CS Das 09 DM CS DOGS DOS N roo o1 VO 1 Wie VO 2 vos D3 VO 3 011 N 004 1O 4 M VO 5 5 N voe VO 6 N 07 O7 za 20 DDR3 SDRAM CKE 1 0 13 0 RAS CAS WE V ODT 1 0 BA 2 0 ui S 1 0 DDR3 SDRAM CK voo SCL SCL sao 9 A0 SPD 4 SDA sai 1 gt A2 0054 0954 DM4 0932 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 0939 0055 0955 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 00953 0954 0955 0057 0957 DM7 0956 0957 DQ58 DQ52. Detail Detail 2 50 0 80 0 05 it nahe 0000 0100000 1 00 Pitch 1 50 0 10 Units Millimeters REV 1 1 26 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Cel a Unbuffered DDR3 SDRAM DIMM el Package Dimensions M2F2G64CB88B7N 2GB 1 Rank 256 8 DDR3 SDRAMs FRONT 133 35 0 15 gt SIDE wo a e 2 7 l e H 2 Detail A Detail TE 1 27 0 10 M BACK Detail A Detail 250 amp 0 80 0 05 010000 1 00 Pitch 1 50 0 10 Units Millimeters REV 1 1 27 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M 64 PC3 8500 PC3 10600 PC3 12800 Cel wn Unbuffered DDR3 SDRAM DIMM el Package Dimensions M2F2G64CB88BHN 2GB 1 Rank 256 8 DDR3 SDRAMs FRONT 133 35 0 15
3. 00 07 opurevas BEBEESBS8s tte 240 Dase 1005 12196 0056 pas 2095 vE Notes DQ 48 55 W DbQ 0 7 D3 1 DQ wiring may differ from that shown however DQ DM DQS7 UDQS DQS and DQS relationships are maintained as shown DQS7 JN 0095 DM7 UDM gt DQ 56 63 DQ 8 15 a ceo opurxuhRhs BRRESEESBS E CIT VDD 5 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 2GB 1 Rank 256Mx8 DDR3 SDRAMs REV 1 1 10 2010 eixir 50 0050 M 56954 paso DQS4 DM4 N DM CS Das Das DM CS DOS DOS N oo DQ32 N 100 pai N 4 01 2033 101 paz 102 102 VV 103 Do 0035 N 103 D4 DQ4 04 2036 4 DQ5 105 2037 105 pas N 4 106 2038 N 6 207 107 za 3 DQ39 N 07 20 DQsi M 0055 0051 DQS5 D
4. Cumulative erroracross6cycles Cumualveemoracoss7cydes __ ts S Cumulative error across 8 cycles tERR a Cumulative error aoross 9 oyoles 224 eps S Cumulative error across 10 cycles ea sts S Cumulative error across 11 cycles Cumulative error across i2cydes 22 S tERR nper min 1 0 68In n tJIT per min Cumulative error across 13 14 49 50 cycles tERR nper tERR nper max 1 0 68In n tJIT per max usn pm m o eS a DOS DAS to DA skew per group peraccess feasa DO output hold ime tom DAS DASE DAlow impedance time tom CK 0 S DQ high impedance ime cK KK zoo cps S tDS Data setup time to DQS DQS referenced to Vih ac Vil ac levels 175 25 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels 150 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 DQandDMipupusewidhforeachinut ow pg eM GN NN DOQS DOS differential READ Preamble meE oo 9 DOS DOS differential READ Postamble eest os DOS DASE differential outputhightime OSH os DOS DASE differential outputowtime DOS DOSE d
5. REV 1 1 22 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M 64 Cel PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el DLL locking time prec tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time wets rs Mode Register Set command cycle time ooo ck tMODmin max 12nCK 15ns Mode Register Set command update delay iMODma to internal read or write delaytime RDP command period ACTtoACTor REF command period RE to CASH command delay eeo Auto precharge write recovery precharge time _ _ _ eek Multi Purpose Register Recovery Time 00 03 ck ACTIVE to PRECHARGE command period eas Standard Speed Bins Jooo tRRDmin max 4nCK ens ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin 4 7 5ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size IFAW Ww Four activate window for 2KB page size IFAW Command Add
6. 126 0 2 SIDE 4 30Max e 4 25 00 0 2 30 00 0 5 0 15 5 175 47 00 PS Detail A 71 00 Perike 1 27 0 1 5 00 Detail Detail 2 50 0 80 0 05 it nahe 0000 0100000 1 00 Pitch 1 50 0 10 Units Millimeters REV 1 1 28 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Cel a Unbuffered DDR3 SDRAM DIMM el Package Dimensions M2F4G64CB8HBSN 4GB 2 Ranks 256 8 DDR3 SDRAMs FRONT 133 35 0 15 ii gt SIDE wo 0 4 00 Max 9 e E Detail A oe Detail B 5 175 47 00 71 00 L BACK Detail A Detail 250 o 0 80 0 05 EE fal 0000 010000 1 00 Pitch 1 50 0 10 Units Millimeters Note Device position and scale are only for reference REV 1 1 29 10 2010 NANYA TECHNOLOGY COR
7. prec tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time wee Pts Mode Register Set command cycle time m tMODmin max 12nCK 15ns Mode Register Set command update delay iMODma to internal read or write delaytime RDP command period ACT or REF command period RE to CASH command delay Auto precharge write recovery precharge time ______ WReromdupiRP Kavg eek Multi Purpose Register Recovery Time o ck ACTIVE to PRECHARGE command period RAS Standard Speed Bins tRRDmin max 4nCK ens ACTIVE to ACTIVE command period for 1KB page size tRRDmax tRRDmin 4 7 5ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size IFAW pot Four activate window for 2KB page size IFAW prs Command and Address setup time to CK P tlS base 65 referenced to Vih ac Vil ac levels Command and Address hold time from CK tlH base 140 referenced to Vih dc Vil dc levels Command and Address setup time to CK tlS base AC150 65 125 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input v p o Cal
8. ACT Auto precharge write recovery precharge time _ _ eek Multi Purpose Register Recovery Time ACTIVE to PRECHARGE commandperiod eas Standard Speed Bins Jooo ACTIVE to ACTIVE command period for 1KB size maamnckzsns _ tRRDmin max 4nCK 10ns ACTIVE to ACTIVE command period for 2KB page size tRRDmax Four activate window for 1KB page size FAW Four activate window for 2KB page size tFAW es Command and Address setup time to CK CK tlS base 125 referenced to Vih ac Vil ac levels Command and Address hold time from CK tlH base 200 referenced to Vih dc Vil dc levels Command and Address setup time to CK tlS base AC150 1254150 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input a es ee NN Calibralion Timing LE a E Power up and RESET calibration time tZQinit Normal operation Full calibration time Ope ck S Normal operation Short calibration time 12963 Reset Timing pe tXPRmin 5 tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR max ne tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax tXSDLLmin tDLLK min Exit Self Refresh to commands req
9. decoder when high When the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by SO Rank 1 is selected by 1 When sampled at the positive rising edge of CK and falling edge of CK signals RAS CAS WE define the operation to be executed by the SDRAM Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 SDRAM mode register The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect The data strobes associated with one data byte sourced with data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window DQS signals are complements and timing is relative to the cross point of respective DQS and DAQS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board Vss and DDR3 SDRAM mode registers programmed appropriately Selects which DDR3 SDRAM internal bank of four or eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write command cycle defines the c
10. 03 03 9 Fine timebase dividend divisor in ps 52 52 52 10 Medium timebase dividend 01 01 01 11 Medium timebase divisor 08 08 08 12 Minimum SDRAM cycle time tCKmin OF 0 0 13 Reserved 00 00 00 14 CAS latencies supported 1 3C FC 15 CAS latencies supported 00 00 00 16 Minimum CAS latency time tAAmin 69 69 69 17 Minimum write recovery time tWRmin 78 78 78 18 Minimum CAS to CAS delay tRCDmin 69 69 69 19 Minimum Row Active to Row Active delay tRRDmin 50 3C 3C 20 Minimum row Precharge delay tRPmin 69 69 69 21 Upper nibble for tRAS and tRC 11 11 11 22 Minimum Active to Precharge delay RASmin 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin 95 89 81 24 Minimum refresh recovery delay tRFCmin LSB 00 00 00 25 Minimum refresh recovery delay tRFCmin MSB 05 05 05 26 Minimum internal Write to Read command delay tWTRmin 3C 3C 3C 27 Minimum internal Read to Precharge command delay tRTPmin 3C 3C 3C 28 Minimum four active window delay tFAWmin LSB 01 01 01 29 Minimum four active window delay tFAWmin MSB 90 68 40 30 SDRAM device output drivers supported 83 83 83 31 SDRAM device thermal and refresh options 05 05 05 32 Module Thermal Sensor 00 00 00 33 SDRAM Device Type 00 00 00 60 Module height nominal 0 0 0 61 Module thickness 01 01 01 62 Raw Card ID reference 02 02 02 63 DRAM address mapping edge connector 00 00 00 117 Module manufacture ID 83 83 83 118 Module manufacture ID 0B 0B 0B 119 121 Module manuf
11. 15 Note 2 V 1 VIL CA AC150 AC Input Logic Low Note 2 Vref 0 15 Note 2 Vref 0 15 Note 2 Vref 0 45 V 1 2 Reference Voltage for ADD 0 49x VDD 0 51 xVDD 0 49xVDD 0 51 xVDD 049xVDD 0O 51xVDD V 3 4 VnetCA DO CMD Inputs Note 1 For input only pins except RESET Vref VrefCA DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Single Ended AC and DC Input Levels for _ _ VIH DQ DC DC Input Logic High Vref 0 100 VDD Vref 0 100 VDD Vref 0 100 VDD VIL DQ DC DC Input Logic Low vss Vref 0 100 vss Vref 0 100 vss Vref 0 100 V 1 VIH DQ AC Input Logic High Vref 0 175 Note2 Vref 0 15 2 Vref 0 15 Note2 V 1 2 5 VIL DQ AC Input Logic Low Note2 0 175 Note2 0 15 2 0 15 V 1 2 5 Reference Voltage for DQ DM 0 49x VDD 0 51xVDD 0 49xVDD 0 51xVDD 0 49xVDD 051 V 3 4 Inputs Note 1 For input only pins except RESET Vref VrefDQ DC 2 See Overshoot and Undershoot Specifications in the device datasheet 3 The ac peak noise on VRef may not allow VRef to deviate from VRefDQ DC by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV 5 Single ended swing requirement for DQS DQS is 350 mV peak
12. 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el Ooo IRDPDENmax NN Timing of WR command to Power Down entry IWRPDENmin WL 4 tWR tCK avg tWRPDEN BL8MRS 4 tWRPDENmax Timing of WRA command to Power Down entry IWRAPDENmin WL 4 WR 1 tWRAPDEN BL8MRS 4 tWRAPDENmax Timing of WR command to Power Down entry BC4MRS tWRPDEN tWRPDENmin WL 2 tCK avg tWRPDENmax Timing of WRA command to Power Down entry tWRAPDENmin WL 2 WR 1 tWRAPDEN BC4MRS tWRAPDENmax Ti f REF d to P D ti tREFPDEN ee rr ming command to Power Down entr ub i i y tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings NEMPE PS ODT high time without write command or ODTH4min 4 igh ti WI Ut wri ODTH4 with write command BC4 ODTH4max ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on dela y z tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on tAON Ooo 30 e RTT Nom and RTT turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew Write Leveling Timings REL nee eed Meine First DQ
13. Down with DLL frozen to commands tXP tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax tCKEmin max 3nCK 5ns CKE minimum pulse width tCKE tCKEmax Command pass disable delay m tPDmin tCKE min Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDENmax Timing of PRE or PREA command to Power Down entry tPRPDENmin 1 REV 1 1 23 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice 9 3 5 i 8 a 2 M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el ee tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entry IWRPDEN IWRPDENmin WL 4 tWR tCK avg BL8MRS 4 tWRPDENmax Timing of WRA command to Power Down entry IWRAPDENmin WL 4 WR 1 tWRAPDEN BL8OTF BL8MRS 4 tWRAPDENmax Timing of WR command to Power Down entry BC4MRS tWRPDEN tWRPDENmin WL 2 tCK avg tWRPDENmax Timing of WRA command to Power Down entr
14. ODTH4 with write command and BC4 ODTH4max e ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on o o aw e RTT Nom and RTT WR turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew Write Leveling Timings GENE NENNEN First DQS DQS rising edge after tWLMRD nCK write leveling mode is programmed DOS DGSi delay after write leveling mode is programmed wiDOSEN 029 ck ST Write leveling setup time from rising CK tWLS 195 crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS tWLH 195 crossing to rising CK crossing Write leveling output delay po ts Write leveling output error IWLOE po rs REV 1 1 21 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M 64 PC3 8500 PC3 10600 PC3 12800 Cel Unbuffered DDR3 SDRAM DIMM el AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1600 2 1 1 Parameter Symbol Units Minimum Glock Cycle Ti
15. PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el Environmental Requirements Topr Module Operating Temperature Range ambient 0 to 55 Hopr Operating Humidity relative 10 to 90 1 Storage Temperature Plastic 55 to 100 C 1 HsTG Storage Humidity without condensation 5 to 95 1 Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum case temperature shall not exceed the value specified in the component spec Absolute Maximum DC Rating Vpp Voltage on VDD pins relative to Vss 0 4 V 1 975 V VDDQ Voltage on VDDQ pins relative to Vss 0 4 V 1 975 V Viy Vout Voltage on I O pins relative to Vss 0 4 V 1 975 V TsrG Storage Temperature 55 to 100 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 St
16. SDRAMs 00 07 RAS RAS SDRAMs 00 07 DDR3 CAS gt CAS SDRAMs 00 07 SDRAM ____________ SDRAMs 00 07 CKEO 13 0 WE SDRAMs 00 07 ODE BA Ww ____________ ODT SDRAMs 00 07 CK SDRAMs 00 07 DDR3 ___________ CK SDRAMs 00 07 SDRAM RESET gt RESET SDRAMs 00 07 W Voo Notes 1 DQ to I O wiring is shown as recommended but may be changed 2 DQ DQS DQS ODT DM CKB S relationships must be maintained as shown 3 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 2400 1 4 One SPD exists per module NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 4GB 2 Ranks 256Mx8 DDR3 SDRAMs Age DQ DQSO DQO DQ1 DQ2 DQ3 DQ4 095 096 097 0051 DQS1 DM1 008 Dag DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 0052 0952 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 0921 0922 DQ23 5053 DQSS3 DMS3 DQ24 DQ25 DQ26 DQ27 DQ28 0929 0030 REV 1 1 10 2010
17. Supported CL Settings S 2 CWL 6 tCK AV 1 875 1 2 5 2 o ns ns ns ns ns ns ns ns 15 n ns ns ns ns ns ns ns ns ns ns ns ns ns ns S REV 1 1 14 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el DDR3 1600MHz Speed Bin DDR3 1600 CL nRCD nRP 11 11 11 DI Parameter Symbol ACT to internal read or write delay time 13 225 PRE command period RP 13 025 ACT to orREFcommandperod RC o 48125 __ ACT to PRE command period 35 3 ns WL 5 eserved eserved L 5 WL 6 served ojo r I D 5 o e o Q T e ns 5 75i s served s eserved s 875 lt 2 5 ns served 5 5 5 ns 5 5 5 5 s Q iL o Q I 50 ojo 2 Q Q ll N Olan Q m a 875 served eserved served eserved 500 Supported CL Settings 6 7 8 9 10 11 Supported CWL Settings 6 7 8 nCK Optional Us 2 ojo I 50 W
18. to peak Differential swing requirement for DQS DQS is 700 mV peak to peak REV 1 1 12 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 AGB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Operating Standby and Refresh Currents elixir Tcase 0 85 1 5V 0 075V 1GB 1 Rank 128Mx16 DDR3 SDRAMs PC3 8500 PC3 10600 PC3 12800 Symbol Parameter Condition BE CG 20 IDDO Operating One Bank Active Precharge Current 396 440 484 mA IDD1 Operating One Bank Active Read Precharge Current 550 572 594 mA IDD2PO Precharge Power Down Current Slow Exit 53 53 53 mA IDD2P1 Precharge Power Down Current Fast Exit 132 154 176 mA IDD2Q Precharge Quiet Standby Current 132 154 176 mA IDD2N Precharge Standby Current 141 163 185 mA IDD3P Active Power Down Current 154 176 198 mA IDD3N Active Standby Current 132 176 198 mA IDD4R Operating Burst Read Current 880 1078 1188 mA IDDAW Operating Burst Write Current 924 1122 1232 mA IDD5B Burst Refresh Current 836 880 946 mA IDD6 Self Refresh Current Normal Temperature Range 53 53 53 mA 1007 Operating Bank Interleave Read Current 1650 1870 2090 m
19. 3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM elixir Functional Block Diagram 1GB 1 Rank 128Mx16 DDR3 SDRAMs REV 1 1 10 2010 5 lt 2 lt BEBE SB as 240o0hm 0050 LDas 0050 M 1095 DMO M LDM i DQ 07 N DQ 0 7 DQS upas Dasi y 0595 UDM g DQ 8 15 DQ 8 15 a eo MMurve oes BERESSS8s 4 240 052 LDQS 10186 0052 1005 Hor OL DM2 N LDM 5 SCL J scL DQ 16 23 N DQ 0 7 01 SAO gt A0 SPD Upas SAT P A1 4 9 SDA 0053 N 0005 Ww A2 li DM3 a DQ 24 31 DQ 8 15 a E BE E BEES ooz vt 9 vit 4 SPD TS 240 VREFCA gt 00 07 49 V gt 00 07 054 LDQS 1 BEEDG TS 5054 2505 Zo WE Vo D0 D7 DM4 LDM Vss 9 9 4 gt 00 07 SPD Temp sensor j DQ 32 39 DQ 0 7 D2 GKO gt om er p DQS5 100 d nes MERESSA EIS p gt 0055 0095 x DMS UDM WK 04 07 n BBGBTSI 5 EVENT Temp Sensor i Tm RESET
20. 4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 Cel PC3 8500 PC3 10600 PC3 12800 m er Unbuffered DDR3 SDRAM DIMM el Package Dimensions M2F1G64CBH4B5P 1GB 1 Rank 128 16 DDR3 SDRAMs FRONT 133 35 0 15 le gt SIDE wo 2 7 I 2 e H Detail P Detail A ri 5 175 47 00 71 00 1 27 0 07 0 10 25 Detail A Detail B 250 amp 0 80 0 05 0010000 1 00 Pitch 1 50 0 10 Units Millimeters Note Device position and scale are only for reference REV 1 1 25 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M 64 PC3 8500 PC3 10600 PC3 12800 Cel wn Unbuffered DDR3 SDRAM DIMM el Package Dimensions M2F1G64CBH4BO9N 1GB 1 Rank 128Mx16 DDR3 SDRAMs FRONT 133 35 0 15 126 0 2 SIDE 4 30Max e 4 25 00 0 2 30 00 0 5 0 15 5 175 47 00 PS Detail A 71 00 Perike 1 27 0 1 5 00
21. 9 DQ60 DQ61 DQ62 DQ63 I DM CS DQS DOS DM CS 095 DOGS N woo 1 00 N WVO1 VO 1 N 02 2 N 4 3 04 103 D12 N 4 4 4 WM 05 VOS N 106 VO6 N 07 Zon VO7 za 7 DM CS DQS 09 DM CS DQS DOGS voo 1 00 N 4 Vo1 VO 1 w 02 yo 2 N vos D5 Vo3 D13 we 104 VO 4 N Vos 5 N 4 voe VO6 N 107 za Fe VO7 za DM CS 06495 DQS DM CS 005 DQS N voo 1 00 N 1 VO 1 WM 1 0 2 1 02 N 103 D6 103 D14 N 4 04 1 0 4 19 75 5 WM voe 1 0 6 ENVE 07 zo x JO 7 za WM 1 DM CS Das DQS DM cs Das DQS N woo 1 00 N 101 VO 1 o2 vO2 N 4 3 D7 D15 N Vvo4 Vo4 WM 1 0 5 5 N voe 1 0 6 N voz zo Ex VO7 za Vooso 9 8 SPD gt 00 015 EE 00 015 Veg 00 015 J 00 015 BAO BA2 gt RS gt CAS gt p gt CKE0 _ gt CKE1 gt gt ODT1 Notes BAO BA2 SDRAMs 00 015 13 SDRA
22. A Operating Standby and Refresh Currents 0 85 Vppa Voo 1 5V 0 075V 2GB 1 Rank 256Mx8 DDR3 SDRAMs PC3 8500 PC3 10600 PC3 12800 Symbol Parameter Condition BE CG Dl Unit IDDO Operating One Bank Active Precharge Current 660 748 836 mA 1001 Operating One Bank Active Read Precharge Current 836 880 924 mA IDD2PO _ Precharge Power Down Current Slow Exit 106 106 106 mA IDD2P1 Precharge Power Down Current Fast Exit 220 264 308 mA IDD2Q Precharge Quiet Standby Current 264 308 352 mA IDD2N Precharge Standby Current 282 326 370 mA IDD3P Active Power Down Current 264 308 352 mA IDD3N Active Standby Current 264 352 396 mA IDD4R Operating Burst Read Current 1232 1452 1584 mA IDD4W Operating Burst Write Current 1276 1452 1628 mA IDD5B Burst Refresh Current 1672 1760 1892 mA IDD6 Self Refresh Current Normal Temperature Range 106 106 106 mA 1007 Operating Bank Interleave Read Current 2948 3388 3828 mA Operating Standby and Refresh Currents Tcase 0 85 1 5V 0 075V 4GB 2 Ranks 256Mx8 DDR3 SDRAMs 2 PC3 8500 PC3 10600 PC3 12800 Symbol Parameter Condition BE CG Dl Unit IDDO Operating One Bank Active Precharge Current 942 1074 1206 mA IDD1 Operating One Bank Active Read Precharge Current 1118 1206 1294 mA IDD2P0 __ Precharge Power Down Current Slow Exit 211 211 211 mA IDD2P1 Precha
23. C DOS17 a y NG 12 008 132 42 0058 162 72 Vo 192 RAS 102 0056 222 00515 TDOST TDQS15 13 009 133 Vss 43 0098 163 Vss 73 WE 193 50 103 0056 223 Vss 14 134 44 164 CB6NC 74 194 104 Vs 224 0054 15 DOSI 135 45 2 165 7 75 V 195 105 0050 225 0055 16 0051 136 Vss 46 CB3 NC 166 Vss 76 SINC 196 A13 106 DQ51 226 Vss 417 Vs 137 0014 47 167 NC TEST 77 197 Vpp 107 Vss 227 0060 18 0010 138 DQ15 48 168 RESET 78 Vp 198 S3 NC 108 0056 228 0061 19 0011 139 Vss 49 Vm NC 169 79 S2NC 199 Vs 109 DQ57 229 Vss DM7 20 Vss 140 DQ20 50 CKEO 170 Voo 80 Va 200 DQ36 110 Vss 230 DQS16 TDQS16 NC 21 0016 141 51 171 15 81 0032 201 00937 111 0057 231 DOSTS 150516 22 0017 142 Um 52 2 172 14 82 202 Vs 112 0087 232 Vss DM4 23 Va 143 53 ERR 173 Voo 83 Va 203 00513 113 Vss 233 0062 NG TDQS13 Ee NC DOS71 2 NO 24 DOSZ 144 NODQSI 174 A12 BC 84 DOS4 204 00513 114 0058 234 TOAST DOST 150513 25 0052 145 Vss 55 11 175 A9 85 DQS4 205 Vs 115 0059 235 Vss 26 Vss 146 DQ22 56 A7 176 Voo 86 Vss 206 DQ38 116 Vss 236 27 0018 147 57 Vp 177 A8 87 207 DQ39 117 SAO 237 SA1 28 DQI9 148 Vss 58 178 A6 88 0035 208 Vs 118 SCL 238 SDA 29 Vss 149 0028 55 4 179 m 89 Vs 209 0044 119 SA2 239 Vss 30 DQ24 150 DQ29 60 180 A3 90 0040 210 0045 120 Vm 240 Vr Not
24. L 5 WL 6 n Di n n n n eserved n CL 10 m Din REV 1 1 15 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Cel Unbuffered DDR3 SDRAM DIMM el AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1066MHz 1 Parameter Symbol Units Minimum Glock Cycle Time DLL off mode Average Clock Period Reter to Standard Speed sins es Wveagehighpusewidh hoea Average low pulsewidth 0 05 Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth 049 o Absolute clock LOW pulsewidth baes ts Clock Period siter 9 9 je S Clock Period Jitter during DLL locking period Cycle to Cycle Period siter 18 twos S Cycle to Cycle Period during DLL locking period 10 10 S DuyOydedter fairy Ps Cumulative erroracross2cycles tz Jes S Cumuatveemoraeoss3cydes HERS Cumualveemoracoss4cydes Cumulative error across Scycles
25. M1 gt DMS WV gt DM CS Das Das DM CS DOS DOS N 4 100 DQ40 N roo pag N 4 01 2041 o1 DQ10 N 02 DQ42 N 2 DQii N 103 Di DQ43 W 05 2012 N 1 04 2044 N 04 2913 105 2045 05 2014 1 06 2046 06 2915 N 07 za 2047 N 107 za AL Das2 DQS6 M DQS2 DQS6 DM2 DM6 N 4 DM CS Das Das DM CS DOS DOS pais 100 2048 N roo DQ17 N 1 DQ49 N 4 VO 1 DQ18 N 1 02 DQ50 N O2 DQ19 1 03 02 2951 103 06 2920 N 04 2952 104 2921 N 1 05 2953 N O5 DQ22 N 1 06 DQ54 N 6 DQ 23 N 07 za DQ55 N 7 za m AL Das3 DQS7 DQS3 DQS7 DM3 DM7 N DM CS Das Das DM CS DOS DOS DQ24 N 100 2956 roo 2925 1 2957 N 01 2926 N 2 2958 02 2927 N 103 D3 5959 M vos D7 2928 1 04 W 104 2929 N 5 2061 N 5 DQ30 1 06 2962 N DQ31 N 07 za DQ63 N 107 za gt SCL scL VpbpsPb gt SPD Ao Ao SPD Voo Vooa 00 07 A1 4 gt SDA m e gt 00 07 A2 WP Vss gt 00 07 Varera gt 00 07 e BAO BA2 gt BA0 BA2 SDRAMs 00 07 A0 A13 p gt A0 A13
26. M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Celixir Based on DDR3 1066 1333 128Mx16 1GB and DDR3 1066 1333 1600 256Mx8 2GB 4GB SDRAM B Die Features Performance Speed Sort PC3 8500 PC3 10600 PC3 12800 BE CG DI DIMM CAS Latency 7 9 11 fck Clock Frequency 533 667 800 tck Clock Cycle 1 875 1 5 1 25 fDQ DQ Burst Frequency 1066 1333 1600 240 Pin Dual In Line Memory Module UDIMM 128Mx64 1GB 256Mx64 2GB 512Mx64 4GB DDR3 Unbuffered DIMM based on 256Mx8 DDR3 SDRAM B Die devices Intended for 533MHz 667MHz 800MHz applications Inputs and outputs are SSTL 15 compatible Voo 1 5V 0 075V SDRAMs have 8 internal banks for concurrent operation Differential clock inputs Data is read or written on both clock edges e DRAM DLL aligns DQ and DGS transitions with clock transitions Address and control signals are fully synchronous to positive clock edge Nominal and Dynamtic On Die Termination support Halogen free product Description Unit MHz ns Mbps Programmable Operation DIMM CAS Latency 6 7 8 PC3 8500 6 7 8 9 PC3 10600 6 7 8 9 10 11 PC3 12800 Burst Type Sequential or Interleave Burst Length BC4 BL8 Operation Burst Read and Write Two different termination values Rtt Nom amp Rtt WR e 14 10 1 row co
27. Ms 00 015 RAS SDRAMs 00 015 CAS SDRAMs DO D15 WE SDRAMs DO D15 SDRAMs 00 07 SDRAMs 08 015 ODT SDRAMs 00 07 ODT SDRAMs D8 D15 CK SDRAMs 00 07 CK SDRAMs 00 07 CK SDRAMs D8 D15 CK SDRAMs D8 D15 RESET SDRAMs 08 015 1 DQ to I O wiring is shown as recommended but may be changed 2 DQ DQS DQS ODT DM CKE S relationships must be maintained as shown 3 For resistor is 240 1 4 One SPD exists per module ich DRAM a unique ZQ resistor is connected to ground The ZQ NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 AGB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect M2F1G64CBH4B5P 1GB 1 Rank 128Mx16 DDR3 SDRAMs Tm Serial PD Data Entry Hex Byte Description CG Di 0 CRC range EEPROM bytes bytes used 92 92 92 1 SPD revision 10 10 10 2 DRAM device type 0B 0B 0B 3 Module type form factor 02 02 02 4 SDRAM Device density and banks 03 03 03 5 SDRAM device row and column count 11 11 11 6 Module minimum nominal voltage 00 00 00 7 Module ranks and device DQ count 02 02 02 8 ECC tag and module memory Bus width 03
28. PORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M 64 Cel PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el Package Dimensions M2F4G64CB8HBON 4GB 2 Ranks 256 8 DDR3 SDRAMs FRONT 133 35 0 15 126 00 0 2 SIDE 5 60 Max EB 25 00 0 2 30 00 0 5 0 15 1 27 0 1 Detail A Detail B o 250 e e err 0 80 0 05 a i MM eid gt l 00110000 0170000 B 1 00 Pitch 1 50 0 10 Units Millimeters 1 REV 1 1 30 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 swe Unbuffered DDR3 SDRAM DIMM Celixi r Revision Log Rev Date Modification 0 1 01 2010 Preliminary Release 0 5 05 2010 Preliminary Release 2 1 0 06 2010 Official Release 1 1 10 2010 Revision Update Re move Over Clocking Products REV 1 1 31 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice
29. Power Down Entry to Exit Timing tPDmax 9 tREFI tACTPDENmin 1 Timing of ACT command to Power Down entry tACTPDENmax Timing of PRE or PREA command to Power Down entry tPRPDEN tPRPDENmin 1 REV 1 1 20 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice tXPDLL 2 o 4 U 2 M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el ae a O tRDPDENmin RL 4 1 Timing of RD RDA command to Power Down entry tRDPDEN tRDPDENmax Timing of WR command to Power Down entry IWRPDEN IWRPDENmin WL 4 tWR tCK avg BL8OTF BL8MRS 4 tWRPDENmax Timing of WRA command to Power Down entry IWRAPDENmin WL 4 WR 1 tWRAPDEN BL8OTF BL8MRS 4 tWRAPDENmax Timing of WR command to Power Down entry BC4MRS tWRPDEN tWRPDENmin WL 2 tCK avg tWRPDENmax Timing of WRA command to Power Down entry tWRAPDENmin WL 2 WR 1 tWRAPDEN BC4MRS tWRAPDENmax tREFPDENmin 1 Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings ODT high time without write command ODTH4min 4
30. S DQS rising edge after WLMRD write leveling mode is programmed DQS DQS delay after write leveling mode is programmed ck S Write leveling setup time from rising CK CK tWLS 245 crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS tWLH 245 crossing to rising CK CK crossing Write leveling output delay s fa p Write leveling output error _ REV 1 1 18 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M 64 Cel PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el AC Timing Specifications for DDR3 SDRAM Devices Used on Module 1333MHz L 1 9 Parameter Symbol Units Minimum Glock Cycle Time DLL off mode Average Clock Period Reter to Standard Speed Bin es _ Average high pulsewidth oo 04 oos Average low pulsewidth 0 oa Absolute Clock Period tCK abs Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth Absolute clock LOW pulse width Clock Period sitter TT wo ws S Clock Period Jitter during DLL locking period
31. YA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 a Unbuffered DDR3 SDRAM DIMM el Serial Presence Detect M2F X 4G64CB8HB5N 4GB 2 Ranks 256 8 DDR3 SDRAMs um Serial PD Data Entry Hex Byte Description c6 Di 0 CRC range EEPROM bytes bytes used 92 92 92 1 SPD revision 10 10 10 2 DRAM device type 0B 0B 0B 3 Module type form factor 02 02 02 4 SDRAM Device density and banks 03 03 03 5 SDRAM device row and column count 19 19 19 6 Module minimum nominal voltage 00 00 00 7 Module ranks and device DQ count 09 09 09 8 ECC tag and module memory Bus width 03 03 03 9 Fine timebase dividend divisor in ps 52 52 52 10 Medium timebase dividend 01 01 01 11 Medium timebase divisor 08 08 08 12 Minimum SDRAM cycle time tCKmin OF 0 0 13 Reserved 00 00 00 14 CAS latencies supported 1 3 15 CAS latencies supported 00 00 00 16 Minimum CAS latency time tAAmin 69 69 69 17 Minimum write recovery time tWRmin 78 78 78 18 Minimum CAS to CAS delay tRCDmin 69 69 69 19 Minimum Row Active to Row Active delay tRRDmin 3C 30 30 20 Minimum row Precharge del
32. __ Cycle to Cycle Period siter tos S Cycle to Cycle Period Jiter during DLL locking period Duty Cumulative error across 2 eyes JERRGe tt ows jp Cumulative erroracrossScycles HERG tos S Cumulative error across 4 oyoles Cumulative error across Scycles Cumulative error across 6oyoles tps S Cumulative error across 7 oyoles HERAT Cumulative error across 8 cycles tERR Cumuatveemoraeoss9cydes 20 __ _ je S Cumulative error across iOcydes 205 25 s Cumulative error across icydes 20 ets S Cumulative error across i2cydes as o 25 s tERR nper min 1 0 68In n tJIT per min Cumulative error across n 18 14 49 50 cycles tERR nper tERR nper max 1 0 68In n tJIT per max DOS DAS to DQ skew per group peraccess feasa DO output hold ime tom DAS DASE bon DAlow impedance time tom CK CKK zoo so __ S DQ highimpedance time CKF tps tDS Data setup time to DQS DQS referenced to Vih ac Vil ac levels 175 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels 150 tDH base Data hol
33. acturer Information 126 CRC 73 0D A9 127 CRC F7 2E AE 128 145 Module part number 146 Module die revision 147 Module PCB revision 150 175 Manufacturer reserved 176 255 Intel Extreme Memory Profile XMP REV 1 1 8 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 a Unbuffered DDR3 SDRAM DIMM el Serial Presence Detect M2F X 2G64CB88B7N 2GB 1 Rank 256Mx8 DDR3 SDRAMs T Serial PD Data Entry Hex Byte Description Dl 0 CRC range EEPROM bytes bytes used 92 92 92 1 SPD revision 10 10 10 2 DRAM device type 0B 0B 0B 3 Module type form factor 02 02 02 4 SDRAM Device density and banks 03 03 03 5 SDRAM device row and column count 19 19 19 6 Module minimum nominal voltage 00 00 00 7 Module ranks and device DQ count 01 01 01 8 ECC tag and module memory Bus width 03 03 03 9 Fine timebase dividend divisor in ps 52 52 52 10 Medium timebase dividend 01 01 01 11 Medium timebase divisor 08 08 08 12 Minimum SDRAM cycle time tCKmin OF 0 0 13 Reserved 00 00 00 14 CAS latencies supported 1 3C FC 15 CAS latencies suppor
34. ay tRPmin 69 69 69 21 Upper nibble for tRAS and tRC 11 11 11 22 Minimum Active to Precharge delay 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin 95 89 81 24 Minimum refresh recovery delay tRFCmin LSB 00 00 00 25 Minimum refresh recovery delay tRFCmin MSB 05 05 05 26 Minimum internal Write to Read command delay WTRmin 3C 3C 3C 27 Minimum internal Read to Precharge command delay tRTPmin 3C 3C 3C 28 Minimum four active window delay tFAWmin LSB 01 00 00 29 Minimum four active window delay tFAWmin MSB 2C F0 F0 30 SDRAM device output drivers supported 83 83 83 31 SDRAM device thermal and refresh options 05 05 05 32 Module Thermal Sensor 00 00 00 33 SDRAM Device Type 00 00 00 60 Module height nominal OF OF OF 61 Module thickness Max 11 11 11 62 Raw Card ID reference 01 01 01 63 DRAM address mapping edge connector 01 01 01 117 Module manufacture ID 83 83 83 118 Module manufacture ID 0B 0B 0B 119 121 Module manufacturer Information se e 126 CRC 68 2A 1E 127 CRC 59 F0 2F 128 145 Module part number 146 Module die revision 147 Module PCB revision 150 175 Manufacturer reserved 176 255 Intel Extreme Memory Profile XMP REV 1 1 10 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M 64 2GB 256M x 64 4GB 512M x 64 PC3 8500
35. d time from DQS DQS referenced to Vih dc Vil dc levels DC100 DQandDMipupusewidhforeachinut pg esM tt NIE SUN NN DOQS DOS differential READ Preamble meE 09 DOS DOSE differential READ Postamble eest os DOS DASE differential output high time jo o4 DOS DOSRdfeemiaowpulow m poss o4 DOS DOSE differential WRITE Preamble were 09 Kev DOS DASE differential WRITE Postamble west ER c DQS and DQS low impedance time i LZ DQS 500 tCK avg Referenced from RL 1 DQS and DQS high impedance time D tHZ DQS tCK avg Referenced from RL BL 2 EE DOS DASE differential input high pulse width DOS DAS rising edge to CK risingedge 25 0 DOS DASE falling edge setup time to CKirsmgedge 055 o2 Kev DOS DQS falling edge hold time from CK CK rising edge SM oe ice REV 1 1 19 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M 64 Cel PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el DLL locking time
36. e CK1 CK1 CKE1 S1 and ODT1 are for 4GB modules only REV 1 1 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM elixir Input Output Functional Description Symbol Type CKO CK1 CKO Input CKEO CKE1 Input 50 51 Input RAS CAS WE Input ODTO ODT1 Input DM8 Input 00950 DQS8 DQS0 0058 BAO BA1 BA2 Input A9 A10 AP A11 Input A12 BC A13 A15 DQO DQ63 Input Vop Vss Supply Vnerpo VREFCA Supply SDA SCL Input SA2 Input EVENT Output RESET Input REV 1 1 10 2010 Polarity Cross point Active High Active Low Active Low Active High Active High Cross point Function The system clock inputs All address and command lines are sampled on the cross point of the rising edge of and falling edge of A Delay Locked Loop DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated DDR3 SDRAM command decoder when low and disables the command
37. emperature Range capability MR2 A6 Ob and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 Ob Please refer to the supplier data sheet and or the DIMM SPD for Auto Self Refresh option availability Extended Temperature Range support and tREFI requirements in the Extended Temperature Range REV 1 1 11 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el DC Electrical Characteristics and Operating Conditions VDD Supply Voltage 1 425 1 575 VDDQ Output Supply Voltage 1 425 1 5 1 575 V 2 Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together Single Ended AC and DC Input Levels for Command and Address quM VIH CA DC DC Input Logic High Vref 0 100 VDD Vref 0 100 VDD Vref 0 100 VDD V VIL CA DC Input Logic Low VSS Vref 0 100 VSS Vref 0 100 VSS Vref 0 100 V 1 VIH CA AC Input Logic High Vref 0 175 2 Vref 0 175 2 Vref 0 175 Note2 V 1 VIL CA AC Input Logic Low Note2 Vref 0 175 Note2 X Vref 0 175 Note2 Vref 0 175 V 1 VIH CA AC150 AC Input Logic High Vref 0 15 Note2 Vref 0 15 Note 2 Vref 0
38. esence Detect Clock Input NC No Connect SDA Serial Presence Detect Data input output REV 1 1 2 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment Celixir Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 121 Vss 31 DQ25 151 Vss 61 A2 181 91 0041 211 Vs DM5 2 Vs 122 004 32 Vs 152 a 62 182 Vo 92 212 00514 TDQS14 ER NC DaS12 e NC 3 000 123 DQ5 0053 153 63 1 183 V 93 DOS 213 DOST 150512 150514 4 001 124 Vss 34 0053 154 Vss 64 CKiNC 184 CKO 94 0055 214 Vss 5 Vs 125 35 155 DQ30 65 185 CKO 95 Vg 215 0046 6 0950 126 36 00926 156 0031 66 Vo 186 96 0042 216 0047 7 0080 127 Vss 37 0027 157 Vss 67 Vaerca 187 ud 97 0043 217 Vss 8 Va 128 DQ6 38 158 CBANC 68 P n 188 AO 98 Va 218 0052 Daz 129 DQ7 39 CBO NC 159 5 69 Vo 189 V 99 DQ48 219 0053 10 130 Vss 40 CB1 NC 160 Vss 70 A10 AP 190 100 0049 220 Vss DM6 11 131 0012 44 Vas 161 DM amp DQS17 74 191 101 Vas 221 00815 TDQS17 NC TDOSIS N
39. ibration Timing OU Power up and RESET calibration time Normal operation Full calibration time Ope ck ST Normal operation Shor calibration time 2005 Reset Timing 22 user eee ce c enit E a Se tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR max Self Refresh Timings tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax XSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL CK tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE tCKSREmin max 5 nCK 10 ns tCKSRE or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Exit Power Down with DLL on to any valid command tXPmin max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands tXPmax not requiring locked DLL A n 20 3 5 i 8 a 2 Exit Precharge Power Down with DLL frozen to commands tXPDLLmin max 10nCK 24ns requiring a locked DLL tXPDLLmax tCKEmin max 3nCK 5 625ns CKE minimum pulse width tCKE tCKEmax Command pass disable delay m tPDmin tCKE min
40. ifferential WRITE Preamble were _ DOS DOSE differential WRITE Postamble west ae o DQS DQS low impedance time P i LZ DQS tCK avg Referenced from RL 1 DQS and DQS high impedance time tHZ DQS tCK avg Referenced from RL T T T E 1 E 1 DOS DASE differential input high pulse width 045 05 DAS rising edge to Cr risingedge eass ot 0 oo 05 5 falling edge setup time to CK CK risingedoe 055 oz __ Ke 05 DASE falling edge hold time CK rising edge Picea REV 1 1 16 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FAG64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M 64 Cel PC3 8500 PC3 10600 PC3 12800 wn Unbuffered DDR3 SDRAM DIMM el DLL locking time prec tRTPmin max 4nCK 7 5ns Internal READ Command to PRECHARGE Command delay tRTP tRTPmax Delay from start of internal write WTR tWTRmin max 4nCK 7 5ns transaction to internal read command tWTRmax WRITE recovery time wee Pts Mode Register Set command cycle time o ck tMODmin max 12nCK 15ns Mode Register Set command update delay iMODma to internal read or write delaytime RDP command period
41. ing the mode register set cycle The DIMM uses serial presence detect implemented via a serial EEPROM using a standard IIC protocol The first 128 bytes of SPD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 1 1 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 Unbuffered DDR3 SDRAM DIMM el Ordering Information 256Mx64 Pin Description Pin Name Description Pin Name Description CKO CK1 Clock Inputs positive line 0090 0063 Data input output CKO CK1 Clock Inputs negative line DQS0 DQS8 Data strobes CKE1 Clock Enable DQS0 DQS8 Data strobes complement RAS Row Address Strobe DMO DM8 Data Masks CAS Column Address Strobe EVENT Temperature event pin WE Write Enable RESET Reset pin 50 51 Chip Selects Vrerva VnEFCA Input Output Reference AO A9 A11 A13 A15 Address Inputs VopsPp SPD and Temp sensor power A10 AP Address Input Auto Precharge SAO SA1 Serial Presence Detect Address Inputs A12 BC Address Input Burst Chop Vtt Termination voltage BAO BA2 SDRAM Bank Address Inputs Vss Ground ODTO ODT1 Active termination control lines Vop Core and I O power SCL Serial Pr
42. lumn rank Addressing for 1GB 15 10 1 row column rank Addressing for 2GB 15 10 2 row column rank Addressing for 4GB Extended operating temperature rage Auto Self Refresh option Serial Presence Detect Gold contacts 1GB SDRAMs are in 96 ball BGA Package 2GB SDRAMs are in 78 ball BGA Package 4GB SDRAMs are in 78 ball BGA Package RoHS compliance M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2FA4G64CB8HBB5 9 N are 240 Pin Double Data Rate 3 DDR3 Synchronous DRAM Unbuffered Dual In Line Memory Module UDIMM organized as one rank of 128Mx64 1GB 256Mx64 2GB and two ranks of 512Mx64 4GB high speed memory array Modules use four 128Mx16 1GB 96 ball BGA packaged devices eight 256Mx8 2GB 78 ball BGA packaged devices and sixteen 256Mx8 4GB 78 ball BGA packaged devices These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SDRAM DIMMs provide a high performance flexible 8 byte interface in a space saving footprint The DIMM is intended for use in applications operating of 5S33MHz 667MHz 800MHz clock speeds and achieves high speed data transfer rates of 1066Mbps 1333Mbps 1600Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs A0 A13 1GB A0 A14 2GB 4GB and inputs BAO BA us
43. me DLL off mode Average Clock Period Reter to Standard Speed Bin ps o Average highpulsewith hoea oa tka Average low pulsewidth os 05 _ Max tCK avg max tJIT per max Absolute clock HIGH pulsewidth Absolute clock LOW pulsewidth baes os Clock Period siter stipe 70 7 je Clock Period Jitter during DLL locking period Cycle to Cycle Period tos S Cycle to Cycle Period during DLL locking period Ps Cumulative erroracross2cycles as tps S Cumuatveemoraeoss3cydes ae tes S Cumualveemoracss4cydes 36 136 ps S Cumulative error across Scycles Cumulative erroracross6cycles Cumulative error across 7oyoles tsps S Cumulative error across 8 cycles tERR EEUU s Cumulative error aoross 9 oyoles Cumulative error across 10 cycles ts 10 S Cumulative error across 11 cycles Cumulative error across i2cydes S tERR nper min 1 0 68In n tJIT per min Cumulative error across n 18 14 49 50 cycles tERR nper tERR nper max 1 0 68In n tJIT per max Bema T T DOS DAS to DQ skew pe
44. olumn address when sampled at the cross point of the rising edge of CK and falling edge of CK In addition to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge Data Input Output pins Power supplies for core I O Serial Presence Detect Temp sensor and ground for the module Reference voltage for SSTL15 inputs This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor A resistor must be connected from the SDA bus line to Vopsep on the system planar to act as a pull up This signal is used to clock data into and out of the SPD EEPROM and Temp sensor Address pins used to select the Serial Presence Detect and Temp sensor base address The EVENT pin is reserved for use to flag critical module temperature This signal resets the DDR3 SDRAM NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M 64 2GB 256M x 64 4GB 512M x 64 PC
45. orage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VDD and VDDQ must be within 300 mV of each other at all times and VREF must be not greater Operating temperature Conditions ToPER Normal Operating Temperature Range 0 to 85 1 2 Extended Temperature Range 85 to 95 C 1 3 Note 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 and 95 case temperature Full specifications are supported in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to supplier data sheet and or the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended T
46. r group peraccess feasa DO output hold ime DAS DASE DOQlowimpedance time tom CK zoo __ DOhghimpdane metomCK KK zoo tDS em Data setup time to DQS DQS referenced to Vih ac Vil ac levels 17 tDS base Data setup time to DQS DQS referenced to Vih ac Vil ac levels 150 tDH base Data hold time from DQS DQS referenced to Vih dc Vil dc levels DC100 DQandDMipupusewidhforeachimut pg e PIDEN tt MNT SN NN DQS DOS differential READ Preamble meE oo Kew 05 DOSE differential READ Postamble os DOS DASE differential output hightime jo tev DOS DASE differential outputiowtime pos Kev DOS DASE differential WRITE Preamble were 09 DOS DASE differential WRITE Postamble west 083 Kev Ern c DQS DQS low impedance time i tLZ DQS 450 tCK avg Referenced from RL 1 DQS and DQS high impedance time tHZ DQS tCK avg Referenced from RL DOS DASE differential input high pulse width DOS 005 rising edge to Ck rsingedge eass oxn 05 5 falling edge setup time to CK CK risingedoe 055 Ke 05 DASE falling edge hold time CK CK rising edge te
47. ress setup time to CK CK tlS base referenced to Vih ac Vil ac levels Command and Address hold time from CK i tlH base 120 referenced to Vih dc Vil dc levels Command and Address setup time to CK tlS base AC150 170 referenced to Vih ac Vil ac levels Control and Address Input pulse width for each input a Calibration Timing eee Power up and RESET calibration time ee eee Normal operation Full calibration time Zope se Normal operation Short calibration time 2005 Reset Timing 22 Ser eee ce c eni ee Se tXPRmin max 5nCK tRFC min 10ns Exit Reset from CKE HIGH to a valid command tXPR Self Refresh Timings ee ee eee T tXSmin max 5nCK tRFC min 10ns Exit Self Refresh to commands not requiring a locked DLL tXS tXSmax XSDLLmin tDLLK min Exit Self Refresh to commands requiring a locked DLL tXSDLL CK tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE ICKSRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX ICKSRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax Exit Power Down with DLL on to any valid command tXPmin max 3nCK 6ns Exit Precharge Power
48. rge Power Down Current Fast Exit 440 528 616 mA IDD2Q Precharge Quiet Standby Current 528 616 704 mA IDD2N Precharge Standby Current 563 651 739 mA IDD3P Active Power Down Current 528 616 704 mA IDD3N Active Standby Current 546 678 766 mA IDD4R Operating Burst Read Current 1514 1778 1954 mA IDDAW Operating Burst Write Current 1558 1778 1998 mA IDD5B Burst Refresh Current 1954 2086 2262 mA IDD6 Self Refresh Current Normal Temperature Range 211 211 211 mA IDD7 Operating Bank Interleave Read Current 3230 3714 4198 mA REV 1 1 13 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M x 64 2GB 256M x 64 4GB 512M x 64 PC3 8500 PC3 10600 PC3 12800 _ Unbuffered DDR3 SDRAM DIMM el DDR3 1066MHz Speed Bin CL nRCD nRP Parameter Symbol Min Internal read command tofirstdata ACT to internal read or write delay time tRCD mug E ACT to ACT or REF command period 50 625 E ACT to PRE command period IRAS 75 eREF fns C CWL 5 ICK AVG E CWL 6 tCK AVG 3 ES 2 U A o o o o ns Em CWL 5 ICK AVG ps5 Be o S S Reserved CWL 6 ICK AVG Reserved 2 o n n CWL 5 ICK AVG Reserved f CWL 6 ICK AVG 1 875 2s
49. ted 00 00 00 16 Minimum CAS latency time tAAmin 69 69 69 17 Minimum write recovery time tWRmin 78 78 78 18 Minimum CAS to CAS delay tRCDmin 69 69 69 19 Minimum Row Active to Row Active delay tRRDmin 3C 30 30 20 Minimum row Precharge delay tRPmin 69 69 69 21 Upper nibble for tRAS and tRC 11 11 11 22 Minimum Active to Precharge delay tRASmin 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin 95 89 81 24 Minimum refresh recovery delay tRFCmin LSB 00 00 00 25 Minimum refresh recovery delay tRFCmin MSB 05 05 05 26 Minimum internal Write to Read command delay WTRmin 3C 3C 3C 27 Minimum internal Read to Precharge command delay tRTPmin 3C 3C 3C 28 Minimum four active window delay tFAWmin LSB 01 00 00 29 Minimum four active window delay tFAWmin MSB 2C F0 F0 30 SDRAM device output drivers supported 83 83 83 31 SDRAM device thermal and refresh options 05 05 05 32 Module Thermal Sensor 00 00 00 33 SDRAM Device Type 00 00 00 60 Module height nominal OF OF OF 61 Module thickness Max 01 01 01 62 Raw Card ID reference 01 01 01 63 DRAM address mapping edge connector 01 01 01 117 Module manufacture ID 83 83 83 118 Module manufacture ID 0B 0B 0B 119 121 Module manufacturer Information 126 CRC 47 05 31 127 CRC 29 80 5F 128 145 Module part number 146 Module die revision 147 Module PCB revision 150 175 Manufacturer reserved 176 255 Intel Extreme Memory Profile XMP REV 1 1 9 10 2010 NAN
50. uiring a locked DLL tXSDLL tXSDLLmax tCKESRmin tCKE min 1 nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR tCKESRmax Valid Clock Requirement after Self Refresh Entry SRE tCKSREmin max 5 nCK 10 ns or Power Down Entry PDE tCKSREmax Valid Clock Requirement before Self Refresh Exit SRX tCKSRXmin max 5 nCK 10 ns or Power Down Exit PDX or Reset Exit tCKSRXmax A A eo n 2 2 5 g is 3 8 3 a 2 Exit Power Down with DLL on to any valid command tXPmin max 3nCK 7 5ns Exit Precharge Power Down with DLL frozen to commands tXPmax not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL tXPDLLmin max 10nCK 24ns tXPDLLmax tCKEmin max 3nCK 5 625ns tCKEmax tCPDEDmin 1 tCPDED tCPDEDmin tPDmin tCKE min tPDmax 9 tREFI tACTPDENmin 1 tACTPDENmax in tPRPDENmin 1 tXPDLL CKE minimum pulse width tCKE Command pass disable delay Power Down Entry to Exit Timing Timing of ACT command to Power Down entry Timing of PRE or PREA command to Power Down entry uU 2 D O U U m 2 2 tPRPDENmax D o 2 K 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH4B5 9 P M2F2G64CB88B7 H N M2F4G64CB8HB5 9 N 1GB 128M
51. y tWRAPDENmin WL 2 WR 1 tWRAPDEN BC4MRS tWRAPDENmax tREFPDENmin 1 Timing of REF command to Power Down entry tREFPDEN tREFPDENmax tMRSPDENmin tMOD min Timing of MRS command to Power Down entry tMRSPDEN tMRSPDENmax ODT Timings ODT high time without write command ODTH4min 4 ODTH4 with write command BC4 ODTH4max e ODTH8min 6 ODT high time with Write command and BL8 ODTH8 ODTH8max Asynchronous RTT turn on delay tAONPD 2 8 5 Power Down with DLL frozen Asynchronous RTT turn off delay tAOFPD 2 8 5 Power Down with DLL frozen RTT turn on tAON om zs e RTT Nom and RTT turn off time tAOF 0 3 0 7 tCK avg from ODTLoff reference RTT dynamic change skew Pos Write Leveling Timings GENE ae a ee ar NENNEN First DQS DQS rising edge after tWLMRD write leveling mode is programmed DAS DQS delay after write leveling mode is programmed wiDOSEN ck Write leveling setup time from rising CK tWLS 165 crossing to rising DQS DQS crossing Write leveling hold time from rising DQS DQS tWLH 165 crossing to rising CK CK crossing Write leveling output delay WLO pos Write leveling output error __ rs REV 1 1 24 10 2010 NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice M2F1G64CBH
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