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Elixir M2Y2G64CB8HA9NDG memory module

1. Si S0 DQSO M DQS4 M DASO M DAS M DMO M DM4 M DM CS DAS Das DM CS DAS bas DM CS DOS Das DM CS DQS DQS Da0 H 00 VOo DQ32 M 1 00 V00 DAI H 101 01 DQ33 M 101 V01 paz 102 02 DQ34 1 02 02 Da3 H 103 DO 03 D8 DQ35 M 1 03 D4 03 D12 DQ4 M 104 VO 4 DQ36 4 1 04 VO 4 DQ5 H 105 05 DQ37 M 1 05 VO5 pas 106 VO 6 pass 4 1 06 06 DQ7 1 07 1 07 DQ39 1 07 VO7 DQS1 WV pass M DAST M Das5 M DM1 M DM5 M DM CS DAS Das DM CS DAS Das DM CS DAS DAQS DM CS DAS pas pas 4 00 00 DQ40 1 00 V00 Dag 101 V01 DQ41 4 101 V01 DQ10 M 102 02 DQ42 1 02 O2 DQ11 4 103 D1 03 D9 DQ43 4 1 03 D5 03 D13 DQ12 1 04 VO 4 DQ44 1 04 O 4 DQ13 4 105 05 DQ45 M 1 05 VO5 DQ14 4 06 1 06 DQ46 1 06 06 DQ15 1 07 V07 DQ47 107 VO7 DQS2 pase DQS2 M DaS M DM2 M DM6 M DM CS DAS Das DM CS DAS Das DM CS DOS D
2. DDR3 1066 DDR3 1333 Parameter Symbol Min Max Min Max Units Command and Address Timing DLL locking time tDLLK 512 512 nCK ae READ Command to PRECHARGE Command tRTP max 4nCK 7 5ns max 4nCK 7 5ns T om of internal write transaction to internal WTR max 4nCK 7 5ns max 4nCK 7 5ns p WRITE recovery time tWR 15 15 z ns Mode Register Set command cycle time tMRD 4 4 nCK Mode Register Set command update delay tMOD max 12nCK 15ns max 12nCK 15ns CAS to CAS command delay tCCD 4 4 nCK Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK avg nCK Multi Purpose Register Recovery Time tMPRR 1 1 ACTIVE to ACTIVE command period for 1KB page size tRRD max 4nCK 7 5ns max 4nCK 6ns Four activate window for 1KB page size tFAW 37 5 z 30 E ns N ee setup time to CK CK referenced tIS base 125 _ 65 _ ps GEIN ie elias hold time to CK CK referenced to tIH base 200 140 _ ps Calibrating Timing Power up and RESET calibration time tZQinit 512 512 nCK Normal operation Full calibration time tZQoper 256 256 z nCK Normal operation Short calibration time tZQCS 64 64 nCK Reset Timing max 5nCK max 5nCK Exit Reset from CKE HIGH to a valid command tXPR tRFC min tRFC min 10ns 10ns Self Refresh Timings max 5nCK max 5nCK Exit Self Refresh to commands not requiring a locked DLL tXS tRFC
3. Part Number Speed Organization Leads Power Note M2Y1G64CB88A9N BE 533MHz 1 875ns CL 7 DDR3 1066 PC3 8500 M2Y1G64CB88A9N CG 667MHz 1 500ns CL 9 DDR3 1333 PC3 10660 128Mx64 M2Y1G64CB88A9N DG 800 MHz 1 250ns CL 9 DDR3 1600 PC3 12800 M2Y2G64CB8HA9N BE 533MHZz 1 875ns CL 7 DDR3 1066 PC3 8500 oe ai M2Y2G64CB8HA9N CG 667MHZz 1 500ns CL 9 DDR3 1333 PC3 10660 256Mx64 M2Y2G64CB8HA9N DG 800 MHz 1 250ns CL 9 DDR3 1600 PC3 12800 Pin Description Pin Name Description Pin Name Description A0 A13 Address Inputs SCL Serial Presence Detect Clock Input BAO BA2 SDRAM Bank select SDA Serial Presence Detect Data input output RAS Row Address Strobe SA0 SA2 Serial Presence Detect Address Inputs CAS Column Address Strobe Voo SDRAM core power supply WE Write Enable Vopa SDRAM I O Driver power supply S0 S1 Chip Selects VREFDa SDRAM I O reference supply CKEO CKE1 Clock Enable VREFCA SDRAM command address reference supply ODTO0 ODT1 On die termination control lines Vss Ground DQO0 DQ63 Data input output Vopspp Serial EEPROM positive power supply oa SDRAM differential data strobes NC No Connect DMO0 DM7 Input Data Mask High Data Strobes Vir SDRAM I O termination supply aa Differential Clock Inputs RESET Set DRAMs to Know State Note CK1 CK1 Sl OTD1 and CKE1 are used for 2GB module only REV 1 0 11 2008 2 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CO
4. Speed Bins Speed Bin DDR3 1066 BE DDR3 1333 CF DDR3 1333 CG DDR3 1600 DG DDR3 1600 DH CL nRCD nRP 7 7 7 8 8 8 9 9 9 9 9 9 10 10 10 Unit Parameter Symbol Min Max Min Max Min Max Min Max Min Max hteral rgad commana tAA 13 125 20 12 20 13 5 20 11 25 20 12 5 20 ns to first data penne anes igis 12 35 W25 125 i write delay time PRE command period tRP 13 125 F 12 13 5 11 25 Ss 12 5 i ns PATRUN tRC 50 625 48 495 4625 an n command period ACT to PRE command teas 375 9 REFIU 36 94REFI 36 9 4REFI 35 MREFI 35 9REFI ns period CWL 5 tCK AVG Reserved 2 5 3 3 Reserved 2 5 3 3 2 5 3 3 ns BESS CWL 6 7 8 tCK AVG Reserved Reserved Reserved Reserved Reserved ns CWL 5 tCK AVG 2 5 3 3 2 5 3 3 2 5 3 3 2 5 3 3 2 5 3 3 ns CL 6 CWL 6 tCK AVG Reserved Reserved Reserved 1 875 lt 2 5 Reserved ns CWL 7 8 tCK AVG Reserved Reserved Reserved Reserved Reserved ns CWL 5 tCK AVG Reserved Reserved Reserved Reserved Reserved ns CWL 6 tCK AVG 1 875 lt 2 5 1 875 lt 2 5 Reserved 1 875 lt 2 5 1 875 lt 2 5 ns SLST CWL 7 tCK AVG Reserved Reserved Reserved Reserved Reserved ns CWL 8 tCK AVG Reserved Reserved Reserved Reserved Reserved ns CWL 5 tCK AVG Reserved Reserved Reserved Reserved Reserved ns CWL 6 tCK AVG 1 875 lt 2 5 1 875 lt 2 5 1 875 lt 2 5 1 875 lt 2 5 1 875 lt 2 5 ns CETS CWL 7 tCK AVG 1 5 lt 1 875 Reserved 1 5 lt 1 875 Reserved ns CWL 8 tCK AVG
5. Part 2 of 2 1GB 128Mx64 1 Rank UNBUFFERED DDR3 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 5V DDR3 SDRAMs with SPD Byte Description ee ee Pe hademe Note BE CG DG BE CG DG 61 Module thickness Max ae i Bites a 11 62 Raw Card ID reference Raw Card A 00 63 DRAM address mapping edge connector Undefined 00 64 116 Reserved 117 118 Module manufacture ID 830B 119 125 Module information 126 127 CRC 1944 CB62 D93C 128 145 Module part number Undefined 146 Module die revision Undefined 00 147 Module PCB revision Nanya Technology 00 148 149 DRAM device manufacturer ID 830B 150 175 Manufacturer reserved Undefined za 176 255 Customer reserved 7 REV 1 0 8 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HAIN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect Part 1 of 2 2GB 256Mx64 2 Ranks UNBUFFERED DDR3 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 5V DDR3 SDRAMs with SPD Serial PD Data Entry SPD Entry Value Byte Description d Hexadecimal Note BE CG DG BE CG DG CRC Covers Bytes 0 116 0 CRC range EEPROM bytes bytes used Tota
6. Reserved Reserved Reserved Reserved ns CWL 5 6 tCK AVG Reserved Reserved Reserved Reserved ns CL 9 CWL 7 tCK AVG 1 5 lt 1 875 15 lt 1 875 1 5 lt 1 875 1 5 lt 1 875 ns CWL 8 tCK AVG Reserved Reserved 1 25 lt 1 5 Reserved ns CWL 5 6 tCK AVG Reserved Reserved Reserved Reserved ns CL 10 CWL 7 tCK AVG 2 a oti ee 15 lt 1875 15 lt 1 875 ns CWL 8 tCK AVG 1 25 lt 1 5 1 25 lt 1 5 ns CWL 5 6 7 tCK AVG Reserved Reserved ns T ows ORAS OE oar S Supported CL settings 6 7 8 5 6 7 8 9 10 6 8 9 10 5 6 7 8 9 10 11 5 6 7 8 9 10 11 nCK Supported CWL Settings 5 6 5 6 7 5 6 7 5 6 7 8 5 6 7 8 nCK REV 1 0 13 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HAIN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module DDR3 1066 DDR3 1333 Parameter Symbol Min Max Min Max Units Clock Timing Minimum Clock Cycle time DLL off mode Se 8 8 ns Average high pulse width tCH avg 0 47 0 53 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 0 47 0 53 tCK avg Absolute Clock Period tCK abs iripermin_tlll perymaxstlipen
7. Detail A Detail B S 2 50 S a 0 80 0 05 Ooi UDU OQU000 a 1 00 Pitch J 1 50 0 10 Units Millimeters Note Device position is only for reference REV 1 0 21 11 2008 i NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HAIN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Package Dimensions 2GB 2 Ranks 128Mx8 DDR3 SDRAMs FRONT 133 35 0 15 SIDE iS i ong Datel Pa Detail B M TATA N I COCO COCO 5175 le 47 00 Mi eg 71 00 R BACK a O I Detail A o 2 50 o o v j OUI O00 A 1 50 0 10 Units Millimeters Note Device position is only for reference REV 1 0 11 2008 Detail B 0 8 0 0 05 O000 1 00 Pitch 22 gt 30 00 0 5 0 15 s cr 1 27 0 07 0 1 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM M2Y1G64CB88A9N M2Y2G64CB8HAIN Cel e Package Dimensions 2GB 2 Ranks Heat Spreader 12
8. 78 18 Minimum CAS to CAS delay tRCDmin ns 13 125 13 5 11 25 69 6C 5A 19 Minimum Row Active to Row Active delay tRRDmin ns 7 5 6 3C 30 20 Minimum row Precharge delay tRPmin ns 13 125 13 5 11 25 69 6C 5A 21 Upper nibble for tRAS and tRC 1 1 11 22 Minimum Active to Precharge delay tRASmin ns 37 5 36 35 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin ns 50 625 49 5 46 25 95 8C 72 24 Minimum refresh recovery delay tRFCmin LSB Combo bytes 24 25 70 25 Minimum refresh recovery delay tRFCmin MSB 110ns 03 26 Minimum internal Write to Read command delay tWTRmin 7 5ns 3C 27 Minimum internal Read to Precharge command delay 7 5ns 3C tRTPmin 28 Minimum four active window delay tFAWmin LSB Combo byte 28 29 01 00 29 Minimum four active window delay tFAWmin MSB 37 5ns 30ns 2C FO RZQ 6 RZQ 7 30 SDRAM device output drivers suported DLL Off Mode Support 83 Extended Temperature Range ASR 31 SDRAM device thermal and refresh options ODTS PASR 8D 32 Module thermal sensor Non Thermal Sensor Support 00 33 SDRAM device type Standard Monolithic Device 00 34 59 Reserved Undefined 60 Module height nominal 29 lt height lt 30 mm OF REV 1 0 11 2008 7 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HA9ON 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect
9. SCL Vopspp REV 1 0 11 2008 Type SSTL SSTL SSTL SSTL Supply Supply Supply SSTL SSTL SSTL SSTL Supply SSTL Input Supply Polarity Differential crossing Active High Active Low Active Low Active High Active High Differential crossing Active High Function CK and CK are differential clock inputs All the DDR3 SDRAM address control inputs are sampled on the crossing of positive edge of CK and negative edge of CK Output read data is reference to the crossing of CK and CK Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode Enables the associated SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue This signal provides for external rank selection on systems with multiple ranks RAS CAS WE along with S define the command being entered Reference voltage for SSTL15 I O inputs Reference voltage for SSTL15 command address inputs Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity When high termination resistance is enabled for all DQ DQS DQS and DM pins assuming this function is enabled in the Mode Register 1 MR1 Selects which SDRAM bank is to be active During a Bank Activate command cycle A
10. TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HA9ON 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Serial Presence Detect Part 1 of 2 1GB 128Mx64 1 Rank UNBUFFERED DDR3 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 5V DDR3 SDRAMs with SPD Serial PD Data Entry SPD Entry Value h Byte Description y Hexadecimal Note BE CG DG BE CG DG CRC Covers Bytes 0 116 0 CRC range EEPROM bytes bytes used Total SPD Bytes 256 92 SPD Bytes Used 176 1 SPD revision Revision 1 0 10 2 DRAM device type DDR3 SDRAM 0B 3 Module type form factor UDIMM 02 4 SDRAM Device density and banks 8 banks 1Gb 02 5 SDRAM device row and column count 14 rows 10 columns 11 6 Reserved Undefined 00 7 Module ranks and device DQ count 1 rank 8 bits 01 8 ECC tag and module memory Bus width Non ECC 64bits 03 9 Fine timebase dividend divisor in ps 2 5ps 52 10 Medium timebase dividend ins 01 11 Medium timebase divisor 8ns 08 12 Minimum SDRAM cycle time tCKmin ns 1 875 1 5 1 25 OF 0c 0A 13 Reserved Undefined 00 14 CAS latencies supported 6 7 8 6 8 9 5 6 7 8 9 10 1C 34 7E 15 CAS latencies supported Undefined 00 16 Minimum CAS latency time tAAmin ns 13 125 13 5 11 25 69 6C 5A 17 Minimum write recovery time tWRmin 15ns
11. data into and out of the SPD EEPROM A resistor may be connected from the SCL bus time to V DD to act as a pull up Power Supply for SPD EEPROM This supply is separate from the VDD VDDQ power plane EEPROM supply is operable from 3 0V to 3 6V 4 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HA9IN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 1GB 1 Rank 128Mx8 DDR3 SDRAMs S0 Daso M pas4 M bDaso M Das4 M DMO N DM4 DM CS DAS DQS DM CS DAS DAQS pao N o0 DQ32 1 00 pai N 101 DQ33 M 101 paz 4 102 DQ34 1 02 DQ3 4 103 Do pass 4 1 03 D4 pa4 N 104 pass M 04 DQ5 M 105 DQ37 4 1 05 Das M 106 DQ38 M 1 06 DQ7 M 107 DQ39 M 107 DASI M pass M DAST M Das5 M DMI M DM5 DM CS DAS DQS DM CS DAS Das Das 100 DQ40 M 100 Dag M 101 pa41 4 01 DQ10 4 102 DQ42 02 Da1 03 D1 DQ43 M 03 D5 DQ12 4 04 pa44 4 104 DQ13 M 1 05 DQ45 1 05 pai4 M 1 06 DQ46 M 1 06 pais 4 107 DQ47 M 07 Dpas2 pas Das2 DaS M DM2 DM6 N DM CS DOS DQS paig M 103 p2 DM CS DOS DOS DQ24 M 00 paz
12. 0 2 tCK avg REV 1 0 17 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HA9ON 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM DDR3 1600 Parameter Symbol Min Max Units Command and Address Timing DLL locking time tDLLK 512 nCK Internal READ Command to PRECHARGE Command delay tRTP max 4nCK 7 5ns Delay from start of internal write transaction to internal read WTR max 4nCK 7 5ns 7 command WRITE recovery time tWR 15 ns Mode Register Set command cycle time tMRD 4 nCK Mode Register Set command update delay tMOD max 12nCK 15ns CAS to CAS command delay tCCD 4 nCK Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK avg nCK Multi Purpose Register Recovery Time tMPRR 1 ACTIVE to ACTIVE command period for 1KB page size tRRD max 4nCK 6ns Four activate window for 2KB page size tFAW 30 ns Command and Address setup time to CK CK referenced to Vih ac tIS base TBD _ ps Vil ac levels Command and Address hold time to CK CK referenced to Vih ac tlH base TBD _ ps Vil ac levels Calibrating Timing Power up and RESET calibration time tZQinit 512 nCK Normal operation Full calibration time tZQoper 256 nCK Normal opera
13. 04 Vss 143 DM2 183 Voo 224 DQ54 24 DQS2 64 CKI NC 105 DQ50 144 NC 184 CKO 225 DQ55 25 DQS2 65 Voo 106 DQ51 145 Vss 185 CKO 226 Vss 26 Vss 66 Vop 107 Vss 146 DQ22 186 VDD 227 DQ60 27 DQ18 67 VREFCA 108 DQ56 147 DQ23 187 NC 228 DQ61 28 DQ19 68 NC 109 DQ57 148 Vss 188 AO 229 Vss 29 Vss 69 Vop 110 Vss 149 DQ28 189 Vop 230 DM7 30 DQ24 70 A10 AP 111 DQs7 150 DQ29 190 BA1 231 NC 31 DQ25 71 BAO 112 DQS7 151 Vss 191 Vop 232 Vss 32 Vss 72 Vop 113 Vss 152 DM3 192 RAS 233 DQ62 33 DQs3 73 WE 114 DQ58 153 NC 193 S0 234 DQ63 34 DQS3 74 CAS 115 DQ59 154 Vss 194 Voo 235 Vss 35 Vss 75 Vop 116 Vss 155 DQ30 195 ODTO 236 Vopspp 36 DQ26 76 S1 NC 117 SAO 156 DQ31 196 A13 237 SA1 37 DQ27 77 ODT1 NC 118 SCL 157 Vss 197 Vop 238 SDA 38 Vss 78 Voo 119 SA2 158 NC 198 NC 239 Vss 39 NC 79 NC 120 Vir 159 NC 199 Vss 240 Vir 40 NC 80 Vss 160 Vss 200 DQ36 41 Vss 81 DQ32 161 NC 201 DQ37 Note 1 NC No Connect 2 Pin 63 64 76 77 and 169 CK1 CK1 Sl OTD1 and CKE1 are used for 2GB module only REV 1 0 3 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HA9ON 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Input Output Functional Description Symbol CKO CK1 CKO CK1 CKE0O CKE1 VREFDa VREFCA Vopa ODT0 ODT1 BAO BA2 AO A13 DQO DQ63 VDD VSS DQS0 DQS7 DQS0 DQS7 DMO DM7 SAO SA2 SDA
14. 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HASN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Package Dimensions 1GB 1 Rank 128Mx8 DDR3 SDRAMs FRONT 133 35 0 15 5 175 47 00 SIDE A 2 70 Max q Detail A r Detail B MANAAAANANANANNNANNAANNNANAATENNN N OCC CACC eee y 71 00 1 27 0 07 wit gt 5 00 lt gt Detail A Detail B 3 80 ig 2 50 8 Co mi 4 Units Millimeters Note Device position is only for reference REV 1 0 11 2008 gt il 1 0000 COMOOON F 1 00 Pitch 1 50 0 10 0 80 0 05 ig ee 20 X NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM M2Y1G64CB88A9N M2Y2G64CB8HAON Cel el Package Dimensions 1GB 1 Rank Heat Spreader 128Mx8 DDR3 SDRAMs FRONT 133 35 0 15 126 0 2 4 30Max E gt E 25 00 0 2 30 00 0 5 0 15 1 274 0 07
15. 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM M2Y1G64CB88A9N M2Y2G64CB8HASN Cel elixir 240pin Unbuffered DDR3 SDRAM MODULE Based on 128Mx8 DDR3 SDRAM A Die Features e Performance PC3 8500 PC3 10660 PC3 12800 Speed Sort BE CG DG Unit DIMM CAS Latency 7 9 9 fex Clock Frequency 533 667 800 MHz tek Clock Cycle 1 875 1 5 1 25 ns foa DQ Burst Frequency 1066 1333 1600 Mbps e JEDEC Standard 240 pin Dual In Line Memory Module e Automatic and controlled precharge commands e 128Mx64 and 256Mx64 DDR3 Unbuffered DIMM based on e Programmable Operation 128Mx8 DDR3 Elixir SDRAM DIMM CAS Latency 5 6 7 8 9 10 e Intended for 533MHz 667MHz and 800MHz applications Burst Type Sequential amp Interleave e Inputs and outputs are SSTL15 compatible Burst Length BC4 BL8 Voo Vona 1 5Volt 0 075Volt Operation Burst Read and Write SDRAMs have 8 internal banks for concurrent operation e 14 10 1 Addressing row column rank 1GB e Differential clock inputs e 14 10 2 Addressing row column rank 2GB e Data is read or written on both clock edges e Serial Presence Detect 8 bit pre fetch Gold contacts e Two different termination values Rtt_Nom amp Rtt_WR SDRAMs in 78 BGA Package e Extended operating temperature rage RoHS and Halogen Free compliance e Auto Self Refresh option Green DIMM with Heat Spreader Description M2Y1G64CB88AQ9N and M2Y2G64CB8HASN are 240 Pin Double Data Rate 3 DDR3 Synchronous DRAM
16. 250 ps Tear time to DQS DQS reference to Vih ac tDS base 25 TBD ps pata hold time to DQS DQS reference to Vih ac Vil ac tDH base 100 TBD ps Data Strobe Timing DQS DQS differential READ Preamble tRPRE 0 9 0 9 tCK avg DQS DQS differential READ Postamble tRPST 0 3 0 3 tCK avg DQS DQS differential output high time tQSH 0 38 0 40 tCK avg DQS DQS differential output low time tQSL 0 38 0 40 tCK avg DQS DQS differential WRITE Preamble tWPRE 0 9 0 9 tCK avg DQS DQS differential WRITE Postamble tWPST 0 3 0 3 tCK avg a DQS rising dege output access time from rising CK tDascK 300 300 255 255 ps DQS DOS low impedance time Reference from RL 1 tLZ DQS 600 300 500 250 ps a8 DQS high impedance time Reference from RL tHZ DQS 7 300 250 ps DQS DQS differential input low pulse width tDQSL 0 4 0 6 0 4 0 6 tCK avg DQS DQS differential input high pulse width tDQSH 0 4 0 6 0 4 0 6 tCK avg DQS DQS rising edge to CK CK rising edge tDQSS 0 25 0 25 0 25 0 25 tCK avg DQS DQS falling edge setup time to CK CK rising edge tDSS 0 2 0 2 tCK avg DQS DQS falling edge hold time to CK CK rising edge tDSH 0 2 0 2 tCK avg REV 1 0 14 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HA9ON 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM
17. 8Mx8 DDR3 SDRAMs FRONT 133 35 0 15 126 00 0 2 5 60 Max 25 00 0 2 30 00 0 5 0 15 1 27 0 07 0 1 Detail A Detail B S 2 50 s S x 0 80 0 05 1 OOM O00 OOMOO00 a 1 00 Pitch 1 50 0 10 Units Millimeters Note Device position is only for reference REV 1 0 23 11 2008 i NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88AQ9N M2Y2G64CB8HASN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Revision Log Rev Date Modification 1 0 11 2008 Official Release REV 1 0 24 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice
18. AQS DM CS DOS Das pais 100 00 DQ48 M 100 00 DQ17 W 101 V01 DQ49 M 101 V01 pais M 102 1 02 DQ50 M 1 02 V02 DQ19 M 103 D2 03 D10 DQ51 4 1 03 D6 03 D14 DQ20 M 1 04 VO 4 DQ52 M 1 04 VO 4 DQ21 4 105 05 DQ53 4 1 05 VO5 DQ22 4 06 1 06 DQ54 1 06 06 DQ23 4 1 07 VO7 DQ55 4 1 07 VO7 DQs3 M DQS7 DQs3 M Das7 DM3 DM7 DM CS DAS Das DM CS DOS DQS DM CS DOS Das DM CS DQS DQS DQ24 00 vO 0 DQ56 00 V00 DQ25 M 101 V01 DQ57 M 101 V01 DQ26 M 102 V02 DQ58 M 102 VO 2 DQ27 M 03 D3 03 D11 DQ59 4 1 03 D7 03 D15 DQ28 M 1 04 VO 4 Da60 M 04 VO 4 DQ29 4 1 05 05 DQ61 M 105 VO5 DQ30 4 06 1 06 DQ62 M 1 06 V06 DQ31 107 VO7 DQ63 4 1 07 VO7 BAO BA2 gt BAO BA2 SDRAMs D0 D15 A0 A13 gt A0 A13 SDRAMs DO D15 RAS RAS 20 RAS RAS SDRAMs D0 D15 hives fear gt Pai CAS TAS SDRAMs D0 D15 VrerDa T DO D15 WE gt WE SDRAMs D0 D15 Vss a a ae oe Vrerca gt DO D15 CKE0 CKE SDRAMs D0 D7 CKE1 gt CKE SDRAMs D8 D15 ODTO gt ODT SDRAMs D0 D7 ODT1 gt ODT SDRAMs D8 D15 Serial PD CKO gt CK SDRAMs D0 D7 scL p CK1 gt CK SDRAMs D8 D15 MPa a ag A gt SDA CKO gt CK SDRAMs D0 D7 ae ahi al CKi gt CK SDRAMs D8 D15 REV 1 0 6 11 2008 NANYA TECHNOLOGY CORP NANYA
19. D min tMOD min z REV 1 0 15 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HASN 1GB 128M x 64 2GB 256M x 64 el Unbuffered DDR3 SDRAM DIMM DDR3 1066 DDR3 1333 Parameter Symbol Min Max Min Max Units ODT Timings ODT high time without write command or with write _ _ command and BC4 oo i mek ODT high time with Write command and BL8 ODTH8 6 6 nCK Pe dia RTT turn on delay Power Down with DLL tAONPD 1 9 9 ns Asynchronous RTT turn off delay Power Down with DLL tAOFPD 9 9 hs frozen RTT turn on tAON 300 300 250 250 ps RTT_Nom and RTT_WR turn off time from ODTLoff tAOF 03 0 7 0 3 0 7 tCK avg reference RTT dynamic change skew tADC 0 3 0 7 0 3 0 7 tCK avg Write Leveling Timings First DQS DQS rising edge after write leveling mode is iWLMRD 40 p 40 _ nCK programmed DQS DQS delay after write leveling mode is programmed tWLDQSEN 25 25 nCK Write leveling setup time from rising CK CK crossing to E E rising DQS DQS crossing WES 245 195 ps Write leveling setup hold from rising CK CK crossing to z rising DQS DQS crossing WEN 245 195 ps Write leveling output delay tWLO 0 9 0 9 ns Write leveling output error tWLOE 0 2 0 2 ns REV 1 0 16 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Product
20. DRAM device manufacturer ID 830B 150 175 Manufacturer reserved Undefined 176 255 Customer reserved REV 1 0 10 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM M2Y1G64CB88A9N M2Y2G64CB8HA9ON Cel e Absolute Maximum DC Ratings Symbol Parameter Rating Units Vin Vout Voltage on I O pins relative to Vss 0 4 to 1 975 V Vpp Voltage on VDD supply relative to Vss 0 4 to 1 975 V VDDQ Voltage on VDDQ supply relative to Vss 0 4 to 1 975 V Note Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability DC Electrical Characteristics and Operating Conditions Tcase 0 C 85 C Vona 1 5V 0 075V Voo 1 5V 0 075V See AC Characteristics Symbol Parameter Min Max Units Notes VDD Supply Voltage 1 425 1 575 V 1 VDDQ I O Supply Voltage 1 425 1 575 V 1 VREF I O Reference Voltage 0 49VDDQ 0 51VDDQ V 1 2 Note 1 Inputs are not recognized as valid until VREF stabilizes 2 VREF is expected to be equal to 0 5 V DDQ of the transmitting device and to track varia
21. R 9per 175 175 ps Cumulative error across 10 cycles tERR 10per 180 180 ps Cumulative error across n 11 50 cycles tERR nper een N Pree las eae ps Data Timing DQS DOS to DQ skew per group per access tDQSQ 100 ps DQ output hold time from DQS DQS tQH 0 38 tCK avg DQ low impedance time from CK CK tLZ DQ 450 225 ps DQ high impedance time from CK CK tHZ DQ 225 ps Data setup time to DQS DQS reference to Vih ac Vil ac levels tDS base TBD ps Data hold time to DQS DQS reference to Vih ac Vil ac levels tDH base TBD ps Data Strobe Timing DQS DQS differential READ Preamble tRPRE 0 9 tCK avg DQS DQS differential READ Postamble tRPST 0 3 tCK avg DQS DQS differential output high time tQSH 0 40 tCK avg DQS DQS differential output low time tQSL 0 40 tCK avg DQS DQS differential WRITE Preamble tWPRE 0 9 tCK avg DQS DQS differential WRITE Postamble tWPST 0 3 tCK avg DQS DQS rising dege output access time from rising CK CK tDQSCK 225 225 ps DQS DOS low impedance time Reference from RL 1 tLZ DQS 450 225 ps DQS DOS high impedance time Reference from RL BL 2 tHZ DQS 225 ps DQS DQS differential input low pulse width tDQSL 0 4 0 6 tCK avg DQS DQS differential input high pulse width tDQSH 0 4 0 6 tCK avg DQS DQS rising edge to CK CK rising edge tDQSS 0 25 0 25 tCK avg DQS DQS falling edge setup time to CK CK rising edge tDSS 0 2 tCK avg DQS DQS falling edge hold time to CK CK rising edge tDSH
22. RP reserves the right to change Products and Specifications without notice 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM M2Y1G64CB88A9N M2Y2G64CB8HA9ON Cel e Pinout Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 Vrerba 42 NC 82 DQ33 121 Vss 162 NC 202 Vss 2 Vss 43 NC 83 Vss 122 DQ4 163 Vss 203 DM4 3 DQO 44 Vss 84 DQAS4 123 DQ5 164 NC 204 NC 4 DQ1 45 NC 85 DQS4 124 Vss 165 NC 205 Vss 5 Vss 46 NC 86 Vss 125 DMO 166 Vss 206 DQ38 6 DASO 47 Vss 87 DQ34 126 NC 167 NC 207 DQ39 7 DQSO 48 NC 88 DQ35 127 Vss 168 RESET 208 Vss 8 Vss KEY 89 Vss 128 DQ6 KEY 209 DQ44 9 DQ2 49 NC 90 DQ40 129 DQ7 169 CKE1 NC 210 DQ45 10 DQ3 50 CKEO 91 DQ41 130 Vss 170 Vop 211 Vss 11 Vss 51 Vpop 92 Vss 131 DQ12 171 NC 212 DM5 12 DQ8 52 BA2 93 Dass 132 DQ13 172 NC 213 NC 13 DQ9 53 NC 94 DQS5 133 Vss 173 Voo 214 Vss 14 Vss 54 Vop 95 Vss 134 DM1 174 A12 BC 215 DQ46 15 Das1 55 A11 96 DQ42 135 NC 175 A9 216 DQ47 16 DQS1 56 A7 97 DQ43 136 Vss 176 Voo 217 Vss 17 Vss 57 Vpop 98 Vss 137 DQ14 177 A8 218 DQ52 18 DQ10 58 A5 99 DQ48 138 DQ15 178 A6 219 DQ53 19 DQ11 59 A4 100 DQ49 139 Vss 179 Vop 220 Vss 20 Vss 60 Vop 101 Vss 140 DQ20 180 A3 221 DM6 21 DQ16 61 A2 102 DQs6 141 DQ21 181 Al 222 NC 22 DQ17 62 Vop 103 DQS6 142 Vss 182 Voo 223 Vss 23 Vss 63 CK1 NC 1
23. RTPmin 28 Minimum four active window delay tFAWmin LSB Combo byte 28 29 01 00 29 Minimum four active window delay tFAWmin MSB 37 5ns 30ns 2C FO 7 RZQ 6 RZQ 7 30 SDRAM device output drivers suported DLL Off Mode Support 83 Extended Temperature Range ASR 31 SDRAM device thermal and refresh options ODTS PASR 8D 32 Module thermal sensor Non Thermal Sensor Support 00 33 SDRAM device type Standard Monolithic Device 00 34 59 Reserved Undefined 60 Module height nominal 29 lt height lt 30mm OF REV 1 0 11 2008 9 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HAIN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM elixir erial Presence Detect Part 2 of 2 2GB 256Mx64 2 Ranks UNBUFFERED DDR3 SDRAM DIMM based on 128Mx8 8Banks 8K Refresh 1 5V DDR3 SDRAMs with SPD Byte Description SPD Entry Value pae ima Note BE CG DG BE CG DG 61 Module thickness Max a Erea 7 ae 11 62 Raw Card ID reference Raw Card B 01 63 DRAM address mapping edge connector Undefined 01 64 116 Reserved 117 118 Module manufacture ID 830B 119 125 Module information 126 127 CRC 90D1 42F7 50A9 128 145 Module part number Undefined 146 Module die revision Undefined 00 147 Module PCB revision Nanya Technology 00 148 149
24. Unbuffered Dual In Line Memory Module UDIMM organized as one rank 128Mx64 and two ranks 256Mx64 high speed memory array M2F1G64CB88A9N uses eight 128Mx8 DDR3 SDRAMs M2F2G64CB8HASN uses sixteen 128Mx8 DDR3 SDRAMs These DIMMs are manufactured using raw cards developed for broad industry use as reference designs The use of these common design files minimizes electrical variation between suppliers All Elixir DDR3 SDRAM DIMMs provide a high performance flexible 8 byte interface in a 5 25 long space saving footprint The DIMM is intended for use in applications operating up to 533 MHz 667MHz or 800MH7z clock speeds and achieves high speed data transfer rates of up to 1066Mbps 1333 Mbps or 1600 Mbps Prior to any access operation the device CAS latency and burst length operation type must be programmed into the DIMM by address inputs AO A13 and I O inputs BAO BA1 and BA2 are using for the mode register set cycle The DIMM uses serial presence detect implemented via a serial 2 048 bit EEPROM using a standard IIC protocol The first 128 bytes of serial PD data are programmed and locked during module assembly The remaining 128 bytes are available for use by the customer REV 1 0 1 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HAIN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Ordering Information
25. ddress input defines the row address RAO RA13 During a Read or Write command cycle Address input defines the column address In addition to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BO and B1 to control which banks s to precharge If AP is high all banks will be precharged regardless of the state of BAO BA1 or BAZ If AP is low BAO BA1 and BA2 are used to define which bank to precahrge A12 BC is sampled during READ and WRITE commands to determine if burst chop on the fly will be performed High no burst chop Low burst chopped Data and Check Bit Input Output pins Power and ground for the DDR3 SDRAM input buffers and core logic Data strobe for input and output data DM is an input mask signal for write data Input data is masked when DM is sampled High coincident with that input data during a write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loadings These signals are tied at the system planar to either Vss or Vppspp to configure the serial SPD EEPROM address range This bi directional pin is used to transfer data into or out of the SPD EEPROM A external resistor must be connected from the SDA bus line to VDD to act as a pull up on the system board This signal is used to clock
26. ef to deviate from Vref DC by more than 1 VDD 3 For reference approx VDD 2 15mV REV 1 0 11 11 2008 i NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM M2Y1G64CB88A9N M2Y2G64CB8HA9ON Cel e Operating Standby and Refresh Currents Toase 0 C 85 C Vona Voo 1 5V 0 075V 1GB 1 Rank base on 128Mx8 DDR3 SDRAMs Symbol Parameter Condition DDR3 1066 DDR3 1333 DDR3 1600 Unit DDo Operating Current one bank activate Precharge 968 1056 1056 mA DD1 Operating Current one bank activate Read Precharge 1100 1188 1276 mA DD2P 0 Precharge Power Down Current Fast Exit MRO bit A12 0 141 141 141 mA DD2P 1 Precharge Power Down Current Slow Exit MRO bit A12 1 264 264 264 mA DD2N Precharge Standby Current 572 616 660 mA DD2Q Precharge Quiet Standby current 484 528 572 mA DD3P Active Power Down Current Always Fast Exit 352 396 440 mA DD3N Active Standby Current 572 616 660 mA DD4w Operating Current Burst Write 1408 1760 2024 mA DD4R Operating Current Burst Read 1408 1760 2200 mA DD5B Burst Refresh Current 2200 2376 2552 mA lDD6 Self Refresh Current Normal Temperature Range 0 85C 123 123 123 mA DD7 All Bank Interleave Read Current 2640 3168 3432 mA Note Module IDD was calculated from component IDD It may differ from the actual measurement Operating Standby and Refres
27. h Currents Toase 0 C 85 C Vona Von 1 5V 0 075V 2GB 2 Ranks base on 128Mx8 DDR3 SDRAMs Symbol Parameter Condition DDR3 1066 DDR3 1333 DDR3 1600 Unit DDo Operating Current one bank activate Precharge 1540 1672 1716 mA DD1 Operating Current one bank activate Read Precharge 1672 1804 1936 mA DD2P 0 Precharge Power Down Current Fast Exit MRO bit A12 0 282 282 282 mA DD2P 1 Precharge Power Down Current Slow Exit MRO bit A12 1 528 528 528 mA DD2N Precharge Standby Current 1144 1232 1320 mA DD2Q Precharge Quiet Standby current 968 1056 1144 mA DD3P Active Power Down Current Always Fast Exit 704 792 880 mA DD3N Active Standby Current 1144 1232 1320 mA DD4w Operating Current Burst Write 1980 2376 2684 mA DD4R Operating Current Burst Read 1980 2376 2860 mA DD5B Burst Refresh Current 2772 2992 3212 mA lDD6 Self Refresh Current Normal Temperature Range 0 85C 246 246 246 mA DD7 All Bank Interleave Read Current 3212 3784 4092 mA Note Module IDD was calculated from component IDD It may differ from the actual measurement REV 1 0 12 11 2008 i NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HAIN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM
28. l SPD Bytes 256 92 SPD Bytes Used 176 1 SPD revision Revision 1 0 10 2 DRAM device type DDR3 SDRAM 0B 3 Module type form factor UDIMM 02 4 SDRAM Device density and banks 8 banks 1Gb 02 5 SDRAM device row and column count 14 rows 10 columns 11 6 Reserved Undefined 00 7 Module ranks and device DQ count 2 ranks 8 bits 09 8 ECC tag and module memory Bus width Non ECC 64bits 03 9 Fine timebase dividend divisor in ps 2 5ps 52 10 Medium timebase dividend ins 01 11 Medium timebase divisor 8ns 08 12 Minimum SDRAM cycle time tCKmin ns 1 875 1 5 1 25 OF 0c 0A 13 Reserved Undefined 00 14 CAS latencies supported 6 7 8 6 8 9 5 6 7 8 9 10 1C 34 7E 15 CAS latencies supported Undefined 00 16 Minimum CAS latency time tAAmin ns 13 125 13 5 11 25 69 6C 5A 17 Minimum write recovery time tWRmin 15ns 78 18 Minimum CAS to CAS delay tRCDmin ns 13 125 13 5 11 25 69 6C 5A 19 Minimum Row Active to Row Active delay tRRDmin ns 7 5 6 3C 30 20 Minimum row Precharge delay tRPmin ns 13 125 13 5 11 25 69 6C 5A 21 Upper nibble for tRAS and tRC 1 1 11 22 Minimum Active to Precharge delay tRASmin ns 37 5 36 35 2C 20 18 23 Minimum Active to Active Refresh delay tRCmin ns 50 625 49 5 46 25 95 8C 72 24 Minimum refresh recovery delay tRFCmin LSB Combo bytes 24 25 70 25 Minimum refresh recovery delay tRFCmin MSB 110ns 03 26 Minimum internal Write to Read command delay tWTRmin 7 5ns 3C 27 Minimum internal Read to Precharge command delay 7 5ns 3C t
29. min tRFC min 10ns 10ns Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min tDLLK min nCK Minimum CKE low width for Self Refresh entry to exit tCKESR tCKE min p tCKE min 7 timing 1nCK 1nCK a a Self Refresh Entry SRE or icxsRE max 5nCK 10ns max 5nCK 10ns Pe E after Self Refresh Exit SRX or ICKSRX max 5nCK 10ns max 5nCK 10ns Power Down Timings Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not tXP max 3nCK 7 5ns max 3nCK 6ns requiring a locked DLL Slee eet Se EE frozenito tXPDLL max 10nCK 24ns max 10nCK 24ns CKE minimum pulse width tCKE a a Command pass disable delay tCPDED 1 1 nCK Power Down Entry to Exit Timing tPD tCKE min 9 tREFI tCKE min 9 tREFI Timing of ACT command to Power Down entry tACTPDEN 1 1 nCK Timing of PRE or PREA command to Power Down entry tPRPDEN 1 1 7 nCK Timing of RD RDA command to Power Down entry tRDPDEN RL 4 1 RL 4 1 nCK Timing of WR command to Power Down entry BL8OTF WRPDEN WL 4 tWR tCK a E WL 4 tWR tCK a 7 nCK BL8MRS BC4OTF vg vg et ee ec Pownentry WRAPDEN WL 4 WR 1 WL 4 WR 1 nCK Timing of WR command to Power Down entry BC4MRS tWRPDEN dai aay aah i tCK a 3 nCK BOANA command to Power Down entry IWRAPDEN WL 2 4WR 1 WL 24 WR 1 nCK Timing of REF command to Power down entry tREFPDEN 1 1 7 nCK Timing of MRS command to Power Down entry tMRSPDEN tMO
30. min st Tiperymax P Absolute clock high pulse width tCH abs 0 43 0 43 ps Absolute clock low pulse width tCL abs 0 43 0 43 ps Clock Period Jitter tUIT per 90 90 80 80 ps Clock Period Jitter during DLL locking period tUIT per Ick 80 80 70 70 ps Cycle to Cycle Period Jitter tUIT cc 180 160 ps Cycle to Cycle Period Jitter during DLL locking period tuIT cc Ick 160 140 ps Duty Cycle Jitter tJIT duty ps Cumulative error across 2 cycles tERR 2per 132 132 118 118 ps Cumulative error across 3 cycles tERR 3per 157 157 140 140 ps Cumulative error across 4 cycles tERR 4per 175 175 155 155 ps Cumulative error across 5 cycles tERR 5per 188 188 168 168 ps Cumulative error across 6 cycles tERR 6per 200 200 177 177 ps Cumulative error across 7 cycles tERR 7per 209 209 186 186 ps Cumulative error across 8 cycles tERR 8per 217 217 193 193 ps Cumulative error across 9 cycles tERR 9per 224 224 200 200 ps Cumulative error across 10 cycles tERR 10per 231 231 205 205 ps tERR npr min tERR npr max tERR npr min tERR npr max Cumulative error across n 11 50 cycles tERR nper 1 0 68In n tUIT 1 0 68In n tUIT 1 0 68In n tUIT 1 0 68In n tJIT ps per min per max per min per max Data Timing DQS DOS to DQ skew per group per access tDQSQ 150 125 ps DQ output hold time from DQS DQS tQH 0 38 0 38 tCK avg DQ low impedance time from CK CK tLZ DQ 600 300 500 250 ps DQ high impedance time from CK CK tHZ DQ 300
31. nd to Power Down entry BC4MRS tWRAPDEN WL 2 WR 1 nCK Timing of REF command to Power down entry tREFPDEN 1 nCK Timing of MRS command to Power Down entry tMRSPDEN tMOD min REV 1 0 18 11 2008 NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HAIN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM DDR3 1600 Parameter Symbol Min Max Units ODT Timings oa high time without write command or with write command and ODTH4 4 7 nCK ODT high time with Write command and BL8 ODTH8 6 nCK Asynchronous RTT turn on delay Power Down with DLL frozen tAONPD 1 9 ns Asynchronous RTT turn off delay Power Down with DLL frozen tAOFPD 1 9 ns RTT turn on tAON 225 225 ps RTT_Nom and RTT_WR turn off time from ODTLoff reference tAOF 0 3 0 7 tCK avg RTT dynamic change skew tADC 0 3 0 7 tCK avg Write Leveling Timings First DQS DQS rising edge after write leveling mode is programmed tWLMRD 40 nCK DQS DQS delay after write leveling mode is programmed tWLDQSEN 25 nCK Write leveling setup time from rising CK CK crossing to rising DQS WLS TBD 7 ps DQS crossing Write leveling setup hold from rising CK CK crossing to rising DQS iWLH TBD _ ps DQS crossing Write leveling output delay tWLO 0 7 5 ns Write leveling output error tWLOE 0 2 ns REV 1 0 19
32. s 101 pazs 4 102 paz7 M 1 03 D3 pazs M 104 pazg 105 paso M 1 06 pasi M 107 BA0 BA2 gt BA0 BA2 SDRAMs D0 D7 A0 A13 A0 A13 SDRAMs D0 D7 RAS gt RAS SDRAMs D0 D7 CAS gt TAS SDRAMs D0 D7 WE gt WE SDRAMs D0 D7 CKEO CKE SDRAMs D0 D7 ODTO gt ODT SDRAMs D0 D7 CKO CK SDRAMs D0 D7 CKO gt CK SDRAMs D0 D7 DM DQ48 1 00 DQ49 M 101 DQ50 1 02 DQ51 1 03 D6 DQ52 1 04 05 1 07 w pas4 M 1 06 w M W DM DQ56 N 1 00 M DQ58 N 1 02 DQ59 1 03 D7 DQ60 N 1 04 DQ61 N 1 05 DQ62 N 1 06 DQ63 N 1 07 SCL Vooso gt SPD Voo Voa _ D0 D7 Vrerpa gt D0 D7 Ve e e gt D0 D7 Vrerca e gt DO0 D7 Serial PD lt gt SDA WPao AM A2 sho sh sho REV 1 0 11 2008 5 x NANYA TECHNOLOGY CORP NANYA TECHNOLOGY CORP reserves the right to change Products and Specifications without notice M2Y1G64CB88AQ9N M2Y2G64CB8HASN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram 2GB 2 Rank 128Mx8 DDR3 SDRAMs
33. s and Specifications without notice M2Y1G64CB88A9N M2Y2G64CB8HAIN 1GB 128M x 64 2GB 256M x 64 Unbuffered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module DDR3 1600 Parameter Symbol Min Max Units Clock Timing Minimum Clock Cycle time DLL off mode tCK DLL_OFF 8 ns Average high pulse width tCH avg 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 tCK avg Absolute Clock Period tCK abs tCK avg min tUlT per min tCK avg max tJIT per max ps Absolute clock high pulse width tCH abs 0 43 ps Absolute clock low pulse width tCL abs 0 43 ps Clock Period Jitter tJIT per 70 70 ps Clock Period Jitter during DLL locking period tJIT per lck 60 60 ps Cycle to Cycle Period Jitter tJIT cc 140 ps Cycle to Cycle Period Jitter during DLL locking period tJIT cc Ick 120 ps Duty Cycle Jitter tJIT duty ps Cumulative error across 2 cycles tERR 2per 103 103 ps Cumulative error across 3 cycles tERR 3per 122 122 ps Cumulative error across 4 cycles tERR 4per 136 136 ps Cumulative error across 5 cycles tERR 5per 147 147 ps Cumulative error across 6 cycles tERR 6per 155 155 ps Cumulative error across 7 cycles tERR 7per 163 163 ps Cumulative error across 8 cycles tERR 8per 169 169 ps Cumulative error across 9 cycles tER
34. tion Short calibration time tZQCS 64 nCK Reset Timing Exit Reset from CKE HIGH to a valid command tXPR e tad F Self Refresh Timings Exit Self Refresh to commands not requiring a locked DLL tXS We C min Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min nCK Minimum CKE low width for Self Refresh entry to exit timing tCKESR ee a Valid Clock Requirement after Self Refresh Entry SRE or _ Power Down Entry PDE tCKSRE max 5nCK 10ns Valid Clock Requirement after Self Refresh Exit SRX or _ Power Down Exit PDX or Reset Exit tCKSRX max 5nCK 10ns Power Down Timings Exit Power Down with DLL on to any valid command Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL tXP max 3nCK 6ns Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL tXPDLL max 10nCK 24ns g CKE minimum pulse width tCKE max 3nCK 5ns Command pass disable delay tCPDED 1 nCK Power Down Entry to Exit Timing tPD tCKE min 9 tREFI Timing of ACT command to Power Down entry tACTPDEN 1 nCK Timing of PRE or PREA command to Power Down entry tPRPDEN 1 7 nCK Timing of RD RDA command to Power Down entry tRDPDEN RL 4 1 3 nCK beon command to Power Down entry BL8OTF BL8MRS IWRPDEN WL 4 tWR tCK avg 7 nCK Timing of WRA command to Power Down entry BL8OTF 7 BL8MRS BC4OTF tWRAPDEN WL 4 WR 1 nCK Timing of WR command to Power Down entry BC4MRS tWRPDEN WL 2 tWR tCK avg nCK Timing of WRA comma
35. tions in the DC level of the same Peak to peak noise on VREF may not exceed 2 of the DC value Environmental Parameters Symbol Parameter Rating Units Note Topr Module Operating Temperature Range ambient 0 to 55 C 3 Hopr Operating Humidity relative 10 to 90 1 TsTG Storage Temperature Plastic 50 to 100 C 1 HsTG Storage Humidity without condensation 5 to 95 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a tress rating only and device functional operation at or above the conditions indicated is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Up to 9850 ft 3 The component maximum case temperature shall not exceed the value specified in the component spec Single Ended AC and DC Input Levels DDR3 1066 DDR3 1333 DDR3 1600 Symbol Parameter Units Note Min Max VIH DC DC input logic high Vref 0 100 VDD V 1 VIL DC DC input logic low VSS Vref 0 100 V 1 VIH AC AC input logic high Vref 0 175 V 1 VIL AC AC input logic low z Vref 0 175 V 1 VrefDQ DC Reference Voltage for DQ DM inputs 0 49 VDD 0 51 VDD V 2 3 VrefCA DC Reference Voltage for ADD CMD inputs 0 49 VDD 0 51 VDD V 2 3 Note 1 For DQ and DM Vref VrefDQ For input only pins except RESET Vref VrefCA 2 The AC peak noise on Vref may not allow Vr

Elixir M2Y2G64CB8HA9NDG memory module

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