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Intel Itanium 9140M

1. Pin Name i E Input Output Notes GND GND AD21 IN GND GND AD23 IN GND GND AD25 IN GND GND AE02 IN GND GND AE24 IN GND GND AF01 IN GND GND AF05 IN GND GND AF07 IN GND GND AF09 IN GND GND AF11 IN GND GND AF13 IN GND GND AF15 IN GND GND AF17 IN GND GND AF19 IN GND GND AF21 IN GND GND AG02 IN GND GND AG04 IN GND GND AG06 IN GND GND AG08 IN GND GND AG10 IN GND GND AG12 IN GND GND AG14 IN GND GND AG16 IN GND GND AG18 IN GND GND AG20 IN GND GND AG22 IN GND GND AG24 IN GND GND AH01 IN GND GND B03 IN GND GND 05 GND GND BO7 IN GND GND 09 GND GND B10 IN GND GND 11 GND GND B13 IN GND GND B15 IN GND GND B17 IN GND GND B19 IN GND GND B21 IN GND GND B23 IN GND GND B25 IN GND GND C02 IN GND GND C06 IN GND GND C10 IN Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 1 Signal Information Sorted by Pin Name Sheet 8 of 15 Pin Name Eis eed Tia s Input Output Notes GND GND C14 IN GND GND C18 IN GND GND C22 IN GND GND D01 IN GND GND D03 IN GND GND D05 IN GND GND D07 IN GND GND D09 IN GND GND D11 IN GND GND D13 IN GND GND D15 IN GND GND D17 IN GND GND D19 IN GND GND D21 IN
2. Pin Name Th m Input Output Notes D009 D09 H06 IN OUT GND GND H07 IN D042 D42 H08 IN OUT GND GND 09 0032 032 10 IN OUT GND GND H11 IN D046 D46 H12 IN OUT GND GND H13 IN DO75 D75 H14 IN OUT GND GND H15 IN 2076 D76 H16 IN OUT GND GND H17 IN DO77 D77 H18 IN OUT GND GND H19 IN 0111 0111 H20 IN OUT GND GND H21 IN D105 D105 H22 IN OUT GND GND H23 IN D109 D109 H24 IN OUT GND GND H25 IN GND GND 01 VCTERM VCTERM 102 D013 D13 J03 IN OUT GND GND 104 DEPO1 DEP1 105 IN OUT VCTERM VCTERM 106 DEPOO DEPO 107 IN OUT GND GND 108 DEPO4 DEP4 109 IN OUT VCTERM VCTERM 10 DEPO5 DEP5 11 IN OUT GND GND 12 0047 D47 13 IN OUT VCTERM VCTERM 14 DO78 D78 J15 IN OUT GND GND 16 9 9 17 IN OUT VCTERM VCTERM 18 DEPO8 DEP8 j19 IN OUT GND GND 20 DEP12 DEP12 21 IN OUT VCTERM VCTERM 22 DEP13 DEP13 23 IN OUT GND GND 24 54 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 6 of 15 Pin Name Input Output Notes D110 D110 25 IN OUT N C K02 GND GND K03 IN 0016 016
3. 102 STBp 7 0 and STBn 7 0 5 1 4 4 22 114414 4 104 mm 105 EEUU 105 Input Output Signals Single 0 mne 106 Input Output Signals Multiple 2 107 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 7 intel Revision History Document Revision Description Dare Number Number 314054 002 Updated with 9100 series product information updated brand name from October 2007 Itanium 2 to Itanium 314054 001 Initial release of the document July 2006 8 Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet intel Dual Core Intel Itanium Processor 9000 and 9100 Series Dual Core Intel Itanium Processor 1 6 GHz with 24 MB L3 Cache 9050 Dual Core Intel Itanium Processor 1 6 GHz with 18 MB 13 Cache 9040 Dual Core Intel Itanium Processor 1 6 GHz with 8 MB Cache 9030 Dual Core Intel Itanium Processor 1 42 GHz with 12 MB L3 Cache 9020 Dual Core Intel Itanium Processor 1 4 GHz with 12 MB L3 Cache 9015 Intel I tanium Processor 1 6 GHz with 6 MB 13 Cache 9010 Dual Core Intel Itanium Processor 1 66 GHz with 24 L3 Cache 9150M Dual Core Intel Itanium Processor 1 6 GHz with 24
4. 1 4 1 41 1 EE nen nennen nnne nnn nnn 87 Command Byte Bit 4 70 2 2 1 0 0 88 Thermal Sensing Device Status Register 89 Thermal Sensing Device Configuration ee 89 Thermal Sensing Device Conversion Rate 90 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 1 2 A 3 A 5 A 4 A 6 A 7 A 8 A 9 A 10 11 12 13 14 15 Address Space SIZze secti bM ORTA MM LEM a E DUE UE 92 Effective Memory Type Signal 92 Special Transaction Encoding on Byte 93 BRO 1 0 BR1 BR2 BR3 Signals for 2P Rotating Interconnect 95 BRO 1 0 BR1 BR2 BR3 Signals for Rotating Interconnect 95 BR 3 0 Signals Agent 5 95 DID 9 01 97 Extended trm Rer E E UD Xu RR ERR RE an EXER kain 98 Length of Data Transfers ici te e td E tinned FEAR AUTRE ERR TERRI IP adn cian 100 Transaction Types Defined by REQa REQb
5. Top View Front View 001349 66 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Mechanical Specifications n tel Table 4 1 Processor Package Dimensions MILLIMETERS COMMENTS MIN MAX B 112 9 113 B 48 16 18 36 C 49 9 50 1 b 42 4 42 6 11 CJAI D 11 5 2 1 668 5 368 G 34 29 BASIC 6 30 48 BASIC 30 5 BASIC 120 06 8 H 5 24 BASIC j J 27 BASIC 7 1 27 BASIC p 0 28 0 33 Figure 4 2 Package Height and Pin Dimensions IHS 7 0 185 SUBSTRATE 0 65 MAX mE 2 34 0 08 0 31 MAX P 0 65 MAX 0254 0 0650 01 030 DETAIL A Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 67 n tel Mechanical Specifications Table 4 2 Processor Package Mechanical I nterface Dimensions MILLIMETERS SYMBOL COMMENTS MIN T 15 24 BASIC 8 43 5 BASIC Ha 1 263 BASIC de 045 C D a 21 16 BASIC 3 1 27 BASIC 4 1 8 BASIC 2 0 875 0 925 3 275 325 4 25 BASIC 59 1015010 MILLIMETERS SYMBOL COMMENTS MIN M
6. 108 VCTERM L12 IN VCTERM VCTERM L16 IN VCTERM VCTERM L20 IN VCTERM VCTERM L24 IN VCTERM VCTERM N02 IN VCTERM VCTERM N06 IN VCTERM VCTERM N10 IN VCTERM VCTERM N14 IN VCTERM VCTERM N18 IN VCTERM VCTERM N22 IN VCTERM VCTERM RO1 IN VCTERM VCTERM R04 IN VCTERM VCTERM R08 IN VCTERM VCTERM R12 IN VCTERM VCTERM R16 IN VCTERM VCTERM R20 IN VCTERM VCTERM R24 IN VCTERM VCTERM U02 IN VCTERM VCTERM U06 IN VCTERM VCTERM U10 IN VCTERM VCTERM U14 IN VCTERM VCTERM U18 IN VCTERM VCTERM 022 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 49 intel Pinout Specifications Table 3 1 Pin Signal Information Sorted by Pin Name Sheet 15 of 15 Pin Name lider TN Input Output Notes VCTERM VCTERM U25 IN VSSMON VSSMON A09 N C Table 3 2 Pin Signal I nformation Sorted by Pin Location Sheet 1 of 15 Pin Name Input Output Notes GND GND 01 VCTERM VCTERM 02 GND GND A03 IN N C A04 GND GND A05 IN VCTERM VCTERM A06 IN THRMALERT THRMALERT 07 OUT GND GND 08 VSSMON VSSMON 09 VCTERM VCTERM 10 VCCMON VCCMON All N C GND GND A13 IN VCTERM VCTERM A14 IN SMA2 SMA2 A15 IN SMBus signal GND GND A16 IN 5 1 5 1 17 SMBus signal VCTERM VCTERM 18 GND GND 19
7. Maximum Unit Notes ViL Input Low Voltage A V 1 Input High Voltage A 0 875 V 1 VoL Output Low Voltage A 0 3 V 2 Output High Voltage A VCTERM VCTERM VcTERM V minimum maximum lon Output Low Current 0 3 V A 34 mA 3 lo Output Low Current 0 3 V A 17 mA lu Leakage Current A 5 CAGTL AGTL Pad Capacitance A pF 6 Notes 1 The typical transition point between Vi and Vj assuming 125 mV uncertainty for ODT Veer nigh and evels are Vref 100 respectively for a system bus agent using on board termination Vger high and VREF low levels Veer 125 respectively for a system bus agent using on die termination VREF_low d characterization gvn Sw by design for all AGTL buffers Power Good Signal DC Specifications Calculated using off die termination through two 45 ohm 1 resistors in parallel Calculated using on die termination to a 45 15 resistor measured at Vo At 1 2 V 1 5 minimum lt Vpin lt maximum Total of 1 0 buffer with ESD structure and processor parasitics if applicable Capacitance values guaranteed Parameter measured into a 22 5 ohm resistor to 1 2 V Minimum Vo and lo are guaranteed by design Symbol Parameter Minimum Maximum Unit Notes Input Low Voltage 0 440 V Input High Voltag
8. Name Active Level Clock Signal Group Qualified ID 9 0 Low BCLKp Defer IDS 105 1 IDS Low BCLKp Defer Always INIT Low Asynch Exec Control Always INT LINTO High Asynch Exec Control 1 1 0 Low BCLKp System Bus IDS 41 NMI LINT1 High Asynch Exec Control RESET Low BCLKp Control Always RS 2 0 Low BCLKp Response Always RSP Low BCLKp Response Always PMI Low Asynch Exec Control PWRGOOD High Asynch Control TCK High Diagnostic Always TDI High TCK Diagnostic Always TMS High TCK Diagnostic Always TRST Low Asynch Diagnostic Always TRDY Low BCLKp Response Response Phase Notes 1 Synchronous assertion with asserted RS 2 0 guarantees synchronization Table 14 Input Output Signals Single Driver Sheet 1 of 2 106 Name Active Level Clock Signal Group Qualified 49 3 Low BCLKp Request ADS ADS 4 1 ADS Low BCLKp Request Always AP 1 0 Low BCLKp Request ADS ADS 4 1 ASZ 1 0 Low BCLKp System Bus ADS ATTR 3 0 Low BCLKp System Bus ADS 4 1 BE 7 0 Low BCLKp System Bus ADS 4 1 BRO Low BCLKp System Bus Always BPM 5 0 Low BCLKp Diagnostic Always CCL Low BCLKp System Bus ADS 1 D 127 0 Low BCLKp Data DRDY DBSY Low BCLKp Data Always D C Low BCLKp System Bus ADS DEN Low BCLKp System Bus ADS 1 DEP 15 0 Low BCLKp System Bus DRDY DID 9 0 Low BCLKp System Bus ADS 41 DRDY Low BCLKp Data Always
9. Pin Name Tom Input Output Notes GND GND 09 GND GND Y11 IN GND GND Y13 IN GND GND 15 GND GND Y17 IN GND GND Y19 IN GND GND 21 GND GND Y23 IN GND GND Y25 IN GSEQ GSEQ AD14 IN HIT HIT AB10 IN OUT HITM HITM AB12 IN OUT 100 DAO 1PO AD02 IN 101 12 1 1 1 ABO2 IN 102 IDA2 DHIT 103 IDA3 IDB3 AA03 IN ID4 IDA4 IDB4 AD04 IN ID5 IDA5 IDB5 AB04 IN ID6 IDA6 IDB6 AE05 IN ID7 IDA7 IDB7 AC05 IN ID8 IDA8 IDB8 AD06 IN ID9 IDA9 IDB9 AB06 IN IDS IDS AC07 IN IGNNE IGNNE AG23 N C INIT INIT AF08 IN LINTO INT AF22 IN LINT1 NMI AF24 IN LOCK LOCK AE15 N C N C A04 N C AB16 17 21 AD18 N C AE17 N C 05 11 AG17 N C 19 AG21 N C 5 11 17 19 AH21 Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet Pinout Specifications tel Table 3 1 Signal Information Sorted by Pin Name Sheet 12 of 15 Pin Name 58 Input Output Notes N C 04 06 08 14 16 B20 N C C13 N C 15 C25 N C K02 N C K12 N C K14 N C K24 N C 005 011 OUTEN OUTEN AF04 IN Power pod signal PMI PMI AE25 IN PPODGD PPODGD AF20 OUT Power
10. 62 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 2 intel Pin Signal I nformation Sorted by Pin Location Sheet 14 of 15 Pin Name E uan eae Input Output Notes BRO BREQO AF16 IN OUT GND GND AF17 IN BR3 BREQ3 AF18 IN GND GND AF19 IN PPODGD PPODGD AF20 OUT Power pod signal GND GND AF21 IN LINTO INT AF22 IN LINT1 NMI AF24 IN GND GND 02 TUNER 2 0 GND GND 04 05 GND GND 06 TDI TDI AGO7 IN JTAG GND GND 08 09 JTAG GND GND AG10 IN N C 11 GND GND AG12 IN BCLKp CLK AG13 IN GND GND AG14 IN CPUPRES CPUPRES AG15 OUT Power pod signal GND GND AG16 IN N C AG17 GND GND AG18 IN N C 19 GND GND AG20 IN N C AG21 GND GND AG22 IN IGNNE IGNNE AG23 N C GND GND AG24 IN THRMTRIP THRMTRIP AG25 OUT Thermal trip GND GND AH01 IN TUNER 1 AH03 IN N C AH05 TDO TDO AH07 OUT JTAG TMS TMS AH09 IN JTAG N C AH11 BCLKn BCLKN AH13 IN PWRGOOD PWRGOOD AH15 IN N C AH17 N C AH19 N C AH21 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 63 intel Table 3 2 64 Pinout Specifications Pin Signal Information Sorted by Pin Location Sheet 15 of 15 System Bus Pin Pin Name Signal Name L
11. HTM A25 AIS De2t 057 051 VC NC GND D46t VC D44 GND VO TERM TERM TERM TERM O O O O O O O O O O O O O O O O O O O O BOLKN BCLKP GND SESY GND FP GND SESY0O A22 GND A166 GND D69 GND D55 GND 052 GND D4zit GND GND D89 GND NC GND GND 14 O O O O O O 14 GND TFDY DEFER D Ds7 VC NC 07 D68 065 GND NC VW TERM TERM TERM TERM TERM 5 O O O O O O O O O O O O O O O O O 15 PAR PROC GND LOCK GND TND GND BINT GND A37 GND 28 GND 2 GND D91 GND D81 GND D GND 071 GND 05 GND NC GND SWe 16 O O O O O 46 GND BREQI NC A38 11 VC STBPS VC D83 GND D 6 STBNM4 GND 066 NC GND TERM TERM TERM 7 O O O O O O NC NC GND NC GD NC GND GND GND BNR GND 089 GND STBN5 GND 088 GND DEPS GND 072 GND STEP4 GND D73 GND SMAI 18 18 GND BREGBH NC A35 A29 DEPIO 295 VC Dso D77 Des WC D644 GND WMO VC TERM TERM TERM TERM TERM 9 O O qs NC NC GND GND SBSY14 GND DBSY1 GND A30 GND A27 GND D90t GND DS GND Dee GND
12. SMSC Clock Low Time 4 7 us 1 SMSC Clock Rise Time 1 0 us 1 trail SMSC Clock Fall Time 0 3 us tvALID SMBus Output Valid Delay 1 0 us tsu SMBus Input Setup Time 250 ns tup SMBus Input Hold Time 0 ns FREE Bus Free Time 4 7 us 2 Notes 1 Please refer to Figure 2 2 for the Standard Microsystems Corporation SMSC clock waveform 2 Bus Free Time is the minimum time allowed between request cycles Figure 2 1 Generic Clock Waveform Thigh Tiow Trise 80 e 20 pamm Anm ii tn in ai alsin nap nana Tjitter Trise Rise Time Tperiod Period Fall Time Tjitter Long Term Peak to Peak Jitter Thigh High Time Vpp Peak to Peak Swing Low Time 000615 21 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet intel Figure 2 2 2 4 1 Table 2 12 22 Electrical Specifications SMSC Clock Waveform SMSC Trise Rise Time Thigh High Time Fall Time Low Time 000618 Maximum Ratings Table 2 12 contains the processor stress ratings Functional operation at the absolute maximum and minimum is neither implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating conditions are given in the DC tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circu
13. 4 4 1 1 6 67 Processor Package Mechanical Interface 68 Processor Package Load Limits at Power Tab 71 Case Temperature Specification cece ee eect eee eese ens 77 System Management Interface Signal 79 Thermal Sensing Device SMBus Addressing on the Dual Core Intel Itanium Processor 9000 9100 81 EEPROM SMBus Addressing on the Dual Core Intel tanium Processor 9000 and 9100 Series ua ua rir cercana eer erede Ea t r Ra REA KEY e RR 82 Processor Information ROM 61 nnne nnn 82 Current Address Read SMBus 85 Random Address Read SMBus 010 86 Byte Write SMBUS Packet pena bere oes Pus Levi ede er Ere Las er ex lan e E S ea 86 Write Byte SMBus enn 87 Read Byte SMBus Packet o Ve PER Ra eure e beni e PEE er Ua Ede 87 Send Byte SMBUS 0020 seem sene emen 87 Receive Byte SMBus eee nee eene 87 ARA SMBUS
14. memory or 1 0 transactions the byte enable signals indicate that valid data is requested or being transferred on the corresponding byte on the 128 bit data bus BE 0 indicates that the least significant byte is valid and BE 7 indicates that the most significant byte is valid Since BE 7 0 specifies the validity of only 8 bytes on the 16 byte wide bus A 3 is used to determine which half of the data bus is validated by BE 7 0 For special transactions REQa 5 0 001000B and REQb 1 0 01B the BE 7 0 signals carry special cycle encodings as defined in Table A 3 All other encodings are reserved Special Transaction Encoding on Byte Enables Special Transaction Byte Enables 7 0 NOP 0000 0000 Shutdown 0000 0001 Flush INVD 0000 0010 Halt 0000 0011 Sync WBINVD 0000 0100 Reserved 0000 0101 StopGrant Acknowledge 0000 0110 Reserved 0000 0111 xTPR Update 0000 1000 For Deferred Reply transactions 7 0 signals are reserved Defer Phase transfer length is always the same length as that specified in the Request Phase except the Bus Invalidate Line BIL transaction A BIL transaction may return one cache line 128 bytes BERR 1 Bus Error BERR signal be asserted to indicate recoverable error with global MCA BERR assertion conditions are configurable at the system level Configuration options enable BERR to be driven as follows
15. 0 5 AF 0 25 0 1 AF 0 05 AF 0 01 165 0 45 0 01248 0 0144 0 0230 0 0461 0 1155 0 2301 11530 1 6 0 4 0 0380 0 0507 0 0763 0 1522 0 3814 0 7627 3 75 1 55 0 35 0 1250 0 1668 0 2507 0 5004 1 2537 2 5059 3 75 1 5 0 3 0 4054 0 5424 0 8163 1 6302 3 75 3 75 3 75 1 45 0 25 1 3013 1 7396 2 6246 3 75 3 75 3 75 3 75 1 4 0 2 3 75 3 75 3 75 3 75 3 75 3 75 3 75 1 35 0 15 3 75 3 75 3 75 3 75 3 75 3 75 3 75 Notes 1 Activity Factor 1 means signal toggles every 7 5 ns Voltage Regulator Connector Signals The VR module consists of three DC DC converters Vcore Veacher V ixeg Table 2 18 lists all of the signals which are part of the processor package VR output connector VR Connector Signals Group Name Signals Voltage Regulator PPODGD CPUPRES GND Vid_valid Vid_Core 5 0 Connector Vid_cache 5 0 Vcache_sense Gnd_sense Vcore_sense Vfixed_sense OUTEN If the VR cannot supply the voltages requested by the components in the processor package then it must disable itself Figure 2 4 shows the top view of the processor package power tab See Table 2 19 for power tab connector signals Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 27 tel Electrical Specifications Figure 2 4 Processors Power Tab Physical Layout Power Tab IHS Pin 1 N 0000000 600000000 6609 0 56005 600000 00000 Top
16. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low During the Idle state of RS 2 0 RS 2 0 000 RSP is also high since it is not driven by any agent guaranteeing correct parity SBSY 1 0 The Strobe Bus Busy SBSY signal is driven by the agent transferring data when it owns the strobe bus SBSY holds the strobe bus before the first DRDY and between DRDY assertions for a multiple clock data transfer SBSY is deasserted before DBSY to allow the next data transfer agent to predrive the strobes before the data bus is released SBSY is replicated three times to enable partitioning of data paths in the system agents This copy of the Strobe Bus Busy signal SBSY is an input as well as an output SBSY_C1 O SBSY is a copy of the Strobe Bus Busy signal This copy of the Strobe Bus Busy signal SBSY_C1 is an output only SBSY_C2 SBSY is a copy of the Strobe Bus Busy signal This copy of the Strobe Bus Busy signal SBSY_C2 is an output only SPLCK 1 Split Lock SPLCK signal is driven the second clock of the Request Phase on the 6 pin of the first transaction of a locked operation It is driven to indicate that the locked operation will consist of four locked transactions STBn 7 0 STBp 7 0 1 STBp 7 0 and STBn 7 0 and DRDY are used to transfer data at the 2x transfer rate in li
17. 005 AA05 EXF2 U03 IN OUT GND GND 004 005 VCTERM VCTERM U06 IN 009 09 1 007 IN OUT 018 AA18 DID2 009 VCTERM VCTERM 010 011 016 AA16 DIDO U13 IN OUT VCTERM VCTERM 014 028 AA28 xTPRValuel 015 BNR BNR 017 VCTERM VCTERM 018 027 AA27 XTPRValueO 019 58 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 10 of 15 intel Pin Name mom Input Output Notes GND GND U20 IN 048 48 48 021 VCTERM U22 IN 042 42 42 023 GND GND U24 IN VCTERM VCTERM U25 IN GND GND vol IN A004 AA04 EXF1 v02 IN OUT GND GND v03 IN 010 AA10 BE2 V04 IN OUT GND GND V05 IN 003 AA03 EXFO V06 IN OUT GND GND V07 IN 015 AA15 BE7 V08 IN OUT GND GND V09 IN 020 AA20 DID4 V10 IN OUT GND GND V11 IN 019 AA19 DID3 V12 IN OUT GND GND V13 IN 031 AA31 xTPRDisable V14 IN OUT GND GND V15 IN 038 AA38 AB38 V16 IN OUT GND GND V17 IN 029 AA29 xTPRValue2 V18 IN OUT GND GND V19 IN 045 AA45 AB45 V20 IN OUT GND GND V21 IN A047 AA47 AB47 22 GND GND V23 IN A040 AA40 AB40 V2
18. 12h 00h 11h 3 10h 2 OFh 1 OEh S 14h 2 Sample Production 00b Sample only MSB First 00000001b Production 15h 8 Reserved Reserved for future use 00h 16h 8 Checksum 1 byte checksum Add up by byte and take 2 s complement Core 17h 8 Architecture Revision From CPUID Taken from CPUI D 3 archrev 18h 8 Processor Core Family From CPUID Taken from CPUI D 3 family 19h 8 Processor Core Model From CPUID Taken from CPUI D 3 model 1Ah 8 Processor Core Stepping From CPUID Taken from CPUI D 3 revision 1Bh 24 Reserved Reserved for future use 000000h 1 16 Maximum Core Frequency Four 4 bit hex digits in MHz 1 GHz 1000h 2 20h 12 Maximum System Bus Three 4 bit hex digits in MHz 200 MHz 200h 1 Frequency 22h 16 Core Voltage ID Voltage in four 4 bit hex digits 1500 mV 1500h 1 in mV 24h 8 Core Voltage Tolerance High Edge finger tolerance in mV 1 5 22 mV 22h 1 two 4 bit hex digits 25h 8 Core Voltage Tolerance Low Edge finger tolerance 1 5 22 mV 22h two 4 bit hex digits 26h 8 Reserved Reserved for future use 00h 27h 8 Checksum 1 byte checksum Add up by byte and take 25 complement Cache 28h 32 Reserved Reserved for future use 00000000h 2Ch 16 Cache Size Four 4 bit hex digits in Kbytes 3072 Kbytes 3072h 53 2Eh 64 Reserved Reserved for future use 36h 8 Checksum 1 byte checksum Package 37h 32 Package Revision Four 8 bit ASCII characters NE 37
19. FERR The FERR signal may be asserted to indicate a processor detected error when IERR mode is enabled If IERR mode is disabled the FERR signal will not be asserted in the processor system environment GSEQ 1 Assertion of the Guaranteed Sequentiality GSEQ signal indicates that the platform guarantees completion of the transaction without a retry while maintaining sequentiality HIT 1 O and HITM 1 0 The Snoop Hit HIT and Hit Modified HITM signals convey transaction snoop operation results Any bus agent can assert both HIT and HITM together to indicate that it requires a snoop stall The stall can be continued by reasserting HIT and HITM together 10 9 0 1 The Transaction ID 10 9 0 signals are driven by the deferring agent The signals in the two clocks are referenced Da 9 0 and IDb 9 0 During both clocks 10 9 0 signals are protected by the PO parity signal for the first clock and by the IP 1 parity signal on the second clock Da 9 0 returns the ID of the deferred transaction which was sent on Ab 25 16 DID 9 0 IDS 1 The ID Strobe 105 signal is asserted to indicate the validity of ID 9 0 in that clock and the validity of DHIT and 1 1 0 in the next clock 1 IGNNEZ is no connect and is ignored the processor system environment INI T 1 The Initialization INIT signal triggers an unmasked interrupt to the processor INIT
20. System Management Signals 3 3 V SMA 2 0 SMSC SMSD SMWP THRMALERT Power Signals GND VCTERM LVTTL Power Pod Signals CPUPRES OUTEN PPODGD Other TERMA TERMB TUNER1 TUNER2 TUNER3 VCCMON VSSMON Notes 1 Signals will not be terminated on die even when on die termination ODT is enabled See the ntel Itanium 2 Processor Hardware Developer s Manual for further details All system bus outputs should be treated as open drain signals and require a high level source provided the supply AGTL inputs have differential input buffers which use Vggr as a reference level AGTL output signals require termination to this document AGTL Input Signals refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output Signals refers to the AGTL output group as well as the AGTL I O group when driving The Test Access Port TAP connection input signals use a non differential receiver with levels that are similar to AGTL No reference voltage is required for these signals TAP Connection Output signals are AGTL output signals The processor system bus requires termination on both ends of the bus The processor system bus supports both on die and off die termination controlled by two pins TERMA and TERMB Please see the TERMA and TERMB pin description in Section 2 2 2 The HSTL clock signals are the differential clock inputs for the processo
21. Asserted by the requesting agent of a bus transaction after it observes an internal error Asserted by any bus agent when it observes an error in a bus transaction When the bus agent samples an asserted BERR signal and BERR sampling is enabled the processor enters a Machine Check Handler BERRZ is a wired OR signal to allow multiple bus agents to drive it at the same time Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 93 intel ee A 1 10 1 11 1 12 1 13 1 14 94 BINIT I O If enabled by configuration the Bus Initialization BINIT signal is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration and BINIT is sampled asserted all bus state machines are reset All agents reset their rotating IDs for bus arbitration to the same state as that after reset and internal count information is lost The L2 and L3 caches are not affected If BINIT observation is disabled during power on configuration BINIT is ignored by all bus agents with the exception of the priority agent The priority agent must handle the error in a manner that is appropriate to the system architecture BINIT is a wired OR signal BNR 1 0 The Block Next Request BNR signal is used to assert a bus stall by any bus agent that is unable to accept new bus transactions to avoid an internal transaction queue overflow
22. DPS Low BCLKp System Bus ADS 1 DSZ 1 0 Low BCLKp System Bus ADS 1 EXF 4 0 Low BCLKp System Bus ADS 1 FCL Low BCLKp System Bus ADS 1 LEN 2 0 Low BCLKp System Bus ADS 1 OWN Low BCLKp System Bus ADS 1 Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet Signals Reference Table A 14 Input Output Signals Single Driver Sheet 2 of 2 Table A 15 intel Name Active Level Clock Signal Group Qualified REQ 5 0 Low BCLKp Request ADS ADS 1 RP Low BCLKp Request ADS 5 1 SBSY Low BCLKp Data Always SPLCK Low BCLKp System Bus ADS 1 STBn 7 0 Low Data Always STBp 7 0 Low Data Always WSNP Low BCLKp System Bus ADS Input Output Signals Multiple Driver Name Active Level Clock Signal Group Qualified BNR Low BCLKp System Bus Always BERR Low BCLKp Error Always BINIT Low BCLKp Error Always HIT Low BCLKp Snoop Snoop Phase HITM Low BCLKp Snoop Snoop Phase TND Low BCLKp Snoop Always Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 107 intel 108 Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet
23. EA Rap 93 A 1 10 BINITA a a Plone ege jn o e tk 94 al cape RUNE Db ed Rn ice dba Uu 94 A 112 BPME5 0T9E 2555 eene vs aca artnet Er tai ra fer nn 94 A 1 13 t m acc en ERES EI ORBE EP ER IN 94 1 14 BR O 1 0 and 3 1 1 2 4 4 0 0 94 A 1 15 BREQI 3 0 screen eo rre anced eem PU eR EX RR RET A ER EYE n 95 16 MM EEUU 96 A 1 17 CPUPRES 3 RR 96 1 185012 7070 96 A 1 19 D CH C O 96 1 20 DBSY VQ A PAA 96 1 21 DBS 0 Untere prias 96 A 1 22 DBSY C235 96 A 1 23 DEBER D oce neret akun OUR 96 CO adc er del dri E uo 97 A 1 25 DEP 15 0 9F 01 0 racer P Rok ar ant ek Pere 97 A126 DAT CL atenta 97 98 1 28 DRDY RUD cats 98 1 29 DRDY CLA XEM 98 A 1 30 DRDY_C2 Q waqaq aska aaa asawa qia
24. GND GND N24 IN GND GND P01 IN GND GND P03 IN GND GND P05 IN GND GND P07 IN Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 1 Signal Information Sorted by Pin Name Sheet 10 of 15 Pin Name Eis eed Thom Input Output Notes GND GND P09 IN GND GND P11 IN GND GND P13 IN GND GND P15 IN GND GND P17 IN GND GND P19 IN GND GND P21 IN GND GND 23 GND GND P25 IN GND GND RO2 IN GND GND 01 GND GND GND GND T05 IN GND GND T07 IN GND GND T09 IN GND GND T11 IN GND GND T13 IN GND GND T15 IN GND GND T17 IN GND GND T19 IN GND GND T21 IN GND GND T23 IN GND GND T25 IN GND GND 004 GND GND U20 IN GND GND U24 IN GND GND vol IN GND GND V03 IN GND GND V05 IN GND GND V07 IN GND GND V09 IN GND GND V11 IN GND GND V13 IN GND GND V15 IN GND GND V17 IN GND GND V19 IN GND GND V21 IN GND GND 23 GND GND V25 IN GND GND wo2 IN GND GND 01 GND GND Y03 IN GND GND Y05 IN GND GND YO7 IN Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 45 intel Table 3 1 46 Pin Signal Information Sorted by Pin Name Sheet 11 of 15 Pinout Specifications
25. and participate in the transaction as necessary as shown in Table A 10 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 101 L e intel SEE Table A 10 Transaction Types Defined by REQa REQb Signals REQa 5 0 REQb 5 0 Transaction 5 4 3 2 1 0 5 4 3 2 1 0 Deferred Reply 0 0 0 0 0 0 0 x x Reserved 0 0 0 0 0 1 0 x x Interrupt 0 0 1 0 0 0 0 DSZ 1 0 Acknowledge Special 0 1 0 0 0 0 DSZ 1 0 0 0 1 Transactions Reserved 0 0 1 0 0 0 0 DSZ 1 0 0 1 Reserved 0 0 1 0 0 1 0 DSZ 1 0 0 Interrupt 0 0 1 0 0 1 0 DSZ 1 0 1 0 0 0 0 1 0 0 1 0 DSZ 1 0 1 0 1 Reserved 0 0 1 0 0 1 0 DSZ 1 0 1 1 x 1 O Read 0 1 0 0 0 0 0 DSZ 1 0 x x x 1 O Write 0 T 0 0 0 1 0 DSZ 1 0 x x x Reserved 0 1 1 0 0 0 DSZ 1 0 x x x Memory Read amp 0 ASZ 1 0 0 1 0 0 DSZ 1 0 LEN 2 0 Invalidate Reserved 0 ASZ 1 0 0 1 1 0 DSZ 1 0 LEN 2 0 Memory Read 0 ASZ 1 0 1 D C 0 0 DSZ 1 0 LEN 2 0 Memory Read 1 ASZ 1 0 1 0 0 0 DSZ 1 0 LEN 2 0 Current Reserved 1 ASZ 1 0 1 1 0 0 DSZ 1 0 LEN 2 0 Memory Write 0 5711 01 1 WSNP 1 0 DSZ 1 0 LEN 2 0 Cache Line 1 ASZ 1 0 1 WSNP 1 0 DSZ 1 0 0 0 0 Replacement A 1 51 RESET I Asserting the RESET signal resets all processors to known states and invalidates all caches without writing back Modified M state lines RESET must remain asse
26. is defined in Table 2 20 VID pins will be controlled by the processor Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 29 intel Electrical Specifications Table 2 20 Processors Core Voltage Identification Code Vcore and Processor Pins 0 low 1 high 400 200 100 50 25 12 5 mV 400 200 100 50 25 12 5 mV VID VID VID VID VID VID Vout VID VID VID VID VID VID Vout 5 4 3 2 1 0 V 5 4 3 2 1 0 V 1 1 1 1 1 1 OFF 0 1 1 1 1 1 0 9125 1 1 1 1 1 0 1 3 0 1 1 1 1 0 0 9 1 1 1 1 0 1 1 2875 0 1 1 1 0 1 0 8875 1 1 1 1 0 0 1 275 0 1 1 1 0 0 0 875 1 1 1 0 1 1 1 2625 0 1 1 0 1 1 0 8625 1 1 1 0 1 0 1 25 0 1 1 0 1 0 0 85 1 1 I 0 0 I 1 2375 0 I 1 0 0 1 0 8375 1 1 1 0 0 0 1 225 0 1 1 0 0 0 0 825 1 1 0 1 1 1 1 2125 0 1 0 1 1 1 0 8125 1 1 0 1 1 0 1 2 0 1 0 1 1 0 0 8 1 1 0 1 0 1 1 1875 0 1 0 1 0 1 0 7875 1 1 0 1 0 0 1 175 0 1 0 1 0 0 0 775 1 1 0 0 1 1 1 1625 0 1 0 0 1 1 0 7625 1 1 0 0 1 0 1 15 0 1 0 0 1 0 0 75 1 1 0 0 0 1 1 1375 0 1 0 0 0 1 0 7375 1 1 0 0 0 0 1 125 0 1 0 0 0 0 0 725 1 0 1 1 1 1 1 1125 0 0 1 1 1 1 0 7125 1 0 1 1 1 0 1 1 0 0 1 1 1 0 0 7 1 0 1 1 0 1 1 0875 0 0 1 1 0 1 0 6875 1 0 L 1 0 0 1 075 0 0 1 1 0 0 0 675 1 0 1 0 1 1 1 0625 0 0 I 0 1 1 0 6625 1 0 1 0 1 0 1 05 0 0 1 0 1 0 0 65 1 0 1 0 0 1 1
27. 9100 Series Datasheet 35 Table 3 1 36 Pinout Specifications Table 3 1 provides the Dual Core Intel Itanium processor 9000 and 9100 series pin list in alphabetical order Table 3 2 provides the Dual Core Intel Itanium processor 9000 and 9100 series list by pin location Pin Signal Information Sorted by Pin Name Sheet 1 of 15 Pin Name Es bie ero ie Input Output Notes 3 3V B02 IN SMBus supply voltage 003 AA03 EXFO V06 IN OUT 004 AA04 EXF1 V02 IN OUT 005 AA05 EXF2 003 IN OUT 006 AA06 EXF3 W03 IN OUT 007 07 Y02 IN OUT A008 AA08 BE0 Y06 IN OUT A009 AA09 BE1 U07 IN OUT A010 AA10 BE2 V04 IN OUT 011 AA11 BE3 05 IN OUT 012 12 4 WO05 IN OUT 013 AA13 BE5 04 IN OUT 014 AA14 BE6 W07 IN OUT A015 AA15 BE7 V08 IN OUT 016 AA16 DIDO U13 IN OUT 017 AA17 DID1 08 IN OUT A018 AA18 DID2 009 IN OUT A019 AA19 DID3 V12 IN OUT 020 AA20 DID4 V10 IN OUT 021 AA21 DID5 09 IN OUT 022 22 0106 13 IN OUT A023 AA23 DID7 11 IN OUT 024 AA24 DID8 Y10 IN OUT 025 25 0109 12 IN OUT A026 AA26 AB26 W11 IN OUT A027 AA27 xTPRValue0 019 IN OUT A028 AA28 xTPRValuel 015 IN OUT A029 AA29 xTPRValue2 V18 IN OUT 030 AA30 xTPRValue3 W19 IN OUT 031 AA31 xTPRDisable V14 IN O
28. D002 D02 C05 IN OUT D003 D03 D04 IN OUT D004 D04 D02 IN OUT D005 D05 D06 IN OUT D006 D06 F06 IN OUT D007 D07 FO2 IN OUT D008 D08 G05 IN OUT D009 D09 H06 IN OUT DO10 D10 E07 IN OUT 011 11 H02 IN OUT D012 D12 H04 IN OUT D013 D13 103 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 37 intel Table 3 1 38 Pin Signal Information Sorted by Pin Name Sheet 3 of 15 Pinout Specifications Pin Name Input Output Notes 0014 014 G03 IN OUT D015 D15 G07 IN OUT 0016 D16 K04 IN OUT D017 D17 103 IN OUT 0018 D18 K06 IN OUT 0019 D19 105 IN OUT 0020 D20 M02 IN OUT 0021 021 107 IN OUT D0223 D22 NO7 IN OUT 0023 023 N03 IN OUT 0024 D24 P04 IN OUT D025 D25 R03 IN OUT D026 D26 P06 IN OUT 0027 D27 02 IN OUT 0028 D28 M06 IN OUT 0029 D29 R05 IN OUT D0304 030 T02 IN OUT D031 D31 R07 IN OUT D032 D32 H10 IN OUT D033 D33 C11 IN OUT D034 D34 D10 IN OUT D035 D35 C09 IN OUT 2036 D36 D12 IN OUT 2037 D37 D08 IN OUT D038 D38 G09 IN OUT D039 D39 E13 IN OUT D040 D40 E09 IN OUT 0041 D41 G11 IN OUT D042 D42 H08 IN OUT D043 D43 G13 IN OUT D044 D44 F12 IN OUT D045 D45 F08 IN OUT D046 D46 H12 IN OUT D047 D47 J13 IN OUT D048 D48 M08 IN OUT D049 D49
29. Datasheet intel The Dual Core Intel Itanium processor 9000 and 9100 series delivers new levels of flexibility reliability performance and cost effective scalability for your most data intensive business and technical applications With double the performance of previous Intel Itanium processors the Dual Core Intel Itanium processor 9000 and 9100 series provides more reasons than ever to migrate your business critical applications off RISC and mainframe systems and onto cost effective Intel architecture servers The Dual Core Intel Itanium processor 9000 and 9100 series provides close to triple the amount of L3 cache 24 megabytes Hyper Threading Technology for increased performance Intel virtualization Technology for improved virtualization Intel Cache Safe Technology for increased availability and 20 percent lower power consumption Dual Core Itanium based systems are available from leading OEMs worldwide and run popular 64 bit operating systems such as Microsoft Windows Server 2003 Linux from SuSE Red Hat Red Flag and other distributions HP NonStop OpenVMS and HP UX More than 7 000 applications are available for Itanium based systems from vendors such as Microsoft BEA I BM Ansys Gaussian Symantec VERITAS Oracle SAP and SAS And with industry support growing and future Intel Itanium processor family advances already in development your Itanium based server investment will continue to deliver performance adva
30. GND GND A20 IN SMWP SMWP A21 IN SMBus signal VCTERM VCTERM A22 IN GND GND A23 IN GND GND A24 IN VCTERM VCTERM A25 IN 3 3V B02 IN SMBus supply voltage GND GND B03 IN N C B04 GND GND B05 IN N C B06 GND GND B07 IN Tuner 3 Tuner 3 B08 IN GND GND B09 IN GND GND B10 IN GND GND B11 IN GND GND B13 IN N C 14 GND GND B15 IN N C B16 50 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 2 of 15 System Bus Pin Pin Name Signal Name Location Input Output Notes GND GND B17 IN SMA0 SMA0 B18 IN SMBus signal GND GND B19 IN N C B20 GND GND B21 IN SMSD SMSD B22 IN OUT SMBus signal GND GND B23 IN SMSC SMSC B24 IN SMBus signal GND GND B25 IN VCTERM VCTERM 01 GND GND C02 IN N C C03 VCTERM VCTERM C04 IN 002 DO2 5 GND GND C06 IN 000 DOO C07 IN OUT VCTERM VCTERM C08 IN 035 D35 C09 IN OUT GND GND C10 IN 033 D33 Cll IN OUT VCTERM VCTERM C12 IN N C C13 GND GND C14 IN N C C15 VCTERM VCTERM C16 IN 073 D73 C17 GND GND C18 IN DO70 D70 19 IN OUT VCTERM VCTERM C20 IN 099 D99 C21 IN OUT GND GND C22 IN 097 97 C23 IN OUT VCTERM C24 IN N C C25 GND GND 001 D004 D04 D02 IN OUT GND GND 003 003 D03 D04 IN OUT G
31. GND GND D23 IN GND GND D25 IN GND GND E04 IN GND GND E08 IN GND GND E12 IN GND GND E16 IN GND GND E20 IN GND GND E24 IN GND GND F01 IN GND GND F03 IN GND GND F05 IN GND GND F07 IN GND GND F09 IN GND GND F11 IN GND GND F13 IN GND GND F15 IN GND GND F17 IN GND GND F19 IN GND GND F21 IN GND GND F23 IN GND GND F25 IN GND GND G02 IN GND GND H03 IN GND GND H05 IN GND GND H07 IN GND GND 09 GND GND H11 IN GND GND H13 IN GND GND H15 IN GND GND H17 IN Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 43 intel Table 3 1 44 Pin Signal Information Sorted by Pin Name Sheet 9 of 15 Pinout Specifications Pin Name 28 ia E Input Output Notes GND GND H19 IN GND GND H21 IN GND GND H23 IN GND GND H25 IN GND GND 01 GND GND 104 GND GND 108 GND GND 12 GND GND 16 GND GND 20 GND GND 124 GND GND GND GND K05 IN GND GND K07 IN GND GND K09 IN GND GND K11 IN GND GND K13 IN GND GND K15 IN GND GND K17 IN GND GND K19 IN GND GND K21 IN GND GND K23 IN GND GND K25 IN GND GND 102 GND GND 01 GND GND M03 IN GND GND M05 IN GND GND M07 IN GND GND M09 IN GND GND M11 IN GND GND M13 IN GND GND M15 IN GND GND M17 IN GND GND M19 IN GND GND M21 IN GND GND M23 IN GND GND M25 IN GND GND N04 IN GND GND N20 IN
32. NC TERM TERM TERM TERM 5 O O O O O O O 5 NC NC GND 105 GND 107 GND A114 GND A127 GND NC GND GND STBNI GND DI GND GND 008 GND STBPO GND DO2 GND GND 6 6 GND RSP IDB ID9 VC DEP2H Des Dest Di8 VC 009 206 DOS GND NC TERM TERM TERM TERM TERM 7 O O O O O O O O O O O O O O O O O O 7 TDO TI FSO GND IDS GNDDRDYO GND 14 GND A09 GND 081 GND De2 GND GND GND 015 GND DIO GND GND THM ALERT 8 GND INT 5814 17 AISHE DEP6 054 Dist VC Dis GND Dte DS GND VC NC GND o o o o o o s TVS TOK FECD GND DBSY GND DSBYO GND A214 GND GND 063 GND GND 053 GND GND 088 GND D40 GND D85 GND VSSVON 10 O O O O GND FECP HT A24 A20 VC DEP7H Det Deo Dee D34 GND GND VCTERM TERM TERM TERM TERM O O O 06000000000 n NC NC GND REGB GND DRDY GND GND GND NC GND 0508 GND STBNG GND DG66 GND DEPS GND D41 GND 5 2 GND 083 GND VOOVON 12 O O O O 12 GND FEO
33. NR C FEE EVER 86 6 6 Thermal Sensing Device Supported SMBUS 5 0 44 87 6 7 Thermal Sensing Device 0 88 6 7 1 Thermal Reference Registers eene 88 6 7 2 Thermal Limit Registers nter rere nr ek dade cia nee e enn 89 6 7 3 Status Registe 89 6 7 4 Configuration Register 22 2 enne 89 6 7 5 Conversion Rate Register 5 eene nnns 90 Signals iic 91 A 1 Alphabetical Signals Reference ene n nne 91 AO AMISTA O des Deme aha aq ee a OR RE 91 A 1 2 GA20M3 a ae cod Pb acd a n RR 91 A3 fO oco etx ur Urt Rer RUE REINO EIU payqasawkussaqaa 91 1 4 AP 1 01 91 AU 5 LO F C O u u usa sasa apana kamu chapana yawqawanaleqa aquqa 91 16 ATTR 3 01 1 O 92 AAT cera 92 8 0 ua akhu wispa aaa akawa aa 92 O aka RE CERE
34. Side 001356 Table 2 19 Power Connector Pinouts Sheet 1 of 2 Power Tab VR Pads Description 1 C1 GND 11 1 GND A2 PPODGD B2 CPUPRES D1 K1 C2 D2 E2 Vfixed H2 N2 Vfixed A3 Vid_valid B3 Vid_core 0 C3 Vid core 1 D3 Vid core 2 E3 Vid core 3 F3 Vid core 4 G3 Vid core 5 H3 Vid cache 0 3 Vid_cache 1 K3 Vid_cache 2 L3 Vid_cache 3 M3 Vid_cache 4 N3 Vid_cache 5 A4 NA GND A5 N5 Vcache A6 N6 GND 7 7 Vcore 8 8 GND A9 9 Vcore 28 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Electrical Specifications Table 2 19 Power Connector Pinouts Sheet 2 of 2 Power Tab VR Pads Description 10 N10 GND 11 N11 Vcore 12 N12 GND A13 N13 Vcore 14 14 GND 15 N15 Vcore A16 N16 GND A17 N17 Vcore A18 N18 GND A19 N19 Vcore A20 N20 GND A21 N21 Vcore A22 N22 GND A23 N23 Vcore A24 N24 GND A25 N25 Vcore A26 N26 GND A27 N27 Vcache A28 N28 GND A29 Vcache sense B29 Gnd sense C29 Vcore sense D29 Vfixed sense K29 GND L29 Reserved M29 Reserved N29 OUTEN A30 D30 GND L30 N30 GND The VR shall provide a selectable output voltage controlled via multiple binary weighted Voltage Identification VID inputs The VID value high 1 low 0
35. Specifications The overshoot undershoot specifications listed in Table 2 13 through Table 2 17 specify the allowable overshoot undershoot for a single overshoot undershoot event However most systems will have multiple overshoot and or undershoot events that each has their own set of parameters duration AF and magnitude While each overshoot on its own may meet the overshoot specification the total impact of all overshoot events may cause the system to fail A guideline to ensure a system passes the overshoot and undershoot specifications is shown below 1 Ensure that no signal ever exceeds or GND 2 If only one overshoot undershoot event magnitude occurs ensure that it meets the specifications listed in Table 2 13 through Table 2 17 3 If multiple overshoots and or multiple undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF 1 specifications If all of these worst case overshoot or undershoot events meet the specifications measured time lt specifications in the table where AF 1 then the system passes Wired OR Signals To ensure platform compatibility between the processors system bus signals must meet certain overshoot and undershoot requirements The system bus wired OR signals BINIT HIT HITM BNR TND BERR have the same absolute overshoot and undershoot specification as the Source Synchronous AGTL Signals but they have different t
36. Supported SMBus Transactions The thermal sensing device responds to five of the SMBus packet types write byte read byte send byte receive byte and alert response address ARA The send byte packet is used for sending one shot commands only The receive byte packet accesses the register commanded by the last read byte packet If a receive byte packet was preceded by a write byte or send byte packet more recently than a read byte packet then the behavior is undefined Table 6 8 through Table 6 12 diagram the five packet types In these tables S represents the SMBus start bit P represents a stop bit Ack represents an acknowledge and represents a negative acknowledge The shaded bits are transmitted by the thermal sensor and the unshaded bits are transmitted by the SMBus host controller Table 6 13 shows the encoding of the command byte Write Byte SMBus Packet S Address Write Ack Command Ack Data Ack P 1 7 bits 1 1 8 bits 1 8 bits 1 1 Read Byte SMBus Packet 5 Address Write Ack Command Ack S Address Read Ack Data 2 P 1 7 bits 0 1 8 bits 1 1 7 bits 1 1 8 bits 1 1 Send Byte SMBus Packet 5 Address Write Ack Command Ack P 1 7 bits 1 1 8 bits 1 Receive Byte SMBus Packet 5 Address Read Ack Data hid P 1 7 bits 1 il 8 bits L 1 ARA SMBus Packe
37. Therefore the thermal sensing device supports six unique resulting addresses To set the Hi Z state for SMA2 the pin must be left floating The system should drive SMA1 and SMAO and will be pulled low if not driven by the 10 pull down resistor on the processor substrate Attempting to drive either of these signals to a Hi Z state would cause ambiguity in the memory device address decode possibly resulting in the devices not responding thus timing out or hanging the SMBus As before the Z bit is the read write bit for the serial bus transaction Figure 6 1 shows a logical diagram of the pin connections Table 6 2 and Table 6 3 describe the address pin connections and how they affect the addressing of the devices Addresses of the form 0000XXXXb are Reserved and should not be generated by an SMBus master Also system management software must be aware of the processor select in the address for the thermal sensing device Thermal Sensing Device SMBus Addressing on the Dual Core Intel Itanium Processor 9000 and 9100 series Address Hex Upper Address Processor Select 8 Bit Address Word on Serial Bus SMA2 5 1 b 7 0 3Xh 0011 0 0 0011000Xb 0011 0 1 0011010Xb 5Xh 0101 72 0 0101001Xb 0101 zb 1 0101011Xb 9Xh 1001 1 0 1001100Xb 1001 1 1 1001110Xb Notes 1 Upper address bits are decoded in conjunction with the select pins 2 tri state or Z state on this is achieved by
38. by direction output input and 1 0 For a complete pinout listing including processor specific pins please refer to Chapter 3 Pinout Specifications Alphabetical Signals Reference A 49 3 1 The Address 49 3 signals with byte enables define 250 Byte physical memory address space When ADS is active these pins transmit the address of a transaction These pins are also used to transmit other transaction related information such as transaction identifiers and external functions in the cycle following ADS assertion These signals must connect the appropriate pins of all agents on the processor system bus A 49 27 signals are parity protected by the AP1 parity signal and the A 26 3 signals are parity protected by the APO parity signal On the active to inactive transition of RESET the processors sample the A 49 3 pins to determine their power on configuration A20M 1 A20M is no connect and is ignored in the processor system environment ADS 1 The Address Strobe ADS signal is asserted to indicate the validity of the transaction address the A 49 3 REQ 5 0 AP 1 0 and RP pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction AP 1 0 1 O The Address Parity AP 1 0 signals can be driven by the request initiator along w
39. core Thermal Design Power 1 6 GHz 75 w single core Notes 1 The range for Vcore is 1 0875 V to 1 25 V 2 Vcache typical is 1 025 V 3 The processor system bus is terminated at each end of the system bus The processor supports both on die and off die termination which is selected by the TERMA and TERMB pins Termination tolerance is 15 for on die termination measured at Vo and 1 for off die termination This is measured for On Die Termination with a 45 ohm pull up resistor Max power is peak electrical power that must be provided for brief periods by the VR Represents the TDP level that should be used for system thermal design Sustained power for all real world applications will remain at or below this power level Sy Dr P Signal Specifications This section describes the DC specifications of the system bus signals The processor signal s DC specifications are defined at the processor pins Table 2 4 through Table 2 9 describe the DC specifications for the AGTL PWRGOOD HSTL clock TAP port system management and LVTTL signals Please refer to the 700 Debug Port Design Guide for the connection signals DC specifications at the debug port Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Electrical Specifications Table 2 4 Table 2 5 Table 2 6 Table 2 7 AGTL Signals DC Specifications Symbol Parameter
40. is usually used to break into hanging or idle processor states Semantics required for platform compatibility are supplied in the PAL firmware interrupt service routine Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 99 ee 1 41 1 42 1 43 Table 9 1 44 1 45 100 INT is the 8259 compatible Interrupt Request signal which indicates that external interrupt has been generated The interrupt is maskable The processor vectors to the interrupt handler after the current instruction execution has been completed An interrupt acknowledge transaction is generated by the processor to obtain the interrupt vector from the interrupt controller The LINT O pin can be software configured to be used either as the INT signal or another local interrupt 1 1 0 1 The ID Parity 1 1 0 signals are driven the second clock of the Deferred Phase by the deferring agent IP0 protects the Da 9 0 and DS signals for the first clock and IP 1 protects the IDb 9 2 01 IDS signals on the second clock LEN 2 0 1 0 The Data Length LEN 2 0 signals are transmitted using REQb 2 0 signals by the requesting agent in the second clock of Request Phase LEN 2 0 defines the length of the data transfer requested by the requesting agent as shown in Table A 9 The LEN 2 0 HITM and RS 2 0 signals together define the length of the actual data transfer
41. on case temperature Case Temperature See Table 5 1 for the case temperature specifications for the Dual Core Intel Itanium processor 9000 and 9100 series The case temperature is defined as the temperature measured at the center of the top surface of the IHS Data may be lost if the case temperature exceeds the specified maximum Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Thermal Specifications Table 5 1 Case Temperature Specification Symbol Parameter Unit Notes Tcase Case Temperature 1 6GHz 24MB 5 76 C 1 6GHz 18MB 5 76 1 6GHz 9MB 5 76 1 42GHz 12MB 5 76 1 4GHz 12MB 5 76 1 6GHz 6MB 5 74 Figure 5 2 contains dimensions for the thermocouple location the processor package This is the recommended location for placement of a thermocouple for case temperature measurement Figure 5 2 Itanium Processor Package Thermocouple Location U 4500 dimensions are measured in mm Not to scale Thermocouple Location 001103a Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 77 78 Thermal Specifications Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet m e System Management Feature Specifications n te D 6 6 1 6 1 1 6 1 2 Table 6 1 System Management Feat
42. pod signal PWRGOOD PWRGOOD AH15 IN REQO REQA0 LENO 09 IN OUT REQ1 WSNP D C LEN1 AF10 IN OUT REQ2 REQA2 REQB2 AD10 IN OUT REQ3 ASZ0 DSZ0 AE11 IN OUT REQ4 ASZ1 DSZ1 AF12 IN OUT REQ5 REQ5 AD12 IN OUT RESET RESET AD20 IN RP RP AC13 IN OUT RSO RSO 07 RS1 RS1 AD08 IN RS2 RS2 AB08 IN RSP RSP AF06 IN SBSY SBSY AE13 IN OUT SBSY0 SBSY_C1 AA13 OUT SBSY1 SBSY_C2 AC19 OUT SMA0 SMA0 B18 IN SMBus signal SMA1 SMA1 17 SMBus signal SMA2 SMA2 15 SMBus signal SMSC SMSC B24 IN SMBus signal SMSD SMSD B22 IN OUT SMBus signal SMWP SMWP A21 IN SMBus signal STBNO STBNO F04 IN OUT STBN1 STBN1 N05 IN OUT STBN2 STBN2 F10 IN OUT Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet intel Pinout Specifications Table 3 1 Pin Signal Information Sorted by Pin Name Sheet 13 of 15 Pin Name Tom Input Output Notes STBN3 STBN3 N11 IN OUT STBN4 STBN4 F16 IN OUT STBN5 STBN5 N17 IN OUT STBN6 STBN6 F22 IN OUT STBN7 STBN7 N23 IN OuT STBPO STBPO E05 IN OUT STBP1 STBP1 M04 IN OUT STBP2 STBP2 Ell IN OUT STBP3 STBP3 M10 IN OUT STBP4 STBP4 E17 IN OUT STBP5 STBP5 M16 IN OUT srBP6 stBP6e STBP7 STBP7 M22 IN OUT TCK TCK AGO9 IN JTAG TDI TDI AGO7 IN JTAG TD
43. qaq 98 1 31 DSZ 1 01 O u u u XA RA REFER ERR R 98 1 32 1 O 98 ALa JO gent Ecc 99 A 1 34 BERR CO eterni eri der 99 A 1 35 D nc ta de aya ama etg x doct dide d eoa RR a 99 A 1 36 HIT 1 0 and HITM 1 0 mmm nmn nnn 99 D 9 013 99 A T 38 DSH icici vein gual enone 99 1 39 E uu uyu hi rk denota o e aca ER edt oae a ca CER PR P 99 PE oM IE AU Em 99 AA d INT CL rex RE DR dia 100 1 42 1 mm Enna ER EF XY Ya RE YR es 100 1 43 LEN 2 0 4 I O 9 E ER FERREA RU i RR I ER 100 1 44 EINTE OI OU m 100 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 1 45 100 E 101 147 EEEE 101 ArT AS PMU Ru 101 1 49 PWRGOOD I i ciorum sua me era Back a 101 1 50 REQI520 14E I O siriana a uiaiia Ya busana pus E Eg pr ER cn Re RR eh 101 WINE RESET rcc 102 1 52 nnna ida enar deep ERR RR a e p D x EAE 102 A 1 53 RS 2 0 3 I iridis rep orientar e Ro
44. regarding individual fields in the product markings will be furnished in a future release of this document 4 2 1 Processor Top Side Marking The top side mark is a laser marking on the IHS Figure 4 7 shows the general location of the processor top side mark that provides the following information Intel 9 e Itanium Processor Family Legal Mark Assembly Process Order APO Number Unit Serial Number 2D Matrix Mark 72 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Mechanical Specifications n tel Figure 4 7 4 2 2 Processor Top Side Marking on IHS PVN MA INA Intel Itanium 2 i 06 Apo NUMBER Processor Bottom Side Marking The processor bottom side mark for the product is a laser marking on the pin side of the interposer Figure 4 8 shows the placement of the laser marking on the pin side of interposer The processor bottom side mark provides the following information Product ID S Spec Finish Process Order FPO 2D Matrix Mark Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 73 intel Mechanical Specifications Figure 4 8 Processor Bottom Side Marking Placement on I nterposer 74 1 S 0000000000000 1 U U amp ee9e9eeee Laser Marking 2D Matrix Mark see notes Dual Core
45. signal is driven during the Deferred Phase by the deferring agent For read transactions on the bus DHIT returns the final cache status that would have been indicated on HIT for a transaction which was not deferred DID 9 0 1 0 01019 0 are Deferred Identifier signals The requesting agent transfers these signals by using A 25 16 They are transferred Ab 25 16 during the second clock of the Request Phase on all transactions but Ab 20 16 is only defined for deferrable transactions DEN asserted DID 9 0 is also transferred on Aa 25 16 during the first clock of the Request Phase for Deferred Reply transactions The Deferred Identifier defines the token supplied by the requesting agent DID 9 and DID 8 5 carry the agent identifiers of the requesting agents always valid and DID 4 0 carry a transaction identifier associated with the request valid only with DEN asserted This configuration limits the bus specification to 32 logical bus agents with each one of the bus agents capable of making up to 32 requests Table A 7 shows the DID encodings DID 9 0 Encoding DID 9 DID 8 5 DID 4 0 Agent Type Agent ID 3 0 Transaction 10 4 0 DID 9 indicates the agent type Symmetric agents use 0 Priority agents use 1 DID 8 5 indicates the agent ID Symmetric agents use their arbitration ID DID 4 0 indicates the transaction ID for an agent The transaction ID must be unique for all deferr
46. the 0 3 mm processor power tab in z direction max under load P Tz Allowable torque on the package tip 0 Package loading in Y direction is not 2 axis allowed Hence zero torque in Z axis Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 71 n tel Mechanical Specifications Table 4 3 Processor Package Load Limits at Power Tab Sheet 2 of 2 Parameter Description Value Comments Tx Allowable torque at the package power 0 57Nm max tab in X axis T y Allowable torque at the package power 1 24 Nm max Torque on the package edge in Y tab in y direction direction is determined by the load applied in Z and the distance from the Allowable torque at the package power edge the package to the socket tab in y direction Torque on the package edge in Y direction is determined by the load applied in Z and the distance from the edge the package to the heatsink 0 93 base determine T y distance from the edge the package to the socket of 55 7mm is applied To determine T y distance from the edge the package to the heatsink pedestal of 42mm is applied Notes 1 Load determination done with 100 16 load on the processor heatsink 4 2 Package Marking The following section details the processor top side and bottom side markings for engineering samples and production units This is provided to aid in identification Specific details
47. to the processor Power for the processor core is supplied through the power tab connector by Vcore Vfixea The 3 3 V is included on the processor to provide power to the system management bus SMBus The 3 3 V and GND pins must remain electrically separated from each other System Bus No Connect pins designated as or No Connect must remain unconnected System Bus Signals Signal Groups Table 2 1 shows processor system bus signals that have been combined into groups by buffer type and whether they are inputs outputs or bidirectional with respect to the processor Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 15 intel Table 2 1 16 Electrical Specifications Itanium Processor System Bus Signal Groups Group Name Signals AGTL Input Signals BPRI BR 3 1 DEFER GSEQ 10 9 0 IDS RESET RS 2 0 RSP TRDY AGTL 1 0 Signals 49 3 ADS AP 1 0 BERR BINIT BNR BPM 5 0 1 BRO D 127 0 DBSY DEP 15 0 DRDY HIT HITM LOCK REQ 5 0 RP SBSY STBN 7 0 STBP 7 0 AGTL Output Signals FERR THRMTRIP DBSY 1 0 DRDY 1 0 SBSY 1 0 Special AGTL Asynchronous A20M IGNNE INIT LINT 1 0 PMI Interrupt Input Signals Power Good Signal PWRGOOD HSTL Clock Signals BCLKn BCLKp TAP Input Signals TCK TDI TMS TRST TAP Output Signals TDO
48. waveform occurs one time in every 200 clock cycles For source synchronous signals data and associated strobes the activity factor is in reference to the strobe edge The highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe So an AF 1 indicates that the specific overshoot or undershoot waveform occurs every other strobe cycle The specifications provided in Table 2 14 through Table 2 17 show the maximum pulse duration allowed for a given overshoot undershoot magnitude at a specific activity factor Each table entry is independent of all others meaning that the pulse duration reflects the existence of overshoot undershoot events of that magnitude ONLY A platform with an overshoot undershoot that just meets the pulse duration for a specific magnitude where the AF lt 1 means that there can be no other overshoot undershoot events even of lesser magnitude if AF 1 then the event occurs at all times and no other events can occur AF for the common clock AGTL signals is referenced to BCLKn and BCLKp frequency The wired OR Signals BINIT HIT HITM BNR TND BERR are common clock AGTL signals AF for source synchronous 2x signals is referenced to STBP 7 0 and STBN 7 0 Reading Overshoot Undershoot Specification Tables The overshoot undershoot specification for the processor is not a simple single value Instead many factors are needed in order to correctly int
49. 0375 0 0 1 0 0 1 0 6375 1 0 1 0 0 0 1 025 0 0 1 0 0 0 0 625 1 0 0 1 1 1 1 0125 0 0 0 1 1 1 0 6125 1 0 0 1 1 0 1 0 0 0 1 1 0 0 6 1 0 0 1 0 1 0 9875 0 0 0 1 0 1 0 5875 1 0 0 1 0 0 0 975 0 0 0 1 0 0 0 575 1 0 0 0 1 1 0 9625 0 0 0 0 1 1 0 5625 1 0 0 0 1 0 0 95 0 0 0 0 1 0 0 55 1 0 0 0 0 1 0 9375 0 0 0 0 0 1 0 5375 1 0 0 0 0 0 0 925 0 0 0 0 0 0 0 525 30 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet m Electrical Specifications tel 2 7 System Bus Clock and Processor Clocking The BCLKn and BCLKp inputs control the operating frequency of the processor system bus interface All processor system bus timing parameters are specified with respect to the falling edge of BCLKn and rising edge of BCLKp The address pins A 21 17 will be used to specify the system bus frequency during reset The processor will ensure that the correct bus core ratio is elected based on the bus frequency that is specified during reset Cold Reset Sequence The configuration pins A 21 17 must be asserted the entire time RESET is asserted e RESET must be asserted before PWRGOOD is asserted The duration from the assertion of PWRGOOD to the deassertion of RESET must be 1 millisecond minimum After RESET is deasserted all the configuration including pins A 21 17 must remain valid for 2 BCLKs minimum to 3 BCLKs maximum BCLK is shown as a time reference to the BCLK period It is not a requirement
50. 06 ns Figure 2 1 4 20 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Electrical Specifications Table 2 10 System Bus Clock Differential HSTL AC Specifications Sheet 2 of 2 intel System Symbol Parameter B Minimum Typ Maximum Unit Figure Notes MHz Trise BCLKp Rise Time All 333 500 667 ps Figure 2 1 20 80 BCLKp Fall Time All 333 500 667 ps Figure 2 1 20 80 Vpp Minimum Input Swing All 600 Figure 2 1 6 Notes 1 The system clock skew is 100 ps 2 Measured on cross point of rising edge of BCLKp and falling edge of BCLKn Long term jitter is defined as peak to peak variation measured by accumulating a large number of clock cycles and recording peak to peak jitter 3 Cycle to cycle jitter is defined as peak to peak variation measured over 10 000 cycles peak to peak jitter 4 Measured on cross point of rising edge of BCLKp and falling edge of BCLKn 5 The system clock skew is 60 ps 6 Vppmin is defined as the minimum input differential voltage which will cause no increase in the clock receiver timing 7 The measurement is taken at 40 60 of the signal and extrapolated to 20 80 Table 2 11 SMBus AC Specifications Symbol Parameter Minimum Maximum Unit Notes fsusc SMSC Clock Frequency 100 kHz Tsmsc SMSC Clock Period 10 us thigh SMSC Clock High Time 4 0 us
51. 2 4 2 1 Processor Top Side 72 4 2 2 Processor Bottom Side 73 5 Thermal Specifications i arriere nece ox akapa lene td ade EESE 75 51 Thermal Features ostro there peer nines 75 5 1 1 Thermal nete telas curi be peras 72 75 5 1 2 Enhanced Thermal Management sss emnes 76 5 1 3 Power 76 5 1 4 nc IUE 76 5 2 Case REFER 76 6 System Management Feature Specifications memes 79 6 1 System Management Bus nennen nain nnne nnn 79 6 1 1 System Management Bus 79 6 1 2 System Management Interface Signals 79 6 1 3 SMBus Device 0 2 mener 81 6 2 Processor Information ROM u saiwa x Ua AF 82 6 3 Scratch EEPROM u ien RM 85 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 3 ntel 6 4 Processor Information ROM and Scratch EEPROM Supported SMBus ENT Tnm 85 6 5 Thermal Sensing Device eee esses seis eaedem LEX ea da
52. 4 IN OUT GND GND V25 IN GND GND wo2 IN A006 AA06 EXF3 w03 IN OUT A012 AA12 BE4 W05 IN OUT A014 AA14 BE6 W07 IN OUT A021 AA21 DID5 09 026 AA26 AB26 W11 IN OUT A022 AA22 DID6 W13 IN OUT A037 AA37 AB37 W15 IN OUT A032 AA32 ATTR0 W17 IN OUT A030 AA30 xTPRValue3 W19 IN OUT 044 AA44 AB44 W21 IN OUT A046 AA46 AB46 W23 IN OUT A041 AA41 AB41 W25 IN OUT Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 59 intel Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 11 of 15 Pin Name ee Tu m Input Output Notes GND GND 01 007 AAO7 EXF4 02 IN OUT GND GND YO3 IN 013 AA13 BE5 04 IN OUT GND GND YO5 IN 008 AA08 BEO 06 IN OUT GND GND YO7 IN 017 AA17 DID1 08 IN OUT GND GND YOO IN 024 AA24 DID8 Y10 IN OUT GND GND 11 025 AA25 DID9 Y12 IN OUT GND GND Y13 IN A034 AA34 ATTR2 Y14 IN OUT GND GND 15 036 AA36 AB36 16 IN OUT GND GND Y17 IN A035 AA35 ATTR3 Y18 IN OUT GND GND 19 039 AA39 AB39 Y20 IN OUT GND GND Y21 IN A049 AA49 AB49 Y22 IN OUT GND GND Y23 IN A043 AA43 AB43 Y24 IN OUT GND GND Y25 IN GND GND 02 103 IDA3 IDB3 AA03 IN A011 AA11 BE3 AA05 IN OUT DRDYO DRDY C1 AA07 O
53. 7 1 18 1 19 1 20 1 21 1 22 1 23 96 symmetric agent deassert BREQn before it becomes symmetric owner symmetric agent can reassert BREQn after keeping it deasserted for one clock CCL 1 0 CCL is the Cache Cleanse signal It is driven on the second clock of the Request Phase on the EXF 2 Ab 5 pin CCL is asserted for Memory Write transaction to indicate that a modified line in a processor may be written to memory without being invalidated in its caches CPUPRES CPUPRES can be used to detect the presence of a processor in a socket A ground indicates that a processor is installed while an open indicates that a processor is not installed D 127 0 1 0 The Data D 127 0 signals provide a 128 bit data path between various system bus agents Partial transfers require one data transfer clock with valid data on the byte s indicated by asserted byte enables BE 7 0 and A 3 Data signals that are not valid for a particular transfer must still have correct ECC if data bus error checking is enabled The data driver asserts DRDY to indicate a valid data transfer D C 1 0 The Data Code D C signal is used to indicate data 1 or code 0 on REQa 1 only during Memory Read transactions DBSY 1 0 The Data Bus Busy DBSY signal is asserted by the agent that is responsible for driving data on the system bus to indicate that the data bus is in use Th
54. 8 IN OUT DEP11 DEP11 T16 IN OUT DEP12 DEP12 21 IN OUT DEP13 DEP13 23 IN OUT 40 Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 1 Signal Information Sorted by Pin Name Sheet 6 of 15 Pin Name Tas Input Output Notes DEP14 DEP14 T20 DEP15 DEP15 T22 IN OUT DRDY DRDY 11 IN OUT DRDYO DRDY_C1 07 OUT DRDY1 DRDY_C2 AA21 OUT FERR FERR AH25 OUT GND GND 01 GND GND A03 IN GND GND A05 IN GND GND A08 IN GND GND A13 IN GND GND A16 IN GND GND A19 IN GND GND A20 IN GND GND A23 IN GND GND A24 IN GND GND AA02 IN GND GND AA20 IN GND GND AA24 IN GND GND 01 GND GND ABO3 IN GND GND ABO5 IN GND GND ABO7 IN GND GND 09 GND GND AB11 IN GND GND AB13 IN GND GND AB15 IN GND GND AB17 IN GND GND AB19 IN GND GND AB21 IN GND GND AB23 IN GND GND AB25 IN GND GND 2 GND GND AC24 IN GND GND ADO1 IN GND GND AD03 IN GND GND AD05 IN GND GND AD07 IN GND GND AD09 IN GND GND AD11 IN GND GND AD13 IN GND GND AD15 IN GND GND AD17 IN GND GND AD19 IN Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 41 intel Table 3 1 42 Pin Signal Information Sorted by Pin Name Sheet 7 of 15 Pinout Specifications
55. AD02 IN GND GND AD03 IN ID4 IDA4 IDB4 AD04 IN GND GND AD05 IN ID8 IDA8 IDB8 AD06 IN GND GND AD07 IN RS1 RS1 AD08 IN GND GND AD09 IN Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 61 m e n tel Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 13 of 15 Pin Name 0 Ta m Input Output Notes REQ2 REQA2 REQB2 AD10 IN OUT GND GND AD11 IN 5 5 AD12 IN OUT GND GND AD13 IN GSEQ GSEQ AD14 IN GND GND AD15 IN BR1 BREQ1 AD16 IN GND GND AD17 IN N C AD18 GND GND AD19 IN RESET RESET AD20 IN GND GND AD21 IN BPMO BPMO AD22 IN OUT GND GND AD23 IN BPM4 BPM4 AD24 IN OUT GND GND AD25 IN GND GND AE02 IN TERMB FSBT2 AE03 106 IDA6 IDB6 AE05 IN RS0 RS0 AE07 IN REQ0 REQA0 LEN0 AE09 IN OUT REQ3 ASZ0 DSZ0 AE11 IN OUT SBSY SBSY AE13 IN OUT LOCK LOCK AE15 N C N C AE17 BPRI BPRI AE19 IN TRST TRST AE21 IN BPM2 BPM2 AE23 IN OUT GND GND AE24 IN PMI PMI 25 GND GND 01 TERM FSBT AF02 IN OUTEN OUTEN AF04 IN Power pod signal GND GND AF05 IN RSP RSP AF06 IN GND GND AF07 IN INIT INIT AF08 IN GND GND AF09 IN REQ1 WSNP D C LEN1 AF10 IN OUT GND GND AF11 IN REQ4 ASZ1 DSZ1 AF12 IN OUT GND GND AF13 IN TRDY TRDY AF14 IN GND GND AF15 IN
56. AX Ry 4 2 4 3 045 1 Ro 1 87 2 13 21 40 25 45 745 BASIC To 24 BASIC um 2 405 BASIC 22 BASIC Wi 24 405 BASIC We 22 BASIC 68 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet intel Imensions Processor Package Mechanical I nterface D 69 q 117130 1101 xe AS O0 oC ADDE ROCIO IID 2892000000000 29009990090 to pP Yr Y ae a e e A Y 59900000009 LIRA RKA 60 4 7 5 50 5495900000005 000000009 OOO 2000000007 428829191790 2220000020 2000 2232600002002909 2200000000 Vy A 5 2350 0000 0 OOG yg xz ixl Mechanical Specifications Figure 4 3 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet m tel Mechanical Specifications Figure 4 4 Processor Package Top Side Components Height Dimensions CONPONENT KEEPOUT CROSS HATCHED AREA 3 MAX ALLOWABLE COMPONENT HEIGHT 2X 9 5 2X 14 15 x 5522 OX 000000 DOO XO OI ODO 5 2 3 MAX ALLOWABLE COMPONENT HEIGHT TOP VIEW Note Keepout zones indicate no components will be the processor package Figure 4 5 Processor Package Bottom Side Components Height Dimensions OMPONENT KEEPOUT C
57. Core Intel Itanium processor 9000 and 9100 series signals and pinout standard pin naming convention The pins labeled N C must remain unconnected The processor uses a JEDEC In this chapter pin names are the actual names given to each physical pin of the processor System bus signal names are the names associated with the functions of those pins For those pins associated with multiple functions their pin names and system bus signal names are not necessarily identical Figure 3 1 shows the processor pin location diagram from the top view Figure 3 1 Dual Core Intel Itanium Processor 9000 and 9100 Series Pinout AH AG AF AD Y W V U T R P N M L K J H G F E D C B A 1 O 1 GND GND GND GND GND GND GND VC G D GND GND GD GND GND TERM TERM TERM TERM 2 O O O O O O O O O O O O O O 2 GND TERVA GND 100 GND IDI GND A07 GND A044 VC DG0f GND VC GND NC VC GND VC GND 33V VW TERM TERM TERM TERM TERM O oe O 8 TUNER TUERA TERVB GND 0 GND IDG GND A06 GND 5 GND 5 GND GND DI7 GND GND Di4 GND GND NC GND GD 4 4 GND ID4 ID5 1 GND De4 GND STBPI Diet GND Di2 VC SIBNO GND VC NC
58. D097 D97 C23 IN OUT D098 D98 D22 IN OUT D099 D99 C21 IN OUT D100 D100 E25 IN OUT D101 D101 G21 IN OUT Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 39 intel Table 3 1 Pin Signal Information Sorted by Pin Name Sheet 5 of 15 Pinout Specifications Pin Name bius I nput Output Notes D102 D102 D20 IN OUT D103 D103 F24 IN OUT D104 D104 D24 IN OUT D105 D105 H22 IN OUT D106 D106 F20 IN OUT D107 D107 G25 IN OUT D108 D108 G23 IN OUT D109 D109 H24 IN OUT D110 D110 25 IN OUT 0111 0111 20 IN OUT D112 D112 L21 IN OUT D113 D113 L25 IN OUT 0114 0114 K22 IN OUT D115 D115 M24 IN OUT D116 D116 L23 IN OUT D117 D117 K20 IN OUT D118 D118 M20 IN OUT D119 D119 N25 IN OUT D120 D120 P24 IN OUT D121 D121 R25 IN OUT D122 D122 P20 IN OUT D123 D123 T24 IN OUT D124 D124 R21 IN OUT D125 D125 P22 IN OUT D126 D126 R23 IN OUT D127 D127 N21 IN OUT DBSY DBSY 09 IN OUT DBSYO DBSY C1 09 OUT DBSY1 DBSY_C2 19 OUT DEFER DEFER AB14 IN DEPOO DEPO 07 IN OUT DEPO1 DEP1 105 IN OUT DEPO2 DEP2 06 IN OUT DEPO3 DEP3 T04 IN OUT DEP04 DEP4 J09 IN OUT DEP05 DEP5 11 IN OUT DEPO6 DEP6 T08 IN OUT DEPO7 DEP7 T10 IN OUT DEPO8 DEP8 19 IN OUT 9 9 17 IN OUT DEP10 DEP10 1
59. DEP8 GND D 9 GND D 4 GND 070 GND GD O O O O O O O O O O O GND FFCD FESET ADS AS39 Ad5 GND DEP14 D122 GND D118 VC 0117 GND 0111 VC 0106 GND D1024 VC NC GND GDH TERM O O O O O O O O O O O a NC NC GND TRST GND GNDDRDY1I GND A44 GND Ad48 GND Di244 GND D127 GND 0112 GND DEP12 GND 0101 GND 096 GND D99 GND 2 O O gt GND UNTO AAOH DEPIS 21254 STEP7 114 VC DI05 STBNS Dss GND SVED VC TERM TERM TERM O O O O O O O O O O O O O O AZ0M IGNNE GND GND 1 GND Ad6 GND GND 0126 GND SIBN7 GND D116 GND DEP13 GND DI08 GND STBP6 GND D97 GND GND 24 O O O O O O O O O O O O O O A GND UNTI GND GND GND A43 AdO GND D1234 1208 GND 0115 VC GND D1094 VC 0103 GND Di04 VC SVSC GND TERM TERM TERM TERM 20000 O O O O O O O O O O O 0 gt Z GND GND GND GND GND DI21 GND 0119 GND 0113 GND 0110 GND 0107 GND 21008 GND NC GND TERM TERM AG AF AD Y W U T R P N M L K J H G F E D C B 44 Power Pod 000638b Dual Core Intel Itanium Processor 9000 and
60. During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wired OR signal In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is asserted and sampled on specific clock edges BPM 5 0 1 The BPM 5 0 signals are system support signals used for inserting breakpoints and for performance monitoring They can be configured as outputs from the processor that indicate programmable counters used for monitoring performance or inputs from the processor to indicate the status of breakpoints BPRI 1 The Bus Priority agent Request signal is used by the priority agent to arbitrate for ownership of the system bus Observing BPRI asserted causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI 1 and BR 3 1 1 BR 3 0 are the physical bus request pins that drive the BREQ 3 0 signals the system The BREQ 3 0 signals are interconnected in a rotating manner to individual processor pins Table A 4 and Table A 4 give the rotating interconnection between the processor and bus signals for both the 4P and 2P system bus topologies Dual Core Intel tanium Pr
61. GND GND P19 IN 0122 0122 20 GND GND P21 IN D125 D125 P22 IN OUT GND GND P23 IN D120 D120 P24 GND GND P25 IN VCTERM VCTERM RO1 IN GND GND RO2 IN 025 025 R03 IN OUT VCTERM VCTERM R04 IN D029 D29 RO5 IN OUT 0031 D31 RO7 IN OUT VCTERM VCTERM R08 IN D063 D63 ROO IN OUT 060 D60 R11 VCTERM VCTERM R12 IN 059 D59 R13 IN OUT 092 D92 R15 IN OUT VCTERM VCTERM R16 IN 089 D89 R17 IN OUT 090 D90 R19 IN OUT VCTERM VCTERM R20 IN Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 57 intel Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 9 of 15 Pin Name ee To m Input Output Notes 0124 0124 R21 IN OUT D126 D126 R23 IN OUT VCTERM VCTERM R24 IN D121 D121 R25 IN OUT GND GND TO1 IN 0030 030 TO2 IN OUT GND GND TO3 IN DEPO3 DEP3 T04 IN OUT GND GND T05 IN DEPO2 DEP2 06 IN OUT GND GND TO7 IN DEPO6 DEP6 TO8 IN OUT GND GND TO9 IN DEPO7 DEP7 T10 IN OUT GND GND T11 IN D062 D62 T12 IN OUT GND GND T13 IN D094 D94 T14 IN OUT GND GND T15 IN DEP11 DEP11 T16 IN OUT GND GND T17 IN DEP10 DEP10 T18 IN OUT GND GND T19 IN DEP14 DEP14 T20 IN OUT GND GND T21 IN DEP15 DEP15 T22 IN OUT GND GND T23 IN D123 D123 T24 IN OUT GND GND T25 IN VCTERM VCTERM 002
62. IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Dual Core Intel Itanium 9000 and 9100 series processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling1 800 548 4725 or by visiting Intel s website at http www intel com Intel Itanium and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Copyrigh
63. Intel Itanium Processor 9000 and 9100 Series Datasheet m Thermal Specifications n tel 5 5 1 Note Figure 5 1 5 1 1 Thermal Specifications This chapter provides a description of the thermal features relating to the Dual Core Intel Itanium processor 9000 and 9100 series Thermal Features The processor has an internal thermal circuit which senses when a certain temperature is reached on the processor core This circuit is used for controlling various thermal states In addition an on chip thermal diode is available for use by the thermal sensing device on the processor Figure 5 1 shows the relationship between temperature time and the thermal alert enhanced thermal management ETM and thermal trip points Figure 5 1 is not intended to show a linear relationship in time or temperature as a processor s thermal state advances from one state to the next state when the cooling solution fails to control the processor temperature as this is affected by many factors such as cooling solution performance degradation and processor workload variations Dual Core Intel Itanium Processor 9000 and 9100 Series Thermal Features Thermal Trip Thermal Alert Temperature Time 000653b Thermal Alert THRMALERT is a programmable thermal alert signal which is part of the processor system management feature THRMALERT is asserted when the measured temperature from the processor thermal diode equa
64. K04 IN OUT GND GND 5 0018 018 K06 IN OUT GND GND K07 IN 049 D49 K08 IN OUT GND GND K09 IN DO50 D50 K10 IN OUT GND GND K11 IN N C K12 GND GND K13 IN N C K14 GND GND K15 IN D083 D83 K16 IN OUT GND GND K17 IN D080 D80 K18 IN OUT GND GND K19 IN D117 D117 K20 IN OUT GND GND K21 IN D114 D114 K22 IN OUT GND GND K23 IN N C K24 GND GND K25 IN VCTERM VCTERM 101 GND GND 102 0017 017 103 IN OUT VCTERM VCTERM 104 019 D19 105 IN OUT 021 021 107 VCTERM 108 D053s 053 109 056 D56 L11 IN OUT VCTERM VCTERM L12 IN 052 052 113 0081 081 115 VCTERM L16 IN DO88 088 117 IN OUT 0082 082 119 IN OUT VCTERM VCTERM L20 IN 0112 0112 121 0116 D116 L23 IN OUT VCTERM VCTERM L24 IN Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 55 m e n tel Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 7 of 15 Pin Name 1 Tu m Input Output Notes D113 D113 L25 IN OUT GND GND 01 D020 D20 M02 IN OUT GND GND M03 IN STBP1 STBP1 M04 IN OUT GND GND M05 IN D028 D28 06 IN OUT GND GND M07 IN D048 D48 M08 IN OUT GND GND M09 IN STBP3 STBP3 M10 IN OUT GND GND M11 IN 0051 D51
65. K08 IN OUT DO50 D50 K10 IN OUT 0051 D51 M12 IN OUT 0052 D52 L13 IN OUT 0053 053 109 IN OUT 0054 054 P08 IN OUT 2055 D55 N13 IN OUT DO56 D56 L11 IN OUT DO57 D57 P12 IN OUT Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 1 Signal Information Sorted by Pin Name Sheet 4 of 15 Pin Name Input Output Notes DO58 D58 09 059 D59 R13 IN OUT DO60 D60 R11 IN OUT 0061 D61 P10 IN OUT D062 D62 T12 IN OUT D063 D63 R09 IN OUT D064 D64 D18 IN OUT D065 D65 D14 IN OUT 066 D66 D16 IN OUT D067 D67 E15 IN OUT 2068 D68 F14 IN OUT D069 D69 F18 IN OUT D070 D70 C19 IN OUT D071 D71 G15 IN OUT D072 D72 G17 IN OUT D073 D73 C17 IN OUT D074 D74 E19 IN OUT DO75 D75 H14 IN OUT DO76 D76 H16 IN OUT DO77 D77 H18 IN OUT DO78 D78 15 DO79 D79 G19 IN OUT DO80 D80 K18 IN OUT 0081 081 115 0082 082 119 083 D83 K16 084 D84 M14 IN OUT D085 D85 N19 IN OUT D086 D86 M18 IN OUT D087 D87 P14 IN OUT D088 D88 L17 IN OUT D089 D89 R17 IN OUT D090 D90 R19 IN OUT D091 D91 N15 IN OUT D092 D92 R15 IN OUT D093 D93 P16 IN OUT D094 D94 T14 IN OUT D095 D95 P18 IN OUT D096 D96 E21 IN OUT
66. Length of Data Transfers LEN 2 0 Length 000 0 8 bytes 001 16 bytes 010 32 bytes 011 64 bytes 100 128 bytes 101 Reserved 110 Reserved 111 Reserved LINT 1 0 1 LINT 1 0 are local interrupt signals These pins are disabled after RESET LINT O is typically software configured as INT an 8259 compatible maskable interrupt request signal LINT 1 is typically software configured as NMI a non maskable interrupt Both signals are asynchronous inputs LOCK 1 O LOCK is no connect and is ignored in the processor system environment Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet intel A 1 46 A 1 47 A 1 48 A 1 49 A 1 50 NMI 1 The NMI signal is the Non maskable Interrupt signal Asserting NMI causes an interrupt with an internally supplied vector value of 2 An external interrupt acknowledge transaction is not generated If NMI is asserted during the execution of an NMI service routine it remains pending and is recognized after the EOI is executed by the NMI service routine At most one assertion of NMI is held pending NMI is rising edge sensitive Recognition of NMI is guaranteed in a specific clock if it is asserted synchronously and meets the setup and hold times If asserted asynchronously asserted and deasserted pulse widths of NMI must be a minimum of two clocks This signal must be software configured to be used either as NMI as anoth
67. M12 IN OUT GND GND M13 IN D084 D84 M14 IN OUT GND GND M15 IN STBP5 STBP5 M16 IN OUT GND GND M17 IN D0863 086 18 IN OUT GND GND M19 IN D118 D118 M20 IN OUT GND GND M21 IN STBP7 STBP7 M22 IN OUT GND GND M23 IN D115 D115 M24 IN OUT GND GND M25 IN VCTERM VCTERM 2 0023 023 N03 IN OUT GND GND N04 IN STBN1 STBN1 N05 IN OUT VCTERM VCTERM N06 IN 0022 D22 NO7 IN OUT 0058 058 09 IN OUT VCTERM VCTERM N10 IN STBN3 STBN3 11 IN OUT 0055 D55 N13 IN OUT VCTERM VCTERM N14 IN 0091 D91 N15 IN OUT STBN5 STBN5 N17 IN OUT VCTERM VCTERM N18 IN 085 D85 N19 IN OUT GND GND N20 IN D127 D127 N21 IN OUT VCTERM VCTERM N22 IN 56 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 2 Signal Information Sorted by Pin Location Sheet 8 of 15 Pin Name E Pan oc Input Output Notes STBN7 STBN7 N23 IN OuT GND GND N24 IN 0119 0119 25 IN OUT GND GND P01 IN 0027 027 02 IN OUT GND GND 0024 024 P04 IN OUT GND GND P05 IN D026 D26 P06 IN OUT GND GND P07 IN 0054 054 GND GND P09 IN 0061 061 10 GND GND 11 057 D57 P12 IN OUT GND GND P13 IN 087 D87 P14 IN OUT GND GND P15 IN 0093 093 16 IN OUT GND GND P17 IN 095 D95 P18 IN OUT
68. MB L3 Cache 9150N Dual Core Intel Itanium Processor 1 66 GHz with 18 MB L3 Cache 9140M Dual Core Intel Itanium Processor 1 6 GHz with 18 L3 Cache 9140N Dual Core Intel Itanium Processor 1 42 GHz with 12 MB L3 Cache 9120N Dual Core I ntel Itanium Processor 1 66 GHz with 8 MB L3 Cache 9130 Intel I tanium Processor 1 6 GHz with 12 MB 13 Cache 9110N Product Features m Dual Core Intel Virtualization Technology for virtualization for Two complete 64 bit processing cores on one data intensive applications processor Reduces virtualization complexity m EPIC Explicitly Parallel Instruction Computing Improves virtualization performance m Technology for current and future requirements of Increases operating system compatibility high end enterprise and technical workloads Intel Cache Safe Technology ensures mainframe Provide a variety of advanced caliber availability implementations of parallelism predication Minimize L3 cache errors and speculation resulting in superior Instruction Level Parallelism I LP m Outstanding Energy Efficiency 20 percent less power than previous Intel Hyper Threading Technology Itanium processor Two times the number of OS threads per core 2 5 times higher performance per watt provided by earlier single thread implementations High bandwidth system bus for multiprocessor scalability Wide parallel hardware based on Intel Itaniu
69. ND GND D05 IN D005 DO5 D06 IN OUT GND GND D07 IN 037 037 008 IN OUT GND GND 009 D034s 034 010 IN OUT Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 51 intel Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet of 15 Pin Name ee Tu m Input Output Notes GND GND D11 IN D036 D36 D12 IN OUT GND GND D13 IN 065 D65 014 IN OUT GND GND D15 IN 2066 D66 D16 IN OUT GND GND D17 IN 064 D64 018 IN OUT GND GND D19 IN D102 D102 D20 IN OUT GND GND D21 IN D098 D98 D22 IN OUT GND GND D23 IN D104 D104 D24 IN OUT GND GND D25 IN VCTERM VCTERM E02 IN D001 D01 E03 IN OUT GND GND E04 IN STBP0 STBP0 05 IN OUT VCTERM VCTERM E06 IN DO10 D10 E07 IN OUT GND GND E08 IN 0040 D40 E09 IN OUT VCTERM VCTERM E10 IN STBP2 STBP2 Ell IN OUT GND GND E12 IN D039 D39 E13 IN OUT VCTERM VCTERM E14 IN 067 D67 E15 IN OUT GND GND E16 IN STBP4 STBP4 E17 IN OUT VCTERM VCTERM E18 IN DO74 074 19 IN OUT GND GND E20 IN DO96 96 21 IN OUT VCTERM VCTERM E22 IN STBP6 STBP6 E23 IN OUT GND GND E24 IN D100 D100 E25 IN OUT GND GND 01 007 DO7 FO2 IN OUT GND GND F03 IN STBNO STBNO F04 IN OUT GND GND F05 IN 52 Dual Core Intel Itanium Processor 9000 and 9100 Series Data
70. O TDO AHO7 OUT JTAG TERMA FSBT1 AF02 IN TERMB FSBT2 AE03 IN THRMTRIP THRMTRIP AG25 OUT THRMALERT THRMALERT A07 OUT TMS TMS AH09 IN JTAG TND TND AC15 IN OUT TRDY TRDY AF14 IN TRST TRST AE21 IN JTAG TUNER 1 TUNER 1 AH03 IN TUNER 2 TUNER 2 AG03 IN TUNER 3 TUNER 3 B08 IN VCCMON VCCMON A11 N C VCTERM VCTERM A02 IN VCTERM VCTERM A06 IN VCTERM VCTERM A10 IN VCTERM VCTERM A14 IN VCTERM VCTERM A18 IN VCTERM VCTERM A22 IN VCTERM VCTERM A25 IN VCTERM VCTERM C01 IN VCTERM VCTERM C04 IN VCTERM VCTERM C08 IN VCTERM VCTERM C12 IN VCTERM VCTERM C16 IN VCTERM VCTERM C20 IN vCTEERM c IN VCTERM VCTERM E02 IN VCTERM VCTERM E06 IN 48 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 1 Pin Signal Information Sorted by Pin Name Sheet 14 of 15 Pin Name E Pan Tham Input Output Notes VCTERM VCTERM E10 IN VCTERM VCTERM E14 IN VCTERM VCTERM E18 IN VCTERM VCTERM E22 IN VCTERM VCTERM G01 IN VCTERM VCTERM G04 IN VCTERM VCTERM G08 IN VCTERM VCTERM G12 IN VCTERM VCTERM G16 IN VCTERM VCTERM G20 IN VCTERM VCTERM G24 IN VCTERM VCTERM J02 IN VCTERM VCTERM 106 VCTERM 10 VCTERM VCTERM 14 VCTERM 18 VCTERM 22 VCTERM 101 VCTERM VCTERM 104
71. ROSS HATCHED AREA A INST Se mm cm Z eee ee 17 hoz p 3 ALLOWABLE IN CROSS HATCHED AREA COMPONENT HEIGHT BOTTOM VIEW Note Keepout zones indicate no components will be on the processor package 70 Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet Mechanical Specifications n tel 4 1 1 Figure 4 6 Table 4 3 Voltage Regulator MVR to Processor Package I nterface Critical package mechanical requirements at its interface with the MVR are identified in Figure 4 6 and Table 4 3 The processor interface boundary conditions with which MVR must comply during and after installation are outlined in Table 4 3 These requirements are intended to minimize potential damage to the processor that may result from installation of the MVR Processor to MVR Interface Loads Processor Heatsink N Processor Heatsink Substrate Mother Board Processor Package Load Limits at Power Tab Sheet 1 of 2 Parameter Description Value Comments A Final position of the package at the 3 8 Position of the processor power tab is power tab unloaded with respect to 0 1mm based on the height of the mPGA700 system board ZIF socket height from the mother post SMT P Allowable load on the package in 7 22 25N max and z direction d Allowable displacement at
72. Table 2 16 Source Synchronous AGTL Signal Group Time Dependent Overshoot Undershoot Tolerance for 533 MHz System Bus Sheet 1 of 2 Absolute Maximum V Pulse Duration ns pier 11 0 75 AF 0 5 AF 2 0 25 0 1 0 05 0 01 1 65 0 45 0 0026 0 0027 0 0028 0 0030 0 0091 0 0181 0 0902 1 6 0 4 0 0029 0 0030 0 0034 0 0118 0 0297 0 0600 0 2989 1 55 0 35 0 0093 0 0126 0 0191 0 0387 0 0980 0 1963 0 9822 1 5 0 3 0 0303 0 0409 0 0625 0 1268 0 3178 0 6406 1 875 145 025 0 3095 0 4191 0 6366 1 2965 1875 1875 1875 26 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet m Electrical Specifications tel Table 2 16 Table 2 17 2 6 Table 2 18 Warning Source Synchronous AGTL Signal Group Time Dependent Overshoot Undershoot Tolerance for 533 MHz System Bus Sheet 2 of 2 Ma n Pulse Duration ns 1 4 0 2 0 9925 1 3358 1 875 1 875 1 875 1 875 1 875 1 35 0 15 1 875 1 875 1 875 1 875 1 875 1 875 1 875 1 3 0 10 1 875 1 875 1 875 1 875 1 875 1 875 1 875 Notes 1 Activity Factor 1 means signal toggles every 3 75 ns Wired OR Signal Group BINIT HIT HITM BNR TND BERR Overshoot Undershoot Tolerance for 533 MHz System Bus Pulse Duration ns B 11 AF 0 75
73. UT A032 AA32 ATTRO W17 IN OUT A033 AA33 ATTR1 AA17 IN OUT A034 AA34 ATTR2 Y14 IN OUT A035 AA35 ATTR3 Y18 IN OUT A036 AA36 AB36 Y16 IN OUT A037 AA37 AB37 W15 IN OUT 038 AA38 AB38 V16 IN OUT 039 AA39 AB39 Y20 IN OUT A040 AA40 AB40 V24 IN OUT Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 1 Pin Signal Information Sorted by Pin Name Sheet 2 of 15 Pin Name E RAE Tam Input Output Notes 041 AA41 AB41 W25 IN OUT 042 42 42 023 043 AA43 AB43 Y24 IN OUT A044 AA44 AB44 W21 IN OUT A045 AA45 AB45 V20 IN OUT A046 AA46 AB46 W23 IN OUT A047 AA47 AB47 22 048 48 48 021 049 AA49 AB49 Y22 IN OUT A20M A20M AH23 N C ADS ADS AB20 IN OUT AP0 AP0 AA25 IN OUT AP1 AP1 AA23 IN OUT BCLKn BCLKN AH13 IN BCLKp BCLK AG13 IN BERR BERR AB22 IN OUT BINIT BINIT AA15 IN OUT BNR BNR U17 IN OUT BPM0 BPM0 AD22 IN OUT BPM1 BPM1 AC25 IN OUT BPM2 BPM2 AE23 BPM3 BPM3 AC23 IN OUT BPM4 BPM4 AD24 IN OUT BPM5 BPM5 AB24 IN OUT BPRI BPRI 19 BRO BREQO AF16 IN OUT BR1 BREQ1 AD16 IN BR2 BREQ2 AB18 IN BR3 BREQ3 AF18 IN CPUPRES CPUPRES AG15 OUT Power pod signal D000 D00 C07 IN OUT D001 D01 E03 IN OUT
74. UT DBSYO DBSY C1 09 OUT A023 AA23 DID7 11 IN OUT SBSYO SBSY C1 AA13 OUT BINIT BINIT AA15 IN OUT A033 AA33 ATTR1 AA17 IN OUT DBSY1 DBSY_C2 19 OUT GND GND AA20 IN DRDY1 DRDY_C2 AA21 OUT AP1 AP1 AA23 IN OUT GND GND AA24 IN APO APO AA25 IN OUT GND GND ABO1 IN ID1 IDA1 IP1 2 GND GND ID5 IDA5 IDB5 04 60 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 12 of 15 intel Pin Name 2 Input Output Notes GND GND ABO5 IN 109 IDA9 IDB9 AB06 IN GND GND AB07 IN RS2 RS2 AB08 IN GND GND AB09 IN HIT HIT AB10 IN OUT GND GND AB11 IN HITM HITM AB12 IN OUT GND GND AB13 IN DEFER DEFER AB14 IN GND GND AB15 IN N C AB16 GND GND AB17 IN BR2 BREQ2 AB18 IN GND GND AB19 IN ADS ADS AB20 IN OUT GND GND AB21 IN BERR BERR AB22 IN OUT GND GND AB23 IN BPM5 BPM5 AB24 IN OUT GND GND AB25 IN GND GND AC02 IN ID2 IDA2 DHIT AC03 IN ID7 IDA7 IDB7 AC05 IN IDS IDS AC07 IN DBSY DBSY AC09 IN OUT DRDY DRDY AC11 IN OUT RP RP AC13 IN OUT TND TND 15 17 SBSY1 SBSY_C2 19 OUT N C AC21 BPM3 BPM3 AC23 IN OUT GND GND AC24 IN BPM1 BPM1 AC25 IN OUT GND GND AD01 IN ID0 IDA0 IP0
75. able transactions issued by an agent which have not reported their snoop results The Deferred Reply agent transmits the DID 9 0 Ab 25 16 signals received during the original transaction on the Aa 25 16 signals during the Deferred Reply transaction This process enables the original requesting agent to make an identifier match with the original request that is awaiting completion Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 97 intel A 1 27 A 1 28 A 1 29 A 1 30 A 1 31 A 1 32 Table A 8 98 DPS 1 O The Deferred Phase Enable DPS signal is driven to the bus on the second clock of the Request Phase on the Ab 3 DPS is asserted if a requesting agent supports transaction completion using the Deferred Phase A requesting agent that supports the Deferred Phase will always assert DPS A requesting agent that does not support the Deferred Phase will always deassert DPS DRDY I O The Data Ready DRDY signal is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi cycle data transfer DRDY can be deasserted to insert idle clocks DRDY is replicated three times to enable partitioning of data paths in the system agents This copy of the Data Ready signal DRDY is an input as well as an output DRDY_C1 O DRDY is a copy of the Data Ready signal This copy of the Data Phase data ready signal DRDY_C1 is an output on
76. and TERMB pins are terminated as indicated above The TUNER3 pin will not be required for the majority of platforms supporting the Dual Core Intel Itanium processor 9000 and 9100 series The TUNER3 pin is used only in the case where A 21 17 are driven to all zeros or all ones during the configuration cycles at reset When all zeros or all ones are observed by the processor the presence of the TUNER3 and 1 pins is used to determine system bus frequency See Table 2 22 for the various TUNER pin combinations and resulting system bus frequency and slew rate combination These pins allows remote measurement of on die Vcore voltage No connections that constitute a current load can be made to these pins Table 2 2 Nominal Resistance Values for Tuner2 Tuner3 400 MHz 400 MHz 533 MHz 5 Load Platform Ohms 3 Load Platform Ohms 3 Load Platform Ohms NC NC NC Tuner2 150 Tuner2 150 Tuner2 150 Tuner3 NC Tuner3 NC Tuner3 NC Notes 1 Depending on system configuration the processor may or may not require a resistor on the TUNER pin OEMs may leave the pin unconnected or connect it to VCTERM through a 150 or 100 ohm resistor If A 21 17 are driven to all O s or all 1 s at reset see Table 2 22 for proper use of the TUNER Pins Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 17 Table 2 3 2 4 18 Electrical Specifica
77. d subscript for example State of Data The data contained in this document is subject to change It is the best information that Intel is able to provide at the publication date of this document Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Introduction ke 1 6 Reference Documents The reader of this specification should also be familiar with material and concepts presented in the following documents Intel Itanium 2 Processor Specification Update Intel Itanium Architecture Software Developer s Manual Volume 1 Application Architecture Intel Itanium Architecture Software Developer s Manual Volume 2 System Architecture Intel Itanium Architecture Software Developer s Manual Volume 3 Instruction Set Reference Intel Itanium 2 Processor Reference Manual for Software Development and Optimization Intel Itanium Processor Family System Abstraction Layer Specification 700 Debug Port Design Guide System Management Bus Specification Note Contact your Intel representative or check http developer intel com for the latest revision of the reference documents Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 13 14 Introduction Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet Electrical Specifications tel 2 2 1 2 1 1 2 1 2 2 2 2 2 1 Electrical Specif
78. e 0 875 V System Bus Clock Differential HSTL DC Specifications Symbol Parameter Minimum Maximum Unit Notes Input High Voltage 0 78 1 3 V Input Low Voltage 0 3 0 5 V Vx Input Crossover Voltage 0 55 0 85 V Input Pad Capacitance 1 75 pF TAP Connection DC Specifications Symbol Parameter Minimum Maximum Unit Notes Input Low Voltage 0 3 0 5 V Input High Voltage 1 1 1 57 V 12 VoL Output Low Voltage 0 3 V Vou Output High Voltage 1 2 V 2 3 Output Low Current 20 mA lic Input Current 690 uA Notes 1 There is a 100 mV hysteresis on TCK 2 MAX 1 5 V 5 Max 1 2 V 5 3 There is no internal pull up An external pull up is always assumed Max voltage tolerated at TDO is 1 5 V 4 Per input pin Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 19 intel Electrical Specifications Table 2 8 SMBus DC Specifications Symbol Parameter Minimum Typ Maximum Unit Notes 3 3V Vcc for the System Management 3 14 3 3 3 47 V 3 3 V 5 Components ViL Input Low Voltage 0 3 0 3 3 3 V V Vin Input High Voltage 2 31 3 47 V 3 3 5 Min 0 7 3 3V VoL Output Low Voltage 0 4 V 13 3 3V Supply Current 5 0 30 0 mA lot Output Low Current 3 mA l loi2 Output Low Current 6 mA 2 lu Input Leakage Current 10 lio Output Leakage Current 10 Notes 1 The value specified for 1 o applies to all s
79. e SpecifiCatiO is ciere exero eX r on 18 2 4 Signal Specifications u aa REDE E Ra Gd 18 2 4 1 Maximum Ratings aste erret 22 2 5 System Bus Signal Quality Specifications and Measurement Guidelines 23 2 5 1 Overshoot Undershoot 23 2 5 2 Overshoot Undershoot Pulse Duration 24 2 5 3 Activity M pd 24 2 5 4 Reading Overshoot Undershoot Specification 24 2 5 5 Determining if a System Meets the Overshoot Undershoot 25 2 5 6 Wired OR SigQnals 25 2 6 Voltage Regulator Connector 5190 5 ee 27 2 7 System Bus Clock and Processor 0 0 1 mme 31 2 8 Recommended Connections for Unused Pins s sess 33 Pinout SPECiil CATIONS writs ial dated lade 35 4 Mechanical Specifications 2 2 eoru Medi aan b etd ies ak reel del nies 65 4 1 Processor Package 1 menn 65 4 1 1 Voltage Regulator MVR to Processor Package 71 42 Package Marking o teo i e de x MU E asa 7
80. e a kara Re Sc race ad ri eus 103 1 54 6 Medd T 103 A 1 55 SBSYX 103 1 56 SBSY daha qawa 103 57 SBSY 103 1 58 SPECK 1 elev i bo WE UTOR 103 1 59 STBn 7 0 5 7 0 1 2 2 0 103 60 Cip er PEUT 104 P NIMMT RUD ED LT TET 104 104 1 63 0 ca ias o aon ERR e PRU ce cea re a e o E 104 1 64 THRMALERT nean nnn EEE assqa 104 ALOS fi MS Duy atau 104 1 66 TND 1 2 1 7 7 2 4 4 4 4 aa wawa maak wasuaka 104 1 67 1 a n as s aus aasan RAN RUE RE RE FUGO ERR MEE 105 68 TRSTA I Ax UNT 105 A 1 69 WSNP 1 Q ierra t rr RR TERRE A iA 105 A2 Signal Um Ex h 105 Figures 2 1 Generic Clock Waveform 1 1 2 21 2 2 SMSC Clock 1 1 nennen nen nn nn enn nennen 22 2 3 System Bus Signal Waveform Exhibiting Overshoot Under
81. e data bus is released after DBSY is deasserted DBSY is replicated three times to enable partitioning of the data paths in the system agents This copy of the Data Bus Busy signal DBSY is an input as well as an output DBSY_C1 DBSY is a copy of the Data Bus Busy signal This copy of the Data Bus Busy signal DBSY_C1 is an output only DBSY_C2 O DBSY is a copy of the Data Bus Busy signal This copy of the Data Bus Busy signal DBSY_C2 is an output only DEFER 1 The DEFER signal is asserted by an agent to indicate that the transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the priority agent Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet 1 24 1 25 1 26 Table 7 DEN 1 The Defer Enable DEN signal is driven the bus on the second clock of the Request Phase on the Ab 4 pin DEN is asserted to indicate that the transaction can be deferred by the responding agent DEP 15 0 1 0 The Data Bus ECC Protection DEP 15 0 signals provide optional ECC protection for Data Bus D 127 0 They are driven by the agent responsible for driving D 127 0 During power on configuration bus agents can be enabled for either ECC checking or no checking The ECC error correcting code can detect and correct single bit errors and detect double bit or nibble errors DHIT 1 The Deferred Hit DHIT
82. e immediately stops converting and enters standby mode If low the device converts in either one shot or timer mode 5 0 RESERVED 0 Reserved for future use Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 89 System Management Feature Specifications Conversion Rate Register The contents of the conversion rate register determine the nominal rate at which analog to digital conversions happen when the thermal sensing device is in auto convert mode Table 6 16 shows the mapping between conversion rate register values and the conversion rate As indicated in Table 6 16 the conversion rate register is set to its default state of 02h 0 25 Hz nominally when the thermal sensing device is powered up There is a 25 error tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate Table 6 16 Thermal Sensing Device Conversion Rate Register 90 Register Contents Conversion Rate Hz 00h 0 0625 Olh 0 125 02h 0 25 03h 0 5 04h 1 05 2 06h 4 07h 8 08h to FFh Reserved for future use Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet intel A A 1 A 1 1 A 1 2 A 1 3 A 1 4 A 1 5 Signals Reference This appendix provides an alphabetical listing of all Dual Core Intel Itanium 9000 and 9100 series processor system bus signals The tables at the end of this appendix summarize the signals
83. er local interrupt LINT1 pin OWN 1 Guaranteed Cache Line Ownership OWN signal is driven to the bus the second clock of the Request Phase on the Ab 5 pin OWN is asserted if cache line ownership is guaranteed This allows a memory controller to ignore memory updates due to implicit writebacks PMI 1 The Platform Management Interrupt PMI signal triggers the highest priority interrupt to the processor PMI is usually used by the system to trigger system events that will be handled by platform specific firmware PWRGOOD 1 The Power Good PWRGOOD signal must be deasserted L during power on and must be asserted H after RESET is first asserted by the system REQ 5 0 1 O The REQ 5 0 are the Request Command signals They are asserted by the current bus owner in both clocks of the Request Phase In the first clock the REQa 5 0 signals define the transaction type to a level of detail that is sufficient to begin a snoop request the second clock REQb 5 0 signals carry additional information to define the complete transaction type REQb 4 3 signals transmit DSZ 1 0 or the data transfer information of the requestor for transactions that involve data transfer REQb 2 0 signals transmit LEN 2 0 the data transfer length information In both clocks REQ 5 0 and ADS are protected by parity RP receiving agents observe the REQ 5 0 signals to determine the transaction type
84. erpret the overshoot undershoot specification In addition to the magnitude of the overshoot the following parameters must also be known the width of the overshoot and the AF To determine the allowed overshoot for a particular overshoot event the following must be done 1 Determine the signal group that the particular signal falls into For AGTL signals operating in the 2x source synchronous domain use Table 2 14 through Table 2 16 If the signal is a wired OR AGTL signal operating in the common clock domain use Table 2 15 through Table 2 17 2 Determine the magnitude of the overshoot or the undershoot relative to GND 3 Determine the activity factor how often does this overshoot occur 4 Next from the appropriate specification table determine the maximum pulse duration in nanoseconds allowed The pulse duration shown in the table refers to the period where either the maximum overshoot for high phase and undershoot for low phase occurred Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Electrical Specifications 2 5 5 2 5 6 intel 5 Compare the specified maximum pulse duration to the signal being measured If the pulse duration measured is less than the pulse duration shown in the table then the signal meets the specifications 6 Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive Determining if a System Meets the Overshoot Undershoot
85. eu of BCLKp They are driven by the data transfer agent with a tight skew relationship with respect to its corresponding bus signals and are used by the receiving agent to capture valid data in its latches This functions like an independent double frequency clock constructed from a falling edge of either STBp 7 0 or STBn 7 0 The data is synchronized by DRDY Each strobe pair is associated with 16 data bus signals and two ECC signals as shown in Table A 11 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 103 intel Table 11 STBp 7 0 and STBn 7 0 Associations 1 60 1 61 1 62 1 63 1 64 1 65 1 66 104 Strobe Bits Data Bits ECC Bits STBp 7 STBn 7 D 127 112 DEP 15 14 STBp 6 STBn 6 D 111 96 DEP 13 12 STBp 5 STBn 5 0 95 80 2 11 10 STBp 4 STBn 4 D 79 64 DEP 9 8 STBp 3 STBn 3 D 63 48 DEP 7 6 STBp 2 5 2 0 47 32 DEP 5 4 STBp 1 STBn 1 D 31 16 DEP 3 2 STBp 0 5 0 D 15 0 DEP 1 0 1 The Test Clock signal provides the clock input for the IEEE 1149 1 compliant TAP TDI 1 The Test Data In TDI signal transfers serial test data into the processor TDI provides the serial input needed for IEEE 1149 1 compliant TAP TDO O The Test Data Out TDO signal transfers serial test data out from the processor TDO provides t
86. family 73h 32 Processor Feature Flags All others are reserved 1 indicates EEPROM data 9 Demand Based Switching for specified field is valid Enabled 8 Core Level Lockstep Enabled 7 Socket Level Lockstep Enabled 6 Dual Core Enabled 5 Hyper Threading Enabled 4 Upper temp reference byte 3 Thermal calibration offset byte present 2 Scratch EERPOM present 1 Core VID Present 77h 4 Number of Devices in TAP One 4 bit hex digit 2h for dual core Chain processor 78h Reserved Reserved for future use Oh 79h Checksum 1 byte checksum Add up by byte and take 2 5 complement Other 7Ah 16 Reserved Reserved for future use 0000h 84 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet m e System Management Feature Specifications n te D 6 3 6 4 Table 6 5 Notes 1 Refer to the Intel Itanium Architecture Software Developer s Manual for details on CPUID registers 2 The translation is using BCD 3 Itanium 9000 and 9100 series use a hex to decimal conversion Scratch EEPROM Also available on the SMBus interface on the processor is an EEPROM which may be used for other data at the system vendor s discretion Intel will not be using the scratch EEPROM The data in this EEPROM once programmed can be write protected by asserting the active high SMWP signal This signal has a weak pull down 10 to allow the EEPROM to be programmed in systems with no implementati
87. g frequencies and differing cache sizes there may be uncharacterized errata that exist in such configurations Customers would be fully responsible for validation of system configurations with mixed components other than the supported configurations described above Terminology In this document the processor refers to the Dual Core Intel Itanium processor 9000 and 9100 series processor unless otherwise indicated symbol after a signal name refers to an active low signal This means that a signal is in the active state based on the name of the signal when driven to a low level For example when RESET is low a processor reset has been requested When NMI is high a non maskable interrupt has occurred In the case of lines where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 refers to a hex and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level The term system bus refers to the interface between the processor system core logic and other bus agents The system bus is a multiprocessing interface to processors memory 1 0 signal name has all capitalized letters for example VCTERM A symbol referring to a voltage level current level or a time value carries a plain subscript for example Vcore or a Capitalized abbreviate
88. h N 38 39h 3Bh 2 Substrate Revision Software 2 bit revision number 00 ID Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 83 intel System Management Feature Specifications Table 6 4 Processor Information ROM Format Sheet 3 of 3 Offset of Section Bits Function Notes Examples 3Ch 8 Reserved Reserved for future use 00h 3Dh 8 Checksum 1 byte checksum Add up by byte and take 2 s complement Part Numbers 3Eh 56 Processor Part Number Seven 8 bit ASCII characters 80549 3Eh 8 3Fh 0 40h 5 41h 4 42h 2 43h K 44h C 45h 64 Processor Electronic 64 bit identification number May have padded zeros Signature 4Dh 168 Reserved Reserved for future use x0h 62h 8 Checksum 1 byte checksum Add up by byte and take 2 s complement Thermal Reference 63h 8 Upper Temp Reference Byte Hex value of thermal upper temp Default 92 5Ch limit 64h 8 Thermal Calibration Offset Number of degrees in error will be set per Byte Present part and expected to be 12C 65h 8 Reserved Reserved for future use 00h 66h 8 Checksum 1 byte checksum Add up by byte and take 2 s complement Features 67h 32 1A 32 Processor Core From 32 bit CPUID 4387FBFFh Feature Flags 6Bh 64 Reserved Reserved Processor core feature 0000 0000 6380 811Bh flags implemented in the Itanium processor
89. hat is values above 127 are represented at 127 decimal and values below 128 are represented as 128 decimal 88 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet System Management Feature Specifications n tel 6 7 2 6 7 3 Table 6 14 6 7 4 Table 6 15 Thermal Limit Registers The thermal sensing device has two thermal limit registers they define high and low limits for the processor core thermal diode The encoding for these registers is the same as for the thermal reference registers If the diode thermal value equals or exceeds one of its limits then its alarm bit in the status register is triggered This indication is also brought out to the processor system bus via the THRMALERT signal Status Register The status register shown in Table 6 14 indicates which if any of the thermal value thresholds have been exceeded It also indicates if a conversion is in progress or if an open circuit has been detected in the processor core thermal diode connection Once set alarm bits stay set until they are cleared by a status register read A successful read to the status register will clear any alarm bits that may have been set unless the alarm condition persists Note that the THRMALERT interrupt signal is latched and is not automatically cleared when the status flag bit is cleared The latch is cleared by sending the Alert Response Address 0001100 on the SMBus Thermal Sensing Device Status Reg
90. he serial output needed for IEEE 1149 1 compliant TAP THRMTRI P The Thermal Trip THRMTRIP signal protects the processor from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips Data will be lost if the processor goes into thermal trip signaled to the system by the assertion of the THRMTRI P signal Once THRMTRIP is asserted the platform must assert RESET to protect the physical integrity of the processor THRMALERT THRMALERT is asserted when the measured temperature from the processor thermal diode equals or exceeds the temperature threshold data programmed in the high temp THIGH or low temp TLOW registers on the sensor This signal can be used by the platform to implement thermal regulation features TMS 1 The Test Mode Select TMS signal is an 1149 1 compliant TAP specification support signal used by debug tools TND 1 Purge Not Done TND signal is asserted to delay completion of a TLB Purge instruction even after the TLB Purge transaction completes on the system bus Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Signals Reference A 1 67 A 1 68 A 1 69 A 2 Table A 12 Table A 13 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet intel TRDY 1 The Target Ready TRDY signal is asserted by
91. ications This chapter describes the electrical specifications of the Dual Core Intel Itanium Processor 9000 and 9100 series Dual Core Intel Itanium Processor 9000 and 9100 Series System Bus Most Dual Core Intel Itanium processor 9000 and 9100 series signals use the Itanium processor s assisted gunning transceiver logic AGTL signaling technology The termination voltage Vcterm is generated on the baseboard and is the system bus high reference voltage The buffers that drive most of the system bus signals on the processor are actively driven to during a low to high transition to improve rise times and reduce noise These signals should still be considered open drain and require termination to which provides the high level The processor system bus is terminated to Vcterm at each end of the bus There is also support of off die termination in which case the termination is provided by external resistors connected to AGTL inputs use differential receivers which require a reference signal Vref Vggr is used by the receivers to determine if a signal is a logical O or a logical 1 The processor generates Vper on die thereby eliminating the need for an off chip reference voltage source System Bus Power Pins VCTERM 1 2 V input pins on the processor provide power to the driver buffers and on die termination The GND pins in addition to the GND input at the power tab connector provide ground
92. ies thermal sensing device provides a means of acquiring thermal data from the processor The accuracy of the thermal reading is expected to be better than 5 C The thermal sensing device is composed of control logic SMBus interface logic a precision analog to digital converter and a precision current source The thermal sensing device drives a small current through a thermal diode located on the processor core and measures the voltage generated across the thermal diode by the current With this information the thermal sensing device computes a byte of temperature data Software running on the processor or on a micro controller can use the temperature data from the thermal sensing device to thermally manage the system The thermal sensing device provides a register with a data byte seven bits plus sign which contains a value corresponding to the sampled output of the thermal diode in the processor core The value of the byte read from the thermal sensor is always higher than the actual processor core temperature therefore the offset from the reading needs to be subtracted to obtain an accurate reading of the processor core temperature This data can be used in conjunction with the upper temperature reference byte provided in the Processor Information ROM for thermal management purposes The temperature data from the thermal sensor can be read out digitally using an SMBus read command see Section 6 6 The thermal sensor detects when SMBus po
93. ificant bit first Table 6 4 Processor Information ROM Format Sheet 1 of 3 Offset of Section Bits Function Notes Examples Header 00h 8 Data Format Revision Two 4 bit hex digits Start with 00h 018 16 EEPROM Size Size in bytes MSB first Use a decimal to hex transfer 128 bytes 0080h 02h 7 4 0000 02h 3 0 0000 e 01h 7 4 1000 e O1h 3 0 0000 03h 8 Processor Data Address Byte pointer 00h if not present OEh 04h 8 Processor Core Address Byte pointer if not present 17h 05h 8 Processor Cache Address Byte pointer if not present 28h 06h 8 Processor Data Address Byte pointer 00h if not present 37h 07h 8 Part Number Data Address Byte pointer if not present 3Eh 08h 8 Thermal Reference Data Byte pointer if not present 63h Address 09h Feature Data Address Byte pointer OOh if not present 67h OAh Other Data Address Byte pointer 00h if not present 7Ah 82 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet System Management Feature Specifications intel Table 6 4 Processor Information ROM Format Sheet 2 of 3 Offset of Section Bits Function Notes Examples OBh 16 Reserved Reserved for future use 0000h ODh 8 Checksum 1 byte checksum Add up by byte and take 2 s complement Processor OEh 48 S spec Number Six 8 bit ASCII characters S spec number of 5123 would be 13h 00h
94. ignals except for THRMALERT 2 The value specified for g gt applies only to THRMALERT which is an open drain signal Table 2 9 LVTTL Signal DC Specifications Symbol Parameter Minimum Maximum Unit Notes Vu Input Low Voltage 0 8 V Vin Input High Voltage 2 0 3 63 V VoL Output Low Voltage 0 4 V Vou Output High Voltage 2 4 V Table 2 10 through Table 2 11 list the AC specifications for the processor s clock and SMBus timing diagrams begin with Figure 2 1 The processor uses a differential HSTL clocking scheme with a frequency of 200 266 or 333 MHz The SMBus is a subset of the I2C interface which supports operation of up to 100 kHz Table 2 10 System Bus Clock Differential HSTL AC Specifications Sheet 1 of 2 System Symbol Parameter Maximum Unit Figure Notes MHz Tperiod BCLKp Period 200 5 0 ns Figure 2 1 System Clock Skew 200 100 ps 1 BCLKp Frequency 200 200 200 MHz Figure 2 1 2 Tjitter BCLKp Input Jitter 200 100 ps Figure 2 1 3 Thigh BCLKp High Time 200 2 25 2 5 2 75 ns Figure 2 1 E Tiow BCLKp Low Time 200 2 25 2 5 2 75 ns Figure 2 1 Tperiod BCLKp Period 266 3 75 ns Figure 2 1 System Clock Skew 266 60 ps 5 BCLKp Frequency 266 266 266 MHz Figure 2 1 2 Tjitter BCLKp Input J itter 266 50 ps Figure 2 1 3 Thigh BCLKp High Time 266 1 69 1 88 2 06 ns Figure 2 1 a Tiow BCLKp Low Time 266 1 69 1 88 2
95. ime dependent overshoot undershoot requirements Table 2 13 Source Synchronous AGTL Signal Group and Wired OR Signal Group Absolute Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Overshoot Undershoot Tolerance Parameter Description Specification Units VcTERM 1 O power supply voltage nominal 1 20 V VMAX Maximum absolute voltage for system bus signals at the input 1 65 V of the receiver buffers VMIN Minimum absolute voltage for system bus signals at the input 0 45 V of the receiver buffers Overshoot Time dependent overshoot amount above Vcterm Undershoot Time dependent undershoot amount below GND 1 Notes 1 These parameters cannot be specified in absolute terms Notes The following notes apply to Table 2 14 through Table 2 17 1 Absolute Maximum Overshoot magnitude of 1 65 V must never be exceeded 2 Absolute Maximum Overshoot is measured referenced to GND Pulse duration of overshoot is measured relative to Vcterm Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to GND Ringback below cannot be subtracted from overshoots undershoots Lesser undershoot does not allocate overshoot with longer duration or greater magnitude values specified by design characterization gy tn qs t 25 n tel Electrical Specifications Table 2 14 Source Synchronous AGTL Signal Group Time Dependent Overshoot Unde
96. imum specifications the pulse magnitude duration and activity factors must all be used to determine if the overshoot undershoot pulse is within specifications System Bus Signal Waveform Exhibiting Overshoot Undershoot Maximum Absolute Overshoot Time dependent Overshoot GND MIN Time dependent Maximum Undershoot Absolute Undershoot 000588 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 23 tel Electrical Specifications Note 2 5 3 Note Note 2 5 4 24 Overshoot Undershoot Pulse Duration Pulse duration describes the total time that an overshoot undershoot event exceeds the overshoot undershoot reference voltage Vcrerm GND The total time could encompass several oscillations above the reference voltage Multiple overshoot undershoot pulses within a single overshoot undershoot event may need to be measured to determine the total pulse duration Oscillations below the reference voltage cannot be subtracted from the total overshoot undershoot pulse duration Activity Factor Activity factor AF describes the frequency of overshoot or undershoot occurrence relative to a clock Since the highest frequency of assertion of any common clock signal is every other clock an AF 1 indicates that the specific overshoot or undershoot waveform occurs every other clock cycle Thus an AF 0 01 indicates that the specific overshoot or undershoot
97. ination of abundant resources to exploit ILP as well as increased frequency for minimizing the latency of each instruction The resources consist of six integer units six multimedia units two load and two store units three branch units two extended precision floating point units one additional single precision floating point unit per core The hardware employs dynamic prefetch branch prediction a register scoreboard and non blocking caches to optimize for compile time non determinism Three levels of on die cache minimize overall memory latency This includes up to a 24 MB L3 cache accessed at core speed providing up to 8 53 GB sec of data bandwidth The system bus is designed to support up to four physical processors on a single system bus and can be used as an effective building block for very large systems The balanced core and memory subsystem provide high performance for a wide range of applications ranging from commercial workloads to high performance technical computing The Dual Core Intel Itanium processor 9000 and 9100 series supports a range of computing needs and configurations from a two way to large SMP servers This document provides the electrical mechanical and thermal specifications for the Dual Core Intel Itanium processor 9000 and 9100 series for use while employing systems with the processors Processor Abstraction Layer The Dual Core Intel Itanium processor 9000 and 9100 series requires implementation
98. ing Device SD 10K V ALERT AO sc 9 IK M geratch SP AW e A2 EEPROM WP e 10K e gt SMAO SMWP SMA1 SMSD 3 3V SMA2 SMSC THRMALERT 10K System Board System Board NOTE 1 Actual implementation may vary 2 For use in general understanding of the architecture 000668b Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet System Management Feature Specifications n te D 6 1 3 Note Table 6 2 SMBus Device Addressing Of the addresses broadcast across the SMBus the memory components claim those of the form 1010XXYZb The XX and Y bits are used to enable the devices on the processor at adjacent addresses The Y bit is hard wired on the processor to GND 0 for the Scratch EEPROM and pulled to 3 3 V 1 for the processor information ROM The XX bits are defined by the processor socket via the SMAO and 5 1 pins on the processor connector These address pins have a weak pull down 10 to ensure that the memory components are in a known state in systems which do not support the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction The thermal sensing device internally decodes one of three upper address patterns from the bus of the form 0011XXXZb 1001XXXZb or 0101XXXZb The device s addressing as implemented uses SMA2 and 5 1 and includes Hi Z state for the SMA2 address pin
99. intel Dual Core Intel I tanium Processor 9000 and 9100 Series Dual Core Intel Itanium Processor 1 6 GHz with 24 L3 Cache 9050 Dual Core Intel Itanium Processor 1 6 GHz with 18 MB Cache 9040 Dual Core I ntel Itanium Processor 1 6 GHz with 8 MB L3 Cache 9030 Dual Core Intel Itanium Processor 1 42 GHz with 12 MB Cache 9020 Dual Core Intel Itanium Processor 1 4 GHz with 12 MB L3 Cache 9015 Intel I tanium Processor 1 6 GHz with 6 MB L3 Cache 9010 Dual Core I ntel amp I tanium Processor 1 66 1 6 GHz with 24 MB Cache 9152 Dual Core Intel Itanium Processor 1 66 GHz with 24 MB L3 Cache 9150M Dual Core Intel Itanium Processor 1 6 GHz with 24 MB L3 Cache 9150N Dual Core Intel Itanium Processor 1 66 GHz with 18 MB L3 Cache 9140M Dual Core I ntel Itanium Processor 1 6 GHz with 18 MB L3 Cache 9140N Dual Core Intel Itanium Processor 1 42 GHz with 12 MB L3 Cache 9120 Dual Core Intel Itanium Processor 1 66 GHz with 8 MB Cache 9130M Intel Itanium Processor 1 6 GHz with 12 MB L3 Cache 9110N Datasheet October 2007 Document Number 314054 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR
100. ions tel 2 5 2 5 1 Figure 2 3 System Bus Signal Quality Specifications and Measurement Guidelines Overshoot or undershoot is the absolute value of the maximum voltage above the nominal Vcterm voltage or below GND as shown in Table 2 3 The overshoot undershoot specifications limit transitions beyond or GND due to the fast signal edge rates The processor can be permanently damaged by repeated overshoot or undershoot events on any input output or I O buffer if the charge is large enough that is if the overshoot undershoot is great enough Determining the impact of an overshoot undershoot condition requires knowledge of the magnitude the pulse duration and the activity factor AF Overshoot Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level For the processor both are referenced to GND as shown in Figure 2 3 It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently Overshoot undershoot magnitude levels must observe the absolute maximum specifications listed in Table 2 13 through Table 2 17 These specifications must not be violated at any time regardless of bus activity or system state Within these specifications are threshold levels that define different allowed pulse duration Provided that the magnitude of the overshoot undershoot is within the absolute max
101. ircuitry sess mmm eene 80 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 5 Tables 2 1 NJ F2 O O DANBRREWWNNNNN NP PP ON P N PP N N N F w Itanium Processor System Bus Signal Groups eene 16 Nominal Resistance Values for Tunerl Tuner2 17 Processor Package Specifications 1 nnne nen nnn 18 AGTL Signals DC 5 00 enn 19 Power Good Signal DC 5 1 nemen 19 System Bus Clock Differential HSTL DC 19 Connection DC Specifications ccc cece eee eee eee nee memes enn 19 SMBus DG Specifications 20 LVITE Signal DC SPecihiCAatlon uu uu T canes 20 System Bus Clock Differential HSTL 20 SMBUS AC SPECI Cation Sess 21 Dual Core Intel Itanium Processor Absolute Maximum 5 22 Source Synchronous AGTL Signal Group and Wired OR Signal Group Absol
102. ister Bit Name Function 7 MSB BUSY A one indicates that the device s analog to digital converter is busy converting 6 RESERVED Reserved for future use 5 RESERVED Reserved for future use 4 RHIGH A one indicates that the processor core thermal diode high temperature alarm has been activated 3 RLOW A one indicates that the processor core thermal diode low temperature alarm has been activated 2 OPEN A one indicates an open fault in the connection to the processor core diode 1 RESERVED Reserved for future use 0 LSB RESERVED Reserved for future use Configuration Register The configuration register controls the operating mode standby vs auto convert of the thermal sensing device Table 6 15 shows the format of the configuration register If the RUN STOP bit is set high then the thermal sensing device immediately stops converting and enters standby mode The thermal sensing device will still perform analog to digital conversions in standby mode when it receives a one shot command If the RUN STOP bit is clear low then the thermal sensor enters auto conversion mode The thermal sensing device starts operating in free running mode auto converting at 0 25 Hz after power up Thermal Sensing Device Configuration Register Reset 5 Bit Name State Function 7 MSB RESERVED 0 Reserved for future use 6 RUN STOP 0 Standby mode control bit If high the devic
103. ith ADS and A 49 3 AP 1 covers A 49 27 and AP 0 covers A 26 3 correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high ASZ 1 0 1 The ASZ 1 0 signals are the memory address space size signals They are driven by the request initiator during the first Request Phase clock the REQa 4 3 pins ASZ 1 0 signals are valid only when REQa 2 1 signals equal 01B 10B or 11B indicating a memory access transaction The ASZ 1 0 decode is defined in Table A 1 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 91 intel Table A 1 A 1 6 Table A 2 A 1 7 A 1 8 92 Address Space Size Signals Reference ASZ 1 01 ni im du 0 0 Reserved Reserved 0 1 36 bit 0 to 64 GByte 1 1 0 50 bit 64 GByte to 1 Pbyte 1 1 1 Reserved Reserved Any memory access transaction addressing a memory region that is less than 64 GB that is Aa 49 36 are all zeroes must set ASZ 1 0 to 01 Any memory access transaction addressing a memory region that is equal to or greater than 64 GB that is 49 36 are not all zeroes must set ASZ 1 0 to 10 All observing bus agents that support the 64 GByte 36 bit address space must respond to the transaction when ASZ 1 0 equals 01 All observing bus agents that sup
104. itry to resist damage from static electric discharge one should always take precautions to avoid static voltages or electric fields Dual Core Intel Itanium Processor Absolute Maximum Ratings Symbol Parameter Minimum Maximum Unit Notes Tstorage Processor Storage Temperature 10 45 1 Tshipping Processor Shipping Temperature 45 75 2 Vcore Any Vcore Voltage with Respect to GND 0 3 1 55 V Vcache Any Veache Voltage with Respect to GND 0 3 1 55 V V ixed Any Voltage with Respect to GND 0 3 1 55 V 3 3V Any 3 3 V Supply Voltage with Respect to 0 3 5 5 V 3 GND Vin sMBus SMBus Buffer DC Input Voltage with 0 1 6 0 V 3 Respect to GND Vin AGTL AGTL Buffer DC Input Voltage with 0 45 1 65 V 4 5 Respect to GND VCTERM Any Vcterm Voltage with Respect to GND 0 45 1 65 Vin TAP TAP Buffer DC Input Voltage with Respect 0 45 1 65 V 4 to GND Notes 1 Storage temperature is temperature in which the processor can be stored for up to one year 2 Shipping temperature is temperature in which the processor can be shipped for up to 24 hours 3 Parameters are from third party vendor specifications 4 Maximum instantaneous voltage at receiver buffer input 5 Specification includes Vin agti and Vin acTL ASYNCHRONOUS AGTL asynchronous buffer DC input voltage with respect to GND Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet m Electrical Specificat
105. leaving this pin unconnected Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 81 intel System Management Feature Specifications Table 6 3 EEPROM SMBus Addressing on the Dual Core Intel Itanium Processor 9000 and 9100 Series Memory upper 1 Processor Select Device mead Address Write Address Select Device Addressed Hex 5 1 SMAO gt Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 AOh A1h 1010 0 0 0 X Scratch EEPROM 1 A2h A3h 1010 0 0 1 X Processor Information ROM 1 A4h A5h 1010 0 1 0 X Scratch EEPROM 2 A6h A7h 1010 0 1 1 X Processor Information ROM 2 A8h A9h 1010 1 0 0 x Scratch EEPROM 3 AAh ABh 1010 1 0 1 X Processor Information ROM 3 ACh ADh 1010 1 1 0 X Scratch EEPROM 4 AEh AFh 1010 1 1 1 X Processor Information ROM 4 Notes 1 Although this addressing scheme is targeted for up to four way MP systems more processors can be supported by using a multiplexed or separate SMBus implementation 6 2 Processor nformation ROM An electrically programmed read only memory ROM provides information about the processor The checksum bits for each category provide error correction and serve as a mechanism to check whether data is corrupted or not This information is permanently write protected Table 6 4 shows the data fields and formats provided in the memory Note The data in byte format is written and read serially with the most sign
106. ls or exceeds the temperature threshold data programmed in the high temp THIGH or low temp TLOW registers on the sensor Intel recommends using the upper temperature reference byte listed in the Processor Information ROM when programming the THIGH register see Chapter 6 for more details This signal can be used by the platform to implement thermal regulation features such as generating an external interrupt to tell the operating system that the processor core die temperature is increasing Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 75 intel 5 1 2 5 1 3 Warning 5 1 4 Warning 5 2 Warning 76 Enhanced Thermal Management ETM is a power and thermal protection feature On the Dual Core Intel Itanium processor 9000 and 9100 series ETM uses power and thermal sensing devices on the die to monitor entry points indicating dangerous operation exceeding the thermal or power specification Once the sensing devices observe the temperature rising above the power or thermal entry point the processor will enter a low power mode of execution and notify the system by sending a Correctable Machine Check Interrupt CMCI The processor will remain in this low power mode until the power and temperature decrease below the entry points and remain there for approximately one second at which point it will send another CMCI and resume normal operation If the power and temperature cannot be reduced and continue
107. ly DRDY C2s DRDY is copy of the Data Ready signal This copy of the Data Phase data ready signal DRDY C235 is an output only DSZ 1 0 1 O The Data Size DSZ 1 0 signals are transferred on 4 3 signals in the second clock of the Request Phase by the requesting agent The DSZ 1 0 signals define the data transfer capability of the requesting agent For the processor 057 01 always EXF 4 0 1 O The Extended Function EXF 4 0 signals are transferred the 7 3 pins by the requesting agent during the second clock of the Request Phase The signals specify any special functional requirement associated with the transaction based on the requestor mode or capability The signals are defined in Table A 8 Extended Function Signals CE eM Signal Name Alias Function EXF 4 Reserved Reserved EXF 3 SPLCK FCL Split Lock Flush Cache Line EXF 2 OWN CCL Memory Update Not Needed Cache Cleanse EXF 1 DEN Defer Enable 0 DPS Deferred Phase Supported Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 1 33 1 34 1 35 1 36 1 37 1 38 1 39 1 40 FCL 1 The Flush Cache Line FCL signal is driven to the bus the second clock of the Request Phase on the A 6 pin FCL is asserted to indicate that the memory transaction is initiated by the global Flush Cache Fc instruction
108. m architecture for high performance Integrated on die L3 cache of up to 24MB Up to 8 53GB s bandwidth 128 bit wide data bus i 50 bits of physical memory addressing and 64 65 of virtual addressing ina noi Up to four physical processors the same EUR genera and 128 floating point r gisters system bus at 400 MHz or 533 MHz data bus pporting register rotation frequency Register stack engine for effective management of processor resources to systems with multiple system Support for predication and speculation Extensive RAS features for business critical applications Full SMBus compatibility Enhanced machine check architecture with extensive ECC and parity protection Enhanced thermal management m Features to support flexible platform environments A 32 Execution Layer supports 1 32 application binaries Bi endian support Processor abstraction layer eliminates processor dependencies Built in processor information ROM PIROM 667 MHz 1 66 GHz 3 load bus Built in programmable EEPROM This feature enables increased bandwidth for Socket Level Lockstep Enterprise and HPC Core Level Lockstep m Demand Based Switching DBS Provides additional power management capability a This feature is applicable to only the 9100 series processors Dual Core Intel Itanium Processor 9000 and 9100 Series
109. nces and savings for your most demanding applications 8 10 Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet Introduction 1 1 1 1 2 intel Introduction Overview The Dual Core Intel Itanium processor 9000 9100 series employs Explicitly Parallel Instruction Computing EPIC design concepts for a tighter coupling between hardware and software In this design style the interface between hardware and software is engineered to enable the software to exploit all available compile time information and efficiently deliver this information to the hardware It addresses several fundamental performance bottlenecks in modern computers such as memory latency memory address disambiguation and control flow dependencies The EPIC constructs provide powerful architectural semantics and enable the software to make global optimizations across a large scheduling scope thereby exposing available Instruction Level Parallelism ILP to the hardware The hardware takes advantage of this enhanced and provides abundant execution resources Additionally it focuses on dynamic run time optimizations to enable the compiled code schedule to flow at high throughput This strategy increases the synergy between hardware and software and leads to greater overall performance The Dual Core Intel Itanium processor 9000 and 9100 series provides a 6 wide and 8 stage deep pipeline running at up to 1 6 GHz This provides a comb
110. nt that this is BCLKn or BCLKp signal Configuration signals other than A 21 17 must be asserted four BCLKs prior to the deasserted edge of RESET and must remain valid for two BCLKs minimum to three BCLKs maximum after the deasserted edge of RESET Figure 2 6 outlines the timing relationship between the configuration pins RESET and PWRGOOD for warm reset Figure 2 6 System Bus Reset and Configuration Timings for Warm Reset 32 PWRGOOD Additional Configuration RESET A217 Signals TA 1 15 ns minimum set up time to BCLK for deassertion edge of RESET 1 ms minimum for warm reset Bus ratio signals must be asserted no later than RESET Tp 2 BCLKs minimum 3 BCLKs maximum 4 BCLKs minimum 2 minimum 3 maximum 0007770 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet m Electrical Specifications tel 2 8 Recommended Connections for Unused Pins Pins that are unused in an application environment as opposed to testing environment should be connected to the states listed in Table 2 21 Pins that must be used in an application are stated as such and do not have a recommended state for unused connection Table 2 21 Connection for Unused Pins Pins Pin Groups gl daa Notes AGTL pins H 11 2 HSTL Cl
111. ocation Input Output Notes A20M A20M AH23 N C FERR FERR AH25 OUT Dual Core Intel tanium Processor 9000 and 9100 Series Datasheet Mechanical Specifications n tel 4 Mechanical Specifications This chapter provides the mechanical specifications of the Dual Core Intel Itanium processor 9000 and 9100 series 4 1 Processor Package Dimensions Figure 4 1 through Figure 4 5 provide package mechanical drawings and dimensions of the processor Table 4 1 and Table 4 2 provide additional details on the package dimensions The main components of processor package are identified in Figure 4 2 All specified package dimensions are in millimeters Figure 4 1 illustrates key package mechanical features These features enable package integration with socket power pod and cooling solution Vcore Vcache Vfixed GND and VID Pads Contact pads for delivering power and 1 0 signals from the voltage regulator to the processor through its substrate Socket Alignment Keyways They define package position in X and Y direction with respect to socket for proper alignment of package pins to socket contact holes Pin Shroud Alignment Keyways They define pin shroud position in X and Y direction with respect to processor Pin 1 Indicators Identifies package orientation with respect to socket motherboard Integrated Heat Spreader IHS Enhances dissipation of heat generated by the processor Provides interface surface between proce
112. ocessor 9000 and 9100 Series Datasheet Signals Reference intel Table 4 BRO 1 BR1 BR2 BR3 Signals for Rotating I nterconnect Bus Signal Agent 0 Pins Agent 1 Pins Agent 2 Pins Agent 3 Pins BREQ 0 BR 0 BR 3 BR 2 BR 1 BREQ 1 BR 1 BR 0 BR 3 BR 2 BREQ 2 BR 2 BR 1 BR 0 BR 3 BREQ 3 BR 3 BR 2 BR 1 BR 0 Table 5 BRO 1 BR1 BR2 BR3 Signals for 2P Rotating I nterconnect Bus Signal Agent 0 Pins Agent 3 Pins BREQ 0 BR 0 BR 1 BREQ 1 BR 1 BR 0 BREQ 2 Not Used Not Used BREQ 3 Not Used Not Used During power on configuration the priority agent must assert the BR 0 bus signal All symmetric agents sample their BR 3 0 pins on asserted to deasserted transition of RESET The pin on which the agent samples an asserted level determines its agent ID All agents then configure their pins to match the appropriate bus signal protocol as shown in Table A 6 Table A 6 BR 3 0 Signals and Agent IDs Pin Sampled A gent ID EC Arbitration ID Reported BR O 0 0 BR 3 1 2 BR 2 2 4 BR 1 3 6 A 1 15 BREQ 3 0 1 O BREQ 3 0 signals the symmetric agent arbitration bus signals called bus request A symmetric agent n arbitrates for the bus by asserting its BREQn signal Agent drives BREQn as an output and receives the remaining BREQ 3 0 signals as in
113. ock Signals Must be used All Power Signals Must be used PWRGOOD Must be used TAP Signals TCK ls TRST L L3 TDI H 1 3 TDO H 1 2 5 H tis System Management Signals 3 3V GND 2 0 N C SMSC N C SMSD N C SMWP N C THRMALERT H 14 LVTTL Power Pod Signals OUTEN Must be used PPODGD Must be used PROCPRES Must be used Other Pins N C N C A20M N C LOCK N C FERR N C TUNER1 N C or H 3 5 TUNER2 H 1 TUNER3 N C or H 3 5 Notes 1 L GND H 2 AGTL output signals SBSY 0 1 DBSY 0 1 and DRDY 0 1 may be left as N C if not used on platform 3 Can be No Connect or connected to via 1000hm or 150 ohm resistor 4 THRMALERT should be pulled up to 3 3 V through a resistor 5 With A 21 17 settings to all O or all 15 please refer to Table 2 22 for proper connection Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 33 intel Table 2 22 TUNER1 TUNER3 Translation Table 34 21 17 1 TUNER12 TUNER32 elie gu dm 0 0 0 667 1 7 0 0 1 533 1 4 0 1 N A 400 0 8 1 0 0 667 1 92 1 0 1 533 1 7 1 1 400 0 82 Notes 1 0 1 GND 2 0 Resistor not present 1 Resistor present Electrical Specifications Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Pinout Specifications 3 Note Pinout Specifications This chapter describes the Dual
114. on of this signal Processor nformation ROM and Scratch EEPROM Supported SMBus Transactions The processor information ROM and scratch EEPROM responds to three of the SMBus packet types current address read random address read and sequential read Table 6 5 shows the format of the current address read SMBus packet The internal address counter keeps track of the address accessed during the last read or write operation incremented by one Address roll over during reads is from the last byte of the last eight byte page to the first byte of the first page Roll over during writes is from the last byte of the current eight byte page to the first byte of the same page Table 6 6 shows the format of the random read SMBus packet The write with no data loads the address desired to be read Sequential reads may begin with a current address read or a random address read After the SMBus host controller receives the data word it responds with an acknowledge This will continue until the SMBus host controller responds with a negative acknowledge and a stop Table 6 7 shows the format of the byte write SMBus packet The page write operates the same way as the byte write except that the SMBus host controller does not send a stop after the first data byte and acknowledge The Scratch EEPROM internally increments its address The SMBus host controller continues to transmit data bytes until it terminates the sequence with a stop All data bytes will re
115. port larger than the 64 GByte 36 bit address space must respond to the transaction when ASZ 1 0 equals 01 or 10 3 0 1 The ATTR 3 0 signals are the attribute signals They are driven by the request initiator during the second clock of the Request Phase the Ab 35 32 pins The ATTR 3 0 signals are valid for all transactions ATTR 3 signal is reserved The ATTR 2 0 are driven based on the memory type Please refer to Table A 2 Effective Memory Type Signal Encoding 2 0 Description 000 Uncacheable 100 Write Coalescing 101 Write Through 110 Write Protect 111 Writeback BCLKp BCLKn 1 The BCLKp and BCLKn differential clock signals determine the bus frequency All agents drive their outputs and latch their inputs on the differential crossing of BCLKp and BCLKn on the signals that are using the common clock latched protocol BCLKp and BCLKn indirectly determine the internal clock frequency of the processor Each processor derives its internal clock by multiplying the BCLKp and BCLKn frequency by a ratio that is defined and allowed by the power on configuration BE 7 0 1 0 The BE 7 0 signals are the byte enable signals for partial transactions They are driven by the request initiator during the second Request Phase clock on the Ab 15 8 pins Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet intel Table A 3 1 9
116. puts The symmetric agents support distributed arbitration based on a round robin mechanism The rotating ID is an internal state used by all symmetric agents to track the agent with the lowest priority at the next arbitration event At power on the rotating ID is initialized to three allowing agent 0 to be the highest priority symmetric agent After a new arbitration event the rotating ID of all symmetric agents is updated to the agent ID of the symmetric owner This update gives the new symmetric owner lowest priority in the next arbitration event A new arbitration event occurs either when a symmetric agent asserts its BREQn on an Idle bus all BREQ 3 0 previously deasserted or the current symmetric owner deasserts BREQn to release the bus ownership to a new bus owner n On a new arbitration event all symmetric agents simultaneously determine the new symmetric owner using BREQ 3 0 and the rotating ID The symmetric owner can park on the bus hold the bus provided that no other symmetric agent is requesting its use The symmetric owner parks by keeping its BREQn signal asserted On sampling BREQn asserted by another symmetric agent the symmetric owner deasserts BREQn as soon as possible to release the bus A symmetric owner stops issuing new requests that are not part of an existing locked operation on observing BPRI asserted Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 95 intel 1 16 1 1
117. r The SMBus signals and LVTTL power pod signals are driven using the 3 3 V CMOS logic levels listed in Table 2 8 and Table 2 9 respectively Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Electrical Specifications intel 2 2 2 Signal Descriptions Appendix A Signals Reference contains functional descriptions of all system bus signals and LVTTL power pod signals Further descriptions of the system management signals are contained in Chapter 6 The signals listed under the Power and Other group are described here VCTERM GND N C TERMA TERMB TUNERI TUNER2 TUNER3 VCCMON VSSMON System bus termination voltage System ground No connection can be made to these pins The processor uses two pins to control the on die termination function TERMA and TERMB Both of these termination pins must be pulled to VCTERM in order to terminate the system bus using the on die termination resistors Both of these termination pins must be pulled to GND in order to use off die termination The TUNERI Pin can either be left as a no connect or left connected to VCTERM via resistor for the majority of platforms supporting the Dual Core Intel Itanium processor 9000 and 9100 series The TUNER2 resistor is used to control the termination resistance for the system bus I O buffers A lower resistance will cause a lower on die termination resistance On die termination mode will only be selected if the TERMA
118. rshoot Tolerance for 400 MHz System Bus cines ui Pulse Duration ns gyer Under 11 0 75 AF 0 5 AF 0 25 AF 0 1 AF 0 05 AF 0 01 1 65 0 45 0 0035 0 0036 0 0037 0 0040 0 0121 0 0241 0 1207 1 6 0 4 0 0039 0 0040 0 0045 0 0157 0 0396 0 0799 0 3996 1 55 0 35 0 0124 0 0168 0 0255 0 0520 0 1309 0 2626 1 3107 15 0 3 0 0405 0 0546 0 0833 0 1682 0 4279 0 8546 2 5 1 45 0 25 0 1304 0 1755 0 2671 0 5438 1 3629 2 5 2 5 14 0 2 0 4136 0 5581 0 8524 1 7215 2 5 2 5 2 5 135 0 15 1 3163 1 7815 2 5 2 5 2 5 2 5 2 5 13 01 35 2 5 2 5 2 5 2 5 2 5 2 5 1 25 0 05 2 5 2 5 2 5 2 5 2 5 2 5 2 5 Notes 1 Activity Factor 1 means signal toggles every 5 ns Table 2 15 Wired OR Signal Group BINIT HIT HITM BNR BERR Overshoot Undershoot Tolerance for 400 MHz System Bus mu Pulse Duration ns Over Under ars 0 75 AF 0 5 0 25 AF 01 0 05 0 01 shoot shoot 1 65 0 45 0 0166 0 0192 0 0306 0 0614 0 1539 0 3067 1 5374 1 6 0 4 0 0506 0 0674 0 1017 0 2032 0 5090 1 0213 5 1 55 0 35 0 1659 0 2216 0 3342 0 6676 1 6734 3 3413 5 1 5 0 3 0 5413 0 7218 1 0840 2 1814 5 5 5 1 45 0 25 1 7343 2 3194 3 4995 5 5 5 5 1 4 0 2 5 5 5 5 5 5 5 1 35 0 15 5 5 5 5 5 5 5 Notes 1 Activity Factor 1 means signal toggles every 10 ns
119. rted for one millisecond for a warm reset for a power on reset RESET must stay asserted for at least one millisecond after PWRGOOD and BCLKp have reached their proper specifications On observing asserted RESET all system bus agents must deassert their outputs within two clocks A number of bus signals are sampled at the asserted to deasserted transition of RESET for the power on configuration Unless its outputs are tristated during power on configuration after asserted to deasserted transition of RESET the processor begins program execution at the reset vector 1 52 RP 1 0 The Request Parity RP signal is driven by the requesting agent and provides parity protection for ADS REQ 5 0 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This definition allows parity to be high when all covered signals are high 102 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 1 53 1 54 1 55 1 56 1 57 1 58 1 59 RS 2 0 1 The Response Status RS 2 0 signals are driven by the responding agent the agent responsible for completion of the transaction RSP 1 The Response Parity RSP signal is driven by the responding agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection
120. sheet Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 4 of 15 Pin Name Input Output Notes DO06 D063 F06 IN OUT GND GND F07 IN 045 D45 F08 IN OUT GND GND F09 IN STBN2 STBN2 10 GND GND F11 IN 0044 D44 F12 IN OUT GND GND F13 IN D068 D68 F14 IN OUT GND GND F15 IN STBN4 STBN4 F16 IN OUT GND GND F17 IN 2069 D69 F18 IN OUT GND GND F19 IN D106 D106 20 IN OUT GND GND F21 IN STBN6 STBN6 F22 IN OUT GND GND F23 IN D103 D103 F24 IN OUT GND GND F25 IN VCTERM VCTERM G01 IN GND GND G02 IN D014 D14 G03 IN OUT VCTERM VCTERM G04 IN D008 DO8 G05 IN OUT D015 D15 G07 IN OUT VCTERM VCTERM G08 IN 038 038 G09 IN OUT D041 D41 G11 IN OUT VCTERM G12 IN D043 D43 G13 IN OUT D071 D71 G15 IN OUT VCTERM VCTERM G16 IN DO72 D72 G17 IN OUT DO79 D79 G19 IN OUT VCTERM VCTERM G20 IN D101 D101 G21 IN OUT D108 D108 G23 IN OUT VCTERM VCTERM G24 IN D107 D107 G25 IN OUT 0011 011 H02 IN OUT GND GND H03 IN D012 D12 H04 IN OUT GND GND H05 IN Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 53 m e n tel Pinout Specifications Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 5 of 15
121. shoot 23 2 4 Processors Power Tab Physical 28 2 5 System Bus Reset and Configuration Timings for Cold 31 2 6 System Bus Reset and Configuration Timings for Warm 2 32 3 1 Dual Core Intel Itanium Processor 9000 and 9100 Series 35 ASU Processor sese tror E RERUM 66 4 2 Package Height Pin 67 4 3 Processor Package Mechanical Interface DIMENSIONS 69 4 4 Processor Package Top Side Components Height Dimensions 70 4 5 Processor Package Bottom Side Components Height Dimensions 70 4 6 Processor to MVR Interface 1 5 4 0 6 nnn 71 4 7 Processor Top Side Marking 5 0 73 4 8 Processor Bottom Side Marking Placement 74 5 1 Dual Core Intel Itanium Processor 9000 and 9100 Series Thermal FOGEUICS EEUU 75 5 2 tanium Processor Package Thermocouple 77 6 1 Logical Schematic of SMBus C
122. specific Processor Abstraction Layer PAL firmware PAL firmware supports processor initialization error recovery and other functionality It provides a consistent interface to system firmware and operating systems across processor hardware implementations The Intel Itanium Architecture Software Developer s Manual Volume 2 System Architecture describes PAL Platforms must provide access to the firmware address space and PAL at reset to allow the processors to initialize Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 11 intel 1 4 1 5 12 The System Abstraction Layer SAL firmware contains platform specific firmware to initialize the platform boot to an operating system and provide runtime functionality Further information about SAL is available in the Intel Itanium Processor Family System Abstraction Layer Specification Mixing Processors of Different Frequencies and Cache Sizes Dual Core Intel Itanium processor 9000 and 9100 series on the same system bus are required to have the same cache size 24 MB 18 MB 12 MB 8 MB or 6 MB and identical core frequency Mixing components of different core frequencies and cache sizes is not supported and has not been validated by Intel Operating system support for multiprocessing with mixed components should also be considered While Intel has done nothing to specifically prevent processors within a multiprocessor environment from operating at differin
123. ssor and cooling solution Substrate Processor mechanical and electrical integration vehicle with the motherboard and processor enabling components Pin Field Grid 28 x 25 partially filled pin field for transmitting signals to and from processor to motherboard Voltage Regulator Connector Back Plate Keyway It defines the VR connector back plate position in X and Y direction with respect to the processor Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 65 n tel Mechanical Specifications Figure 4 1 Processor Package co 9000 id U U VU 1 8802690200200890640 25 ese AH25 9000000000000 Lp E Bottom View Side View S iv N 0000 0000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0900000000000 00000000000 _ z 4 Exo z m B 9006006000600 H 0000000000000 0000000000000 0000000000000 0000000000 8000000000600 I 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 9900090009000 0000 0000 2 Y 8000 78280 1 Ke Y Package E IHS A D
124. sult in an acknowledge from the Scratch EEPROM If more than eight bytes are written the internal address will roll over and the previous data will be overwritten In Table 6 5 through Table 6 7 S represents the SMBus start bit P represents a stop bit R represents a read W represents a write bit A represents an acknowledge and represents a negative acknowledge The shaded bits are transmitted by the processor information ROM or Scratch EEPROM and the bits that are not shaded are transmitted by the SMBus host controller In the tables the data addresses indicate eight bits The SMBus host controller should transmit eight bits but as there are only 128 addresses the most significant bit is a don t care Current Address Read SMBus Packet Device S Address R A Data PUER P 1 7 bits 1 1 8 bits 1 1 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 85 tel System Management Feature Specifications Table 6 6 Table 6 7 6 5 86 Random Address Read SMBus Packet Device Data Device S Address W 5 Address A 5 Address R A Data 111 1 7 bits 1 1 8 bits il 1 7 bits 1 1 8 bits 1 1 Byte Write SMBus Packet Device Data S Address W A Address A Data bs 1 7 bits 0 1 8 bits 8 bits 1 1 Thermal Sensing Device The Dual Core Intel Itanium processor 9000 9100 ser
125. t 5 Read Ack Address E P 1 0001 100 1 1 1001 1011 1 1 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 87 tel System Management Feature Specifications Table 6 13 Command Byte Bit Assignment Register Command Reset State Function RESERVED 00h N A Reserved for future use RRT 01 Read processor core thermal data RS 02h N A Read status byte flags busy signal RC 03h 0000 0000 Read configuration byte RCR 04h 0000 0010 Read conversion rate byte RESERVED 05h 0111 1111 Reserved for future use RESERVED 06h 1100 1001 Reserved for future use RRHL 07h 0111 1111 Read processor core thermal diode TuiGn limit RRLL 08h 1100 1001 Read processor core thermal diode T ow limit WC 09h N A Write configuration byte WCR OAh N A Write conversion rate byte RESERVED OBh N A Reserved for future use RESERVED OCh N A Reserved for future use WRHL 0Dh N A Write processor core thermal diode Ty Gy limit WRLL OEh N A Write processor core thermal diode ow limit OSHT OFh N A One shot command use send byte packet RESERVED 10h FFh N A Reserved for future use All of the commands are for reading or writing registers in the thermal sensor except the one shot command OSHT The one shot command forces the immediate start of a new voltage to temperature conversion cycle If a conversion is in progress
126. t 2002 2007 Intel Corporation Other names and brands be claimed as the property of others 12 is two wire communication bus protocol developed by Phillips SMBus is a subset of the 2 bus protocol developed by Intel Implementation of the 12C bus protocol or the SMBus bus protocol may require licenses from various entities including Phillips Electronics N V and North American Phillips Corporation 2 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Contents 1 LINEKOODUCHON X Em 11 TL OVERVIEW MELDE 11 1 2 Processor Abstraction ease e oca neve EEE EEE LESER rx de E sra 11 1 3 Mixing Processors of Different Frequencies and Cache Sizes 2 12 12 12 1 5 State ust ean 12 1 6 Reference DOCUFPentsS 13 2 Electrical Specifications nor o e PER Sto aa eu RR RIDERE Medea 15 2 1 Dual Core Intel Itanium Processor 9000 and 9100 Series System 15 2 1 1 System Bus Power Pins 15 2 1 2 System BUS ER KA 15 2 2 System BUS Sigrials 15 2 2 1 Signal 15 2 2 2 Signal Descriptions iie dt 17 2 3 Packag
127. tem management interface signals and their descriptions These signals are used by the system to access the system management components via the SMBus System Management I nterface Signal Descriptions Signal Name Pin Count Description 3 3V 1 Voltage supply for EEPROMs and thermal sensor SMA 2 0 3 Address select passed through from socket SMSC 1 System management bus clock SMSD 1 System management serial address data bus SMWP 1 Scratch EEPROM write protect THRMALERT 1 Temperature alert from the thermal sensor Figure 6 1 shows the logical schematics of SMBus circuitry on the processor and shows how the various system management components are connected to the SMBus The reference to the System Board at the lower left corner of Figure 6 1 shows how SMBus address configuration for multiple processors can be realized with resistor stuffing options Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 79 intel System Management Feature Specifications Figure 6 1 Logical Schematic of SMBus Circuitry ntel Itanium 2 Processor 3 3V EE 10K 10K 10K THERMDA Voc THERMDC A0 processor SC E A2 SD i STBY D 0 Thermal 5 Sens
128. that this is BCLKn or BCLKp signal Configuration signals other than 21 17 must be asserted 4 BCLKs prior to the deasserted edge of RESET and must remain valid for 2 BCLKs minimum to 3 BCLKs maximum after the deasserted edge of RESET 4 Figure 2 5 outlines the timing relationship between the configuration pins RESET PWRGOOD for cold reset Figure 2 5 System Bus Reset and Configuration Timings for Cold Reset t t Lt t t t t PWRGOOD RESET epee SS contain TM 1 15 minimum set up time to BCLK for deassertion edge of RESET 1 ms minimum for cold reset Bus ratio signals must be asserted no later than Tp 2 BCLKs minimum 3 BCLKs maximum 4 BCLKs minimum 2 BCLKs minimum BCLKs maximum 0008590 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 31 intel Electrical Specifications Warm Reset Sequence PWRGOOD remains high throughout the entire sequence as power is already available and stable to the processor The configuration pins A 21 17 must be asserted the entire time RESET is asserted The duration from the assertion of RESET to the deassertion of RESET must be 1 millisecond minimum After RESET is deasserted the configuration pins must remain valid for two BCLKs minimum to three BCLKs maximum BCLK is shown as a time reference to the BCLK period It is not a requireme
129. the target to indicate that it is ready to receive a write or implicit writeback data transfer TRST 1 The Reset TRST signal is an IEEE 1149 1 compliant support signal used by debug tools WSNP 1 O The Write Snoop WSNP signal indicates that snooping agents will snoop the memory write transaction Signal Summaries Table A 12 through Table A 15 list attributes of the processor output input and 1 0 signals Output Signals Name Active Level Clock Signal Group CPUPRES Low Platform DBSY C1 Low BCLKp Data DBSY C24 Low BCLKp Data DRDY C1 Low BCLKp Data DRDY C24 Low BCLKp Data FERR Low Asynchronous PC Compatibility ERR Mode SBSY C1 Low BCLKp Data SBSY C24 Low BCLKp Data TDO High TCK TAP THRMTRIP Low Asynchronous Error THRMALERT Low Asynchronous Error Input Signals Sheet 1 of 2 Name Active Level Clock Signal Group Qualified BPRI Low BCLKp Arbitration Always BR1 Low BCLKp Arbitration Always BR2 Low BCLKp Arbitration Always BR3 Low BCLKp Arbitration Always BCLKp High Control Always BCLKn High Control Always D C Low BCLKp System Bus Request Phase Mem Rd DEFER Low BCLKp Snoop Snoop Phase DHIT Low BCLKp System Bus 105 1 GSEQ Low BCLKp Snoop Snoop Phase 105 intel Table A 13 Input Signals Sheet 2 of 2 Signals Reference
130. tions Package Specifications Table 2 3 through Table 2 9 list the DC voltage current and power specifications for the processor The voltage and current specifications are defined at the processor pins Operational specifications listed in Table 2 3 through Table 2 9 are only valid while meeting specifications for case temperature clock frequency and input voltages Processor Package Specifications Symbol Parameter Core Minimum Typ Maximum Unit Notes requency Vcore PS Vcc from the Voltage A VID 17 mV VID VID 17 mV V 1 Regulator Veache PS Vcache from the Voltage A VID 17 mV VID VID 17 mV V 2 Regulator Vtixed Vfixed from the Voltage A 1 25 20 mV 1 25 1 25 20 mV V Regulator VCTERM Termination Voltage A 1 2 1 596 1 2 1 241 596 V Recommended Termination A 45 15 45 45 15 Ohm Resistance Test Access Port Voltage A 1 2 1 5 1 2 1 5 V VCCrap core PS Core Current Required from A 2 8 89 121 A Power Supply cache PS Cache Current Required from A 2 0 17 18 A Power Supply I fixed PS Fixed Current Required from A 0 7 9 2 11 A Power Supply Termination Voltage Current A 7 2 A 4 PS r Power Supply Slew Rate for A 0 05 A ns the Termination Voltage at the Processor Pins PWRmax Max Power A 177 w 5 Thermal Power Envelope A 130 w PWRrpp Thermal Design Power dual A 104 w B
131. to rise to critical levels the processor will assert Power Trip or Thermal Trip The ETM feature may be disabled through the PAL Power Trip The Dual Core Intel Itanium processor 9000 and 9100 series protects itself and the MVR from catastrophic over power by use of an internal power sensor The sensor trip point is set above the normal operating power to ensure that there are no false trips The processor will signal a continuable MCA when the power draw exceeds a safe operating level Data will be lost if the MVR overheats and shuts down as a result of an extended over power condition Once power trip is activated the processor can continue operation but may continue to signal continuable MCAs as long as the over power condition exists Thermal Trip The Dual Core Intel Itanium processor 9000 and 9100 series protects itself from catastrophic overheating by use of an internal thermal sensor The sensor trip point is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds a safe operating level Data will be lost if the processor goes into thermal trip signaled to the system by the THRMTRIP Once thermal trip is activated the processor remains stopped until RESET is asserted The processor case temperature must drop below the specified maximum before issuing a reset to the processor Please see Section 5 2 for details
132. ure Specifications The Dual Core Intel Itanium processor 9000 and 9100 series includes a system management bus SMBus interface This chapter describes the features of the SMBus and SMBus components System Management Bus System Management Bus Interface The processor includes an Itanium processor family SMBus interface which allows access to several processor features The system management components on the processor include two memory components EEPROMs and a thermal sensing device digital thermometer The processor information EEPROM PIROM is programmed by Intel with manufacturing and feature information specific to the Dual Core Intel Itanium processor 9000 and 9100 series This information is permanently write protected Section 6 2 provides details on the PIROM The other EEPROM is a scratch EEPROM that is available for other data at the system vendor s discretion The thermal sensor can be used in conjunction with the information in the PIROM and or the Scratch EEPROM for system thermal monitoring and management The thermal sensing device on the processor provides an accurate means of acquiring an indicator of the junction temperature of the processor core die The thermal sensing device is connected to the anode and cathode of the processor on die thermal diode SMBus implementation on the processor uses the clock and data signals as defined by SMBus specifications System Management nterface Signals Table 6 1 lists the sys
133. ute Overshoot Undershoot Tolerance 25 Source Synchronous AGTL Signal Group Time Dependent Overshoot Undershoot Tolerance for 400 2 System BUS 26 Wired OR Signal Group BINIT HIT HITM BNR TND BERR Overshoot Undershoot Tolerance for 400 MHz System 26 Source Synchronous AGTL Signal Group Time Dependent Overshoot Undershoot Tolerance for 533 2 System BUS 26 Wired OR Signal Group BINIT HIT HITM BNR BERR Overshoot Undershoot Tolerance for 533 MHz System 27 VR Connector Signals 27 Power Connector Pinouts rennen nnns 28 Processors Core Voltage Identification Code VCORE and 30 Connection for Unused 44444 4 44 nennen 33 TUNER1 TUNER3 Translation 1 34 Pin Signal Information Sorted by Pin 0202222 36 Pin Signal Information Sorted by Pin 2 50 Processor Package Dimensions
134. wer is applied to the processor and resets itself at power up The thermal sensing device also contains alarm registers to store thermal reference threshold data These values can be individually programmed on the thermal sensor If the measured temperature equals or exceeds the alarm threshold value the appropriate bit is set in the thermal sensing device status register which is also brought out to the processor system bus via the THRMALERT signal see Section 6 1 1 for more details At power up the appropriate alarm register values need to be programmed into the thermal sensing device via the SMBus It is recommended that the upper thermal reference threshold byte provided in the processor information ROM be used for setting the upper threshold value in the alarm register To account for the offset inherent in the thermal sensing device reading the actual programmed value of the upper threshold value in the alarm register should be the sum of the upper thermal reference threshold byte and the thermal calibration offset byte both provided in the PIROM When polling the thermal sensing device on the processor to read the processor temperatures it is recommended that the polling frequency be every 0 5 to 1 second Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet e System Management Feature Specifications n te D 6 6 Table 6 8 Table 6 9 Table 6 10 Table 6 11 Table 6 12 Thermal Sensing Device
135. when the one shot command is received then the command is ignored If the thermal sensing device is in standby mode when the one shot command is received a conversion is performed and the sensor returns to standby mode If the thermal sensor is in auto convert mode and is between conversions then the conversion rate timer resets and the next automatic conversion takes place after a full delay elapses Please refer to Section 6 7 4 for further detail on standby and auto convert modes The default command after reset is the reserved value 00h After reset receive byte packets will return invalid data until another command is sent to the thermal sensing device 6 7 Thermal Sensing Device Registers The system management software can configure and control the thermal sensor by writing to and interacting with different registers in the thermal sensor These registers include a thermal reference register two thermal limit registers a status register a configuration register a conversion rate register and other reserved registers The following subsections describe the registers in detail 6 7 1 Thermal Reference Registers The processor core and thermal sensing device internal thermal reference registers contain the thermal reference value of the thermal sensing device and the processor core thermal diodes This value ranges from 127 to 128 decimal and is expressed as a two s complement eight bit number These registers are saturating t

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