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Samsung M393B5670EH1-CF8 memory module

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2. 133 35 0 15 Is C S 128 95 8 Max 4 0 32 40 A 18 93 9 74 PA SJ V C m LE LN y re S p p o 2 o Oo E 2 1 Lu Q 2 50 8 amp 1 0 max A N r me 54 675 2d A B 1 27 0 10 P 47 00 k 71 00 gt O W O 5 00 S 0 80 0 05 H 1 1 eo Ww As s y l 3 80 MIB 0 2
3. 133 35 0 15 lt 128 95 c lt gt gt Max 4 0 9 76 3 1802 32 40 18 93 974 X s 1 1 1 C LE L re 2 B o 5 H Q D 3 d e i LT OI I Y 2 50 g amp 1 0 max CN N 54 675 A B 1 27 0 10 x U 47 00 A 71 00 O UO O q 2 0 80 0 05 H 1 1 eo Ww ES y l 3 80 MIB 0 2 0 15 i 10 9 0 4 le 1 50 dE 4 1 50 0 10 0 eS Detail A Detail B Detail C 19 4 1 x72 DIMM pop
4. 133 35 0 15 lt C 8 128 95 E gt Ss Max 4 0 9 76 10 9 18 92 32 40 18 93 9 74 x lt lt gt mi e X A d E 4 g r1 H E 2 8 P c e ud e 1 2 50 e S 1 0 max N i m 54 675 P 1 27 0 10 A B 47 00 2 ES 71 00 j Oo X o 8 2 E 0 80 0 05 1 1 Q i A 1 Y 3 80 MIB 0 2 0 15 10 9 0 4 1 UO 7 izao 4 1 00 F 1 50 0 10 i Detail A Detail B Detail C 19 1 1 x72 DIMM populated as one physical rank of x8
5. 133 35 0 15 lt P 12999 ES 1 Max 4 0 a 976 1091892 n 32 40 4 9 74 L 4 uml r lo o d s L d 1 o o e E 8 e NE A 2 50 S 8 1 0 max N N a x 54 675 A B 47 00 mI i zii j 1 27 0 10 O O q 200 0 80 0 05 H 1 1 Q 7 A l 3 80 T MIB 0 2 0 15 ae 109 04 0 amp e 1 50 0 10 0 eS Detail A Detail B Detail C 19 2 1 x72 DIMM populated as two physical ranks of x8 DDR3 SDRAMs O IU O C 2x 2 10 0 15 d F B J d b d b Lymm d d d Lt J a O O LC O Address Command and Control lines The used device is 128M x8 DDR3 SDRAM FBGA DDR3 SDRAM Part NO K4B1G0846E HC Note Tolerances on all dimensions 0 15 unless otherwise specified IO Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 19 3 256Mbx4 based 256Mx72 Module 1 Rank M393B5670EH1 Units
6. lt a ac c mm cn en omo SE LES nA SETE SZ gieSs 55025 ess 585023 Peer sa elelelr dla ce c n LLIELITI LL ILI TIL DQS8 w Das za DQS17 w bas za pass bas za DQS17 w Das za Dass DQS i s DQS17 w DQS s Dass DQS S E DQS17 w DQS g E vss DM Zz vss DM Zz vss DM gt vss DM CB 3 0 DQ 3 0 D3 T cgp7 41 A DQIS Q Dif X pols5 321 DOI3 0 D4 T 3 Da 39 36 DQ 5 0 D13 T 3 E aj gt gj gt E gt eo eo eo eo iu m iu Qn i es m Dn SE Ul xc Oz Ll ee x Oz Wie oz uxxxaz AERE 5502 lasse Sos 8 8 88 PHRES l os v v t La gt DQS3 w DAS ZQ DQS17 w j DQS za DQS8 w DOS za DQS17 w j DQS za DQS3 w DQS e DQS17 DQS e DQS8 DQS e DQS17 w DQS e vss DM D3 e vss DM D12 zl vss DM D5 zi vss DM D14 zi Dal27 24 W DQ 3 0 DQ 31 28 PQI3 0 8 Dol43 40 PQI3 0 3 Do47 44 W PQI3 0 E 2 eo 2 eo ii ms iis mh ues Qin ee We Yaz Weer ad wxxxazZ uxxxaz PERE Ss8s PRHE SIS88 g os
7. gt gt gt gt gt bd bd bd bd d d gt gt gt gt gt o NIva fo NIv Io NIvg o NIv o Nlva lo Nlv o N va lo Nlv oNjvaO NIv 1qo 1qo 1qo ao 1qo 3x9 30 390 3X0 3x9 o 9 q X2 a 2 o 9 co 3 A x A x A yO A x lt X A m A m A m A m A m _ SVo _ SVo Svo SS _ SVo Q SVa Q SVa Q SVa Q SVa Q SVa _ 2 _ 2 Qn _ 2 Qo eo osa 2 gg 2 gag 2 ggag 2 osa 2 NAAA Nalaaa Nalaaa N I N IQ gt gt gt gt gt Io NIva fo NIv Io NIvg fo NIv o Nlva lo Nlv o N va lo Nlv o N va fo Nlv 1do 1do 1do 1qo 1do MO 390 390 30 3o z 22 gt w 3 o 3 o 9 A I A I A o CN o X d Oo sw He A m O ame O ame Oo ame Svo e MESUS Svo e Svo e Svo je S SVY e 3 S S SVY e 3 SVY e S SVY o gag 2 ggz 2 g3Bzg 9 goIo 9 2 gag 2 NOOOGO Nalaaa Nalaqa NOAOA NAAAA QQO OO T 0 OR CD gt gt gt gt gt gt gt QIG B8 8 88 B BB 8 88 2 aa7 e g g g e a
8. 133 35 0 15 lt 128 95 A 3 Max 4 0 Ie 976 108 118 92 n 32 40 4 9 74 ie Em el H s 3 L T 2 D o X amp NE A 2 50 amp amp 1 0 max N N a 54 675 A B 47 00 MI n zii j 1 27 0 10 O O q 200 0 80 0 05 H 1 1 Q i A 1 Y i l 3 80 MIB 0 2 0 15 ae i 10 9 0 4 Azo o amp 1 50 0 10 0 eS Detail A Detail B Detail C 19 3 1 x72 DIMM populated as one physical rank of x4 DDR3 SDRAMs O U O E C 2x 2 10 0 15 J B J d d b LISL d d d Lt B a O N O Address Command and Control lines The used device is 256M x4 DDR3 SDRAM FBGA DDR3 SDRAM Part NO KAB1G0446E HC Note Tolerances on all dimensions 0 15 unless otherwise specified MEE Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 19 4 256Mbx4 based 512Mx72 Module 2 Ranks M393B5170EH1 Units Millimeters
9. 133 35 x 0 15 mj gt C 128 95 e Max 4 0 32 40 A 18 93 4 9 74 PA SJ V C ni TF 3 E m 5 z 8 LT A 2 50 amp 1 0 max N N me 54 675 A B aon ES kx Wins 1 27 0 10 O W O S J C X 500 S 0 80 0 05 H 1 1 Q ze Qi l 3 80 T MIB 0 2 0 15 i 10 9 0 4 k T 1 z50 e 4 1 50 0 10 00 eS Detail A Detail B Detail C 19 6 1 x72 DIMM populated as four physical ranks of x4 DDR3 SDRAMs O U O Ei M I 5 Ef 2x 2 10 0 15 D p rsd E H Ho H H HH H th 4 H H HH HH H HR e J m L D 7H HH H RU YH YE o O N O Address Command and Control lines The used device is 512M x4 DDP DDR3 SDRAM FBGA DDR3 SDRAM Part NO K4B2G0446E MC Note Tolerances on all dimensions 0 15 unless otherwise specified nibns Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 19 6 2 Heat Spreader Design Guide 1 FRONT PART Outside 133 15 x 0 2 pe 130 45 x 0 15 0 65 0 2 2 9 26 29 77 gt 31 4 rs F E T a i o 1 U E ww B N eS al
10. Measured Description Defined by From To Von AC VoL AC Single ended output slew rate for rising edge Voi AC Von AC von AC VoL AC Delta TRse Von AC VoL AC Single ended output slew rate for falling edge Von AC Voi AC Von AC VoL AC _ Delta TFse Note Output slew rate is verified by design and characterization and may not be subject to production test Single Ended Output slew rate DDR3 1066 DDR3 1333 1 Parameter Symbol Units Min Max Min Max Single ended output slew rate SRQse 2 5 5 2 5 5 Vins Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Singe ended Signals For Ron RZQ 7 setting VoH AC Vit VoLAc delta TFse delta TRse Figure 6 Single Ended Output Slew Rate definition 2Bof 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 14 4 Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo qig AC and Vonairt AC for differential signals as shown in below Differential Output slew rate definition Measured Description Defined by From To VoHd AC Voudif AC Differential output slew rate for rising edge Voudi AC Vougit AC onair C oa Delta TRdiff Voggait AC Vo ai AC Differential output slew rate for falling edge Vouair AC VoLaif AC oni AS Lait Delta TFdiff No
11. Organization Row Address Column Address Bank Address Auto Precharge 256x4 1Gb based Module A0 A13 A0 A9 A11 BAO BA2 A10 AP 128x8 1Gb based Module A0 A13 A0 A9 BA0 BA2 A10 AP 512x4 2Gb DDP based Module A0 A13 A0 A9 A11 BAO BA2 A10 AP 2993 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 4 0 Registered DIMM Pin Configurations Front side Back side Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back NC DQS17 1 VREFDQ 121 Vss 42 DQS8 162 5QS17 82 DQ33 202 Vss DM4 DQS13 2 Vss 122 DQ4 43 DQS8 163 Vss 83 Vss 203 TDQS13 NC DQS13 3 DQO 123 DQ5 44 Vss 164 CB6 NC 84 DQS4 204 Thas13 4 DQ1 124 Vss 45 CB2 NC 165 CB7 NC 85 DQS4 205 Vss DM0 DQS9 5 Vss 125 TDQS9 46 CB3 NC 166 Vss 86 Vss 206 DQ38 6 DQSO 126 No MGSS 47 Vss 167 NC TEST 87 DQ34 207 DQ39 TDQS9 7 DQSO 127 Vss 48 Vrr NC 168 RESET 88 DQ35 208 Vss 8 Vss 128 DQ6 KEY 89 Vss 209 DQ44 9 DQ2 129 DQ7 49 Vrr NC 169 CKE1 NC 90 DQ40 210 DQ45 10 DQ3 130 Vss 50 CKE0 170 Vpp 91 DQ41 211 Vss DM5 DQS14 11 Vss 131 DQ12 51 Vpp 171 A15 92 Vss 212 TDQS14 NC DQS14 12 DQ8 132 DQ13 52 BA2 172 A14 93 DQS5 213 5QS14 13 DQ9 133 Vss 53 Err Out NC 173 Vpp 94 DQS5 214 Vss DM1 DQS10 14 Vss 134 TDQS10 54 Vpp 174 A12 BC 95 Vss 215 DQ46 NC DQS10 15 DQS1 135 5Qs1o 55 A11 175 A9 96 DQ42 216 DQ47 16 DQS1
12. gt gt bd bd bd bd gt gt o Njva O NIV o Nlvg o NIv 1qo 1qo 30 ayo NO NO A 0 xW A m A am _ SVo Svo Q SVa Q Sva peA ies asa 2 aSBzg 2 xNalaaa Nalaga gt gt Io NIvg fo NIv Io Nlvg Do NIv 1do 1do 390 390 No 9 o y e lt X A am A am Svo re Svo re O SWH te O SVd te Qo 2 so NIN _ so gQooao gt goaoszo vNalaaa vNalaaa 0 c 0 t 2 alg gt gt alg 29 ala g ala g S a Vtt Rev 1 06 July 2009 17 of 53 ELECTRONICS DDR3 SDRAM Registered DIMM adn VI Odd vesud vio Nivaua vio Nivug VL1qOdd V0 yOdd VO Ogd vOxoda V Add vsvoud VSVadd VS adn VI OdV VLSdV VIO NlvgaV VIO NIvav VOLGONV VO3XOuV VOMOdV vOxodv V3MWHv VSVoSV VSVaaV VO0SdV
13. eeeeeeeeeeeeeee nennen nennen nnn nnn nnn 22 13 0 AC amp DC Input Measurement Levels nanan 23 13 1 AC amp DC Logic Input Levels for Single ended Signals eeeeeeee essen eene enne nnne nnn 23 QRPATUTEDIICDI I Ae 24 13 3 AC and DC Logic Input Levels for Differential Signals cccccsceeeeeeeeeeeeeeeeeeeeseueueueueneneneneenenenenee 25 13 3 1 Differential Signals Definition eeeeeeeeeeeeee eene nnnm nnnm nennen nnm nnne he nhan nnn nnne nene 25 13 3 2 Differential Swing Requirement for Clock CK CK and Strobe DQS DQS LPC 25 13 3 3 Single ended Requirements for Differential Signals cesse scenes eene nennen nennen nnn 26 13 3 4 Differential Input Cross Point Voltage uuu 27 13 4 Slew Rate Definition for Single Ended Input Signals cessere enne nnn 27 13 5 Slew Rate Definition for Differential Input Signals ceeeeeeeeeeeeeeeenenen nemen nnn nnn nnn 27 14 0 AC and DC Output Measurement Levels rr 28 14 1 Single Ended AC and DC Output Levels eeeeeeeeeeee eene nennen nennen nnn nnn nnne nnn nnn nnn nnn 28 14 2 Differential AC and DC Output Levels eeeeeee nennen nnne nnn nnn n nnn n nns a snas a uasa ansa nnmnnn nennen 28 aoe Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 14 3 Single Ended Output Slew Rate
14. eeeeseee esses eene enne nnn nnn n nnne nnn nnn nnn nns n nnne n nnn n nnn nnne 28 14 4 Differential Output Slew Rate mee 29 15 0 IDD specification definition Lanna 30 15 1 IDD SPEC Table EEE EE 32 16 0 Input Output Capacitance ecc 35 17 0 Electrical Characteristics and AC timing eee 36 17 1 Refresh Parameters by Device Density eeeeeeeeee eese nennen nennen nnn nnn nnne nnn nnn nnn nnn nnn nnne 36 17 2 Speed Bins and CL tRCD tRC and tRAS for Corresponding Bin eene nennen nn 36 17 3 Speed Bins and CL tRCD tRP tRC and tRAS for corresponding Bin 37 17 3 1 Speel IT 38 18 0 Timing Parameters for DDR3 800 DDR3 1066 and DDR3 1333 csse 39 EAS drei MN 42 18 2 Timing PNGIMNBIIG NO 43 19 0 Physical Dimensions ec 44 19 1 128Mbx8 based 128Mx72 Module 1 Rank M393B2873EH1 44 19 1 1 x72 DIMM populated as one physical rank of x8 DDR3 SDRAMS eene 44 19 2 128Mbx8 based 256Mx72 Module 2 Ranks M393B5673EH1 45 19 2 1 x72 DIMM populated as two physical ranks of x8 DDR3 SDRAMS eee 45 19 3 256Mbx4 based 256Mx72 Module 1 Rank M393B5670EH1 46 19 3 1 x72 DIMM populated as one physical rank of x4 DDR3 SDRAMS eee 46 19 4 256Mbx4 based 512Mx72 Module 2 Ranks M393B517
15. Speed DDR3 800 CL nRCD nRP 6 6 6 Units Note Parameter Symbol min max Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 ns PRE command period tRP 15 ns ACT to ACT or REF command period tRC 52 5 ns ACT to PRE command period tRAS 37 5 9 tREFI ns 8 CL 6 CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 Supported CL Settings nCK Supported CWL Settings 5 nCK DDR3 1066 Speed Bins Speed DDR3 1066 CL nRCD nRP 7 7 7 Units Note Parameter Symbol min max Internal read command to first data tAA 13 125 20 ns ACT to internal read or write delay time tRCD 13 125 ns PRE command period tRP 13 125 ns ACT to ACT or REF command period tRC 50 625 ns ACT to PRE command period tRAS 37 5 9 tREFI ns 8 6 CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 6 CWL 6 tCK AVG Reserved ns 1 2 3 4 DE CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 4 m CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 Supported CL Settings 6 7 8 nCK Supported CWL Settings 5 6 nCK 37 of 53 ELECTRONICS Rev 1 06 July 2009 Registered DIMM DDR3 SDRAM DDR3 1333 Speed Bins Speed DDR3 1333 CL nRCD nRP 9 9 9 Units Note Parameter Symbol min max Internal read command to first data tAA 13 5 13 125 59 20 ns ACT to internal read or write delay time tRCD 13 5 13 125 59 ns PRE command period tRP 13
16. o o A 2 i IS l d e N a 127 0 12 il Al CN 1 3 8 amp H SSS Sam 4 4 Inside e Green Line TIM Attach Line L p S9 pedestal line J 7 I i BM 80 78 lt al 119 29 jat 128 5 al 2 BACK PART Outside ES E Re Ec rle Dit DF Inside Green Line TIM Attach Line 52 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 3 CLIP PART 39 3 0 2 Upper Bending 29 77 Tilting Gap 0 1 0 3 T N E x TT SERE 3 Yi 3 5 5 X z gt 4 DDR3 RDIMM ASS Y View Reference thickness total Maximum 7 71 With Clip thickness 132 95 133 45 1 40 1 27 39 3 0 2 7 3 0 1 19 0 1 i Clip open size text mark D punch press stamp Rev 1 06 July 2009 53 of 53 ELECTRONICS
17. oe Ede E ee Ede sk i BAIN 0 w I RBA N O A gt BA N 0 SDRAMs D 3 0 D 12 8 D17 gn RBA N 0 B gt BA N 0 SDRAMs D 7 4 D 16 13 ti AIN 0 RAIN O A gt A N 0 SDRAMs D 3 0 D 12 8 D17 Ig RA N 0 B gt A N 0 SDRAMs D 7 4 D 16 13 vit RAS w RRASA gt RAS SDRAMs D 3 0 D 12 8 D17 NE RRASB gt RAS SDRAMs D 7 4 D 16 13 CAS w RCASA gt CAS SDRAMs D 3 0 D 12 8 D17 m 12 RCASB gt CAS SDRAMs D 7 4 D 16 13 Thermal sensor with SPD VppsPD Serial PD WE w R RWEA gt WE SDRAMs D 3 0 D 12 8 D17 SCL E RWEB gt WE SDRAMs D 7 4 D 16 13 EVENT TuS IK SDA Vpp DO D17 CKEO w G RCkKEOA gt CKE0 SDRAMs D 3 0 D 12 8 D17 A0 A1 A2 Va I y RCKEOB gt CKE0 SDRAMs D 7 4 D 16 13 ODTO w 4 RODTOA gt ODTO SDRAMs D 3 0 D 12 8 D17 SA0 SA1 SA2 VREFCA DO D17 E RODTOB gt ODTO SDRAMs D 7 4 D 16 13 R VREFDQ DO D17 E cko J Ves b i PCKOA gt CK SDRAMs D 3 0 D 12 8 D17 s PCKOB gt CK SDRAMs D 7 4 D 16 13 CKO I PCKOA gt CK SDRAMs D 3 0 D 12 8 D17 Note PCKOB gt CK SDRAMs D 7 4 D 16 13 1 DQ to I O wiring may be changed within a nibble PAR IN QERE Er oui 2 Unless otherwise noted resistor values are 1502 596 RESET RST
18. Speed DDR3 800 DDR3 1066 DDR3 1333 Units Note Parameter Symbol MIN MAX MIN MAX MIN MAX Command and Address Timing DLL locking time tDLLK 512 512 512 nCK internal READ Command to PRECHARGE Command tRTP max _ max _ max delay 4nCK 7 5ns 4nCK 7 5ns 4nCK 7 5ns Delay from start of internal write transaction to internal WTR max max _ max _ e 18 read command 4nCK 7 5ns 4nCK 7 5ns 4nCK 7 5ns WRITE recovery time tWR 15 15 15 ns e Mode Register Set command cycle time tMRD 4 4 4 nCK Mode Register Set command update delay MOD 12nCK 4 5ns 12nCK 1 5ns 2nCK1 5ns CAS to CAS command delay CCD 4 4 4 nCK Auto precharge write recovery precharge time tDAL min WR roundup tRP tCK AVG nCK Multi Purpose Register Recovery Time tMPRR 1 1 1 nCK 22 ACTIVE to PRECHARGE command period RAS See 13 3 Speed Bins and CL tRCD tRP tRC and tRAS for corresponding Bin on page 37 ns e ACTIVE to ACTIVE command period for 1KB page size tRRD AnCK 10ns AnCK 7 5ns 4nCK 6ns e ACTIVE to ACTIVE command period for 2KB pagesize tRRD 4n CK 10ns 7 4nCK 10ns i BECK T 5ns e Four activate window for 1KB page size FAW 40 37 5 30 ns e Four activate window for 2KB page size FAW 50 50 45 ns e Ene VACII N AOE Sipas 200 125 65 ps b 16 waco MASS 275 200 140 ps b 16 oe ET ssetas ps pez Control amp Address Input pulse width for each input PW 900 780 620 ps 28 C
19. nu m Wk gt wH We Wee oZ e Wie lt OZ Wie voz Wee x az OIIOI olooo OlrloE OO o oO q OlFIOIS olo o OIIOI OIO O BEsesss Se Bese s Besess 582 iets milll L L b Vtt Vt Ww Option 1 I Option 2 I Option 3 Serial PD Integrated Thermal sensor in SPD Serial PD SCL SCL gt SCL gt SDA EVENT EVENT SDA SDA WP A0 A1 A2 AO A1 A2 WP A0 A1 A2 L SAO SA1 SA2 SAO SA1 SA2 l SAO SA1 SA2 Thermal sensor Serial PD w integrated Thermal sensor 1 Serial PD no Thermal sensor SCL EVENT EVENT SDA A0 A1 A2 RS0A gt CS0 SDRAMs D 3 0 D 12 0 D17 Vppspp Serial PD 80 Ww RS0B gt C80 SDRAMs DJ 7 4 D 16 13 SAO SA1 SA2 nz 8 we RS1A gt CS1 SDRAMs D 21 18 D 30 26 D35 Vpp D0 D35 RS1B gt CS1 SDRAMs D 25 22 D 34 31 Serial PD w stand alone Thermal sensor RBA N 0 A gt BA N 0 SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 1 Vor BAIN O RBA N 0 B gt BA N 0 SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 RAIN OJA gt A N 0 SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 VREFCA 4 D0 D35 AIN 0 W RA N 0 B gt AIN 0 SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 RS s RRASA gt RAS SDRAMs D 3 0 D 12 8 D 21 17 D 30 26 D35 VREFDO x DO
20. VSEH Vpp 2 or Vppo 2 CK or DOS VsEL max VsEL Vss or Vssa time Figure 3 Single ended requirement for differential signals Note that while ADD CMD and DQ signal requirements are with respect to VsEr the single ended components of differential signals have a requirement with respect to Vpp 2 this is nominally the same The transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach Vsg max VsEnmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU Symbol Parameter Min BDRM I Max Unit Notes Vsen Single ended high level for strobes Vpp 2 0 175 Note3 V 1 Single ended high level for CK CK Vpp 2 0 175 Note3 V 1 Va Single ended low level for strobes Note3 Vpp 2 0 175 V 1 Single ended low level for CK CK Note3 Vpp 2 0 175 V 1 Notes 1 For CK CK use Vj Vii AC of ADD CMD for strobes DQS DQS DQSL DQSL DQSU DQSU use Vin ViL AC of DQs 2 VI AC IVi AC for DQs is based on Vggepo Viu AC Vi AC for ADD CMD is based on VREFca if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here E 3 These values are not defined however they single ended signals CK CK DQS DQS DQSL D
21. 3 See the wiring diagrams for all resistors associated with the command address and control bus 4 ZQ resistors are 240Q 1 For all other resistor values refer to the appropriate wiring diagram PST SDRAMs D 17 0 S 3 2 CKE1 ODT1 CK1 and CK1 are NC Unused register inputs ODT1 and CKE1 have a 330 Q resistor to ground ELECTRONICS 13 of 53 Rev 1 06 July 2009 Registered DIMM DDR3 SDRAM 10 4 4GB 512Mx72 Module Populated as 2 ranks of x4 DDR3 SDRAMs zx E x ZZ lt lt 389E 2 lt ELE STESS a gai ols lt u xx vases Ylexa oz ele ears Yl lt a orozsoooozxz OOOO oroszsoooozx OOOO RIED ED Co sa E ala x l aa dc ac a ala oom LILLLILLI Litt LIII I IIiI Litt DQS17 w Das E DQS DQS17 DAS E DQS E DQS17 w DQS Zz DQS DQS17 w j DQS Zz Das 2 VSS DM T DM Ed VSS w4 DM T DM Ed CB 7 4 DQ 3 0 Di DQ 3 0 D35 a CB 3 0 A DQ 3 0 DS amp DQ 3 0 D25 m Dui ce Y5 Gwe tbe ou x52 ou x52 lesse sss asd ssss las ses5ssot lasse SSSSF DQS12 DQS E DQS S DQS12 A DQS E DQS is DQS12 w Das Z DQS Z DQS12 w DQS Zz Das Zz VSS DM T DM T VSS w4 DM lt DM Ed DQ 31 28 A DQ 3 0 pus E DQ 3 0
22. D35 RRASB gt RAS SDRAMs D 7 4 D 16 13 D 25 22 D 34 31 a CAS RCASA gt CAS SDRAMs D 4 0 D8 D 13 9 D 22 18 D 31 27 Vss DO D35 RCASB gt CAS SDRAMs DI8 5 D 17 14 D 26 23 D 35 32 WE 12 RWEA gt WE SDRAMs D 4 0 D8 D 13 9 D 22 18 D 31 27 R RWEB gt WE SDRAMs DJ8 5 D 17 14 D 26 23 D 35 32 RCKEOA gt CKE0 SDRAMs D 3 0 D 12 8 D17 SE i a RCKEOB gt CKE0 SDRAMs D 7 4 D 16 13 RCKE1A gt CKE1 SDRAMs D 21 18 D 30 26 D35 Notes m T ext S RCKEIB CKE1 SDRAMs D 25 22 D 34 31 1 DQ to I O wiring may be changed within a nibble mM M RODTOA gt ODTO SDRAMs D 3 0 D 12 8 D17 F Mi R RODTOB ODTO SDRAMs D 74 D 16 13 2 See wiring diagrams for resistor values on RODT1A gt ODT1 SDRAMs D 21 18 D 30 26 D35 3 ZQ pins of each SDRAM are connected to individual RZQ resistors 240 1 ohms RODTIB gt ODT SDRAMS Dize 771 041 Eko PCKOA gt CK SDRAMs D 3 0 D 12 8 D17 PCKOB gt CK SDRAMs D 7 4 D 16 13 i PCK1A gt CK SDRAMs D 21 18 D 30 26 D35 PCK1B gt CK SDRAMs D 25 22 D 34 31 KO PCKOA gt CK SDRAMs D 3 0 D 12 8 D17 PCKOB gt CK SDRAMs D 7 4 D 16 13 CK 06 PCK1A gt CK SDRAMs D 21 18 D 30 26 D35 ko 5394 PCK1B gt CK SDRAMs D 25 22 D 34 31 PAR IN ERR OUT RESET RST RST SDRAMs D 35 0 15 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRA
23. H SSS Sam 4 4 Inside e Green Line TIM Attach Line L p S9 pedestal line J 7 I i BM 80 78 lt al 119 29 jat 128 5 al 2 BACK PART Outside ES E Re Ec rle Dit DF Inside Green Line TIM Attach Line 48 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 3 CLIP PART 39 3 0 2 Upper Bending 29 77 Tilting Gap 0 1 0 3 a T N CT 1 a E 3 Yi Ben Ms 2 A d Q5 P i i 7 gt 4 DDR3 RDIMM ASS Y View Reference thickness total Maximum 7 55 With Clip thickness 132 95 x 133 45 el 1 05 1 27 39 3 0 2 19 x 0 1 1 Clip open size 2 5 3 6 text mark B or K punch press stamp gt Rev 1 06 July 2009 49 of 53 ELECTRONICS Registered DIMM DDR3 SDRAM 19 5 128Mbx8 based 512Mx72 Module 4 Ranks M393B5173EH1 Units Millimeters
24. D23 D25 s D63 D65 D67 D69 D71 T ARODTOB gt ODT1 SDRAMs D11 D13 D15 D17 T BRODT1B gt ODT1 SDRAMs D37 D39 D41 D43 E D29 D31 D33 D35 E D55 D57 D59 D61 CKO t R APCKOA gt CK SDRAMs D 9 0 CKO0 t 3 R BPCKOA CK SDRAMs D 53 44 APCKOB gt CK SDRAMs D 17 10 BPCKOB gt CK SDRAMs D 43 36 1200 A APCK1A gt CK SDRAMs D 27 18 S 1200 B BPCK1A gt CK SDRAMs D 71 62 APCK1B gt CK SDRAMs D 35 28 BPCK1B gt CK SDRAMs D 61 54 CK0 c APCKOA gt CK SDRAMs D 9 0 CK0 c BPCKOA gt CK SDRAMs D 53 44 APCKOB gt CK SDRAMs D 17 10 BPCKOB gt CK SDRAMs D 43 36 APCK1A gt CK SDRAMs D 27 18 BPCK1A gt CK SDRAMs D 71 62 CK1 NE APCK1B gt CK SDRAMs D 35 28 BPCK1B gt CK SDRAMs D 61 54 CK1 PAR_IN Err_out PAR_IN Err_out RESET RSTn RESET 1 RSTn PST SDRAMs D 71 0 21 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 11 0 Absolute Maximum Ratings 11 1 Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes Vpp Voltage on Vpp pin relative to Vss 0 4 V 1 975 V V 1 3 Vppo Voltage on Vppo pin relative to Vss 0 4 V 1 975 V V 1 3 Vin Vout Voltage on any pin relative to Vss 0 4 V 1 975 V V 1 TsTG Storage Temperature 55 to 100 C 1 2 Note 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only
25. De RESSS5 o EIME i T i i I i La e DQS3 w DQS DQS DQS5 w DQS DQS DQS3 A DQS S DQS S DQS5 DQS S DQS S DM3 DQS12 TIDAS p3 A TDGS p42 z DM5 DQS14 v TDQS p5 2 IDQS D14 A DQS12 w TDQS TDQS DQS14 w TDQS TDQS DQ 31 24 A DQ 7 0 DQ 7 0 Ly DQ 47 40 A DQI7 0 E LA DQ 0 S TEREE TEREE IE TEE u x Ez 8 SIS88 Bellz S56 Bisse sioe i 8 siSie S55 i 1 1 gt L2 e DQS2 w DQS DQS DQS6 w DOS DQS DQS2 w DAs E DQS ES DQS6 w DES S DQS DM27DQS11 TDOS p2 E TDOS p44 DM6 DQS15 Ww IDAS pe Zz TOS p5 Z DQS11 TDAS T TDQS lt DQS15 w TDQS TDQS DQI23 16 DQ 7 0 ee DQ 7 0 amp DQ 55 48 M DQ 7 0 DQ7 0 E Hasael uest aeae gO 88 BESE SSS ARERI Saisie sss B d j e i La DQS1 w DOS DQS DQS7 w Das DOS DQS1 w DQS E DQS S DQS7 w pQS es DQS 5 DM1 DQS10 TDQS p4 E TDGS p10 z DM7 DQS16 TDQS p7 2 IDQS p46 2i DQS10 TDQS lt TDQS a DQS16 TDQS lt TDQS ES DQ 15 8 A DQ 7 0 DQ 7 0 DQI63 56 Ww DQI7 0 E DQ 7 0 ZQ Inn WES ZQ ioo we gt ZQ oo Wks ZQ ioo wes n Weer ad Wee vad wxxxaz W ie SOZ i esset Bells 51S 69 amp BESES oos lale sls SSS os L4 e DQS0 w 4 DQS DQS Mit DQS0 w DAS S DQS Si DMO DQS9 A TDQS po 2 TDQS pg z DQS9 A TDQS
26. RST RST SDRAMs D 35 0 Vtt g e z gE z Thermal sensor with SPD 8 5 5 8 z SIS 5 8 y Sis 5 8 AIEE Ec Le spa SSE sa SS Bspis EVENT 7 EVENT UL AO BSS es BSISYE DQS4 w pas OO pas OO SAO SA1 SA2 DQS4 DES US DQS MA Vppspp Serial PD DQ 39 32 DQ 7 0 DQI7 0 T l l a ZQ ZQ Vpp D0 D35 Vit m 6 6575 85626 DQS5 Ww pas 210 DQS S e VREFCA DO D35 DQS5 w 4 DQS DQS U6 U15 Verba DO D35 DQ 47 40 DQ 7 0 LJ DQ 7 0 a fl ZQ za Vss e o DO D35 F mx 5 8 bolo a OOIO DQS6 w pas 9 e pas 9e Note DQS6 w bas n bas UTC 1 DQ to I O wiring may be changed within a nibble DQ 55 48 DQ 7 0 DQ 7 0 2 Unless otherwise noted resistor values are 15 596 sd ze e 3 See the wiring diagrams for all resistors associated with EV E TS AITE the command address and control bus SIE A OOIO 19 it Dass DOS 8 Das 6 4 ZQ resistors are 2400 1 h For all other resistor val DQS3 w Das um Das T ues refer to the appropriate wiring diagram DQ 31 24 W DQIZ 0 DQ 7 0 Fl ZQ ZQ Vtt 34 16 of 53 Rev 1 06 July 2009 ELECTRONICS DDR3 SDRAM Registered DIMM 10 6 8GB 1Gx72 Module Populated as 4 ranks of x DDR3 SDRAMs aadA VL yOd VeSdd VIO NJvgag VIO Nlvad villaodd V03xOug
27. Vin ca AC150 AC input logic high i Vngr 150 2 mV 1 2 Vit ca AC150 AC input logic lowM z VREF 150 mV 12 Vrerca DC DD TOPADD 0 49 Vpp 0 51 Vpp 0 49 Vpp 0 51 Vpp V 34 Note 1 For input only pins except RESET VREF VREFcA DC 2 See Overshoot and Undershoot specifications section 3 The AC peak noise on Veer may not allow VsEr to deviate from Vgge DC by more than 1 Vpp for reference approx 15mV 4 For reference approx Vpp 2 x 15mV Single Ended AC and DC input levels for DQ and DM Symbol Parameter SA DOES M Unit Notes Min Max Min Max Vinpo DC100 DC input logic high Vrer 100 Vpp Vngr 100 Vpp mV 1 Vit pa DC100 DC input logic low Vss Vrer 100 Vss VREF 100 mV 1 Vin po AC175 AC input logic high VREF 175 VREF 150 mV 1 2 5 ViL po AC175 AC input logic low 2 VREF 175 VREF 150 mV 1 2 5 Vi po AC150 AC input logic high VREF 150 Note 2 z mV 1 2 5 ViL po AC150 AC input logic low Note 2 VREF 150 mV 1 2 5 Vaerpo DC I O Reference Voltage DQ 0 49 Vpp 0 51 Vpp 0 49 Vpp 0 51 Vpp V 3 4 Note 1 For input only pins except RESET VsEF VREFpo DC 2 Overshoot and Undershoot specifications section 3 The AC peak noise on VsEF may not allow VsEr to deviate from VsEF DC by more than 1 Vpp for reference approx 15mV 4 For reference approx Vpp 2 15mV 5 Single ended swing requirement for D
28. 136 Vss 56 A7 176 Vpp 97 DQ43 217 Vss 17 Vss 137 DQ14 57 Vpp 177 A8 98 Vss 218 DQ52 18 DQ10 138 DQ15 58 A5 178 A6 99 DQ48 219 DQ53 19 DQ11 139 Vss 59 A4 179 Vpp 100 DQ49 220 Vss DM6 DQS15 20 Vss 140 DQ20 60 Vpp 180 A3 101 Vss 221 TDQS15 NC DQS15 21 DQ16 141 DQ21 61 A2 181 A1 102 DQS6 222 Thas15 22 DQ17 142 Vss 62 Vpp 182 Vpp 103 DQS6 223 Vss DM2 DQS11 23 Vss 143 TDQS11 63 NC CK1 183 Vpp 104 Vss 224 DQ54 24 DQS2 144 NC DQS11 64 NC CK1 184 CKO 105 DQ50 225 DQ55 TDQS11 25 DQS2 145 Vss 65 Vpp 185 CKO 106 DQ51 226 Vss 26 Vss 146 DQ22 66 Vpp 186 Vpp 107 Vss 227 DQ60 27 DQ18 147 DQ23 67 VREFcA 187 EVENTNC 108 DQ56 228 DQ61 28 DQ19 148 Vss 68 NC Par In 188 AO 109 DQ57 229 Vss 29 Vss 149 DQ28 69 Vpp 189 Vpp 110 Vss 230 pco DM7 DQS16 30 DQ24 150 DQ29 70 A10 AP 190 BA1 114 DQS7 231 TDS16 31 DQ25 151 Vss 71 BAO 191 Vpp 112 DQS7 232 Vss DM3 DQS12 32 Vss 152 TDQS12 72 Vpp 192 RAS 113 Vss 233 DQ62 ru NC DQS12 33 DQS3 153 TbOS12 73 WE 193 SO 114 DQ58 234 DQ63 34 DQS3 154 Vss 74 CAS 194 Vpp 115 DQ59 235 Vss 35 Vss 155 DQ30 75 Vpp 195 ODTO 116 Vss 236 VppsPp 36 DQ26 156 DQ31 76 S1 NC 196 A13 117 SAO 237 SA1 37 DQ27 157 Vss 77 ODT1 NC 197 Vpp 118 SCL 238 SDA 38 Vss 158 CB4 NC 78 Vpp 198 S3 NC 119 SA2 239 Vss 39 CBO NC 159 CB5 NC 79 S2 NC 199 Vss 120 Vor 240 Vir 40 CB1 NC 160 Vss 80 Vss 200 DQ36 DM8 DQS17 41 Vss 161 TDQS17 NC 81 DQ32 201 DQ37 NC No Connect SAMSUNG ELECTRONICS CO Ltd reser
29. 17 DQ and DM Input pulse width for each input tDIPW 600 i 490 400 ps 28 Data Strobe Timing DQS DQS READ Preamble tRPRE 0 9 Note 19 0 9 Note 19 0 9 Note 19 tCK 13 19 g DQS DQS differential READ Postamble tRPST 0 3 Note 11 0 3 Note 11 0 3 Note 11 tCK 11 13 b Das DAs output high time tQSH 0 38 0 38 0 4 tCK avg 13 g Das DQS output low time tQSL 0 38 0 38 0 4 tCK avg 13 g DQS DQS WRITE Preamble tWPRE 0 9 0 9 0 9 tCK DQS DQS WRITE Postamble tWPST 0 3 0 3 0 3 tCK oe rising edge output access time from rising tDQSCK 400 400 300 300 255 255 ps 13f DQS DQS low impedance time Referenced from RL 1 tLZ DQS 800 400 600 300 500 250 ps 13 14 f REND high impedance time Referenced from 1HZ DQS _ 400 _ 300 E 250 ps 12 13 14 DQS DQS differential input low pulse width tDQSL 0 45 0 55 0 45 0 55 0 45 0 55 tCK 29 31 DQS DQS differential input high pulse width tDQSH 0 45 0 55 0 45 0 55 0 45 0 55 tCK 30 31 DQS DQS rising edge to CK CK rising edge tDQSS 0 25 0 25 0 25 0 25 0 25 0 25 tCK avg c DQS DQS falling edge setup time to CK CK rising edge tDSS 0 2 0 2 0 2 tCK avg c 32 DQS DQS falling edge hold time to CK CK rising edge tDSH 0 2 0 2 0 2 tCK avg c 32 39 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM Timing Parameters by Speed Bin Cont
30. 26 23 D 35 32 DQS2 9 ee gS Sol A RAS m WRAS gt RAS SDRAMs D 4 0 D8 D 13 9 22 18 D 31 27 Buse w bas Das ERAS gt RAS SDRAMs D 8 5 D 17 14 D 26 23 D 35 32 DQS2 w DQS U2 DQS naa os wd WCAS gt CAS SDRAMs D 4 0 D8 D 13 9 D 22 18 D 31 27 8 ECAS gt CAS SDRAMs D 8 5 D 17 14 D 26 23 D 35 32 DQI23 16 W cds p T WE 12 WWE gt WE SDRAMs D 4 0 D8 D 13 9 D 22 18 D 31 27 x uH S EWE gt WE SDRAMs D 8 5 D 17 14 D 26 23 D 35 32 WCKEO gt CKE0 SDRAMs D 4 0 D 22 18 Fs UE SGU ER Y ECKEO gt CKEO SDRAMs D 8 5 D 26 23 b OO lt a OOIO WCKE1 gt CKE1 SDRAMs D 13 9 D 31 27 DQS3 pas O O DQS hel Y s ECKE1 gt CKE1 SDRAMs D 17 14 D 35 32 5063 ETE SEE WODT0 gt ODTO SDRAMs D 4 0 DQS3 w DQS u3 DQS U12 ODIO Ww E EODTO gt ODTO SDRAMs D 8 5 AA 8 WODT1 gt ODT1 SDRAMs D 22 18 DQI31 24 p Pa rea opr YY EODT1 ODT1 SDRAMs D 26 23 id PCKO gt CK SDRAMs D 4 0 D 13 9 T PCK1 gt CK SDRAMs D 8 5 D 26 23 PCK2 gt CK SDRAMs D 22 18 D 31 27 esia B S5 La PCK3 gt CK SDRAMs D 17 14 D 35 32 Dass A pas oo DOS oo PCKO gt CK SDRAMs D 4 0 D 13 9 acis PCK1 gt CK SDRAMs D 8 5 D 26 23 DQS8 w DOS UA DQS U13 CKo PCK2 gt CK SDRAMs D 22 18 D 31 27 CBI7 0 DQ 7 0 DQ 7 0 PCK3 gt CK SDRAMs D 17 14 D 35 32 a 2Q za PAR IN w GERE Eroi Reset
31. 5 13 125 59 ns ACT to ACT or REF command period tRC 49 5 49 125 gt 9 ns ACT to PRE command period tRAS 36 9 tREFI ns 8 CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 6 tCK AVG Reserved ns 1 2 3 4 7 CWL 7 tCK AVG Reserved ns 4 CWL 5 tCK AVG Reserved ns 4 CL 7 CWL 6 tCK AVG uis ns 1 2 3 4 7 Optional Note 5 9 CWL 7 tCK AVG Reserved ns 1 2 3 4 CWL 5 tCK AVG Reserved ns 4 CL 8 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 tCK AVG Reserved ns 1 2 3 4 TN CWL 5 6 tCK AVG Reserved ns 4 CWL 7 tCK AVG 1 5 1 875 ns 1 2 3 4 CWL 5 6 tCK AVG Reserved ns 4 CL 10 1 5 1 875 ns 1 2 3 CWL 7 tCK AVG Optional ns 5 Supported CL Settings 6 7 8 9 nCK Supported CWL Settings 5 6 7 nCK 17 3 1 Speed Bin Table Notes Absolute Specification Toper Vppa Vpp 1 5V 0 075 V Note 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When making a selection of tCK AVG both need to be ful filled Requirements from CL setting as well as requirements from CWL setting 2 tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchronized by the DLL all possible intermediate frequen cies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next SupportedCL 3 tCK AVG MAX limits Calculate tCK
32. 9 D17 1 DQ to I O wiring may be changed within a byte PCK1B gt CK SDRAMs D 16 13 2 Unless otherwise noted resistor values are 15Q 5 eK0 PCKOA gt CK SDRAMs D 3 0 D8 PCKoB gt CK SDRAMs D 7 4 3 RS0 and RS1 alternate between the back and front sides of the PCK1A gt CK SDRAMs D 12 9 D17 DIMM PCK1B gt CK SDRAMs D 16 13 4 ZQ resistors are 240Q 1 For all other resistor values refer to the PAR IN oe Em out appropriate wiring diagram RESET 5 See the wiring diagrams for all resistors associated with the command PST SDRAMs D 8 0 address and control bus S 3 2 CKE1 ODT1 CK1 and CK1 are NC ELECTRONICS 12 of 53 Rev 1 06 July 2009 Registered DIMM DDR3 SDRAM 10 3 2GB 256Mx72 module Populated as 1 rank of x4 DDR3 SDRAMs
33. AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED 4 Reserved settings are not allowed User must program a different value 5 Optional settings allow certain devices in the industry to support this setting however it is not a mandatory feature Refer to supplier s data sheet and or the DIMM SPD information if and how this setting is supported 6 Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 7 Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 8 Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 9 For devices supporting optional downshift to CL 7 and CL 9 tAA tRCD tRP min must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333 CL9 devices supporting downshift to DDR3 1066 CL7 should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600 CL 11 devices supporting downshift to DDR3 1333 CL9 or DDR3 1066 CL7 shou
34. D30 E DQ 27 24 W4 DQ 3 0 DS E DQ 3 0 D24 E 7 ipl os Au IE o ad Wie Ss al wxx aZ Wie V Rz agsiesis 82 gail SISSOS 8 BERS ot DQS11 w pas E pas gt DoS11 w pas E Dos DQS11 w Das Das Z DQS11 w DES pas Z VSS DM lt DM T VSS DM Ed DM T DQ 23 20 A DQ 3 0 Di Dol3 0 p22 a DQ 19 16 A DQ 3 0 e DQ 3 0 D20 am viduis UE S ease sss ME EE Basss S84 aiios SIS SOS DQS10 A DQS 5 Das DQS10 w DAS 5 DQS S DQS10 v Das E DQS zi DQS10 DOS Z DQS Z VSS w DM DM Ed VSS w DM DM DQ 15 12 A DQ 3 0 p pQ 3 0 D28 aj DQ 11 8 jr DQ 3 0 n 8 L 4 pais Dis m A Jux esse sss lesse sss ls sesso assess paso pas 5 Das paso Das z Dos DQS0 w DOS E DQS DQS0 w Das 2 DOS 2 VSS wv D
35. Millimeters
36. RDIMMs n 0 7 NC cgn Used on x72 UDIMMs n 0 7 not 165 used on x64 UDIMMs 12534 143 pase comede io pas on x4 sprawe DL a 212 221 230 TDQSn TDQS on x8 SDRAMs on RDIMMs n 9 17 n 0 8 126 135 144 LAS DQSn Connected to DQS on x4 DRAMs TDQS on x8 153 162 204 i bacs NC Not used on UDIMMs 213 222 231 TDQSn SDRAMs on RDIMMs n 9 17 Connected to optional thermal sensing compo EVENT nent 1er NC NC on Modules without a thermal sensing NG Nofiused on UDINIMS component Note NC no internal connection iii Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 9 0 Registering Clock Driver Specification 9 1 Timing amp Capacitance values Tc TBD Symbol Parameter Conditions Vpp 1 5 0 075V Units Notes Min Max fclock Input Clock Frequency application frequency 300 670 MHz tcn tcL Pulse duration CK CK HIGH or LOW 0 4 tck tact Inputs active time4 before RESET is taken HIGH DEKEN ae ane 8 tek tsu Setup time Input valid before CK CK 100 ps ty Hold time peut to remain Valid after CK 175 tppm Propagation delay single bit switching CK CK to output 0 65 1 0 ns tois output disable time 1 2 Clock pre launch amor in o tput dai 0 5 tox output disable time 3 4 Clock pre launch 0 25 T output enable time 1 2 Clock pre launch PES sutpue
37. Similarly tQH min derated tQH min tUlT per act min 0 38 x tCK avg act tJIT per act min 0 38 x 2500 ps 72 ps 878 ps Caution on the min max usage 0 38 x 2500 ps 72 ps 878 ps Caution on the min max usage 42 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 18 2 Timing Parameter Notes 1 Actual value dependant upon measurement level definitions which are TBD 2 Commands requiring a locked DLL are READ and RAP and synchronous ODT commands 3 The max values are system dependent 4 WR as programmed in mode register 5 Value must be rounded up to next higher integer value 6 There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI T For definition of RTT turn on time tAON see Device Operation 8 For definition of RTT turn off time tAOF see Device Operation 9 tWR is defined in ns for calculation of tWRPDEN it is necessary to round up tWR tCK to the next integer 10 WR in clock cycles as programmed in MRO 11 The maximum read postamble is bound by tDQSCK min plus tQSH min on the left side and tHZ DQS max on the right side Device Operation 12 Output timing deratings are relative to the SDRAM input clock When the device is operated with input clock jitter this parameter needs to be derated by TBD 13 Value is valid for RON34 14 Single ended signal parameter 15 tREFI depends on Toper 16 tIS base and tIH base values are f
38. VSS VSS VSS VSS VSS VSS aaa 7 VL MOgV 7 VLSgV 7 o Nlvg o NIv 100 345 o Nlva lo Nlv do 330 9 lo NIva lo nlv 1qo 3X0 VIO NIvgaV VIo Nlvav volaodv V0 MOaV VOMOdV VO0JOgV V AdV VSVOdV VSVddV vosuv Io Nlvg o NIv 100 3X9 Mo yO e A mh Svo e Q SVY r e 8 5 o Nlva lo Nlv 1dO 390 9 ro x A m Svo ag So Io NIvg Io Nlv 1do ayo 39 j D5 sige o VSS w4ZQ DQS8 A DQS DQS8 A DES VSS DM CB 3 0 WW DQ 3 VSS wZQ DQS3 w DQs DQS3 A 1DQS vss DM DQ 27 24 A DOQ 3 VSS AN ZQ DQS2 DES DQS2 w DQs VSS DM DQ 19 16 A DQ 3 0
39. and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 Vpp and Vppo must be within 300mV of each other at all times and Veer must be not greater than 0 6 x Vppo When Vpp and Vppo are less than 500mV Vggre may be equal to or less than 300mV 11 2 DRAM Component Operating Temperature Range Symbol Parameter rating Unit Notes TOPER Operating Temperature Range 0 to 95 C 1 2 3 Note 1 Operating Temperature Toper is the case surface temperature on the center top side of the DRAM For measurement conditions please refer to the JEDEC document JESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported During operation the DRAM case tem perature must be maintained between 0 85 C under all operating conditions 3 Some applications require operation of the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaran teed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the refresh interval tREFI t
40. associated with Veer ac noise Timing and voltage effects due to ac noise on VsE up to the specified limit 1 of Vpp are included in DRAM timings and their associated deratings 24 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 13 3 AC and DC Logic Input Levels for Differential Signals 13 3 1 Differential Signals Definition r4 tDVAC Vn DIFF AC MIN Vin DIFFMIN Differential Input Voltage i e DQS DQS CK CK 0 0 half cycle Vi DIFF MAX Vi DIFF AC MAX time _ Figure 2 Definition of differential ac swing and time above ac level tDVAC 13 3 2 Differential Swing Requirement for Clock CK CK and Strobe DQS DQS DDR3 1066 1333 Symbol Parameter unit Note min max Vinditt differential input high 0 2 note 3 V 1 ViLdif differential input low note 3 0 2 V 1 Vinai AC differential input high ac 2 x Vn AC VsEr note 3 V 2 ViLai AC differential input low ac note 3 2 x VREF ViL AC V 2 Notes 1 Used to define a differential signal slew rate 2 for CK CK use Vin ViL AC of ADD CMD and Vperca for DQS DOS DQSL DQSL DQSU DQSU use Vip ViL AC of DQs and VREFpoi if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however they single ended signals CK CK DQS DQS DQSL DQSL DQSU DQSU need to be within the resp
41. at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 33 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 33 IDD1 Precharge Standby Current CKE High External clock On tCK CL see Table 30 on page 31 BL 83 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 34 on page 36 Data IO FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 34 Precharge Standby ODT Current CKE High External clock On tCK CL see Table 30 on page 31 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 35 on page 37 Data IO FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according to Table 35 Pattern Details see Table 35 DDQ2NT Precharge Standby ODT IDDQ Current optional Same definition like for IDD2NT however measuring IDDQ current instead of IDD current IDD2N DD2NT Precharge Power Down Current Slow Exit CKE Low External clock On tCK CL see Table 30 on page 31 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 HEBER Data IO FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and
42. side Back side 6 5 0 Pin Description M 7 6 0 ON Hp Mi nib IDIOT nnn 7 7 0 Input Output Functional Description cee 8 8 0 Pinout comparison Based on Module Type anes 9 9 0 Registering Clock Driver Specification cannes 10 94 Timing amp Capacitance WMB 10 5 2 Clock driver Characteristics 2 2 cico reco riora a nao anane Da RE reo gna cEUa a 10 10 0 Functional Block Diagram es 11 10 1 1GB 128Mx72 Module Populated as 1 rank of x8 DDR3 SDRAMS eren 11 10 2 2GB 256Mx72 Module Populated as 2 ranks of x8 DDR3 SDRAMS eene 12 10 3 2GB 256MX72 module Populated as 1 rank of x4 DDR3 SDRAMS eere 13 10 4 4GB 512Mx72 Module Populated as 2 ranks of x4 DDR3 SDRAMS sssssssssnsnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnn 14 10 5 4GB 512Mx72 Module Populated as 4 ranks of x8 DDR3 SDRAMS ssssssssssssunnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 16 10 6 8GB 1Gx72 Module Populated as 4 ranks of x4 DDR3 SDRAMS ener 17 11 0 Absolute Maximum Ratings ue 22 11 1 Absolute Maximum DO RRBRdERaaaeiigsais 22 11 2 DRAM Component Operating Temperature Range eeseeseeeeee eene nennen nnn nennen nn 22 12 0 AC amp DC Operating Conditions ai 22 12 1 Recommended DC Operating Conditions SSTL 15
43. 0 15 i 10 9 0 4 k 1 rs 50 dE 4 1 50 0 10 0 eS Detail A Detail B Detail C 19 5 1 x72 DIMM populated as four physical ranks of x8 DDR3 SDRAMs O U O Ei HoN 2x 2 10 0 15 m m En n m H r1 H Hm H ER LUA LLA I I I I I I I I I I I I I I T O Address Command and Control lines The used device is 128M x8 DDR3 SDRAM FBGA DDR3 SDRAM Part NO KAB1G0846E HC Note Tolerances on all dimensions 0 15 unless otherwise specified 50 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 19 6 512Mbx4 based 1Gx72 Module 4 Ranks M393B1G70EM1 Units Millimeters
44. 00 DDR3 1066 DDR3 1333 Parameter Symbol Units Notes Min Max Min Max Min Max Input output capacitance DQ DM DOS DQS TDQS TDQS kb TBD TED TBD pF Input capacitance CK and CK CCK TBD TBD TBD pF Input capacitance All other input only pins al i TBD TBD pF Input output capacitance of ZQ pin CZQ TBD TBD TBD pF M393B5670EH1 DDR3 800 DDR3 1066 DDR3 1333 Parameter Symbol Units Notes Min Max Min Max Min Max Input output capacitance DQ DM DQS DQS TDQS TDQS MS IBD TDR TE PF Input capacitance CK and CK CCK TBD TBD TBD pF Input capacitance All other input only pins sl TBD EP 18D pF Input output capacitance of ZQ pin CZQ TBD TBD TBD pF M393B5170EH1 DDR3 800 DDR3 1066 DDR3 1333 Parameter Symbol Units Notes Min Max Min Max Min Max Input output capacitance DQ DM DOS DQS TDQS TDQS WP TBD TBD TED pF Input capacitance CK and CK CCK TBD TBD TBD pF Input capacitance All other input only pins a TED TED TBD pr Input output capacitance of ZQ pin CZQ TBD TBD TBD pF M393B5173EH1 M393B1G70EM1 DDR3 800 DDR3 1066 DDR3 800 DDR3 1066 Parameter Symbol Units Notes Min Max Min Max Min Max Min Max Input output capacitance DQ DM DQS DQS TDQS TDQS DE i TBD TBD d TBD TBD pF Input capacitance CK and CK CCK TBD TBD TBD TBD pF Input capacitance All other input only pins el i TBD TBD TBD i TBD pF Input output capacitance of ZQ pin CZQ TBD TBD TBD TBD p
45. 0EH1 uae 47 19 4 1 x72 DIMM populated as two physical ranks of x4 DDR3 SDRAMS eene 47 19 4 2 Heat Spreader Design Guide eens 48 19 5 128Mbx8 based 512Mx72 Module 4 Ranks M393B5173EH1 Lan 50 19 5 1 x72 DIMM populated as four physical ranks of x8 DDR3 SDRAMS eene 50 19 6 512Mbx4 based 1Gx72 Module 4 Ranks M393B1G70EM1 51 19 6 1 x72 DIMM populated as four physical ranks of x4 DDR3 SDRAMS eene 51 19 6 2 Heat Spreader Design Guide eee 52 notes Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM Revision History Revision Month Year History 1 0 December 2008 First Release 1 01 January 2009 Corrected Module Physical Dimensions 1 02 January 2009 Corrected Typo 1 03 February 2009 Added Tolerances to Physical Dimensions 1 04 April 2009 Corrected Module Physical Dimensions 1 05 July 2009 Corrected Typo 1 06 July 2009 Added part number information on physical dimensions page iui Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 1 0 DDR3 Registered DIMM Ordering Information Part Number Density Organization Component Composition Boat ai Height M393B2873EH1 CF8 H9 1GB 128Mx72 128Mx8 K4B1G0846E HC 9 1 30mm M393B5673EH1 CF8 H9 2GB 256Mx72 128Mx8 K4B1G0846E HC 18 2 30mm M393B5670EH1 CF8 H9 2GB 256Mx72 256
46. 2 ranks of x8 DDR3 SDRAMs lt a XX gt x mm mm mm mmoomeo mm ES SS me m ES e u H gass E s We dereic 8 gE BE SED C p sa AA d c IE ala cox DQS8 DQS DQS DQS4 DOS DQS DQS8 A DQS E DQS DQS4 w DAS DQS DM8 DQS17 TDQS pg E TDGS p47 Z DM4 DQS13 w4 TDQS p4 2 IDQS p43 z DQS17 4 TDQS TDQS DQS13 w TDQS lt TDQS ES CB 7 0 Ww DQ 7 0 f DQI7 0 S DQ 39 32 DQ 7 0 PA ZQ joja ZQ ioo we gt ZQ oo Wk ZQ jan wes ad UWvie OZ Lu az LI vie OZ
47. 240 V Termination Voltage for Address Command Con V Termination Voltage for Address Command Con i Tr trol Clock nets n trol Clock nets 53 Err Out Connected to the register on all RDIMMs NC Not NC NC Not used on UDIMMs used on UDIMMs 63 NC CK1 i 2 Not used on RDIMMs Used for 2 rank UDIMMs not used on single rank 64 NC CK1 UDIMMs but terminated 68 Par In Connected to the register on all RDIMMs NC Not used on RDIMMs 76 1 Connected to the register on all RDIMMs S1 Used for duai rank UDIMMS fot connected on single rank UDIMMs Connected to the register on dual and quadrank Used for dual rank UDIMMs not connected n ODTIENE RDIMMs NC on single rank RDIMMs ODTING on single rank UDIMMs Connected to the register on quad rank 79 2 NC RDIMMs not connected on single or dual rank NC Not used on UDIMMs RDIMMs 167 NC TEST input used only on bus analysis probes NC Uae us d only on bus analysts 169 CKE1 Connected to the register on dual and quadrank CKE1 Used for dual rank UDIMMs not connected RDIMMs NC on single rank RDIMMs NC on single rank UDIMMs 171 A15 A15 NC Depending on device density may not be 172 A14 Connected to the register on all RDIMMs A14 connected i SDRAMS on UDIMMS However these signals are terminated on 196 A13 A13 UDIMMs A15 not routed on some RCs E Connected to the register on quad rank 198 S3 NC RDIMMs not connected on single or dual rank NC Not used on UDIMMs RDIMMs 39 40 45 46 E 158 159 164 CBn Used on all
48. 6 is valid even if Tm 6 Tm is less than 15ns due to input clock jitter Specific Note f When the device is operated with input clock jitter this parameter needs to be derated by the actual tERR mper act of the input clock where 2 lt m lt 12 output deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR3 800 SDRAM has tERR mper act min 172 ps and tERR mper act max 193 ps then tDQSCK min derated tDQSCK min tERR mper actmax 400 ps 193 ps 593 ps and tDQSCK max derated tDQSCK max tERR mper act min 400 ps 172 ps 572 ps Similarly tLZ DQ for DDR3 800 derates to tLZ DQ min derated 800 ps 193 ps 993 ps and tLZ DQ max derated 400 ps 172 ps 572 ps Caution on the min max usage Note that tERR mper act min is the minimum measured value of tERR nper where 2 lt n lt 12 and tERR mper act max is the maximum measured value of tERR nper where 2 lt n lt 12 Specific Note g When the device is operated with input clock jitter this parameter needs to be derated by the actual tJIT per act of the input clock out put deratings are relative to the SDRAM input clock For example if the measured jitter into a DDR3 800 SDRAM has tCK avg act 2500 ps tJIT per act min 72 ps and tJIT per act max 93 ps then tRPRE min derated tRPRE min tJIT per actmin 0 9 x tCK avg act tUlT per act min 0 9 x 2500 ps 72 ps 2178 ps
49. 840 2100 mA IDD2Q 1620 1840 2100 mA IDD3P fast exit 1620 1660 1740 mA IDD3N 2160 2380 2640 mA IDD4R 2295 2515 2910 mA IDD4W 2295 2605 3000 mA IDD5B 2880 2920 3225 mA IDD6 1080 1120 1200 mA IDD7 2970 3145 3855 mA M393M1G70EM1 8GB 1Gx72 Module Symbol cr cre MH Unit Notes DDR3 800 CL 6 DDR3 1066 CL 7 DDR3 1333 CL 9 IDDO 3906 4068 4572 mA IDD1 4176 4338 4842 mA IDD2PO slow exit 2016 2088 2232 mA IDD2P1 fast exit 3096 3168 3312 mA IDD2N 3456 3528 4032 mA IDD2Q 3096 3528 4032 mA IDD3P fast exit 3096 3168 3312 mA IDD3N 4176 4608 5112 mA IDD4R 4266 4698 5472 mA IDD4W 4446 4878 5652 mA IDD5B 5616 5688 6282 mA IDD6 2016 2088 2232 mA IDD7 5796 6048 7452 mA BN Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 16 0 Input Output Capacitance M393B2873EH1 DDR3 800 DDR3 1066 DDR3 1333 Parameter Symbol Units Notes Min Max Min Max Min Max Input output capacitance DQ DM DQS DQS TDQS TDQS cio TBD TBD TBD pF Input capacitance CK and CK CCK TBD TBD TBD pF Input capacitance All other input only pins bd TBD TBD TEP Input output capacitance of ZQ pin CZQ TBD TBD TBD pF M393B5673EH1 DDR3 8
50. CS High between REF Command Address Bank Address IBDSR Inputs partially toggling according to Table 38 on page 38 Data IO FLOATING DM stable at 0 Bank Activity REF command every nRFC see Table 38 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 38 Self Refresh Current Normal Temperature Range IDD6 TCASE 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Low External clock Off CK and CK LOW CL see Table 30 on page 31 BL 89 AL 0 CS Command Address Bank Address Data IO FLOATING DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal FLOATING 30 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM Symbol Description Self Refresh Current Extended Temperature Range optional IDD6ET TCASE 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended CKE Low External clock Off CK and CK LOW CL see Table 30 on page 31 BL 89 AL 0 CS Command Address Bank Address Data IO FLOATING DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal FLOATING Auto Self Refresh Current optionar IDDGTC TCASE 0 95 C Auto Self Refresh ASR Enabled Self Refresh Temperature Ra
51. DDR3 SDRAMs 2x 2 10 0 15 m E yoy py y m Y C E 7 E O NON O O Address Command and Control lines Note DRAMs indicated with dotted outline are located on the backside of the module The used device is 128M x8 DDR3 SDRAM FBGA DDR3 SDRAM Part NO K4B1G0846E HC Note Tolerances on all dimensions 0 15 unless otherwise specified ses Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 19 2 128Mbx8 based 256Mx72 Module 2 Ranks M393B5673EH1 Units Millimeters
52. ECTRONICS Registered DIMM DDR3 SDRAM M393B5670EH1 2GB 256Mx72 Module Symbol KC chs He Unit Notes DDR3 800 CL 6 DDR3 1066 CL 7 DDR3 1333 CL 9 IDDO 1710 1840 2010 mA IDD1 1980 2110 2280 mA IDD2P0 slow exit 900 940 1020 mA IDD2P1 fast exit 1170 1210 1290 mA IDD2N 1260 1300 1470 mA IDD2Q 1170 1300 1470 mA IDD3P fast exit 1170 1210 1290 mA IDD3N 1440 1570 1740 mA IDD4R 2070 2470 2910 mA IDD4W 2250 2650 3090 mA IDD5B 3420 3460 3720 mA IDD6 700 740 1020 mA IDD7 3600 3820 4890 mA M393B5170EH1 4GB 512Mx72 Module Symbol SEY ote oe Unit Notes DDR3 800 CL 6 DDR3 1066 CL 7 DDR3 1333 CL 9 IDDO 2250 2380 2640 mA IDD1 2520 2650 2910 mA IDD2PO slow exit 1080 1120 1200 mA IDD2P1 fast exit 1620 1660 1740 mA IDD2N 1800 1840 2100 mA IDD2Q 1620 1840 2100 mA IDD3P fast exit 1620 1660 1740 mA IDD3N 2160 2380 2640 mA IDD4R 2610 3010 3540 mA IDD4W 2790 3190 3720 mA IDD5B 3960 4000 4350 mA IDD6 1080 1120 1200 mA IDD7 4140 4360 5520 mA BMN Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM M393B5173EH1 4GB 512Mx72 Module Symbol cry che cH9 Unit Notes DDR3 800 CL 6 DDR3 1066 CL 7 DDR3 1333 CL 9 IDDO 2025 2110 2370 mA IDD1 2160 2245 2505 mA IDD2P0 slow exit 1080 1120 1200 mA IDD2P1 fast exit 1620 1660 1740 mA IDD2N 1800 1
53. Ed CB 47 44 DQ 3 0 D a DQ 3 0 D32 CB 39 36 A DQ 3 0 DS DQ 3 0 DS MJ We pn os m ni rs az algigw xe oe eau xxx as Wee az dk BESE SISS8S BOSSES Sox Bisz l5 o amp DQS4 DQS DQS E DQS5 DQS DQS S DQS4 A DQS DQS 2 Dass w DQS zi DQS zl VSS w DM lt DM lt VSS w DM Ed DM lt DQ 35 32 W DQI3 0 De E DQ 3 0 D22 DQ 43 40 W DQ 3 0 D5 DQ 3 0 D23 E IE wes We w Wye voz e Wie lt aZ uwxxxaz Wee x az MS SS8 Bsz SESS Bese Gl6 os Oise l5 So E L III La DQS16 DQS i DQS S DQS15 w DQS S DQS S DQS16 DQS 2 DQS 2 DQS15 w DQS e DQS VSS WT DM lt DM lt VSS w DM Ed DM DQ 63 60 A_ DQ 3 0 DIO E DQ 3 0 34 2 DQ 55 52 A DQ 3 0 D DQ 3 0 DS33 S Iu pa am I sa uit es imc des os Wee lt aoZ gl Wie lt OZ Wee lt aoZ Wee lt aZz akse 8 88 Bless 8588 ain GS8 Oise 86 DQS10 DQS ES DQS y DQS6 w DQS E DQS 5 DQS10 v j DQS DQS zi DQS6 DQS Z DQS Z VSS WT DM lt DM lt VSS w DM lt DM lt DQ 59 56 W DQ 3 0 Dj 2 DQ 3 0 D25 E DQ 51 48 w DQ 3 0 D5 DQ 3 0 D24 E
54. F 3510193 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 17 0 Electrical Characteristics and AC timing 0 C lt T cage lt 95 C Vppo 1 5V 0 075V Vpp 1 5V 0 075V 17 1 Refresh Parameters by Device Density Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units Note All Bank Refresh to active refresh cmd time tRFC 110 160 300 350 ns 0 C lt TcAsE lt 85 C 7 8 7 8 7 8 7 8 us Average periodic refresh interval tREFI 85 C lt TcAsE lt 95 C 3 9 3 9 3 9 3 9 us 1 Note 1 Users should refer to the DRAM supplier data sheet and or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material 17 2 Speed Bins and CL tRCD tRC and tRAS for Corresponding Bin Speed DDR3 800 DDR3 1066 DDR3 1333 Bin CL tRCD tRP 6 6 6 7 7 7 9 9 9 Units Note Parameter min min min CL 6 7 9 tCK tRCD 15 13 13 13 5 ns tRP 15 13 13 13 5 ns tRAS 37 5 37 5 36 ns tRC 52 5 50 63 49 5 ns tRRD 10 7 5 6 0 ns tFAW 40 37 5 30 ns PROS Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 17 3 Speed Bins and CL tRCD tRP tRC and tRAS for corresponding Bin DDR3 SDRAM Speed Bins include tCK tRCD DDR3 800 Speed Bins tRP tRAS and tRC for each corresponding bin
55. M 9 DM VSS A DM 9 DM lt DQ 3 0 A DQ 3 0 a amp paso Dis a DQ 7 4 A DQ 3 0 2g DQ3 0 D27 a Dui ee SZ A awn YB 2 PERIE d ot assis d ot Blaise Soso sase d ot vtt vtt we 14 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM am nad as ds PEA EE nage Bese ss S823 E FEF Bee EE E ER zZ c Z Peseseoses 2 8588 aksess g SEB LI ll lil LLLI LILLLLLI LLLI DQS14 w DQS DQS 5 DQS13 w DQS E Das zy DQS14 w DOS 2 DQS Zz DQS13 DOS Zz DQS zi VSS w DM lt DM lt VSS w DM lt DM
56. M 10 5 4GB 512Mx72 Module Populated as 4 ranks of xa DDR3 SDRAMs o O X So Uuh oou aa eb goal g8853 98852 g8858 ipio Oo cic ss Gg ss Erz 5g zs 8S YE EAE Solo e OOIO DQS0 Ww pas Ee pas SEO DQS0 DQS DQS Uo u9 DQ 7 0 A DQIZ 0 DQ 7 0 f ZQ ZQ SW SRM5 DQS1 w pas o0 Das o0 80 w RS0 gt C80 SDRAMs D amp 0 DOS1 A been Tm 81 w RS1 gt CS1 SDRAMs D 17 9 Das DOS U1 pes u10 S2 w4 _ RS2 gt CS2 SDRAMs D 26 18 DQ 15 8 WPDQI7 0 DQ 7 0 33 wm ___ RS3 gt CS3 SDRAMs D 35 27 ZQ Za 6 WBAIN 0 gt BA N 0 SDRAMs D 4 0 D8 D 13 9 22 18 D 31 27 i BAIN 0 EBAIN 0 gt BAIN 0 SDRAMs D 8 5 D 17 14 D 26 23 D 35 32 WAIN 0 gt A N 0 SDRAMs D 4 0 D8 D 13 9 D 22 18 D 31 27 x 5 mgs 23 5 AIN 0 W EA N 0 gt AIN O SDRAMs D 8 5 D 17 14 D
57. Mx4 K4B1G0446E HC 18 1 30mm M393B5170EH1 CF8 H9 4GB 512Mx72 256Mx4 K4B 1G0446E HC 36 2 30mm M393B5173EH1 CF7 F8 4GB 512Mx72 128Mx8 K4B1G0846E HC 36 4 30mm M393B1G70EM1 CF7 F8 8GB 1Gx72 512Mx4 K4B2G0446E MC 36 4 30mm Note F7 800Mbps 6 6 6 F8 1066Mbps 7 7 7 H9 1333Mbps 9 9 9 2 0 Key Features DDR3 800 DDR3 1066 DDR3 1333 Speed Unit 6 6 6 7 7 7 9 9 9 tCK min 2 5 1 875 1 5 ns CAS Latency 6 7 9 tCK tRCD min 15 13 125 13 5 ns tRP min 15 13 125 13 5 ns tRAS min 37 5 37 5 36 ns tRC min 52 5 50 625 49 5 ns JEDEC standard 1 5V 0 075V Power Supply VDDQ 1 5V 0 075V 400 MHz fck for 800Mb sec pin 533MHz fck for 1066Mb sec pin 667MHz fck for 1333Mb sec pin 8 independent internal bank Programmable CAS Latency 6 7 8 9 10 Programmable Additive Latency Posted CAS 0 CL 2 or CL 1 clock Programmable CAS Write Latency CWL 5 DDR3 800 6 DDR3 1066 7 DDR3 1333 8 bit pre fetch Burst Length 8 Interleave without any limit sequential with starting address 000 only 4 with tCCD 4 which does not allow seamless read or write either On the fly using A12 or MRS Bi directional Differential Data Strobe On Die Termination using ODT pin Average Refresh Period 7 8us at lower then Tease 85 C 3 9us at 85 C lt Tc sE lt 95 C Asynchronous Reset 3 0 Address Configuration
58. N 0 SDRAMs D 43 36 D 61 54 RAS w I ARRASA gt RAS SDRAMs D 9 0 D 27 18 RAS w BRRASA gt RAS SDRAMs D 53 44 D 71 62 M ARRASB RAS SDRAMs D 17 10 D 35 28 BRRASB gt RAS SDRAMs D 43 36 D 61 54 CAS _w I ARCASA gt CAS SDRAMs D 9 0 D 27 18 CAS w BRCASA gt CAS SDRAMs D 53 44 D 71 62 ARCASB gt CAS SDRAMs D 17 10 D 35 28 BRCASB gt CAS SDRAMs D 43 36 DI61 54 WE ARWEA gt WE SDRAMs D 9 0 D 27 18 WE BRWEA gt WE SDRAMs D 53 44 D 71 62 ARWEB gt WE SDRAMs D 17 10 D 35 28 BRWEB gt WE SDRAMs D 43 36 D 61 54 CKE0 ARCKEOA gt CKE1 SDRAMs D1 D3 D5 D7 D9 CKEO w BRCKEOA gt CKE1 SDRAMs D45 D47 D49 D51 D53 D19 D21 D23 D25 D27 D63 D65 D67 D69 D71 ARCKEOB gt CKE1 SDRAMs D11 D13 D15 D17 BRCKEOB gt CKE1 SDRAMs D37 D39 D41 D43 D29 D31 D33 D35 D55 D57 D59 D61 CKE1 w 4 2 ARCKE1A gt CKE0 SDRAMs DO D2 D4 D6 D8 CKE1 4 9 BRCKE1A gt CKE0 SDRAMs D44 D46 D48 D50 D52 R D18 D20 D22 D24 D26 R D62 D64 D66 D68 D70 E ARCKE1B gt CKE0 SDRAMs D10 D12 D14 D16 E BRCKE1B gt CKE0 SDRAMs D36 D38 D40 D42 G D28 D30 D32 D34 G D54 D56 D58 D60 ODT0 ARODTOA gt ODT1 SDRAMs D1 D3 D5 D7 D9 ODT1I w BRODT1A gt ODT1 SDRAMs D45 D47 D49 D51 D53 S D19 D21
59. Nlv o NIva lo nlv 1do 1do 1do 1qo MO 390 390 ayo 2 o 2 o 8 2e yX vo co lt X e A m Oo am D am Oo awFHe Svo Svo _ Svo Svo e Q SVa Q SVa SVa Q SYV gag 2 ggz 2 a9Ba 2 q98zg 2 NAAA Nalaaa Nalaqa NN EIE EIE EIER SooS g AnA v QO s aia 10 aia w e e e e a a a a Vtt Rev 1 06 July 2009 19 of 53 ELECTRONICS Registered DIMM DDR3 SDRAM lt lt axo axo IIIT lt SZ lt 2 Z 88 e Ea Za Eele Te E Fa LILLI LIL L A A I lt lt gt mlmlmlm mim m m m L co a gt Litt itt L1 VSS m ZQ VSS N ZQ VSS VSS DQS13 v DQS DQS DQS13 wDQS DQS E v
60. QS DQS is 350mV peak to peak Differential swing for DQS DQS is 700mV peak to peak 23 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 13 2 Veer Tolerances The dc tolerance limits and ac noise limits for the reference voltages VREFcA and VsEFpo are illustrate in Figure 2 It shows a valid reference voltage Vrer t as a function of time V amp ge stands for VsEFcA and VsEFpo likewise VsEE DC is the linear average of VsEE t over a very long period of time e g 1 sec This average has to meet the min max requirements of VsEE Fur thermore VsEr 1 may temporarily deviate from VsE DC by no more than 1 Vpp A voltage Vref ac noise V U i7 Ref DC max mmm eos VDD VRef DC min Figure 1 Illustration of VsEE DC tolerance and VREF ac noise limits The voltage levels for setup and hold time measurements Vin AC Viy DC Vi AC and V DC are dependent on Vggr VsEF shall be understood as Vgge DC as defined in Figure 2 This clarifies that dc variations of Veer affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for VsEE DC deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage
61. QSL DQSU DQSU need to be within the respective limits Vi DC max Vi DC min for single ended signals as well as the limitations for overshoot and undershoot Refer to Overshoot and Undershoot Specification 26 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 13 3 4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in below table The differential input cross point voltage Vix is measured from the actual cross point of true and complement signal to the mid level between of Vpp and Vss Vpp CK DQS CK DQS Vss Figure 4 Vix Definition Cross point voltage for differential input signals CK DQS DDR3 1066 1333 Symbol Parameter Unit Notes u Min Max Vix Differential Input Cross Point Voltage relative to Vnp 2 for CK CK uu 130 my 175 175 mV 1 Vix Differential Input Cross Point Voltage relative to Vpp 2 for DQS DQS 150 150 mV Note 1 Extended range for Vix is only allowed for clock and if single ended clock input signals CKand CK are monotonic have a single ended swing Vse VsEn Of at least Vpp 2 250 mV and the differential slew rate of CK CK is larger than 3 V ns 13 4 Slew Rate Definition for Single Ended Input Signals S
62. RTT Enabled in Mode Registers ODT Signal stable at 0 Pre charge Power Down Mode Slow Exi Precharge Power Down Current Fast Exit IDD2P1 CKE Low External clock On tCK CL see Table 30 on page 31 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pre charge Power Down Mode Fast Exit Precharge Quiet Standby Current IDD2Q CKE High External clock On tCK CL see Table 30 on page 31 BL 8 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Active Standby Current CKE High External clock On tCK CL see Table 30 on page 31 BL 82 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 34 on page 36 Data IO FLOATING DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 34 IDD3N Active Power Down Current IDD3P CKE Low External clock On tCK CL see Table 30 on page 31 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING DM stable at 0 Bank Activity all banks open Output Buffe
63. Registered DIMM DDR3 SDRAM DDR3 SDRAM Specification 240pin Registered DIMM based on 1Gb E die 72 bit ECC 78FBGA with Lead Free RoHS compliant INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS AND IS SUBJECT TO CHANGE WITHOUT NOTICE NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHER WISE TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL OGY ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS AS IS BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND 1 For updates or additional information about Samsung products contact your nearest Samsung office 2 Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where Product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply Samsung Electronics reserves the right to change products or specification without notice 1 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM Table Contents 1 0 DDR3 Registered DIMM Ordering Information naan 5 2 0 Key Feature 5 3 0 Address Configuration Me 5 4 0 Registered DIMM Pin Configurations Front
64. TDQS DQ 7 0 4 DQ 7 0 DQI7 0 e NE ae Qui vie V az So RS0A CS0 SDRAMs D 3 0 D8 Sells olo o o Z dedz s sog RS0B CS0 SDRAMs D 7 4 E st RS1A gt CS1 SDRAMs D 12 9 D17 re RS1B gt CS1 SDRAMs D 16 13 BA N 0 RBAIN O A gt BA N 0 SDRAMs D 3 0 D 12 8 D17 vtt we RBA N 0 B gt BA N 0 SDRAMs D 7 4 D 16 13 A N 0 RAIN 0 A gt A N 0 SDRAMs D 3 0 D 12 8 D17 RA N 0 B gt A N 0 SDRAMs D 7 4 D 16 13 RAS RRASA gt RAS SDRAMs D 3 0 D 12 8 D17 i RRASB gt RAS SDRAMs D 7 4 D 16 13 Vppspp Serial PD Thermal sensor with SPD CAS RCASA CAS SDRAMs D 3 0 D 12 8 D17 scL 4 2 RCASB gt CAS SDRAMs D 7 4 D 16 13 Vpp s L DO D17 e SDA WE R RWEA gt WE SDRAMs D 3 0 D 12 8 D17 EVENT aa M A2 E RWEB gt WE SDRAMs D 7 4 D 16 13 Vit CKEO G RCKEOA gt CKEO SDRAMs D 3 0 D8 I RCKEOB gt CKEO SDRAMs D 7 4 VREFCA DO D17 SA0 SA1 SA2 CKE1 s RCKE1A gt CKE1 SDRAMs D 12 9 D17 T RCKE1B gt CKE1 SDRAMs D 16 13 VREFDQ DO D17 ODTO E RODTOA gt ODTO SDRAMs D 3 0 D8 RODTOB gt ODTO SDRAMs D 7 4 Vss e D0 D17 OpT1 RODT1A gt ODT1 SDRAMs D 12 9 D17 RODT1A gt ODT1 SDRAMs D 16 13 cko I PCKOA gt CK SDRAMs D 3 0 D8 PCKOB gt CK SDRAMs D 7 4 Note IL PCK1A gt CK SDRAMs D 12
65. a DQS0 w DQS S DMO DQS9 w TDS po zit DQS9 TDQS T Note DQ 7 0 Ww DQ 7 0 E ae jee ee ven 1 DQ to I O wiring may be changed within a byte BERS els eos 2 ZQ resistors are 240 1 For all other resistor values refer to the appro Vit priate wiring diagram S0 RSO0A gt CS0 SDRAMs D 3 0 D8 S1 w RSOB gt CSO SDRAMs D 7 4 BA N 0 W RBA N 0 A gt BA N 0 SDRAMs D 3 0 D8 RBA N 0 B gt BA N 0 SDRAMs D 7 4 A N 0 RA N 0 A gt A N 0 SDRAMs D 3 0 D8 1 2 RA N 0 B gt A N 0 SDRAMs D 7 4 RAS WM R RRASA gt RAS SDRAMs D 3 0 D8 E RRASB gt RAS SDRAMs D 7 4 CAS WwW G RCASA gt CAS SDRAMs D 3 0 D8 mE I RCASB gt CAS SDRAMs D 7 4 WE S RWEA gt WE SDRAMs D 3 0 D8 T RWEB gt WE SDRAMs D 7 4 CKEQ E RCKEOA gt CKE0 SDRAMs D 3 0 D8 R RCKEOB gt CKE0 SDRAMs D 7 4 ODTO RODTOA gt ODTO SDRAMs D 3 0 D8 RODTOB gt ODTO SDRAMs D 7 4 CKO PCKOA gt CK SDRAMs D 3 0 D8 PCKOA gt CK SDRAMs D 7 4 CKO PCKOA gt CK SDRAMs D 3 0 D8 PCKOA gt CK SDRAMs D 7 4 PAR_IN Ws QERR Err_out RESET peu PST SDRAMs D 8 0 S 3 2 CKE1 ODT1 CK1 and CK1 are NC Unused register inputs ODT1 and CKE1 have a 330 ohm resistor to ground 110f53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 10 2 2GB 256Mx72 Module Populated as
66. a a Vtt Rev 1 06 July 2009 18 of 53 ELECTRONICS DDR3 SDRAM Registered DIMM adn VI Odd vesyg vlo Nlvay9a vlo Nlvya VL1qOdd V0 yOdd VO Ogd vOxoda V Add vsvoud VSVadd vesud adn VI OdV VLSdV VIO NlvgaV VIO NIvav VOlQONV VO3XOuVv VOMOdV vOxodv V3MWHv VSVOUV VSVaaV VO0SdV gt gt gt gt bd gt gt gt gt o NIva fo Nlv Io NIvg o NIv o Nlva lo Nlv o N va lo Nlv 1qo 1qo 1qo ao ED 30 390 3x9 o a 3 q 3 o 2 X X lt X XW A m A m A m A m _ SVo _ SVo SA Syo Q SVa Q SVa Q Sva Q SVa _ 2 _ 2 _ 2 Qo 2 q9Bag 2 ogs 2 gg 2 ggag 2 Nalaqa Nalaqaa Nalaqaa NN gt gt gt gt oNjva O NIV Io NIvg fo NIv o Nlva lo
67. alibration Timing Power up and RESET calibration time tZGinitl 512 512 512 nCK Normal operation Full calibration time tZQoper 256 256 256 nCK Normal operation short calibration time tZQCS 64 64 64 nCK 23 Reset Timing Exit Reset from CKE HIGH to a valid command XPR cuc ad RIA nice ue Self Refresh Timing Exit Self Refresh to commands not requiring a locked xs max 5nCK tRFC E max 5nCK tRFC 7 max 5nCK tRFC S DLL 10ns 10ns 10ns Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK min tDLLK min tDLLK min nCK Minimum CKE low width for Self refresh entry to exit 1CKESR tCKE min _ tCKE min 7 tCKE min E timing 1tCK 1tCK 1tCK Valid Clock Requirement after Self Refresh Entry 1CKSRE max 5nCK _ max 5nCK _ max 5nCK E SRE or Power Down Entry PDE 10ns 10ns 10ns Valid Clock Requirement before Self Refresh Exit tCKSRX max 5nCK 3 max 5nCK max 5nCK SRX or Power Down Exit PDX or Reset Exit 10ns 10ns 10ns ELECTRONICS 40 of 53 Rev 1 06 July 2009 Registered DIMM DDR3 SDRAM Timing Parameters by Speed Bin Cont Speed DDR3 800 DDR3 1066 DDR3 1333 Units Note Parameter Symbol MIN MAX MIN MAX MIN MAX Power Down Timing Exit Power Down with DLL on to any valid com max max max mand Exit Precharge Power Down with DLL tXP 3nCK 3nCK 3nCK 6ns frozen to command
68. and The address inputs also provide the op code during Mode Register Set commands DQ 63 0 CB 7 0 y o Data and Check Bit Input Output pins Active High Masks write data when high issued concurrently with input data DM 8 0 Vpp Vss Supply Power and ground for the DDR SDRAM input buffers and core logic V411 Supply Termination Voltage for Address Command Control Clock nets DQS 17 0 1 0 Positive Edge Positive line of the differential data strobe for input and output data DQS 17 0 1 0 Negative Edge Negative line of the differential data strobe for input and output data TDOS 17 9 TDQS TDGS is applicable for X8 DRAMs only When enabled via Mode Register A11 1 in MR1 DRAM will enable the same termination resistance function on TDQS TDQS that is applied to DQS DQS When dis TDQST17 9 OM abled via mode register A11 0 in MR1 DM TDQS will provide the data mask function and TDQS is not used X4 X16 DRAMs must disable the TDQS function via mode register A11 0 in MR1 SA 2 0 IN These signals are tied at the system planar to either Vss or Vppspp to configure the serial SPD EEPROM address range SDA vo This bidirectional pin is used to transfer data into or out of the SPD EEPROM A resistor must be connected from the SDA bus line to Vppspp on the system planar to act as a pull up SCL IN This signal is used to clock data into and out of the SPD EEPROM A resistor may be c
69. ariving 0 5 tek output enable time 3 4 Clock pre launch 0 25 CiN DATA Data Input Capacitance 15 25 CiN CLOCK Data Input Capacitance 2 3 pF CiN RST Reset Input Capacitance E 3 9 2 Clock driver Characteristics Tc TBD Symbol Parameter Conditions Vpp 1 5 0 075V Units Notes Min Max tji cc Cycle to cycle period jitter 0 40 ps tsTAB Stabilization time 6 us tayn Dynamic phase offset 50 50 ps tcksk Clock Output skew 50 ps ti per Yn Clock Period jitter 40 40 ps ti hper Half period jitter 50 50 DS T Qn Output to clock tolerance Standard 1 2 Clcok _ Output Inversion enabled 100 200 8 Pre Launch OUtput Inversion disabled 100 300 task1 Output clock tolerance 3 4 Clock Pre Launch Output Inversion eee is ae ps OUtput Inversion disabled 100 300 taynof Maximum re driven dynamic clock off set 80 80 ps ELECTRONICS 10 of 53 Rev 1 06 July 2009 Registered DIMM DDR3 SDRAM 10 0 Functional Block Diagram 10 1 1GB 128Mx72 Module Populated as 1 rank of x8 DDR3 SDRAMs au ium e cn noe ene 329ge usce PREMERE oroz
70. delay Power Down with tAONPD 2 85 2 85 2 85 ns DLL frozen Asynchronous RTT turn off delay Power Down with tAOFPD 2 85 2 85 2 85 is DLL frozen ODT turn on tAON 400 400 300 300 250 250 ps Tf RTT NOM and RTT WR turn off time from ODTLoff tAOF 0 3 07 0 3 07 03 0 7 tCK avg 8f reference RTT dynamic change skew tADC 0 3 0 7 0 3 0 7 0 3 0 7 tCK avg f Write Leveling Timing First Das pulse rising edge after tDQSS margining tWLMRD 40 2 40 _ 40 _ tCK 3 mode is programmed DQS DQS delay after tDQS margining mode is pro tWLDQSEN 25 _ 25 _ 25 CK 3 grammed Setup time for tDQSS latch tWLS 325 245 195 ps Write leveling hold time from rising DQS DQS cross tWLH 325 7 245 _ 195 _ ps ing to rising CK CK crossing Write leveling output delay tWLO 0 9 0 9 0 9 ns Write leveling output error tWLOE 0 2 0 2 0 2 ns 41 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 18 1 Jitter Notes Specific Note a Unit 1CK avg represents the actual tCK avg of the input clock under operation Unit nCK represents one clock cycle of the input clock counting the actual clock edges ex tMRD 4 nCK means if one Mode Register Set command is registered at Tm another Mode Register Set command may be registered at Tm 4 even if Tm 4 Tm is 4 x tCK avg tERR Aper min Specific Note b These parameters are measured from a command address signal CKE CS RAS CAS WE ODT BAO AO A1 etc transition edg
71. e to its respective clock signal CK CK crossing The spec values are not affected by the amount of clock jitter applied i e tJIT per tJIT cc etc as the setup and hold are relative to the clock signal crossing that latches the command address That is these param eters should be met whether clock jitter is present or not Specific Note c These parameters are measured from a data strobe signal DQS L U DQS L U crossing to its respective clock signal CK CK cross ing The spec values are not affected by the amount of clock jitter applied i e tJIT per tJIT cc etc as these are relative to the clock signal crossing That is these parameters should be met whether clock jitter is present or not Specific Note d These parameters are measured from a data signal DM L U DQ L U 0 DQ L U 1 etc transition edge to its respective data strobe signal DQS L U DQS L U crossing Specific Note e For these parameters the DDR3 SDRAM device supports tnPARAM nCK RU tPARAM ns tCK avg ns which is in clock cycles assuming all input clock jitter specifications are satisfied For example the device will support tnRP RU tRP tCK avg which is in clock cycles if all input clock jitter specifications are met This means For DDR3 800 6 6 6 of which tRP 15ns the device will support tnRP RU tRP tCK avg 6 as long as the input clock jitter specifications are met i e Precharge command at Tm and Active command at Tm
72. ective limits Vj DC max Vi DC min for single ended signals as well as the limitations for overshoot and undershoot Refer to overshoot and Undersheet Specification Allowed time before ringback tDVAC for CLK CLK and DQS DQS SE tDVAC ps IVinLaiw AC 350mV tDVAC ps IVinLai AC 300mV min max min max gt 4 0 75 175 3 4 0 57 170 3 0 50 167 2 0 38 163 B 1 8 34 162 1 6 29 161 6 1 4 22 159 z 1 2 13 155 1 0 0 150 1 0 0 150 25 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 13 3 3 Single ended Requirements for Differential Signals Each individual component of a differential signal CK DQS DQSL DQSU CK DQS DQSL or DQSU has also to comply with certain requirements for single ended signals CK and CK have to approximately reach VsEnmin Vsg max approximately equal to the ac levels Vin AC Vj AC for ADD CMD signals in every half cycle DQS DQSL DQSU DQS DQSL have to reach Vsgumin Vsg max approximately the ac levels Vi AC Vj AC for DQ signals in every half cycle proceeding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if Vij150 AC Vjj 150 AC is used for ADD CMD sig nals then these ac levels apply also for the single ended signals CK and CK Vpp or Vppo VSEH min
73. ee Address Command Setup Hold and Derating for single ended slew rate definitions for address and command signals See Data Setup Hold and Slew Rate Derating for single ended slew rate definitions for data signals tDH nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vi DC min and the first crossing of VREE 13 5 Slew Rate Definition for Differential Input Signals Input slew rate for differential signals CK CK and DQs DQS are defined and measured as shown in below Differential input slew rate definition Measured Description Defined b i From To i z T ViHaiWmn 7 ViLdiffmax Differential input slew rate for rising edge CK CK and DQS DQS Vii diffmax V iL4diffmin Fela Reale elta i c Vinaitimin ViLdiffmax Differential input slew rate for falling edge CK CK and DQS DQS ViHdiffmin ViLdiffmax elta i Note The differential signal i e CK CK and DQS DQS must be linear between these thresholds ViHdiffmin Vit diffmax delta TFdiff delta TRdiff Figure 5 Differential Input Slew Rate definition for DQS DQS and CK CK 27 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 14 0 AC and DC Output Measurement Levels 14 1 Single Ended AC and DC Output Levels Single Ended AC and DC output levels Symbol Parameter DDR3 1066 1333 Units Notes Vou DC DC output high measur
74. ement level for IV curve linearity 0 8 x Vbpo V Vom DC DC output mid measurement level for IV curve linearity 0 5 x Vbpo VoL DC DC output low measurement level for IV curve linearity 0 2 x Vbpo V Von AC AC output high measurement level for output SR V17 0 1 x Vppo V 1 Vou AC AC output low measurement level for output SR VTr 0 1 x Vppa V 1 Note 1 The swing of 0 1 x Vppa is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25Q to VTT Vppo 2 14 2 Differential AC and DC Output Levels Differential AC and DC output levels Symbol Parameter DDR3 1066 1333 Units Notes Vougi AC AC differential output high measurement level for output SR 0 2 X Vppa V 1 Voigig DC AC differential output low measurement level for output SR 0 2 x VDDQ V 1 Note 1 The swing of 0 2xVppq is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25Q to VTT Vppo 2 at each of the differential outputs 14 3 Single Ended Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo AC and Von AC for single ended signals as shown in below Single Ended Output slew rate definition
75. ess and Control 1 Ver Termination Voltage 4 VppsPp SPD Power 1 Total 240 The VDD and VDDQ pins are tied common to a single power plane on these designs 6 0 ON DIMM Thermal Sensor SCL 4 p SDA EVENT WP EVENT R1 00 SAO SA1 SA2 OS NN s SAO SA1 SA2 Temperature Sensor Characteristics Temperature Sensor Accuracy p Grade Range Units Notes Min Typ Max 75 lt Ta lt 95 0 5 1 0 B 40 lt Ta lt 125 1 0 2 0 C 20 lt Ta lt 125 2 0 3 0 Resolution 0 25 C LSB 7 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 7 0 Input Output Functional Description Symbol Type Polarity Function CKO Input jd Positive line of the differential pair of system clock inputs that drives input to the on DIMM Clock Driver Negative F CKO Input Edge Negative line of the differential pair of system clock inputs that drives the input to the on DIMM Clock Driver CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers CKE 1 0 Input Active High land output drivers of the SDRAMs Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation all banks idle or ACTIVE POWER DOWN row ACTIVE in any bank Enables the associated SDRAM command decoder when low and disables decoder when high When decoder is disabled new commands are ignored and previous operations continue These input signals also disable all outputs
76. except CKE and ODT of the register s on the DIMM when both inputs are high When both S 1 0 are high all register outputs except CKE ODT and Chip select remain in the previous state For modules supporting 4 ranks S 3 2 operate similarly to S 1 0 for a second set of reg ister outputs S 3 0 Input Active Low ODT 1 0 Input Active High On Die Termination control signals When sampled at the positive rising edge of the clock CAS RAS and WE define the operation to be exe RAS CAS WE Input Active Low cuted by the SDRAM VREFpo Supply Reference voltage for DQ0 DQ63 and CB0 CB7 VREFCA Supply Reference voltage for A0 A15 BAO BA2 RAS CAS WE SO S1 CKEO CKE1 Par In ODTO and ODT1 Selects which SDRAM bank of eight is activated BA 2 0 Input BAO BA2 define to which bank an Active Read Write or Precharge command is being applied Bank address also determines mode register is to be accessed during an MRS cycle Provided the row address for Active commands and the column address and Auto Precharge bit for Read Write commands to select one location out of the memory array in the respective bank A10 is sampled dur cl Input ing a Precharge command to determine whether the Precharge applies to one bank A10 LOW or all banks 107AP 9 0 p A10 HIGH If only one bank is to be precharged the bank is selected by BA A12 is also utilized for BL 4 8 id identification for BL on the fly during CAS comm
77. ification by adding an additional 100 ps of derating to accommodate for the lower alter nate threshold of 150 mV and another 25 ps to account for the earlier reference point 175 mv 150 mV 1 V ns 28 Pulse width of a input signal is defined as the width between the first crossing of VsEE DC and the consecutive crossing of VsEF DC 29 tDQSL describes the instantaneous differential input low pulse width on DQS DQS as measured from one falling edge to the next consecutive rising edge 30 tDQSH describes the instantaneous differential input high pulse width on DQS DQS as measured from one rising edge to the next consecutive falling edge 31 tDQSH act tDQSL act 1 tCK act with tXYZ act being the actual measured value of the respective timing parameter in the application 32 tDSH act tDSS act 1 tCK act with tXYZ act being the actual measured value of the respective timing parameter in the application 43 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 19 0 Physical Dimensions 19 1 128Mbx8 based 128Mx72 Module 1 Rank M393B2873EH1 Units Millimeters
78. ld pro gram 13 125 ns in SPD bytes for tAAmin Byte16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRC min Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36ns 13 125ns for DDR3 1333 CL9 and 48 125ns tRASmin tRPmin 35ns 13 125ns for DDR3 1600 CL 11 38 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 18 0 Timing Parameters for DDR3 800 DDR3 1066 and DDR3 1333 Timing Parameters by Speed Bin Speed DDR3 800 DDR3 1066 DDR3 1333 Units Note Parameter Symbol MIN MAX MIN MAX MIN MAX Clock Timing Minimum Clock Cycle Time DLL off mode iu ud 8 8 8 ns 6 Average Clock Period tCK avg See Speed Bins Table ps Clock Period tCK abs upsomm urpenmak ueemn upama tupeomim upsmax PS Average high pulse width tCH avg 0 47 0 53 0 47 0 53 0 47 0 53 tCK avg Average low pulse width tCL avg 0 47 0 53 0 47 0 53 0 47 0 53 tCK avg Clock Period Jitter tJIT per 100 100 90 90 80 80 ps Clock Period Jitter during DLL locking period tJIT per Ick 90 90 80 80 70 70 ps Cycle to Cycle Period Jitter JIT cc 200 180 160 ps Cycle to Cycle Period Jitter during DLL locking period tJIT cc Ick 180 160 140 ps Cumulative error acros
79. lf Refresh Temperature Range SRT set MR2 A7 0B for normal or 1B for extended temperature range f Refer to DRAM supplier data sheet and or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device 9 Read Burst type Nibble Sequential set MRO A 3 0B 31of53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 15 1 IDD SPEC Table M393B2873EH1 1GB 128Mx72 Module Symbol SN e pk Unit Notes DDR3 800 CL 6 DDR3 1066 CL 7 DDR3 1333 CL 9 IDDO 1215 1330 1425 mA IDD1 1350 1435 1560 mA IDD2PO slow exit 810 850 930 mA IDD2P1 fast exit 945 985 1065 mA IDD2N 990 1030 1155 mA IDD2Q 945 1030 1155 mA IDD3P fast exit 945 985 1065 mA IDD3N 1080 1165 1290 mA IDD4R 1485 1705 1965 mA IDD4W 1485 1795 2055 mA IDD5B 2070 2110 2280 mA IDD6 810 850 930 mA IDD7 2160 2335 2910 mA M393B5673EH1 2GB 256Mx72 Module Symbol cu ce p Unit Notes DDR3 800 CL 6 DDR3 1066 CL 7 DDR3 1333 CL 9 IDD0 1485 1570 1740 mA IDD1 1620 1705 1875 mA IDD2P0 slow exit 900 940 1020 mA IDD2P1 fast exit 1170 1210 1290 mA IDD2N 1260 1300 1470 mA IDD2Q 1170 1300 1470 mA IDD3P fast exit 1170 1210 1290 mA IDD3N 1440 1570 1740 mA IDD4R 1755 1975 2280 mA IDD4W 1755 2065 2370 mA IDD5B 2340 2380 2595 mA IDD6 900 940 1020 mA IDD7 2430 2605 3225 mA M iin Rev 1 06 July 2009 EL
80. minimum of 0 5 96 ZQCorrection of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the Output Driver Voltage and Temperature Sensitivity and ODT Voltage and Temperature Sensitivity tables The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters One method for calculating the interval between ZQCS commands given the temperature Tdriftrate and voltage Vdriftrate drift rates that the SDRAM is sub ject to in the application is illustrated The interval could be defined by the following formula ZQCorrection TSens x Tdriftrate VSens x Vdriftrate where TSens max dRTTdT dRONdTM and VSens max dRTTdV dRONdVM define the SDRAM temperature and voltage sensitivities For example if TSens 1 5 C VSens 0 1596 mV Tdriftrate 1 C sec and Vdriftrate 15 mV sec then the interval between ZQCS commands is calcu lated as 0 5 20 133 128ms 1 5 x 1 0 15 x 15 24 n from 13 cycles to 50 cycles This row defines 38 parameters 25 tCH abs is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge 26 tCL abs is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge 27 The tlS base AC150 specifications are adjusted from the tIS base spec
81. nge SRT Normal CKE Low External clock Off CK and CK LOW CL see Table 30 on page 31 BL 89 AL 0 CS Command Address Bank Address Data IO FLOATING DM stable at 0 Bank Activity Auto Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal FLOATING Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD nRRD nFAW CL see Table 30 on page 31 BL 88 AL CL 1 CS High between ACT and RDA IDD7 Command Address Bank Address Inputs partially toggling according to Table 39 on page 39 Data IO read data bursts with different data between one burst and the next one according to Table 39 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different addressing see Table 39 Output Buffer and RTT Enabled in Mode RegistersP ODT Signal stable at 0 Pattern Details see Table 39 RESET Low Current a un IDD8 RESET Low External clock off CK and CK LOW CKE FLOATING CS Command Address Bank Address Data IO FLOATING ODT Signal FLOATING a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RTT Wr enable set MR2 A 10 9 10B c Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable or 1B to enable feature e Se
82. o 3 9us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 Ob and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 0b 12 0 AC amp DC Operating Conditions 12 1 Recommended DC Operating Conditions SSTL 15 Rating Symbol Parameter Units Notes Min Typ Max Vpp Supply Voltage 1 425 1 5 1 575 V 1 2 VDDQ Supply Voltage for Output 1 425 1 5 1 575 V 1 2 Note 1 Under all conditions Vppa must be less than or equal to Vpp 2 Vppa tracks with Vpp AC parameters are measured with Vpp and Vppo tied together 22 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 13 0 AC amp DC Input Measurement Levels 13 1 AC amp DC Logic Input Levels for Single ended Signals Single Ended AC and DC Input for Command and Address Symbol Parameter COR UGG Sania Unit Notes Min Max Min Max Vin ca DC DC input logic high VREF 100 Vpp VREF 100 Vpp mV 1 Vit ca DC DC input logic low Vss VRE 100 Vss Vngr 100 mV 1 Vin ca AC AC input logic high VREF 175 Vngr 175 mV 1 2 ViL cA AC AC input logic low VREF 175 VREF 175 mV 1 2
83. ole oos IM SI588 g P La v t La pass w Das za DQS17 w pas za Dass Das za DQS17 w DOS za Dass w DQS S DQS17 w DOS E Dass w DQS E DQS17 w DQS s vss DM D2 zi vss DM D11 zi vss 4 DM D6 zi vss 1 DM D15 DQ 19 16 DQ 3 0 DQ 23 20 DQ 3 0 Q DQ 51 48 4 DQ 3 0 DQ 55 52 w DQ 3 0 eo e IE mE HIE m Wy Bz w az ul waz w Yaz Bebe ss 88 ele usse elle ssa Bese sss as La 3k ii b t La Dass w DQS za DQS17 w DQS za DQS8 w bas za DQS17 w DOS za Dass wY Das 5 DQS17 w DAS Dass DQS E DQS17 w DQS vss DM D1 zi vss DM D10 zi vss DM D7 zi vss 1 DM D16 a DQ 11 8 DQ 3 0 E 2 DQ 15 12 MM DGI 0 amp 2 DQ 59 56 C DQ 3 0 amp DQ 63 60 MM DQI3 0 o ml m gt o EM gt zy zy e Eu ee vez RE x EE PRERE eise ssss osse soos assis soot Bisse SSS 8S e gt t e DQS8 w Das za 3 DQS17 w Das za vt Dass w bas DQS17 w DQs g vss DM Do 2B vss DM D9 Z DQ 3 0 DQ 3 0 DQ 7 4 W DQ 3 0 lt S0 w I RS0A gt CSO SDRAMs D 3 0 D 12 8 D17 S m S RSOB gt CSO SDRAMs D 7 4 D 16 13 i UE Wie OZ m daz st
84. onnected from the SCL bus time to Vppspp on the system planar to act as a pull up EVENT d Active Low This signal indicates that a thermal event has been detected in the thermal sensing device The system ain should guarantee the electrical level requirement is met for the EVENT pin on TS SPD part V Suppl Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from DDSPD PPY 3 0 Volt to 3 6 Volt nominal 3 3V operation The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM When RESET IN low all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register s will be set to low level the Clock Driver will remain synchronized with the input clock Par In IN Parity bit for the Address and Control bus 1 Odd 0 Even Er Ot OUT Parity error detected on the Address and Control bus A resistor may be connected from Err_Out TEE ah bus line to Vpp on the system planar to act as a pull up TEST Used by memory bus analysis tools unused NC on memory DIMMs 8 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 8 0 Pinout comparison Based on Module Type Pin RDIMM UDIMM in Signal Notes Signal Notes Additional connection for Termination Voltage for 58 49 Var Address Command Control Clock nets NG Nobusad on UBIMNIS 420
85. oooozzs oecjizoooozzs Ixxi ala ac ac E ICICICE aia oc ac 1 Il 1 ft bass w Das za DQS4 w DAS za DQS8 w DAS g DQS4 Das S DM8 DQS17 w TDQS pg Z DM4DQS13 w TDQS p4 Zr DQS17 v TDQS EN i DQS13 w TDAS x CB 7 0 A DQ 7 0 S DQ 39 32 A DQ 7 0 S Were z wie z ease sts 5287 else ss T pass w T pas ZQ pass v pas ZQ Thermal sensor with SPD DQS3 Das S DQS5 w_ Das SCL DM3 DQS12 TDQS p3 Z I omspasi4 w TPQS ps ENG EVENT 4 EVENT A ASDA DQS12 TDQS lt DQS14 TDQS AO A1 A2 DQ 31 24 DQ 7 0 a DQ 47 40 DQ 7 0 e ess x UBSZ gleauxn b 2 SAO SA1 SA2 aisi SIS OOT Blasi 5 OO DQS2 pas za DQS6 w4 DOS za DQS2 w DOS S DQS6 w DQS E DM2 DQS11 TDQS p2 L DM6 DQS15 v IDOS pe 2 DQS11 TDQS i DQS15 TDAS i DQ 23 16 A DQ 7 0 s DQ 55 48 WW DQI 7 0 E else xxx B eu xx x82 V e Serial PD BHEE d ot laisse ISSO DDSED RE Vpp ee D0 D8 DQS1 w pas ZQ DQS7 w DQS za DQS1 w DAS S DQS7 w DAS g Vrr DM1 DQS10 w TDQS p4 Z L DM7DQS16 w TDOS p7 aL DQS10 TDQS lt gt DQS16 w TDAS EN 7 VREFCA DO D8 DQ 15 8 A DQ 7 0 S DQ 63 56 A DQ 7 0 wks Vi DO D8 z REFDQ lese sis 8 8S debe ss sss 1 I II I II Vss DO D8 vtt DQS0 w pas z
86. or 1V ns CMD ADD single ended slew rate and 2V ns CK CK differential slew rate Note for DQ and DM signals Vngr DC VREFDQ DC FOr input only pins except RESET VsEF DC VsEFCA DC See Address Command Setup Hold and Derating 17 tDS base and tDH base values are for 1V ns DQ single ended slew rate and 2V ns DQS DQS differential slew rate Note for DQ and DM signals VREF DC VREFDQ DC For input only pins except RESET VsEF DC VsEECA DC See Data Setup Hold and Slew Rate Derating 18 Start of internal write transaction is defined as follows For BL8 fixed by MRS and on the fly Rising clock edge 4 clock cycles after WL For BC4 on the fly Rising clock edge 4 clock cycles after WL For BC4 fixed by MRS Rising clock edge 2 clock cycles after WL 19 The maximum read preamble is bound by tLZDQS min on the left side and tDQSCK max on the right side See Device Operation 20 CKE is allowed to be registered low while operations such as row activation precharge autoprecharge or refresh are in progress but power down IDD spec will not be applied until finishing those operations 21 Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN min is satisfied there are cases where additional time such as tXPDLL min is also required See Device Operation 22 Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function 23 One ZQCS command can effectively correct a
87. r and RTT Enabled in Mode Registers ODT Signal stable at 0 Operating Burst Read Current CKE High External clock On tCK CL see Table 30 on page 31 BL 83 AL 0 CS High between RD Command Address Bank Address Inputs par IDD4R tially toggling according to Table 36 on page 37 Data IO seamless read data burst with different data between one burst and the next one according to Table 36 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 on page 14 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 36 IDDQ4R Operating Burst Read IDDQ Current optional Same definition like for IDD4R however measuring IDDQ current instead of IDD current Operating Burst Write Current CKE High External clock On tCK CL see Table 30 on page 31 BL 83 AL 0 CS High between WR Command Address Bank Address Inputs Dar IDD4W tially toggling according to Table 37 on page 38 Data IO seamless write data burst with different data between one burst and the next one according to Table 37 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 37 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Pattern Details see Table 37 Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 30 on page 31 BL 82 AL 0
88. s 2 cycles tERR 2per 147 147 132 132 118 118 ps Cumulative error across 3 cycles tERR 3per 175 175 157 157 140 140 ps Cumulative error across 4 cycles tERR 4per 194 194 175 175 155 155 ps Cumulative error across 5 cycles tERR 5per 209 209 188 188 168 168 ps Cumulative error across 6 cycles tERR 6per 222 222 200 200 177 177 ps Cumulative error across 7 cycles tERR 7per 232 232 209 209 186 186 ps Cumulative error across 8 cycles tERR 8per 241 241 217 217 193 193 ps Cumulative error across 9 cycles tERR 9per 249 249 224 224 200 200 ps Cumulative error across 10 cycles tERR 10per 257 257 231 231 205 205 ps Cumulative error across 11 cycles tERR 11per 263 263 237 237 210 210 ps Cumulative error across 12 cycles tERR 12per 269 269 242 242 215 215 ps Cumulative error across n 13 14 49 50 cycles tERR nper ERR DER t 0 SAn IIT ie due ps 24 Absolute clock HIGH pulse width tCH abs 0 43 0 43 0 43 tCK avg 25 Absolute clock Low pulse width tCL abs 0 43 0 43 0 43 tCK avg 26 Data Timing DQS DQS to DQ skew per group per access tDQSQ 200 150 125 ps 13 DQ output hold time from DQS DQS tQH 0 38 0 38 0 38 tCK avg 13 g DQ low impedance time from CK CK tLZ DQ 800 400 600 300 500 250 ps 13 14 f DQ high impedance time from CK CK tHZ DQ 400 300 250 ps 13 14 f VLA AG eaa tDS base 75 25 30 ps d 17 VCI CCS EE DOS retereneedo tDH base 150 3 100 65 ps d
89. s not requiring a locked DLL 7 5ns 7 5ns max max max ee REDL 10nCK 10nCK 10nCK 2 quiring 24ns 24ns 24ns max max max CKE minimum pulse width tCKE 3nCK 3nCK 3nCK 7 5ns 5 625ns 5 625ns Command pass disable delay tCPDED 1 1 nCK Power Down Entry to Exit Timing tPD tCKE min 9 tREFI tCKE min 9 tREFI tCKE min 9 tREFI tCK 15 Timing of ACT command to Power Down entry tACTPDEN 1 1 1 nCK 20 Timing of PRE command to Power Down entry tPRPDEN 1 1 1 nCK 20 Timing of RD RDA command to Power Down entry tRDPDEN RL 4 41 RL 4 1 RL 4 1 Timing of WR command to Power Down entry tWRPDEN WL 4 tWR _ WL 4 tWR E WL 4 tWR _ nCK 9 BL8OTF BL8MRS BL4OTF tCK avg tCK avg tCK avg Timing of WRA command to Power Down entry _ _ _ BL8OTF BL8MRS BL4OTF tWRAPDEN WL 4 WR 1 WL 4 WR 1 WL 4 WR 1 nCK 10 Timing of WR command to Power Down entry WL 2 tWR WL 2 tWR WL 2 tWR BL4MRS WWRPDEN ckayo tCK avg g tCK avg nck 9 Timing of WRA command to Power Down entry tWRAPDEN WL 2 WR 1 7 WL 2 WR 1 7 WL 2 WR 1 _ nCK 10 BL4MRS Timing of REF command to Power Down entry tREFPDEN 1 1 1 20 21 Timing of MRS command to Power Down entry tMRSPDEN tMOD min MOD min MOD min ODT Timing ODT high time without write command or with write ODTH4 4 4 _ 4 nCK command and BC4 ODT high time with Write command and BL8 ODTH8 6 6 6 nCK Asynchronous RTT turn on
90. ss DM D29 T DM D28 T DQ 39 36 A DQ 3 0 DQ 3 0 S els xEEB el SE xEES BESESSES8S BIEISE SIS 58 VSS wZQ VSS wZQ VSS VSS DQS14 DQS DQS DQS14 w Das z DQS 2 VSS TDM D31 3 DM D30 3 DQ 47 44 QAWDQIS 0 DQ 3 0 e E xe see el RE xEES Bsslss5 ot BESE SS SS VSS AZQ VSS AZQ VSS VSS DQS15 A DEAS DQS S DQS15 wDas Das E vss DM D33 DM D32 DQ 55 52 A DQ 3 0 S DQ 3 0 E ess xx vez el RE xis 82 BESE SSS 8 BISISE sse e e e VSS A ZQ VSS N ZQ VSS VSS DQS16 DQS DQS 5 DQS16 wDQs E DQS E vss DM D35 z DM D34 DQ 63 60 A DQ 3 0 DQ 3 0 elis xEB el SE xEES Bese SS S58 BISISE SS SSS e e La vit Serial PD Integrated Thermal sensor with SPD Serial PD SCL ScL c ees EVENT n EVENT n p ps ScL poses WP A0 A1 A2 A0 A1 A2 WP A0 A1 A2 SAO SA1 SA2 SA0 SA1 SA2 SAO SA1 SA2 Serial PD w integrated Thermal Sensor Serial PD no Thermal Sensor Thermal sensor with SPD Vppspp Serial PD SCL j Ae EVENT_n EVENT_n SP SDA Vo ee DO D71 A0 A1 A2 Vir SAO SA1 SA2 VREFcA DO D71 Serial PD w integrated Thermal Sensor V DO D74 REFDQ S Vss e e DO D71 Note 1 DQ to I O wiring may be changed
91. te Output slew rate is verified by design and characterization and may not be subject to production test Table 19 Differential Output slew rate DDR3 1066 DDR3 1333 Parameter Symbol Units Min Max Min Max Differential output slew rate SRQse 5 10 5 10 Vins Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output diff Singe ended Signals Vonaitt AC Vrr Voraif AC delta TFdiff delta TRdiff Figure 7 Differential Output Slew Rate definition 29 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 15 0 IDD specification definition Symbol Description Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 30 on page 31 BL 88 AL 0 CS High between ACT and PRE Command Address Bank Address Inputs partially toggling according to Table 32 on page 35 Data IO FLOATING DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 32 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 32 IDDO Operating One Bank Active Read Precharge Current CKE High External clock On tCK nRC nRAS nRCD CL see Table 30 on page 31 BL 82 AL 0 CS High between ACT RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 33 on page 36 DM stable
92. ulated as two physical ranks of x4 DDR3 SDRAMs O U O E RH n H m H n Hh Ef 2x 2 10 0 15 7 En Foo m um H H H ER LLA LLA I I I I I I I I 4 I I I I I I T O Address Command and Control lines The used device is 256M x4 DDR3 SDRAM FBGA DDR3 SDRAM Part NO KAB1G0446E HC Note Tolerances on all dimensions 0 15 unless otherwise specified 47 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 19 4 2 Heat Spreader Design Guide 1 FRONT PART Outside 133 15 x 0 2 pe 130 45 x 0 15 0 65 0 2 2 9 26 29 77 gt 31 4 rs F E T a i o 1 U E ww B N eS al o o A 2 i IS l d e N a 127 0 12 il Al CN 1 3 8 amp
93. ves the right to change products and specifications without notice 6 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM 5 0 Pin Description Pin Name Description Number Pin Name Description Number CKO Clock Input positive line 1 ODT 1 0 On Die Termination Inputs 2 CKO Clock Input negative line 1 DQ 63 0 Data Input Output 64 CKE 1 0 Clock Enables 2 CB 7 0 Data check bits Input Output 8 RAS Row Address Strobe 1 DQS 8 0 Data strobes CAS Column Address Strobe 1 DQS 8 0 Data strobes negative line E DM 8 0 WE Write Enable 1 DQS 17 9 Pipe di 9 TDQS 17 9 A DQS 17 9 Data strobes negative line Termination data S 3 0 Chip Selects j TDQS 17 9 strobes x AS Ob eM Address Inputs 2 14 RFU Reserved for Future Use 2 A 15 13 A10 AP Address Input Autoprecharge 1 EVENT ae TOF optional hardware temperature 1 L Memory bus test toll Not Connected and Not A12 BC Address Input Burst chop 1 TEST Usable on DIMMs 1 BA 2 0 SDRAM Bank Addresses 3 RESET Register and SDRAM control pin 1 SCL Serial Presence Detect SPD Clock Input 1 Vpp Power Supply 22 SDA SPD Data Input Output 1 Vss Ground 59 SA 2 0 SPD Address Inputs 3 VREFpo Reference Voltage for DQ 1 Par In Parity bit for the Address and Control bus 1 VREFCA Reference Voltage for CA 1 Er Out dd error found on the Addr
94. within a nibble 2 Unless otherwise noted resistor values are 15 5 3 See the wiring diagrams for all resistors associated with the command address and control bus 4 ZQ resistors are 240 1 For all other resistor values refer to the appropriate wiring diagram 20 of 53 Rev 1 06 July 2009 ELECTRONICS Registered DIMM DDR3 SDRAM S0 ARSOA gt CS1 SDRAMs D1 D3 D5 D7 D9 s2 w BRS2A gt CS1 SDRAMs D45 D47 D49 D51 D53 D19 D21 D23 D25 D27 D63 D65 D67 D69 D71 ARSOB gt CS1 SDRAMs D11 D13 D15 D17 BRS2B gt CS1 SDRAMs D37 D39 D41 D43 D29 D31 D33 D35 D55 D57 D59 D61 1 _w ARS1A gt CSO SDRAMs DO D2 D4 D6 D8 S3 BRS3A gt CS0 SDRAMs D44 D46 D48 D50 D52 D18 D20 D22 D24 D26 D62 D64 D66 D68 D70 ARS1B gt CS0 SDRAMs D10 D12 D14 D16 BRS3B gt CS0 SDRAMs D36 D38 D40 D42 D28 D30 D32 D34 D54 D56 D58 D60 BAIN 0 I ARBA N 0JA gt BA N 0 SDRAMs D 9 0 D 27 18 BA N 0 J BRBA N O A gt BA N 0 SDRAMs D 53 44 D 71 62 ARBAQ N 0 B gt BA N 0 SDRAMs D 17 10 D 35 28 BRBA N 0 B gt BA N 0 SDRAMs D 43 36 D 61 54 A N 0 v I ARA N 0JA gt A N 0 SDRAMs D 9 0 D 27 18 A N 0 w BRA N O A gt A N 0 SDRAMs D 53 44 D 71 62 ARAI N O B gt A N 0 SDRAMs D 17 10 D 35 28 BRA N 0 B gt A

Samsung M393B5670EH1-CF8 memory module

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