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Transcend Transcend DDR 200Pin SO-DIMM DDR-400 Non-ECC Memory

1. A Y ALOCACOCNONCOA CRANO TETRA TTR TAT HEN 1 am t IMAN i et ite L y G p 3 H gt K gt lt I gt ___ gt PCB 09 1220 Transcend Information Inc TS64MSD64V4J I 200PIN DDR400 Unbuffered SO DIMM 512MB With 64Mx8 CL3 Pin Identification Symbol Function A0 A12 BAO BA1 Address input Dimensions Side Millimeters Inches A 67 60 0 20 2 661 0 008 B 47 40 1 866 C 11 40 0 449 D 4 20 0 165 E 2 15 0 085 F 1 80 0 071 G 6 00 0 236 H 18 00 0 709 20 00 0 787 J 31 75 0 20 1 250 0 008 K 1 00 0 10 0 039 0 004 Refer Placement Transcend Information Inc DQ0 DQ63 Data Input Output DQS0 DQS7 Data strobe input output CK0 CK2 Clock Input CKO CK2 CKEO CKE1 Clock Enable Input CSO CS1 Chip Select Input RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DM0 DM7 Data in Mask VDD 2 5 Voltage power supply VREF Power Supply for Reference VDDSPD 2 5 Voltage Serial EEPROM Power Supply SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection 200PIN DDR400 Unbuffered SO DIMM TS64MSD64V4J I 512MB With 64Mx8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 VREF 69 VDD 137 VSS 02 VREF 70 VDD 13
2. 8 VSS 03 VSS 71 CBO 139 DQ35 04 VSS 72 CB4 140 DQ39 05 DQO 73 CB1 141 DQ40 06 DQ4 74 CB5 142 DQ44 07 DQ1 75 VSS 143 VDD 08 DQ5 76 VSS 144 VDD 09 VDD 77 DQS8 145 DQ41 10 VDD 78 DM8 146 DQ45 11 DQSO 79 CB2 147 DQS5 12 DMO 80 CB6 148 DM5 13 DQ2 81 VDD 149 VSS 14 DQ6 82 VDD 150 VSS 15 VSS 83 CB3 151 DQ42 16 VSS 84 CB7 152 DQ46 17 DQ3 85 DU 153 DQ43 18 DQ7 86 DU 154 DQ47 19 DQ8 87 VSS 155 VDD 20 DQ12 88 VSS 156 VDD 21 VDD 89 CK2 157 VDDD 22 VDD 90 VSS 158 CK1 23 DQ9 91 CK2 159 VSS 24 DQ13 92 VDD 160 CK1 25 DQS1 93 VDD 161 VSS 26 DM1 94 VDD 162 VSS 27 VSS 95 CKE1 163 DQ48 28 VSS 96 CKEO 164 DQ52 29 DQ10 97 A13 165 DQ49 30 DQ14 98 DU 166 DQ53 31 DQ11 99 A12 167 VDD 32 DQ15 100 A11 168 VDD 33 VDD 101 A9 169 DQS6 34 VDD 102 A8 170 DM6 35 CKO 103 VSS 171 DQ50 36 VDD 104 VSS 172 DQ54 37 CKO 105 A7 173 VSS 38 VSS 106 A6 174 VSS 39 VSS 107 A5 175 DQ51 40 VSS 108 A4 176 DQ55 41 DQ16 109 A3 177 D56 42 DQ20 110 A2 178 DQ60 43 DQ17 111 Al 179 VDD 44 DQ21 112 AO 180 VDD 45 VDD 113 VDD 181 DQ57 46 VDD 114 VDD 182 DQ61 47 DQS2 115 A10 183 DQS7 48 DM2 116 BA1 184 DM7 49 DQ18 117 BAO 185 VSS 50 DQ22 118 RAS 186 VSS 51 VSS 119 WE 187 DQ58 52 VSS 120 CAS 188 DQ62 53 DQ19 121 CSO 189 DQ59 54 DQ23 122 CS1 190 DQ63 55 DQ24 123 DU 191 VDD 56 DQ28 124 DU 192 VDD 57 VDD 125 VSS 193 SDA 58 VDD 126 VSS 194 SAO 59 DQ25 127 DQ32 195 SCL 60 DQ29 128 DQ36 196 SA1 61 DQS3 129 DQ33 197 VDDSPD 62 DM3 130 DQ37 198 SA2 63 V
3. SS 131 VDD 199 VDD 64 VSS 132 VDD 200 DU 65 DQ26 133 DQS4 66 DQ30 134 DM4 67 DQ27 135 DQ34 68 DQ31 136 DQ38 Transcend Information Inc 3
4. TS64MSD64V4J I 200PIN DDR400 Unbuffered SO DIMM 512MB With 64Mx8 CL3 Description The TS64MSD64V4J I is a 64M x 64bits Double Data Rate SDRAM high density for DDR400 The TS64MSD64V4J I consists of 8pcs CMOS 64Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages and a 2048 bits serial EEPROM on a 200 pin printed circuit board The TS64MSD64V4J I is a Dual In Line Memory Module and is intended for mounting into 200 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Industrial Temperature TA 40C to 85C e Power supply VDD VDDQ 2 6V 0 1V e Max clock Freq 200MHZ e Double data rate architecture two data transfers per clock cycle e Differential clock inputs CK and Ck e DLL aligns DQ and DGS transitions with CLK transition e Commands entered on each positive CLK edge e Auto and Self Refresh e Data I O transactions on both edge of data strobe e Serial Presence Detect SPD with serial EEPROM e SSTL 2 compatible inputs and outputs e MRS cycle with address key programs CAS Latency Access from column address 3 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Placement T HU

Transcend Transcend DDR 200Pin SO-DIMM DDR-400 Non-ECC Memory

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