Kingston Technology ValueRAM KVR1066D3Q8R7SK3/24G
Contents
1. read or write either on the fly using A12 or MRS e Bi directional Differential Data Strobe Internal self calibration Internal self calibration through ZQ pin RZQ 240 ohm 1 e On Die Termination using ODT pin e On DIMM thermal sensor Grade B e Average Refresh Period 7 8us at lower than TCASE 85 C 3 9us at 85 C lt TCASE lt 95 C e Asynchronous Reset e PCB Height 1 180 30 00mm double sided component Continued gt gt Kingston com Document No VALUERAM0857 001 A00 09 18 09 Page 1 continued ValueRAM MODULE DIMENSIONS Do M e s lt 2 ae S S S S gt S S BB 30 00 29 60x4 24 80x2 91 80x2 8 802 15 80x2 ei C R 0 65 MAX TYPICAL 11 00x2 8 00x2 p C 3 80 A 2 30x2 o 0 000 K 150 4 010 AET CHAMFER 0 50 X 45 DEG Ja D 4 PLACES SAT E S S o Kingston com Document No VALUERAM0857 001 A00 09 18 09 Page 22. kingston TECHIN OLOGY Memory Module Specifications Value i KVR1066D3Q8R7SK3 24G 24GB 8GB 1024M x 72 Bit x 3 pcs PC3 8500 CL7 Registered w Parity 240 Pin DIMM DESCRIPTION SPECIFICATIONS ValueRAM s KVR1066D3Q8R7SK3 24G is a kit of three 1024M CL IDD 7 cycles x 72 bit 8GB 8192MB DDR3 1066 CL7 SDRAM Synchronous Row Cycle Time tRCmin 50 63ns min DRAM registered w parity quad rank memory modules based on thirty six 256M x 8 bit DDR3 1066 FBGA components per Refresh to Active Refresh 160ns min Command Time tRFCmin module Total kit capacity is 24GB The SPDs are programmed to JEDEC standard latency 1066Mhz timing of 7 7 7 at 1 5V Each Row Active Time tRASmin 37 5ns min 240 pin DIMM uses gold contact fingers and requires 1 5V The Power 3 705 W operating per module electrical and mechanical specifications are as follows Z lt Z lt G3I oo es UL Rating 94V 0 FEATURES Operating Temperature 0 C to 85 C e JEDEC standard 1 5V 0 075V Power Supply Storage Temperature 55 C to 100 C e VDDQ 1 5V 0 075V e 533MHz fCK for 1066Mb sec pin e 8 independent internal bank e Programmable CAS Latency 6 7 8 9 e Programmable Additive Latency 0 CL 2 or CL 1 clock e Programmable CAS Write Latency CWL 6 DDR3 1066 8 bit pre fetch Burst Length 8 Interleave without any limit sequential with starting address O00 only 4 with tCCD 4 which does not allow seamless
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