Intel MFS5000SI
Contents
1. ccc cecccececeeeeeeeeeeeeeeeeseeeeeteeeteeeeeeanes 23 Table 12 Internal 9 pin Serial A Header Pin out OB 25 Table 13 External USB Connector Pin out ccc ccc eccecececeeeeceeeeeeeeseeesaeeseeeseeeeseeeeeeeesaeesaes 25 Table T4 RECOVERY JUINDONS 455 6 19s MT C T keiciebstatacdiecaeacons 2f Table 15 BMC Senso Sock hee o utei tea la v D eda p tu dct tuta e css pe MU I ALICE 32 Table T6 Analog Sensor nen e e EE 36 Table 17 POST Error Messages and Handlmg 37 Table 18 POST Error Beep Codes cccccccssscssscnsrecusecescavenasenssenssccurecurecurecusecussavenssscuresarecars 39 vi Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS OBIntroduction 1 Introduction This Technical Product Specification TPS provides board specific information detailing the features functionality and high level architecture of the Intel Compute Module MFS5000SI The Intef 5000 Series Chipsets Server Board Family Datasheet should also be referenced for more in depth detail of various board subsystems including chipset BIOS System Management and System Management software 1 1 Chapter Outline This document is divided into the following chapters Chapter 1 Introduction Chapter 2 Product Overview Chapter 3 Functional Architecture Chapter 4 Connector Header Locations and Pin outs Chapter 5 Jumper Block Settings2. Event Reading Type The Event Reading Type references values from the Event Heading Type Code Ranges and Generic Event Reading Type Codes tables in the PMI Specification Note that digital sensors are specific type of discrete sensors which have only two states Event Offset Triggers This column defines what event offsets the sensor generates For Threshold analog reading type sensors the BMC can generate events for the following thresholds Upper Critical Upper Non critical lower Non critical lower Critical The abbreviation U L is used to indicate that both Upper and Lower thresholds are supported A few sensors support only a subset of the standard four threshold triggers Note that even if a sensor does support all thresholds the SDRs may not contain values for some thresholds Consult Table 16 for information on the thresholds that are defined in the SDRs For Digital and Discrete type sensor event triggers the supported event generating offsets are listed The offsets can be found in the Generic Event Reading Type Codes or Sensor Type Codes tables in the IPMI Specification depending on whether the sensor event reading type is a generic or sensor specific response All sensors generate both assertions and deassertions of the defined event triggers The assertions and deassertions may or may not generate events into the System Event Log SEL depending on the sensor SDR settings Fault LED This colu
3. Appendix A Integration and Usage Tips Intel Compute Module MFS5000SI TPS 30 Appendix A Integration and Usage Tips When two processors are installed both must be of identical revision core voltage and bus core speed Mixed processor steppings is supported However the stepping of one processor cannot be greater than one stepping back of the other Processors must be installed in order CPU 1 is located near the edge of the server board and must be populated to operate the board Only Fully Buffered DIMMs FBD are supported on this server board Mixing memory type size speed rank and or memory vendors is not validated and is not supported on this server board Non ECC memory is not validated and is not supported in a server environment For a list of supported memory for this server board see the Inte Compute Module MFS5000SI Tested Memory List in the Intel Server Configurator Tool For a list of Intel supported operating systems add in cards and peripherals for this server board see the Intef Compute Module MFS5000SI Tested Hardware and Operating System List Only Dual Core processors 5100 sequence or Quad Core Intel Xeon processors 5300 or 5400 sequence with system bus speeds of 1066 1333 MHz are supported on this server board Previous generation Intel Xeon processors are not supported For best performance the number of DIMMs installed should be balanced across both memory branches For example a four DIMM
4. 180 28 Figure 3 Intel Compute Module MFS5000SI Hole and Component Positions Revision 1 4 Intel order number 15154 007 2BFunctional Architecture Intel Compute Module MFS5000SI TPS 3 Functional Architecture The architecture and design of the Intel Compute Module MFS5000SI is based on the Intel 5000 Chipset Family The chipset is designed for systems based on the Dual Core and Quad Core Intel Xeon processor 5000 sequence with system bus speeds of 667 MHz 1066 MHz and 1333 MHz The chipset is made up of two main components the Memory Controller Hub MCH for the host bridge and the Intel 6321ESB UO controller hub for the I O subsystem This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that make up the server board For more in depth detail of the functionality for each of the chipset components and each of the functional architecture blocks see the Intel 5000 Series Chipsets Server Board Family Datasheet B FB DIMM A1 FB DIMM A2 FB DIMM B1 FB DIMM B2 Gigabit Ethernet Mezzanine Card Intel 82571EB Gigabit Ethernet Controller PCle x4 2GB PCle x4 2GB FB DIMM C1 FB DIMM C2 FB DIMM D1 FB DIMM D2 Ben o o co E E o o xo b o N N o ESI x4 2GB RS232 Flash BIOS 4MB PCI 133MB s SDRAM LSI 1064e SAS PCle x8
5. Chapter 6 Product Regulatory Requirements Appendix A Integration and Usage Tips Appendix B BMC Sensor Tables Appendix C Post Error Messages and Handling Appendix D Supported Intel Modular Server System 1 2 Intel Compute Module Use Disclaimer Intel Modular Server components require adequate airflow to cool Intel ensures through its own chassis development and testing that when these components are used together the fully integrated system will meet the intended thermal requirements It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the system does not operate correctly when used outside any of their published operating or non operating limits Revision 1 4 1 Intel order number 15154 007 1BProduct Overview Intel Compute Module MFSSOOOSI TPS Product Overview The Intel Compute Module MFS5000SI is a monolithic printed circuit board with features that were designed to support the high density compute module market 2 1 Intel Compute Module MFS5O0O00SI Feature Set Processors 771 pin LGA sockets supporting one or two Dual Core or Quad Core Intel Xeon processors 5000 sequence with system bus speeds of 1066 MH
6. an error is logged to the SEL and the system cannot boot unless the error is resolved The user needs to replace the faulty part and restart the system The setup POST error Pause setting does not have any effect with this error Table 17 POST Error Messages and Handling en Processor 01 internal error IERR on last boot Processor 02 internal error IERR on last boot Baseboard management controller failed self test Revision 1 4 37 Intel order number 15154 007 Appendix C POST Error Messages and Handling Intel Compute Module MFSSOOOSI TPS 8500 Memory Component could not be configured in the selected RAS mode 8510 System supports a maximum of 16 GB of main memory Additional Major memory will not be counted This error is SSOOOV specific 8520 DIMM A 1 failed Self Test BIST Major DIMM A2 failed Self Test BIST DIMM A3 failed Self Test BIST DIMM A4 failed Self Test BIST DIMM B1 failed Self Test BIST DIMM B2 failed Self Test BIST DIMM B3 failed Self Test BIST Major Major Major Major Major Major we me gg m 4A j j Oe A o 7052 8528 DIMM C1 failed Self Test BIST Major BIST BIST BIST BIST DIMM C2 failed Self Test DIMM C3 failed Self Test DIMM CA failed Self Test DIMM D1 failed Self Test DIMM D2 failed Self Test BIST DIMM D3 failed Self Test BIST Major Major Major Major Major Major l Major _ AN AAN A ee Override jumper is
7. 4GB s USB2 OMB s High Speed I O PCle x4 2GB s SAS 300MB s 2 ea 2 Gb Ethernet Mid plane Connector Figure 4 Compute Module Functional Block Diagram Note The previous diagram uses the Intel 5000P MCH as a general reference designator for MCH components supported on this server board 6 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS 2BFunctional Architecture 3 1 Intel 5000P Memory Controller Hub MCH This section describes the general functionality of the memory controller hub as it is implemented on this server board The MCH is a single 1432 pin FCBGA package which includes the following core platform functions oystem Bus Interface for the processor subsystem Memory Controller PCI Express Ports including the Enterprise South Bridge Interface ESI FBD Thermal Management SMBus Interface Additional information about MCH functionality can be obtained from the Inte 5000 Series Chipsets Server Board Family Datasheet and the Inte 5000P Memory Controller Hub External Design Specification 3 1 1 System Bus Interface The MCH is configured for symmetric multi processing across two independent front side bus interfaces that connect to the Dual Core and Quad Core Intel Xeon processors 5000 sequence Each front side bus on the MCH uses a 64 bit wide 1066 or 1333 MHz data bus The 1333 MHz data bus is capable of transferring data at up to 10 66
8. BMC firmware update procedure through the Intel Modular Server Control software 8 Power down and remove AC power 9 Remove compute module from the server system 10 Move jumper from Enabled position pins 1 2 to Disabled position pins 2 3 11 Close the server system 12 Reinstall the compute module into the modular server chassis 13 Reconnect AC power and power up the compute module DE Or us Note Normal BMC functionality for example KVM monitoring and remote media is disabled with the force BMC update jumper set to the Enabled position The server should never be run with the BMC force update jumper set in this position and should only be used when the standard firmware update process fails This jumper should remain in the default disabled position when the server is running normally 5 1 3 System Status LED BMC Initialization When the AC power is first applied to the system and 5V STBY is present the Integrated BMC controller on the server board requires 15 20 seconds to initialize During this time the system status LED blinks alternating between amber and green and the power button functionality of the control panel is disabled preventing the server from powering up Once BMC initialization has completed the status LED stops blinking and power button functionality is restored The power button can then be used to turn on the server 28 Revision 1 4 Intel order number 15154 007 Intel Comp
9. DIMM D2 Single channel mode is only tested and supported with a 512 MB x8 FBDIMM installed in DIMM slot A1 The supported memory configurations must meet population rules defined above For best performance the number of DIMMs installed should be balanced across both memory branches For example a four DIMM configuration will perform better than a two DIMM configuration and should be installed in DIMM slots A1 B1 C1 and D1 An eight DIMM configuration will perform better then a six DIMM configuration Although mixed DIMM capacities size type timing and or rank between channels is supported by the memory controller mixed DIMMs configurations are not validated or supported with the Intel Compute Module MFS5000SI Refer to section 3 1 3 2 for supported and nonsupported DIMM configuration information 3 1 3 3 1 Minimum Non Mirrored Mode Configuration The server board is capable of supporting a minimum of one DIMM installed However for system performance reasons Intel s recommendation is that at least 2 DIMMs be installed The following diagram shows the recommended minimum DIMM memory configuration Populated DIMM slots are shown in Grey Revision 1 4 11 Intel order number 15154 007 2BFunctional Architecture Intel Compute Module MFS5000SI TPS Channel B Channel A Channel C Channel D Dr H TP02300 Figure 7 Recommended Minimum Two DIMM Memory Configuration Note The server board suppor
10. Mong D1h 01h Process FEh 7 Process Started Progress OEM OEM l Ss D2h D2h 8 Process Finished OK 9 Process Finished Fail Note 1 SDRs for these sensors are loaded only into the compute module SKU that supports these drives Reading these sensors in a SKU that does not support drives will return unknown data Error Device installed Attention ID LED Lit State Drive Backplane Present Z S 5 Is D D D C Sensor SDR Information This section describes the information that is entered into the SDRs The SDRs for all sensors will be set to generate events for both assertions and de assertions of all supported sensor offsets as listed in Table 15 Analog Sensor Thresholds Table 16 shows the thresholds set into the SDR records for the BMC s analog sensors These values are preliminary at the time of this writing Revision 1 4 35 Intel order number 15154 007 Appendix B Sensor Tables Intel Compute Module MFSSOOOSI TPS Table 16 Analog Sensor Thresholds Lower Non Upper Non BB 1 5V AUX ES Voltage 1 33V 1 65V mew qm poem sw ev BB BBO 0 9V Voltage 078V 78V 1 1 0200 LL NN 1 8 LA Processor 1 Core 1 2 3 4 92h Thermal Margin 93h Temperature N A N A N A N A PECI Processor 2 Core 1 2 3 4 94h Te ature Thermal Margin 95h P PECI Processor 1 2 9Ah Temperaire EN Thermal Ctrl 96 9Bh H EN 36 Revision 1 4 Intel order number 15154 007 Intel Compute Modu
11. Table 8 Power Connector Pin out J1A1 12Vdc L3 m5 Revision 1 4 21 Intel order number 15154 007 3BConnector Header Locations and Pin outs Intel Compute Module MFS5000SI TPS 4 3 1 0 Connector Pin out Definition 4 3 1 VGA Connector The following table details the pin out definition of the VGA connector J6K1 Table 9 VGA Connector Pin out J6A1 Pin SinalName Description Blue analog color signal B S 955 Gmm e 955 Gmmi e TPNG GONVES Jee a 4 3 2 I O Mezzanine Card Connector The server board provides an internal 120 pin Airmax connector J2B1 to accommodate high speed I O expansion modules which expands the I O capabilities of the server board The currently available I O mezzanine card for this server is the Intel Modular Server Accessory AXXGBIOMEZ a dual gigabit Ethernet card based on the Intel 82571EB The following table details the pin out of the Intel I O expansion module connector Table 10 120 pin I O Mezzanine Card Connector Pin out Lm pee in Sgwme Pn Sionainne GND GND m ONDER penne e me CC eS wwe Im 22 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS 3BConnector Header Locations and Pin outs gt 10 GND E10 SMB SCL 10 P12V PEA MCH TAP C0 PES CH TN CO 5 UJ TI UJ PE4 MCH TXP C1 PE5 MCH TXN C1 GND UJ Be PEAMCH T
12. configuration will perform better than a two DIMM configuration and should be installed in DIMM Slots A1 B1 C1 and D1 An eight DIMM configuration will perform better than a six DIMM configuration Normal Integrated BMC functionality for example KVM monitoring and remote media is disabled with the force BMC update jumper set to the enabled position pins 1 2 The server should never be run with the BMC force update jumper set in this position and should only be used when the standard firmware update process fails This jumper should remain in the default disabled position pins 2 3 when the compute module is running normally When performing the BIOS update procedure the BIOS select jumper must be set to its default position pins 2 3 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFSSOOOSI TPS Appendix B Sensor Tables Appendix B BMC Sensor Tables Table 15 lists the sensor identification numbers and information regarding the sensor type name supported thresholds and a brief description of the sensor purpose See the ntelligent Platform Management Interface Specification Version 2 0 for sensor and event reading type table information Sensor Type The Sensor Type references the values enumerated in the Sensor Type Codes table in the PMI Specification It provides the context in which to interpret the sensor for example the physical entity or characteristic that is represented by this sensor
13. in the BIOS setup The BIOS will configure Rank Sparing Mode The larger of the pairs DIMM A1 DIMM B1 and DIMM A2 DIMM B2 will be selected as the spare pair unit Note Use of identical memory is recommended with the Intel Compute Module MFS5000SI Mixing memory type size speed rank and or vendors is not validated and is not supported with this product Refer to section 3 1 3 2 for supported and nonsupported memory features and configuration information 3 1 3 4 2 2 Dual Branch Mode Sparing Dual branch mode sparing requires that all eight DIMM slots be populated and compliant with the following population rules DIMM A1 and DIMM B1 must be identical in organization size and speed DIMM A2 and DIMM B2 must be identical in organization size and speed DIMM C1 and DIMM D1 must be identical in organization size and speed DIMM C2 and DIMM D2 must be identical in organization size and speed DIMM A1 and DIMM A2 should be identical in organization size and speed See note below DIMM B1 and DIMM B2 should be identical in organization size and speed See note below DIMM C1 and DIMM C2 should be identical in organization size and speed See note below DIMM D1 and DIMM_D2 should be identical in organization size and speed See note below Sparing should be enabled in BIOS setup BIOS will configure Rank Sparing Mode The larger of the pairs DIMM A1 DIMM_B1 and DIMM A2 DIMM B2 and DIMM C1 DIMM_D1 and DIMM C2 DIMM_
14. of the system These interfaces are used in SERDES mode and do not require a Physical Layer Transceiver PHY These ports provide the server board with support for dual LAN ports designed for 10 100 1000 Mbps operation Each Network Interface Controller NIC drives a single LED located on the front edge of the board The link activity LED indicates network connection when on and Transmit Receive activity when blinking 3 4 1 Intel UO Acceleration Technology Intel UO Acceleration Technology I OAT moves network data more efficiently through Dual Core and Quad Core Intel Xeon processors 5000 sequence based servers for improved application responsiveness across diverse operating systems and virtualized environments Intel OAT improves network application responsiveness by unleashing the power of Dual Core and Quad Core Intel Xeon processors 5000 sequence through more efficient network data movement and reduced system overhead Intel multi port network adapters with Intel UOAT provide high performance I O for server consolidation and virtualization through stateless network acceleration that seamlessly scales across multiple ports and virtual machines Intel UOAT provides safe and flexible network acceleration through tight integration into popular operating systems and virtual machine monitors avoiding the support risks of third party network stacks and preserving existing network requirements such as teaming and failover 3 4 2 MA
15. 2 Connectors CPU 2 Socket o Intel 6321ESB UO Controller Hub LE CMOS Battery LG WO Werzaine Card Connect ma NN Figure 1 Component and Connector Location Diagram Revision 1 4 j Intel order number 15154 007 1BProduct Overview Intel Compute Module MFSSOOOSI TPS 2 2 2 External I O Connector Locations The following drawing shows the layout of the external I O components for the Intel Compute Module MFS50008SI O mmm Sie F DiE B Ne pors taz mem Figure 2 Intel Compute Module MFS5000SI Front Panel Layout 4 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFSSOOOSI TPS 2 2 3 6 35 246 13 89 25 32 36 75 48 18 5861 71 04 B247 117 15 152 04 165 19 2X 171 45 191 44 241 97 2X 255 54 282 89 10 16 618 5 AT Compute Module Mechanical Drawings e 3 K md Zei d M E x A x SES Sg SES Sg ri SES St SES Sg e et En e i SSO E l as ESSE n A A EHF S i Ch n 124 89 m e 2 es 176 40 o H cou T 208 76 208 35 5 ui S S J E S E E a e 7 8 T Ke Za aw x AN 313 76 TUTTI a N 357 34 387 24 ITT T 2X 383 54 iT tt TD TI T 386 24 1BProduct Overview 635 2 43 6 46 18 95 2X 21 24 33 15 47 02 2X 58 34 63 55 70 55 82 55 88 55 2K 103 78 410 44 2X 141 89 144 19 161 19
16. C Address Definition Each Intel Compute Module MFS5000SI has four MAC addresses assigned to it at the Intel factory During the manufacturing process each server board will have a white MAC address sticker placed on the board The sticker will display the MAC address in both barcode and alpha numeric formats The printed MAC address is assigned to NIC 1 on the server board NIC 2 is assigned the NIC 1 MAC address 1 Two additional MAC addresses are assigned to the Integrated Baseboard Management Controller BMC embedded in the Intel 6321ESB I O Controller Hub These MAC addresses are used by the Integrated BMC s embedded network stack to enable IPMI remote management over LAN BMC LAN Channel 1 is assigned the NIC1 MAC address 2 and BMC LAN Channel 2 is assigned the NIC1 MAC address 3 35 Super I O Legacy I O support is provided by using a National Semiconductor PC87427 Super I O device This chip contains all of the necessary circuitry to support the following functions GPIOs One serial port internal and used for debug only Wake up control 3 5 1 1 Serial Ports The server board provides one serial port through an internal DH 10 serial header J1B1 to be used for debug purposes only The serial interface follows the standard RS 232 pin out as defined in the following table Revision 1 4 19 Intel order number 15154 007 2BFunctional Architecture Intel Compute Module MFSSOOOSI TPS Table 6 Serial Header Pi
17. D2 will be selected as the spare pair units Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS 2BFunctional Architecture Note Use of identical memory is recommended with the Intel Compute Module MFS5000SI Mixing memory type size speed rank and or vendors is not validated and is not supported with this product Refer to section 3 1 3 2 for supported and nonsupported memory features and configuration information Revision 1 4 15 Intel order number 15154 007 2BFunctional Architecture Intel Compute Module MFSSOOOSI TPS 3 2 Intel 6321 SB I O Controller Hub The Intel 6321ESB I O Controller Hub is a multi function device that provides four distinct functions an IO Controller a PCI X Bridge a Gb Ethernet Controller and an Integrated Baseboard Management Controller BMC Each function within the Intel 6321ESB I O Controller Hub has its own set of configuration registers Once configured each appears to the system as a distinct hardware controller A primary role of the Intel 6321ESB UO Controller Hub is to provide the gateway to all PC compatible I O devices and features The server board uses the following Intel 6321ESB I O Controller Hub features Dual GbE MAC Integrated Baseboard Management Controller BMC Universal Serial Bus 2 0 USB interface LPC bus interface PC compatible timer counter and DMA controllers APIC and 8259 interrupt controller Power manage
18. EK Design Support The compute module complies with Intel s Common Enabling Kit CEK processor mounting and heatsink retention solution The compute module ships with a CEK spring snapped onto the underside of the server board beneath each processor socket The heatsink attaches to the CEK over the top of the processor and the thermal interface material TIM For the stacking order of the chassis CEK spring server board TIM and heatsink see the following figure The CEK spring is removable allowing for the use of non Intel heatsink retention solutions Note The processor heatsink and CEK spring shown in the following diagram are for reference purposes only The actual processor heatsink and CEK solutions compatible with this generation server board may be of a different design Heatsink assembly Thermal interface material TIM 9 Server board 9 CEK spring 9 Chassis gt Figure 5 CEK Processor Mounting 3 1 3 Memory Subsystem The MCH masters four fully buffered DIMM FBD memory channels FBD memory utilizes a narrow high speed frame oriented interface referred to as a channel The four FBD channels are organized into two branches of two channels per branch Each branch is supported by a separate memory controller The two channels on each branch operate in lock step to increase FBD bandwidth On the server board the four channels are routed to eight DIMM slots and ar
19. Ed Tl TI J1 J2 J3 J4 C C EE c K1 K2 K3 K4 5 reserved N reserved Co 8 L1 L2 L3 L4 reserved GND FM BL SLOT ID1 GND FM BL PRES N zl OI Oil A ol N gt CO O1 A j N gt CO O 4 3 4 Serial Port Connector The server board provides one internal 9 pin Serial A port header J1B1 The following table defines the pin out See 24 Intel order number 15154 007 Revision 1 4 Intel Compute Module MFS5000SI TPS Table 6 for the pin out of the serial header 3BConnector Header Locations and Pin outs Table 12 Internal 9 pin Serial A Header Pin out J1B1 Pin Signal Name SPA DCD SPA DSR SPA SIN L SPA RTS SPA SOUT N SPA CTS sam oo e SPAR s 9 4 3 5 USB 2 0 Connectors Description DCD carrier detect DSR data set ready RXD receive data RTS request to send TXD transmit data CTS clear to send DTR data terminal ready RI ring Indicate Ground The following table details the pin out of the external USB connectors J4K1 J4K2 found on the front edge of the server board Table 13 External USB Connector Pin out Pin Signal Name USB OCH FB 1 USB PWR 2 USB PZN FB 2 DATALO Differential data line paired with DATAHO Em USB P P FB 2 DATAHO Differential data line paired with DATALO 1 2 3 Revision 1 4 25 Intel order number 15154 007 4BJumper Block Settings Intel Compute Module
20. GB s The MCH supports a 36 bit wide address bus capable of addressing up to 64 GB of memory The MCH is the priority agent for both front side bus interfaces and is optimized for one processor on each bus 3 1 2 Processor Support The Intel Compute Module MFS5000SI supports one or two Dual Core Intel Xeon processors 5100 sequence or Quad Core Intel Xeon processors 5300 and 5400 sequence with system bus speeds of 1066 MHz and 1333 MHz Previous generations of the Intel Xeon processor are not supported in the Intel Compute Module MFS50008SlI To see a list of the latest processors that have been validated on this product refer to http support intel com support motherboards server MFS50008Sl and select the Supported Processors List 3 1 2 1 Processor Population Rules When two processors are installed both must be of identical revision core voltage and bus core speed Mixed processor steppings is supported in N and N 1 configurations only When only one processor is installed it must be in the socket labeled CPU1 The other socket must be empty The board is designed to provide up to 115 A of current per processor Processors with higher current requirements are not supported When using a single processor configuration a terminator is not required in the second processor socket Revision 1 4 7 Intel order number 15154 007 2BFunctional Architecture Intel Compute Module MFSSOOOSI TPS 3 1 2 2 Common Enabling Kit C
21. I design 3 2 1 1 PCI32 32 bit 33 MHz PCI Bus Segment All 32 bit 33 MHz PCI I O is directed through the Intel 6321ESB I O Controller Hub The 32 bit 33 MHz PCI segment created by the Intel 6321ESB UO Controller Hub is known as the PCI32 segment The PCI32 segment supports the following embedded device 2D Graphics Accelerator ATI ES1000 Video Controller 3 2 1 2 PXA 64 bit 133MHz PCI X Bus Segment One 64 bit PCI X bus segment is directed through the Intel 6321ESB I O Controller Hub PCI X segment PXA is not used in the Intel Compute Module MFS5000SI design 3 2 1 3 DEI One x4 PCI Express Bus Segment One x4 PCI Express bus segment is directed through the Intel 6321ESB UO Controller Hub PCI Express segment PE1 is not used in the Intel Compute Module MFS5000SI design 3 2 1 4 PE2 One x4 PCI Express Bus Segment One x4 PCI Express bus segment is directed through the Intel 6321ESB UO Controller Hub PCI Express segment PE2 supports the LSI 1064e SAS controller 3 2 1 5 DEA PES Two x4 PCI Express Bus Segments Two x4 PCI Express bus segments are directed through the MCH PCI Express segments PE4 and PE5 support the optional I O mezzanine card 3 2 1 6 DEG PE7 Two x4 PCI Express Bus Segments Two x4 PCI Express bus segments are directed through the MCH PCI Express segments PE6 and PE7 are not used in the Intel Compute Module MFS5000Sl1 design 3 2 2 Serial ATA Support The Intel 6321ESB I O Controll
22. Intel Compute Module MFS5000SI Technical Product Specification Intel order number E15154 007 Revision 1 4 June 2009 Enterprise Platforms and Services Division BOARD inside Revision History Intel Compute Module MFS5000SI TPS Revision History Number July 2007 Initial release August 2007 096 Updated September 2007 Updated February 2008 Updated November 2008 Updated May 2009 Updated June 2009 Updated supported memory configurations Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no respons
23. MFSSOOOSI TPS 5 Jumper Block Settings The server board has several 3 pin jumper blocks that can be used to configure protect or recover specific features of the server board Pin 1 on each jumper block is denoted by an or Y 5 1 Recovery Jumper Blocks BIOS Bank Select EE Default BOOT FROM EMERGENCY BIOS IMAGE J3A3 en pm pn pn pn pen pn pn pn pen pn pen pn pen vn pen n en PASSWORD CLR ge Default 210115 CLEAR O 3 0 PASSWORD J4A1 BMC Force Update y 2 3 C Enabled Default dey PA Pa pa pa pa pap Disabled i J7A1 CMOS CLR CLEAR Deu ED En i J1F2 AF002220 i TET V LI x CAAS J H J i9 i9 i9 i9 Figure 10 Recovery Jumper Blocks 26 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFSSOOOSI TPS 4BJumper Block Settings Table 14 Recovery Jumpers JumperName Pins What happens at system reset J7A1 BMC Force BMC Firmware Force Update Mode Enabled Update 23 BMC Firmware Force Update Mode Disabled Default J4A1 Password KE These pin
24. Om PS Go ND O10 aA P WN Unknown Ticket SOL Session Inactive 1 SOL Session Active Yes Yes Digital Discrete State asserted 03h Sensor Specific Uncorrectable ECC 6Fh Sensor Specific Bus uncorrectable Error 6Fh Thresh None None Yes 01h Thresh None None Yes 01h 0 IERR No Z O No Fault No Z O O O Sensor Specific 1 Thermal trip Yes 6Fh Yes T Presence Upper Non critical Thresh 01h Upper Critical Upper Non critical Thresh 01h Upper Critical Intel order number 15154 007 Fault Fault Fault Z O EMEN O O Revision 1 4 Intel Compute Module MFS5000SI TPS Sensor Type Appendix B Sensor Tables Event Reading Event Offset Triggers Processor 1 2 Thermal Ctrl 96 Processor 1 2 VRD Hot Proc Max Thermal Margin Processor 1 2 Vcc Out of Range CPU Population 9Ah Temp 9Bh Oth s rem Des 9Dh Oth 05h Temp Thresh 9Fh 01h 01h AOh Digital Mh Voltage Discrete 05h BOh Upper Critical 1 Limit exceeded Limit exceeded State De asserted 1 State Asserted Fault Fault None Fault None Fault Digital Processor 07h Discrete O3h Mezzanine Slot Conne Sensor Card ctor Specific Present 21h 6Fh Cth Sd Fault State Active Drive Slot Digital Device Absent C2h Discrete ODh 08h 1 Device Present Sensor Drive 1 2 a o SE Specific 0 Present 6Fh Slot ID C5h OEM Thresh
25. Os 5 59748 08 CODING CIOES eebe 25 5 JUMPEE lee E dn eomm 26 5 1 ROCOVErY Jutriper BIOCKS moaten a a a S 26 5 1 1 CMOS Clear and Password Reset Usage Procedure nannnnnnannennnnnnennennnneneennnne 27 5 1 2 BMC Force Update Procedure inana e bw d te e tcn e oe 2f 5 1 3 System Status LED BMC JInmtalzaton 28 6 Product Regulatory Requirements eegene NEGER EEN 29 6 1 Product Regulatory Heouirements 29 6 2 Product Regulatory Compliance and Safety Markings 29 6 3 Product Environmental Ecology Requirements naannannnnnnennennnnnnrnnnnrenrrnnrnnenne 29 6 4 Product Environmental Ecology Markings aanaannannnnnnnnnnnnnnnnnnnnnrnnnnnrnnrrnnrrennnne 29 Appendix A Integration and Usage TIDS i usbssux enisi avi ux uu aL Sca bru dual asa Fauna Ra EE Ee capo 30 Appendix B BME Sensor Tables ao cst uaria VES UU Macs Goa Queso dE 31 Appendix C POST Error Messages and Handling eese 37 Appendix D Supported Intel Modular Server System 11eee eese eene nnne 40 Secr EE 41 KEE e Reine 44 WM Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS List of Figures List of Figures Figure 1 Component and Connector Location Diagram seeseeeseeeeeereeenen nn 3 Figure 2 Intel Compute Module MFS5000SI Front Panel Layout 4 Figure 3 Intel Compute Mo
26. XP C2 7 GND Bo CLK wow PCIE N rs oND SCH GND GND Card ID O XE P2 D RXP DEA MCH TXN CO GND XE P2 D TXN GND P5V XE P2 C RXP PE4 MCH TXN C1 XE P2 C TXN PE4 MCH TXN C2 XE P2 B TXN PEA MCH TXN C3 Go E D GND 7 DB GND 5 7 D fse UJ c Q O D D D Al AL NI AL AL A o A J ie J Jo 4 3 3 Midplane Signal Connector The server board connects to the midplane through a 96 pin Airmax connector J3A1 power is J1A1 to connect the various I O management and control signals of the system Table 11 96 pin Midplane Signal Connector Pin out Pin Signal Name Pin Signal Name Pin Signal Name XE P1 A RXP XE P2 D RXN GND END Revision 1 4 Intel order number 15154 007 23 3BConnector Header Locations and Pin outs Intel Compute Module MFSSOOOSI TPS Di Z E6 XE P2 B TXP l6 SAS P2 TXN E7 XE P2 A RXN GND 8 XE P2 A TXP Fm bl slot id5 F1 GND SMB SCL A F2 XE P2 D TXN GND F3 GND FM BL SLOT ID2 F4 12V BL PWR ON GND F GND reserved XE P2 B TXN GND GND reserved XE P2 A TXN GND SAS P1 RXP SMB SDA A GND FM BL SLOT IDO XE P2 C RXP FM BL SLOT ID3 GND FM BL SLOT ID4 SAS P2 RXP reserved GND spare GND SAS P1 RXN SAS P1 TXP A7 XE P1 D RXP GND XE P1 A RXN XE P1 A TXP XE P1 B RXN XE P1 B TXP XE P1 C RXN XE P1 C TXP XE P1 D RXN XE P1 D TXP GND XE P1 A TXN GND XE P1 B TXN GND XE P1 C TXN GND XE P1 D TXN D1 XE P2 D RXP H1 D2 GND H2 wj
27. cal Fault BB 5V 17h Voltage ew U L Critical Fault U L Non critical Fault BB 12V 18h Voltage Thresh AUX 01h U L Critical Fault U L Non critical Fault BB 0 9V 19h Voltage e U L Critical Fault Status LED Sensor Type State N 2 Digital pias 1Ah Voltage Discrete 1 Limit exceeded Fault SIO 05h Revision 1 4 Intel order number 15154 007 Appendix B Sensor Tables Read Standby Yes Yes H Yes Yes Z O Yes Z O O Z O Z O Yes Yes Yes Yes Yes No Yes No Yes A No Yes Yes 33 Appendix B Sensor Tables Sensor Type Hot Swap Hot Swap 20h 2Ch OEM d Session COh OEM COh Session SMI Error Critical Critical Int 42h Interrupt 13h DIMM 1 8 50h Temp Temp 57h Oth Temp DIMM Max 5Fh p Temp 01h Processor Processor 1 2 Status 91h Oh Processor 1 Core 1 2 3 4 92h Temp 95h 01h 96h Temp 99h 01h Timeout F3h co e 3 Thermal Margin PECI Processor 2 Core 1 2 3 4 Thermal Margin PECI 34 Intel Compute Module MFSSOOOSI TPS Event Reading Event Offset Triggers Type Status LED Read Rearm Standby Inactive Activation Required Sensor Specific 6Fh Activation In Progress Active Deactivation Required Deactivation in Progress Pending Established Ended Normally Ticket Expiration Yes Yes Lost Heartbeat Forcibly Terminated Oo
28. dule MFS5000SI Hole and Component Positions 5 Figure A Compute Module Functional Block Diagram ccccccccceccceeceeeeceeeeseeeeseeeseeeeaeeseeeeaes 6 Figure 5 CEK Processor MOUNMUNG EEN 8 PIQUE Os Memory AY OUN NOE T ER 9 Figure 7 Recommended Minimum Two DIMM Memory Configuration 12 Figure 8 Recommended Four DIMM Contgouraton 13 Figure 9 Single Branch Mode Sparing DIMM Configuration cccccccececeecceeeeeeeeeaneeseeeeauees 14 Figure 10 Recovery Jumper Blocks nnnaan0nnannnnnnnnnnnnnnnnnanrnnnnronennrnnrnrrnnrnrenrrnrrnernrrnenrrnnrsrrnnnne 26 Figure 11 Intel Modular Server System MES Sp 40 Revision 1 A V Intel order number 15154 007 List of Tables Intel Compute Module MFS5000SI TPS List of Tables Table 1 I C Addresses for Memory Module MP 9 Table 2 Maximum 8 DIMM System Memory Configuration x8 Single Rank 10 Table 3 Maximum 8 DIMM System Memory Configuration x4 Dual Rank 10 Table A PCI Bus Segment Characherstce 16 ee Vdeo EE RTT 18 Table o eral Header PIN OU Uden EE 20 Table 7 Board Connector WAU IK EE 21 Table 8 Power Connector Pinout JT A T EE 21 Table 9 VGA Connector PInsout IOAN osa tia etia t pe Eau es ha tee uta oz o De cR edu idu 22 Table 10 120 pin I O Mezzanine Card Connector bm out 22 Table 11 96 pin Midplane Signal Connector Pin out
29. e Password and or CMOS is now cleared and can be reset by going into the BIOS setup i aM C E ER dim Note Removing AC power before performing the CMOS Clear operation will cause the system to automatically power up and immediately power down after the reset procedure has been completed and AC power is re applied Should this occur remove the AC power cord again wait 30 seconds and re install the AC power cord Power up the system and proceed to the F2 BIOS Setup utility to reset desired settings 5 1 2 BMC Force Update Procedure When performing a standard BMC firmware update procedure the update utility places the BMC into an update mode allowing the firmware to load safely onto the flash device In the unlikely event that the BMC firmware update process fails due to the BMC not being in the proper update state the server board provides a BMC Force Update jumper J7A1 which will force the BMC into the proper update state The following procedure should be followed in the event the standard BMC firmware update process fails 1 Power down and remove AC power 2 Remove compute module from modular server chassis 3 Open compute module Revision 1 4 27 Intel order number 15154 007 4BJumper Block Settings Intel Compute Module MFSSOOOSI TPS Move jumper from Default operating position pins 2 3 to Enabled position pins 1 2 Close the compute module Reconnect AC power and power up the compute module Perform standard
30. e capable of supporting registered DDR2 533 and DDR2 667 FBDIMM memory stacked or unstacked Peak theoretical memory data bandwidth is 6 4 GB s with DDR2 533 and 8 0 GB s with DDR2 667 On the Intel Compute Module MFS5000SI a pair of channels becomes a branch where Branch 0 consists of channels A and B and Branch 1 consists of channels C and D FBD memory channels are organized into two branches for RAID 1 mirroring support 8 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS 2BFunctional Architecture Channel C Channel D Channel B Channel A NN Lu Seen VS WS W l N W NNS W gt G a US AS TP02299 Figure 6 Memory Layout To boot the system the system BIOS on the server board uses a dedicated DC bus to retrieve DIMM information needed to program the MCH memory registers The following table provides the IC addresses for each DIMM slot Table 1 I C Addresses for Memory Module SMB DIMM A2 OxA2 DIMM B1 OxAO DIMM C2 OxA2 Dumez om2 3 1 3 1 Memory RASUM Features The MCH supports several memory RASUM Reliability Availability Serviceability Usability and Manageability features These features include the Intel x4 Single Device Data Correction Intel x4 SDDC for memory error detection and correction Memory Scrubbing Retry on Correctable Errors Memory Built In Self Test DIMM Sparing and Memory Mirroring For more information regarding these f
31. eatures see the Intel 5000 Series Chipsets Server Board Family Datasheet 1 DIMM Sparing and Memory Mirroring features will be made available post production launch with a BIOS update Revision 1 4 9 Intel order number 15154 007 2BFunctional Architecture Intel Compute Module MFSSOOOSI TPS 3 1 3 2 Supported and Nonsupported Memory Configurations The server board design supports up to eight DDR2 533 or DDR2 667 Fully Buffered DIMMs FBD memory Use of identical DIMMs with this server board is recommended The following tables show the maximum memory configurations supported using the specified memory technology Table 2 Maximum 8 DIMM System Memory Configuration x8 Single Rank DRAM Technology x8 Single Maximum Capacity Maximum Capacity 368 Mb Mirrored Mode Non Mirrored Mode 256Mb 1GB 2GB 512 Mb 1024 Mb 2048 Mb 16 GB Table 3 Maximum 8 DIMM System Memory Configuration x4 Dual Rank DRAM Technology x4 Dual Maximum Capacity Mirrored Maximum Capacity Rank Mode Non Mirrored Mode 256 Mb CGB 512 Mb 16 GB 1024 Mb 16 GB 32 GB 2048 Mb 16 GB 32 GB The following configurations are not validated or supported with the Intel Compute Module MFS5000SI DDR2 DIMMs that are not fully buffered are NOT supported on this server board DDR2 533 memory is not planned to be validated on this product Mixing memory type size speed and or rank is not validated and is not support
32. ed Mixing memory vendors is not validated and is not supported Non ECC memory is not validated and is not supported in a server environment For a complete list of supported memory for the Intel Compute Module MFS5000SI refer to the Tested Memory List published in the Intel Server Configurator Tool 3 1 3 3 DIMM Population Rules and Supported DIMM Configurations DIMM population rules depend on the operating mode of the memory controller which is determined by the number of DIMMs installed DIMMs must be populated in pairs DIMM pairs are populated in the following DIMM slot order A1 and B1 C1 and D1 A2 and B2 C2 and D2 DIMMs within a given pair must be identical with respect to size speed and organization Intel supported DIMM configurations for this server board are shown in the following table 10 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS 2BFunctional Architecture Supported and Validated configuration Slot is populated Supported but not validated configuration Slot is populated Slot is not populated Mirroring Y Yes and indicates that configuration supports Memory Mirroring Sparing Y x Yes and indicates that configuration supports Memory Sparing Where x 0 Sparing supported on BranchO only 1 Sparing supported on Branch1 only 0 1 Sparing supported on both branches Channel A Channel B Channel C Channel D DIMM A1 DIMM A2 DIMM B1 DIMM B2 DIMM C1 DIMM C2 DIMM D1
33. el Compute Module Use Disclaimer c EE 2 1 Intel Compute Module MFS5000SI Feature Set 2 2 Compute Module E e EE 22 Connector and Component Locations sssaaa a aaa 2 2 2 External I O Connector Locations ccccceccceecesececeeeeeeeeceneeseeeseeessaeeseeessaeesaaes 2 2 9 Compute Module Mechanical Drawings aannannannnnnnnnnennnnnenrnnnnnnrrnnnnnrnneneerenee 3 Functional e gn te di 3 1 Intel 5000P Memory Controller Hub MCH eene 3 1 1 System ER an e 3 1 2 PFOCCSSOl SUID DOM EE 3 1 3 Memory SUDSY SUC EE 3 2 Intel 6321ESB I O Controller Hub 3 2 1 Keele WEE oue oelal ATA SUBDO gener re nr da uet EH Mb Fm EM i ID 3 2 3 Parallel ATA PATA Support eege 3 2 4 UJ5B 2 0 SUPPO EE 3 3 VACO SUDDO GE 3 4 Network Interface Controller NIC 3 4 1 Intel UO Acceleration Technology 3 4 2 MAG Address Definitio EE 3 5 Super VO WEE 4 Connector Header Locations and PIN OUTS ccccceeeeseseceeeeeeeeeeeeeeseneeeeeeeeeeeeesnseneeeessenooeenseees 4 1 Board Connector Intformmaton 4 2 Bee CONNGCIOTS EE 4 3 UO Connector Pin out Definition 1sseessessessseeeeneennnnnnnne nnn 4 3 1 VCOA eos dH EM 4 3 2 UO Mezzanine Card CGonnechor nennen nennen nnne nnn nnns 4 3 3 MIablane signal Connector EE Revision 1 4 Intel order number 15154 007 Table of Contents Table of Contents Intel Compute Module MFSSOOOSI TPS 4 3 4 Seral Port C ONMCCIOM sich EU UU ILLI 24 4 3 5
34. er Hub has an integrated Serial ATA SATA controller that supports independent DMA operation on six ports and supports data transfer rates of up to 3 0 Gb s These ports are not used in the Intel Compute Module MFS5000SI design 3 0 3 Parallel ATA PATA Support The integrated IDE controller of the Intel 6321ESB UO Controller Hub provides one IDE channel The PATA interface is not used in the Intel Compute Module MFS5000SI design Revision 1 4 17 Intel order number 15154 007 2BFunctional Architecture Intel Compute Module MFSSOOOSI TPS 3 2 4 USB 2 0 Support The USB controller functionality integrated into the Intel 6321ESB UO Controller Hub provides the server board with the interface for up to eight USB 2 0 ports Two external connectors are located on the front edge of the server board These two ports are the only ports of the Intel 6321ESB I O Controller Hub that are used in the compute module design 3 3 Video Support The server board provides an ATI ES1000 PCI graphics accelerator along with 16 MB of video DDR SDRAM and supports circuitry for an embedded SVGA video subsystem The ATI ES1000 chip contains an SVGA video controller clock generator 2D engine and RAMDAC in a 359 pin BGA One 4Mx16x4 bank DDR SDRAM chip provides 16 MB of video memory The SVGA subsystem supports a variety of modes up to 1024 x 768 resolution in 8 16 32 bpp modes under 2D It also supports both CRT and LCD monitors up to a 100 Hz ve
35. ibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Compute Module MFS5000SI may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Intel Corporation server baseboards support peripheral components and contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions Intel Corporation can not be held responsible if components fail or the compute module does not operate correctly when used outside any of their published operating or non operating limits Intel Pentium Itanium and Xeon are trademarks or registered trademarks of Intel Corporation Other brands and names may be claimed as the property of others Copyright O Intel Corporation 2007 2009 li Revision 1 4 Intel order number 15154 007 Intel Compute Module MFSSOOOSI TPS Table of Contents EE nh de ul e de mec 1 1 chap er IURE ET LUE 1 2 Int
36. le MFSSOOOSI TPS Appendix C POST Error Messages and Handling Appendix C POST Error Messages and Handling Whenever possible the BIOS will output the current boot progress codes on the video screen Progress codes are 32 bit quantities plus optional data The 32 bit numbers include class subclass and operation information The class and subclass fields point to the type of hardware that is being initialized The operation field represents the specific initialization activity Based on the data bit availability to display progress codes a progress code can be customized to fit the data width The higher the data bit the higher the granularity of information that can be sent on the progress port The progress codes may be reported by the system BIOS or option ROMs The Response section in the following table is divided into two types Minor The message is displayed on the screen or in the Error Manager screen The system will continue booting with a degraded state The user may want to replace the erroneous unit The setup POST error Pause setting does not have any effect with this error Major The message is displayed in the Error Manager screen and an error is logged to the SEL The setup POST error Pause setting determines whether the system pauses to the Error Manager for this type of error where the user can take immediate corrective action or choose to continue booting Fatal The message is displayed in the Error Manager screen
37. mable Interrupt Control Application Specific Integrated Circuit Advanced Server Management Interface Basic Input Output System Built In Self Test Baseboard Management Controller Circuitry connecting one computer bus to another allowing an agent on one to access the other Bootstrap Processor 8 bit quantity Chassis Bridge Controller A microcontroller connected to one or more other CBCs together they bridge the IPMB buses of multiple chassis Common Enabling Kit Challenge Handshake Authentication Protocol In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board Direct Platform Control Electrically Erasable Programmable Read Only Memory Enhanced Host Controller Interface Emergency Management Port External Product Specification Enterprise South Bridge 2 Fully Buffered DIMM Flexible Mother Board Fault Resilient Booting Field Replaceable Unit Front Side Bus 1024MB General Purpose I O Gunning Transceiver Logic Hot Swap Controller Hertz 1 cycle second Inter Integrated Circuit Bus Intel Architecture Input Buffer UO Controller Hub Intelligent Chassis Management Bus Internal Error JI Intel order number 15154 007 Glossary Intel Compute Module MFS50008SI TPS Term Definition IFB UO and Firmware Bridge INTR Interrupt Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intellige
38. ment System RTC General purpose I O This section describes the function of most of the listed features as they pertain to this server board For more detailed information see the Inte 5000 Series Chipsets Server Board Family Datasheet or the Inte Enterprise South Bridge 2 External Design Specification 3 2 1 PCI Subsystem The primary I O buses for the server board are PCI and PCI Express The PCI buses comply with the PCI Local Bus Specification Revision 2 3 The following table lists the characteristics of the PCI bus segments Details about each bus segment follow the table Table 4 PCI Bus Segment Characteristics PCI Bus Segment Width Speed On board Device Support PCI32 32 bit 33 MHz PCI Used internally for video controller Intel 6321ESB UO 10 Gb S PCI This interface is not used in the Intel Express Compute Module MFS5000SI design Controller Hub PE1 Intel 6321ESB I O Controller Hub PCI Express Port2 PE4 PES BNB PCI Express Ports 4 5 PE2 Intel 6321ESB I O PCI Controller Hub 3 3V 10 Gb S Express Used internally for LSI 1064e SAS controller PCI Express Port3 20 Gb S I O Mezzanine slot Express 16 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS 2BFunctional Architecture PCI Bus Segment On board Device Support PE6 PE7 33V x8 soaps PC This interface is not used in the Intel seat ele Express Compute Module MFS5000S
39. mn indicates whether an assertion of an event lights the front panel fault LED The Integrated BMC aggregates all fault sources including outside sources such as the BIOS such that the LED will be lit as long as any source indicates that a fault state exists The Integrated BMC extinguishes the fault LED when all sources indicate no faults are present Revision 1 4 31 Intel order number 15154 007 Appendix B Sensor Tables Intel Compute Module MFS5000SI TPS Sensor Rearm The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states Rearming the sensors can be done manually or automatically The following abbreviations are used in the column A Auto rearm M Manual rearm Readable Some sensors are used simply to generate events into the System Event Log The Watchdog timer sensor is one example These sensors operate by asserting and then immediately de asserting an event Typically the SDRs for such sensors are defined such that only the assertion causes an event message to be deposited in the SEL Reading such a sensor produces no useful information and is marked as No in this column Note that some sensors may actually be unreadable in that they return an error code in response to the IPMI Get Sensor Heading command These sensors are represented by type 3 SDR records Standby Some sensors operate on standby power These sensors may be acces
40. n out Pin Signal Name Serial Port Header Pin out 3 5 1 2 Floppy Disk Controller The server board does not support a floppy disk controller FDC interface However the system BIOS does recognize USB floppy devices 3 5 1 3 Keyboard and Mouse Support Keyboard and mouse support is provided locally by the two USB ports located on the front panel of the board The compute module also provides remote keyboard and mouse support 3 5 1 4 Wake up Control The super I O contains functionality that allows various events to power on and power off the system 20 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS 3BConnector Header Locations and Pin outs 4 Connector Header Locations and Pin outs 4 1 Board Connector Information The following section provides detailed information regarding all connectors headers and jumpers on the server board Table 7 lists all connector types available on the board and the corresponding reference designators printed on the silkscreen Table 7 Board Connector Matrix Quantity Reference Designators Midplane Signal Connector J3A1 CPU J7G1 J5G1 we SLE J7B1 J7B2 J7B3 J8B2 J8B3 J8B4 J9B2 J9B3 Video connector connector 1 IJ kKi EI o an Recovery Setting NM geg J7A1 J1F2 Jumpers 4 2 Power Connectors The power connection is obtained using a 2x2 FCI Airmax power connector The following table defines the power connector pin out
41. nt Plattorm Management Interface Infrared In Target Probe 1024 bytes KC Keyboard Controller Style LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode el 3 UJ PEF Platform Event Filtering PEP PIA Platform Information Area This feature configures the firmware for the platform hardware Low Pin Count en uc Om Platform Event Filtering Platform Event Paging S Platform Event Paging PLD Programmable Logic Device PMI Platform Management Interrupt POST Power On Self Test PSMI Power Supply Management Interface PWM Pulse Width Modulation RAM RASUM RISC Reduced Instruction Set Computing ROM Read Only Memory C R SECC SEEPROM Serial Electrically Erasable Programmable Read Only Memory SEL System Event Log Reliability Availability Serviceability Usability and Manageability Random Access Memory AJ CD Real Time Clock Component of ICH peripheral chip on the server board Sensor Data Record Single Edge Connector Cartridge 42 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS Glossary SM SenerManagementierupr SMI the highest prioriy nonmaskable item mm SeweMamgemexMode OOOO ms SewerManxgemenSoRa OOO LIII H H To Be Determined Thermal Interface Material UART Universal Asynchronous Receiver Transmitter User Datagram Protocol Revision 1 4 43 Intel order number 15154 007 Refe
42. overy No PPC The system has detected a corrupted BIOS in the flash part and is recovering the last good BIOS Revision 1 4 39 Intel order number 15154 007 Appendix D Supported Intel Server Chassis Intel amp Compute Module MFS5000SI TPS Appendix D Supported Intel Modular Server System The Intel Compute Module MFS5000SI is supported in the following chassis Intel Modular Server System MFSYS25 Intel Modular Server System MFSYS35 This section provides a high level descriptive overview of each chassis For more details refer to the Inte Modular Server System MFSYS25 MFSYS35 Technical Product Specification TPS 8 emnes D Compute module cooing fans Figure 11 Intel Modular Server System MFSYS25 40 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS Glossary Glossary This appendix contains important terms used in the preceding chapters For ease of use numeric entries are listed first for example 82460GX followed by alpha entries for example AGP 4x Acronyms are followed by non acronyms Term ACPI AP APIC ASIC ASMI BIOS BIST BMC Bridge BSP byte CBC CEK CHAP CMOS EEPROM EHCI M ESB2 MB G UJ TT Tl Tl Tij T mi m U OI D I UJ U U wi ciu J N 7g O GPIO GTL HSC gt N O I slol spela ICMB IERR Revision 1 4 Definition Advanced Configuration and Power Interface Application Processor Advanced Program
43. rence Documents Intel Compute Module MFS5000SI TPS Reference Documents See the following documents for additional information Intel 5000 Series Chipsets Server Board Family Datasheet Intel 5000P Memory Controller Hub External Design Specification Inte Enterprise South Bridge 2 ESB2 External Design Specification Inte Modular Server System MFSYS25 MFSYS35 Technical Product Specification 44 Intel order number 15154 007 Revision 1 4
44. rtical refresh rate Video is accessed using a standard 15 pin VGA connector found on the front edge of the server board Hot plugging the video while the system is still running is supported On board video can be disabled using the BIOS Setup utility 3 3 1 1 Video Modes The ATI ES1000 chip supports all standard IBM VGA modes The following table shows the 2D modes supported for both CRT and LCD Table 5 Video Modes 2D Mode Refresh Rate Hz 2D Video Mode Support 8 bpp 16 bpp 32 bpp 640x480 60 72 75 85 90 Supported Supported Supported lia ar not age a Supporied Supported Supported 3 3 1 2 Video Memory Interface The memory controller subsystem of the ATI ES1000 arbitrates requests from the direct memory interface the VGA graphics controller the drawing co processor the display controller the video scalar and the hardware cursor Requests are serviced in a manner that ensures display integrity and maximum CPU co processor drawing performance The server board supports a 16 MB 4Meg x 16 bit x 4 banks DDR SDRAM device for video memory 18 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS 2BFunctional Architecture 3 4 Network Interface Controller NIC Network interface support is provided from the built in Dual GbE MAC features of the Intel 6321ESB I O Controller Hub These interfaces are routed over the midplane board to the Ethernet switch module in the rear
45. s should have a jumper in place for normal system operation Default Clear If these pins are jumpered the administrator and user passwords are cleared immediately These pins should not be jumpered for normal operation 2 3 i J1F2 CMOS Clear KE These pins should have a jumper in place for normal system operation Default 2 If these pins are jumpered the CMOS settings are cleared immediately These pins should not be jumpered for normal operation 3 J3A3 BIOS Bank If these pins are jumpered the BIOS is forced to boot from the lower bank These pins should not be jumpered for normal operation 23 These pins should have a jumper in place for normal system operation Default 5 1 1 CMOS Clear and Password Reset Usage Procedure The CMOS Clear J1F2 and Password Reset J4A1 recovery features are designed such that the desired operation can be achieved with minimal system down time The usage procedure for these two features has changed from previous generation Intel server boards The following procedure outlines the new usage model Select Power down compute module do not remove AC power Remove compute module from modular server chassis Open compute module Move jumper from Default operating position pins 1 2 to Reset Clear position pins 2 3 Wait 5 seconds Move jumper back to default position pins 1 2 Close the compute module Reinstall compute module in modular server chassis 9 Power up the compute modul
46. sed and or generate events when the compute module payload power is off but standby power is present Table 15 BMC Sensors Sensor Eventy Status Reading Event Offset Triggers Read Rearm Standby Type Type LED 0 Power down 1 Power cycle Sensor 4 AIC lost DC input lost Specific 6Fh 5 Soft power control failure did not turn on or off Power Unit Power Unit Status 09h 6 Power unit failure power good dropout 0 Timer expired 1 Hard reset Watchdog Sensor Watchdog O3h 2 Specific 2 Power down 23h 6Fh 3 Power cycle 8 Timer interrupt System Sensor ACPI Power Specific State 6Fh 0 S0 GO 1 Gi 32 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS Event Reading Event Offset Triggers Type 3 S3 4 S4 5 S5 G2 7 G3 mechanical off B Legacy ON state C Legacy OFF state U L Non critical Fault BB Vtt 10h Voltage DUERA UL x 01h U L Critical Fault BB 1 5V ee ee Thresh U L Non critical Fault AUX g 01h U L Critical Fault U L Non critical Fault BB 1 5V 12h Voltage E U L Critical Fault Thresh U L Non critical BB 1 8V 13h Voltage 01h l Thresh U L Non critical Fault BB 3 3V 14h Voltage 01h l U L Critical Fault BB 3 3V Thresh U L Non critical Fault STB 15h Voltage 01h U L Critical Fault U L Non critical Fault BB 1 5V 16h Voltage Thresh ESB 01h U L Critical Fault U L Non criti
47. set to force boot from lower alternate BIOS bank Minor 8601 of flash ROM 8602 WatchDog timer expired secondary BIOS may be bad 8603 Secondary BIOS checksum fail 38 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS Appendix C POST Error Messages and Handling 92A3 Serial port component was not detected 92A9 Serial port component encountered a resource conflict error 0xA000 TPM device not detected 0xA001 TPM device missing or not responding 0xA002 TPM device failure 0xA003 TPM device failed self test POST Error Pause Option In case of POST error s that are listed as Major the BIOS enters the Error Manager and waits for the user to press an appropriate key before booting the operating system or entering the BIOS Setup The user can override this option by setting POST Error Pause to disabled in the BIOS Setup Main menu page If the POST Error Pause option is set to disabled the system boots the operating system without user intervention The default value is set to disabled POST Error Beep Codes The following table lists the POST error beep codes Prior to system video initialization the BIOS uses these beep codes to inform users of error conditions The beep code is followed by a user visible code on POST Progress LEDs Table 18 POST Error Beep Codes PPC Memory error No PPC System halted because a fatal error related to the memory was detected BIOS rec
48. to support memory mirroring is four DIMMs populated as shown in Figure 8 All four DIMMs must be identical with respect to size speed and organization To upgrade a four DIMM mirrored memory configuration four additional DIMMs must be added to the system All four DIMMs in the second set must be identical to the first 3 1 3 4 2 DIMM Sparing Mode Memory Configuration The MCH provides DIMM sparing capabilities Sparing is a RAS feature that involves configuring a DIMM to be placed in reserve so it can be used to replace a DIMM that fails DIMM sparing occurs within a given bank of memory and is not supported across branches Two Memory Sparing configurations are supported Single Branch Mode Sparing Dual Branch Mode Sparing Revision 1 4 13 Intel order number 15154 007 2BFunctional Architecture Intel Compute Module MFS5000SI TPS 3 1 8 4 2 1 Single Branch Mode Sparing Slot 2 DIMM A2 DIMM B2 L DIMM CO L DIMM D2 Slot 1 DIMM AI DIMM Bl DIMM CL 4 DIMM DI Channel A Channel B Channel C Channel D Branch 0 Branch 1 Figure 9 Single Branch Mode Sparing DIMM Configuration DIMM A1 and DIMM B1 must be identical in organization size and speed DIMM A2 and DIMM B2 must be identical in organization size and speed DIMM A1 and DIMM A2 should be identical in organization size and speed See note below DIMM B1 and DIMM B2 should be identical in organization size and speed See note below Sparing should be enabled
49. ts single DIMM mode operation Intel only validates and supports this configuration with a single 512MB x8 FBDIMM installed in DIMM slot A1 3 1 3 4 Non mirrored Mode Memory Upgrades The minimum memory upgrade increment is two DIMMs per branch The DIMMs must cover the same slot position on both channels DIMM pairs must be identical with respect to size speed and organization When adding two DIMMs to the configuration shown in Figure 7 the DIMMs should be populated in DIMM slots C1 and D1 as shown in the following diagram Populated DIMM slots are shown in Grey Revision 1 4 Intel order number 15154 007 Intel Compute Module MFS5000SI TPS 2BFunctional Architecture Channel C Channel D Channel B Channel A A WAA SS QE a 1 Wi TP02301 Figure 8 Recommended Four DIMM Configuration Functionally DIMM slots A2 and B2 could also have been populated instead of DIMM slots C1 and D1 However your system will not achieve equivalent performance Figure 8 shows the supported DIMM configuration that is recommended because it allows both memory branches from the MCH to operate independently and simultaneously FBD bandwidth is doubled when both branches operate in parallel 3 1 3 4 1 Mirrored Mode Memory Configuration When operating in the mirrored mode both branches operate in lock step In mirrored mode branch 1 contains a replicate copy of the data in branch 0 The minimum DIMM configuration
50. ute Module MFSSOOOSI TPS 5BProduct Regulatory Requirements 6 Product Regulatory Requirements 6 1 Product Regulatory Requirements The Intel Compute Module MFS5000SI is evaluated as part of the Intel Modular Server System MFSYS25 MFSYS35 which requires meeting all applicable system component regulatory requirements Refer to the InteP Modular Server System MFSYS25 MFSYS35 Technical Product Specification for a complete listing of all system and component regulatory requirements 6 2 Product Regulatory Compliance and Safety Markings No markings are required on the Intel Compute Module MFS5000SI server board itself as it is evaluated as part of the Intel Modular Server System MFSYS25 MFSYS35 6 3 Product Environmental Ecology Requirements The Intel Compute Module MFS5000SI is evaluated as part of the Intel Modular Server System MFSYS25 MFSYS35 which requires meeting all applicable system component environmental and ecology requirements For a complete listing of all system and component environment and ecology requirements and markings refer to the Inte Modular Server System MFSYS25 MFSYS35 Technical Product Specification 6 4 Product Environmental Ecology Markings The following Product Ecology markings are required on the Intel Compute Module MFS5000SI server board en O O ms China Restriction of Hazardous Substance China Environmental Friendly Use Period Mark Lay Revision 1 4 29 Intel order number 15154 007
51. z or 1333 MHz Memory 8 keyed DIMM slots supporting fully buffered DIMM technology FBDIMM memory 240 pin DDR2 677 FBDIMMs must be used R Chipset Intel 5000 Chipset family which includes the following components Intel 5000P Memory Controller Hub Intel 6321ESB UO Controller Hub On board External connections Connectors Headers Two USB 2 0 ports Video connector Internal connectors headers One DH 10 Serial A debug header One Intel UO Mezzanine Connector supporting Dual Gigabit NIC Intel UO Expansion Module Optional On board Video ATI ES1000 video controller with 16MB DDR SDRAM On board Hard Drive LSI 1064e SAS controller Controller LAN Two integrated 10 100 1000 Ethernet ports and two optional 10 100 1000 Ethernet ports provided by the Dual Gigabit NIC mezzanine module 2 Revision 1 4 Intel order number 15154 007 Intel Compute Module MFSSOOOSI TPS 1BProduct Overview 2 2 Compute Module Layout 2 2 1 Connector and Component Locations The following figure shows the board layout of the Intel Compute Module MFS5000SI Each connector and major component is identified by a number or letter A description of each identified item is provided below the figure a AF002460 Description o LL Description O P Wiblane Power Connector B Mapane Signal Gamnector C POST Code Diagnose tens D fers core ooo S CPU A Sod Activity and ID LEDs L Video Connector N USB1 and USB
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