Home

Intel Core Core™ i5-750 Processor (8M Cache, 2.66 GHz)

1. eese 229 4 19 5 eif uet hd iil pei 229 4 20 Halt and Mask Bit 2 7 5 230 4 21 Registers ERE 230 5 1 Transaction Address Ranges Compatible High and 5 287 5 2 SMM iSpace Table Ro che RR Ra FORM i ERI XR RARE LI E RES 288 5 3 SMM Control Table 289 5 4 Outbound Target Decoder Entries 293 5 5 Decoding of Outbound Memory Requests from Intel QuickPath Interconnect from processor or remote Peer to Peer 2 4 4 44 41 4 0 293 5 6 Decoding of Outbound Configuration Requests from Processor or Peer to Peer from Intel QuickPath Interconnect and Decoding of Outbound Peer to Peer Completions from Intel QuickPath Interconnect 294 5 7 Subtractive Decoding of Outbound 1 0 Requests from Intel QuickPath Interconnect 294 5 8 Inbound Memory Address Decoding sssssssssss eee ee emm 296 5 9 Inbound I O Address nee e enin 298 5 10 Inbound Configuration Request Decoding sssssssssee mme 299 Datasheet Volume 2 Revision History ntel
2. Device 3 Function 1 Offset COh C4h C8h CCh DOh D4h D8h DCh Access as a DWord Bit Attr Default Description 31 30 RO 0 Reserved 29 28 RW Branch7 Branch or index 111 of the Interleave List Bits determined from the matching TAD DRAM RULE mode 27 26 RO Reserved 25 24 RW Branch6 Branch or index 110 of the Interleave List Bits determined from the matching TAD_DRAM_RULE mode 23 22 RO Reserved 21 20 RW Branch5 Branch or index 101 of the Interleave List Bits determined from the matching TAD DRAM RULE mode 19 18 RO Reserved 17 16 RW Branch4 Branch or index 100 of the Interleave List Bits determined from the matching TAD_DRAM_RULE mode 15 14 RO Reserved 13 12 RW Branch3 Branch or index 011 of the Interleave List Bits determined from the matching TAD DRAM RULE mode 11 10 RO Reserved 9 8 RW Branch2 Branch or index 010 of the Interleave List Bits determined from the matching TAD DRAM RULE mode 7 6 RO Reserved 5 4 RW Branch1 Branch or index 001 of the Interleave List Bits determined from the matching TAD_DRAM_RULE mode 3 2 RO Reserved 1 0 RW 0 Branch or index 000 of the Interleave List Bits determined from the matching TAD DRAM RULE mode Datasheet Volume 2 Processor Uncore Configuration Registers intel 4 9 I ntegrated Memory Controller Test Registers 4 9 1 I ntegrated Memory Controller Padscan
3. INTPIN INTLIN 3Ch DMIRCBAR 50h MSI CAPI D MSICTL MSINXTPTR 2Ch ROOTCAP ROOTCON ROOTSTS 34h DEVCAP2 DEVCTRL2 LNKCON2 MSIAR MSIMSK MSI PENDING Datasheet Volume 2 94h 98h 9Ch AOh ACh BOh B4h B8h COh 21 Processor Integrated 1 Configuration Registers intel Table 3 3 Device 0 DMI Extended Configuration Map 180h PERFCTRLSTS 184h 188h MISCCTRLSTS 32 Datasheet Volume 2 Processor Integrated 1 Configuration Registers Table 3 4 DID VID 00h PCISTS PCI CMD 04h CCR RID CLSR PEGCAP PEGNXTPTR Device 3 5 PCI Express Registers Legacy Configuration Map PEGCAPID DEVCAP INTPIN INTLIN SNXTPTR SCAPID MSICTRL SVID MSINXTPTR MSICAPID SUBBUS SECBUS PBUS DEVSTS DEVCTRL SECSTS IOLI M 5 1Ch LNKCAP MLIM MBAS 20h LNKSTS LNKCON PMLIMIT PMBASE 24h SLTCAP PMBASEU 28h SLTSTS SLTCON PMLIMITU 2Ch ROOTCAP ROOTCON ROOTSTS DEVCAP2 DEVCTRL2 LNKCON2 MSIMSK MSIPENDING Datasheet Volume 2 94h 98h 9Ch AOh A4h A8h ACh 33 Processor Integrated 1 Configuration Registers intel Table 3 5 Device 3 5 PCI Express Registers Extend
4. 44 3 3 3 19 IOLIM I O Limit Register 2 0 2 0 cece tee eee teeta ns 45 3 3 3 20 SECSTS Secondary Status Register 46 3 3 3 21 MBAS Memory Base 1 111 47 3 3 3 22 MLIM Memory 0 47 3 3 3 23 PMBASE Prefetchable Memory Base 48 3 3 3 24 PMLIMIT Prefetchable Memory 4 48 3 3 3 25 PMBASEU Prefetchable Memory Base Upper 32 bits 49 3 3 3 26 PMLIMITU Prefetchable Memory Limit Upper 32 bits 49 3 3 3 27 BCTRL Bridge Control Register sss 50 3 3 4 Device Specific PCI Configuration Space 40h to 51 3 3 4 1 SCAPID Subsystem Capability Identity 51 Datasheet Volume 2 3 3 3 4 2 SNXTPTR Subsystem ID Next Pointer 51 3 3 4 3 SVID Subsystem Vendor 52 3 3 4 4 SID Subsystem 00 52 3 3 4 5 DMIRCBAR DMI Root Complex Register Block Base Address Register 52 3 3 4 6 MSICAPID MSI Capability ID 53 3 3 4 7 MSINXTPTR MSI Next 53 3 3 4 8 MSICTRL
5. ERRAT EU RATE SE 271 4 13 8 MC THROTTLE OFFSETO THROTTLE OFESETL eet ie aU Rena e Eee ERE 271 4 13 9 MC RANK VIRTUAL TEMPO MC RANK VIRTUAL e enne 272 4 13 10MC DDR THERM COMMANDO MC DDR THERM 1 ssssse IH eere 272 4 13 11MC DDR THERM STATUSO DDR THERM STATUS iieri eee eb peragere P ns 273 5 System Address Map oom LER ERR DR AG hia ds ada Gudang bis Petey SG REPE Ka dads 275 SE s oie etd 275 5 2 Memory Address Space nigieas 276 5 2 1 System Address Map eren E RR ERE edie sited 277 5 2 2 System DRAM Memory 2 2 1 222 278 5 2 3 VGA SMM and Legacy C D E F Regions 279 5 2 3 1 VGA SMM Memory 5 0 279 5 2 3 2 C D E F Segments iinei yer ka err aer der med 280 5 2 4 Address Region between 1 MB and 0212 280 5 2 4 1 Relocatable TSEG iecit eben eene rk e PR ERE DR erie netted 281 5 2 5 Address Region from TOLM to 4 GB cece cece cece eee een mms 281 5 2 5 1 PCI Express Memory Mapped Configuration 281 5 2 5 2
6. 0 291 5 8 4 1 General OVervIew cssc Ra 291 5 8 1 2 EWH Decoding eee ee erre siete 292 5 8 1 3 Other Outbound Target Decoding 292 5 8 1 4 Summary of Outbound Target Decoder 293 5 8 1 5 Summary of Outbound Memory lO Configuration Decoding 293 5 8 2 Inbound Address Decoding rrr nein ntes Re er RE PRX RR 295 5 8 2 1 OVerVIGW per ou sede E E HR epi DR as 295 5 8 2 2 Summary of Inbound Address Decoding 296 5 8 3 Intel VT d Address Map Implications 300 Datasheet Volume 2 Figures 2 1 Tables 3 1 3 2 UJ QJ QJ QJ UJ QJ GJ QJ Ww HA HH H H H H Memory Map to PCI Express Device Configuration 22 Processor Configuration Cycle 1 1 23 DMI Port Device 0 PCI Express Root Ports 1 Configuration Space 29 Base Address of Intel VT d Remap 137 Padscan Accessibility Mechanism 1 230 System address Map seu ADR ERU tn ERE IIT 277 VGA S
7. 0100 286 5 4 Config ration CSR Space dienes peek rine re XL ad ga si dae tiie E P 286 5 4 1 PCle Configuration 5 000 286 Datasheet Volume 2 11 12 ntel System Management Mode SMM 1 7 4 44 4 44 4 4 44 287 5 5 1 SMM Space Definitio G Ki ads Sania ge bin E duri iiic da 287 5 52 SMM Space Restrictions eui RERUM AE V EERE T 288 5 5 3 SMM Space Combinations 4 2 2 22 0 288 5 5 4 SMM Control aka ese ea are v Ra P 289 5 5 5 SMM Space Decode and Transaction 289 5 5 6 Processor WB Transaction to an Enabled SMM Address Space 289 5 5 7 SMM Access Through GTT TLB cece eect eee ee teen 289 Memory Shadowlng davis Pere tte erecta x ber NR ned dean Eae Le DR EI RD P P E RR DRE eee 290 IIO Address Map NOtes trc Eee uH ERR RR DERE ERU EQUI Y KERN M id 290 5 7 1 Memory sse mei ee EX RAG nA DER PAR RR ERR Paw OK 290 5 7 2 Non Coherent Address 5 290 llO Address Decoding oir eitis Gc itas Ke kk rie 291 5 8 1 Outbound Address
8. Datasheet Volume 2 Processor Uncore Configuration Registers 4 10 31 4 10 32 intel MC CHANNEL 0 PAGETABLE 51 MC CHANNEL 1 PAGETABLE PARAMSI These are the parameters used to control parameters for page closing policies Device 4 5 Function O Offset D8h Access as a DWord Bit Attr Default Description 31 16 RO 0 Reserved REQUESTCOUNTER 15 8 RW 0 Upper 8 MSBs of a 12 bit counter This counter determines the window over which the page close policy is evaluated ADAPTI VETI MEOUTCOUNTER Upper 8 MSBs of a 12 bit counter This counter adapts the interval between 7 0 RW 0 assertions of the page close flag For a less aggressive page close the length of the count interval is increased and vice versa for a more aggressive page close policy MC CHANNEL 0 PAGETABLE PARAMS2 MC CHANNEL 1 PAGETABLE PARAMS2 These are the parameters used to control parameters for page closing policies Device 4 5 Function O Offset DCh Access as a DWord Bit Attr Default Description 31 28 RO 0 Reserved 27 RW 0 ENABLEADAPTI VEPAGECLOSE When set enables Adaptive Page Closing MI NPAGECLOSELI MI T 26 18 RW 0 Upper 9 MSBs of a 13 bit threshold limit When the mistake counter falls below this threshold a less aggressive page close interval larger is selected MAXPAGECLOSELI MI T 17 9 RW 0 Upper 9 bits of a 13 bit threshold limit When the mistake counter ex
9. 7 0 WO Oh N A TXT CMD OPEN LOCALI TY2 I ntel TXT Open Locality 2 Command Enables Locality 2 decoding in chipset This command will open Locality2 for decode as an Intel TXT space by the chipset This command is either an TXTMW or a private write when private is open OPEN PRIVATE will open Locality 2 and CLOSE PRIVATE will close Locality 2 without requiring an explicit OPEN CLOSE CMD LOCALITY3 cycle The OPEN CLOSE Locality 2 commands are to be used in the window while PRIVATE is open but the VMM wants to close or re open the Locality 2 space while still leaving PRIVATE open If the locality is closed then cycles to the Locality 2 address range are not decoded as Intel TXT cycles Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers L D Note PRIVATE space must also be Open for Locality 2 to be decoded as Intel TXT space General Behavioral Rules This is a write only register This register is only available in the private Intel TXT configuration space Accesses to this register are done with 1 byte writes The data bits associated with this command are undefined and have no specific meaning Base TXT Offset 0390h Base TXT PR Offset 0390h Bit Attr Default Description 7 0 3 6 1 24 TXT CMD CLOSE LOCALITY2 Intel TXT Close Locality 2 Command Disables Locality 2 decoding in chipset When closed th
10. Processor Claims Processor Claims Yes Processor Claims Processor Claims Datasheet Volume 2 23 m t D Configuration Process and Registers 2 3 2 2 3 2 1 24 I nternal Device Configuration Accesses The processor decodes the Bus Number Bits 23 16 and the Device Number fields of the CONFIG ADDRESS register If the Bus Number field of CONFIG ADDRESS is 0 the configuration cycle is targeting a PCI Bus 0 device If the targeted PCI Bus 0 device exists in the processor and is not disabled the configuration cycle is claimed by the appropriate device Bridge Related Configuration Accesses Configuration accesses on PCI Express or DMI are PCI Express Configuration Transaction Layer Packets TLPs Bus Number 7 0 is Header Byte 8 7 0 Device Number 4 0 is Header Byte 9 7 3 Function Number 2 0 is Header Byte 9 2 0 And special fields for this type of TLP Extended Register Number 3 0 is Header Byte 10 3 0 Register Number 5 0 is Header Byte 11 7 2 See the PCI Express Specification for more information on both the PCI 2 3 compatible and PCI Express Enhanced Configuration Mechanism and transaction rules PCI Express Configuration Accesses When the Bus Number of a Type 1 Standard PCI Configuration cycle or PCI Express Enhanced Configuration access matches the Device 1 Secondary Bus Number a PCI Express Type 0 Configuration
11. 137 d Memory Mapped Registers aicinn ienaa EEEE EE 137 Intel VT d Configuration Register Space 138 Register Description vest vaga 141 3 5 2 1 VTD VERSION O 1 Version Number 141 3 5 2 2 CAP 0 1 Intel VT d Chipset Capabilities Register 142 3 5 2 3 EXT VTD CAP 0 1 Extended Intel VT d Capability Register 143 3 5 2 4 GLBCMD 0 1 Global Command Register 144 3 5 2 5 GLBSTS 0 1 Global Status 145 3 5 2 6 ROOTENTRYADD O0 1 Root Entry Table Address Register 145 3 5 2 7 CTXCMD 0 1 Context Command Register 146 3 5 2 8 FLTSTS 0 1 Fault Status 147 3 5 2 9 FLTEVTCTRL O0 1 Fault Event Control Register 148 3 5 2 10 FLTEVIDATA 0 1 Fault Event Data Register 149 3 5 2 11 FLTEVTADDR O0 1 Fault Event Address Register 149 3 5 2 12 FLTEVTUPRADDR O0 1 Fault Event Upper Address Register 149 3 5 2 13 PMEN 0 1 Protected Memory Enable 149 3 5 2 14 PROT LOW MEM BASE 0 1 Protected Memory Low Base Register
12. 38 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers Sheet 2 of 2 Register Device Function Offset PCISTS 0 DMI 3 5 PCle 0 06h Bit Attr Default Description 13 RW1C Received Master Abort Status This bit is set when a device experiences a master abort condition on a transaction it mastered the primary interface Integrated I O internal bus Note that certain errors might be detected right at the PCI Express interface and those transactions might not propagate to the primary interface before the error is detected for example accesses to memory above TOCM in cases where the PCI Express interface logic itself might have visibility into TOCM Such errors do not cause this bit to be set and are reported using the PCI Express interface error bits secondary status register Conditions that cause Bit 13 to be set include Device receives a completion on the primary interface internal bus of Integrated 1 with Unsupported Request or master abort completion Status This includes UR status received on the primary side of a PCI Express port on peer to peer completions also Device accesses to holes in the main memory address region that are detected by Intel QuickPath Interconnect Source Address Decoder e Other master abort conditions detected on the Integrated 1 0 internal bus 12 RW1C Received Target Abort This bit is set
13. ute MC_SAG_CHO_2 5 CHO 6 SAG CHI 2 5 1 6 5 0 5 CHO 4 SAG 1 0 SAG CHI 4 MC RIR LIMIT CHO 0 MC RIR LIMIT CHO 3 MC RIR LIMIT CHO 6 LIMIT CHI 0 RIR LIMIT CH1 3 MC LIMIT CH1 6 MC SAG CHO 1 MC SAG CHO 5 MC 5 1 1 5 1 5 Integrated Memory Controller Channel Rank Registers MC RIR LIMIT CHO 1 RIRL LIMIT CHO 4 MC RIR LIMIT CHO 7 RIR LIMIT 1 RIR LIMIT CHI 4 MC LIMIT CH1 7 MC SAG CHO 3 SAG CH1 3 MC LIMIT CHO 2 LIMIT CHO 5 MC LIMIT 2 RIR LIMIT CHI 5 SAG CHO 7 SAG CHI 7 4 12 3 WAY CHO 0 MC RIR WAY CHO 3 RIR WAY CHO 6 MC RIR WAY CHO 8 MC RIR WAY CHO 1 MC RIR WAY CHO 2 MC RIR WAY CHO 4 MC RIR WAY CHO 5 MC RIR WAY CHO 7 MC RIR WAY CHO 9 MC RIR WAY CHO 10 MC RIR WAY CHO 12 MC RIR WAY CHO 14 MC RIR WAY CHO 16 MC RIR WAY CHO 18 MC RIR WAY CHO 20 MC RIR WAY CHO 22 MC RIR WAY CHO 24 MC RIR WAY CHO 26 MC RIR WAY CHO 28 MC RIR WAY CHO 11 MC RIR WAY CHO 13 MC RIR WAY CHO 15 MC WAY CHO 17 MC RIR WAY CHO 19 RIR WAY 21 RIR WAY 23 MC RIR WAY CHO 25 MC RIR WAY 27 MC RIR WAY CHO 29 MC RIR WAY CHO 30 MC RIR WAY CHI 0 MC RIR WAY CHI 2 MC RIR WAY CHI 4 MC RIR WAY CHI 6 RIR WAY
14. DID VID 00h PCISTS PCICMD 04h CCR RID 08h HDR CLS OCh SID SVID 2Ch CAPPTR 34h QPIPRDLTO 38h QPI PISOCRES B8h INTP INTL 3Ch QPIPCTRLO 4Ch Notes 1 CAPPTR points to the first capability block 180 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 7 2 1 QPI PCTRLO I ntel QuickPath Interconnect Protocol Control Register can only be modified under system quiescence All RWL bits are locked with the lock1 bit Register QPIPCTRLO Device 16 Function 1 Offset 4Ch Bit Attr Default Description VC1 Priority When Isoc is enabled this value should is expected to be set as Critical 00 Standard a139 RWE s 01 Reserved 10 High 11 Critical recommended when isoc enabled VCp Priority When Isoc is enabled this value should is expected to be set as High 10 00 Standard 19 28 RWE 9 01 Reserved 10 High recommended when isoc enabled 11 Critical 27 0 RWL 0 Reserved 3 7 2 2 QPI PI SOCRES I ntel QuickPath I nterconnect Protocol I sochronous Reservation Controls how TID are allocated to for Isochronous requests Values applies across all TID allocation pools for a given Intel QuickPath Interconnect port Register modified only under system quiescence Register QPIPISOCRES Device 16 Function 1 Offset B8h Bit Attr Default Description 31 17 RV 0 Reserved Enabled 16 RW 1 When
15. 106 3 4 3 3 EXPCAP PCI Express Capabilities 106 3 4 3 4 DEVCAP PCI Express Device Capabilities Register 107 3 4 3 5 DEVCTRL PCI Express Device Control Register 108 3 4 3 6 DEVSTS PCI Express Device Status 110 3 4 44 Intel VT d Address Mapping System Management Registers Device 8 ne 111 3 4 4 1 IIOMISCCTRL Integrated 1 Misc Control Register 111 3 4 4 2 11 15 55 1 I O MISC Status 112 3 4 4 3 TSEGCTRL TSEG Control 2 2 2002 2 112 3 4 4 4 TOLM Top of Low Memory 113 3 4 4 5 TOHM Top of High nanan ens 113 3 4 4 6 NCMEM BASE NCMEM Base 2 113 3 4 4 7 NCMEM LIMIT NCMEM 0 2 0 0 00 0 00 4 114 3 4 4 8 DEVHIDE1 Device Hide 1 Register 114 3 4 4 9 DEVHIDE2 Device Hide 2 Register 117 3 4 4 10 ILOBUSNO IIO Internal Bus Number 118 3 4 4 11 LMMIOL BASE Local MMIOL 118 3 4 4 12 LMMIOL LIMIT Local MMIOL 7 20 0 00002 2 2 2
16. 21 2 3 Routing Configuration emnes 23 2 3 1 Internal Device Configuration ACCESSES mne 24 2 3 2 Bridge Related Configuration 24 2 3 2 1 PCI Express Configuration 24 2 3 2 2 DMI Configuration ACCESSES 25 2 4 Processor Register 1111 25 2 5 O Mapped ena dex Pe e a P PE e PEE REPERTA 26 3 Processor Integrated 1 Configuration Registers 27 3 1 Processor Devices PCI Bus O0 0 0 eect mH 27 3 2 Device MAPPING bia UO RR De RO RM E Bae E RR cae 28 3 2 1 Unimplemented Devices Functions and Registers sss 28 3 3 PCI Express DMI Configuration Registers sesessssssssneemmms 28 3 3 1 Other Register 0001 eme nene nns 28 3 3 2 Configuration Register 29 3 3 3 Standard PCI Configuration Space to 3Fh Type 0 1 Common Configuration 35
17. Datasheet Volume 2 209 Processor Uncore Configuration Registers Device 0 Function 1 Offset 40h Access as a DWord Bit Attr Default Description 27 26 RO 0 Reserved PAM3_LOENABLE 000000 OD3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 000000 to OD3FFFh 25 24 RW 0 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 23 22 RO 0 Reserved PAM2_HI ENABLE OCFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OCCOOOh to OCFFFFh 21 20 RW 0 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 19 18 RO 0 Reserved PAM2 LOENABLE 0 8000 OCBFFFhAttribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0C8000h to OCBFFFh 17 16 RW 0 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads
18. Hide Dev8 Fun2 When set hide Device 8 Function 2 5 RWLB Ob 1 This bit has no effect on J TAG initiated accesses to corresponding device s configuration space 2 This bit has no impact on memory transactions targeting the device Hide Dev8 1 When set hide Device 8 Function 1 4 RWLB Ob 1 This bit has no effect on J TAG initiated accesses to corresponding device s configuration space 2 This bit has no impact on memory transactions targeting the device Hide Dev8 FunO When set hide Device 8 Function 0 1 This bit has no effect on JTAG initiated accesses to corresponding 3 RWLB Ob device s configuration space 2 This bit has no impact on memory transactions targeting the device Note Dev8_Fun0 is hidden then other functions within this device should also be hidden to comply with PCI rules 2 0 RV Oh Reserved Datasheet Volume 2 117 intel 3 4 4 10 Processor Integrated 1 Configuration Registers II OBUSNO IIO Internal Bus Number Register II OBUSNO Device 8 Function O Offset 10Ah Bit Attr Default Description 15 9 RV 00h Reserved Valid 0 The IIO claims PCI configuration access to its internal devices device function defined in Table 3 1 Functions Handled by the Processor Integrated I O II O with ANY Bus number regardless of bits 7 0 of this register 8 RW Ob 1 The Integrated I O claims PCI configuration access to
19. 28 RO 0 Reserved N A to IIO 27 RO 0 Reserved N A to 110 Queued Invalidation Enable Software writes to this field to enable queued invalidations 0 Disable queued invalidations In this case invalidations must be performed through the Context Command and Invalidation registers 1 Enable use of queued invalidations Once enabled all invalidations must be 26 RW 0 submitted through the invalidation queue and the invalidation registers cannot be used without going through an IIO Reset The invalidation queue address register must be initialized before enabling queued invalidations Also software must make sure that all invalidations submitted prior using the register interface are all completed before enabling the queued invalidation interface Interrupt Remapping Enable 0 Disable Interrupt Remapping Hardware 1 Enable Interrupt Remapping Hardware Hardware reports the status of the interrupt remap enable operation through the IRES field in the Global Status register 25 RW 0 Before enabling or re enabling Interrupt remapping hardware through this field software must Setup the interrupt remapping structures in memory Set the Interrupt Remap table pointer in hardware through SIRTP field e Perform global invalidation of OTLB 24 RV 0 Reserved 23 RV 0 Reserved 22 0 RV 0 Reserved Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 5 2 5 GLBSTS 0 1 Global Sta
20. Slot Implemented 0 indicates no slot is connected to this port 1 indicates that the PCI Express link associated with the port is connected to a slot This register bit is of type write once and is controlled by BIOS special initialization firmware Device Port 7 4 RO 1001b This field identifies the type of device It is set to 0100 for all the Express ports and 1001 for the DMA Perfmon and PCI Express DF register devices Capability Version 3 0 RO 2h This field identifies the version of the PCI Express capability structure Set to 2h for Express and DMA devices for compliance with the extended base registers Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 4 3 4 DEVCAP PCI Express Device Capabilities Register The PCI Express Device Capabilities register identifies device specific information for the device Device 8 Function 0 1 2 Offset 44h Bit Attr Default Description 31 28 RO Oh Reserved Captured Slot Power Limit Scale 218 RO an Does not apply to root ports or integrated devices 25 18 RO 00h Captured Slot Power Limit Value Does not apply to root ports or integrated devices 17 16 RO Oh Reserved 15 RO 1 Role Based Error Reporting Integrated 1 0 is 1 1 compliant and so supports this feature 14 RO 0 Power Indicator Present on Device Does not apply to root
21. ian UE Cr 213 4 5 7 SAD MCSEG Ele Ra 214 4 5 8 SAD MCSEG MASK iiie eie ERE e Erbe RARE 214 4 5 9 SAD MESEG BASE 55 0 UU MA Ker E E DRE 215 4 5 10 SAD MESEG MASK recen ER EH ERE EIC E ES Rr a 215 4 5 11 SAD DRAM RULE 0 SAD DRAM RULE 1 SAD DRAM RULE 2 SAD DRAM RULE 3 SAD DRAM RULE 4 SAD DRAM RULE 5 SAD DRAM 6 SAD DRAM RULE 7 216 4 5 12 SAD INTERLEAVE LIST 0 SAD INTERLEAVE LIST 1 SAD INTERLEAVE LIST 2 SAD INTERLEAVE LIST 3 SAD INTERLEAVE LIST 4 SAD INTERLEAVE LIST 5 SAD INTERLEAVE LIST 6 SAD INTERLEAVE LIST 7 217 Intel QuickPath Interconnect Link Reglsters i iius orba ad tas Peiper Brea ro d aie 218 46 1 OPIEGE LO ED 218 Integrated Memory Controller Control 3 2 2 220 4 71 MG CONTROL end ure A 220 4 7 2 5 DIMM ERROR 5 5 00 221 45723 MG SMI CNTRIL eie Ma UR cie 221 ATA ME 5 222 4 7 5 RESET CONTROL eter per auke e Ek a Per RR Rak DER dae
22. 92 3 4 2 Standard PCI Configuration Registers 98 3 4 2 1 VID Vendor Identification 98 3 4 2 2 DID Device Identification 98 3 4 2 3 PCICMD PCI Command Register sss 98 Datasheet Volume 2 3 4 2 4 PCISTS PCI Status 101 3 4 2 5 RID Revision Identification 103 3 4 2 6 CCR Class Code 103 3 4 2 7 CLSR Cacheline Size Register sss 103 3 4 2 8 HDR Header Type Register 2522 104 3 4 2 9 SVID Subsystem Vendor 104 3 4 2 10 SID Subsystem Device ID ees 104 3 4 2 11 CAPPTR Capability Pointer 0 0 104 3 4 2 12 INTLIN Interrupt Line Register 0 0222 105 3 4 2 13 INTPIN Interrupt Pin Register 105 3 4 3 Common Extended Configuration Space 21 105 3 4 3 1 CAPID PCI Express Capability List 105 3 4 3 2 NXTPTR PCI Express Next Capability List Register
23. Bit Attr Default Description 31 4 RO 0 Reserved INC ENTERPWRDWN RATE Powerdown rate will be increased during thermal throttling based on the following configurations 3 2 RW 0 00 tRANKIDLE Default 01 16 10 24 11 32 DIS OP REFRESH When set the refresh engine will not issue opportunistic refresh Setting this 1 RW 0 bit when either the MC DIMM INIT PARAMS QUAD RANK PRESENT bit or the MC DIMM INIT PARAMS THREE DIMMS PRESENT bit is set will prevent entry into self refresh ASR PRESENT When set this bit indicates DRAMs on this channel can support Automatic 0 RW 0 Self Refresh If the DRAM is not supporting ASR Auto Self Refresh then Self Refresh entry will be delayed until the temperature is below the 2x refresh temperature MC CHANNEL 0 MRS VALUE 0 1 MC CHANNEL 1 MRS VALUE O 1 The initial MRS register values for MRO and MR1 can be specified in this register These values are used for the automated MRS writes used as a part of the training FSM The remaining values of the MRS register must be specified here Device 4 5 Function O Offset 70h Access as a DWord Bit Attr Default Description MR1 31 16 RW 9 The values to write to MR1 for A15 A0 MRO 13 0 R 0 The values to write to MRO for 15 0 Datasheet Volume 2 Processor Uncore Configuration Registers intel 4 10 8 MC_CHANNEL_0_MRS_VALUE_2 MC CHANNEL 1 MRS VALUE 2 The in
24. Datasheet Volume 2 Revision m Revision Number Description Date September 001 Initial release 2009 15 16 Datasheet Volume 2 Introduction 1 Note Note Note 1 1 Introduction This is Volume 2 of the Datasheet for the Intel Core i7 800 and i5 700 desktop processor series The processor contains one or more PCI devices within a single physical component The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket This document describes these configuration space registers or device specific control and status registers CSRs only This document does NOT include Model Specific Registers MSRs Throughout this document the Intel Core i7 800 and i5 700 desktop processor series may be referred to as processor Througout this document the Intel 5 series Chipset Platform Controller Hub Platform Controller Hub is also referred to as PCH The term DT refers to desktop platforms Register Terminology Registers and register bits are assigned one or more of the following attributes These attributes define the behavior of register and the bit s that are contained with in All bits are set to default values by hard reset Sticky bits retain their states between hard resets Term Description RO Read Only If a register bit is read only the hardware sets its state The bit may be read by softw
25. Datasheet Volume 2 29 m t D Processor Integrated 1 Configuration Registers 30 Figure 3 1 illustrates how each PCI Express port s configuration space appears to software Each PCI Express configuration space has three regions Standard PCI Header This region is the standard PCI to PCI bridge header providing legacy OS compatibility and resource management PCI Device Dependent Region This region is also part of standard PCI configuration space and contains the PCI capability structures and other port specific registers For the IIO the supported capabilities are SVID SDID Capability Message Signalled Interrupts Power Management PCI Express Capability PCI Express Extended Configuration Space This space is an enhancement beyond standard PCI and only accessible with PCI Express aware software Note that all the capabilities listed above for a PCI Express port are required for a DMI port Through the rest of the chapter as each register is elaborated it will be noted which registers are applicable to the PCI Express port and which are applicable to the DMI port Datasheet Volume 2 Processor Integrated 1 Configuration Registers Table 3 2 Device 0 DMI Configuration Map DID VID 00h PCISTS PCICMD 04h CCR RID 08h HDR CLSR OCh PEGCAP PEGNXTPTR PEGCAPID DEVCAP DEVSTS DEVCTRL LNKCAP LNKSTS LNKCON
26. Express DMI side of the virtual PCI to PCI bridge Register SECSTS Device 3 5 PCI e Function 0 Offset 1Eh Bit Attr Default Description Detected Parity Error 15 RW1C 0 This bit is set by the Integrated I O whenever it receives a poisoned in the PCI Express port This bit is set regardless of the state the Parity Error Response Enable bit in the Bridge Control register Received System Error 14 RWI1C 0 This bit is set by the Integrated 1 0 when it receives a ERR FATAL ERR NONFATAL message Received Master Abort Status This bit is set when the PCI Express port receives a Completion with 13 RW1C 0 Unsupported Request Completion Status or when master aborts Type 0 configuration packet that has a non zero device number Received Target Abort Status 12 RW1C 0 This bit is set when the PCI Express port receives a Completion with Completer Abort Status Signaled Target Abort This bit is set when the PCI Express port sends a completion packet with 11 RW1C 0 i x a Completer Abort Status including peer to peer completions that are forwarded from one port to another DEVSEL Timing 10 9 RO 00 Not applicable to PCI Express Hardwired to 0 Master Data Parity Error This bit is set by the PCI Express port on the secondary side PCI Express link if the Parity Error Response Enable bit PERRE is set in Bridge Control register and either of the following two c
27. MC THROTTLE OFFSETO MC THROTTLE 1 Compared against bits 36 29 of virtual temperature of each rank stored in RANK VIRTUAL TEMP to determine the throttle point Recommended value for each rank is 255 When there are more than 4 ranks attached to the channel the thermal throttle logic is shared Device 4 5 Function 3 Offset 88h Access as a DWord Bit Attr Default Description 31 24 RW 0 RANKS Rank 3 throttle offset 23 16 RW 0 RANK2 Rank 2 throttle offset 15 8 RW 0 RANK1 Rank 1 throttle offset 7 0 RW 0 RANKO Rank 0 throttle offset 271 intel 4 13 9 4 13 10 272 Processor Uncore Configuration Registers MC RANK VIRTUAL TEMPO MC RANK VIRTUAL This register contains the 8 most significant bits 37 30 of the virtual temperature of each rank The difference between the virtual temperature and the sensor temperature can be used to determine how fast fan speed should be increased The value stored is right shifted one bit to the right with respect to the corresponding MC Throttle Offset register value For example when When a rank throttle offset is set to 40h the value read from the corresponding in MC RANK VIRTUAL TEMP register is 20h When there are more than 4 ranks attached to the channel the thermal throttle logic is shared Device 4 5 Function 3 Offset 98h Access as a DWord Bit Attr Default Description 31 24 RO 0 RAN
28. Assigned by PCI SIG for subsystem capability ID SNXTPTR Subsystem I D Next Pointer Register S NXTPTR Device 3 5 PCI e Function O Offset 41h Bit Attr Default Description Next Ptr 7 0 RWO 60h This field is set to 80h for the next capability list MSI capability structure in the chain Datasheet Volume 2 51 intel Processor Integrated 1 Configuration Registers 3 3 4 3 SVI D Subsystem Vendor ID Register Device Function Offset SVID 3 5 PCIe 0 44h Bit Attr Default Description 15 0 RWO 8086h Subsystem Vendor Identification This field is programmed during boot up to indicate the vendor of the system board After it has been written once it becomes read only 3 3 4 4 SI D Subsystem Identity Register Device Function Offset SID 3 5 PCIe 0 46h Bit Attr Default Description 15 0 RWO 00h Subsystem Identification Number Assigned by the subsystem vendor to uniquely identify the subsystem 3 3 4 5 DMI RCBAR DMI Root Complex Register Block Base Address Register This is the base address for the root complex configuration space This window of addresses contains the Root complex Register set for the PCI Express hierarchy associated with the processor On Reset the Root complex configuration space is disabled and must be enabled by writing a 1 to DMIRC
29. CB BAR ABAR MBAR VTBAR and one of the downstream ports positively claimed the address Forward to that port CB BAR ABAR MBAR VTBAR TPM All other memory accesses and none of the downstream ports positively claimed the address and DMI is the subtractive decode port Forward to DMI CB BAR ABAR MBAR VTBAR TPM and none of the downstream ports positively claimed the address and DMI is not the subtractive decode port Master Abort Datasheet Volume 2 293 intel Table 5 6 Table 5 7 294 System Address Map Table 5 6 details 110 behavior for configuration requests from Intel QuickPath Interconnect and peer to peer completions from Intel QuickPath Interconnect Decoding of Outbound Configuration Requests from Processor or Peer to Peer from Intel QuickPath I nterconnect and Decoding of Outbound Peer to Peer Completions from Intel QuickPath I nterconnect ac Conditions 110 Behavior Bus 0 and legacy and device number Forward to that internal device matches one of internal device numbers Forward to the downstream subtractive B Bus 0 and legacy and device number does decode port that legacy om port us 0 NOT match one of IIO s internal device If the transaction is a configuration request numbers the request is forwarded as a Type 01 configuration transaction to the subtractive decode port Bus 0 and
30. Configuration Registers Table 3 19 Intel Trusted Execution Technology Registers cont d 400h 404h 408h 40Ch 410h 414h 418h 41Ch 420h 424h 428h 42Ch 430h 434h 438h 43Ch 440h 444h 448h 44Ch 450h 454h 458h 45Ch 460h 464h 468h 46Ch 470h 474h 478h 47Ch 480h 484h 488h 48Ch 490h 494h 498h 49Ch 4A0h 4A4h 4A8h 4ACh 4BOh 4B4h 4B8h 4BCh 4COh 4C4h 4C8h 4CCh 4D4h 4D8h 4DCh 4E0h 4E4h 4E8h 4ECh 4FOh 4F4h 4F8h TXT Public Key Datasheet Volume 2 161 3 6 1 1 162 Processor Integrated 1 Configuration Registers Intel TXT Space Registers The Intel TXT registers adhere to the public and private attributes described in XREF As described previously each Intel TXT register may have up to three ways to access it These are given the following symbolic names TXT_TXT is the memory region starting at FED2_0000h when it is accessed using the special Intel TXT read or write commands TXT PR is the memory region starting at FED2 0000h when it is accessed using normal read or write commands TXT PB is the memory region starting at FED3 0000h accessed using any read or write command TXT PB noWR is similar to TXT PB but write accesses have no affect The register tables below sometimes list more than one base for a register Normally this would indicate that there is more than one register However in the current section it indicates that the
31. PCI Express Root Port 1 Logically this appears as a virtual PCI to PCI bridge residing on PCI Bus 0 and is compliant with the PCI Express Local Bus Specification Revision 1 0 Device 3 contains the standard PCI Express PCI configuration registers including PCI Express Memory Address Mapping registers It also contains the extended PCI Express configuration space that includes PCI Express error status control registers and I sochronous and Virtual Channel controls Device 5 PCI Express Root Port 3 Logically this appears as a virtual PCI to PCI bridge residing on PCI Bus 0 and is compliant with PCI Express Local Bus Specification Revision 1 0 Device 5 contains the standard PCI Express PCI configuration registers including PCI Express Memory Address Mapping registers It also contains the extended PCI Express configuration space that include PCI Express error status control registers and Isochronous and Virtual Channel controls Device 8 Integrated 1 0 Core This device contains the Standard PCI registers for each of its functions This device implements four functions Function 0 contains Address Mapping Intel Virtualization Technology Intel VT for Directed 1 0 Intel VT d related registers and other system management registers Function 1 contains Semaphore and Scratchpad registers Function 3 contains System Datasheet Volume 2 19 intel 20 Configuration Process and Registers Control Status registers and Fu
32. 1 5 54h MC WAY 21 D4h MC RIR LIMIT CHI 6 58h MC RIR WAY 1 22 D8h MC RIR LIMIT 1 7 5Ch MC RIR WAY 23 DCh RIR WAY 1 24 EOh RIR WAY 1 25 E4h RIR WAY 1 26 E8h WAY 1 27 ECh MC_RIR_WAY_CH1_28 FOh MC_RIR_WAY_CH1_29 F4h MC RIR WAY CH1 30 F8h MC RIR WAY 31 FCh Datasheet Volume 2 199 Processor Uncore Configuration Registers intel Table 4 17 Device 5 Function 3 Integrated Memory Controller Channel 1 Thermal Control Registers DID VID 00h MC_COOLING_COEF1 80h PCISTS PCICMD 04h MC_CLOSED_LOOP1 84h CCR RID 08h MC THROTTLE 5 88h MC RANK VIRTUAL 98h MC DDR THERM 1 MC_DDR_THERM_STATUS1 A4h MC THERMAL CONTROL1 MC THERMAL STATUS1 MC THERMAL DEFEATURE1 MC THERMAL PARAMS A1 MC THERMAL PARAMS B1 200 Datasheet Volume 2 Processor Uncore Configuration Registers L 4 4 4 4 1 4 4 2 PCI Standard Registers These registers appear in every function for every device VI D Vendor Identification Register The VID Register contains the vendor identification number This 16 bit register combined with the Device Identification Register uniquely identifies the manufacturer of the function within the processor Writes to this register have no effect Device 0 Function 0 1 Offset 00h Device 2 Function 0 1 Offset 00
33. 125 3 4 4 30 VTGENCTRL Intel VT d General Control Register 126 3 4 4 31 VTISOCHCTRL Intel VT d Isoch Related Control Register 127 3 4 4 32 VIGENCTRL2 Intel VT d General Control 2 Register 127 3 4 4 33 VTSTS Intel VT d Status 0 128 3 4 5 Semaphore and ScratchPad Registers Dev 8 1 128 3 4 5 1 SR 0 3 Scratch Pad Register 0 3 128 3 4 5 2 SR 4 7 Scratch Pad Register 4 7 128 3 4 5 3 SR 8 11 Scratch Pad Register 8 11 Non Sticky 128 3 4 5 4 SR 12 15 Scratch Pad Register 12 15 Non Sticky 129 3 4 5 5 SR 16 17 Scratch Pad Register 16 17 Non Sticky 129 3 4 5 6 SR 18 23 Scratch Pad Register 18 23 Non Sticky 129 3 4 5 7 CWR O0 3 Conditional Write Registers 0 3 129 Datasheet Volume 2 5 T 3 4 5 8 CWR 4 7 Conditional Write Registers 4 7 130 3 4 5 9 CWR 8 11 Conditional Write Registers 8 11 130 3 4 5 10 CWR 12 15 Conditional Write Registers 12 15 130 3 4 5 11 CWR 16 17 Conditional Write Registers 16 17 131 3 4 5 12 CWR 18 23 Conditional Write Re
34. Access as a DWord Bit Attr Default Description 31 8 RO 0 Reserved 7 0 RW 0 LANE_ DRIVE DC Per lane selection of DC pattern Datasheet Volume 2 235 Processor Uncore Configuration Registers intel 4 9 11 TEST EP SCCTL Memory test electrical parameter scan chain control register Device 3 Function 4 Offset F8h Access as a DWord Bit Attr Default Description 31 RW1S 0 5 _ Perform a scan chain read 30 RWIS 0 SCAN_WRITE Perform a san chain write 29 16 RO 0 Reserved 15 0 RW 0 SCAN OFFSET Shift count to perform upon next shift command 4 9 12 MC TEST EP SCD Memory test electrical parameter scan chain data register Device 3 Function 4 Offset FCh Access as a DWord Bit Attr Default Description DATA 31 0 RW 0 Contains the data written to or read from the scan chain 236 Datasheet Volume 2 Processor Uncore Configuration Registers 4 10 4 10 1 intel Integrated Memory Controller Channel Control Registers MC CHANNEL 0 DIMM RESET CMD MC CHANNEL 1 DIMM RESET CMD Integrated Memory Controller DI MM reset command register This register is used to sequence the reset signals to the DIMMs Device 4 5 Function O Offset 50h Access as a DWord Bit Attr Default Description 31 3 RO 0 Reserved 2 RW 0 BLOCK_CKE When set will be forced to be deasserted 1 R
35. RO Reserved RW PAM4_LOENABLE 008000 ODBFFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D8000h to ODBFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM Datasheet Volume 2 211 4 5 4 212 Processor Uncore Configuration Registers SAD_HEN Register for legacy Hole Enable Device 0 Function 1 Offset 48h Access as a DWord Bit Attr Default Description 31 8 RO 0 Reserved HEN This field enables a memory hole in DRAM space The DRAM that lies 7 RW 0 behind this space is not remapped 0 No Memory hole 1 Memory hole from 15 MB to 16 MB 6 0 RO 0 Reserved SAD_SMRAM Register for legacy 9Dh address space Device 0 Function 1 Offset 4Ch Access as a DWord Bit Attr Default Description 31 15 RO 0 Reserved SMM Space Open D_ OPEN When D_OPEN 1 and D_LCK 0 the SMM space DRAM is made visible even 14 RW 0 when SMM decode is not active This is intended to help BIOS initialize SMM space Software should ensure that D 1 and D_CLS 1 not set at the same time SMM Space Closed D_ CLS When D CLS 1 SMM space D
36. not in the Device Control register 0 No non Fatal Errors detected 1 Non Fatal errors detected Correctable Error Detected This bit applies only to the root DMI ports This bit gets set if a correctable error is detected by the device Errors are logged in this register regardless 0 RO 0 of whether error reporting is enabled or not the PCI Express Device Control register 0 No correctable errors detected 1 Correctable errors detected 116 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 4 4 Intel VT d Address Mapping System Management Registers Device 8 Function 0 3 4 4 1 OMI SCCTRL I ntegrated 1 Misc Control Register Register I OMISCCTRL Device 8 Function O Offset 98h Bit Attr Default Description 31 14 RV 0 Reserved CPUCSR IB Abort 13 RW 0 This bit controls if inbound access to CPUCSR range is enabled 0 IB access to CPUCSR range is disabled that is allowed 1 IB access to CPUCSR range is enabled that is disallowed Lock Thawing Mode Mode controls how inbound queues in the south agents PCle DMI thaw 12 RW 0 when they are target of a locked read 0 Thaw only posted requests 1 Thaw posted and non posted requests SUBDECEN Indicates the port that provides the subtractive decode path for inbound and outbound decode 00 DMI 11 10 RW 00 01 Reserved 10 Reserved 11 Int
37. 1 8 4 12 4 MC RIR WAY CH1 1 RIR WAY CH1 3 MC RIR WAY 1 5 MC RIR WAY 1 7 MC RIR WAY 1 9 MC RIR WAY CHO RIR WAY 1 10 RIR WAY 1 12 RIR WAY 1 14 RIR WAY 1 16 RIR WAY 1 18 RIR WAY CH1 20 MC RIR WAY 1 22 RIR WAY 1 24 MC RIR WAY CHI 11 RIR WAY 1 13 WAY 1 15 WAY 1 17 RIR WAY 1 19 WAY 1 21 MC WAY 1 23 MC WAY 1 25 Datasheet Volume 2 MC_RIR_WAY_CH1_26 MC_RIR_WAY_CH1_27 MC_RIR_WAY_CH1_28 MC_RIR_WAY_CH1_29 MC RIR WAY CH1 30 MC_RIR_WAY_CH1_ 31 2 267 4 13 Memory Thermal menses 268 4 13 1 MC_THERMAL_CONTROLO THERMAL CONTROLI nitinpis gip g 268 4 13 2 MC_THERMAL_STATUSO THERMAL STATUS T uico ero En dade 268 4 13 3 MC THERMAL DEFEATUREO MC THERMAL DEFEATUREL nre enasna T Reale dad 269 4 13 4 MC THERMAL PARAMS 0 THERMAL PARAMS 1 epe EAR 269 4 13 5 MC_THERMAL_PARAMS_BO MC THERMAL PARAMS 270 4 13 6 MC_COOLING_COEFO MC COOLING 270 4 13 7 MC_CLOSED_LOOPO CLOSED LOOP I Lio
38. 102 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 4 2 5 RI D Revision Identification Register This register contains the revision number of the Integrated I O Register RID Device 8 Function 0 3 Offset 08h Bit Attr Default Description Minor Revision 7 4 RO See Steppings which required all masks be regenerated Refer to the Intel description Core 17 800 15 700 Desktop Processor Series Specification Update for the value of the Revision ID Register Minor Revision Identification Number RID 3 0 RO See Increment for each steppings which do not require masks to be regenerated description Refer to the Intel Core 17 800 15 700 Desktop Processor Series Specification Update for the value of the Revision ID Register 3 4 2 6 CCR Class Code Register This register contains the Class Code for the device Register CCR Device 8 Function 0 3 Offset 09h Bit Attr Default Description BaseClass 23 16 RO 08h Provides the PCI Express base class type Most common registers will default to 08h Base system peripherals SubClass 15 8 RO 80h This field defaults to 80h indicating other system peripherals in PCI v3 0 class code mnemonic Register Level Programming I nterface 10 RO unn This field is hardwired to 00 3 4 2 7 CLSR Cacheline Size Register Register CLSR Device 8 F
39. 2 Software servicing the IWC field in the Fault Status register 29 0 RO 0 Reserved 3 5 2 23 INV COMP EVT DATA O0 1 1 nvalidation Completion Event Data Register Register COMP EVT DATA O0 1 Addr MMI O BAR VTBAR Offset A4h 10A4h Bit Attr Default Description 31 16 RO 0 Reserved 15 0 RW 0 Interrupt Data 3 5 2 24 INV_COMP_EVT_ADDR 0 1 I nvalidation Completion Event Address Register Register INV_COMP_EVT_ADDR 0 1 Addr MMIO BAR VTBAR Offset A8h 10 8 Bit Attr Default Description 31 2 RW 0 Interrupt Address 1 0 RO 0 Reserved Datasheet Volume 2 153 Processor Integrated 1 Configuration Registers intel 3 5 2 25 INV COMP EVT UPRADDR O 1 1 nvalidation Completion Event Upper Address Register Register COMP EVT UPRADDR O 1 Addr MMI O BAR VTBAR Offset ACh 10ACh Bit Attr Default Description Address 31 0 RW 0 Integrated 1 0 supports extended interrupt mode and implements this register 3 5 2 26 INTR REMAP TABLE BASE O0 1 Interrupt Remapping Table Base Address Register RegisteR INTR REMAP TABLE BASE O 1 Addr MMI O BAR VTBAR Offset B8h 10B8h Bit Attr Default Description Intr Remap Base 63 12 RW 0 This field points to the base of the page aligned interrupt remapping table If the Interrupt Remapping Table is larger than 4 KB in size it must be si
40. 222 4 7 6 MC CHANNEL e meme nenne 223 4 7 7 Fer b PU EN KEEN DN EFT PP M UNT 223 4 8 224 4 7 9 MC RD CRDT INIT erectio rettet Ra ier eer expe hor ba FO ERE ER Gas 225 45710 MC_CRDT WR THE Di rna ashes EN UEM 226 TAD Target Address Decoder Registers sssssssssssssseeeenmmm m 227 4 8 1 DRAM RULE 0 TAD DRAM 1 TAD DRAM RULE 2 TAD DRAM RULE 3 TAD DRAM RULE 4 TAD DRAM RULE 5 DRAM RULE 6 TAD DRAM RULE 7 4 20 227 4 8 2 INTERLEAVE LIST 0 INTERLEAVE LIST 1 TAD INTERLEAVE LIST 2 TAD INTERLEAVE LIST 3 TAD INTERLEAVE LIST 4 TAD INTERLEAVE LIST 5 INTERLEAVE LIST 6 INTERLEAVE LIST 7 228 Integrated Memory Controller Test Registers e 229 4 9 1 Integrated Memory Controller Padscan 229 4 9 2 MC DIMM CLK RATIO STATUS itineri iiam bri ado cba a nde a 231 4 9 3 DIMM CLK PL DH REDE Nx MERE RE 232 4 9 4 MC TEST Bk MEMENTO 232 4 9 5 MC TEST PH CTR EUER 233 4 9 6 MC TEST PH PISA iiit cio hir te 233 4 9 7 MC TEST PAT GOIR invece Rev E EH ives EEn FT PPP QE FEDERE R
41. Capability Pointer The CAPPTR provides the offset to the location of the first device capability in the capability list Register CAPPTR Device 8 Function 0 3 Offset 34h Bit Attr Default Description 40h 0 1 2 Capability Pointer Points to the first capability structure for the device 7 0 RO 00h Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 4 2 12 3 4 2 13 3 4 3 3 4 3 1 intel INTLI N I nterrupt Line Register The Interrupt Line register is used to communicate interrupt line routing information between initialization code and the device driver Register INTLIN Device 8 Function 0 2 Offset 3Ch Bit Attr Default Description Interrupt Line 7 0 RO 00h This bit is RW for devices that can generate a legacy INTx message and is needed only for compatibility purposes INTPI N I nterrupt Pin Register Indicates what INTx message a device generates This register has no meaning for Device 8 Register INTPIN Device 8 Function 0 2 Offset 3Dh Bit Attr Default Description Interrupt Pin 7 0 RO 00h These bits have no meaning for the device called out in this section and are hard coded to 0 Common Extended Configuration Space Registers CAPI D PCI Express Capability List Register The PCI Express Capability List register enumerates the PCI Express Capability structure in the
42. MSI Control 53 3 3 4 9 MSIAR MSI Address 54 3 3 4 10 MSIDR MSI Data 55 3 3 4 11 MSIMSK MSI Mask Bit 55 3 3 4 12 MSIPENDING MSI Pending Bit 24 56 3 3 4 13 PEGCAPID PCI Express Capability Identity Register 56 3 3 4 14 PEGNXTPTR PCI Express Next Pointer 56 3 3 4 15 Express Capabilities Register 57 3 3 4 16 DEVCAP PCI Express Device Capabilities Register 58 3 3 4 17 DEVCTRL PCI Express Device Control Register 59 3 3 4 18 DEVSTS PCI Express Device Status 61 3 3 4 19 LNKCAP PCI Express Link Capabilities Register 62 3 3 4 20 Express Link Control Register Device 0 64 3 3 4 21 Express Link Control 65 3 3 4 22 LNKSTS PCI Express Link Status 66 3 3 4 23 SLTCAP PCI Express Slot Capabilities Register 68 3
43. OOh FFh 1000h 10FFh 138 Intel VT d Memory Mapped Registers 100h 1FFh 1100 11 139 Intel Trusted Execution Technology 0 157 Intel Trusted Execution Technology Registers 158 Intel Trusted Execution Technology Registers 159 Intel Trusted Execution Technology Registers 160 Intel Trusted Execution Technology Registers 0 211 161 Intel QuickPath Interconnect Physical Link Map Port 0 Device 16 176 CSR Intel QuickPath Interconnect Routing Layer Protocol Device 16 Function 1 180 Functions Specifically Handled by the 184 Device 0 Function 0 Generic Non core Registers 185 Device 0 Function 1 System Address Decoder 186 Device 2 Function 0 Intel QuickPath Interconnect Link 0 Registers 187 Device 2 Function 1 Intel QuickPath Interconnect Physical 0 Registers 188 Device 3 Function 0 Integrated Memory Controller Registers 189 Device 3 Function 1 Target Address Dec
44. PCISTS PCICMD CCR Datasheet Volume 2 185 Processor Uncore Configuration Registers intel Table 4 3 Device 0 Function 1 System Address Decoder Registers DID VID 00h SAD_DRAM_RULE_0 80h PCISTS PCICMD 04h SAD_DRAM_RULE_1 84h CCR SAD_DRAM_RULE_2 88h SAD_DRAM_RULE_3 8Ch SAD_DRAM_RULE_4 90h SAD_DRAM_RULE_5 94h SAD DRAM RULE 6 98h SAD DRAM RULE 7 SAD 0123 40h SAD INTERLEAVE LIST 0 COh SAD PAM456 44h SAD INTERLEAVE LIST 1 C4h SAD HEN 48h SAD INTERLEAVE LIST 2 C8h SAD SMRAM 4Ch SAD INTERLEAVE LIST 3 CCh 50h SAD INTERLEAVE LIST 4 DOh SAD PCIEXBAR 54h SAD INTERLEAVE LIST 5 D4h 58h SAD INTERLEAVE LIST 6 D8h SAD TPCIEXBAR 5Ch SAD INTERLEAVE LIST 7 DCh 60h SAD MCSEG BASE 64h 68h SAD MCSEG MASK 6Ch 70h SAD MESEG BASE 74h 78h SAD MESEG MASK 7Ch 186 Datasheet Volume 2 Processor Uncore Configuration Registers Table 4 4 intel Device 2 Function 0 Intel QuickPath Interconnect Link Registers DID VID PCISTS PCICMD CCR QPI QPILCL LO Datasheet Volume 2 187 Processor Uncore Configuration Registers intel Table 4 5 Device 2 Function 1 Intel QuickPath I nterconnect Physical O Registers DID VID PCISTS PCI CMD CCR 188 Datasheet Volume 2 Processor Uncore Configuration Registers
45. Table 4 6 Device 3 Function 0 Integrated Memory Controller Registers DID VID PCISTS PCICMD CCR MC CONTROL MC STATUS 5 DIMM ERROR STATUS SMI CNTRL MC RESET CONTROL MC CHANNEL MAPPER MC MAX DOD MC CFG LOCK MC RD CRDT INIT MC CRDT WR THLD Datasheet Volume 2 00h 4Ch 50h 60h 64h 189 Processor Uncore Configuration Registers intel Table 4 7 Device 3 Function 1 Target Address Decoder Registers DID VID 00h TAD_DRAM_RULE_0 80h PCISTS PCICMD 04h TAD_DRAM_RULE_1 84h CCR RID 08h TAD DRAM RULE 2 88h OCh TAD DRAM RULE 3 8Ch TAD DRAM RULE 4 90h TAD DRAM RULE 5 94h TAD DRAM RULE 6 98h TAD DRAM RULE 7 TAD INTERLEAVE LIST 0 TAD INTERLEAVE LIST 1 C4h TAD INTERLEAVE LIST 2 C8h TAD INTERLEAVE LIST 3 CCh TAD INTERLEAVE LIST 4 DOh TAD INTERLEAVE LIST 5 D4h TAD INTERLEAVE LIST 6 D8h TAD INTERLEAVE LIST 7 190 Datasheet Volume 2 Processor Uncore Configuration Registers m Table 4 8 Device 3 Function 2 Memory Controller Test Registers DID VID 00h 80h PCISTS PCICMD 04h 84h CCR RID 08h 88h OCh Datasheet Volume 2 191 Processor Uncore Configuration Registers intel Table 4 9 Device 3 Function 4 Integrated Memory Controller Test Registers DID VID
46. WAY 5 94h MC WAY CHO 6 98h WAY CHO 7 9Ch WAY CHO 8 AOh MC RIR WAY CHO 9 A4h MC RIR WAY CHO 10 A8h MC RIR WAY CHO 11 ACh MC RIR WAY CHO 12 BOh MC RIR WAY CHO 13 B4h MC RIR WAY CHO 14 B8h MC RIR WAY CHO 15 BCh MC RIR LIMIT CHO 0 40h MC RIR WAY CHO 16 COh MC RIR LIMIT CHO 1 44h MC RIR WAY CHO 17 C4h MC RIR LIMIT CHO 2 48h MC RIR WAY CHO 18 C8h MC RIR LIMIT CHO 3 4Ch MC RIR WAY CHO 19 CCh MC RIR LIMIT CHO 4 50h MC RIR WAY CHO 20 DOh MC RIR LIMIT CHO 5 54h MC RIR WAY CHO 21 D4h MC RIR LIMIT CHO 6 58h MC RIR WAY CHO 22 D8h MC RIR LIMIT CHO 7 5Ch MC RIR WAY CHO 23 DCh MC RIR WAY CHO 24 EOh MC RIR WAY CHO 25 E4h MC RIR WAY CHO 26 E8h MC RIR WAY CHO 27 ECh MC RIR WAY CHO 28 FOh MC RIR WAY CHO 29 F4h MC RIR WAY CHO 30 F8h MC RIR WAY CHO 31 FCh Datasheet Volume 2 195 Processor Uncore Configuration Registers intel Table 4 13 Device 4 Function 3 Integrated Memory Controller Channel 0 Thermal Control Registers DID VID 00h MC COOLING COEFO 80h PCISTS PCICMD 04h MC_CLOSED_LOOPO 84h CCR RID 08h MC THROTTLE OFFSETO 88h MC RANK VIRTUAL TEMPO 98h MC DDR THERM COMMANDO 9Ch MC DDR THERM STATUSO A4h MC THERMAL CONTROLO MC THERMAL STATUSO MC THERMAL DEFEATUREO MC THERMAL PARAMS AQ MC THERMAL PARAMS BO 196 Datasheet Volume 2 Processor Uncore Configuration Registers Table 4 14 Device 5 Function 0 Int
47. is generated on the PCI Express link targeting the device directly on the opposite side of the link This should be Device 0 on the bus number assigned to the PCI Express link likely Bus 1 The device on other side of link must be Device 0 The processor will Master Abort any Type 0 Configuration access to a non zero Device number If there is to be more than one device on that side of the link there must be a bridge implemented in the downstream device When the Bus Number of a Type 1 Standard PCI Configuration cycle or PCI Express Enhanced Configuration access is within the claimed range between the upper bound of the bridge device s Subordinate Bus Number register and the lower bound of the bridge device s Secondary Bus Number register but doesn t match the Device 1 Secondary Bus Number a PCI Express Type 1 Configuration TLP is generated on the secondary side of the PCI Express link PC The processor will translate writes to PCI Express extended configuration space to configuration writes on the backbone internally Express Configuration Writes Posted writes to extended space are non posted on the PCI Express or DMI that is translated to configuration writes Datasheet Volume 2 Configuration Process and Registers L D 2 3 2 2 2 4 DMI Configuration Accesses Accesses to disabled processor internal devices bus numbers not claimed by the Host PCI Express bridge or PCI Bus 0 devices not part of the processor
48. 11 Reserved MAXNUMROW Maximum Number of Rows 000 2 12 Rows 001 2 13 Rows 8 6 RW 0 010 2 14 Rows 011 2 15 Rows 100 2 16 Rows Others Reserved MAXNUMBANK Maximum Number of Banks 00 Four banked 01 Eight banked 10 Sixteen banked 5 4 RW 0 Datasheet Volume 2 223 Processor Uncore Configuration Registers Device 3 Function 0 Offset 64h Access as a DWord Bit Attr Default Description MAXNUMRANK Maximum Number of Ranks 00 Single Ranked 5 2 RW 9 01 Double Ranked 10 Reserved MAXNUMDI MMS Maximum Number of DI MMs 00 1 DIMM 1 0 RW 0 01 2 DIMMs 10 Reserved 11 Reserved 4 7 8 LOCK BIOS must write the LOCK bit after configuration is complete to allow the Integrated Memory Controller to start accepting requests Device 3 Function 0 Offset 68h Access as a DWord Bit Attr Default Description 31 2 RO 0 Reserved MC_CFG_UNLOCK 1 WO 0 This bit unlocks the Integrated Memory Controller configuration registers without processor reset This bit does NOT unlock any other lock type without a processor reset MC CFG LOCK 0 WO 0 This bit locks the Integrated Memory Controller configuration registers Writes are no longer allowed to the configuration registers 224 Datasheet Volume 2 Processor Uncore Configuration Registers L 4 7 9 MC_RD_CRDT_INIT These regis
49. 119 3 4 4 13 LMMIOH BASE Local 119 3 4 4 14 LMMIOH LIMIT Local MMI OH 0 0 2 20 2 119 3 4 4 15 LMMIOH BASEU Local MMI OH Base Upper 120 3 4 4 16 LMMIOH LIMITU Local MMI OH Limit 120 3 4 4 17 LCFGBUS BASE Local Configuration Bus Number Base Register 120 3 4 4 18 LCFGBUS LI MI T Local Configuration Bus Number Limit Register 121 3 4 4 19 GMMIOL BASE Global MMIOL Base 121 3 4 4 20 GMMIOL LIMIT Global MMIOL 1 121 3 4 4 21 GMMIOH BASE Global MMI OH Base 122 3 4 4 22 GMMI OH LI MI T Global MMI OH 0 220 444 122 3 4 4 23 GMMIOH BASEU Global MMI OH Base 123 3 4 4 24 GMMIOH LIMITU Global MMI OH Limit Upper 123 3 4 4 25 GCFGBUS BASE Global Configuration Bus Number Base Register 123 3 4 4 26 GCFGBUS LI MI T Global Configuration Bus Number Limit Register 124 3 4 4 27 MESEGBASE Intel Management Engine Intel ME Memory Region 00 teeta eene 124 3 4 4 28 MESEGMASK Intel ME Memory Region Mask 124 3 4 4 29 VTBAR Base Address Register for Intel VT d Chipset Registers
50. 3 4 5 10 CWR 12 15 Conditional Write Registers 12 15 Register CWR 12 15 Device Function 1 Offset 110h 11Ch by 4 Bit Attr Default Description Conditional Write These registers are physically mapped to scratch pad registers A read from 31 0 RWLB Oh CWR n reads SR n A write to CWR n writes SR n if SR n 0 0 before the write and has no effect otherwise The registers provide firmware with synchronization variables semaphores that are overloaded onto the same physical registers as SR 130 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 4 5 11 CWR 16 17 Conditional Write Registers 16 17 Register CWR 16 17 Device 8 Function 1 Offset 18h 124h by 4 Bit Attr Default Description Conditional Write These registers are physically mapped to scratch pad registers A read from CWR n reads SR n A write to CWR n writes SR n if SR n 0 0 before the 31 0 RWLB Oh k write and has no effect otherwise The registers provide firmware with synchronization variables semaphores that are overloaded onto the same physical registers as SR 3 4 5 12 CWR 18 23 Conditional Write Registers 18 23 Register CWR 18 23 Device Function 1 Offset 128h 13Ch by 4 Bit Attr Default Description Conditional Write These registers are physically mapped to scratch pad registers A read from CWR n reads SR n A write
51. 31 0 RWSLB Oh CWR n reads SR n A write to CWR n writes SR n if SR n 0 0 before the write and has no effect otherwise The registers provide firmware with synchronization variables semaphores that are overloaded onto the same physical registers as SR Datasheet Volume 2 129 intel Processor Integrated 1 Configuration Registers 3 4 5 8 CWR 4 7 Conditional Write Registers 4 7 Register CWR 4 7 Device 8 Function 1 Offset OECh OF8h by 4 Bit Attr Default Description Conditional Write These registers are physically mapped to scratch pad registers A read from 31 0 RWSLB Oh CWR n reads SR n A write to CWR n writes SR n if SR n 0 0 before the write has no effect otherwise The registers provide firmware with synchronization variables semaphores that are overloaded onto the same physical registers as SR 3 4 5 9 CWR 8 11 Conditional Write Registers 8 11 Register CWR 8 11 Device Function 1 Offset OFCh 104h 10Ch by 4 Bit Attr Default Description Conditional Write These registers are physically mapped to scratch pad registers A read from 31 0 RWLB Oh CWR n reads SR n A write to CWR n writes SR n if SR n 0 0 before the write and has no effect otherwise The registers provide firmware with synchronization variables semaphores that are overloaded onto the same physical registers as SR
52. Configuration Registers SVI D Subsystem Vendor ID This register identifies the vendor of the subsystem This 16 bit register combined with the Device Identification Register uniquely identify any PCI device Register SVID Device 0 DMI Function 0 Offset 2Ch Bit Attr Default Description Subsystem Vendor Identification 15 0 RWO 8086h This field is programmed during boot up to indicate the vendor of the system board After it has been written once it becomes read only SI D Subsystem I dentity This register identifies the particular subsystem Register SID Device 0 DMI Function 0 Offset 2Eh Bit Attr Default Description Subsystem Identification Number 15 0 RWO 00h Assigned by the subsystem vendor to uniquely identify the subsystem CAPPTR Capability Pointer The CAPPTR provides the offset to the location of the first device capability in the capability list Register CAPPTR Device 0 DMI 3 5 PCIe Function O Offset 34h Bit Attr Default Description Capability Pointer 7 0 RWO 40h Points to the first capability structure for the device I NTLI N I nterrupt Line Register The Interrupt Line register is used to communicate interrupt line routing information between initialization code and the device driver The device itself does not use this value OS and device drivers use this to determine priority and vecto
53. Detect Parity Error DPE 15 RO 0 The host bridge does not implement this bit and it is hardwired to a 0 Writes to this bit position have no effect Signaled System Error SSE This bit is set to 1 when this device generates an SERR message over the bus 14 RO 0 for any enabled error condition If the host bridge does not signal errors using this bit this bit is hardwired to a 0 and is read only Writes to this bit position have no effect Received Master Abort Status RMAS This bit is set when this device generates request that receives an Unsupported Request completion packet Software clears the bit by writing 1 13 RO 0 to it If this device does not receive Unsupported Request completion packets this bit is hardwired to 0 and is read only Writes to this bit position have no effect Received Target Abort Status RTAS This bit is set when this device generates a request that receives a Completer 12 RO 0 Abort completion packet Software clears this bit by writing a 1 to it If this device does not receive Completer Abort completion packets this bit is hardwired to 0 and read only Writes to this bit position have no effect Signaled Target Abort Status STAS 11 RO 0 This device will not generate a Target Abort completion or Special Cycle This bit is not implemented in this device and is hardwired to a 0 Writes to this bit position have no effect DEVSEL Timing DEVT These bits are hardwired to 00 Writes to these bit positions
54. Function 0 Offset COh Bit Attr Default Description 15 13 RO 0 Reserved Compliance De Emphasis This bit sets the de emphasis level in Polling Compliance state if the entry 12 RWS 0 occurred due to the Enter Compliance bit being 1b 1b 3 5 dB Ob 6 dB Compliance SOS 11 RWS 0 When set to 1 the LTSSM is required to send SKP Ordered Sets periodically in between the modified compliance patterns Enter Modified Compliance 10 RWS 0 When this bit is set to 1 the device transmits Modified Compliance Pattern if the LTSSM enters Polling Compliance substate Transmit Margin 9 7 RWS 0 This field controls the value of the non de emphasized voltage level at the Transmitter pins Selectable De Emphasis When the Link is operating at 5 0 GT s speed this bit selects the level of de emphasis for an Upstream component Encodings RWO 9 1b 3 5 dB Ob 6 dB When the Link is operating at 2 5 GT s speed the setting of this bit has no effect Hardware Autonomous Speed Disable 5 RW 0 When set to 1 this bit disables hardware from changing the Link speed for device specific reasons other than attempting to correct unreliable Link operation by reducing Link speed Enter Compliance 4 RWS 0 Software is permitted to force a link to enter Compliance mode at the speed indicated in the Target Link Speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link Target Link Speed This field sets an upper limit on
55. MMIOL i iter peux EINER oe aged 282 5 2 5 3 Miscellaneous eire rie 282 5 2 5 4 Processor Local CSR On die ROM and Processor PSeg 282 5 2 5 5 2 282 5 2 59 6 Local XAPIC dire reg exer ekle totas 283 5 2 5 7 High BIOS Area soe DURER KA RIRUE ER DU ITO ZEE 283 52 98 INTA RSVO uiii tette R UR BR dE 283 5 2 5 9 PBIEIWOEG RUM eren n 283 5 2 6 Address Regions above 4 GB ssssssssssessee meme senem emen nnns 284 5 2 6 1 High System Memory 1 nena 284 5 2 6 2 Memory Mapped 10 1 284 5 2 6 3 BIOS Notes on Address Allocation above 4 GB 285 5 2 7 Protected System DRAM 0 22 22 2 285 5532 egre ear tia ss ase 285 5 3 1 Addresses idR eid 285 5 3 2 ISA Addresses ouis vertes ERE 286 5 3 3 286 5 3 4 PCle Device 1 0 Addresses
56. Space Ox1FFFFF PCI Compatible Configuration Device 1 Function 1 Space OxFFFFF PCI Compatible Device 0 Function 0 Configuration Space Header 0 Located by PCI Express Base Address As with PCI devices each device is selected based on decoded address information that is provided as a part of the address portion of Configuration Request packets A Express device will decode all address information fields bus device function and extended address numbers to provide access to the correct register To access this space step 1 is done only once by BIOS 1 Write to CSR address 01050h to enable the PCI Express enhanced configuration mechanism by writing 1 to Bit of the SAD PCIEXBAR register Allocate either 256 128 or 64 busses to PCI Express by writing 000 111 or 110 respectively to Bits 3 1 Pick a naturally aligned base address for mapping the configuration space onto memory space using 1 MB per bus number and write that base address into Bits 39 20 2 Calculate the host address of the register you wish to set using PCI Express base bus number 1 MB device number 32 KB function number 4 KB 1 B offset within the function host address 3 Use a memory write or memory read cycle to the calculated host address to write or read that register Datasheet Volume 2 Configuration Process and Registers 2 3 Routing Configuration Accesses intel The processor sup
57. is hardwired to 06h indicating it is a Bridge Device Sub Class This field qualifies the Base Class providing a more detailed specification of 15 8 RO 0 the device function For all devices the default is 00h indicating Host Bridge Register Level Programming Interface This field identifies a specific programming interface if any that device 7 0 RO 0 independent software can use to interact with the device There are no such interfaces defined for Host Bridge types and this field is hardwired to 00h Datasheet Volume 2 Processor Uncore Configuration Registers 4 4 5 HDR Header Type Register This register identifies the header layout of the configuration space Device 0 Function 0 1 Offset 08h Device 2 Function 0 1 Offset 08h Device 3 Function 0 1 4 Offset 08h Device 4 5 Function 0 3 Offset 08h Bit Attr Default Description Multi Function Device 7 RO 1 This bit selects whether this is a multi function device that may have alternative configuration layouts This bit is hardwired to 1 for devices in the processor Configuration Layout This field identifies the format of the configuration header layout for a PCI to 6 0 RO 0 PCI bridge from bytes 10h through 3Fh For all devices the default is 00h indicating a conventional type 00h PCI header 4 4 6 SVI D Subsystem Vendor Identification Register This register identifies the manu
58. processor Reads 03E0_0000h O3EF_FFFFh R W Pre allocated Graphics VGA memory 1 MB or 4 8 16 32 64 128 256 MB when IGD is enabled 03FO_0000h O3FF FFFFh R W Pre allocated Graphics GTT stolen memory 1 MB or 2 MB when IGD is enabled 5 2 5 Address Region from TOLM to 4 GB 5 2 5 1 PCI Express Memory Mapped Configuration Space This is the system address region that is allocated for software to access the PCI Express Configuration Space This region is relocatable below 4 GB by BIOS firmware and IIO has no explicit knowledge of this address range It is the responsibility of software to make sure that this system address range is not included in any of the system DRAM memory ranges that decodes inbound If software were to mis program in this way accesses to this space could potentially be sent to the processor by the IIO Datasheet Volume 2 281 intel 5 2 5 2 5 2 5 3 5 2 5 4 5 2 5 5 282 MMI OL System Address Map Address Region From To MMI OL GMMI OL Base GMMIOL Limit This region is used for PCI e device memory addressing below 4 GB Each in the system is allocated a portion of this address range and individual PCle ports and other integrated devices within an for example VTBAR use sub portions within that range There are II O specific requirements on how software allocates this system region amongst 1105 to support of peer to peer bet
59. 00h MC TEST PH PIS 80h PCISTS PCICMD 04h CCR 08h OCh MC_TEST_PAT_GCTR MC_TEST_PAT_BA MC_TEST_PAT_IS MC_TEST_PAT_DCD MC_DIMM_CLK_RATIO_STATUS MC_DIMM_CLK_RATIO MC_TEST_LTRCON 5Ch MC_TEST_PH_CTR 6Ch MC_TEST_EP_SCCTL MC_TEST_EP_SCD 192 Datasheet Volume 2 Processor Uncore Configuration Registers Table 4 10 Device 4 Function 0 Integrated Memory Controller Channel 0 Control Registers DID 00h MC CHANNEL 0 RANK TIMING A 80h PCISTS PCICMD 04h MC CHANNEL 0 RANK TIMING B 84h CCR RID 08h MC CHANNEL 0 BANK TIMING 88h OCh MC CHANNEL 0 REFRESH TIMING 8Ch MC CHANNEL 0 CKE TIMING 90h MC CHANNEL 0 ZQ TIMING 94h MC CHANNEL 0 RCOMP PARAMS 98h MC CHANNEL 0 PARAMSI 9Ch MC CHANNEL 0 ODT PARAMS2 AOh MC CHANNEL 0 ODT MATRIX RANK 0 3 RD A4h MC CHANNEL 0 ODT MATRIX RANK 4 7 RD A8h MC CHANNEL 0 ODT MATRIX RANK 0 3 WR ACh MC CHANNEL 0 ODT MATRIX RANK 4 7 WR BOh MC CHANNEL 0 WAQ PARAMS B4h CHANNEL 0 SCHEDULER_ PARAMS B8h MC CHANNEL 0 MAINTENANCE OPS BCh MC CHANNEL 0 TX BG SETTINGS COh MC CHANNEL 0 SETTINGS C8h MC CHANNEL 0 EW BGF SETTINGS CCh CHANNEL 0 DIMM RESET 50h MC CHANNEL 0 EW BGF OFFSET SETTINGS DOh MC CHANNEL 0 DIMM INIT CMD 54h MC CHANNEL 0 ROUND TR
60. 10 9 RO Oh DEVSEL Timing Not applicable to PCI Express Hardwired to 0 RO Master Data Parity Error This bit is set by a device if the Parity Error Response bit in the PCI Command register is set and it receives a completion with poisoned data from the primary side or if it forwards a packet with data including MSI writes to the primary side with poison RO Fast Back to Back Not applicable to PCI Express Hardwired to 0 RO Reserved RO 66 MHz Capable Not applicable to PCI Express Hardwired to 0 RO 1b F 0 1 2 Ob F3 Capabilities List This bit indicates the presence of a capabilities list structure RO INTx Status This bit indicates that a legacy INTx interrupt condition is pending internally This bit has meaning only in the legacy interrupt mode This bit is always 0 when MSI X has been selected for DMA interrupts Note that the setting of the INTx status bit is independent of the I NTx enable bit in the PCI command register that is this bit is set anytime the DMA engine is setup by its driver to generate any interrupt and the condition that triggers the interrupt has occurred regardless of whether a legacy interrupt message was signaled to the PCH or not Note that the INTx enable bit has to be set in the PCICMD register for DMA to generate a INTx message to the PCH This bit is not applicable to PCI Express and DMI ports 2 0 RV Oh Reserved
61. 1C4h 1C8h 1CCh 1DOh 1D4h 1D8h 1DCh 1E0h 1E4h 1E8h 1ECh 1FOh 1F4h 1F8h 1FCh 158 Datasheet Volume 2 Processor Integrated 1 Configuration Registers Table 3 17 Intel Trusted Execution Technology Registers cont d 200h 204h 208h 20Ch 210h 214h 218h 21Ch 220h 224h 228h 22Ch TXT Cmd Lock Base TXT Cmd Unlo ck Base 234h 23Ch 240h 244h 248h 24Ch 250h 254h 258h 25Ch 260h 264h 268h 26Ch 270h N N 1 w TXT SINIT MEMORY BASE TXT SINIT MEMORY SIZE Datasheet Volume 2 TXT MLE J OIN 159 Processor Integrated 1 Configuration Registers intel Table 3 18 Intel Trusted Execution Technology Registers cont d TXT Cmd Ope n 300h 380h TXT Heap Base Locality1 304h 384h TXT Cmd Clos e 388h TXT Heap Size 308h Locality1 30Ch 38Ch TXT Cmd Ope 310h n 390h TXT MSEG Base Locality2 314h 394h TXT Cmd Clos 398h Locality2 31Ch 39Ch 318h TXT MSEG Size 320h 3A0h TXT ScratchpadO 324h 3A4h 328h 3A8h TXT Scratchpad1 32Ch 330h 334h 338h 33Ch 340h 344h 348h 34Ch 350h 354h 358h 35Ch 360h 364h 368h 36Ch 370h 374h 378h 37Ch 3ACh 3BOh 3B4h 3B8h 3BCh 3COh 3C4h 3C8h 3CCh 3DOh 3D4h 3D8h 3DCh 3E0h 3E4h 3E8h 3ECh 3F0h 3F4h 3F8h 3FCh 160 Datasheet Volume 2 Processor Integrated 1
62. 3 3 5 5 CTOCTRL Completion Time out Control Register 83 3 3 6 DMI Root Complex Register 2 84 3 3 6 1 DMIVCH DMI Virtual Channel Capability 85 3 3 6 2 DMIVCCAP1 DMI Port VC Capability Register 1 85 3 3 6 3 DMIVCCAP2 DMI Port VC Capability Register 2 86 3 3 6 4 DMIVCCTL DMI Port VC Control esseere 86 3 3 6 5 DMIVCORCAP DMI VCO Resource 87 3 3 6 6 DMIVCORCTL DMI VCO Resource 87 3 3 6 7 DMIVCORSTS DMI VCO Resource 88 3 3 6 8 DMIVCIRCAP DMI VC1 Resource 88 3 3 6 9 DMIVCIRCTL DMI VC1 Resource 2 89 3 3 6 10 DMIVCIRSTS DMI VC1 Resource 90 3 3 6 11 DMILCAP DMI Link 90 3 3 6 12 DMILCTRL DMI Link 1 mes 91 3 3 6 13 DMILSTS DMI Link Status escis eese a ni mme 91 3 4 Integrated I O Core Registers Device 8 Function 0 3 92 3 4 1 Configuration Register Map Device 8 Function 0 3
63. 54h 58h 5Ch Access as a DWord Bit Attr Default Description 31 10 RO 0 Reserved LIMIT This field specifies the top of the range being mapped to the ranks specified in 9 0 RW 0 the RIR WAY CH registers The most significant bits of the lowest address in this range is one greater than the limit field in the RIR register with the next lower index This field is compared against MA 37 28 Datasheet Volume 2 265 4 12 3 266 Processor Uncore Configuration Registers MC RIR WAY CHO 0 MC RIR WAY CHO 1 MC RIR WAY CHO 2 MC RIR WAY CHO 3 MC RIR WAY CHO 4 MC RIR WAY CHO 5 MC RIR WAY CHO 6 MC RIR WAY CHO 7 MC RIR WAY CHO 8 MC RIR WAY CHO 9 MC RIR WAY CHO 10 MC RIR WAY CHO 11 MC RIR WAY CHO 12 MC RIR WAY CHO 13 MC RIR WAY CHO 14 MC RIR WAY CHO 15 MC RIR WAY CHO 16 MC RIR WAY CHO 17 MC RIR WAY CHO 18 MC RIR WAY CHO 19 MC RIR WAY CHO 20 MC RIR WAY CHO 21 MC RIR WAY CHO 22 MC RIR WAY CHO 23 MC RIR WAY CHO 24 MC RIR WAY CHO 25 MC RIR WAY CHO 26 MC RIR WAY CHO 27 MC RIR WAY CHO 28 MC RIR WAY CHO 29 MC RIR WAY CHO 30 MC RIR WAY CHO 31 Channel Rank Interleave Way Range Registers These registers allow the user to define the ranks and offsets that apply to the ranges defined by the LIMIT in the MC RIR LIMIT CH registers The mappings are as follows RIR LIMIT CH chan 0 gt WAY 3 01 RIR LIMIT CH chan 1 gt RIR WAY CH chan 7 6 RIR LIMIT CH chan 2 gt RIR W
64. 6 way interleave REMOVED 26 24 RW 0 These are the bits to be removed after offset subtraction These bits correspond to System Address 8 7 6 OFFSET 23 0 RW 0 This value should be subtracted from the current system address to create a contiguous address space within a channel BITS 9 0 ARE RESERVED AND MUST ALWAYS BE SET TO 0 Datasheet Volume 2 Processor Uncore Configuration Registers 4 12 Integrated Memory Controller Channel Rank Registers 4 12 1 MC LIMIT CHO 0 MC LIMIT CHO 1 MC RIR LIMIT CHO 3 MC RIR LIMIT CHO 5 MC RIR LIMIT CHO 7 MC RIR LIMIT CHO 2 MC RIR LIMIT CHO 4 MC RIR LIMIT CHO 6 Channel 0 Rank Limit Range Registers Device 4 Function 2 Offset 40h 44h 48h 4Ch 50h 54h 58h 5Ch Access as a DWord Bit Attr Default Description 31 10 RO 0 Reserved LIMIT This field specifies the top of the range being mapped to the ranks 9 0 RW 0 specified in the MC RIR WAY CH registers The most significant bits of the lowest address in this range is one greater than the limit field in the RIR register with the next lower index This field is compared against MA 37 28 4 12 2 MC_RIR_LIMIT_CH1_0 MC_RIR_LIMIT_CH1_2 MC_RIR_LIMIT_CH1_4 MC_RIR_LIMIT_CH1_6 Channel 1 Rank Limit Range Registers RIR LIMIT 1 1 MC_RIR_LIMIT_CH1_ 3 MC_RIR_LIMIT_CH1_5 MC_RIR_LIMIT_CH1_7 Device Function Offset 5 2 40h 44h 48h 4Ch 50h
65. 9 MC CHANNEL 0 RANK PRESENT MC CHANNEL 1 RANK 244 4 10 10MC CHANNEL 0 RANK TIMING MC CHANNEL 1 RANK TIMING A eee eene nenne nnne nns 245 4 10 11MC CHANNEL 0 RANK TIMING B MC CHANNEL 1 RANK TIMING 2 2000004 247 4 10 12MC CHANNEL 0 BANK TIMING MC CHANNEL 1 BANK 2 004002 248 4 10 13MC CHANNEL 0 REFRESH TIMING MC CHANNEL 1 REFRESH TIMING ssesssm IH mme mmn 248 4 10 14MC CHANNEL 0 CKE TIMING MC CHANNEL 1 CKE PUR 249 4 10 15 MC CHANNEL _ 0 ZQ_ TIMING MC 250 4 10 16MC CHANNEL 0 RCOMP PARAMS MC CHANNEL 1 RCOMP PARAMS ssssssese meme emen enn 250 4 10 17MC CHANNEL 0 ODT PARAMS1 MC CHANNEL 1 1 011 2 251 4 10 18MC CHANNEL 0 ODT PARAMS2 MC CHANNEL 1 P RAMSG2 iszssssiroxsirisxtaex copio nk b ka oc b E 252 4 10 19MC CHANNEL _ o ODT_MATRIX_RANK_0_3_RD CHANNEL 1 ODT MATRIX RANK 0 3 252 4 10 20MC CHANNEL O0 MATRIX RANK 4 7 RD MC CHANNEL 1 ODT MATRIX RANK 4 7 253 4 10 21MC CHANNEL 0 ODT MATRIX RANK 0 3 WR MC CHANNEL 1 MATRIX RANK O0 3 WR 253 4 10 22MC CHANNEL 0 ODT MATRIX RANK 4 7 WR MC CHANNEL 1 ODT MATRI
66. Attr Default Description Power Management Event PME Support 31 27 RO 11001 Bits 31 30 and 27 must be set to 1 for PCI to PCI bridge structures representing ports on root complexes 26 RO 0 D2 Support Integrated 1 does not support power management state D2 25 RO 0 D1 Support Integrated I O does not support power management state D1 24 22 RO Oh Reserved 21 RO 0 Device Specific I nitialization 20 RV 0 Reserved 19 RO 0 iene This field is hardwired to Oh as it does not apply to PCI Express Version 18 16 RO 011 This field is set to 3h PM 1 2 compliant as version number for all PCI Express ports Next Capability Pointer 15 8 RO 00h This is the last capability in the chain and hence set to 0 Capability ID 7 0 RO Olh Provides the PM capability ID assigned by PCI SIG 76 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 3 4 33 PMCSR Power Management Control and Status Register Device 0 DMI This register provides status and control information for PM events on the DMI port Register PMCSR Device 0 DMI Function 0 Offset E4h Bit Attr Default Description 31 24 RO 00h Reserved 23 RO Oh Bus Power Clock Control Enable This field is hardwired to Oh as it does not apply to PCI Express 22 RO Oh Bel B3 Support This field is hardwired to Oh as it does not apply to PCI Express 21 16 RV Oh Reserved 15 RO Oh Reserved 14 1
67. CTL O 1 Addr MMI O BAR VTBAR Offset AOh 10A0h Bit Attr Default Description Interrupt Mask 0 No masking of interrupt When a invalidation event condition is detected hardware issues an interrupt message using the Invalidation Event Data amp 31 RW 1 Invalidation Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is set Interrupt Pending Hardware sets the IP field whenever it detects an interrupt condition Interrupt condition is defined as e An Invalidation Wait Descriptor with Interrupt Flag IF field set completed setting the IWC field in the Fault Status register Ifthe IWC field in the Invalidation Event Status register was already set at the time of setting this field it is not treated as a new interrupt condition 30 RO 0 The IP field is kept set by hardware while the interrupt message is held pending The interrupt message could be held pending due to interrupt mask IM field being set or due to other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either 1 M Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field
68. DMI and the internal devices in the processor Integrated 1 0 and Intel PCH logically constitute PCI Bus 0 to configuration software As a result all devices internal to the processor and the Intel PCH appear to be on PCI Bus O The system primary PCI expansion bus is physically attached to the Intel PCH and from a configuration perspective appears to be a hierarchical PCI bus behind a PCI to PCI bridge and therefore has a programmable PCI Bus number The PCI Express Graphics Attach appears to system software to be a real PCI bus behind a PCI to PCI bridge that is a device resident on PCI Bus 0 Devices residing in the Processor Uncore appear on PCI Bus FFh There is a programmable base bus number that determines the top bus number to start top down processor socket to PCI bus mapping The processors default to 255 as the top bus number However this top bus number can be redefined by the SAD PCIEXBAR CSR Bus FFh Device 0 Function 1 Register offset 50h Processor I ntegrated 1 Devices PCI Bus The processor contains the following PCI devices within a single physical component The configuration registers for the devices are mapped as devices residing on PCI Bus O Device DMI Root Port Logically this appears as a PCI device residing on PCI Bus 0 Device 0 contains the standard PCI header registers extended PCI configuration registers and DMI device specific configuration registers Device 3
69. Detected This bit applies only to the root DMI ports This bit indicates that the root port detected an Unsupported Request Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register 0 No unsupported request detected by the root port 3 RW1C 0 1 Unsupported Request detected at the device port These unsupported requests are NP requests inbound that the root port received and it detected them as unsupported requests for example address decoding failures that the root port detected on a packet receiving inbound lock reads BME bit is clear and so forth Note that this bit is not set on peer to peer completions with UR status that are forwarded by the root port to the PCI Express link Fatal Error Detected This bit indicates that a fatal uncorrectable error is detected by the device 2 RWIC 0 Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register 0 No Fatal errors detected 1 Fatal errors detected Non Fatal Error Detected This bit gets set if a non fatal uncorrectable error is detected by the device Errors are logged in this register regardless of whether error reporting is 1 RW1C 0 enabled or not in the Device Control register 0 No Fatal errors detected 1 Fatal errors detected Correctable Error Detected This bit gets set if a correctable error is detected by the device Errors are logge
70. E 150 3 5 2 15 PROT_LOW_MEM_LIMIT 0 1 Protected Memory Low limit Register a 150 3 5 2 16 PROT HIGH MEM BASE 0 1 Protected Memory High Base Reglster 2 ocius esee era eects Rr ete REPE pea 150 3 5 2 17 PROT HIGH MEM LIMIT 0 1 Protected Memory Limit Base Register 151 3 5 2 18 INV QUEUE HEAD O0 1 Invalidation Queue Header Pointer Register ERR ERE 151 3 5 2 19 INV QUEUE TAIL 0 1 Invalidation Queue Tail Pointer Register c e n LII 151 3 5 2 20 INV QUEUE ADD O0 1 Invalidation Queue Address Register e m Tm TEM 152 3 5 2 21 INV COMP STATUS 0 1 Invalidation Completion Status 152 3 5 2 22 INV_COMP_EVT_CTL 0 1 Invalidation Completion Event Control Register sess mmm 153 3 5 2 23 INV COMP EVT DATA 0 1 Invalidation Completion Event Data kg RR Gad ge PRX XP GR Rd GG VERG 153 3 5 2 24 INV COMP EVT ADDR O0 1 Invalidation Completion Event Address Register 153 3 5 2 25 INV EVT UPRADDR O 1 Invalidation Completion Event Upper Address 154 Datasheet Volume 2 3 5 2 26 INTR_REMAP_TABLE_BASE 0 1 Interrupt Remapping Table Bas
71. FEEFFFFFh read DRAM class TCm over DMI Master Abort Address in Intel ME range in DRAM and any Master Abort class over PCIE Address within 0 TOLM or 4 GB TOHM and Forward to Intel QuickPath SAD hit Interconnect Address within FEE00000h FEEFFFFFh and Forward to Intel QuickPath write Interconnect Interrupts UR Response TPM HPET I OxAPIC CPUCSR when enabled CPULocalCSR privileged CSR INTA Rsvd TSEG Relocated CSeg On die ROM FWH VTBAR1 when enabled Protected VT d range Low and High Generic Protected dram range CB DMA and I OxAPIC BARs e FC00000h FEDFFFFFh or FEF00000h FFFFFFFFh VTBAR VT d Prot High VT d Prot Low Generic Prot DRAM DMA BAR OxAPIC ABAR and MBAR Completer Abort VGA Address within 0A0000h OBFFFFh and main switch SAD is programmed to forward VGA Forward to Intel QuickPath Interconnect Address within 0A0000h OBFFFFh and main switch SAD is NOT programmed to forward VGA and one of the PCle has VGAEN bit set Forward to the PCle port Address within 0A0000h OBFFFFh and main switch SAD is NOT programmed to forward VGA and none of the PCle has VGAEN bit set and DMI port is the subtractive decoding port Forward to DMI Address within 0A0000h OBFFFFh and main Switch SAD is NOT programmed to forward VGA and none of the PCle ports have VGAEN bit set and DMI is not the subtractive decode port Master abort Datasheet Vol
72. High System Memory 4 GB TOHM This region is used to describe the address range of system memory above the 4 GB boundary forwards all inbound accesses to this region to the system memory port unless any of these access addresses are also marked protected A portion of the address range within this high system DRAM region could be marked non coherent using NcMem Base NcMem Limit register and treats them as non coherent All other addresses are treated as coherent unless modified using the NS attributes on PCI Express should not receive outbound accesses to this region but does not explicitly check for this error condition but rather subtractively forwards these accesses to the subtractive decode port if one exists downstream else it is a programming error Software must setup this address range such that any recovered DRAM hole from below the 4 GB boundary and that might encompass a protected sub region is not included in the range Memory Mapped IO High The high memory mapped 1 range is located above main memory This region is used to map 1 0 address requirements above 4 GB range Each in the system is allocated a portion of this system address region and within that portion each PCle port use up a sub range Refer to Section 5 8 3 for details of these restrictions Each IIO has a couple of MMI OH address range registers LMMIOH and GMMI OH to support local and remote peer to peer in the MMI OH addre
73. Integrated 1 110 Configuration Registers m Sheet 2 of 2 Register Device Function Offset LNKSTS 0 DMI 3 5 PCIe 0 A2h Bit Attr Default Description 9 4 RO Oh Negotiated Link Width This field indicates the negotiated width of the given PCI Express link after training is completed Only x8 and x16 link width negotiations are supported in Integrated 1 0 0x08 x8 max link width 0x10 x16 max link width The value in this field is not defined and could show any value when the link is not up Software determines if the link is up or not by reading Bit 13 of this register 3 0 RO 1h Current Link Speed This field indicates the negotiated Link speed of the given PCI Express Link 0001b 2 5 Gbps 0010b 5 Gbps Others Reserved The value in this field is not defined and could show any value when the link is not up Software determines if the link is up or not by reading Bit 13 of this register Datasheet Volume 2 67 intel Processor Integrated 1 Configuration Registers 3 3 4 23 SLTCAP PCI Express Slot Capabilities Register The Slot registers Note Hot plug Capabilities register identifies the PCI Express specific slot capabilities These must be ignored by software on the DMI links for PCle is not supported on Desktop Platforms Register Device Function Offset SLTCAP 0 DMI 3 5 PCIe 0 A
74. Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Intel Intel Core Intel Scalable Memory Interconnect Intel SMI Intel Virtualization Technology for Directed 1 0 Intel Trusted Execution Technology Intel TXT Intel Management Engine Intel ME Intel Interconnect BIST Intel IBIST and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2009 Intel Corporation All Rights Reserved 2 Datasheet Volume 2 Contents 1 Introduction once eI ERR Per Pep Xp i e Pa RE ERR Rhee e 17 11 Register 4 sese e memes 17 2 Configuration Process and Registers 19 2 1 Platform Configuration Structure 1222 19 2 1 1 Processor Integrated I O Devices PCI BUS 0 19 2 1 2 Processor Uncore Devices PCI BUS 20 2 2 Configuration Mechanisms eiie ni rario n a P RH ERR LER E Puede 21 2 2 1 Standard PCI Express Configuration 21 2 2 2 PCI Express Configuration
75. LIMIT field the VTGENCTRL register Similarly for isoch else 26h ntel VT d engine this field is set by the Isoch LIMIT field of the VTGENCTRL register 15 RV Oh Reserved 14 13 RO Oh Reserved Off def SAGAW 12 8 RO 08h 4h supports level walks on the Isochronous Intel VT d engine and 4 level else 2h walks on the non Isochronous Intel VT d engine TCM 7 RO 0 110 does not cache invalid pages 6 RO 1 PHMR Support supports protected high memory range 5 RO 1 PLMR Support supports protected low memory range 4 RO 0 Reserved 3 RO 0 Advanced Fault Logging does not support advanced fault logging Number of Domains Supported a0 RD 0109 supports 256 domains with 8 bit domain ID 142 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 5 2 3 EXT CAP O0 1 Extended Intel VT d Capability Register Register EXT CAP O0 1 Addr MMI O BAR VTBAR Offset 10h 1010h Bit Attr Default Description 63 24 RV 0 Reserved Max Handle Mask Value 23 20 RO Fh supports all 16 bits of handle being masked m Note 110 always performs global interrupt entry invalidation on any interrupt cache invalidation command and h w never really looks at the mask value 19 18 RV 0 Reserved Invalidation Unit Offset 17 8 RO 20h has the invalidation registers at offset 200h 0 offset 0 Hardware d
76. Maximum Maximum tags that be used for VCp legacy Isoc Traffic Value should not be set greater then MaxRequests It is required that Pool Index in QPI O PORB QPI 0 Protocol Outgoing Request Buffer be disabled when I soc 3 0 RW 0 traffic is enabled When Isoc is enabled this value must be set to gt 0 0 7 Maximum TIDs pending on Intel QuickPath Interconnect with critical priority set gt 7 Reserved Recommend setting VCp max 4 CAPHDRH PCI Express Capability Header High Register Capability header capability ID for this extended function Device 16 Function 1 Offset 100h Bit Attr Default Description CAPI DH 31 0 RO 000Bh 000Bh is the Capability ID for vendor specific 8 Datasheet Volume 2 Processor Uncore Configuration Registers L 4 4 1 Processor Uncore Configuration Registers The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI specification as defined in the latest revision of the PCI Local Bus Specification as well as the PCI Express enhanced configuration mechanism as specified in the latest revision of the PCI Express Base Specification All the registers are organized by bus device function and so forth as defined in the PCI Express Base Specification All processor registers appear on the PCI bus assigned for the processor socket Bus number is derived by
77. NOT legacy Master Abort Bus 1 255 and it matches the 5 and device number matches one of internal Forward to that internal device device numbers Bus 1 255 and it matches the II OBUSNO and device number does NOT match any of 1105 Master Abort internal device numbers Bus 1 255 and it does not match the Forward that port IIOBUSNO but positively decodes to one of Configuration requests are forwarded as a Bus 1 255 the downstream PCle ports 0 if bus number matches secondary bus number of port or a Type 1 Bus 1 255 and it does not match the Forward to DMI II OBUSNO and does not positively decode to Forward configuration request as Type 0 1 one of the downstream PCle ports and DMI is depending on secondary bus number register the subtractive decode port of the port Bus 1 255 and it does not match the II OBUSNO and does not positively decode to one of the downstream PCle ports and DMI is Master Abort not the subtractive decode port Notes 1 Note that when forwarding to DMI Type 0 transaction with any device number is required to be forwarded by IIO unlike the standard PCI Express root ports 2 Ifa downstream port is a standard PCI Express root port then PCI Express specification requires that all non zero device numbered TypeO transactions are master aborted by the root port If the downstream port is non legacy DMI then Type 0 transaction with any device number is allowed forwarded 3 Note that
78. O does nothing with this bit Retrain Link A write of 1 to this bit initiates link retraining in the given PCI Express port by directing the LTSSM to the recovery state if the current state is LO LOs or L1 If the current state is anything other than LO LOs L1 then a write to this bit does nothing This bit always returns 0 when read 5 RO 0 If the Target Link Speed field has been set to a non zero value different than the current operating speed then the LTSSM will attempt to negotiate to the target link speed It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register When this is done all modified values that affect link retraining must be applied in the subsequent retraining Link Disable This field controls whether the link associated with the PCI Express port is enabled or disabled When this bit is a 1 a previously configured link a link 4 RO 0 that has gone past the polling state would return to the disabled state as defined in the PCI Express Base Specification When this bit is clear an LTSSM in the disabled state goes back to the detect state 0 Enables the link associated with the PCI Express port 1 Disables the link associated with the PCI Express port Read Completion Boundary 3 RO 0 Set to zero to indicate Integrated 1 0 could return read completions at 64B boundaries 2 RV 0 Reserved 1 0 RO 00 Active State Link PM Control i When 01b or 11b
79. Offset F8h Bit Attr Default Description 31 RV 0 Reserved 30 28 RV Oh Reserved 27 RV 0 Reserved VNO NCB credits 26 24 DEMOS Den Allowed values 0 7 credits 23 RV 0 Reserved 1 2h VNO NCS credits 22 205 Allowed values 0 7 credits 19 RV 0 Reserved VNO NDR credits With Isoc enabled this value is expected to be set at 3 to ensure QoS with 18 16 RWDS 1 2h processor Allowed values 0 7 credits 15 RV 0 Reserved VNO DRS credits 14 12 RWDS 1 2h With Isoc enabled this value is expected to be set at 4 to ensure QoS with processor Allowed values 0 7 credits 11 RV 0 Reserved 10 8 RWDS 0 2h VNO Snp credits Allowed values 0 7 credits Snp credits are only needed for debug mode only This should set to 0 for normal operation It can be changed to 1 for debug mode 7 RV 0 Reserved VNA credits Default is set to 102 66h which allows for 1 VNO credit per message class to be assigned with standard headers 0 127 credits 0 RWDS Additional modifiers on VNA credits If VNO Snp Credits is set to 1 this must be set to one less credit If VNO DRS credits are set to the recommended isoc value 4 this should be set to 33 less credits Datasheet Volume 2 179 Processor Integrated 1 Configuration Registers 3 7 2 I ntel QuickPath I nterconnect Routing amp Protocol Layer Registers Table 3 21 CSR Intel QuickPath I nterconnect Routing Layer Protocol Device 16 Function 1
80. Processor Integrated 1 Configuration Registers 3 7 1 4 QPI O LCL I ntel QuickPath I nterconnect Link Control Register per Intel QuickPath Interconnect port This register is used for Control of Link Layer Register Device 16 Function 0 Offset C4h Bit Attr Default Description 31 21 RO 0 Reserved L1 enable Bit is ANDed with the parameter exchanged value for L1 to determine if the 20 RWDS 0 link may enter 11 0 Disable 1 Enable 19 0 RO 0 Reserved 178 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 7 1 5 QPI O0 LCRDC I ntel QuickPath I nterconnect Link Credit Control Registers controls what credits are defined for each message class on VNO and VNA These credits are made visible on Intel QuickPath Interconnect during the initialization phase of the link layer Incorrect programming can result in overflow of the receive queue When returning credits on Intel QuickPath Interconnect this register is used in conjunction with the Intel QuickPath Interconnect standard register QPI O LCL I ntel QuickPath Interconnect Link Control to determine how many credits are returned This value is captured and used by the Link Layer when exiting the parameter exchange This state is referred to as Begin Normal Operation Register QPI O LCRDC Device 16 Function O
81. Represents the guest virtual addressing limit for the Isoch Intel VT d engine 000 011 Reserved 100 2736 that is Bits 35 0 101 2737 110 2738 10 8 RWL 111b 111 2739 When Intel VT d translation is enabled on the isoch Intel VT d engine all incoming guest addresses from isochronous device that go beyond the limit specified in this register will be aborted by the IIO and a UR response returned This register is not used when translation is not enabled Note that translated and pass through addresses are in the host addressing domain and NOT guest addressing domain and hence GPA_LIMIT checking on those accesses are bypassed and instead HPA_LIMIT checking applies This field may be locked as RO in Intel TXT mode Isoch Non Isoch LIMIT Represents the host processor addressing limit 0000 2 36 that is Bits 35 0 0001 2 37 that is Bits 36 0 7 4 RWL Oh 1111 2 51 that is Bits 50 0 When Intel VT d translation is enabled on an Intel VT d engine isoch or non isoch all host addresses during page walks that go beyond the limit specified in this register will be aborted by Note that pass through accesses carry the host address directly in the access and are subject to this check as well This field may be locked as RO in Intel TXT mode Non Isoch GPA LIMIT Represents the guest virtual addressing limit for the non Isoch Intel VT d engine 0000 2 40 that is Bits 39 0 0001 2 41 that is Bits 40
82. Rules This is a read write register This register is available for read or write in the Public and Private Intel TXT configuration space Base TXT_TXT Offset 0328h Base TXT PR Offset 0328h Base TXT PB Offset 0328h Bit Attr Default Description 63 0 RW Oh TXT SCRATCHPAD1 63 0 Datasheet Volume 2 173 m t D Processor Integrated 1 Configuration Registers 3 6 1 21 3 6 1 22 3 6 1 23 Note 174 TXT CMD OPEN LOCALI TY1 I ntel TXT Open Locality 1 Command Enables Locality 1 decoding in chipset General Behavioral Rules This is a write only register This register is only available in the private Intel TXT configuration space Accesses to this register are done with 1 byte writes The data bits associated with this command are undefined and have no specific meaning Base TXT TXT Offset 0380h Bit Attr Default Description 7 0 TXT CMD CLOSE LOCALI TY1 I ntel TXT Close Locality 1 Command Disables Locality 1 decoding in chipset General Behavioral Rules This is a write only register This register is only available in the private Intel TXT configuration space Accesses to this register are done with 1 byte writes The data bits associated with this command are undefined and have no specific meaning Base TXT TXT Offset 0388h Base TXT PR Offset 0388h Bit Attr Default Description
83. Volume 2 Processor Integrated 1 110 Configuration Registers 3 4 4 12 LMMI OL LI MI T Local MMI OL Limit Register LMMIOL LI MIT Device 8 Function 0 Offset 10Eh Bit Attr Default Description Local MMI OL Limit Address This field corresponds to A 31 24 of MMIOL limit An inbound or outbound memory address that satisfies local MMIOL base 15 8 x A 31 24 lt local 15 8 RW 00h MMI OL limit 15 8 is treated as a local peer to peer transaction that does not cross Intel QuickPath Interconnect link Setting LMMIOL BASE greater than LMMIOL LIMIT disables local MMIOL peer to peer This register is programmed once at boot time and does not change after that 7 0 RO Oh Reserved 3 4 4 13 LMMI OH BASE Local MMI OH Base Register LMMI OH BASE Device 8 Function O Offset 110h Bit Attr Default Description Local MMI OH Base Address This field corresponds to A 31 26 of MMIOH base An inbound or outbound memory address that satisfies local MMIOH base upper 31 0 local MMIOH base 15 10 x A 63 26 x local MMI OH limit upper 31 0 local MMIOH 15 10 RW 00h limit 15 10 is treated as a local peer to peer transaction that does not cross an Intel QuickPath Interconnect link Setting LMMIOH BASEU LMMI OH BASE greater than LMMI OH LI MI TU LMMI OH LI MIT disables local MMIOH peer to peer This register is programmed once at boot time and does not change after t
84. allocated to the hierarchy below the Intel QuickPath Interconnect link An inbound or outbound configuration tx falls within the local bus number range if Local Bus 7 0 RW 00h Number Base 7 0 x Bus Number 7 0 x Local Bus Number Limit 7 0 and such transactions are treated as local peer to peer transactions that do not cross an Intel QuickPath Interconnect link Setting LCFGBUS BASE greater than LCFGBUS LIMIT disables local peer to peer configuration cycles This register is programmed once at boot time and does not change after that Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 4 4 18 LCFGBUS LI MI T Local Configuration Bus Number Limit Register Register LCFGBUS LI MIT Device 8 Function 0 Offset 11Dh Bit Attr Default Description Local Configuration Bus Number Limit This field corresponds to Limit bus number of bus number range allocated to the hierarchy below the Intel QuickPath Interconnect link An inbound or outbound configuration falls within the local bus number range if Local Bus Number Base 7 0 x Bus Number 7 0 x Local Bus Number Limit 7 0 and 7 0 RW 00h such transactions are treated as local peer to peer transactions that do not cross an Intel QuickPath Interconnect link Setting LCFGBUS BASE greater than LCFGBUS LIMIT disables local peer to peer configuration cycles This register is programmed once at boot time and does
85. associated with and including this port 1 Indicates that a internal core error logic notification should be generated if a non fatal error is reported by any of the devices in the hierarchy associated with and including this port Note that generation of system notification on a PCI Express DMI non fatal error is orthogonal to generation of an MSI interrupt for the same error Both a system error and MSI can be generated on a non fatal error or software can choose one of the two Refer to the latest PCI Express Base Specification for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express DMI port 70 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers m Sheet 2 of 2 Function O Offset ACh Register ROOTCON Device 0 DMI 3 5 PCIe Bit Attr Default Description Oh System Error on Correctable Error Enable This field controls notifying the internal core error logic of the occurrence of a correctable error in the device or below its hierarchy The internal core error logic of Integrated 1 0 then decides if how to escalate the error further pins message and so forth 0 No internal core error logic notification should be generated on a correctable error reported by any of the devices in the hierarchy associated with and including this port 1 Indicat
86. been 0 ROS 0 received Note that this bit is sticky and is only cleared by a power cycle The effect of TXT POI SON is also held active through reset and so the chipset is poisoned even after the reset The only way to clear the poison effect is to do a power cycle 164 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 6 1 3 TXT THREADS EXI 575 1 ntel TXT Thread Exists Register This register is used to read which threads are registered as Intel TXT capable General Behavioral Rules This is a read only register so writes to this register will be ignored This register is available in both the Public and Private Intel TXT configuration spaces Base TXT Offset 0010h Base TXT PR Offset 0010h Base TXT PB Offset 0010h Bit Attr Default Description TXT THREADS EXI STS 63 0 This bit field indicates the threads that exit in the platform Each thread sets its bit in this register by writing a 1 to the corresponding TXT EXISTS SET 63 0 RO Oh register How each thread determines which bit to write is platform dependent These bits can be cleared by writing a 1 to the corresponding bit in the TXT EXISTS CLEAR register 3 6 1 4 TXT THREADS J OI N Intel TXT Threads J oin Register This register is used to count the threads that have joined the Intel TXT environment General Behavioral Rules This is a read only register so writes to th
87. currently disabled BIOS Requirement 1 enable a Virtual Channel the VC Enable bits for that Virtual Channel must be set in both Components on a Link 2 disable a Virtual Channel the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link 3 Software must ensure that no traffic is using a Virtual Channel at the time it is disabled 4 Software must fully disable a Virtual Channel in both Components on a Link before re enabling the Virtual Channel 30 27 RO Oh Reserved 26 24 RW 001b Virtual Channel 1 I D VC1ID Assigns a VC ID to the VC resource Assigned value must be non zero This field can not be modified when the VC is already enabled 23 20 RO Oh Reserved 19 17 RW Oh Port Arbitration Select PAS Configures the VC resource to provide a particular Port Arbitration service Valid value for this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource 16 8 RO Oh Reserved Traffic Class Virtual Channel 1 Map TCVC1M Indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values 7 1 RW 00h For example when Bit 7 is set in this field TC7 is mapped to this VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource In order to remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no
88. defines the number of rows within these DIMMs 000 2712 Rows 001 2713 Rows 010 2714 Rows 011 2715 Rows 100 2716 Rows 1 0 RW NUMCOL Number of Columns This field defines the number of columns within on these DIMMs 00 2710 columns 01 2711 columns 10 2712 columns 11 RSVD Datasheet Volume 2 261 Processor Uncore Configuration Registers intel 4 11 2 MC 1 0 MC DOD 1 1 Channel 1 DIMM Organization Descriptor Register Device 5 Function 1 Offset 48h 4Ch 50h 54h Access as a DWord Bit Attr Default Description 31 13 RO 0 Reserved RANKOFFSET Rank Offset for calculating RANK This corresponds to the first logical rank on 12 10 RW 0 the DIMM The rank offset is always programmed to 0 for the DIMM 0 DOD registers DIMM 0 rank offset is always 0 DIMM 1 DOD rank offset is 4 for two DIMMs per channel 9 RW 0 DI MMPRESENT DIMM slot is populated NUMBANK This field defines the number of real not shadow banks on these DI MMs 8 7 RW 0 00 Four banked 01 Eight banked 10 Sixteen banked NUMRANK Number of Ranks This field defines the number of ranks on these DIMMs 6 5 RW 0 00 Single Ranked 01 Double Ranked 10 Reserved NUMROW Number of Rows This field defines the number of rows within these DIMMs 000 2712 Rows 4 2 RW 0 001 2713 Rows 010 2714 Rows 011 2715 Rows 100 2716 Rows NUMCOL Number
89. forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 3 0 RO 0 Reserved 210 Datasheet Volume 2 Processor Uncore Configuration Registers 4 5 2 SAD_PAM456 Register for legacy device 0 function 0 94h 97h address space Device 0 Function 1 Offset 44h Access as a DWord Bit Attr Default Description 31 22 RO 0 Reserved 21 20 RW PAM6_HI ENABLE OECOOOh OEFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OECOOOh to OEFFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 17 16 RW PAM6_LOENABLE OE8000h OEBFFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from OE8000h to OEBFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 15 14 RO Reserved
90. have no effect 10 9 RO 0 This device does not physically connect to PCI bus X These bits are set to 00 fast decode so that optimum DEVSEL timing for PCI bus X is not limited by this device Master Data Parity Error Detected DPD 8 RO 0 PERR signaling and messaging are not implemented by this bridge therefore this bit is hardwired to 0 Writes to this bit position have no effect Fast Back to Back FB2B This bit is hardwired to 1 Writes to this bit position have no effect This device 7 RO 1 is not physically connected to a PCI bus This bit is set to 1 indicating back to back capabilities so that the optimum setting for this PCI bus is not limited by this device 6 RO 0 Reserved Datasheet Volume 2 Processor Uncore Configuration Registers Device 0 Function 0 1 Offset 06h Device 2 Function 0 1 Offset 06h Device 3 Function 0 1 4 Offset 06h Device 4 Function 0 3 Offset 06h Bit Attr Default Description 5 RO 0 66 MHz Capable Does not apply to PCI Express Must be hardwired to 0 Capability List CLI ST This bit is hardwired to 1 to indicate to the configuration software that this device function implements a list of new capabilities A list of new capabilities is accessed using registers CAPPTR at the configuration address offset 34h 4 RO 1 from the start of the PCI configuration space header of this function Register CAPPTR contains the offset pointing to the start ad
91. indicate overflow of fault recording registers Datasheet Volume 2 147 intel 3 5 2 9 Processor Integrated 1 Configuration Registers FLTEVTCTRL O 1 Fault Event Control Register Register FLTEVTCTRL O0 1 Addr MMI O BAR VTBAR Offset 38h 1038h Bit Attr Default Description Interrupt Message Mask I 0 Software has cleared this bit to indicate interrupt service is available When 31 RW 1 a faulting condition is detected hardware may issue a interrupt request using the fault event data and fault event address register values depending on the state of the interrupt mask and interrupt pending bits 1 Hardware is prohibited from issuing interrupt message requests Interrupt Pending Hardware sets the field whenever it detects an interrupt condition Interrupt condition is defined as when an interrupt condition occurs when hardware records a fault through one of the Fault Recording registers and sets the PPF field in Fault Status register e Hardware detected error associated with the I nvalidation Queue setting the IQE field in the Fault Status register Hardware detected invalidation completion time out error setting the ITE field in the Fault Status register e If any of the above status fields the Fault Status register was already set at the time of setting any of these fields it is not treated as a new interrupt condition 30 RO 0 The IP field is kept
92. is used in conjunction with other bits to report errors For the PCI Express DMI ports this bit is not used to control the reporting of other internal component uncorrectable non fatal errors at the port unit in any way RW Correctable Error Reporting Enable Applies only to the PCI Express DMI ports Controls the reporting of correctable errors that Integrated I O detects the PCI Express DMI interface 0 Reporting of link Correctable error detected by the port is disabled 1 Reporting of link Correctable error detected by port is enabled Refer to the latest PCI Express Base Specification for complete details of how this bit is used in conjunction with other bits to report errors For the PCI Express DMI ports this bit is not used to control the reporting of other internal component correctable errors at the port unit in any way Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 3 4 18 DEVSTS PCI Express Device Status Register The PCI Express Device Status register provides information about PCI Express device specific parameters associated with the device Register DEVSTS Device 0 DMI 3 5 PCI e Function O Offset 9Ah Bit Attr Default Description 15 6 RV 000h Reserved Transactions Pending 5 RO Oh Does not apply to root DMI ports that is bit hardwired to 0 for these devices 4 RO 0 Reserved Unsupported Request
93. memory reads with NS 1 will not be snooped on Intel QuickPath Interconnect Notes 1 This bit should be set to the same value as Bit 3 Enable No Snoop Optimization on writes of this register 2 This must be set for DMI port to support Isoch traffic For PCI Express ports the NS optimization must not be used and this bit should be zero RO Reserved RO Reserved Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 3 5 4 SCCTRLSTS Miscellaneous Control and Status Register Sheet 1 of 3 Register Device Function Offset MI SCCTRLSTS 0 DMI 3 5 PCIe 0 188h Bit Attr Default Description 63 50 RO 0 Reserved 49 RW1CS 0 Reserved 48 Received PME_TO_ACK RWI1C 0 Indicates that Integrated 1 0 received a PME turn off ACK packet or it timed out waiting for the packet 47 38 RO 0 Reserved 37 RV 0 Reserved 36 Form Factor Indicates what form factor a particular root port controls 0 CEM Cable RWS 0 1 5 This bit is used to interpret bit 6 the VPP serial stream for the port as either MRL CEM Cable input or EMLSTS SIOM input 35 Override System Error on PCI Express Fatal Error Enable When set fatal errors on PCI Express that have been successfully propagated to the primary interface of the port are sent to the Integrated RW 0 1 O core error logic for further esca
94. new or outstanding transactions with the TC labels are targeted at the given Link 0 RO 0 Traffic Class 0 Virtual Channel 0 Map TCOVC1M Traffic Class 0 is always routed to VCO Datasheet Volume 2 89 intel 3 3 6 10 Processor Integrated 1 Configuration Registers DMI VC1LRSTS DMI VC1 Resource Status Reports the Virtual Channel specific status BAR DMI RCBAR Register DMIVCIRSTS Offset 0026h Bit Attr Default Description 15 2 RO Oh Reserved Reserved and Zero for future R WC S implementations Software must use 0 for writes to these bits Virtual Channel 1 Negotiation Pending VC1NP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control initialization It is I RO 1 set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state BIOS Requirement Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO 0 Reserved 3 3 6 11 90 DMI LCAP DMI Link Capabilities Indicates DMI specific capabilities BAR DMI RCBAR Register DMILCAP Offset 0084h Bit Attr Default Desc
95. not change after that 3 4 4 19 GMMI OL BASE Global MMI OL Base Register GMMIOL BASE Device 8 Function 0 Offset 124h Bit Attr Default Description Global MMI OL Base Address This field corresponds to A 31 24 of global MMIOL base An inbound or outbound memory address that satisfies global MMIOL base 15 8 lt A 31 24 lt global MMIOL limit 15 8 but is outside of the local MMIOL range is treated 15 8 RW 00h as a remote peer memory transaction over Intel QuickPath I nterconnect Setting GMMIOL BASE greater than GMMIOL LIMIT disables global MMIOL peer to peer This register is programmed once at boot time and does not change after that 7 0 RO 00h Reserved 3 4 4 20 GMMI OL LI MI T Global MMI OL Limit Register GMMIOL LIMIT Device 8 Function O Offset 126h Bit Attr Default Description Global MMI OL Limit Address This field corresponds to A 31 24 of global MMIOL limit An inbound or outbound memory address that satisfies global MMIOL base 15 8 lt A 31 24 15 8 RW 00h lt global MMIOL limit 15 8 but is outside of the local MMIOL range is treated t as a remote peer to peer transaction over Intel QuickPath Interconnect link Setting GMMIOL BASE greater than GMMIOL LIMIT disables global MMIOL peer to peer This register is programmed once at boot time and does not change after that 7 0 RO 00h Reserved Datasheet Volume 2 121 intel 3 4 4
96. number of the processor The SRID is a 4 bit hardwired value assigned by Intel based on product s stepping The SRID is not a directly addressable PCI register The SRID value is reflected through the RID register when appropriately addressed The 4 bits of the SRID are reflected as the two least significant bits of the major and minor revision field respectively See Table 4 1 Compatible Revision I D CRI D The CRID is an 4 bit hardwired value assigned by Intel during manufacturing process Normally the value assigned as the CRID will be identical to the SRID value of a previous stepping of the product with which the new product is deemed compatible The CRID is not a directly addressable PCI register The CRID value is reflected through the RID register when appropriately addressed The 4 bits of the CRID are reflected as the two least significant bits of the major and minor revision field respectively See Table 4 1 Datasheet Volume 2 203 intel 4 4 4 204 Processor Uncore Configuration Registers CCR Class Code Register This register contains the Class Code for the device Writes to this register have no effect Device 0 Function 0 1 Offset OEh Device 2 Function 0 1 Offset OEh Device 3 Function 0 1 4 Offset OEh Device 4 5 Function 0 3 Offset OEh Bit Attr Default Description Base Class 23 16 RO 06h This field indicates the general device category For the processor this field
97. of Columns This field defines the number of columns within on these DIMMs 00 2710 columns 1 0 RW 0 01 2711 columns 10 2712 columns 11 RSVD 262 Datasheet Volume 2 Processor Uncore Configuration Registers L 4 11 3 5 0 5 1 5 2 SAG CHO 3 5 CHO 4 5 5 6 5 7 Channel Segment Address Registers For each of the 8 interleave ranges they specify the offset between the System Address and the Memory Address and the System Address bits used for level 1 interleave which should not be translated to Memory Address bits Memory Address is calculated from System Address and the contents of these registers by the following algorithm m 39 16 SystemAddress 39 16 25 complement Offset 23 0 m 15 6 SystemAddress 15 6 If Removed 2 Bit 8 removed If Removed 1 Bit 7 removed If Removed 0 Bit 6 removed MemoryAddress 36 6 m 36 6 Removed Div3 Interleave 000 0 None 001 0 2 way 011 0 4 way 000 1 3 way 001 1 6 way All other combinations are not supported Device 4 Function 1 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch Access as a DWord Bit Attr Default Description 31 28 RO 0 Reserved DI VBY3 e RW 9 This bit indicates the rule is 3 6 way interleave REMOVED 26 24 RW 0 These are the bits to be removed after offset subtracti
98. on forwarding of NoSnoop attribute on peer requests 10 RO 0 Reserved 9 RO 0 Reserved Extended Tag Field Enable 8 RO Oh This bit enables the PCI Express port DMI to use an 8 bit Tag field as a requester Max Payload Size This field is set by configuration software for the maximum TLP payload size for the PCI Express port As a receiver the Integrated 1 0 must handle TLPs as large as the set value As a requester that is for requests where Integrated I O s own RequesterlD is used it must not generate TLPs exceeding the set value Permissible values that can be programmed are 7 5 RO 000 indicated by the Max Payload Size Supported in the Device Capabilities register 000 128B max payload size 001 256B max payload size applies only to standard PCI Express ports and other devices alias to 128B others alias to 128B Enable Relaxed Ordering Not applicable to root ports since they never set relaxed ordering bit as a 4 RO 0 requester this does not include Tx forwarded from peer devices This bit has no impact on forwarding of relaxed ordering attribute on peer requests Unsupported Request Reporting Enable This bit applies only to the PCI Express DMI ports This bit controls the reporting of unsupported requests that Integrated I O itself detects on 3 RO 0 requests its receives from a PCI Express DMI port 0 Reporting of unsupported requests is disabled 1 Reporting of unsupported requests is enabled Refer to the latest PCI Express Ba
99. set by hardware while the interrupt message is held pending The interrupt message could be held pending due to interrupt mask IM field being set or due to other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either 1 M Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM Interrupt Mask field in Section 3 5 2 22 2 Software servicing all the pending interrupt status fields in the Fault Status register PPF field is cleared by hardware when it detects all the Fault Recording registers have Fault F field clear Other status fields in the Fault Status register is cleared by software writing back the value read from the respective fields 29 0 RO 0 Reserved 148 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 5 2 10 FLTEVTDATA 0 1 Fault Event Data Register Register FLTEVTDATA O0 1 Addr MMIO BAR VTBAR Offset 3Ch 103Ch Bit Attr Default Description 31 16 RO 0 Reserved 15 0 RW 0 Interrupt Data 3 5 2 11 FLTEVTADDR 0 1 Fault Event Address Register Register FLTEVTADDR O 1 Addr MMIO BAR VTBAR Offset 40h 1040h Bit Attr Default Description Interrup
100. set the VCp and VC1 Isoc flows are enabled on Intel QuickPath Interconnect It is required when this is enabled that the VC1 Maximum and the VCp Maximum values be non zero VC1 Reserved Number of TIDs that are reserved for VC1 Azalia Traffic The value must be less then MaxRequest minus the Reserved for High priority Should be set no 15 12 RW 0 greater than the VC1 Maximum value 0 7 Invalid values gt 7 Reserved Recommend setting VC1 3 Datasheet Volume 2 181 3 7 2 3 182 Processor Integrated 1 Configuration Registers Register QPI PI SOCRES Device 16 Function 1 Offset B8h Bit Attr Default Description VC1 Maximum Maximum tags that can be used for VC1 Azalia Traffic Value should not be set greater then MaxRequests It is required that Pool Index in QPI 0 PORB QPI 0 Protocol Outgoing Request Buffer be disabled when Isoc traffic is enabled 11 8 RW 0 When Isoc is enabled this value must be set to gt 0 0 7 Maximum TIDs pending on Intel QuickPath Interconnect with critical priority set gt 7 Reserved Recommend setting VC1 max 4 VCp Reserved Number of TIDs that are reserved for VCp legacy 15 Traffic The value must be less then MaxRequest minus the Reserved for Critical priority Should be 7 4 RW 0 set greater than the VCp Maximum value 0 7 Invalid values gt 7 reserved Recommend setting VCp 2 VCp
101. setting PLAT Primary Latency Timer Register PLAT Device 0 DMI 3 5 PCle Function 0 Offset ODh Bit Attr Default Description 7 0 RO 00h Prim_ Lat timer Primary Latency umer Not applicable to PCI Express Hardwired to 00h The above register denotes the maximum time slice for a burst transaction in legacy PCI 2 3 on the primary interface It does not affect influence PCI Express functionality HDR Header Type Register This register identifies the header layout of the configuration space Register HDR Device 0 DMI Function 0 Offset OEh Bit Attr Default Description 7 RO 0 Multi Function Device This bit defaults to 0 for Express DMI ports Configuration Layout 6 0 RO 00h This field identifies the format of the configuration header layout For Device 0 DMI default is 00h indicating a conventional type 00h PCI header Register HDR Device 3 5 PCle Function 0 Offset OEh Bit Attr Default Description 7 RO 0 Multi Function Device This bit defaults to 0 for PCI Express DMI ports Configuration Layout 6 0 RO Olh This field identifies the format of the configuration header layout It is Type 1 for all Express ports The default is O1h indicating a PCI to PCI bridge Datasheet Volume 2 41 intel 3 3 3 10 3 3 3 11 3 3 3 12 3 3 3 13 42 Processor Integrated 1
102. status bits in the slot status register or root port status registers set assigns the first vector for PM HP events and so this field is set to 0 Slot Implemented Applies only to the root ports 0 Indicates no slot is connected to this port 8 RWO 0 1 Indicates that the PCI Express link associated with the port is connected to a slot This register bit is of type write once and is controlled by BIOS special initialization firmware Device Port Type 7 4 RO 0100 This field identifies the type of device It is set to 0100 for all the Express ports Dev 3 5 2h Capability version ay 3 0 RWO Dev 3 5 2h This field identifies the version of the PCI Express capability structure Set to Dev 0 Lh 2h for PCI Express devices for compliance with the extended base registers i Note BIOS should set this to 1h for Device 0 DMI Datasheet Volume 2 57 Processor Integrated 1 Configuration Registers intel 3 3 4 16 DEVCAP PCI Express Device Capabilities Register The PCI Express Device Capabilities register identifies device specific information for the device Register DEVCAP Device 0 DMI 3 5 PCle Function 0 Offset 94h Bit Attr Default Description 31 28 RV Oh Reserved 27 26 RO Oh Captured Slot Power Limit Scale Does not apply to root ports or integrated devices 25 18 RO 00h Captured Slot Power Limit Value Does not apply to root ports or integrated devic
103. support local and remote peer to peer in the IO address range debug mode only Refer to section Section 5 8 1 and Section 5 8 2 for details of how these registers are used in the inbound and outbound IO address decoding Configuration CSR Space There are two types of configuration CSR space in PCle configuration space and Intel QuickPath Interconnect CPUCSR space PCle configuration space is the standard PCle configuration space defined in the PCle specification CSR space is memory mapped space used exclusively for special processor registers PCI e Configuration Space PCle configuration space allows for upto 256 buses 32 devices per bus and 8 functions per device There could be multiple groups of these configuration spaces and each is called a segment can support multiple segments a system But each span one segment and no peer to peer accesses are allowed between segments Within each IIO there are multiple devices that are in the PCle configuration space All these devices are accessed using NcCfgWr Rd transactions on Intel QuickPath Interconnect Within each segment bus 0 is always assigned to the internal bus number of IIO which has the legacy PCH attached to it Refer to Section 5 8 1 and Section 5 8 2 for details of configuration transaction decoding Each is allocated a chunk of PCle bus numbers and there are ll O specific requirements on how these chunks are distributed amongst 1105 to sup
104. the internal 110 core error logic 8 RW 0 0 Fatal Non fatal error generation Fatal and Non fatal error message forwarding is disabled 1 Fatal and Non fatal error generation and Fatal and Non fatal error message forwarding is enabled Refer to the latest PCI Express Base Specification for details of how this bit is used in conjunction with other control bits in the Root Control register for forwarding errors detected on the PCI Express interface to the system core error logic IDSEL Stepping Wait Cycle Control 7 RO 0 Not applicable to Processor Integrated 1 devices Hardwired to 0 Parity Error Response 6 RW 0 For PCI 55 ports Processor Integrated 1 0 ignores this bit and always does ECC parity checking and signaling for data address of transactions both to and from Integrated 1 0 VGA Palette Snoop Enable 5 RO 0 Not applicable to Processor Integrated 1 devices Hardwired to 0 Memory Write and I nvalidate Enable 4 RO 0 Not applicable to Processor Integrated 1 devices Hardwired to 0 3 RO 0 Special Cycle Enable Not applicable to PCI Express Hardwired to 0 Bus Master Enable BME This bit controls the ability of the PCI Express port in generating forwarding memory including MSI writes or I O transactions and not messages or configuration transactions from the secondary side to the primary side 0 The Bus Master is disabled When this bit is 0 Integrated I O root 2 RW 0 ports will treat upstre
105. the max bus range setting and processor socket number All multi byte numeric fields use little endian ordering that is lower addresses contain the least significant parts of the field Processor Uncore Configuration Structure PCI Bus FFh The processor Uncore contains the following PCI devices within a single physical component The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket Bus number is derived by the max bus range setting and processor socket number Device 0 Generic processor non core Device 0 Function 0 contains the generic non core configuration registers for the processor and resides at DID Device ID of 2C50 7h Device 0 Function 1 contains the System Address Decode registers and resides at DID of 2C81h Device 2 Intel QuickPath Interconnect Device 2 Function 0 contains the Intel QuickPath Interconnect configuration registers for Intel QuickPath Interconnect Link 0 and resides at DID of 2C90h Device 2 Function 1 contains the frequency control layer registers for Intel QuickPath Interconnect Link 0 and resides at DID of 2C91h Device 3 Integrated Memory Controller Device 3 Function 0 contains the general registers for the Integrated Memory Controller and resides at DID of 2C98h Device 3 Function 1 contains the Target Address Decode registers for the Integrated Memory Controller and resides at DID of 2C99h Device
106. the worst case of 2X refresh must be assumed When there are more than 4 ranks attached to the channel the thermal throttle logic is shared Device 4 5 Function 3 Offset 80h Access as a DWord Bit Attr Default Description 31 24 RW 255 RANK3 Rank 3 Cooling Coefficient 23 16 RW 255 RANK2 Rank 2 Cooling Coefficient 15 8 RW 255 RANK1 Rank 1 Cooling Coefficient 7 0 RW 255 RANKO Rank 0 Cooling Coefficient Datasheet Volume 2 Processor Uncore Configuration Registers 4 13 7 4 13 8 Datasheet Volume 2 intel MC_CLOSED_LOOPO MC_CLOSED_LOOP1 This register controls the closed loop thermal response of the DRAM thermal throttle logic It supports immediate thermal throttle and 2X refresh In addition the register is used to configure the throttling duty cycle Device 4 5 Function 3 Offset 84h Access as a DWord Bit Attr Default Description 31 18 RO 0 Reserved MIN THROTTLE DUTY CYC This parameter represents the minimum number of DCLKs of operation 17 8 RW 64 allowed after throttling order to provide actual command opportunities the number of clocks between CKE deassertion and first command should be considered 7 5 RO 0 Reserved REF 2X NOW Direct control of dynamic 2X refresh if direct throttling is enabled THROTTLE NOW 3 0 RW 0 Throttler Vector to directly control throttling if MC THERMAL CONTROL THROTTLE MODE 2
107. to CWR n writes SR n if SR n 0 0 before the 31 0 RW Oh 4 write and has effect otherwise The registers provide firmware with synchronization variables semaphores that are overloaded onto the same physical registers as SR 3 4 5 13 I R O 3 I ncrement Registers 0 3 Register IR 0 3 Device Function 1 Offset 140h 14Ch by4 Bit Attr Default Description Increment These registers are physically mapped to scratch pad registers A read from IR n reads SR n and then increments SR n A write to IR n increments SR n while 31 0 RWSLB Oh the write data is unused Increments within SR n for reads and writes roll over to zero The read or write and the increment side effect are atomic with respect to other accesses The registers provide firmware with synchronization variables semaphores that are overloaded onto the same physical registers as SR Datasheet Volume 2 131 intel Processor Integrated 1 Configuration Registers 3 4 5 14 IR 4 7 I ncrement Registers 4 7 Register IR 4 7 Device 8 Function 1 Offset 150h 15Ch by 4 Bit Attr Default Description Increment These registers are physically mapped to scratch pad registers A read from IR n reads SR n and then increments SR n A write to IR n increments SR n while 31 0 RWSLB Oh the write data is unused Increments within SR
108. to conform to the DDR3 specification MC CHANNEL 0 RCOMP PARAMS MC CHANNEL 1 RCOMP PARAMS This register contains parameters that specify Rcomp timings Device 4 5 Function O Offset 98h Access as a DWord Bit Attr Default Description 31 17 RO 0 Reserved RCOMP EN Enable Rcomp 16 RW 0 When set the Integrated Memory Controller will do the programmed blocking of requests and send indications RCOMP CMD DCLK Delay from the start of RCOMP command blocking period which the 15 10 RW 2 ip command rcomp update is done Program this field to 15 for all configurations RCOMP LENGTH 9 4 RW 9 Number of Dclks during which all commands are blocked for an RCOMP update Data RCOMP update is done on the last DCLK of this period Program this field to 31 for all configurations RCOMP INTERVAL 3 0 RW 0 Duration of interval between Rcomp in increments of tRefl Register value is tRefl 1 For example a setting of 0 will produce an interval of tRefl Datasheet Volume 2 Processor Uncore Configuration Registers intel 4 10 17 MC_CHANNEL_0_ODT_PARAMS1 MC_CHANNEL_1_ODT_PARAMS1 This register contains parameters that specify ODT timings All values are in DCLK Device 4 5 Function 0 Offset 9Ch Access as a DWord Bit Attr Default Description 31 27 RO 0 Reserved TAOFD doe RW 0 ODT turn off delay MCODT DURATION 25504 RW Co
109. when a device experiences a completor abort condition on a transaction it mastered on the primary interface Integrated 1 0 internal bus Note that certain errors might be detected right at the PCI Express interface and those transactions might not propagate to the primary interface before the error is detected for example accesses to memory above VTCSRBASE Such errors do not cause this bit to be set and are reported using the PCI Express interface error bits secondary status register Conditions that cause Bit 12 to be set include Device receives a completion on the primary interface internal bus of Integrated 1 with completor abort completion Status This includes CA status received on the primary side of a PCI Express port on peer to peer completions also Accesses to Intel QuickPath Interconnect that return a failed completion status e Other completer abort conditions detected on the Integrated 1 O internal bus 11 RW1C Signaled Target Abort This bit is set when a device signals a completer abort completion status on the primary side internal bus of Integrated 1 0 This condition includes a PCI Express port forwarding a completer abort status received on a completion from the secondary side and passed to the primary side on a peer to peer completion 10 9 RO Oh DEVSEL Timing Not applicable to PCI Express Hardwired to 0 RW1C Master Data Parity Error This bit is set by a device if th
110. will subtractively decode to the PCH and consequently be forwarded over the DMI using a PCI Express configuration TLP In Figure 2 2 the subtractive decode is completed by testing Devices 0 through n where Devices 0 through n if enabled and Function 0 is present in the processor are claimed by the processor If the Bus Number is zero the processor will generate a Type 0 Configuration Cycle TLP on DMI If the Bus Number is non zero and falls outside the range claimed by the Host PCI Express bridge the processor will generate Type 1 Configuration Cycle on DMI The PCH routes configurations accesses in a manner similar to the processor The PCH decodes the configuration TLP and generates a corresponding configuration access Accesses targeting a device on PCI Bus 0 may be claimed by an internal device The PCH compares the non zero Bus Number with the Secondary Bus Number and Subordinate Bus Number registers of its PCI to PCI bridges to determine if the configuration access is meant for Primary PCI or some other downstream PCI bus or PCI Express link Configuration accesses that are forwarded to the PCH but remain unclaimed by any device or bridge will result in a master abort Processor Register I ntroduction The processor contains two sets of software accessible registers control registers and internal configuration registers e Control registers are I O mapped into the processor I O space These registers control access t
111. with PAT_DCD asserted 18 14 RO 0 Reserved PATBUF WD SEL uic FE 9 Select word within pattern buffer to be written 11 RO 0 Reserved 10 9 RW 0 PATBUF SEL Select which pattern buffer will be written when MC_TEST_PAT_BA is written 8 6 RO 0 Reserved 5 RW 0 IGN REM PARAM Slave will ignore remote parameters transmitted in Loopback Marker 4 RW 0 ENABLE_LFSR2 Use scrambled output of Pattern Buffer 2 3 RW 0 ENABLE_LFSR1 Use scrambled output of Pattern Buffer 1 2 RW 1 ENABLE_AUTOINV Inversion pattern register will rotate automatically once per loop 1 RW 0 STOP_ON_ERROR Exit Loopback Pattern upon first detected error 0 RWIS 0 ie TEST Initiate transition to Loopback Pattern 234 Datasheet Volume 2 Processor Uncore Configuration Registers L 4 9 8 4 9 9 4 9 10 MC_TEST_PAT_BA Memory Test Pattern Generator Buffer Device 3 Function 4 Offset BOh Access as a DWord Bit Attr Default Description DATA 31 0 RW 0 32 bit window into the indirectly addressed pattern buffer register space 5 15 Memory test pattern inversion selection register Device 3 Function 4 Offset BCh Access as a DWord Bit Attr Default Description 31 8 RO 0 Reserved 7 0 RW 1 LANE I NVERT Per lane selection of normal or inverted pattern MC_TEST_PAT_DCD Memory test DC drive register Device 3 Function 4 Offset COh
112. x TOHM 63 26 is a transaction towards main memory This register is programmed once at boot time and does not change after that including any quiescent flows 25 0 RV 0 Reserved 3 4 4 6 NCMEM BASE NCMEM Base Base address of Intel QuickPath Interconnect non coherent memory Register NCMEM BASE Device 8 Function 0 Offset DCh Bit Attr Default Description Non Coherent Memory Base Address Describes the base address of a 64 MB aligned DRAM memory region on Intel QuickPath Interconnect that is non coherent Address bits 63 26 of an inbound address if it satisfies NcMem Base 63 26 lt A 63 26 lt 3F FFFF NcMem Limit 63 26 is considered to be towards the Intel QuickPath 63 26 RW FFFFh Interconnect non coherent memory region It is expected that the range indicated by the Non coherent memory base and limit registers is a subset of either the low DRAM or high DRAM memory regions as described using the corresponding base and limit registers This register is programmed once at boot time and does not change after that 25 0 RV 0 Reserved Datasheet Volume 2 113 intel Processor Integrated 1 Configuration Registers 3 4 4 7 NCMEM LI MI TCNCMEM Limit Limit address of Intel QuickPath Interconnect non coherent memory Register NCMEM LIMIT Device 8 Function 0 Offset E4h Bit Attr Default Description Non Coherent Memory Limit Address Describes t
113. 0 0111 2 47 1000 2748 3 0 RWL 8h 1001 1111 Reserved When Intel VT d translation is enabled all incoming guest addresses from PCI Express associated with the non isoch Intel VT d engine that go beyond the limit specified in this register will be aborted by and UR response returned This register is not used when translation is not enabled Note that translated and pass through addresses are in the host addressing domain and NOT guest addressing domain and hence GPA LIMIT checking on those accesses are bypassed and instead HPA LIMIT checking applies This field may be locked as RO in Intel TXT mode Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 4 4 31 VTI SOCHCTRL I ntel VT d I soch Related Control Register Register VTISOCHCTRL Device 8 Function O Offset 188h Bit Attr Default Description 31 5 RV 0 Reserved Number of Isoch cache entries when Isoch Intel VT d engine is enabled 000 0 entries 4 2 RWL 0 001 1 entry 010 2 entries Others Reserved 1 RWL 0 2 entries for isochronous Desc This field may be locked as in Intel TXT mode 0 RWL 1 Steer isochronous to non isochronous Intel VT d engine This field may be locked as RO in Intel TXT mode 3 4 4 32 VTGENCTRL2 I ntel VT d General Control 2 Register Register VTGENCTRL2 Device 8 Function O Offset 18Ch Bit Attr Default
114. 0 D2 not supported by Integrated 1 0 11 D3hot If Software tries to write 01 or 10 to this field the power state does not change from the existing power state which is either DO or D3hot and nor do these bits change value 78 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 3 5 PCI e DMI Extended Configuration Space This section describes the extended configuration space 100h to 1FCh for PCI Express and DMI ports 3 3 5 1 API CBASE APIC Base Register Register Device 0 DMI 3 5 PCle Function 0 Offset 140h Bit Attr Default Description 15 12 RO Oh Reserved Bits 19 9 of the APIC Base 11 1 RW Oh Bits 31 20 are assumed to be FECh Bits 8 0 are don t care for address decode Address decoding to the APIC range is done as APIC_BASE 31 8 lt A 31 8 x APIC_LIMIT 31 8 API C Range Enable 8 iid oh Enables the decode of the APIC window 3 3 5 2 API CLI MI T APIC Limit Register Register APICLIMIT Device 0 DMI 3 5 PCle Function 0 Offset 142h Bit Attr Default Description 15 12 RO Oh Reserved Bits 19 9 of the APIC Limit 11 1 RW Oh Bits 31 20 are assumed to be FECh Bits 8 0 are a don t care for address decode Address decoding to the APIC range is done as APIC_BASE 31 8 lt A 31 8 x APIC_LIMIT 31 8 0 RO Oh Reserved 3 3 5 3 PERFCTRLSTS Performance Control and
115. 0 Lock for Intel memory region base mask This bit is only cleared upon reset MESEGMASK and MESEGBASE cannot be changed once this bit is set 9 0 RV 0 Reserved Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 4 4 29 VTBAR Base Address Register for Intel VT d Chipset Registers Register VTBAR Device 8 Function 0 Offset 180h Bit Attr Default Description Intel VT d Chipset Base Address This field provides an aligned 8 K base address for registers relating to 31 13 RWL 00000h e VT d All inbound accesses to this region are completer aborted by the This is programmed once at boot time and does not change after that This field may be locked as RO in Intel TXT mode 12 1 RV 000h Reserved I ntel VT d Chipset Base Address Enable 0 RWL 0 Enables the VTBAR register This bit is RO when VTGENCTRL 15 1 OR may be locked as RO in Intel TXT mode else this bit is RW Datasheet Volume 2 125 intel 3 4 4 30 126 Processor Integrated 1 Configuration Registers VTGENCTRL Intel VT d General Control Register Register VTGENCTRL Device 8 Function 0 Offset 184h Bit Attr Default Description Lock Intel VT d 15 RWO Ob When this bit is 0 the VTBAR 0 is RWL where the lock functionality is described in VTBAR register When this bit is 0 VTBAR O0 is RO 14 11 RV Oh Reserved Isoch GPA LIMIT
116. 12 MC_RIR_WAY_CH1_ 13 MC_RIR_WAY_CH1_14 MC_RIR_WAY_CH1_15 MC_RIR_WAY_CH1_16 MC_RIR_WAY_CH1_17 MC_RIR_WAY_CH1_18 MC RIR WAY CH1 19 RIR WAY 1 20 MC RIR WAY 1 21 RIR WAY 1 22 RIR WAY 1 23 RIR WAY 1 24 MC RIR WAY 1 25 RIR WAY 1 26 MC RIR WAY 1 27 MC WAY 1 28 MC RIR WAY 1 29 WAY 1 30 MC WAY CH1 31 Channel Rank Interleave Way Range Registers These registers allow the user to define the ranks and offsets that apply to the ranges defined by the LIMIT in the MC RIR LIMIT CH registers The mappings are as follows RIR LIMIT CH chan 0 gt RIR WAY CH chan 3 0 RIR LIMIT CH chan 1 gt RIR WAY CH chan 7 6 RIR LIMIT CH chan 2 gt RIR_WAY_CH chan 11 10 RIR LIMIT CH chan 3 gt RIR WAY CH chan 15 14 RIR LIMIT CH chan 4 gt RIR_WAY_CH chan 19 18 RIR LIMIT CH chan 5 gt RIR WAY CH chan 23 22 RIR LIMIT 61 gt RIR WAY CH chan 27 26 LIMIT CH chan 7 gt RIR_WAY_CH chan 31 28 Device 5 Function 2 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch AOh A4h A8h ACh BOh B4h B8h BCh COh C4h C8h CCh DOh D4h D8h DCh EOh E4h E8h ECh FOh F4h F8h FCh Access as a DWord Bit Attr Default Description 31 5 RO 0 Reserved OFFSET 13 4 RW 0 This field defines the offset used in the rank interleave This is a 2 s complement value RANK This field defines whi
117. 13 12 RW PAM5_HI ENABLE OE4000h OE7FFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OE4000h to OE7FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 11 10 RO Reserved RW PAM5_LOENABLE 0 0000 OE3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from OE0000h to OE3FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM RO Reserved RW ODCOOOh ODFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from ODCOOOh to ODFFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM
118. 19 I OLI M I O Limit Register The 1 0 Base register defines an address range that is used by the PCI Express port to determine when to forward 1 0 transactions from one interface to the other using the following formula IO 5 lt A 15 12 x IO LIMIT The bottom of the defined 1 0 address range will be aligned to a 4 KB 1 KB if EN1K bit is set Refer to 5 register for definition of EN1K bit boundary while the top of the region specified by IO LIMIT will be one less than a 4 KB 1 KB if EN1K bit is set multiple Setting the 1 0 limit less than 1 0 base disables the I O range altogether Register IOLIM Device 3 5 PCI e Function O Offset 1Dh Bit Attr Default Description 7 4 RW Oh 1 O Address Limit Corresponds to A 15 12 of the 1 0 addresses at the PCI Express port 3 2 RWL Oh When is set these bits become RW and allow for 1 K granularity of i 1 O addressing otherwise these bits are RO O Address Limit Capability 10 RO on only supports 16 bit addressing Note In general the I O limit register will not be programmed by software without clearing the 5 bit first Datasheet Volume 2 45 intel Processor Integrated 1 Configuration Registers 3 3 3 20 SECSTS Secondary Status Register Secondary Status register is a 16 bit status register that reports the occurrence of various events associated with secondary side that is
119. 2 Processor Integrated 1 110 Configuration Registers 3 3 4 3 3 4 1 3 3 4 2 Sheet 2 of 2 Register Device Function 0 Offset 3Eh BCTRL 3 5 PCle Bit Attr Default Description ISA Enable This bit modifies the response by the Integrated 1 0 to an I O access issued by the processor that target ISA I O addresses This applies only to 1 0 addresses that are enabled by the IOBASE and IOLIM registers 0 All addresses defined by the IOBASE and IOLIM for processor I O transactions will be mapped to PCI Express 1 The Integrated 1 0 will not forward to PCI Express I O transactions addressing the last 768 bytes in each 1 KB block even if the addresses are within the range defined by the IOBASE and IOLIM registers SERR Enable This bit controls forwarding of ERR COR ERR NONFATAL and ERR FATAL messages from the PCI Express port to the primary side 0 Disables forwarding of ERR COR ERR NONFATAL and ERR FATAL 1 Enables forwarding of ERR COR ERR NONFATAL and ERR FATAL messages Parity Error Response Enable The Integrated 1 0 ignores this bit This bit though affects the setting of Bit 8 in the SECSTS register Device Specific PCI Configuration Space 40h to FFh SCAPI D Subsystem Capability I dentity Register SCAPID Device 3 5 PCI e Function O Offset 40h Bit Attr Default Description Capability ID ae RO
120. 21 3 4 4 22 122 Processor Integrated 1 Configuration Registers GMMI OH BASE Global MMI OH Base Register GMMIOH BASE Device 8 Function 0 Offset 128h Bit Attr Default Description Global MMI OH Base Address This field corresponds to A 31 26 of global MMIOH base An inbound or outbound memory address that satisfies global MMI OH base upper 31 0 global MMIOH base 15 10 lt A 63 26 lt global MMI OH limit 15 10 RW 00h upper 31 0 global MMI OH limit 15 10 but is outside of the local MMIOH range is treated as a remote peer to peer transaction over Intel QuickPath Interconnect link Setting GMMIOH BASEU GMMIOH BASE greater than GMMI OH LI MITU GMMI OH LIMI T disables global MMI OH peer to peer This register is programmed once at boot time and does not change after that 9 0 RO 000h Reserved GMMI OH LI MI T Global MMI OH Limit Register GMMIOH LI MIT Device 8 Function O Offset 12Ah Bit Attr Default Description Global MMI OH Limit Address This field corresponds to A 31 26 of global MMIOH limit An inbound or outbound memory address that satisfies global MMIOH base upper 31 0 global MMIOH base 15 10 lt A 63 26 x global MMI OH limit 15 10 RW 00h upper 31 0 global MMI OH limit 15 10 but is outside of the local MMIOH range is treated as a remote peer to peer transaction over Intel QuickPath Interconnect link Setting GMMIOH BASE
121. 3 Function 4 contains the test registers for the Integrated Memory Controller and resides at DID of 2C9Ch Device 4 Integrated Memory Controller Channel 0 Device 4 Function 0 contains the control registers for Integrated Memory Controller Channel 0 and resides at DID of 2CAOh Device 4 Function 1 contains the address registers for Integrated Memory Controller Channel 0 and resides at DID of 2CA1h Device 4 Function 2 contains the rank registers for Integrated Memory Controller Channel 0 and resides at DID of 2CA2h Device 4 Function 3 contains the thermal control registers for Integrated Memory Controller Channel 0 and resides at DID of 2CA3h Device 5 Integrated Memory Controller Channel 1 Device 5 Function 0 contains the control registers for Integrated Memory Controller Channel 1 and resides at DID of 2CA8h Device 5 Function 1 contains the address registers for Integrated Memory Controller Channel 1 and resides at DID of 2CA9h Device 5 Function 2 contains the rank registers for Integrated Memory Controller Channel 1 and resides at DID of 2CAAh Device 5 Function 3 contains the thermal control registers for Integrated Memory Controller Channel 1 and resides at DID of 2CABh Datasheet Volume 2 183 Processor Uncore Configuration Registers Device Mapping Each component in the processor is uniquely identified by a PCI bus address consisting of Bus Number Device Number and Function Number Device configuration is based
122. 3 3 3 1 VID Vendor Identification 35 3 3 3 2 DID Device Identification 35 3 3 3 3 PCICMD PCI Command 36 3 3 3 4 PCISTS PCI Status lt 38 3 3 3 5 RID Revision Identification 40 3 3 3 6 CCR Class Code lt nens 40 3 3 3 7 CLSR Cacheline Size Register sss 41 3 3 3 8 PLAT Primary Latency 41 3 3 3 9 HDR Header Type Register 41 3 3 3 10 SVID Subsystem Vendor nerin 42 3 3 3 11 SID Subsystem Identity sss Hs 42 3 3 3 12 CAPPTR Capability Pointer 000 s 42 3 3 3 13 INTLIN Interrupt Line Register 000022 222 2 42 3 3 3 14 INTPIN Interrupt Pin Register sss 43 3 3 3 15 PBUS Primary Bus Number 43 3 3 3 16 SECBUS Secondary Bus Number 43 3 3 3 17 SUBBUS Subordinate Bus Number 44 3 3 3 18 IOBAS 1 O Base
123. 3 4 24 SLTCON PCI Express Slot Control 69 3 3 4 25 Express Root Control 70 3 3 4 26 ROOTCAP PCI Express Root Capabilities Register 71 3 3 4 27 5 Express Root Status 2 72 3 3 4 28 DEVCAP2 PCI Express Device Capabilities Register 2 73 3 3 4 29 DEVCTRL2 PCI Express Device Control Register 2 74 3 3 4 30 2 Express Link Control Register 2 75 3 3 4 31 LNKSTS2 PCI Express Link Control Register 2 76 3 3 4 32 PMCAP Power Management Capabilities Register 76 3 3 4 33 PMCSR Power Management Control and Status Register Device 0 2 3 77 3 3 4 34 PMCSR Power Management Control and Status Register 78 3 3 5 PCle DMI Extended Configuration 79 3 3 5 1 APICBASE APIC Base 79 3 3 5 2 APICLIMIT APIC Limit Register 222222 79 3 3 5 3 PERFCTRLSTS Performance Control and Status Register 79 3 3 5 4 MISCCTRLSTS Miscellaneous Control and Status Register 81
124. 3 RO Oh Reserved 12 9 RO Oh Reserved 8 RO Oh Reserved 7 4 RV Oh Reserved 3 RV Oh Reserved 2 RV Oh Reserved Power State This 2 bit field is used to determine the current power state of the function and to set a new power state 00 DO default 1 0 RO Oh 01 D1 not supported by Integrated 1 0 10 D2 not supported by Integrated 1 0 11 D3hot If Software tries to write 01 or 10 to this field the power state does not change from the existing power state which is either DO or D3hot and nor do these bits change value Datasheet Volume 2 77 intel Processor Integrated 1 Configuration Registers 3 3 4 34 PMCSR Power Management Control and Status Register This register provides status and control information for PM events in the PCI Express ports of the Integrated 1 0 Register PMCSR Device 3 5 PCle Function 0 Offset E4h Bit Attr Default Description 31 24 RO 00h Reserved 23 RO Oh Bus Power Clock Control Enable This field is hardwired to Oh as it does not apply to PCI Express 22 RO Oh Reserved 21 16 RV Oh Reserved 15 RV Oh Reserved 14 13 RO Oh Reserved 12 9 RO Oh Reserved 8 RWS Oh Reserved 7 4 RV Oh Reserved 3 RWO 1 Reserved 2 RV Oh Reserved Power State This 2 bit field is used to determine the current power state of the function and to set a new power state 00 DO default 1 0 RW Oh 01 01 not supported by Integrated 1 0 1
125. 30 RO 0 Reserved CYCLES THROTTLED 29 4 RO 0 This field indicates the number of throttle cycles triggered in all ranks since last temperature sample 3 0 RO 0 RANK TEMP The field specifies whether the rank is above throttling threshold 268 Datasheet Volume 2 Processor Uncore Configuration Registers 4 13 3 4 13 4 MC_THERMAL_DEFEATUREO MC_THERMAL_DEFEATURE1 Thermal Throttle defeature register Device 4 5 Function 3 Offset 50h Access as a DWord Bit Attr Default Description 31 1 RO 0 Reserved THERM_REG_LOCK 0 RWIS 0 When set to 1 no further modification of all thermal throttle registers are allowed This bit must be set to the same value for all channels MC_THERMAL_PARAMS_ AO MC_THERMAL_PARAMS_ 1 Parameters used by Open Loop Throughput Throttling OLTT and Closed Loop Thermal Throttling CLTT Device 4 5 Function 3 Offset 60h Access as a DWord Bit Attr Default Description CKE_ASSERT_ENERGY 31 24 RW 0 Energy of having CKE asserted when command is issued 23 16 RW 0 CKE_ DEASSERT_ ENERGY Energy of having CKE deasserted when no command is issued 15 8 RW 0 WHCMD ENERGY Energy of a write including data transfer RDCMD ENERGY 7 0 RW 0 Energy of a read including data transfer Datasheet Volume 2 269 intel 4 13 5 4 13 6 270 Processor Uncore Configuration Registers MC THERMAL PARAMS B
126. 32 bits in size Writes to Reserved registers have no effect on the processor Registers that are marked as Intel Reserved must not be modified by system software Writes to Intel Reserved registers may cause system failure Reads to Intel Reserved registers may return a non zero value Default Value upon a Reset Upon a reset the processor sets all of its internal configuration registers to predetermined default states Some register values at reset are determined by external strapping options The default state represents the minimum functionality feature set required to successfully bring up the system Hence it does not represent the optimal system configuration It is the responsibility of the system initialization software usually BIOS to properly determine the DRAM configurations operating parameters and optional system features that are applicable and to program the processor registers accordingly ST appended to the end of a bit name The bit is sticky or unchanged by a hard reset These bits can only be cleared by a PWRGOOD reset Datasheet Volume 2 Configuration Process and Registers L D 2 2 1 2 1 1 Configuration Process and Registers Platform Configuration Structure The DMI physically connects the processor and the Intel Platform Controller Hub PCH From a configuration standpoint the DMI is logically PCI Bus 0 A physical PCI Bus 0 does not exist
127. 4h Bit Attr Default Description 31 19 Physical Slot Number RWO Oh This field indicates the physical slot number of the slot connected to the PCI Express port and is initialized by BIOS 18 Command Complete Not Capable RO Oh Integrated 1 0 is capable of command complete interrupt 17 Electromechanical I nterlock Present When set to 1 this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot and that lock is controlled by Bit 11 in Slot Control register BIOS Note This capability is not set if the Electromechanical Interlock control is connected to main slot power control RWO Oh 16 15 Slot Power Limit Scale This field specifies the scale used for the Slot Power Limit Value and is initialized by BIOS 110 uses this field when it sends a Set_Slot_Power_Limit message on PCI Express RWO Oh Range of Values 00 1 0x 01 0 1x 10 0 01x 11 0 001x 14 7 Slot Power Limit Value This field specifies the upper limit on power supplied by slot in conjunction with the Slot Power Limit Scale value defined previously Power limit in Watts SPLS x SPLV This field is initialized by BIOS IIO uses this field when it sends a RWO 00h Set Slot Power Limit message on PCI Express Design Note Integrated 1 0 can choose to send the Set Slot Power Limit message on the link at first link up condition without regards to whether this register and the S
128. 5 10 is treated as a local peer to peer transaction that does not cross an Intel QuickPath Interconnect link Setting LMMI OH BASEU LMMI OH BASE greater than LMMI OH LI MI TU LMMI OH LI MIT disables local MMI OH peer to peer This register is programmed once at boot time and does not change after that LMMI OH LI MI TU Local MMI OH Limit Upper Register LMMI OH LI MI TU Device 8 Function O Offset 118h Bit Attr Default Description 31 19 RO 0000h This field corresponds to address A 63 51 of the local MMIOH range and is always 0 Local MMI OH Limit Upper Address This field corresponds to A 50 32 of MMI OH limit An inbound or outbound memory address that satisfies local MMIOH base upper 31 0 local MMIOH base 15 10 lt A 63 26 lt local MMIOH limit upper 31 0 local MMI OH 18 0 RW 00000h limit 15 10 is treated as local a peer to peer transactions that does not cross an Intel QuickPath Interconnect link Setting LMMI OH BASEU LMMI OH BASE greater than LMMI OH LI MI TU LMMI OH LIMIT disables local MMI OH peer to peer This register is programmed once at boot time and does not change after that LCFGBUS BASE Local Configuration Bus Number Base Register Register LCFGBUS BASE Device 8 Function O Offset 11Ch Bit Attr Default Description Local Configuration Bus Number Base This field corresponds to base bus number of bus number range
129. 7 16 10 Address bit 6 MOD3 Address 39 6 Note 6 is the high order bit 11 Reserved ENABLE Enable for DRAM rule 0 RW 0 If Enabled Range between this rule and previous rule is Directed to HOME channel unless overridden by other dedicated address range registers If disabled all accesses in this range are directed in MMIO to the IIH Datasheet Volume 2 Processor Uncore Configuration Registers 4 5 12 SAD INTERLEAVE LIST 0 SAD INTERLEAVE LIST 2 SAD INTERLEAVE LIST 4 SAD INTERLEAVE LIST 6 intel SAD INTERLEAVE LIST 1 SAD INTERLEAVE LIST 3 SAD INTERLEAVE LIST 5 SAD INTERLEAVE LIST 7 This register contains SAD DRAM package assignments When the corresponding DRAM RULE hits a 3 bit number determined by mode is used to index into the interleave list to determine which package is the HOME for this address 00 IIH 01 Socket 0 10 Reserved 11 Reserved Device 0 Function 1 Offset COh C4h C8h CCh DOh D4h D8h DCh Access as a DWord Bit Attr Default Description 31 30 RO 0 Reserved 29 28 RW 0 PACKAGE7 Package for group 7 of interleaves 27 26 RO 0 Reserved 25 24 RW 0 PACKAGES Package for group 6 of interleaves 23 22 RO 0 Reserved 21 20 RW 0 PACKAGES Package for group 5 of interleaves 19 18 RO 0 Reserved 17 16 RW 0 PACKAGE4 Package for group 4 of interleaves 15 14 RO 0 Reserved 13 12 RW 0 PACKAGE3 Package for grou
130. 9 RV 0 Reserved Queue Tail 18 4 RW 0 Specifies the offset 128 bit aligned to the invalidation queue for the command that will be written next by software 3 0 RV 0 Reserved Datasheet Volume 2 151 intel Processor Integrated 1 Configuration Registers 3 5 2 20 INV_QUEUE_ADD 0 1 Invalidation Queue Address Register Register INV_QUEUE_ADD 0 1 Addr MMIO BAR VTBAR Offset 90h 1090h Bit Attr Default Description IRQ Base Bode Ra 3 This field points to the base of size aligned invalidation request queue 11 3 RV 0 Reserved Queue Size 2 0 RW 0 This field specifies the length of the invalidation request queue The number of entries in the invalidation queue is defined as 2 X 8 where X is the value programmed in this field 3 5 2 21 INV_COMP_STATUS 0 1 I nvalidation Completion Status Register Register INV_COMP_STATUS 0 1 Addr MMIO BAR VTBAR Offset 9Ch 109Ch Bit Attr Default Description 31 1 RV 0 Reserved Invalidation Wait Descriptor Complete 0 RW1CS 0 Indicates completion of Invalidation Wait Descriptor with Interrupt Flag IF field set Once set this field remains set till software clears it 152 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 5 2 22 INV COMP EVT CTL 0 1 I nvalidation Completion Event Control Register Register COMP EVT
131. AY CH chan 11 10 RIR LIMIT CH chan 3 gt WAY CH chan 15 14 RIR LIMIT CH chan 4 gt RIR WAY CH chan 19 18 RIR LIMIT CH chan 5 gt RIR_WAY_CH chan 23 22 RIR LIMIT CH chan 6 gt RIR WAY CH chan 27 26 RIR LIMIT CH chan 7 gt WAY CH chan 31 28 Access as a DWord Device 4 Function 2 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch AOh A4h A8h ACh BOh B4h B8h BCh COh C4h C8h CCh DOh D4h D8h DCh EOh E4h E8h ECh FOh F4h F8h FCh complement value Bit Attr Default Description 31 14 RO 0 Reserved OFFSET 13 4 RW 0 This field defines the offset used in the rank interleave This is a 2 s RANK RW This field defines which rank participates in WAY n If MC CLOSEDPAGE 1 this field defines the DRAM rank selected when MemoryAddress 7 6 n If MC CLOSEDPAGE 0 this field defines which rank is selected when MemoryAddress 13 12 n n is the instantiation of the register This field is organized by physical rank Bits 3 2 are the encoded DIMM ID slot Bits 1 0 are the rank within that DI MM Datasheet Volume 2 Processor Uncore Configuration Registers L 4 12 4 Datasheet Volume 2 MC_RIR_WAY_CH1_0 MC_RIR_WAY_CH1_1 MC_RIR_WAY_CH1_2 MC_RIR_WAY_CH1_ 3 MC_RIR_WAY_CH1_ 4 MC_RIR_WAY_CH1_5 MC_RIR_WAY_CH1_6 MC_RIR_WAY_CH1_7 MC_RIR_WAY_CH1_8 MC_RIR_WAY_CH1_9 MC_RIR_WAY_CH1_10 MC_RIR_WAY_CH1_11 MC_RIR_WAY_CH1_
132. Attr Default Description Device Identification Number D155h F 0 Identifier assigned to the product Integrated I O will have a unique D156h F 1 id for each device 15 0 RO D157h F 2 value is assigned by Intel to each product Integrated D158h F 3 1 O will have a unique device ID for each of its single function devices and a unique device ID for each function in the multi function devices 3 4 2 3 PCI CMD PCI Command Register This register defines the PCI 3 0 compatible command register values applicable to PCI Express space Sheet 1 of 3 Register PCICMD Device 8 Function 0 3 Offset 04h Bit Attr Default Description 15 11 RV 00h Reserved INTDIS Interrupt Disable This bit does not affect the ability of the Express port to route interrupt 10 RO 0 messages received at the PCI Express port 0 Legacy Interrupt message generation is enabled 1 Legacy Interrupt message generation is disabled 9 RO 0 Fast Back to Back Enable Not applicable to PCI Express and is hardwired to O 98 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers Sheet 2 of 3 Offset Register Device Function PCICMD 8 0 3 04h Bit Attr Default Description RO SERR Enable For PCI Express DMI ports this field enables notifying the internal core error logic of occurrence of an uncorrectable error fatal or no
133. BAR Offset 20h 1020h Bit Attr Default Description Root Entry Table Base Address 4 K aligned base address for the root entry table Processor does not utilize bits 63 36 and checks for them to be 0 Software specifies the base address 63 12 RW 0 of the root entry table through this register and enables it in hardware through the SIRTP field in the Global Command register Reads of this register returns value that was last programmed to it 11 0 RV 0 Reserved Datasheet Volume 2 145 intel Processor Integrated 1 Configuration Registers 3 5 2 7 CTXCMD 0 1 Context Command Register Register Addr BAR Offset CTXCMD 0 1 MMIO VTBAR 28h 1028h Bit Attr Default Description 63 RW 0 Invalidate Context Entry Cache ICC Software requests invalidation of context cache by setting this field Software must also set the requested invalidation granularity by programming the CIRG field Software must read back and check the ICC field to be clear to confirm the invalidation is complete Software must not update this register when this field is set Hardware clears the ICC field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the CAIG field Software must not submit another invalidation request through this register while the ICC field is set Since information from the context cach
134. BAREN Device O offset 50h bit 0 All the bits in this register are locked in Intel TXT enabled mode Register DMIRCBAR Device 0 DMI Function 0 Offset 50h Bit Attr Default Description DMI Base Address DMI RCBAR This field corresponds to Bits 32 12 of the base address DMI Root Complex register space BIOS will program this register resulting in a base address for a 4 KB block of contiguous memory address space This register ensures that 31 12 RWO 00000h naturally aligned 4 KB space is allocated within the first 64 GB of addressable memory space System Software uses this base address to program the DMI Root Complex register set All the Bits in this register are locked in Intel Trusted Execution Technology Intel TXT enabled mode 11 1 RV 00h Reserved DMI RCBAR Enable DMI RCBAREN 0 RW 0 0 DMIRCBAR is disabled and does not claim any memory 1 DMIRCBAR memory mapped accesses are claimed and decoded 52 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 3 4 6 MSICAPID MSI Capability 10 Register MSICAPID Device 0 DMI 3 5 PCIe Function O Offset 60h Bit Attr Default Description Capability I dentifier 7 0 RO 05h Assigned by PCI SIG for MSI root ports 3 3 4 7 MSINXTPTR MSI Next Pointer Register MSINXTPTR Device 0 DMI 3 5 PCle Function 0 Offset 61h Bit Attr Default Desc
135. CAIG field 00 Reserved This is the value on reset 01 Global Invalidation performed sets this in response to a global invalidation request 10 Domain selective invalidation performed using the domain ID that was specified by software in the DID field set this in response to a domain selective or device selective invalidation request 11 Device selective invalidation never sets this encoding 58 34 RV 0000000h Reserved 33 32 RW 00b Function Mask Since does not perform any device selective invalidation this field is a don t care 31 16 RW 0000h Source ID ignores this field Used when performing device selective context cache invalidation RW 0000h Domain ID Indicates the ID of the domain whose context entries needs to be selectively invalidated S W needs to program this for both domain and device selective invalidates ignores Bits 15 8 since it supports only a 8 bit Domain ID 146 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 5 2 8 FLTSTS 0 1 Fault Status Register Register FLTSTS 0 1 Addr MMIO BAR VTBAR Offset 34h 1034h Bit Attr Default Description 31 16 RV 0 Reserved Fault Record Index This field is valid only when the Primary Fault Pending field is set This 15 8 ROS 0 field indicates the index from base of the fault recording re
136. Default Description 63 40 RV 0 Reserved MASK 39 19 RW 0 Mask of Intel ME SEG Space must be power of 2 aligned Field indicates which bits must match the BASE in order to be inside the Intel ME range ENABLE 11 RW 0 Enable for Intel ME SEG When enabled all core access to Intel ME SEG space is aborted LOCK 10 RWE 0 Lock for Intel ME SEG base mask 9 0 RO 0 Reserved Datasheet Volume 2 215 Processor Uncore Configuration Registers SAD_DRAM_RULE_0 SAD_DRAM_RULE_ 1 SAD DRAM RULE 2 SAD DRAM RULE 3 SAD DRAM RULE 4 SAD DRAM RULE 5 SAD DRAM RULE 6 SAD DRAM RULE 7 SAD DRAM rules Address Map for package determination 216 Device 0 Function 1 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch Access as a DWord Bit Attr Default Description 31 20 RV 0 Reserved LI MI T DRAM rule top limit address This bit must be strictly greater than previous rule even if this rule is 19 6 RW disabled unless this rule and all following rules are disabled Lower limit is the previous rule or 0 if it is first rule This field is compared against MA 39 26 in the memory address map 5 3 RO 0 Reserved MODE DRAM rule interleave mode If a DRAM_RULE hits a 3 bit number is used to index into the corresponding interleave list to determine which package the DRAM belongs to This mode selects how that number is computed EE RW 00 Address bits 8 7 6 01 Address bits 8 7 6 XORed with 18 1
137. Description 31 11 RV 0 Reserved 10 7 RWL Fh LRU Timer Prefetch Control This field controls which Intel VT d reads are to be considered for prefetch snarf reuse in the Intel QuickPath Interconnect buffers 6 5 RWL 01 00 Prefetch snarf reuse is disabled 01 Prefetch snarf reuse is enabled for all leaf non leaf Intel VT d page walk reads Others Reserved 4 RV 0 Reserved 3 RV 0 Reserved 2 RV 0 Reserved 1 RV 0 Reserved 0 RV 0 Reserved Datasheet Volume 2 127 Processor Integrated 1 Configuration Registers intel 3 4 4 33 VTSTS Intel VT d Status Register Register VTSTS Device 8 Function O Offset 190h Bit Attr Default Description 31 2 RV 00000000h Reserved 1 RW1CS 0 Interrupt Transaction Seen on VC1 VCp 0 RW1CS 0 Reserved 3 4 5 Semaphore and ScratchPad Registers Dev 8 F 1 3 4 5 1 SR 0 3 Scratch Pad Register 0 3 Sticky Register SR 0 3 Device 8 Function 1 Offset 07Ch 088h by 4 Bit Attr Default Description Scratch Pad Sticky 31 RWSLB Oh 2 Sticky scratch pad registers for firmware utilization 3 4 5 2 SR 4 7 Scratch Pad Register 4 7 Sticky Register SR 4 7 Device 8 Function 1 Offset 08 098 by 4 Bit Attr Default Description Scratch Pad Sticky 31 0 RWSLB Oh 8 Sticky scratch pad registers for firmware utilization 3 4 5 3 SR 8 11 Scratch Pad Regi
138. EJIStE 169 3 6 1 12 TXT SINIT MEMORY BASE Intel TXT SINIT Code Base Register 169 3 6 1 13 TXT SINIT MEMORY SIZE Intel TXT SINIT Memory Size iM 170 3 6 1 14 TXT MLE J OIN Intel TXT MLE Join Base Register 170 3 6 1 15 TXT HEAP BASE Intel TXT HEAP Code Base Register 171 3 6 1 16 TXT HEAP SIZE Intel TXT HEAP Size 171 3 6 1 17 TXT MSEG BASE Intel TXT MSEG Base 172 3 6 1 18 TXT MSEG SIZE Intel TXT MSEG Size Register 172 3 6 1 19 TXT SCRATCHPADO Intel TXT Scratch Pad Register 0 173 3 6 1 20 TXT SCRATCHPAD1 Intel TXT Scratch Pad Register 1 173 3 6 1 21 TXT CMD OPEN LOCALI TY1 Intel TXT Open Locality 1 Gere ET 174 3 6 1 22 TXT CMD CLOSE LOCALITY1 Intel TXT Close Locality 1 EET 174 3 6 1 23 TXT CMD OPEN LOCALI TY2 Intel TXT Open Locality 2 COMMANG E EEUUMMT 174 3 6 1 24 TXT CMD CLOSE LOCALI TY2 Intel TXT Close Locality 2 COMMANG aiiis dines pidintthacsekin simiturfaR eR ein 175 3 6 1 25 TXT PUBLIC KEY Intel TXT Public Key Hash Register 175 3 7 Intel QuickPath Interconnect Device Functions cesse 176 3 7 1 Intel QuickPath Interconnect Link Layer 177 3 7 1 1
139. EN bit set and is not within the 1 0 base limit range of any of the PCle ports and DMI is the subtractive decode port Forward to DMI Address within 03BOh 3BBh 3COh 3DFh and inbound 1 is enabled and main switch SAD is NOT programmed to forward VGA and none of the PCle has VGAEN bit set and is not within the base limit range of any PCIE port and DMI port is not the subtractive decode port Master abort Other Peer to Peer Address within BASE LI O LIMIT and inbound 1 is enabled and a PCle port positively decoded as target Forward to the PCI Express port Address within LI O BASE LI O LIMIT and inbound 1 is enabled and no PCle port positively decoded as target and DMI is the Subtractive decode port Forward to DMI Address within BASE LI O LIMIT and inbound 1 is enabled and no PCle port decoded as target and DMI is not the subtractive decode port Master Abort Inbound I O is enabled and address NOT within LIO BASE LIO LI MIT but is within GIO BASE GIO LIMIT Forward to Intel QuickPath Interconnect Non existent Addresses Address gt 64 KB Master Abort All Else Forward to subtractive decode port Notes 1 Inbound 1 0 is enabled using CSRMISCCTRLSTS 30 298 Datasheet Volume 2 System Address Map intel Table 5 10 summarizes behavior on inbound configuration transactions from any PCIe port Table 5 10 Inbound Con
140. Express Base Specification for details These ranges are also summarized in Table 5 4 VTCSR Remote peer to peer accesses from Intel QuickPath Interconnect that target VTCSR region are not completer aborted by If inbound protection is needed VTd translation table should be used to protect at the source IIO If the VTd table is not enabled a Generic Protected Memory Range could be used to protect A last defense is to turn off IB peer to peer MMIO The remote peer to peer support is an issue not yet closed completely yet Remote peer to peer PCI configuration transactions from Intel QuickPath Interconnect that target the internal bus number of IIO regardless of device number are aborted by IIO 292 Datasheet Volume 2 System Address Map 5 8 1 4 Table 5 4 5 8 1 5 Note Table 5 5 intel Summary of Outbound Target Decoder Entries Table 5 4 provides a list of all the target decoder entries in such as PCle port required by the outbound target decoder to positively decode towards a target Outbound Target Decoder Entries 2 Target Address Region Decoder Entry Comments VGA Memory space A 0000h FFFFh and 1 space 3BOh 4411 Fixed 3BBh and 3COh 3DFh TPM TXT FW ranges E F segs and 4 G 16 M to 4 G 1 Fixed Variable From peer to peer Bridge Configuration MMIOL E Register Space MMIOH 4 Variable From peer to peer Bridge Configuration Regis
141. GBUS LIMIT Device 8 Function 0 Offset 135h Bit Attr Default Description Global Configuration Bus Number Limit This field corresponds to limit bus number of bus number range allocated across all 11 5 in the partition An inbound or outbound configuration that 7 0 RW FFh satisfies Global Bus Number Base 7 0 lt Bus Number 7 0 lt Global Bus Number Limit 7 0 but is outside of the low bus number range is treated as a remote peer to peer transaction over Intel QuickPath Interconnect link This register is programmed once at boot time and does not change after that MESEGBASE Intel Management Engine Intel ME Memory Region Base The MESEGBASE and MESEGMASK registers are used for protecting Intel Management Engine Intel ME stolen memory from processor accesses Register MESEGBASE Device 8 Function O Offset 138h Bit Attr Default Description 63 36 RV 0 Reserved Base address of ME SEG 35 19 RWL 1FFFFh Must be 4 MB aligned This field is controlled by Bit 10 of MESEGMASK register 18 0 RV 0 Reserved MESEGMASK Intel ME Memory Region Mask Register MESEGMASK Device 8 Function 0 Offset 140H Bit Attr Default Description 63 36 RV 0 Reserved Which bits must match the MESEGBASE order to be inside the Intel 35 19 RWL 0 memory region 18 12 RV 0 Reserved 11 RWO 0 Enable for Intel ME memory region 10
142. I Express DMI ports this bit is not used to control the reporting of other internal component uncorrectable non fatal errors at the port unit in any way RO Correctable Error Reporting Enable This bit applies only to the PCI Express DMI ports The bit controls the reporting of correctable errors that detects on the PCI Express DMI interface 0 Reporting of link Correctable error detected by the port is disabled 1 Reporting of link Correctable error detected by port is enabled Refer to the latest PCI Express Base Specification for complete details of how this bit is used in conjunction with other bits to report errors For the PCI Express DMI ports this bit is not used to control the reporting of other internal component correctable errors at the port unit in any way Datasheet Volume 2 109 Processor Integrated Configuration Registers intel 3 4 3 6 DEVSTS PCI Express Device Status Register The PCI Express Device Status register provides information about PCI Express device specific parameters associated with the device Device 8 Function 0 1 2 Offset 4Ah Bit Attr Default Description 15 6 RO 000h Reserved Transactions Pending 0 This bit cleared only when all Completions for any outstanding Non 5 RO Oh Posted Requests it owns have been received 1 Indicates that the DMA device has outstanding Non Posted Request which it has issued either towards
143. I Express port by directing the LTSSM to the recovery state if the current state is LO LOs or L1 If the current state is anything other than LO 105 L1 then a write to this bit does nothing This bit always returns 0 when read 5 wo 0 If the Target Link Speed field has been set to a non zero value different than the current operating speed the LTSSM will attempt to negotiate to the target link speed It is permitted to write 1 to this bit while simultaneously writing modified values to other fields in this register When this is done all modified values that affect link retraining must be applied in the subsequent retraining Link Disable This field controls whether the link associated with the PCI Express port is enabled or disabled When this bit is a 1 a previously configured link a link 4 RW 0 that has gone past the polling state would return to the disabled state as defined in the latest PCI Express Base Specification When this bit is clear an LTSSM in the disabled state goes back to the detect state 0 Enables the link associated with the PCI Express port 1 Disables the link associated with the PCI Express port 3 RO 0 Read Completion Boundary Set to zero to indicate could return read completions at 64B boundaries 2 RV 0 Reserved 1 0 RW 00 Active State Link PM Control When 01b or 11b LOs on transmitter is enabled otherwise it is disabled Datasheet Volume 2 65 intel Proces
144. IP LATENCY D4h MC CHANNEL 0 DIMM INIT PARAMS 58h MC CHANNEL 0 PAGETABLE PARAMS1 D8h MC CHANNEL 0 DIMM INIT STATUS 5Ch MC CHANNEL 0 PAGETABLE PARAMS2 DCh MC CHANNEL 0 DDR3CMD 60h MC TX BG CMD DATA RATIO SETTINGS CHO EOh NEEDED MC TX BG CMD OFFSET SETTINGS CHO E4h CHANNEL 0 REFRESH THROTTLE SUPPORT 68h MC TX BG DATA OFFSET SETTINGS CHO E8h o C Sg o 88m MC CHANNEL 0 MRS VALUE 0 1 70h FOh MC CHANNEL 0 ADDR MATCH MC CHANNEL 0 MRS VALUE 2 74h F4h CHANNEL 0 RANK PRESENT 7Ch FCh Datasheet Volume 2 193 Processor Uncore Configuration Registers intel Table 4 11 Device 4 Function 1 Integrated Memory Controller Channel 0 Address Registers DID VID 00h 5 0 80h PCISTS PCICMD 04h SAG 1 84h CCR RID 08h 5 2 88h SAG 3 8Ch MC SAG CHO 4 90h SAG CHO 5 94h MC SAG CHO 6 MC SAG CHO 7 98h MC DOD CHO 0 MC DOD CHO 1 194 Datasheet Volume 2 Processor Uncore Configuration Registers m Table 4 12 Device 4 Function 2 Integrated Memory Controller Channel 0 Rank Registers DID VID 00h MC RIR WAY CHO 0 80h PCISTS PCICMD 04h WAY CHO 1 84h CCR RID 08h MC RIR WAY CHO 2 88h OCh MC RIR WAY CHO 3 8Ch MC RIR WAY CHO 4 90h MC
145. Interconnect J TAG that targets one of the downstream devices ports of the In the description in the rest of the section PCle refers to all of a standard PCI Express port and DMI unless noted otherwise General Overview Before any transaction from Intel QuickPath Interconnect is validly decoded by the NodelD in the incoming transaction must match the NodelDs assigned to the any exceptions are noted when required Else it is an error All target decoding toward PCle firmware and internal devices follow address based routing Address based routing follows the standard PCI tree hierarchy routing No NodelD based routing is supported south of the Intel QuickPath Interconnect port in Subtractive decode port in is the port that is the recipient of all addresses that are not positively decoded towards of the valid targets the and b the recipient of all message special cycles that are targeted at the legacy PCH n the processor the DMI is always the subtractive port Virtual peer to peer bridge decoding related registers with their associated control bits for example VGAEN bit and other misc address ranges I OxAPIC of a DMI port are NOT valid and ignored by the IIO decoder when it is set as the subtractive decoding port Subtractive decode transactions are forwarded to the legacy DMI port irrespective of the setting of the MSE IOSE bits in that port Unless specified
146. K edge The Bubble Generators will also be reset IGNORE RX 9 RW 0 When set the read return datapath will ignore all data coming from the RX FIFOS This is done by gating the early valid bit STOP ON FAIL 8 RW 0 When set along with the AUTORESETDIS not being set the phyinit FSM will stop if a step has not completed after timing out RANK 7 5 RW 0 The rank currently being tested The Phyl nit FSM must be sequenced for every rank present in the channel The rank value is set to the rank being trained NXT_PHYINIT_STATE Set to sequence the physical layer state machine 000 IDLE 4 2 RW 0 001 RD DQ DQS 010 RcvEn Bitlock 011 Write Level 100 WR DQ DQs AUTODIS Disables the automatic training where each step is automatically 1 RW 0 incremented When set the physical layer state machine must be sequenced with software The training FSM must be sequenced using the NXT_PHYINIT_STATE field 16 RW 0 15 RW 0 14 RW 0 13 RW 0 12 RW 0 11 RW 0 ll ll TRAIN 0 wo 0 Cycle through the training sequence for the rank specified the RANK field 238 Datasheet Volume 2 Processor Uncore Configuration Registers intel 4 10 3 MC_CHANNEL_0O_DIMM_INIT_PARAMS MC CHANNEL 1 DIMM INIT PARAMS Initialization sequence parameters are stored in this register Each field is 2 n count Device 4 5 F
147. K3 Rank 3 virtual temperature 23 16 RO 0 RANK2 Rank 2 virtual temperature 15 8 RO 0 RANK1 Rank 1 virtual temperature 7 0 RO 0 RANKO Rank 0 virtual temperature MC DDR THERM COMMANDO MC DDR THERM COMMANDI This register contains the command portion of the functionality of the PM EXT 75 1 0 signals Device 4 5 Function 3 Offset 9Ch Access as a DWord Bit Attr Default Description 31 4 RO 0 Reserved 3 RW 0 THROTTLE Force throttling when DDR THERM pin is asserted 2 RW 0 2 Force 2x refresh as long as DDR THERMZ is asserted DISABLE EXTTS DDR_THERM pin disable forces signal to look deasserted thus a 1 LOCK When set all bits in this register are RO and cannot be written 1 RW 0 0 RW 0 Datasheet Volume 2 Processor Uncore Configuration Registers intel 4 13 11 MC DDR THERM STATUSO MC DDR THERM STATUS1 This register contains the status portion of the DDR THERM Z functionality as described in the processor datasheet that is what is happening or has happened with respect to the pin Device 4 5 Function 3 Offset A4h Access as a DWord Bit Attr Default Description 31 3 RO 0 Reserved 2 RO 0 ASSERTI ON An assertion edge was seen on DDR_THERM Write 1 to clear DEASSERTI ON s RO 9 A deassertion edge was seen DDR_THERM Write 1 to clear STATE Present logical state of DDR_THERM bit This is
148. LEAR command Thus this bit will be set immediately after reset since the bits are all 0 SENTER DONE STS The chipset sets this bit when TXT THREADS JOIN TXT THREAD EXISTS and TXT THREADS J OIN 0 0 RO 0 When any of the threads does the TXT J OINS CLEAR to clear the set bit in TXT THREADS JOIN register the TXT THREADS OIN and TXT THREADS EXISTS registers will not be equal so the chipset will clear this bit Datasheet Volume 2 163 intel Processor Integrated 1 Configuration Registers 3 6 1 2 TXT ESTS Intel TXT Error Status Register This register is used to read the status associated with various errors that might be detected General Behavioral Rules This register is available for read only access from the Public configuration space This register is available for read and write access from the Private configuration space Each status bit is cleared by writing to this register with a 1 in the corresponding bit position The bits in this register are cleared by writing a 1 to the corresponding bit positions These bits are not cleared by a standard system reset Base TXT TXT Offset 0008h Base TXT PR Offset 0008h Base TXT PB noWROffset 0008h Bit Attr Default Description 7 RV 0 Reserved TXT WAKE ERROR STS The chipset sets this bit when it detects that there might have been secrets in memory and a reset or power failure occurred If th
149. LOs on transmitter is enabled otherwise it is disabled 64 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers m intel 3 3 4 21 LNKCON PCI Express Link Control Register The PCI Express Link Control register controls the PCI Express Link specific parameters Register LNKCON Device 3 5 PCIe Function O Offset AOh Bit Attr Default Description 15 12 RV 0 Reserved Link Autonomous Bandwidth I nterrupt Enable 11 RW 0 When set to 1 this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set Link Bandwidth Management I nterrupt Enable 10 RW 0 When set to 1 this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set Hardware Autonomous Width Disable 9 RW 0 When set to 1 this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width Enable Clock Power Management 8 RO 9 N A to Extended Sync 7 RW 0 When set to 1 this bit forces the transmission of additional ordered sets when exiting 105 and when in recovery Refer to the latest PCI Express Base Specification for details 6 RW 0 Common Clock Configuration Integrated 1 does nothing with this bit Retrain Link A write of 1 to this bit initiates link retraining in the given PC
150. MI Link Status This register indicates DMI status BAR DMIRCBAR Register DMILSTS Offset 008Ah Bit Attr Default Description 15 10 RO Oh Reserved Negotiated Width NWID Indicates negotiated link width This field is valid only when the link is in the LO LOs or L1 states after link width negotiation is successfully completed 00 Reserved 9 4 RO 00h 01h X1 02h2 X2 04h X4 All other encodings are reserved Negotiated Speed NSPD Indicates negotiated link speed e RO th 1h 2 5 Gb s All other encodings are reserved Datasheet Volume 2 91 L D Processor I ntegrated 1 Configuration Registers 3 4 4 Core Registers Device 8 Function This section describes the standard PCI configuration registers and device specific Configuration Registers related to below Intel VT d address mapping system management Device 8 Function 0 Semaphore and Scratchpad Device 8 Function 1 System control status Device 8 Function 2 e Miscellaneous Registers Device 8 Function 3 3 4 1 Configuration Register Map Device 8 Function 0 3 Table 3 7 Core Registers Device 8 Function 0 Offset 000h OFFh DID VID 00h PCISTS PCICMD 04h CCR ILOMISCCTRL 1 5 55 TSEGCTRL A8h SVID 2Ch CAPPTR 34h INTPIN INTLIN EXPCAP NXTPTR CAPID DEVCAP 44h DEVS
151. MI RCBAR Register DMIVCIRCAP Offset 001Ch Bit Attr Default Description 31 24 RO Oh Reserved for Port Arbitration Table Offset 23 RO 0 Reserved 22 16 RO Oh Reserved for Maximum Time Slots Reject Snoop Transactions REJ SNPT 0 Transactions with or without the No Snoop bit set within the TLP header 15 RO Oh are allowed on this VC 1 Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request 14 8 RO Oh Reserved Port Arbitration Capability PAC 7 0 RO Olh Having only Bit 0 set indicates that the only supported arbitration scheme for this VC is non configurable hardware fixed 88 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 3 6 9 DMI VCIRCTL DMI VC1 Resource Control Controls the resources associated with PCI Express Virtual Channel 1 BAR DMI RCBAR Register DMIVCIRCTL Offset 0020h Bit Attr Default Description 31 RW 0 Virtual Channel 1 Enable VC1E 0 Virtual Channel is disabled 1 Virtual Channel is enabled See exceptions below Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete When VC Negotiation Pending bit is cleared a 1 read from this VC Enable bit indicates that the VC is enabled Flow Control Initialization is completed for the PCI Express port A 0 read from this bit indicates that the Virtual Channel is
152. MM and Legacy C D E F Regions 1 279 Pre allocated Memory Example for 64 MB DRAM 1 MB VGA 1 MB GTT Stolen and 1MB TSEG CT 281 Functions Handled by the Processor Integrated 1 0 28 Device 0 DMI Configuration Map 41 1 41 6 31 Device 0 DMI Extended Configuration Map 4 32 Device 3 5 PCI Express Registers Legacy Configuration 2 21 1 33 Device 3 5 PCI Express Registers Extended Configuration 34 R6gISters 84 Core Registers Device 8 Function 0 Offset 92 Core Registers Device 8 Function 0 Offset 100h 93 Core Registers Device 8 Function 1 Semaphore and ScratchPad Registers Sheet Lof 2 ii itu e ER 94 Core Registers Device 8 Function 1 Semaphore and ScratchPad Registers Sheet 2 Of 2 isses eic e AEA En E enii 95 Core Registers Device 8 Function 2 System Control Status Registers 96 Core Registers Device 8 Function 3 Miscellaneous Registers 97 Intel VT d Memory Mapped Registers
153. NNEL 1 RANK PRESENT 7Ch FCh Datasheet Volume 2 197 Processor Uncore Configuration Registers intel Table 4 15 Device 5 Function 1 I ntegrated Memory Controller Channel 1 Address Registers DID VID 00h MC_SAG_CH1_0 80h PCISTS PCICMD 04h MC_SAG_CH1_1 84h CCR RID 08h MC_SAG_CH1_2 88h OCh MC_SAG_CH1_3 8Ch MC_SAG_CH1_4 90h MC_SAG_CH1_5 94h MC_SAG_CH1_6 MC_SAG_CH1_7 98h MC_DOD_CH1_0 MC_DOD_CH1_1 198 Datasheet Volume 2 Processor Uncore Configuration Registers m Table 4 16 Device 5 Function 2 Integrated Memory Controller Channel 1 Rank Registers DID VID 00h WAY CH1 0 80h PCISTS PCICMD 04h MC RIR WAY CH1 1 84h CCR RID 08h MC RIR WAY 1 2 88h MC RIR WAY CHI 3 8Ch MC RIR WAY 1 4 90h MC RIR WAY 1 5 94h MC RIR WAY CHI 6 98h RIR WAY 1 7 9Ch MC RIR WAY 1 8 AOh MC_RIR_WAY_CH1_9 A4h RIR WAY 1 10 A8h MC_RIR_WAY_CH1_11 ACh MC_RIR_WAY_CH1_12 BOh MC_RIR_WAY_CH1_13 B4h MC RIR WAY CH1l 14 B8h MC RIR WAY 1 15 BCh MC RIR LIMIT CH1 0 40h MC WAY 1 16 COh MC RIR LIMIT CH1 1 44h MC RIR WAY 1 17 C4h MC RIR LIMIT CH1 2 48h MC RIR WAY 1 18 C8h RIR LIMIT 1 3 4Ch RIR WAY 1 19 CCh MC RIR LIMIT CHI 4 50h MC RIR WAY 1 20 DOh MC RIR LIMIT
154. O MC THERMAL PARAMS B1 Parameters used by the thermal throttling logic Device 4 5 Function 3 Offset 64h Access as a DWord Bit Attr Default Description SAFE INTERVAL Safe values for cooling coefficient and duty cycle will be applied while the SAFE INTERVAL is exceeded This interval is the number of ZQ intervals since the last time the MC COOLING COEF or MC CLOSED LOOP registers have been written A register to write to MC COOLING COEF or 31 26 RW 1 MC CLOSED LOOP will re apply the normal MC COOLING COEF and MC CLOSED THROTTLE DUTY CYC values The register value written need not be different writing the current value will suffice The MC THERMAL STATUS CYCLES THROTTLED field is reloaded when the number of ZQ intervals exceeds this value This field must not be programmed to 0 this value is invalid SAFE DUTY CYC 25 16 RW 255 This value replaces CLOSED LOOP MIN THROTTLE DUTY CYC while the MC THERMAL PARAMS B SAFE INTERVAL is exceeded SAFE COOL COEF 15 8 RW 1 This value replaces MC COOLING COEF while the THERMAL PARAMS B SAFE INTERVAL is exceeded ACTCMD ENERGY 7 0 RW 0 Energy of an Activate Precharge Cycle MC COOLING COEFO MC COOLING COEF1 Heat removed from DRAM 8 DCLKs This should be scaled relative to the per command weights and the initial value of the throttling threshold This includes idle command and refresh energies If 2X refresh is supported
155. O hardware would depend on this register for inbound decode purposes 3 3 3 16 SECBUS Secondary Bus Number This register identifies the bus number assigned to the secondary side PCI Express of the virtual PCI to PCI bridge This number is programmed by the PCI configuration software to allow mapping of configuration cycles to devices connected to PCI Express Register SECBUS Device 3 5 PCI e Function O Offset 19h Bit Attr Default Description Secondary Bus Number 7 0 RW 00h This field is programmed by configuration software to assign a bus number to the secondary bus of the virtual PCI to PCI bridge Datasheet Volume 2 43 intel 3 3 3 17 3 3 3 18 Note 44 Processor Integrated 1 Configuration Registers SUBBUS Subordinate Bus Number Register This register identifies the subordinate bus if any that resides at the level below the secondary bus of the PCI Express interface This number is programmed by the PCI configuration software to allow mapping of configuration cycles to devices subordinate to the secondary PCI Express port Register SUBBUS Device 3 5 PCI e Function O Offset 1Ah Bit Attr Default Description Subordinate Bus Number This register is programmed by configuration software with the number 7 0 RW 00h of the highest subordinate bus that is behind the PCI Express port Any transaction that falls between the sec
156. PCI 3 0 configuration space Device 8 Function 0 1 2 Offset 40h Bit Attr Default Description Capability ID 7 0 RO 10h Defines the PCI Express capability ID 10h is defined as a PCI Express capability Datasheet Volume 2 105 intel 3 4 3 2 3 4 3 3 106 Processor Integrated 1 Configuration Registers NXTPTR PCI Express Next Capability List Register The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3 0 configuration space Device 8 Function 0 1 2 Offset 41h Bit Attr Default Description 7 0 RO 0 deis NE This field contains the offset to the next PCI Capability structure Express Capabilities Register The PCI Express Capabilities register identifies the Express device type and associated capabilities Device 8 Function 0 1 2 Offset 42h Bit Attr Default Description 15 14 RV Oh Reserved Interrupt Message Number This field indicates the interrupt message number that is generated for BW change events When there are more than one MSI interrupt 13 9 RO 00h Number this register field is required to contain the offset between the base Message Data and the MSI Message that is generated when the associated status bits in this capability register are set 110 assigns the first vector for PM HP BW change events and so this field is set to 0
157. RAM is not accessible to data references 13 RW 0 even if SMM decode is active Code references may still access SMM space DRAM This will allow SMM software to reference through SMM space to update the display even when SMM is mapped over the VGA range Software should ensure that D 1 and D_CLS 1 are not set at the same time SMM Space Locked D LCK When D LCK is set to 1 D OPEN is reset to 0 and D LCK D OPEN C BASE SEG SMRAME PCI ExpressXBAR DRAM RULEs and INTERLEAVE LISTs become read only D LCK can be set to 1 using a normal configuration space write but can only be cleared by a Reset The 12 RWIS 0 combination of D LCK and D OPEN provide convenience with security The BI OS can use the D OPEN function to initialize SMM space and then use D LCK to lock down SMM space in the future so that no application software or BIOS itself can violate the integrity of SMM space even if the program has knowledge of the D OPEN function Note that TAD does not implement this lock Global SMRAM Enable G SMRAME If set to a 1 Compatible SMRAM functions are enabled providing 128 KB of 11 RW 0 DRAM accessible at the A0000h address while in SMM ADSB with SMM decode To enable Extended SMRAM function this bit has to be set to 1 Once D LCK is set this bit becomes read only Compatible SMM Space Base Segment C BASE SEG This field indicates the location of SMM space SMM DRAM is not remapped It 10 8 RO is simply m
158. RESHOLD 24 20 RW 31 Threshold used to raise the priority of underfill requests in the scheduler Set to 31 to disable ISOCEXI TTHRESHOLD 19 15 RW 31 Write Major Mode ISOC Exit Threshold When the number of writes in the WAQ drops below this threshold the MC will exit write major mode in the presence of a read SOCENTRYTHRESHOLD 14 10 RW 31 Write Major Mode ISOC Entry Threshold When the number of writes in the WAQ exceeds this threshold the MC will enter write major mode the presence of a read WMENTRYTHRESHOLD 9 5 RW 22 Write Major Mode Entry Threshold When the number of writes in the WAQ exceeds this threshold the MC will enter write major mode WMEXI TTHRESHOLD 4 0 RW 22 Write Major Mode Exit Threshold When the number of writes in the WAQ drop below this threshold the MC will exit write major mode Datasheet Volume 2 Processor Uncore Configuration Registers 4 10 24 4 10 25 intel MC CHANNEL O SCHEDULER PARAMS MC CHANNEL 1 SCHEDULER PARAMS These are the parameters used to control parameters within the scheduler Device 4 5 Function O Offset B8h Access as a DWord Bit Attr Default Description 31 14 RO 0 Reserved 13 RW 0 DDR CLK TRISTATE DISABLE When set to 0 DDR clock drivers will always be enabled CS ODT TRISTATE DISABLE When set to 0 CS and ODT drivers will 12 RW 0 always be enabled FLOAT_EN 11 RW 0 When set to 1 the address an
159. Root Port 3 Logically this appears as a virtual PCI to PCI bridge residing on PCI Bus 0 and is compliant with PCI Express Local Bus Specification Revision 1 0 Device 5 contains the standard PCI Express PCI configuration registers including PCI Express Memory Address Mapping registers It also contains the extended PCI Express configuration space that include PCI Express error status control registers and Isochronous and Virtual Channel controls Device 8 Integrated 1 0 Core This device contains the Standard PCI registers for each of its functions This device implements four functions Function 0 contains Address Mapping Intel VT d related registers and other system management registers Function 1 contains Semaphore and Scratchpad registers Function 3 contains System Control Status registers Function 4 contains miscellaneous control status registers on power management and throttling Device 16 Intel QuickPath Interconnect Device 16 Function 0 contains the Intel QuickPath Interconnect configuration registers for Intel QuickPath Interconnect Link Device 16 Function 1 contains the routing and protocol Datasheet Volume 2 27 m t D Processor Integrated 1 Configuration Registers 3 2 Table 3 1 3 2 1 3 3 3 3 1 28 Device Mapping All devices on the Integrated I O Module reside on PCI Bus 0 Table 3 1 describes the devices and functions that the integrated I O module implements or
160. SMM space cache coherency when cacheable extended SMM space is used SMM Access Through GTT TLB Accesses through GTT TLB address translation to enabled SMM DRAM space are not allowed Writes will be routed to Memory address 000C 0000h with byte enables de asserted and reads will be routed to Memory address 000 0000h If a GTT TLB translated address hits enabled SMM DRAM space an error is recorded in the PGTBL_ER register PCI Express and DMI Interface originated accesses are never allowed to access SMM space directly or through the GTT TLB address translation If a GTT TLB translated address hits enabled SMM DRAM space an error is recorded in the PGTBL ER register PCI Express and DMI Interface write accesses through GMADR range will be snooped Assesses to GMADR linear range defined using fence registers are supported PCI Express and DMI Interface tileY and tileX writes to GMADR are not supported If when translated the resulting physical address is to enabled SMM DRAM space the request will be remapped to address 000C 0000h with de asserted byte enables Datasheet Volume 2 289 m System Address Map intel 5 6 5 7 5 7 1 5 7 2 290 PCI Express and DMI Interface read accesses to the GMADR range are not supported therefore will have no address translation concerns PCI Express and DMI Interface reads to GMADR will be remapped to address 000C 0000h The read will complete with UR unsupported request completion sta
161. SVID Subsystem Vendor 10 177 3 7 1 2 SID Subsystem Device ID 177 3 7 1 3 CAPPTR Capability Pointer 00 2 177 3 7 1 4 QPI O LCL Intel QuickPath Interconnect Link Control 178 3 7 1 5 QPI O LCRDC Intel QuickPath Interconnect Link Credit Control 179 3 7 2 Intel QuickPath Interconnect Routing amp Protocol Layer Registers 180 3 7 2 1 QPIPCTRLO Intel QuickPath Interconnect Protocol Control 0 181 3 7 2 2 QPIPISOCRES Intel QuickPath Interconnect Protocol Isochronous 181 3 7 2 3 CAPHDRH PCI Express Capability Header High Register 182 4 Processor Uncore Configuration 183 4 1 Processor Uncore Configuration Structure PCI Bus FFh 183 4 2 DEVICE Mappihig 2 2 reiecit rase Ta Pres adi e dafs 184 4 3 Detailed Configuration Space eee 1 185 4 4 PCI Standard Registers 1 1 lt 201 4 4 1 VID Vendor Identification Register 201 4 4 2 DID Device Identification Re
162. Status Register Sheet 1 of 2 Register PERFCTRLSTS Device 0 DMI 3 5 PCIe Function O Offset 180h Bit Attr Default Description 63 42 RO 0 Reserved 41 RO 0 Reserved 40 RV 0 Reserved 39 36 RO 0 Reserved 35 RV 0 Reserved 34 21 RV 0 Reserved Datasheet Volume 2 79 80 Processor Integrated 1 Configuration Registers Sheet 2 of 2 Register Device Function Offset PERFCTRLSTS 0 DMI 3 5 PCle 0 180h Bit Attr Default Description 20 16 RW 18h Number of Outstanding RFOs Pre Allocated Non Posted Requests for PCI Express Genl This register controls the number of outstanding inbound non posted requests 1 config memory that a Gen1 PCI Express downstream port can have for all non posted requests peer to peer or to main memory it pre allocates buffer space for The value of this parameter for the port when operating in Gen1 x8 width is obtained by multiplying this register by 2 and 4 respectively Software programs this register based on the read RFO latency to main memory A value of 1 indicates one outstanding pre allocated request 2 indicates 2 outstanding pre allocated requests and so on If software programs a value greater than the buffer size the DMA engine supports then the maximum hardware supported value is used 15 14 RO Reserved 13 8 RW 30h Number of Outstanding Pre Allocated No
163. T 234 49 8 TEST PAT ABA RAS ux 235 Datasheet Volume 2 4 0 9 TEST PAT 6 235 429 10 MC TEST PAT Rae eu KRIMI MUP Ibi 235 4 9 11 MC TEST EP SCCTL s aieo er D voi dein ok edad ext E UE 236 4 9 12 MC TEST 236 4 10 Integrated Memory Controller Channel Control Registers 237 4 10 1 MC CHANNEL 0 DIMM RESET CMD MC CHANNEL 1 DIMM RESET 0 2 237 4 10 2 MC CHANNEL 0 DIMM INIT CMD MC 1 DIMM INIT iocis Reb er pn Re bin pde 238 4 10 3 MC CHANNEL _ 0 DIMM INIT PARAMS MC CHANNEL 1 DIMM INIT PARAMS cccseee mee 239 4 10 4 MC CHANNEL 0 DIMM INIT STATUS MC CHANNEL 1 DIMM INIT STATUS 2 240 4 10 5 MC CHANNEL 0 DDR3CMD MC CHANNEL 1 01 sese enemies 241 4 10 6 MC CHANNEL 0 REFRESH THROTTLE SUPPORT MC CHANNEL 1 REFRESH THROTTLE 0 242 4 10 7 MC CHANNEL 0 MRS VALUE 0 1 MC CHANNEL 1 MRS VALUE 0 1 1 1 emere 242 4 10 8 MC CHANNEL 0 MRS VALUE 2 MC CHANNEL 1 MRS VALUE 2 nee ee eene innere 243 4 10
164. TAG initiated accesses to corresponding device configuration space 0 RWL 0 3 This bit has no impact on memory transactions forwarded through the device for example memory transactions forwarded through the Device 0 PCI to PCI bridge to the PCI Express link 4 This bit has no impact on IO transactions forwarded through the device to the PCI Express DMI link 5 This bit has no impact on messages forwarded to through the device for example messages forwarded through a PCI to PCI bridge to PCI Express link Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 4 4 9 DEVHI DE2 Device Hide 2 Register This register provides a method to hide the PCI configuration space of devices inside 110 from the host initiated configuration accesses This register does not impact J TAG initiated accesses to the corresponding device s configuration space When set for each device all PCI configuration accesses from Intel QuickPath Interconnect targeting the corresponding device s configuration space inside the Integrated I O are master aborted When clear configuration accesses targeting the device s configuration space are allowed Note If software hides Function 0 in Device 8 it needs to hide all functions within that device to comply with PCI rules Register DEVHIDE2 Device 8 Function O Offset F8h Bit Attr Default Description 31 7 RV 0000000h Reserved 6 RV Ob Reserved
165. TINGS These are the parameters used to set the early warning RX clock crossing BGF Device 4 5 Function O Offset CCh Access as a DWord Bit Attr Default Description 31 16 RO 0 Reserved ALI ENRATI 15 8 a 1 Dclk to Bclk ratio Early warning Alien Ratio setting 7 0 RO 0 Reserved Datasheet Volume 2 257 intel Processor Uncore Configuration Registers 4 10 29 MC CHANNEL O EW BGF OFFSET SETTINGS MC CHANNEL 1 EW BGF OFFSET SETTINGS These are the parameters to set the early warning RX clock crossing BGF Device 4 5 Function O Offset DOh Access as a DWord Bit Attr Default Description 31 16 RO 0 Reserved 15 8 RW 2 EVENOFFSET Early warning even offset setting ODDOFFSET Tid RW 9 Early warning odd offset setting 4 10 30 MC CHANNEL O ROUND TRIP LATENCY 258 MC CHANNEL 1 ROUND TRIP LATENCY These are the parameters to set the early warning RX clock crossing the Bubble Generator FIFO BGF used to go between different clocking domains These settings provide the gearing necessary to make that clock crossing Device 4 5 Function O Offset D4h Access as a DWord Bit Attr Default Description 31 8 RO 0 Reserved ROUND TRIP LATENCY Round trip latency for reads Units are in UCLK This register must be programmed with the appropriate time for read data to be retuned from the pads after a READ CAS is sent to the DIMMs 7 0 RW 0
166. TS DEVCTRL 48h 4Ch 50h TOLM DOh 54h D4h TOHM 58h D8h 5Ch DCh NCMEM BASE 60h EOh RESERVEDPCI Express Header space 64h E4h NCMEM LIMIT 68h E8h 6Ch 70h DEVHIDE 1 FOh 74h 78h DEVHIDE 2 F8h Notes 1 CAPPTR points to the first capability block 92 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers Table 3 8 Core Registers Device 8 Function 0 Offset 100h 1FFh 100h VTBAR 180h 104h wl VTGENCTRL 184h IIOBUSNO 108h VTISOCHCTRL 188h LMMIOL LIMIT LMMIOL BASE 10Ch VTGENCTRL2 18Ch LMMIOH LIMIT LMMIOH BASE 110h VTSTS LMMI OH BASEU LMMI OH LI MITU GMMIOL LIMIT LCFGBUS L LCFGBUS B IMIT ASE GMMIOL BASE GMMIOH LIMIT GMMIOH BASE GMMIOH BASEU GMMIOH LIMITU GCFGBUS L GCFGBUS BASE MESEGBASE MESEGMASK Datasheet Volume 2 114h 118h 11Ch 128h 12Ch 130h 134h 138h 13Ch 140h 93 Processor Integrated 1 Configuration Registers intel Table 3 9 Core Registers Device 8 Function 1 Semaphore and ScratchPad Registers Sheet 1 of 2 DID VID 000h SRI 1 080h PCISTS PCICMD 004h SR 2 084h CCR RID 008h SR 3 088h 00Ch SRI4 08Ch SR 5 090h SR 6 094h SR 7 098
167. Table 4 18 Padscan Accessible Parameters Parameters Accessible Per channel Per Rank Per Strobe 4 pin Group Receive Enable Training Yes Yes Yes RD DQ DQS Training Yes Yes Yes WR DQ DQS Training Yes Yes Yes Write Leveling Training Yes Yes Yes CS ODT Timing amp Control Yes No No Timing Delays for CMD Pins Yes No No Rank Clock Disable Yes Yes No Clock Delay Yes Yes No Transmitter Equalization Control Yes No No CKE Delay Yes Yes No Clock Slew Rate Control No No No Data Buffer Pull up Impedance No No No 1O Training Max Jitter Control No No No 10 Training Number of Samples No No No Scramble Control No No No OTD compensation Control No No No DQ Driver Compensation Control No No No There are four scan chains 1 for each channel and 1 global Table 4 19 Scan Chains Chain Length Scan Chain Subject to Change Channel 0 5261 bits Channel 1 5261 bits Global chain 539 bits Each chain is broken into smaller sections Each section is composed of N bits where N x 32 Each section is used to read write a particular parameter Each section contains N 2 data bits that is the parameter to be read written Each section has two additional bits a Mask bit and a Halt bit Datasheet Volume 2 229 Processor Uncore Configuration Registers intel The mask and halt bits are defined as shown in Table 4 20 Table 4 20 Halt and Mask Bit Usag
168. U GMMIOH BASE greater than GMMI OH LIMI TU GMMI OH LIMI T disables global MMI OH peer to peer This register is programmed once at boot time and does not change after that 9 0 RO 000h Reserved Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 4 4 23 GMMI OH BASEU Global MMI OH Base Upper Register GMMI OH BASEU Device 8 Function O Offset 12Ch Bit Attr Default Description 31 19 RO Oh This field corresponds to address A 63 51 of the global MMIOH range and is always 0 Global MMI OH Base Upper Address This field corresponds to A 50 32 of global MMIOH base An inbound or outbound memory address that satisfies global MMIOH base upper 31 0 global MMIOH base 15 10 lt A 63 26 lt global MMIOH limit 18 0 RW Oh upper 31 0 global MMIOH limit 15 10 but is outside of the local MMIOH range is treated as a remote peer to peer transaction over Intel QuickPath Interconnect link Setting GMMIOH BASEU GMMI OH BASE greater than GMMIOH LIMITU GMMIOH LIMIT disables global MMI OH peer to peer This register is programmed once at boot time and does not change after that 3 4 4 24 GMMI OH LI MI TU Global MMI OH Limit Upper Register GMMI OH LI MI TU Device 8 Function O Offset 130h Bit Attr Default Description 31 19 RO Oh This field corresponds to address A 63 51 of the global MMIOH range and is always 0 Glob
169. UEUE TAIL REG OCh 8Ch 10h 90h EXTCAP_REG INV_QUEUE_ADD_REG 14h 94h GLBSTS_REG 1Ch INV_COMP_STATUS_REG 9Ch 20h INV_COMP_EVT_CTL_REG ROOTENTRYADDR_REG 24h INV_COMP_EVT_DATA_REG A4h 28h INV COMP EVT ADDR REG A8h CTXCMD REG 2Ch COMP EVT UPRADDR REG ACh FLTSTS REG FLTEVTCTRL REG 38h B8h INTR REMAP TABLE BASE REG FLTEVTDATA REG 3Ch BCh FLTEVTADDR REG 40h FLTEVTUPRADDR REG PMEN REG PROT LOW BASE REG 68h PROT LOW MEM LIMIT REG 6Ch 70h PROT HIGH MEM BASE REG 74h 78h PROT HIGH MEM LIMIT REG 7Ch 138 Datasheet Volume 2 Processor Integrated 1 Configuration Registers intel Table 3 14 Intel VT d Memory Mapped Registers 100h 1FFh 1100h 11FFh FLTRECO FLTREC1 FLTREC2 FLTREC3 FLTREC4 FLTREC5 FLTREC6 FLTREC7 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h 12Ch 130h 134h 138h 13Ch 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h 168h 16Ch 170h 174h 178h 17Ch Datasheet Volume 2 139 Processor Integrated 1 Configuration Registers INVADDRREG 140 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 5 2 Register Description intel In the following sections Intel VT d registers 0 correspond to the non isochronous Intel VT d remap engine and registers 1 correspond to the Isochronous Inte
170. V 0 Reserved Source Identifier T9804 ROS 9 Requester ID that faulted Valid only when F bit is set GPA 63 12 ROS 0 4 K aligned GPA for the faulting transaction Valid only when F field is set 11 0 RV 0 Reserved 3 5 2 28 INVADDRREG O0 1 1 nvalidate Address Register Register Addr BAR Offset INVADDRREG O0 1 MMI O VTBAR 200h 1200h Bit Attr Default Description 63 12 RW Address ADDR 0 To request a page specific invalidation request to hardware software must first write the corresponding guest physical address to this register and then issue a page specific invalidate command through the I OTLBINV register 11 7 RV 0 Reserved RW 0 I nvalidation Hint The field provides hint to hardware to preserve or flush the respective non leaf page table entries that may be cached in hardware Software may have modified both leaf and non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request must flush both the cached leaf and nonleaf page table entries corresponding to mappings specified by ADDR and AM fields performs a domain level invalidation on non leaf entries and page selective domain level invalidation at the leaf level Software has not modified any non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request
171. VID 15 0 RO 8086h Vendor ID 8086 for Intel corporation Intel Chipset Implementation Notes For the TXT MIF LARGE CAP bit will be 1 will support having any pointers point to addresses above 4G TXT CMD LOCK BASE I ntel TXT Lock Base Command Register When this command is invoked the chipset will lock the registers listed in the table of registers and commands The command may be used by SCHECK or by SINIT to lock down the location of code or any other information that needs to be passed between SCHECK and the VMM and its loader General Behavioral Rules This is a write only register This register is only available in the Private Intel TXT configuration space Accesses to this register are done with 1 byte writes The data bits associated with this command are undefined and have no specific meaning Base TXT TXT Offset 0230h Base TXT PR Offset 0230h Bit Attr Default Description 7 0 WO Oh N A Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 6 1 11 TXT CMD UNLOCK BASE Intel TXT Unlock Base Command Register When this command is invoked the chipset unlocks the registers listed in the table of registers and commands When unlocked the registers affected by this command may be written with public cycles as well as private or Intel TXT cycles General Behavioral Rules e This is a write only register e This r
172. W 0 ASSERT_RESET When set Reset will be driven to the DIMMs RESET 0 wo 0 Reset the DIMMs Setting this bit will cause the Integrated Memory Controller DIMM Reset state machine to sequence through the reset sequence using the parameters in MC_DIMM_INIT_PARAMS Datasheet Volume 2 237 Processor Uncore Configuration Registers intel 4 10 2 CHANNEL 0 DIMM INIT CMD MC CHANNEL 1 DIMM INIT CMD Integrated Memory Controller DI MM initialization command register This register is used to sequence the channel through the physical layer training required for DDR Device 4 5 Function O Offset 54h Access as a DWord Bit Attr Default Description 31 18 RO 0 Reserved ASSERT CKE 17 WO 0 When set all CKE will be asserted Write a 0 to this bit to stop the init block from driving CKE This bit has no effect once INIT DONE is set This bit must not be asserted during initialization for 3 resume DO RCOMP When set an RCOMP will be issued to the rank specified in the RANK field DO ZQCL When set a ZQCL will be issued to the rank specified in the RANK field WRDQDQS MASK When set the Write DQ DQS training will be skipped WRLEVEL MASK When set the Write Levelization step will be skipped RDDQDQS MASK When set the Read DQ DQS step will be skipped RCVEN MASK When set the RCVEN step will be skipped RESET FIFOS 10 WO 0 When set the TX and RX FIFO pointers will be reset at the next BCL
173. WLB Oh Datasheet Volume 2 171 intel 3 6 1 17 3 6 1 18 172 Processor Integrated 1 Configuration Registers TXT MSEG BASE I ntel TXT MSEG Base Register This register holds a pointer to the base address for the TXT MSEG General Behavioral Rules This is a read write register This register is locked by TXT CMD LOCK BASE When locked it may not be changed by any writes whether they are Intel TXT private or public writes This register is available for read or write in the Public Intel TXT configuration space This register is available for read or write in the Private Intel TXT configuration space Base TXT TXT Offset 0310h Base TXT PR Offset 0310h Base TXT PB Offset 0310h Bit Attr Default Description 63 0 RWL Oh This register will be locked for access using Intel TXT public space when the TXT MSEG BASE 63 0 TXT CMD LOCK BASE is issued When locked this register is updated by private or Intel TXT writes but not public writes TXT MSEG SI ZE I ntel TXT MSEG Size Register This register holds the size in bytes of the Intel TXT MSEG region General Behavioral Rules This is a read write register This register is locked by TXT CMD LOCK BASE When locked it may not be changed by any writes whether they are Intel TXT private or public writes This register is available for read or write in the Public Intel TXT configuration spac
174. X RANK 4 7 WR 2 2 253 4 10 23MC CHANNEL 0 WAQ_ PARAMS MC CHANNEL 1 WAQ PARAMS bI 254 4 10 24MC CHANNEL 0 SCHEDULER PARAMS MC CHANNEL 1 SCHEDULER 222 255 4 10 25MC CHANNEL 0 MAI NTENANCE OPS MC CHANNEL 1 MAINTENANCE 24 255 4 10 26MC CHANNEL 0 TX BG SETTINGS 1 5 02 2 256 4 10 27MC_CHANNEL_ 0_RX_BGF_SETTINGS MC CHANNEL 1 RX 5 2 24 257 Datasheet Volume 2 9 10 4 10 28MC CHANNEL 0 EW BGF SETTINGS MC CHANNEL 1 EW BGF SETTINGS 4 10 29MC CHANNEL 0 EW BGF OFFSET SETTINGS MC CHANNEL 1 EW BGF OFFSET SETTINGS 4 10 30MC CHANNEL 0 ROUND TRIP LATENCY MC CHANNEL 1 ROUND TRIP LATENCY 4 10 31MC CHANNEL 0 PAGETABLE PARAMS1 MC CHANNEL 1 PAGETABLE PARAMS1 4 10 32MC CHANNEL 0 PAGETABLE PARAMS2 MC CHANNEL 1 PAGETABLE PARAMS2 4 10 33MC TX BG CMD DATA RATIO SETTINGS CHO MC TX BG CMD DATA RATIO SETTINGS 1 4 10 34MC TX BG CMD OFFSET SETTINGS CHO MC TX BG OFFSET SETTINGS CH1 4 10 35MC TX BG DATA OFFSET SETTINGS CHO 4 11 1 4 11 2 4 11 3 4 11 4 4 12 1 4 12 2 MC TX BG_ DATA_ OFFSET_ SETTINGS _ CH1 Integrated Memory Controller Channel Address Registers MC DOD CHO 0 M RTT MC_DOD_CH1_0 MC DOD CHI Wc
175. a of 1 MB 2 MB or 8 MB in size The TSEG area lies below IGD stolen memory The above 1 MB solutions require changes to compatible SMRAM handlers code to properly execute above 1 MB DMI Interface and PCI Express masters are not allowed to access the SMM space SMM Space Definition SMM space is defined by its addressed SMM space and its DRAM SMM space The addressed SMM space is defined as the range of bus addresses used by the processor to access SMM space DRAM SMM space is defined as the range of physical DRAM memory locations containing the SMM code SMM space can be accessed at one of three transaction address ranges Compatible High and TSEG The Compatible and TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space is the same address range Since the High SMM space is remapped the addressed and DRAM SMM space is a different address range Note that the High DRAM space is the same as the Compatible Transaction Address space Table 5 1 describes three unique address ranges Compatible Transaction Address High Transaction Address TSEG Transaction Address Transaction Address Ranges Compatible High and TSEG SMM Space Enabled Transaction Address Space DRAM Space DRAM Compatible 000A 0000h to 000 FFFFh 000A 0000h to 000 FFFFh High FEDA 0000h to FEDB FFFFh 000A 0000h to 000B FFFFh TSEG TOLM STOLEN TSEG to TOLM STOLEN TOLM STOLEN TSEG to TOLM STOLEN Datasheet V
176. a static indication of the 0 RO 0 pin and may be several clocks out of date due to the delay between the pin and the signal STATE 0 means DDR_THERM is deasserted STATE 1 means DDR_THERM is asserted Datasheet Volume 2 273 Processor Uncore Configuration Registers 274 Datasheet Volume 2 System Address Map m L 5 5 1 Note System Address Map Introduction This chapter provides a basic overview of the system address map and describes how the processor comprehends and decodes the various regions the system address map The term in this chapter refers to processor IIO in both End Point and Dual Proxy modes This chapter does not provide the full details of the platform system address space as viewed by software and also it does not provide the details of processor address decoding The supports 64 GB 36 bit of host address space and 64 KB 3 of addressable I O space There is a programmable memory address space under the 1 MB region which is divided into regions which can be individually controlled with programmable attributes such as Disable Read Write Write Only or Read Only Attribute programming is described in Section 3 5 2 This section focuses on how the memory space is partitioned and what the separate memory regions are used for 1 0 address space has simpler mapping and is explained near the end of this section The processor supports 36 bit
177. ad or write in the Public Intel TXT configuration space This register is available for read or write in the Private Intel TXT configuration space Base TXT TXT Offset 0300h Base TXT PR Offset 0300h Base TXT PB Offset 0300h Bit Attr Default Description TXT HEAP BASE 63 0 Base address of the heap This register will be locked for access using Intel TXT public space when the TXT CMD LOCK BASE is issued When locked this register is updated by private or Intel TXT writes but not public writes 63 0 RWLB Oh 3 6 1 16 TXT HEAP SI ZE Intel TXT HEAP Size Register This register indicates the size of the Intel TXT Heap General Behavioral Rules This is a read write register This register is locked by TXT CMD LOCK BASE When locked this register is updated by private or Intel TXT writes but not public writes This register is available for read or write in the Public Intel TXT configuration space This register is available for read or write in the Private Intel TXT configuration space Base TXT_TXT Offset 0308h Base TXT_PR Offset 0308h Base TXT PB Offset 0308h Bit Attr Default Description TXT HEAP SI ZE 63 0 Size of the total device space in bytes This register will be locked for access using Intel TXT public space when the TXT CMD LOCK BASE is issued When locked this register is updated by private or Intel TXT writes but not public writes 63 0 R
178. ade visible if the conditions are right to access SMM space otherwise the access is forwarded to HI Only SMM space between A0000 and BFFFF is supported so this field is hardwired to 010 7 0 RO 0 Reserved Datasheet Volume 2 Processor Uncore Configuration Registers 4 5 5 4 5 6 SAD PCIEXBAR Global register for PCI ExpressXBAR address space Device 0 Function 1 Offset 50h Access as a QWord Bit Attr Default Description 63 40 RV 0 Reserved ADDRESS 39 20 RW 0 Base address of PCI ExpressXBAR Must be naturally aligned to size low order bits are ignored 19 4 RO 0 Reserved SIZE Size of the PCI ExpressXBAR address space MAX bus number 000 256 MB 001 Reserved 010 Reserved Bek RW 8 011 Reserved 100 Reserved 101 Reserved 110 64 MB 111 128 MB ENABLE 0 RW 0 Enable for PCI ExpressXBAR address space Editing size should not be done without also enabling range SAD TPCIEXBAR Global register for trusted PCIEXBAR address space Bus number comes from PCI EXBAR Device 0 Function 1 Offset 58h Access as a QWord Bit Type Default Description 63 40 RV 0 Reserved ADDRESS 39 20 RW 0 Base address of PCIEXBAR Must be naturally aligned to size low order bits are ignored 19 1 RO 0 Reserved ENABLE 0 RW 0 Enable for PCIEXBAR address space Datasheet Volume 2 213 intel 4 5 7 4 5 8 214 Proce
179. al MMI OH Limit Upper Address This field corresponds to A 51 32 of global MMI OH limit An inbound or outbound memory address that satisfies global MMIOH base upper 31 0 global MMIOH base 15 10 lt A 63 26 lt global MMIOH limit 8 0 Oh upper 31 0 global MMIOH limit 15 10 but is outside of the local 18 RW range is treated as a remote peer to peer transaction over Intel QuickPath Interconnect link Setting GMMIOH BASEU GMMI OH BASE greater than GMMI OH LI MI TU GMMI OH LIMIT disables global MMI OH peer to peer This register is programmed once at boot time and does not change after that 3 4 4 25 GCFGBUS BASE Global Configuration Bus Number Base Register Register GCFGBUS BASE Device 8 Function O Offset 134h Bit Attr Default Description Global Configuration Bus Number Base This field corresponds to base bus number of bus number range that spans all 7 0 RW Oh 11Os in a partition An inbound or outbound configuration tx that satisfies Global Bus Number Base 7 0 x Bus Number 7 0 x Global Bus Number Limit 7 0 but is outside of the local bus number range is treated as a remote peer to peer transaction over Intel QuickPath Interconnect link Datasheet Volume 2 123 intel 3 4 4 26 3 4 4 27 3 4 4 28 124 Processor Integrated 1 Configuration Registers GCFGBUS LI MI T Global Configuration Bus Number Limit Register Register GCF
180. am PCI Express memory writes reads 1 writes reads and configuration reads and writes as unsupported requests and follow the rules for handling unsupported requests This behavior is also true towards transactions that are already pending in the Integrated 1 0 root port s internal queues when the BME bit is turned off 1 Enables the PCI Express ports to generate forward memory configuration O read write requests Datasheet Volume 2 37 Processor Integrated 1 Configuration Registers Sheet 2 of 2 Register PCICMD Device 3 5 PCle 0 Function Offset 04h Bit Attr Default Description Memory Space Enable MSE 0 Disables a PCI Express port s memory range registers including the CSR range registers to be decoded as valid target addresses for transactions from primary side 1 RW 0 1 Enables a PCI Express port s memory range registers to be decoded as valid target addresses for transactions from primary side Note that if a PCI Express port s MSE bit is clear that port can still be target of any memory transaction if subtractive decoding is enabled on that port 10 Space Enable I OSE Applies to PCI Express ports 0 Disables the 1 address range defined the IOBASE and I OLIM registers of the PCI to PCI bridge header for target decode from primary side 0 RW 0 1 Enables the 1 0 address range defined the IOBASE and IOLIM registers of the PCI to PCI br
181. and save all device SRID values by reading processor device RID registers before setting the SRID CRID register select flip flop The RID values for all devices and functions in the processor are controlled by the SRI D CRID register select flip flop thus writing the key value 69h to the RID register in Bus 0 Device 0 Function 0 sets all processor device RID registers to return the CRID Writing to the RID register of other devices has no effect on the SRID CRID register select flip flop Only a power good reset can change the RID selection back to SRID Datasheet Volume 2 Processor Uncore Configuration Registers 4 4 3 1 4 4 3 2 Device 0 Function 0 1 Offset 08h Device 2 Function 0 1 Offset 08h Device 3 Function 0 1 4 Offset 08h Device 4 5 Function 0 3 Offset 08h Bit Attr Default Description Minor Revision See Steppings which required all masks be regenerated RO descripti amp i i escription Refer to the Intel Core 17 800 i5 700 Desktop Processor Series Specification Update for the value of the Revision ID Register Minor Revision Identification Number S Increment for each steppings which do not require masks to be 3 0 RO regenerated description Refer to the Intel Core 17 800 and 15 700 Processor Specification Update for the value of the Revision ID Register 7 4 Stepping Revision I D SRI D This register contains the revision
182. ank 1 to always be asserted 0 RW 0 FORCE_ODTO Force ODT for Rank 0 to always be asserted 4 10 19 MC CHANNEL O0 MATRIX RANK RD MC CHANNEL 1 ODT MATRIX RANK 0 3 RD This register contains the ODT activation matrix for RANKS 0 to 3 for Reads 252 Device 4 5 Function 0 Offset A4h Access as a DWord Bit Attr Default Description 31 24 RW 1 ODT RD3 ODT values for all 8 Ranks when reading Rank 3 23 16 RW 1 ODT_RD2 ODT values for all 8 Ranks when reading Rank 2 15 8 RW 4 ODT_RD1 ODT values for all 8 Ranks when reading Rank 1 7 0 RW 4 ODT RDO ODT values for all 8 Ranks when reading Rank 0 Datasheet Volume 2 Processor Uncore Configuration Registers m 4 10 20 4 10 21 4 10 22 intel MC CHANNEL 0 ODT MATRIX RANK 4 7 RD MC CHANNEL 1 ODT MATRIX RANK 4 7 RD This register contains the ODT activation matrix for RANKS 4 to 7 for Reads Device 4 5 Function O Offset A8h Access as a DWord Bit Attr Default Description 31 24 RW 1 ODT RD3 ODT values for all 8 Ranks when reading Rank 7 23 16 RW 1 ODT RD2 ODT values for all 8 Ranks when reading Rank 6 15 8 RW 4 ODT RD1 ODT values for all 8 Ranks when reading Rank 5 7 0 RW 4 ODT RDO ODT values for all 8 Ranks when reading Rank 4 MC CHANNEL 0 ODT MATRIX RANK 0 3 WR MC CHANNEL 1 ODT MATRIX RANK 0 3 WR This register contains the ODT activation matrix for RANKS 0 to 3 for Writ
183. are Writes to this bit have no effect wo Write Only The register bit is not implemented as a bit The write causes some hardware event to take place RWO Read Write Once These bits can be read by software After reset these bits can only be written by software once after which the bits becomes Read Only RW Read Write A register bit with this attribute can be read and written by software RC Read Clear The bit or bits can be read by software but the act of reading causes the value to be cleared Read Clear Write A register bit with this attribute will get cleared after the read The RCW R register bit can be written RWIC Read Write 1 Clear A register bit with this attribute can be read or cleared by software In order to clear this bit a one must be written to it Writing a zero will have no effect RWOC Read Write O Clear A register bit with this attribute can be read or cleared by software In order to clear this bit a zero must be written to it Writing a one will have no effect RO Sticky These bits can only be read by software writes have no effect The value of ROS the bits is determined by the hardware only These bits are only re initialized to their default value by a PWRGOOD reset RWS R W Sticky These bits can be read and written by software These bits are only re initialized to their default value by a PWRGOOD reset Read Write 1 Set A register bit can be either read or set
184. are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 35 14 RO 0 Reserved PAM1_HIENABLE 0C4000h OC7FFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from 0C4000h to OC7FFFh 13 12 RW 0 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 11 10 RO 0 Reserved PAM1_LOENABLE 0 0000 OC3FFFh Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0C0000h to OC3FFFh 9 8 RW 0 00 DRAM Disabled All accesses directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM 7 6 RO 0 Reserved PAMO_HIENABLE OF0000h OFFFFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OFOOOOh to OFFFFFh 5 4 RW 0 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are
185. as no effect on J TAG initiated accesses to corresponding device s configuration space 6 RWLB 0 3 This bit has no impact on memory transactions targeting the device or memory transactions forwarded through the device 4 This bit has no impact on IO transactions forwarded through the device to the PCI Express DMI link 5 This bit has no impact on messages forwarded to through the device for example messages forwarded through a PCI to PCI bridge to PCI Express link Hide Dev5 When set hide Device 5 1 This bit has no impact on any configuration transactions that target the secondary side of a device that is a PCI to PCI bridge 2 This bit has no effect on J TAG initiated accesses to corresponding device s configuration space 5 RWLB 0 3 This bit has no impact on memory transactions targeting the device or memory transactions forwarded through the device 4 This bit has no impact on IO transactions forwarded through the device to the PCI Express DMI link 5 This bit has no impact on messages forwarded to through the device for example messages forwarded through a PCI to PCI bridge to PCI Express link Hide Dev4 When set hide Device 4 1 This bit has no impact on any configuration transactions that target the secondary side of the PCI to PCI bridge 2 This bit has no effect on J TAG initiated accesses to corresponding device s configuration space 3 This bit has no impact on memory transactions forwarded 4 RWL 0 th
186. aster may only issue single L1 requests while the slave can only issue single L1 Ack or 11 NAck responses for the corresponding request 20 RW L1 ENABLE Enables L1 mode at the transmitter This bit should be ANDed with the receive L1 capability bit received during parameter exchange to determine if a transmitter is allowed to enter into L1 This is NOT a bit that determines the capability of a device at the transmitter This bit should be ANDed with the receive L1 capability bit received during parameter exchange to determine if a transmitter is allowed to enter into L1 This is NOT a bit that determines the capability of a device 19 RO Reserved 18 RW LOS ENABLE Enables LOs mode at the transmitter This bit should be ANDed with the receive LOs capability bit received during parameter exchange to determine if a transmitter is allowed to enter into LOs This is NOT a bit that determines the capability of a device at the transmitter This bit should be ANDed with the receive LOs capability bit received during parameter exchange to determine if a transmitter is allowed to enter into LOs This is NOT a bit that determines the capability of a device 17 RWST STALL RDY FOR NORMAL Link Layer Initialization stall on next initialization Sticky 0 Disable 1 Enable stall initialization until this bit is cleared 16 RWST STALL_RDY_FOR_INIT Link Layer Initialization stall on next initializati
187. available physical limits of the system Datasheet Volume 2 49 intel Processor Integrated 1 Configuration Registers 3 3 3 27 BCTRL Bridge Control Register The Bridge Control register provides additional control for the secondary interface that is PCI Express as well as some bits that affect the overall behavior of the virtual PCI to PCI bridge embedded within the Integrated 1 0 for example VGA compatible address range mapping Sheet 1 of 2 Register Device Function Offset BCTRL 3 5 PCIe 0 3Eh Bit Attr Default Description 15 12 RO Oh Reserved 11 Discard Timer SERR Status RO 0 Not applicable to PCI Express This bit is hardwired to 0 10 Discard Timer Status RO 9 Not applicable to PCI Express This bit is hardwired to 0 Secondary Discard Timer RD 9 Not applicable to PCI Express This bit is hardwired to 0 Primary Discard Timer RO 9 Not applicable to PCI Express This bit is hardwired to 0 Fast Back to Back Enable RO 0 Not applicable to PCI Express This bit is hardwired to 0 Secondary Bus Reset 0 No reset happens on the PCI Express port 1 Setting this bit triggers hot reset on the link for the corresponding PCI Express port and the PCI Express hierarchy domain subordinate to the port This sends the LTSSM into the Training or Link Control Reset state which necessarily implies a reset to the downstream dev
188. bled Enable Disable 1 1 1 Disabled Enable Enable 288 Datasheet Volume 2 System Address Map L 5 5 4 Table 5 3 5 5 5 5 5 6 5 5 7 SMM Control Combinations The G_SMRAME bit provides a global enable for all SMM memory The D_OPEN bit allows software to write to the SMM ranges without being in SMM mode BIOS software can use this bit to initialize SMM code at powerup The D_LCK bit limits the SMM range access to only SMM mode accesses The D_CLS bit causes SMM both CSEG and TSEG data accesses to be forwarded to the DMI Interface or PCI Express The SMM software can use this bit to write to video memory while running SMM code out of DRAM SMM Control Table G_SMRAME D_LCK D_CLS D_OPEN nsu he 7 0 x X x x Disable Disable 1 0 X 0 0 Disable Disable 1 0 0 0 1 Enable Enable 1 0 0 1 x Enable Enable 1 0 1 0 1 Enable Disable 1 0 1 i x Invalid Invalid 1 1 X x 0 Disable Disable 1 1 0 x 1 Enable Enable 1 1 1 x 1 Enable Disable SMM Space Decode and Transaction Handling Only the processor is allowed to access SMM space PCI Express and DMI Interface originated transactions are not allowed to SMM space Processor WB Transaction to an Enabled SMM Address Space Processor Writeback transactions REQa 1 0 to enabled SMM Address Space must be written to the associated SMM DRAM even though D_OPEN 0 and the transaction is not performed in SMM mode This ensures
189. by software In order to set RW1S this bit a one must be written to it Writing a zero to this bit has no effect Hardware will clear this bit Read Write 0 Set A register bit can be either read or set by software In order to set RWOS this bit a zero must be written to it Writing a one to this bit has no effect Hardware will clear this bit Read Write Lock A register bit with this attribute can be read or written by software RWL Hardware or a configuration bit can lock the bit and prevent it from being updated Datasheet Volume 2 17 18 Introduction Term Description Read Write Once A register bit with this attribute can be written to only once after power up After the first write the bit becomes read only This attribute is applied on a bit RWO by bit basis For example if the RWO attribute is applied to a 2 bit field and only one bit is written then the written bit cannot be rewritten unless reset The unwritten bit of the field may still be written once This is special case of RWL RWDS RW and Sticky Re initialized to default value only with POWERGOOD reset Value written will take effect on the next Link layer init Read Restricted Write This bit can be read and written by software However only RRW supported values will be written Writes of non supported values will have no effect L Lock A register bit with this attribute becomes Read Only after a lock bit is s
190. by the TXT CMD UNLOCK MEMCONFIG command 11 RO 0 0 Indicates that memory configuration checking has not been performed This is the default state after PCI reset This bit is also set to O after the chipset has accepted the TXT CMD UNLOCK MEM CONFIG command 0 Indicates that memory configuration checking has been performed This bit is set to one when the chipset accepts the TXT CMD MEM CONFIG CHECKED TXT command 10 8 RV 0 Reserved TXT PRI VATE OPEN STS 7 RO 0 This bit will be set to 1 when the TXT CMD OPEN PRIVATE is performed This bit cleared by the TXT CMD CLOSE PRIVATE or by a system reset TXT MEM CONFI G LOCK STS This bit will be set to 1 when the memory configuration has been locked This 6 RO 0 bit is cleared by TXT CMD UNLOCK MEMCONFIG or by a system reset When this bit is set registers VTCTRL D20 F0 7Ch and VTBAR D20 F0 78h will be locked And these registers will be unlocked when this bit is clear TXT BASE LOCKED STS This bit will be set to 1 when the TXT LOCK BASE command is issued This bit is cleared by TXT UNLOCK BASE or by a system reset 5 RO 0 When this bit is set TXT space registers BASE TXT SIZE TXT MSEG BASE TXT MSEG SIZE TXT SCRATCHPADO and TXT_SCRATCHPAD1 will be locked And these registers will be unlocked when this bit is clear 4 2 RV Oh Reserved SEXIT DONE STS 1 RO 1 This bit is set when all of the bits in the TXT THREADS J OIN register are clear 0 using TXT JOINS C
191. ccess as a DWord Bit Type Default Description 31 17 RO 0 Reserved INTERRUPT_SELECT_NMI NMI Enable 16 RW 0 This bit is set to enable NMI signaling Clear to disable NMI signaling If both NMI and SMI enable bits are set then only SMI is sent INTERRUPT SELECT SMI SMI Enable 15 RW 0 This bit is set to enable SMI signaling Clear to disable SMI signaling If both NMI and SMI enable bits are set then only SMI is sent 14 0 RW 0 Reserved Datasheet Volume 2 221 intel 4 7 4 MC_ STATUS MC Primary Status register Processor Uncore Configuration Registers Device 3 Function 0 Offset 4Ch Access as a DWord Bit Attr Default Description 31 17 RO 0 Reserved 4 RO 1 Reserved RO 0 Reserved 2 RO 0 Reserved CHANNEL1_ DISABLED Channel 1 is disabled 1 RO 0 This can be factory configured or if Init done is written without the channel_active being set Clocks in the channel will be disabled when this bit is set CHANNELO DISABLED Channel 0 is disabled 0 RO 0 This can be factory configured or if Init done is written without the channel_active being set Clocks in the channel will be disabled when this bit is set 4 7 5 222 MC_RESET_CONTROL DIMM Reset enabling controls Device 3 Function 0 Offset 5Ch Access as a DWord Bit Attr Default Description 31 1 RO 0 Reserved BIOS RESET ENABLE 0 WO 0 When set MC takes over control o
192. ce the command is complete INIT CMPLT 8 RO 0 This bit is cleared when a new training command is issued It is set once the sequence is complete regardless of whether all steps passed or not ZQCL CMPLT 7 RO 0 When set indicates that ZQCL command has completed This bit is cleared by hardware on command issuance and set once the command is complete WR DQ DQS PASS 6 RO 0 Set after a training command when the Write DQ DQS training step passes The bit is cleared by hardware when a new training command is sent WR LEVEL PASS 5 RO 0 Set after a training command when the write leveling training step passes The bit is cleared by hardware when a new training command is sent RD RCVEN PASS 4 RO 0 Set after a training command when the Read Receive Enable training step passes The bit is cleared by hardware when a new training command is sent RD DQ DQS PASS 3 RO 0 Set after a training command when the Read DQ DQS training step passes The bit is cleared by hardware when a new training command is sent PHYFSMSTATE The current state of the top level training FSM 000 IDLE 2 0 RO 0 001 RD DQ DQS 010 RcvEn Bitlock 011 Write Level 100 2 WR DQ DQS Datasheet Volume 2 Processor Uncore Configuration Registers 4 10 5 intel MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD DDR3 Configuration Command This register is used to issue commands to the DIMMs such as MRS commands The register is used by setting one of the VALID bits along wi
193. ceeds this threshold a more aggressive page close interval smaller is selected STAKECOUNTER Upper 9 MSBs of a 12 bit counter This counter adapts the interval 8 0 RW 0 between assertions of the page close flag For a less aggressive page close the length of the count interval is increased and vice versa for a more aggressive page close policy Datasheet Volume 2 259 L D Processor Uncore Configuration Registers 4 10 33 4 10 34 4 10 35 260 MC TX BG CMD DATA RATIO SETTINGS CHO MC TX BG CMD DATA RATIO SETTINGS 1 Channel Bubble Generator ratios for CMD and DATA Device 4 5 Function O Offset EOh Access as a DWord Bit Attr Default Description 31 16 RO 0 Reserved 15 8 RW 0 ALI ENRATI O DCLK to BCLK ratio 7 0 RW 0 NATI VERATI O UCLK to BCLK ratio MC TX BG CMD OFFSET SETTINGS CHO MC TX BG CMD OFFSET SETTINGS 1 Integrated Memory Controller Channel Bubble Generator Offsets for CMD FIFO The Data command FIFOs share the settings for channel 0 across all three channels The register in Channel 0 must be programmed for all configurations Device 4 5 Function O Offset E4h Access as a DWord Bit Attr Default Description 31 10 RO 0 Reserved 9 8 RW 0 PTROFFSET pointer offset 7 0 RW 0 BGOFFSET BG offset MC TX BG DATA OFFSET SETTINGS CHO MC TX BG DATA OFFSET SETTINGS 1 Integrated Memory Con
194. ch rank participates in WAY n If MC CLOSEDPAGE 1 this field defines the DRAM rank selected when MemoryAddress 7 6 n If 3 0 RW 0 MC CLOSEDPAGE 0 this field defines which rank is selected when MemoryAddress 13 12 n is the instantiation of the register This field is organized by physical rank Bits 3 2 are the encoded DIMM ID slot Bits 1 0 are the rank within that DIMM 267 Processor Uncore Configuration Registers intel 4 13 Memory Thermal Control 4 13 1 MC THERMAL CONTROLO MC THERMAL CONTROLI1 Controls for the Integrated Memory Controller thermal throttle logic Device 4 5 Function 3 Offset 48h Access as a DWord Bit Attr Default Description 31 3 RO 0 Reserved APPLY SAFE 2 RW 1 Enable the application of safe values while MC THERMAL PARAMS B SAFE INTERVAL is exceeded THROTTLE MODE Selects throttling mode 0 Throttle disabled 1 Open Loop Throttle when Virtual Temperature is greater than 1 0 RW 0 MC THROTTLE OFFSET 2 Closed Loop Throttle when MC CLOSED LOOP THROTTILE NOW is set 3 Closed Loop Throttle when MC DDR THERM COMMAND THROTTLE is set and the PM EXT 5 is asserted OR OLTT will be implemented Condition 1 4 13 2 MC THERMAL STATUSO MC THERMAL STATUS1 Status registers for the thermal throttling logic Device 4 5 Function 3 Offset 4Ch Access as a DWord Bit Attr Default Description 31
195. cond step is the fine source decode towards an individual socket using the Intel QuickPath I nterconnect memory source address decoders A sub region within one of the two coarse regions can be marked as non coherent VGA memory address would overlap one of the two main memory ranges and decoder is cognizant of that and steers these addresses towards the VGA device of the system e Inbound peer to peer decoding also happens in two steps The first step involves decoding peer to peer not crossing Intel QuickPath Interconnect local peer to peer The second step involves actual target decoding for local peer to peer if transaction targets another device south of the IIO A pair of base limit registers are provided for to positively decode local peer to peer transactions On the processor the global pair must be set to be the same as local so the second pair of base limit registers do not add any functionality Note The processor supports peer 2 peer writes interrupt messages for legacy interrupt and GPE Please see section on Platform Interrupts in the Interrupt Chapter for more details The processor does not support peer 2 peer reads Fixed VGA memory addresses A0000h BFFFFh are always peer to peer addresses and would reside outside of the global peer to peer memory address ranges mentioned above The VGA memory addresses also overlap one of the system memory address regions but IIO always
196. d Setting the memory limit less than memory base disables the 32 bit memory range altogether In general the memory base and limit registers will not be programmed by software without clearing the MSE bit first MLIM Memory Limit Register MLIM Device 3 5 PCle Function 0 Offset 22h Bit Attr Default Description Memory Limit Address 15 4 RW Oh This field corresponds to A 31 20 of the memory address that corresponds to the upper limit of the range of memory accesses that will be passed by the PCI Express bridge 3 0 RO Oh Reserved by PCI SIG Datasheet Volume 2 47 m t D Processor Integrated 1 Configuration Registers 3 3 3 23 Note 3 3 3 24 48 PMBASE Prefetchable Memory Base Register The Prefetchable Memory Base and Memory Limit registers define a memory mapped I O prefetchable address range 64 bit addresses which is used by the PCI Express bridge to determine when to forward memory transactions based on the following formula PREFETCH MEMORY BASE UPPER PREFETCH MEMORY BASE x A 63 20 PREFETCH MEMORY LIMIT UPPER PREFETCH MEMORY LIMIT The upper 12 bits of both the Prefetchable Memory Base and Memory Limit registers are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit addresses The bottom of the defined memory address range will be aligned to a 1 MB boundary and the top of the defined memory address rang
197. d 1 0 devices Hardwired to 0 Memory Write and I nvalidate Enable 4 RO 0 Not applicable to Processor Integrated 1 0 devices Hardwired to 0 Special Cycle Enable 3 RO 8 Not applicable Hardwired to 0 Bus Master Enable BME 2 RO 0 For Device 0 DMI this bit is hardwired to 0 since the DMI is not a PCI bridge Hardware should ignore the functionality of this bit Memory Space Enable MSE 1 RO 0 For Device 0 DMI this bit is hardwired to 0 since the DMI is not a PCI bridge IO Space Enable I OSE 0 RO 0 For Device 0 DMI this bit is hardwired to 0 since the DMI is not a PCI bridge 36 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers Sheet 1 of 2 Register PCICMD Device 3 5 PCle Function 0 Offset 04h Bit Attr Default Description 15 11 RV 00h Reserved by PCI SIG 10 RW 0 Legacy Interrupt Mode Enable Disable 9 RO 0 Fast Back to Back Enable Not applicable to PCI Express and is hardwired to 0 SERR Enable For PCI Express DMI ports this field enables notifying the internal core error logic of occurrence of an uncorrectable error fatal or non fatal at the port The internal core error logic of then decides if how to escalate the error further pins message and so forth This bit also controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL messages received from the port to
198. d command lines will float to save power when commands are not being sent out PRECASRDTHRESHOLD 10 6 RW 7 Threshold above which Medium Low Priority reads can PRE CAS write requests DISABLE ISOC RESERVE 5 RW 0 When set to 1 this bit will prevent any RBC s from being reserved for ISOC 4 RW 0 ENABLES3N Enable Timing 3 RW 0 ENABLE2N Enable 2n Timing 2 0 RW 0 PRI ORI TYCOUNTER Upper 3 MSB of 8 bit priority time out counter MC CHANNEL 0 MAINTENANCE OPS MC CHANNEL 1 MAINTENANCE OPS This register enables various maintenance operations such as Refreshes ZQ RCOMP and so forth Device 4 5 Function O Offset BCh Access as a DWord Bit Attr Default Description 31 13 RO 0 Reserved MAINT CNTR 12 0 RW 0 Value to be loaded in the maintenance counter This counter sequences the rate to Refreshes ZQ RCOMP It should be set to 7800 DCLKperiodl nNS The value of 0 is invalid Datasheet Volume 2 255 m t D Processor Uncore Configuration Registers 4 10 26 256 MC CHANNEL O TX BG SETTINGS MC CHANNEL 1 TX BG SETTINGS These are the parameters used to set the Start Scheduler for TX clock crossing This is used to send commands to the DI MMs The NATIVE RATIO is UCLK multiplier of BCLK U ALIEN RATIO is DCLK multiplier of BCLK D PIPE DEPTH 8 UCLK design dependent variable MIN SEP DELAY 670 ps design dependent variable Internally this is logic delay of FIFO clock skew b
199. d in this register regardless of whether error reporting is enabled or not 0 RW1C 0 the PCI Express Device Control register 0 No Fatal errors detected 1 Fatal errors detected Datasheet Volume 2 61 3 62 intel Processor Integrated 1 Configuration Registers 3 4 19 LNKCAP PCI Express Link Capabilities Register The Link Capabilities register identifies the PCI Express specific link capabilities Sheet 1 of 2 Register Device Function Offset LNKCAP 0 DMI 3 5 PCIe 0 9Ch Bit Attr Default Description 31 24 Port Number RWO 0 This field indicates the PCI Express port number for the link and is initialized by software BIOS 23 22 RV Oh Reserved 21 Link Bandwidth Notification Capability RO 1 A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms 20 Data Link Layer Link Active Reporting Capable RO 1 supports reporting status of the data link layer so software knows when it can enumerate a device on the link or otherwise know the status of the link 19 Surprise Down Error Reporting Capable RO 1 supports reporting a surprise down error condition 18 Clock Power Management RO 0 Does not apply to IIO 17 15 L1 Exit Latency This field indicates the L1 exit latency for the given PCI Express port It indicates the length of time this
200. defined using fence registers are not supported from DMI or the PEG port GMADR read accesses are not supported from either DMI or PEG In the following sections it is assumed that all of the compatibility memory ranges reside on the DMI Interface The exception to this rule is VGA ranges which may be mapped to PCI Express DMI or to the internal graphics device IGD In the absence of more specific references cycle descriptions referencing PCI should be interpreted as the DMI Interface PCI while cycle descriptions referencing PCI Express or IGD are related to the PCI Express bus or the internal graphics device respectively The Processor does not remap APIC or any other memory spaces above TOLM The TOLM register is set to the appropriate value by BIOS The reclaim base reclaim limit registers remap logical accesses bound for addresses above 4 GB onto physical addresses that fall within DRAM Memory Address Space Figure 5 1 shows the system memory address space There are three basic regions of memory address space in the system address below 1 MB address between 1 MB and 4 GB and address above 4 GB These regions are described in the following sections Throughout this section there will be references to subtractive decode port It refers to the port of that is attached to a legacy DMI This port is also the recipient of all addresses that are not positively decoded towards any PCIE device or towards memory Refer t
201. description Integrated 1 supports both 2 5 Gbps and 5 Gbps speeds 3 0 RWO Dev 3 5 See n description 0001b 2 5 GT s support only Dev 0 0001b 0010b 2 5 GT s and 5 0GT s support Datasheet Volume 2 63 intel Processor Integrated 1 Configuration Registers 3 3 4 20 LNKCON PCI Express Link Control Register Device 0 The PCI Express Link Control register controls the PCI Express Link specific parameters Register LNKCON Device 0 DMI Function 0 Offset AOh Bit Attr Default Description 15 12 RV 0 Reserved Link Autonomous Bandwidth I nterrupt Enable 11 RO 0 When set to 1 this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set Link Bandwidth Management I nterrupt Enable 10 RO 0 When set to 1 this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set Hardware Autonomous Width Disable 9 RO 0 When set this bit disables hardware from changing the link width for reasons other than attempting to correct unreliable link operation 8 RO 0 Enable Clock Power Management N A to Integrated 1 0 Extended Sync 7 RO 0 When set to 1 this bit forces the transmission of additional ordered sets when exiting LOs and when in recovery See the latest PCI Express Base Specification for details 6 RO 0 Common Clock Configuration Integrated I
202. dless of whether MSI is enabled at the root port or not When clear PMEGPE message generation for PM events 2 RW 0 is disabled and OS can choose to generate MSI interrupts for delivering PM events by setting the MSI enable bit in root ports This bit does not apply to the DMI ports Clearing this bit from being 1 schedules a Deassert PMEGPE event on behalf of the root port provided there was any previous Assert PMEGPE message that was sent without an associated Deassert message 82 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers m Sheet 3 of 3 Register MISCCTRLSTS Device 0 DMI 3 5 PCIe Function O Offset 188h Bit Attr Default Description Inbound Configuration Enable 1 RWO Oh When clear all inbound configuration transactions are sent a UR response by the receiving PCI Express port When set inbound configs are allowed Note Enabling is only for debug purposes Dev attr Dev val Set Host Bridge Class Code 0 0 RO 0 1 When this bit is set the class code register indicates Host Bridge else RW else 0 3 3 5 5 CTOCTRL Completion Time out Control Register Register CTOCTRL Device 0 DMI 3 5 PCle Function 0 Offset 1EOh Bit Attr Default Description 31 10 RV 00 Reserved XP to PCle Time out Select within 17 s to 64 s Range When OS selects a time out range of 17 s to 64 s for Windows XP that affect NP tx issued to t
203. dress Decode registers for the Integrated Memory Controller and resides at DID of 2C99h Device 3 Function 4 contains the test registers for the Integrated Memory Controller and resides at DID of 2C9C Device 4 Integrated Memory Controller Channel 0 Device 4 Function 0 contains the control registers for Integrated Memory Controller Channel 0 and resides at DID of 2CAOh Device 4 Function 1 contains the address registers for Integrated Memory Controller Channel 0 and resides at DID of 2CA1h Device 4 Function 2 contains the rank registers for Integrated Memory Controller Channel 0 and resides at DID of 2CA2h Device 4 Function 3 contains the thermal control registers for Integrated Memory Controller Channel 0 and resides at DID of 2CA3h Device 5 Integrated Memory Controller Channel 1 Device 5 Function 0 contains the control registers for Integrated Memory Controller Channel 1 and resides at DID of 2CA8h Device 5 Function 1 contains the address registers for Integrated Memory Controller Channel 1 and resides at DID of 2CA9h Device 5 Function 2 contains the rank registers for Integrated Memory Controller Channel 1 and resides at DID of 2CAAh Device 5 Function 3 contains the thermal control registers for Integrated Memory Controller Channel 1 and resides at DID of 2CABh Datasheet Volume 2 Configuration Process and Registers 2 2 Configuration Mechanisms The processor is the originator of configuration cycles Internal to th
204. dress with configuration space of this device where the capability register resides This bit must be set for a PCI Express device or the VSEC capability If no capability structures are implemented this bit is hardwired to 0 Interrupt Status If this device generates an interrupt then this read only bit reflects the state of the interrupt in the device function Only when the Interrupt Disable bit in 3 RO 0 the command register is 0 and this Interrupt Status bit is 1 will the device s function s INTx signal be asserted Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit If this device does not generate interrupts this bit is not implemented RO and reads returns 0 2 0 RO 0 Reserved 4 5 SAD System Address Decoder Registers 4 5 1 SAD PAMO123 Register for legacy device 0 function 0 90h 93h address space Device 0 Function 1 Offset 40h Access as a DWord Bit Attr Default Description 31 29 RO 0 Reserved HIENABLE 004000 0D7FFFh Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to 0D7FFFh 29 28 RW 0 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are forwarded to DMI 10 Write Only All writes are send to DRAM Reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM
205. e Mask Halt Function 0 X Serial data is not loaded into the shadow register 1 0 Serial data is loaded into shadow register but will be overwritten 1 1 Serial data is loaded into shadow register and held until halt is cleared This is the most commonly used setting There are 3 registers defined for Padscan usage Table 4 21 Padscan Registers Register Name Description MC_TEST_EP_SCCTL Scan chain control register MC_TEST_EP_SCD Scan chain data register MC_TEST_LTRCON Scan chain select register Figure 4 1 Padscan Accessibility Mechanism Control Register 32 bit Payload Wr Index 29 0 Rd Data Register FSM Shadow Register Shift Capture Update Reset Index Index n Index 0 Pad Scan Chain A read operation is performed by writing the index Chain length Offset 38 length of section 1 of the section to be read and read bit into the control register The appropriate scan chain is selected in the scan chain select register The read is complete when the read bit in the control register is cleared by the Integrated Memory Controller The control register must be read after the read write command is issued to guarantee the read write command completes When the read data is complete the contents of the data register will be valid Note that reads will provide a total of 32 bit
206. e This register is available for read or write in the Private Intel TXT configuration space Base TXT TXT Offset 0318h Base TXT PR Offset 0318h Base TXT PB Offset 0318h Bit Attr Default Description 63 0 RWL Oh This register will be locked for access using Intel TXT public space when the TXT MSEG SI ZE 63 0 TXT CMD LOCK BASE is issued When locked this register is updated by private or Intel TXT writes but not public writes Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 6 1 19 TXT SCRATCHPADO I ntel TXT Scratch Pad Register Intel TXT Scratch Pad Register General Behavioral Rules This is a read write register This register is locked by TXT CMD LOCK BASE When locked this register is updated by private or Intel TXT writes but not public writes This register is available for read or write the Public and Private Intel TXT configuration space Base TXT Offset 0320h Base TXT PR Offset 0320h Base TXT PB Offset 0320h Bit Attr Default Description TXT SCRATCHPADO 63 0 63 0 RWLB Oh This register will be locked for access using Intel TXT public space when the TXT CMD LOCK BASE is issued When locked this register is updated by private or Intel TXT writes but not public writes 3 6 1 20 TXT SCRATCHPAD1 Intel TXT Scratch Pad Register 1 Intel TXT Scratch Pad Register General Behavioral
207. e Address 154 3 5 2 27 FLTREC 10 7 0 Fault Record Register 155 3 5 2 28 INVADDRREG 0 1 Invalidate Address Register 155 3 5 2 29 IOTLBINV 0 1 I OTLB Invalidate 156 3 6 Intel Trusted Execution Technology Intel TXT Register 157 251 Intel TXT Space lt 162 3 61 5 5 1 TXT Status Register oo enatis 162 3 6 1 2 TXT ESTS Intel TXT Error Status 164 3 6 1 3 TXT THREADS EXISTS Intel TXT Thread Exists Register 165 3 6 1 4 TXT THREADS J OI N Intel TXT Threads Join Register 165 3 6 1 5 TXT ERRORCODE Intel TXT Error Code Register 166 3 6 1 6 TXT CMD RESET Intel TXT System Reset Command Register 166 3 6 1 7 TXT CMD CLOSE_PRIVATE Intel TXT Close Private Command ace T 167 3 6 1 8 167 3 6 1 9 TXT ID Intel TXT Identifier 168 3 6 1 10 TXT CMD LOCK BASE Intel TXT Lock Base Command Register 168 3 6 1 11 TXT CMD UNLOCK BASE Intel TXT Unlock Base Command R
208. e Class Code for the device Register CCR Device 0 Function 0 Offset 09h Bit Attr Default Description Base Class 23 16 RO 06h For DMI port this field is hardwired to O6h indicating it is a Bridge Device Sub Class 27 RO gon For Device 0 DMI this field defaults to 00h to indicate a Host Bridge Register Level Programming I nterface 10 RO uh This field is hardwired to 00h for DMI port Register CCR Device 3 5 PCIe Function O Offset 09h Bit Attr Default Description Base Class 23 16 RO 06h For PCI Express ports this field is hardwired to O6h indicating it is a Bridge Device Sub Class See For PCI Express ports this field defaults to 04h indicating PCI to PCI 15 8 RO Description bridge This register changes to the sub class of 00h to indicate Host Bridge when bit 0 in MISCCTRLSTS Misc Control and Status Register is set 7 0 RO 00h Register Level Programming Interface This field is hardwired to 00h for PCI Express ports 40 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 3 3 7 3 3 3 8 3 3 3 9 CLSR Cacheline Size Register Register CLSR Device 0 DMI 3 5 PCle Function 0 Offset OCh Bit Attr Default Description Cacheline Size 7 0 RW Oh This register is set as RW for compatibility reasons only Cacheline size for Integrated I O is always 64B Hardware ignores this
209. e Parity Error Response bit in the Command register is set and it receives a completion with poisoned data from the primary side or if it forwards a packet with data including MSI writes to the primary side with poison RO Fast Back to Back Not applicable to PCI Express Hardwired to 0 RO Reserved RO 66 MHz Capable Not applicable to PCI Express Hardwired to 0 RO Capabilities List This bit indicates the presence of a capabilities list structure RO Reserved 2 0 RO Oh Reserved Datasheet Volume 2 39 intel Processor Integrated 1 Configuration Registers 3 3 3 5 RI D Revision Identification Register This register contains the revision number of the Integrated 1 0 Register RID Device 0 DMI 3 5 PCIe Function 0 Offset 08h Bit Attr Default Description Minor Revision 7 4 RWO See Steppings that required all masks be regenerated Refer to the Intel Description Core i7 800 and i5 700 Desktop Processor Series Specification Update for the value of the Revision ID Register Minor Revision Identification Number See Increment for each steppings that do not require masks to be 3 0 RWO Description regenerated Refer to the Intel Core i7 800 and i5 700 Desktop Processor Series Specification Update for the value of the Revision ID Register 3 3 3 6 CCR Class Code Register This register contains th
210. e chipset may decode this range as normal memory space or it may abort cycles to this range This command is either an TXTMW or a private write when private is open General Behavioral Rules This is a write only register Accesses to this register are done with 1 byte writes The data bits associated with this command are undefined and have no specific meaning Base TXT Offset 0398h Base TXT PR Offset 0398h Bit Attr Default Description 7 0 WO Oh N A 3 6 1 25 TXT PUBLIC KEY Intel TXT Public Key Hash Register Chipset public key hash Base TXT_TXT Offset 0400h Base TXT_PR Offset 0400h Base TXT PB Offset 0400h Bit Attr Default Description 256 0 RO N A Datasheet Volume 2 175 m t D Processor I ntegrated 1 Configuration Registers 3 7 Intel QuickPath I nterconnect Device Functions The following device functions control the Intel QuickPath Interconnect coherent link Register Group Device Function Comment Intel QuickPath Interconnect Port 16 0 Link and PPR Intel QuickPath Interconnect Port 16 1 Routing and protocol Table 3 20 Intel QuickPath I nterconnect Physical Link Map Port Device 16 DID VID 00h PCISTS PCICMD 04h CCR RID 08h HDR CLS OCh SID SVID 2Ch CAPPTR 34h QPI O LCL C4h QPI O LCRDC F8h 176 Datasheet Volume 2 Processor Integrated 1 110 C
211. e may be used by hardware to tag IOTLB entries software must perform domain selective or global invalidation of I OTLB after the context cache invalidation has completed 62 61 RW 0 Context I nvalidation Request Granularity CI RG When requesting hardware to invalidate the context entry cache by setting the ICC field software writes the requested invalidation granularity through this field Following are the encoding for the 2 bit CIRG field 00 Reserved 01 Global Invalidation request 110 supports this 10 Domain selective invalidation request The target domain D must be specified in the DID field supports this 11 Device selective invalidation request The target SID must be specified the SID field and the domain ID programmed in the context entry for this device must be provided the DID field aliases the h w behavior for this command to the Domain selective invalidation request Hardware indicates completion of the invalidation request by clearing the ICC field At this time hardware also indicates the granularity at which the actual invalidation was performed through the CAIG field 60 59 RO 0 Context Actual I nvalidation Granularity CAI G Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion by clearing the ICC field The following are the encoding for the 2 bit
212. e processor transactions received through both of the below configuration mechanisms are translated to the same format 22 2 Standard PCI Express Configuration Mechanism The following is the mechanism for translating processor 1 0 bus cycles to configuration cycles The PCI specification defines a slot based configuration space that allows each device to contain up to eight functions with each function containing up to 256 8 bit configuration registers The PCI specification defines two bus cycles to access the PCI configuration space Configuration Read and Configuration Write Memory and I O spaces are supported directly by the processor Configuration space is supported by a mapping mechanism implemented within the processor The configuration access mechanism makes use of the CONFIG_ADDRESS Register at I O address OCF8h though OCFBh and CONFIG DATA Register at I O address OCFCh though OCFFh To reference a configuration register DW I O write cycle is used to place a value into CONFIG_ADDRESS that specifies the PCI bus the device on that bus the function within the device and a specific configuration register of the device function being accessed CONFIG_ADDRESS 31 must be 1 to enable a configuration cycle CONFIG_DATA then becomes a window into the four bytes of configuration space specified by the contents of CONFIG_ADDRESS Any read or write to CONFIG_DATA will result in the processor translating the CONFIG_ADDRESS into the ap
213. e status bit the status bit should remain set and if MSI is enabled the hardware should trigger a new MSI 13 RO Data Link Layer Link Active This bit is set to 1 when the Data Link Control and Management State Machine is in the DL Active state Ob otherwise On a downstream port or upstream port when this bit is Ob the transaction layer associated with the link will abort all transactions that would otherwise be routed to that link 12 RWO Slot Clock Configuration This bit indicates whether Integrated 1 0 receives clock from the same XTAL that also provides clock to the device on the other end of the link 0 Indicates that the device uses an independent clock irrespective of the presence of a reference on the connector 1 Indicates the same physical reference clock to devices on both ends of the link 11 RO Link Training This field indicates the status of an ongoing link training session in the PCI Express port 0 LTSSM has exited the recovery configuration state 1 LTSSM is in recovery configuration state or the Retrain Link was set but training has not yet begun The Integrated I O hardware clears this bit once LTSSM has exited the recovery configuration state Refer to the latest PCI Express Base Specification for details of which states within the LTSSM would set this bit and which states would clear this bit 10 RO Reserved 66 Datasheet Volume 2 Processor
214. e will be one less than a 1 MB boundary Register PMBASE Device 3 5 PCIe Function O Offset 24h Bit Attr Default Description Prefetchable Memory Base Address 15 4 RW 000h This field corresponds to A 31 20 of the prefetchable memory address on the PCI Express port Prefetchable Memory Base Address Capability 3 0 RO 1h Integrated 1 0 sets this bit to O1h to indicate 64 bit capability The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit registers are read only contain the same value and encode whether or not the bridge supports 64 bit addresses If these four bits have the value Oh then the bridge supports only 32 bit addresses If these four bits have the value O1h then the bridge supports 64 bit addresses and the Prefetchable Base Upper 32 bits and Prefetchable Limit Upper 32 bits registers hold the rest of the 64 bit prefetchable base and limit addresses respectively Setting the prefetchable memory limit less than prefetchable memory base disables the 64 bit prefetchable memory range altogether In general the memory base and limit registers won t be programmed by software without clearing the MSE bit first PMLI MIT Prefetchable Memory Limit Register PMLIMIT Device 3 5 PCIe Function 0 Offset 26h Bit Attr Default Description Prefetchable Memory Limit Address 15 4 RW 000h This field corresponds to A 31 20 of the memory addre
215. ed Configuration Map 180h 184h 188h PERFCTRLSTS MISCCTRLSTS 34 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers L D 3 3 3 Standard PCI Configuration Space Oh to 3Fh Type 0 1 Common Configuration Space This section covers registers in the Oh to 3Fh region that are common to devices 0 3 5 Comments at the top of the table indicate what devices functions the description applies to Exceptions that apply to specific functions are noted in the individual bit descriptions 3 3 3 1 VI D Vendor Identification Register Register VID Device 0 3 5 Function O Offset 00h Bit Attr Default Description Vendor Identification Number VI D 13 0 RO goseti PCI Standard Identification for Intel 3 3 3 2 DI D Device Identification Register Register DID Device 0 3 5 Function 0 Offset 02h Bit Attr Default Description Device Identification Number 15 0 oes Identifier assigned to the product Datasheet Volume 2 35 intel Processor Integrated Configuration Registers 3 3 3 3 PCI CMD PCI Command Register This register defines the PCI 3 0 compatible command register values applicable to PCI Express space Register PCICMD Device 0 DMI Function 0 Offset 04h Bit Attr Default Description 15 11 RV 00h Reserved 10 RW 0 Legac
216. ed to the VC resource In order to remove or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link 0 RO 1 Traffic Class 0 Virtual Channel 0 Map TCOVCOM Traffic Class 0 is always routed to VCO Datasheet Volume 2 87 Processor Integrated 1 Configuration Registers intel 3 3 6 7 DMI VCORSTS DMI VCO Resource Status Reports the Virtual Channel specific status BAR DMI RCBAR Register DMIVCORSTS Offset 001Ah Bit Attr Default Description 15 2 RO Oh Reserved Reserved and Zero for future R WC S implementations Software must use 0 for writes to these bits Virtual Channel 0 Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control initialization It is I RO 1b set by default on Reset as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL Down state It is cleared when the link successfully exits the FC INIT2 state BI OS Requirement Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link 0 RO Ob Reserved 3 3 6 8 DMI VCIRCAP DMI VC1 Resource Capability BAR D
217. egister is only available in the Private Intel TXT configuration space e Accesses to this register are done with 1 byte writes e The data bits associated with this command are undefined and have no specific meaning Base TXT_TXT Offset 0238h Base TXT_PR Offset 0238h Bit Attr Default Description 7 0 3 6 1 12 TXT SINIT MEMORY BASE I ntel TXT SINIT Code Base Register This register holds a pointer to the base address of the SINIT code General Behavioral Rules This is a read write register This register is available for reads or writes in the Public Intel TXT configuration space This register is available for read or write in the Private Intel TXT configuration space Base TXT_TXT Offset 0270h Base TXT_PR Offset 0270h Base TXT PB Offset 0270h Bit Attr Default Description 63 40 RO Oh Reserved TXT SI NI T BASE 39 12 Base address of the SINIT code 39 12 RW Oh Note Only Bits 39 12 are implemented because the SINIT code must be aligned to a 4 KB page boundary 11 0 RO Oh Reserved Datasheet Volume 2 169 intel 3 6 1 13 3 6 1 14 170 Processor Integrated 1 Configuration Registers TXT SI NI T MEMORY SI ZE I ntel TXT SI Memory Size Register This register indicates the size of the SINIT memory space General Behavioral Rules This is a read write register This register i
218. egrated Memory Controller Channel 1 Control Registers DID VID 00h MC CHANNEL 1 RANK TIMING A 80h PCISTS PCICMD 04h MC CHANNEL 1 RANK TIMING B 84h CCR RID 08h MC CHANNEL 1 BANK TIMING 88h OCh MC_CHANNEL_1_REFRESH_TIMING 8Ch MC CHANNEL 1 CKE TIMING 90h MC CHANNEL 1 ZQ TIMING 94h MC CHANNEL 1 RCOMP PARAMS 98h MC CHANNEL 1 PARAMSI 9Ch MC CHANNEL 1 ODT PARAMS2 AOh MC CHANNEL 1 ODT MATRIX RANK 0 3 RD A4h MC CHANNEL 1 ODT MATRIX RANK 4 7 RD A8h MC CHANNEL 1 ODT MATRIX RANK 0 3 WR ACh MC CHANNEL 1 ODT MATRIX RANK 4 7 WR BOh MC CHANNEL 1 WAQ PARAMS B4h MC CHANNEL 1 SCHEDULER PARAMS B8h MC CHANNEL 1 MAINTENANCE OPS BCh MC CHANNEL 1 TX BG SETTINGS COh MC CHANNEL 1 RX BGF SETTINGS C8h MC CHANNEL 1 EW BGF SETTINGS CCh MC CHANNEL 1 DIMM RESET CMD 50h MC CHANNEL 1 EW OFFSET SETTINGS DOh MC CHANNEL 1 DIMM INIT CMD 54h MC CHANNEL 1 ROUND TRIP LATENCY D4h MC CHANNEL 1 DIMM INIT PARAMS 58h MC CHANNEL 1 PAGETABLE PARAMSI D8h MC CHANNEL 1 DIMM INIT STATUS 5Ch MC CHANNEL 1 PAGETABLE PARAMS2 DCh MC CHANNEL 1 DDR3CMD 60h MC TX BG CMD DATA RATIO SETTINGS EOh ee ee MC TX CMD OFFSET SETTINGS 1 E4h MC CHANNEL 1 REFRESH THROTTLE SUPPORT 68h MC TX BG DATA OFFSET SETTINGS E8h a JEMEN MC CHANNEL 1 MRS VALUE 0 1 70h FOh MC CHANNEL 1 MRS VALUE 2 74h F4h MC CHA
219. el QuickPath Interconnect When this points to DMI all address ranges in the configuration space of the port are ignored for address decode purposes 9 RV 0 Reserved TOCMVALID 8 RW 0 This bit is set by software after it has initialized the TOCM register with the right value decoder uses this bit to determine if bits from 32 to are to be decoded towards privileged CSR space TOCM Indicates the top of Intel QuickPath Interconnect physical addressability limit das RO 0100 00100 2736 default uses this to abort all inbound transactions that cross this limit EN1K 2 RW 0 This bit when set enables 1 K granularity for 1 0 space decode in each of the virtual PCI to PCI bridges corresponding to root ports and DMI ports 1 0 RV 0 Reserved Datasheet Volume 2 111 intel 3 4 4 2 3 4 4 3 112 Processor Integrated 1 Configuration Registers OMISCSS I ntegrated MISC Status This register be used to read the status of Integrated 1 strapping pins Register 5 55 Device 8 Function 0 Offset 9Ch Bit Attr Default Description 31 5 RO 0 Reserved 4 RO 1b Reserved 3 RO 1b Reserved CFG 2 0 Strap Port Bifurcation 111 x16 default 2 0 RO Strap 110 x8x8 101 Reserved Others Reserved TSEGCTRL TSEG Control Register The location of the TSEG region size and enable disable control Regist
220. en Data Link Layer Link Active field is changed Electromechanical I nterlock Control If an electromechanical lock is implemented a write of 1b to this field causes 11 RW 0 the state of the interlock to toggle Write of Ob has no effect This bit always returns a 0 when read If electromechanical lock is not implemented then either a write of 1 or 0 to this register has no effect Power Controller Control If a power controller is implemented when written this bit sets the power state of the slot per the defined encodings Reads of this field must reflect 10 RWS 1 the value from the latest write 0 Power On 1 Power Off Power Indicator Control If a Power Indicator is implemented writes to this register set the Power Indicator to the written state Reads of this field must reflect the value from the latest write 00 Reserved 01 On 9 8 RW 3h 10 Blink Integrated I O drives 1 5 Hz square wave for Chassis mounted LEDs 11 Off When this register is written the event is signaled using the virtual pins of the Integrated 1 0 over a dedicated SMBus port Integrated I O does not generate the Power_Indicator_On Off Blink messages on PCI Express when this field is written to by software Attention Indicator Control If an Attention Indicator is implemented writes to this register set the Attention Indicator to the written state Reads of this field reflect the value from the latest write 00 Reserved 7 6 RW 3h o On 10 Blink The I
221. ences in RID during device enumeration The solution is to implement a mechanism to read one of two possible values from the RID register 1 Stepping Revision ID SRID This is the default power on value for mask metal steppings 2 Compatible Revision I D CRID The CRID functionality gives BIOS the flexibility to load OS drivers optimized for a previous revision of the silicon instead of the current revision of the silicon in order to reduce drivers updates and minimize changes to the OS image for minor optimizations to the silicon for yield improvement or feature enhancement reasons that do not negatively impact the OS driver functionality Reading the RID in the processor returns either the SRID or CRID depending on the state of a register select flip flop Following reset the register select flip flop is reset and the SRID is returned when the RID is read at offset 08h The SRID value reflects the actual product stepping To select the CRID value BIOS configuration software writes a key value of 69h to Bus 0 Device 0 Function 0 DMI device of the processor s RID register at offset 08h This sets the SRID CRID register select flip flop and causes the CRID to be returned when the RID is read at offset 08h RID register the DMI device Bus 0 device 0 Function 0 is a write once sticky register and gets locked after the first write This causes the CRID to be returned on all subsequent RID register reads Software should read
222. er ROOTSTS Device 0 DMI 3 5 PCI e Function O Offset BOh Bit Attr Default Description 31 18 RV Oh Reserved PME Pending This field indicates that another PME is pending when the PME Status bit is set 17 RO Oh When the PME Status bit is cleared by software the pending PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately The PME pending bit is cleared by hardware if no more PMEs are pending PME Status This field indicates a PM_PME message either from the link or internally from 16 RW1C Oh within that root port was received at the port 1 PME was asserted by a requester as indicated by the PMEREQID field This bit is cleared by software by writing a 1 PME Requester ID 15 0 RO 0000h This field indicates the PCI requester ID of the last PME requestor If the root port itself was the source of the virtual PME message then a RequesterlD of 0 is logged in this field 72 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 3 4 28 DEVCAP2 PCI Express Device Capabilities Register 2 Register DEVCAP2 Device 0 DMI 3 5 PCIe Function O Offset B4h Bit Attr Default Description 31 6 RO Oh Reserved 5 RO 1 Alternative RID Interpretation ARI Capable This bit is set to 1b indicating Root Port supports this capability 4 RO 1 Completion T
223. er TSEGCTRL Device 8 Function 0 Offset A8h Bit Attr Default Description TBA TSEG Base Address 31 20 RWO FEOh Indicates the base address which is aligned to a 1 MB boundary Bits 31 20 corresponds to A 31 20 address bits 19 4 RV 0 Reserved TSEG SIZE Size of TSEG 000 512 KB 001 1 MB 3 1 RWO 100 010 2 MB 011 4 MB 100 8 MB Others Reserved TSEG_EN TSEG Enabling Control 0 RWO 1 0 Disabling the TSEG in 1 Enabling the TSEG in IIO for IB access check Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 4 4 4 TOLM Top of Low Memory Top of low memory Note that bottom of low memory is assumed to be 0 Register TOLM Device 8 Function 0 Offset DOh Bit Attr Default Description TOLM Address 31 26 RWLB 0 Indicates the top of low DRAM memory which is aligned to a 64 MB boundary i A 32 bit transaction that satisfies 0 lt A 31 26 lt TOLM 31 26 is a transaction towards main memory 25 0 RV 0 Reserved 3 4 4 5 TOHM Top of High Memory Top of high memory Note that bottom of high memory is fixed at 4 GB Register TOHM Device 8 Function 0 Offset D4h Bit Attr Default Description TOHM Address Indicates the limit of an aligned 64 MB granular region that decodes gt 4 GB addresses towards system memory A 64 bit transaction that satisfies 4G 63 26 RWLB 0 t A 63 26
224. erating a fatal error 22 10 RV Reserved 9 RV 0 Reserved PME_TO_ACK Time out Control This field sets the time out value for receiving a PME_TO_ACK message after a PME_TURN_OFF message has been transmitted This field has meaning only if bit 6 is set to a Ob 8 7 RW 0 00 1ms 01 10 ms 10 50 11 test mode 6 RW 0 Disable Time out for Receiving When set disables the time out to receiving the PME_TO_ACK Send PME_TURN_OFF Message 5 RW 0 When this bit is written with a 1 110 sends a PME_TURN_OFF message to the PCI Express link Hardware clears this bit when the message has been sent on the link When set the PCI Express errors do not trigger an MSI interrupt regardless of the whether MSI is enabled or not When this bit is cleared PCI Express errors are reported using MSI and or NMI SMI MCA When this bit is clear and if MSI enable bit in the MSICTRL 4 RW 0 register is set then MSI interrupt is generated for PCI Express errors When this bit is clear and System Error on Fatal Error Enable bit in Section 3 3 4 25 ROOTCON PCI Express Root Control Register is set then NMI SMI MCA is also generated for a PCI Express fatal error Similar behavior for non fatal and corrected errors 3 RW 0 Reserved Enable ACPI Mode for PM When set all PM events at the PCI Express port are handled using PMEGPE messages to the PCH and no MSI interrupts are ever generated for PM events at the root port regar
225. erating memory accesses to the VGA memory range and it will abort all transactions to that address range Also if peer to peer memory read disable bit is set VGA memory reads are aborted 4 f peer to peer memory read disable bit is set then peer to peer memory reads are aborted Datasheet Volume 2 297 intel System Address Map Table 5 9 summarizes behavior on inbound I O transactions from any PCle port Table 5 9 Inbound O Address Decoding Address Range Conditions 110 Behavior Any Inbound I O is disabled Master Abort VGA Address within 3BOh 3BBh 3COh 3DFh and inbound 1 0 is enabled and main switch SAD is programmed to forward VGA OR address not within local peer to peer I O base limit range but within global peer to peer 1 0 base limit range Forward to Intel QuickPath Interconnect Address within 3BOh 3BBh 3COh 3DFh inbound 1 is enabled and main switch SAD is NOT programmed to forward VGA and one of the PCle ports has VGAEN bit set Forward to that PCle port Address within 3BOh 3BBh 3COh 3DFh and inbound 1 is enabled and main switch SAD is NOT programmed to forward VGA and none of the PCle has VGAEN bit set but is within the 1 O base limit range of one of the PCle port Forward to that PCle port Address within 3BOh 3BBh 3COh 3DFh and inbound 1 is enabled and main switch SAD is NOT programmed to forward VGA and none of the PCle has VGA
226. es Device 4 5 Function 0 Offset ACh Access as a DWord Bit Attr Default Description 31 24 RW 9 ODT_WR3 ODT values for all 4 Ranks when writing to Rank 3 23 16 RW 5 ODT_WR2 ODT values for all 4 Ranks when writing to Rank 2 15 8 RW 6 ODT_WRI1 ODT values for all 4 Ranks when writing to Rank 1 7 0 RW 5 ODT WRO ODT values for all 4 Ranks when writing to Rank 0 MC CHANNEL 0 MATRIX RANK 4 7 WR MC CHANNEL 1 ODT MATRIX RANK 4 7 WR This register contains the ODT activation matrix for RANKS 4 to 7 for Writes Device 4 5 Function O Offset BOh Access as a DWord Bit Attr Default Description 31 24 RW 9 ODT_WR7 ODT values for all 4 ranks when writing to Rank7 23 16 RW 5 WR6e ODT values for all 4 ranks when writing to Rank6 15 8 RW 6 WR5 ODT values for all 4 ranks when writing to Rank5 7 0 RW 5 WRA ODT values for all 4 ranks when writing to Rank4 Datasheet Volume 2 253 intel Processor Uncore Configuration Registers 4 10 23 MC CHANNEL 0 WAQ PARAMS MC CHANNEL 1 WAQ PARAMS This register contains parameters that specify settings for the Write Address Queue 254 Device 4 5 Function 0 Offset B4h Access as a DWord Bit Attr Default Description 31 30 RO 0 Reserved PRECASWRTHRESHOLD 29 25 RW 6 Threshold above which Medium Low Priority reads cannot PRE CAS write requests PARTWRTH
227. es 17 16 RV Oh Reserved Role Based Error Reporting 15 RO 1 Integrated 1 is PCI Express Base Specification compliant and supports this feature Power Indicator Present on Device 14 RO 0 Does not apply to root ports integrated devices 13 RO 0 Attention Indicator Present Does not apply to root ports or integrated devices Attention Button Present 12 RO 0 Does not apply to root ports or integrated devices 11 9 RO 000 Reserved 8 6 RO 000 Reserved 5 RO 1 Extended Tag Field Supported Integrated 1 0 devices support 8 bit tag 4 3 RO Oh Reserved Dev 0 000b Max Payload Size Supported 2 0 RO Dev 3 5 001b supports 256B payloads on PCI Express ports 128B on the DMI port Dev 3 5 001b Device 0 58 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 3 4 17 DEVCTRL PCI Express Device Control Register The PCI Express Device Control register controls PCI Express specific capabilities parameters associated with the device Sheet 1 of 2 Register DEVCTRL Device 0 DMI 3 5 PCIe Function O Offset 98h Bit Attr Default Description 15 RV Oh Reserved Max_Read_Request_Size 14 12 RO 000 Express DMI ports in Integrated 1 0 do not generate requests greater than 128B and this field is ignored Enable No Snoop 11 RO 0 Not applicable to root ports since they never s
228. es that an internal core error logic notification should be generated if a correctable error is reported by any of the devices in the hierarchy associated with and including this port Note that generation of system notification on a PCI Express correctable error is orthogonal to generation of an MSI interrupt for the same error Both a system error and MSI can be generated on a correctable error or software can choose one of the two Refer to the latest PCI Express Base Specification for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express DMI port 3 3 4 26 Express Root Capabilities Register The PCI Express Root Status register specifies parameters specific to the root complex port Function O Register ROOTCAP Device 0 DMI 3 5 PCIe Offset AEh Bit Attr Default Description 15 1 RV Oh Reserved CRS Software Visibility 0 RO 1 When set to 1 this bit indicates that the Root Port is capable of returning Configuration Request Retry Status CRS Completion Status to software Integrated 1 0 supports this capability Datasheet Volume 2 71 Processor Integrated 1 Configuration Registers intel 3 3 4 27 5 5 Express Root Status Register The PCI Express Root Status register specifies parameters specific to the root complex port Regist
229. ests is disabled 1 Reporting of unsupported requests is enabled Refer to the latest PCI Express Base Specification for complete details of how this bit is used in conjunction with other bits to UR errors Fatal Error Reporting Enable Applies only to the PCI Express DMI ports Controls the reporting of fatal errors that Integrated 1 detects on the PCI Express DMI interface 0 Reporting of Fatal error detected by device is disabled 2 RW 0 1 Reporting of Fatal error detected by device is enabled Refer to the latest PCI Express Base Specification for complete details of how this bit is used in conjunction with other bits to report errors For the PCI Express DMI ports this bit is not used to control the reporting of other internal component uncorrectable fatal errors at the port unit in any way Datasheet Volume 2 59 60 Processor Integrated 1 Configuration Registers Sheet 2 of 2 Register Device Function Offset DEVCTRL 0 DMI 3 5 PCle 0 98h Bit Attr Default Description RW Non Fatal Error Reporting Enable Applies only to the PCI Express DMI ports Controls the reporting of non fatal errors that Integrated 1 detects on the PCI Express DMI interface 0 Reporting of Non Fatal error detected by device is disabled 1 Reporting of Non Fatal error detected by device is enabled Refer to the latest PCI Express Base Specification for complete details of how this bit
230. et Reserved Bit This bit is reserved for future expansion and must not be written The latest version of the PCI Local Bus Specification requires that reserved bits must be RSVD RV preserved Any software that modifies a register that contains a reserved bit is responsible for reading the register modifying the desired bits and writing back the result Reserved Bits Some of the processor registers described in this section contain reserved bits These bits are labeled Reserved Software must deal correctly with fields that are reserved On reads software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value On writes software must ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and then written back Note that software does not need to perform a read merge write operation for the Configuration Address CONFIG_ADDRESS register Reserved Registers In addition to reserved bits within a register the processor contains address locations in the configuration space that are marked either Reserved or Intel Reserved The processor responds to accesses to Reserved address locations by completing the host cycle When a Reserved register location is read a zero value is returned Reserved registers can be 8 16 or
231. et the No Snoop bit for transactions they originate not forwarded from peer to PCI Express This bit has no impact on forwarding of NoSnoop attribute on peer requests 10 RO 0 Reserved 9 RO 0 Reserved Extended Tag Field Enable 8 RW Oh This bit enables the PCI Express DMI ports to use an 8 bit Tag field as a requester Max Payload Size This field is set by configuration software for the maximum TLP payload size for the PCI Express port As a receiver the must handle TLPs as large as the set value As a requester that is for requests where Integrated O s own Requesterl D is used it must not generate TLPs exceeding the set value 7 5 RW 000 Permissible values that can be programmed are indicated by the Max Payload Size Supported in the Device Capabilities register 000 128B max payload size 001 256B max payload size applies only to standard PCI Express ports and DMI port aliases to 128B others alias to 128B Enable Relaxed Ordering Not applicable to root ports since they never set relaxed ordering bit as a 4 RO 0 requester this does not include Tx forwarded from peer devices This bit has no impact on forwarding of relaxed ordering attribute on peer requests Unsupported Request Reporting Enable Applies only to the PCI Express DMI ports This bit controls the reporting of unsupported requests that Integrated I O itself detects on requests its 3 RW 0 receives from a PCI Express DMI port 0 Reporting of unsupported requ
232. etting this field to tRFC current to a single DI MM can be limited to that required to 0 support this scenario without significant performance impact 8 panic refreshes in tREFI to one rank 1 opportunistic refresh every tRFC to another rank full bandwidth delivered by the third and fourth ranks Platforms that can supply peak currents to the DIMMs should disable opportunistic refresh throttling for max performance 29 19 RW tREFI 8 15 9 RW 9 Average periodic refresh interval divided by 8 tRFC 840 M Delay between the refresh command and an activate or refresh command Datasheet Volume 2 Processor Uncore Configuration Registers intel 4 10 14 MC_CHANNEL_0_CKE_TIMING MC CHANNEL 1 CKE TIMING This register contains parameters that specify the CKE timings All units are in DCLK Device 4 5 Function O Offset 90h Access as a DWord Bit Attr Default Description tRANKI DLE Rank will go into powerdown after it has been idle for the specified number of DCLKs tRANKIDLE covers max txxxPDEN Minimum value is 31 24 RW 0 tWRAPDEN If CKE is being shared between ranks then both ranks must be idle for this amount of time A Power Down Entry command will be requested for a rank after this number of DCLKs if no request to the rank is in the MC tXP 23 21 RW 0 Minimum delay from exit power down with DLL and any valid command i Exit Precharge Power Down with DLL fro
233. etween U and D TOTAL EFFECTIVE DELAY PIPE DEPTH UCLK PERIOD in ps MIN SEP DELAY DELAY FRACTION TOTAL EFFECTIVE DELAY D UCLK PERIOD in ps G C D U D Determine OFFSET MULTIPLE using the equation FLOOR OFFSET MULTIPLE 1 G C D U D gt DELAY FRACTION OFFSET VALUE MOD OFFSET MULTIPLE U x Final answer for OFFSET MULTIPLE Device 4 5 Function O Offset COh Access as a DWord Bit Attr Default Description 31 17 RO 0 Reserved OFFSET RW 2 TX offset setting ALI ENRATI O 188 RW 8 Dclk ratio to BCLK TX Alien Ratio setting 7 0 RW 4 NATI VERATI Uclk ratio to BCLK TX Native Ratio setting Datasheet Volume 2 Processor Uncore Configuration Registers 4 10 27 MC CHANNEL 0 SETTINGS MC CHANNEL 1 RX BGF SETTINGS These are the parameters used to set the Rx clock crossing BGF Device 4 5 Function 0 Offset C8h Access as a DWord Bit Attr Default Description 31 27 RO 0 Reserved PTRSEP 26 24 RW 2 RX FIFO pointer separation settings THIS FIELD IS NOT USED BY HARDWARE RX Pointer separation can be modified using the round trip setting larger value causes a larger pointer separation OFFSET 2316 RW 0 RX offset setting ALIENRATIO 15 8 ins 1 Qclk to BCLK ratio RX Alien Ratio setting NATI VERATIO h RW 2 Uclk to BCLK ratio RX Native Ratio setting 4 10 28 MC CHANNEL 0 EW SETTINGS MC CHANNEL 1 EW BGF SET
234. f an uncorrectable fatal error at the port or below its hierarchy The internal core error logic of Integrated I O then decides if how to escalate the error further pins message an so forth 0 No internal core error logic notification should be generated on a fatal error reported by any of the devices in the hierarchy associated with and including this port 1 Indicates that a internal core error logic notification should be generated if a fatal error is reported by any of the devices in the hierarchy associated with and including this port Note that generation of system notification on a PCI Express DMI fatal error is orthogonal to generation of an MSI interrupt for the same error Both a system error and MSI can be generated on a fatal error or software can choose one of the two Refer to the latest PCI Express Base Specification for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express DMI port System Error on Non Fatal Error Enable This field enables notifying the internal core error logic of occurrence of an uncorrectable non fatal error at the port or below its hierarchy The internal core error logic of Integrated I O then decides if how to escalate the error further pins message and so forth 0 No internal core error logic notification should be generated on a fatal error reported by any of the devices in the hierarchy
235. f driving RESET to the DIMMs This bit is set on S3 exit and cold boot to take over RESET driving responsibility from the physical layer Datasheet Volume 2 Processor Uncore Configuration Registers 4 7 6 4 7 7 intel MC_CHANNEL_ MAPPER Channel mapping register The sequence of operations to update this register is Read MC_Channel_ Mapper register Compare data read to data to be written If different then write Poll MC_Channel_ Mapper register until the data read matches data written Device 3 Function 0 Offset 60h Access as a DWord Bit Attr Default Description 31 12 RO 0 Reserved RDLCH1 11 9 RW 0 Mapping of Logical channel 1 to physical channel for Reads WRLCH1 8 6 RW 0 Mapping of Logical channel 1 to physical channel for Writes RDLCHO 9a RM Mapping of Logical channel 0 to physical channel for Read WRLCHO 2 0 RW 0 Mapping of Logical channel 0 to physical channel for Writes MC MAX DOD This register defines the MAX number of DIMMS RANKS BANKS ROWS COLS among all DIMMS populating the two channels The Memory Init logic uses this register to cycle through all the memory addresses writing all Os to initialize all locations Device 3 Function O Offset 64h Access as a DWord Bit Attr Default Description 31 11 RO 0 Reserved MAXNUMCOL Maximum Number of Columns 00 2 10 columns 10 9 RW 0 01 2 11 columns 10 2 12 columns
236. f root port 0100 NMI Not supported using MSI of root port 0101 INIT Not supported using MSI of root port 0110 Reserved 0111 ExtINT Not supported using MSI of root port 1000 1111 Reserved Interrupt Vector The interrupt vector LSB will be modified by the Integrated I O to provide 7 0 RW Oh context sensitive interrupt information for different events that require attention from the processor for example Power Management and error events 3 3 4 11 MSI MSK MSI Mask Bit Register The Mask Bit register enables software to disable message sending on a per vector basis Register MSIMSK Device 0 DMI 3 5 PCIe Function 0 Offset 6Ch Bit Attr Default Description 31 2 RV Oh Reserved Mask Bit 1 0 RW Oh For each Mask bit that is set the PCI Express port is prohibited from sending the associated message Datasheet Volume 2 55 intel Processor Integrated 1 Configuration Registers 3 3 4 12 MSI PENDI NG MSI Pending Bit Register The Mask Pending register enables software to defer message sending on a per vector basis Register MSIPENDING Device 0 DMI 3 5 PCIe Function 0 Offset 70h Bit Attr Default Description 31 2 RV Oh Reserved Pending Bit 1 0 RO Oh For each Pending bit that is set the PCI Express port has a pending associated message 3 3 4 13 PEGCAPI D PCI Express Capability dentity Register The PCI Exp
237. facturer of the system This 16 bit register combined with the Device Identification Register uniquely identify any PCI device Device 0 Function 0 1 Offset 2Ch Device 2 Function 0 1 Offset 2Ch Device 3 Function 0 1 4 Offset 2Ch Device 4 5 Function 0 3 Offset 2Ch Bit Attr Default Description Vendor Identification Number 13 0 RWO sogeh The default value specifies Intel A write to any of the above registers on the processor will write to all of them Datasheet Volume 2 205 Processor Uncore Configuration Registers intel 4 4 7 SI D Subsystem Identity This register identifies the system It appears in every function Device 0 Function 0 1 Offset 2bh Device 2 Function 0 1 Offset 2bh Device 3 Function 0 1 4 Offset 2bh Device 4 5 Function 0 3 Offset 2bh Bit Attr Default Description Subsystem Identification Number 15 9 RWO SURG The default value specifies Intel 206 Datasheet Volume 2 Processor Uncore Configuration Registers intel 4 4 8 PCI CMD Command Register This register defines the PCI 3 0 compatible command register values applicable to PCI Express space Device 0 Function 0 1 Offset 04h Device 2 Function 0 1 Offset 04h Device 3 Function 0 1 4 Offset 04h Device 4 5 Function 0 3 Offset 04h Bit Attr Default Descrip
238. figuration Request Decoding Transaction Type Conditions 110 Behavior Type 0 N A Master Abort Type 1 Inbound Configuration disabled Master Abort Inbound Configuration enabled by MISCCTRLSTS 1 and bus 0 Master Abort Inbound Configuration enabled and bus is between 1 255 and Bus number matches the internal bus number of IIOBUSNO or PBN register Master Abort Inbound Configuration enabled and bus is between 1 255 and Bus number does not match the internal bus number of IIOBUSNO or PBN register and bus number is outside of LCFGBUS BASE LCFGBUS LI MIT and inside of GCFGBUS BASE GCFGBUS LI MIT Forward to Intel QuickPath Interconnect Inbound Configuration enabled and bus is between 1 255 and Bus number does not match the internal bus number of IIOBUSNO or PBN register and bus number is outside of GCFGBUS BASE GCFGBUS LI MIT Forward to subtractive decode port DMI or Intel QuickPath Interconnect if enabled using MISCCTRLSTS 1 Inbound Configuration enabled and bus is between 1 255 and Bus number does not match the internal bus number of ILOBUSNO or PBN register and is within LCFGBUS BASE LCFGBUS LIMIT and one of the PCle ports is positively decoded Forward to that PCle port Forward as Type 0 1 depending on secondary bus number of the port Inbound Configuration enabled and bus is between 1 255 and Bus number does not match the inter
239. fset 48h Access as a DWord Bit Attr Default Description 31 8 RO 0 Reserved CHANNEL1 ACTIVE 9 RW 0 When set this bit indicates MC channel 1 is active This bit is controlled set reset by software only This bit is required to be set for any active channel when INIT DONE is set by software CHANNELO ACTIVE When set this bit indicate MC channel 0 is active This bit is controlled 8 RW 0 ds set reset by software only This bit is required to be set for any active channel when INIT_DONE is set by software INIT_DONE MC initialize complete signal Setting this bit will exit the training mode of 7 WO 0 the Integrated Memory Controller and begin normal operation including all enabled maintenance operations Any CHANNNEL ACTIVE bits not set when writing a 1 to INIT DONE will cause the corresponding channel to be disabled DI VBY3EN Divide By 3 Enable When set MAD would use the longer pipeline for transactions that are 3 6 RW 0 4 TOC or 6 way interleaved and shorter pipeline for all other transactions The SAG registers must be appropriately programmed as well 5 RO 0 Reserved CHANNELRESET1 4 RW 0 Reset only the state within the channel Equivalent to pulling warm reset for that channel CHANNELRESETO 3 RW 0 Reset only the state within the channel Equivalent to pulling warm reset for that channel AUTOPRECHARGE Autoprecharge Enable 2 RW 0 This bit should be set with the closed page bi
240. gister sss men 201 4 4 3 RID Revision Identification Register sss 202 4 4 3 1 Stepping Revision ID 5 2 222 203 Datasheet Volume 2 7 4 5 4 6 4 7 4 8 4 9 4 4 3 2 Compatible Revision ID CRID 0 203 4 4 4 CCR Class Code Register xx sic nas ria tet a RR Y 204 4 4 5 HDR Header Type nemen ene 205 4 4 6 SVID Subsystem Vendor Identification 2 2 2 205 4 4 7 SID Subsystem Identity ccc aa eee ee reese ee memes 206 4 4 8 PCICMD Command 207 4 4 9 5 5 Status Register 208 SAD System Address Decoder 1 2 1 222 209 4 5 1 SAD PAMO0123 ore Moris deep pep ER Re Re e exa Ka dE i Ra RR 209 4 5 2 SAD PAM S6 ides 211 4 5 3 SAD HEN excea 212 4 5 4 SAD SMRAM ii DEED up Lie Ux MED UE 212 4 525 SAD PCIEXBAR mirsanana nn Ie dapag ades Pr re adis 213 4 5 6 SAD TPGIEXBAR AER E
241. gister Device Function Offset PCISTS 8 0 3 06h Bit Attr Default Description 12 RO Received Target Abort This bit is set when a device experiences a completor abort condition on a transaction it mastered on the primary interface Integrated 1 0 internal bus Note that certain errors might be detected right at the PCI Express interface and those transactions might not propagate to the primary interface before the error is detected for example accesses to memory above VICSRBASE Such errors do not cause this bit to be set and are reported using the PCI Express interface error bits secondary status register Conditions that cause Bit 12 to be set include Device receives a completion on the primary interface internal bus of Integrated 1 0 with completor abort completion Status This includes CA status received on the primary side of a PCI Express port on peer to peer completions also e Accesses Intel QuickPath InterConnect that return a failed completion status Other completer abort conditions detected on the Integrated 1 O internal bus 11 RO Signaled Target Abort This bit is set when a device signals a completer abort completion status on the primary side internal bus of Integrated I O This condition includes a PCI Express port forwarding a completer abort status received on a completion from the secondary side and passed to the primary side on a peer to peer completion
242. gister to which the first pending fault was recorded when the Primary Fault pending field was set by hardware 7 RV 0 Reserved Invalidation Time out Error ITE Hardware detected a Device IOTLB invalidation completion time out At 6 RW1CS 0 hd this time a fault event may be generated based on the programming of the Fault Event Control register Invalidation Completion Error Hardware received an unexpected or invalid Device IOTLB invalidation 5 RW1CS 0 Pad completion At this time a fault event is generated based on the programming of the Fault Event Control register Invalidation Queue Error I QE Hardware detected an error associated with the invalidation queue For 4 RW1CS 0 example hardware detected an erroneous or un supported Invalidation Descriptor in the Invalidation Queue At this time a fault event is generated based on the programming of the Fault Event Control register 3 2 RV 0 Reserved Primary Pending Fault PPF This field indicates if there are one or more pending faults logged in the fault recording registers 0 No pending faults in any of the fault recording registers 1 ROS 0 1 One or more fault recording registers has pending faults The fault recording index field is updated by hardware whenever this field is set by hardware Also depending on the programming of fault event control register a fault event is generated when hardware sets this field 0 RWICS 0 Primary Fault Overflow Hardware sets this bit to
243. gisters 18 23 131 3 4 5 13 IR 0 3 Increment Registers 0 3 131 3 4 5 14 IR 4 7 Increment Registers 4 7 0 0 04 132 3 4 5 15 IR 8 11 Increment Registers 8 11 132 3 4 5 16 IR 12 15 Increment Registers 12 15 132 3 4 5 17 IR 16 17 Increment Registers 16 17 133 3 4 5 18 IR 18 23 Increment Registers 18 23 133 System Control Status Registers Device 8 Function 2 134 3 4 6 1 SYSMAP System Error Event Map Register 134 4 6 2 GENMCA Generate nnn nnn 134 4 6 3 SYRE System 135 iscellaneous Registers Dev 8 3 7 2 1 1 1 1 1 4 135 4 7 1 lIOSLPSTS L IIO Sleep Status Low 135 4 7 2 lIOSLPSTS H IIO Sleep Status High Register 136 4 7 3 PMUSTATE Power Management State 136 4 7 4 CTSTS Throttling Status 137 4 7 5 CTCTRL Throttling Control Register
244. guration accesses from Intel QuickPath Interconnect targeting the corresponding device s configuration space 27 RWL 0 inside are master aborted When clear configuration accesses targeting the device s configuration space are allowed This bit has no effect on smbus and jtag initiated accesses to corresponding device s configuration space The lock bit is lock1 TXT Lock Register 114 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers Sheet 2 of 3 Register DEVHIDE1 Device 8 Function 0 Offset FOh Bit Attr Default Description Hide Dev16 FunO When set hide Device 16 Function 0 When set all PCI configuration accesses from Intel QuickPath Interconnect targeting the corresponding device s configuration space 26 RWL 0 inside are master aborted When clear configuration accesses targeting the device s configuration space are allowed This bit has no effect on smbus and jtag initiated accesses to corresponding device s configuration space The lock bit is lock1 TXTLOCK TXT Lock Register 25 20 RV 00h Reserved 19 12 RV 0 Reserved Hide Dev8 Fun3 12 MER 9 When set hide Device 8 Function 3 11 8 RV 0 Reserved 7 RV 0 Reserved Hide Dev6 When set hide Device 6 1 This bit has no impact on any configuration transactions that target the secondary side of a device that is a PCI to PCI bridge 2 This bit h
245. h Device 3 Function Offset 00h Device 4 5 Function 0 3 Offset 00h Bit Attr Default Description Vendor Identification Number 15 0 RO The value assigned to Intel 8086h DI D Device Identification Register This 16 bit register combined with the Vendor Identification register uniquely identifies the Function within the processor Writes to this register have no effect See Table 4 1 for the DID of each processor function Device 0 Function 0 1 Offset 02h Device 2 Function 0 1 Offset 02h Device 3 Function Offset 02h Device 4 5 Function 0 3 Offset 02h Bit Attr Default Description 15 0 RO See Device Identification Number Table 4 1 Identifies each function of the processor Datasheet Volume 2 201 m L D Processor Uncore Configuration Registers 202 RI D Revision Identification Register This register contains the revision number of the processor The Revision ID RID is a traditional 8 bit Read Only RO register located at offset 08h in the standard PCI header of every PCI PCI Express compatible device and function Previously a new value for RID was assigned for Intel chipsets for every stepping There is a a need to provide an alternative value for software compatibility when a particular driver or patch unique to that stepping or an earlier stepping is required for instance to prevent Windows software from flagging differ
246. h SR 8 09Ch SR 9 OAOh SR 10 OA4h SR 11 OA8h SR 12 OACh SR 13 OBOh CAPPTR SR 14 0B4h SR 15 OB8h INTPIN INTLIN SR 16 OBCh EXPCAP NXTPTR CAPID 040h SR 17 DEVCAP 044h SR 18 OC4h DEVSTS DEVCTRL 048h SR 19 OC8h 04Ch 20 OCCh 050h SR 21 ODOh 054h SR 22 0D4h 058h SRI23 OD8h 05Ch CWRIO ODCh RESERVEDPCI Express Header space 10 064h CWR 2 OE4h 068h CWRI3 OE8h 06Ch CWR 4 OECh 070h CWRI5 OFOh 074h CWRI6 OF4h 078h CWRI7 OF8h SR O 07Ch CWRI8 OFCh Notes 1 CAPPTR points to the first capability block 94 Datasheet Volume 2 Processor Integrated 1 Configuration Registers intel Table 3 10 Core Registers Device 8 Function 1 Semaphore and ScratchPad Registers Sheet 2 of 2 RESERVEDPCI Express Header space CWR 9 CWR 10 CWR 11 CWR 12 CWR 13 CWR 14 CWR 15 CWR 16 CWR 17 CWR 18 CWR 19 CWR 20 CWR 21 CWR 22 CWR 23 IR O IR 1 IR 2 IR 3 IR 4 IR 5 IR 6 IR 7 IR 8 IR 9 IR 10 IR 11 IR 12 IR 13 IR 14 IR 15 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 128h 12Ch 130h 134h 138h 13Ch 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h 168h 16Ch 170h 174h 178h 17Ch Datasheet Vol
247. hat 9 0 RO Oh Reserved 3 4 4 14 LMMI OH LI MI T Local MMI OH Limit Register LMMI OH LIMIT Device 8 Function O Offset 112h Bit Attr Default Description Local MMI OH Limit Address This field corresponds to A 31 26 of MMIOH limit An inbound or outbound memory address that satisfies local MMIOH base upper 31 0 local MMIOH base 15 10 x A 63 26 x local MMI OH limit upper 31 0 local MMIOH 15 10 RW 00h limit 15 10 is treated as local a peer to peer transactions that does not cross an Intel QuickPath Interconnect link Setting LMMIOH BASEU LMMIOH BASE greater than LMMI OH LI MI TU LMMI OH LI MIT disables local MMIOH peer to peer This register is programmed once at boot time and does not change after that 9 0 RO 000h Reserved Datasheet Volume 2 119 intel 3 4 4 15 3 4 4 16 3 4 4 17 120 Processor Integrated 1 Configuration Registers LMMI OH BASEU Local MMI Base Upper Register LMMI OH BASEU Device 8 Function O Offset 114h Bit Attr Default Description 31 19 RO 0000h This field corresponds to address A 63 51 of the local MMIOH range and is always 0 Local MMI OH Base Upper Address This field corresponds to A 50 32 of MMIOH base An inbound or outbound memory address that satisfies local MMIOH base upper 31 0 local MMIOH base 15 10 lt A 63 26 lt local MMIOH limit upper 31 0 local MMI OH 18 0 RW 00000h limit 1
248. he PCI Express DMI using the root port s DEVCTRL2 register this field selects the sub range within that larger range for additional controllability 9 8 RW 00 00 175 305 01 31 5 45 s 10 46 5 64 5 11 Reserved Note This field is subject to redefinition based on design feedback 7 0 RV 00 Reserved Datasheet Volume 2 83 L D Processor I ntegrated 1 Configuration Registers 3 3 6 DMI Root Complex Register Block This block is mapped into memory space using register DMIRCBAR DevO FO offset 50h Table 3 6 DMI RCRB Registers DMI VCH 00h DMIVCCAP1 04h DMILCAP DMI VCCAP2 08h DMILSTS DMILCTRL DMIVCCTL OCh DMI VCORCAP 10h DMI VCORCTL 14h DMIVCORSTS 21 18h DMIVC1RCAP 1Ch DMIVC1RCTL DMIVC1RSTS 84 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 3 6 1 3 3 6 2 DMIVCH DMI Virtual Channel Capability Header This register Indicates DMI Virtual Channel capabilities BAR DMIRCBAR Register DMIVCH Offset 0000h Bit Attr Default Description Pointer to Next Capability PNC 31 20 RO 040h This field contains the offset to the next PCI Express capability structure in the linked list of capabilities Link Declaration Capability PCI Express Virtual Channel Capability Version PCI EVCCV 19 16 RO 1h Hardwired to 1 to indicate compliances with the 1 1 version of the PCI Express specificati
249. he limit address of a 64 MB aligned DRAM memory region on Intel QuickPath Interconnect that is non coherent Address bits 63 26 of an inbound address if it satisfies NcMem Base 63 26 lt A 63 26 lt NcMem Limit 63 26 is considered to be towards the non coherent Intel 63 26 RW 0 QuickPath Interconnect memory region It is expected that the range indicated by the non coherent memory base and limit registers is a subset of either the low DRAM or high DRAM memory regions as described using the corresponding base and limit registers This register is programmed once at boot time and does not change after that 25 0 RV 0 Reserved 3 4 4 8 DEVHI DE1 Device Hide 1 Register This register provides a method to hide the PCI configuration space of devices inside the Integrated 1 0 from the host initiated configuration accesses This register does not impact JTAG initiated accesses to the corresponding device s configuration space When set for each device all PCI configuration accesses from Intel QuickPath Interconnect targeting the corresponding device s configuration space inside the Integrated I O IIO are master aborted When clear configuration accesses targeting the device s configuration space are allowed Sheet 1 of 3 Register DEVHIDE1 Device 8 Function 0 Offset FOh Bit Attr Default Description 31 28 RV 0 Reserved Hide Dev16 1 When set hide Device 16 Function 1 When set all PCI confi
250. ice and all subordinate devices The transaction layer corresponding to port will be RW 0 emptied by Integrated I O when this bit is set This means that in the outbound direction all posted transactions are dropped and non posted transactions are sent a UR response In the inbound direction completions for inbound NP requests are dropped when they arrive Inbound posted writes are required to be flushed as well either by dropping the packets are by retiring them normally Note also that a secondary bus reset will not reset the virtual PCI to PCI bridge configuration registers of the targeted PCI Express port Master Abort Mode RO 9 Not applicable to PCI Express This bit is hardwired to 0 VGA 16 bit Decode This bit enables the virtual PCI to PCI bridge to provide 16 bit decoding of VGA 1 0 address precluding the decoding of alias addresses every 1 KB 0 Execute 10 bit address decodes on VGA 1 0 accesses RW 0 1 Execute 16 bit address decodes on VGA I O accesses This bit only has meaning if bit 3 of this register is also set to 1 enabling VGA 1 O decoding and forwarding by the bridge Refer to the Bridge Specification for further details of this bit behavior VGA Enable This bit controls the routing of processor initiated transactions targeting VGA RW 0 bab compatible 1 0 and memory address ranges This bit must only be set for one PCI Express port 50 Datasheet Volume
251. idge header for target decode from primary side Note that if a PCI Express port s IOSE bit is clear that port can still be target of an 1 0 transaction if subtractive decoding is enabled on that port 3 3 3 4 PCI STS PCI Status Register The PCI Status register is a 16 bit status register that reports the occurrence of various events associated with the primary side of the virtual PCI to PCI bridge embedded in PCI Express ports and also primary side of the other devices on the internal Processor Integrated 1 bus Sheet 1 of 2 Register PCISTS Device 0 DMI 3 5 PCIe Function O Offset 06h Bit Attr Default Description Detected Parity Error This bit is set by a device when it receives a packet on the primary side 15 RW1C 0 with an uncorrectable data error or an uncorrectable address control parity error The setting of this bit is regardless of the Parity Error Response bit PERRE in the PCI CMD register Signaled System Error 0 The device did not report a fatal non fatal error 1 The device reported fatal non fatal and not correctable errors it 14 RW1C 0 detected its Express interface through a message to the PCH with SERRE bit enabled Software clears this bit by writing a 1 to it For Express ports this bit is also set when SERR enable bit is set when a FATAL NON FATAL message is forwarded from the Express link to the PCH using a message
252. ilizes a flat memory mapped address space to access device configuration registers This address space is reported by the system firmware to the operating system The register SAD PCIEXBAR defines Datasheet Volume 2 21 m t y Configuration Process and Registers Figure 2 1 22 the base address for the block of addresses below 4 GB for the configuration space associated with busses devices and functions that are potentially a part of the PCI Express root complex hierarchy the SAD PCIEXBAR register there exists controls to limit the size of this reserved memory mapped space 256 MB is the amount of address space required to reserve space for every bus device and function that could possibly exist Options for 128 MB and 64 MB exist in order to free up those addresses for other uses In these cases the number of busses and all of their associated devices and functions are limited to 128 or 64 busses respectively The PCI Express Configuration Transaction Header includes an additional four bits ExtendedRegisterAddress 3 0 between the Function Number and Register Address fields to provide indexing into the 4 KB of configuration space allocated to each potential device For PCI Compatible Configuration Requests the Extended Register Address field must be all zeros Memory Map to PCI Express Device Configuration Space OxFFFFFFF OxFFFFF Ox7FFF 255 Device 31 Function 7 PCI Express Extended Configuration
253. ime out Disable Supported supports disabling completion time out Completion Time out Values Supported This field indicates device support for the optional Completion Time out programmability mechanism This mechanism allows system software to modify the Completion Time out range Bits are one hot encoded and set according to the table below to show time out value ranges supported A device that supports the optional capability of Completion Time out Programmability must set at least two bits Four time values ranges are defined A 50 us to 10 ms B 10 ms to 250 ms C 250 ms to4s D 4sto 64s 3 0 RO 1110b Bits are set according to table below to show time out value ranges supported 0000b Completions Time out programming not supported values is fixed by implementation in the range 50 us to 50 ms 0001b Range 0010b Range B 0011b Range A amp B 0110b Range amp 0111b RangeA B amp 1110b Range B C amp D 1111b Range A B C amp D All other values are reserved Integrated 1 0 supports time out values to 10 ms 64 s Datasheet Volume 2 73 intel 3 3 4 29 Processor Integrated 1 Configuration Registers DEVCTRL2 PCI Express Device Control Register 2 Register Device Function Offset DEVCTRL2 0 DMI 3 5 PCle 0 B8h Bit Attr Default Description 15 6 RO Oh Reserved RW 0 Alternative RID Interpretation ARI Enable When set
254. in response to a page selective invalidation request 100 111 Reserved 56 50 RV 00h Reserved 49 RW Drain Reads uses this to drain or not drain reads an invalidation request 48 RW Drain Writes uses this to drain or not drain writes on an invalidation request 47 32 RW Domain ID Domain to be invalidated and is programmed by software for both page and domain selective invalidation requests ignores the bits 47 40 since it supports only an 8 bit Domain ID RV 00000000h Reserved Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 6 Intel Trusted Execution Technology Intel TXT Register Map Table 3 15 Intel Trusted Execution Technology Registers 80h 84h 88h OCh 8Ch 10h 90h 94h 98h 9Ch AOh A4h A8h ACh BOh B4h TXT STS 00h 04h TXT ESTS TXT THREADS EXISTS TXT THREADS J OINS TXT ERRORCODE 30h TXT Cmd Res 38h et B8h BCh COh C4h CCh 50h DOh 54 D4h 58 D8h 5C DCh 60 EOh 64 E4h 68 E8h 6C ECh 70 FOh 74 F4h 78 F8h 7Ch FCh Datasheet Volume 2 157 Processor Integrated 1 Configuration Registers intel Table 3 16 Intel Trusted Execution Technology Registers cont d TXT VER QPIIF 180h 184h 188h 18Ch 190h 194h 198h 19Ch 1A0h 1A4h 1A8h 1ACh 1BOh 1B4h 1B8h 1BCh 1COh
255. ing forwarding memory including MSI writes or I O transactions and not messages or configuration transactions from the secondary side to the primary side 0 The Bus Master is disabled When this bit is 0 Integrated I O root ports will treat upstream PCI Express memory writes reads 10 writes reads and configuration reads and writes as unsupported requests and follow the rules for handling unsupported requests This behavior is also true towards transactions that are already pending the Integrated 1 0 root port s internal queues when the BME bit is turned off 1 Enables the PCI Express ports to generate forward memory configuration or 1 read write requests RO Memory Space Enable 0 Disables a PCI Express port s memory range registers to be decoded as valid target addresses for transactions from primary side 1 Enables a PCI Express port s memory range registers to be decoded as valid target addresses for transactions from primary side Note that if a PCI Express port s MSE bit is clear that port can still be target of any memory transaction if subtractive decoding is enabled on that port Datasheet Volume 2 99 Processor Integrated 1 Configuration Registers Sheet 2 of 3 Register Device Function Offset PCICMD 8 0 3 04h Bit Attr Default Description RO SERR Enable For PCI Express DMI ports this field enables notifying the inte
256. intel Intel Core i7 800 and i5 700 Desktop Processor Series Datasheet Volume 2 September 2009 Document Number 322165 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining critical control or safety systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Core i7 800 and i5 700 desktop processor series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characteri
257. is bit is set after a system reset the chipset will prevent memory accesses until specifically enabled The software that is authorized to enable the memory accesses 6 RW1C 0 will also be responsible for clearing the secrets from memory Software read chipset specific registers to determine the specific cause of the error The location of those bits is beyond the scope of this specification On a reset if NOP_ACK_WITH_SECRETS is received then this bit is set to 1 On a reset if NOP_ACK_WITHOUT_SECRETS is received then this bit is cleared to 0 This bit must be cleared if a read to FED4_0000h returns a 1 in Bit 0 TXT ALI AS FAULT 5 RWC 0 Set when the platform determines there is an address alias error that could be a security violation Software can clear this bit by writing a 1 to it Reserved 4 RWC 0 This bit is set when the processor issues a write to TXT ESTS SET register with bit 4 1 Reserved 3 RWC 0 This bit is set when the processor issues a write to TXT ESTS SET register with bit 3 1 TXT MEMORY ATTACK 2 RWC 0 This bit is set when there is some illegal read of DRAM This bit is set when the processor issues a write to TXT ESTS SET register with bit 2 1 Software can clear this bit by writing a 1 to it TXT ROGUE STS 1 RW1C 0 The chipset sets this bit to indicate that some thread has left the secure environment improperly TXT POI SON Cycle Received The chipset sets this bit to indicate that the TXT POI SON cycle has
258. is host bridge does not implement this bit This bit is hardwired to a 0 Writes to this bit position have no effect MWIEN Memory Write and I nvalidate Enable 4 RO 0 This host bridge will never issue memory write invalidate commands This bit is therefore hardwired to 0 Writers to this bit position will have no effect SCE Special Cycle Enable 3 RO 0 This host bridge does not implement this bit This bit is hardwired to a 0 Writers to this bit position will have no effect BME Bus Master Enable 2 RO 1 This host bridge is always enabled as a master This bit is hardwired to a 1 Writes to this bit position have no effect MSE Memory Space Enable 1 RO 1 This host bridge always allows access to main memory This bit is not implemented and is hardwired to 1 Writes to this bit position have no effect Access Enable 0 RO 0 This bit is not implemented in this host bridge and is hardwired to 0 Writes to this bit position have no effect Datasheet Volume 2 207 intel 4 4 9 Processor Uncore Configuration Registers PCI STS PCI Status Register The PCI Status register is a 16 bit status register that reports the occurrence of various error events on this device s PCI interface 208 Device 0 Function 0 1 Offset 06h Device 2 Function 0 1 Offset 06h Device 3 Function 0 1 4 Offset 06h Device 4 5 Function 0 3 Offset 06h Bit Attr Default Description
259. is register will be ignored This register is available in both the Public and Private Intel TXT configuration spaces Base TXT TXT Offset 0020h Base TXT PR Offset 0020h Base TXT PB Offset 0020h Bit Attr Default Description TXT THREADS J OI N 63 0 This bit field indicates the threads that exist in the platform Each thread sets its bit in this register by writing a 1 to the corresponding 63 0 RO Oh TXT J OINS SET register How each thread determines which bit to write is platform dependent These bits can be cleared by writing a 1 to the corresponding bit in the OINS CLEAR register Datasheet Volume 2 165 D Processor Integrated 1 Configuration Registers 3 6 1 5 3 6 1 6 166 TXT ERRORCODE Intel TXT Error Code Register When software discovers an error it can write this scratch pad register However the register is sticky and reset only by a power good reset and so allows diagnostic software after the hard reset to determine why the SENTER sequence failed by examining various status bits General Behavioral Rules This is a read only register the public Intel TXT configuration space This register is for read and write in the private Intel TXT configuration space Accesses to this register are done with 1 2 or 4 byte writes and reads The default value of this register is 00000000h Access to this register has no other effect o
260. ister When the write operation begins Section 62 will be shifted in first followed by sections 51 and 40 The index that is programmed into the control register in this case would be 69 62 8 1 Refer to Figure 4 1 4 9 2 MC DIMM RATIO STATUS This register contains status information about DIMM clock ratio Device 3 Function 4 Offset 50h Access as a DWord Bit Attr Default Description 31 29 RO 0 Reserved MAX RATIO Maximum ratio allowed by the part Value Qclk 00000 RSVD 28 24 RO 0 00010 266 MHz 00100 533 MHz 00110 800 MHz 01000 1066 MHz 01010 1333 MHz 23 5 RO 0 Reserved QCLK RATIO Current ratio of Qclk Value Qclk 00000 RSVD 4 0 RO 0 00010 266 MHz 00100 533 MHz 00110 800 MHz 01000 1066 MHz 01010 1333 MHz Datasheet Volume 2 231 intel Processor Uncore Configuration Registers 4 9 3 MC DIMM CLK RATIO Requested DI MM clock ratio Qclk This is the data rate going to the DIMM The clock sent to the DIMM is 1 2 of QCLK rate Device 3 Function 4 Offset 54h Access as a DWord Bit Attr Default Description 31 5 RO 0 Reserved QCLK RATIO Requested ratio of Qclk Bclk 00000 RSVD 00010 266 MHz 550 RW 00100 533 MHz 00110 800 MHz 01000 1066 MHz 01010 1333 MHz 4 9 4 MC_TEST_LTRCON 232 Memory test configuration register Device 3 Function 4 Offset 5Ch Acces
261. isters 226 MC CRDT WR THLD Memory Controller Write Credit Thresholds A Write threshold is defined as the number of credits reserved for this priority or higher request It is required that High threshold be greater than or equal to Crit threshold and that both be lower than the total Write Credit init value BIOS must initialize this register with appropriate values depending on the level of Isoch support in the platform The new values take effect immediately upon being written Register programming rules CRIT threshold value must correspond to the number of critical RTIDs reserved at the IIH HIGH threshold value must correspond to the sum of critical and high RTIDs reserved at the IIH which must not exceed 30 Set MC Channel WAQ PARAMS ISOCENTRYTHRESHHOLD equal to 31 CRIT Device 3 Function O Offset 74h Access as a DWord Bit Attr Default Description 31 13 RO 0 Reserved HI GH DR RW High Credit Threshold 7 5 RO 0 Reserved 4 0 RW 3 CRIT Critical Credit Threshold Datasheet Volume 2 Processor Uncore Configuration Registers 4 8 4 8 1 TAD Target Address Decoder Registers TAD DRAM RULE 0 TAD DRAM RULE 1 TAD DRAM RULE 2 TAD DRAM RULE 3 TAD DRAM RULE 4 TAD DRAM RULE 5 TAD DRAM RULE 6 TAD DRAM RULE 7 TAD DRAM rules Address map for channel determination within a package All addresses sent to this HOME agent must hit a valid enabled DRAM RULE No e
262. itial MRS register values for MR2 The RC fields do not need to be programmed if the address inversion and 3T 1T transitions are disabled Device 4 5 Function O Offset 74h Access as a DWord Bit Attr Default Description 31 24 RO 0 Reserved 23 20 RW 0 Reserved 19 16 RW 0 Reserved MR2 udi RW values to write to MR2 for 15 0 Datasheet Volume 2 243 Processor Uncore Configuration Registers intel 4 10 9 CHANNEL 0 RANK PRESENT MC CHANNEL 1 RANK PRESENT This register provides the rank present vector Device 4 5 Function O Offset 7Ch Access as a DWord Bit Attr Default Description 31 8 RO 0 Reserved RANK PRESENT Vector that represents the ranks that are present Each bit represents a logical rank When two or fewer DI MMs are present 3 0 represents the four possible ranks in DIMMO and 7 4 represents the ranks that are possible in DIMM1 When three DIMMs are present then the following 7 0 RW 0 applies 1 0 represents ranks 1 0 in Slot 0 3 2 represents ranks 3 2 in Slot 1 5 4 represents ranks 5 4 in Slot 2 7 6 represents ranks 7 6 in Slot 3 244 Datasheet Volume 2 Processor Uncore Configuration Registers intel 4 10 10 MC CHANNEL 0 RANK TIMING A MC CHANNEL 1 RANK TIMING A This register contains parameters that specify the rank timing used All parameters are in DCLK Device 4 5 Functio
263. its internal devices device function defined in Table 3 1 Functions Handled by the Processor Integrated 1 0 II O with the Bus number defined in bits 7 0 of this register only Since the processor does not support values other than 00 for the bus number BIOS should set this bit to 1 to prevent the bus number from changing Internal bus number of 110 Integrated 1 This field is used to compare against the bus in the Intel QuickPath Interconnect configuration tx and decide if the access is to the IIO internal 7 0 RW 00h devices or if it goes out to a bus hierarchy below the internal bus This register is programmed once at boot time and does not change after that For the processor the default value of 00h is the only valid setting 3 4 4 11 118 LMMI OL BASE Local MMI OL Base Register LMMIOL BASE Device 8 Function 0 Offset 10Ch Bit Attr Default Description Local MMI OL Base Address This field corresponds to A 31 24 of MMIOL base address An inbound or outbound memory address that satisfies local MMIOL base 15 8 lt A 31 24 lt local MMI OL limit 15 8 is treated as a local peer to peer transaction that 15 8 RW 00h does not cross an Intel QuickPath Interconnect link Setting LMMI OL BASE greater than LMMIOL LIMIT disables local MMIOL peer to peer This register is programmed once at boot time and does not change after that 7 0 RO Oh Reserved Datasheet
264. l VT d remap engine 3 5 2 1 VERSI ON 0 1 Version Number Register Register VTD_VERSION 0 1 Addr MMIO BAR VTBAR Offset 00h 1000h Bit Attr Default Description 31 8 RV Oh Reserved 7 4 RO 1h Major Revision 3 0 RO Oh Minor Revision Datasheet Volume 2 141 intel Processor Integrated O 110 Configuration Registers 3 5 2 2 VTD_CAP 0 1 I ntel VT d Chipset Capabilities Register Sheet 1 of 2 Register VTD_CAP 0 1 Addr MMIO BAR VTBAR Offset 08h 1008h Bit Attr Default Description 63 56 RV 0 Reserved 55 54 RO 11b Reserved Max Address Mask Value MAMV 2348 RO oah 110 supports MAMV value of 9h Off def Number of Fault Recording Registers 47 40 RO m supports 8 fault recording registers for non isochronous Intel VT d engine soch and 1 fault recording register for isochronous Intel VT d engine Oh Isoch 39 RO 1 Page Selective Invalidation Supported in IIO Integrated 1 0 38 RV 0 Reserved 37 34 RO Oh Reserved Fault Recording Register Offset 33 24 RO 10h Fault registers are at offset 100h Off def 5 23 RWO 08h 0 This bit is set to 1 for isochronous Intel VT d engine and 0 for the non else 1 isochronous engine 22 RV 1 Reserved MGAW Off def For non isochronous Intel VT d engine this field is set based on the setting of 21 16 RO 08h 2Fh the Non Isoch GPA
265. lation regardless of the setting of the equivalent bit in the ROOTCON register When clear the fatal errors are only propagated to the Integrated I O core error logic if the equivalent bit in ROOTCTRL register is set 34 Override System Error on PCI Express Non Fatal Error Enable When set non fatal errors on PCI Express that have been successfully propagated to the primary interface of the port are sent to the Integrated RW 0 1 O core error logic for further escalation regardless of the setting of the equivalent bit in the ROOTCON register When clear the non fatal errors are only propagated to the Integrated 1 0 core error logic if the equivalent bit in ROOTCON register is set 33 Override System Error on PCI Express Correctable Error Enable When set correctable errors on PCI Express that have been successfully propagated to the primary interface of the port are sent to the Integrated RW 0 1 O core error logic for further escalation regardless of the setting of the equivalent bit in the ROOTCON register When clear the correctable errors are only propagated to the Integrated 1 0 core error logic if the equivalent bit in ROOTCON register is set 32 ACPI PME Interrupt Enable When set Assert Deassert_PMEGPE messages are enabled to be RW 0 generated when ACPI mode is enabled for handling PME messages from PCI Express When this bit is cleared from a 1 a Deassert_PMEGPE message is scheduled on behalf of the root p
266. link operational speed by restricting the values advertised by the upstream component in its training sequences Dev0 0001b Defined encodings are Dev 3 5 0001b 2 5 Gb s Target Link Speed 3 0 RWS 0010b 0010b 5 Gb s Target Link Speed PD All other encodings are reserved If a value is written to this field that does not correspond to a speed included in the Supported Link Speeds field Integrated 1 0 will default to Gen1 speed This field is also used to set the target compliance mode speed when software is using the Enter Compliance bit to force a link into compliance mode Datasheet Volume 2 75 intel Processor Integrated 1 Configuration Registers 3 3 4 31 LNKSTS2 PCI Express Link Control Register 2 Register LNKSTS2 Device 0 DMI 3 5 PCI e Function 0 Offset C2h Bit Attr Default Description 15 1 RO 0 Reserved Compliance De Emphasis Current de emphasis level when operating at Gen2 speed This is unused in 0 RO 0 1 speed 1b 3 5 dB Ob 6 dB 3 3 4 32 PMCAP Power Management Capabilities Register The PM Capabilities Register defines the capability ID next pointer and other power management related support The following PM registers capabilities are added for software compliance For Device 0 DMI this register should be RO and zero Register PMCAP Device 0 DMI 3 5 PCle Function 0 Offset EOh Bit
267. lot Power Limit Scale register are programmed yet by BIOS Integrated 1 must then be designed to discard a received Set Slot Power Limit message without an error 6 5 RV Oh Reserved Hot Plug is not supported Power Indicator Present RWO Oh When set to 1 this bit indicates that a Power Indicator is implemented for this slot and is electrically controlled by the chassis Attention Indicator Present RWO Oh When set to 1 this bit indicates that an Attention Indicator is implemented for this slot and is electrically controlled by the chassis MRL Sensor Present RWO Oh When set to 1 this bit indicates that an MRL Sensor is implemented on the chassis for this slot Power Controller Present RWO Oh When set to 1 this bit indicates that a software controllable power controller is implemented on the chassis for this slot RV Oh Reserved Hot Plug is not supported 68 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 3 4 24 SLTCON PCI Express Slot Control Register The Slot Control register identifies the PCI Express specific slot control parameters for operations such as Power Management Register SLTCON Device 0 DMI 3 5 PCIe Function O Offset A8h Bit Attr Default Description 15 13 RV Oh Reserved Data Link Layer State Changed Enable 12 RWS 0 When set to 1 this field enables software notification wh
268. lse Master Abort Datasheet Volume 2 285 5 3 2 5 3 3 5 3 4 5 4 5 4 1 286 System Address Map 15 Addresses supports ISA addressing per the PCI PCI Bridge 1 2 Specification ISA addressing is enabled a PCle port using the ISAEN bit in the bridge configuration space Note that when VGAEN bit is set in a PCle port without the VGA16DECEN bit being set the ISAEN bit must be set in all the peer PCle ports in the system CFC CF8 Addresses These addresses are used by legacy operating systems to generate PCI configuration cycles These have been replaced with a memory mapped configuration access mechanism in PCI Express which only PCI Express aware operating systems utilize That said does not explicitly decode these 1 0 addresses and take any specific action These accesses are decoded as part of the normal inbound and outbound I O transaction flow and follow the same routing rules Refer also to Table 5 8 and Table 5 10 for further details of I O address decoding in PCI e Device I O Addresses These addresses could be anywhere the 64KB I O space and are used to allocate I O addresses to PCle devices Each is allocated a chunk of I O address space and there are requirements on how these chunks are distributed amongst 1105 to support peer to peer Refer to Section 5 8 3 for details of these restrictions Each has a couple of IO address range registers LIO and GIO to
269. main memory or a peer PCI Express port which have not been completed 4 RO 0 Reserved Unsupported Request Detected This bit applies only to the root DMI ports This bit indicates that the root port detected an Unsupported Request Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register 0 No unsupported request detected by the root port 3 RO 0 1 Unsupported Request detected at the device port These unsupported requests are NP requests inbound that the root port received and it detected them as unsupported requests for example address decoding failures that the root port detected on a packet receiving inbound lock reads BME bit is clear and so forth Note that this bit is not set on peer to peer completions with UR status that are forwarded by the root port to the PCI Express link Fatal Error Detected This bit applies only to the root DMI ports This bit indicates that a fatal uncorrectable error is detected by the device Errors are logged in this 2 RO 0 register regardless of whether error reporting is enabled or not the Device Control register 0 No Fatal errors detected 1 Fatal errors detected Non Fatal Error Detected This bit applies only to the root DMI ports This bit gets set if a non fatal uncorrectable error is detected by the device Errors are logged in this 1 RO 0 register regardless of whether error reporting is enabled
270. me 2 Processor Integrated 1 110 Configuration Registers ntel 3 5 2 17 PROT_HIGH_MEM_LIMIT 0 1 Protected Memory Limit Base Register Register PROT HIGH MEM LIMIT O 1 Addr MMI O BAR VTBAR Offset 78h 1078h Bit Attr Default Description HPD Limit 2 MB aligned limit address of the high protected DRAM LPD region Note that Intel VT d engine generated reads writes page walk interrupt queue 63 21 RWL 0 invalidation queue read invalidation status themselves are allowed toward this i region but no DMA accesses of any kind from any device is allowed toward this region when enabled This bit may be locked as RO in Intel Trusted Execution Technology Intel TXT mode 20 0 RV 0 Reserved 3 5 2 18 INV_QUEUE_HEAD 0 1 I nvalidation Queue Header Pointer Register Register INV_QUEUE_HEAD 0 1 Addr MMIO BAR VTBAR Offset 80h 1080h Bit Attr Default Description 63 19 RV 0 Reserved Queue Head Specifies the offset 128 bit aligned to the invalidation queue for the command 18 4 RO 0 that will be fetched next by hardware This field is incremented after the command has been fetched successfully and has been verified to be a valid supported command 3 0 RV 0 Reserved 3 5 2 19 INV_QUEUE_TAIL 0 1 I nvalidation Queue Tail Pointer Register Register INV QUEUE TAIL O 1 Addr MMI O BAR VTBAR Offset 88h 1088h Bit Attr Default Description 63 1
271. ment to system DRAM If it is necessary to block inbound access to these ranges a Generic Memory Protection Ranges could be used C D region is used in system DRAM memory for BIOS and option ROM shadowing does not explicitly decode these regions for inbound accesses Software must program one of the system DRAM memory decode ranges that 11 uses for inbound system memory decoding to include these ranges If it is necessary to block inbound access to these ranges the Generic Memory Protection Ranges could be used All outbound accesses to the C F regions are first positively decoded against all valid targets address ranges and if none match these address are forwarded to the subtractive decode port of the 110 110 will complete locks to this range but cannot guarantee atomicity when writes and reads are mapped to separate destinations Address Region between 1 MB and TOLM The ME stolen memory space must be located below Top Of Low Memory TOLM or TOHM ifit needs to be above 4 GB This region is always allocated to system DRAM memory Software must set up one of the coarse memory decode ranges that uses for inbound system memory decoding to include this address range By virtue of that will forward inbound accesses to this region to system memory unless any of these access addresses fall within a protected DRAM range as described in Section 5 2 7 It would be an error for to receive outbound accesses to an add
272. n 0 Offset 80h Access as a DWord Bit Attr Default Description 31 27 RO 0 Reserved tddWrTRd Minimum delay between a write followed by a read to different DIMMs 000 1 001 2 28 26 RW 0 010 3 011 4 100 5 101 6 110 7 111 8 tdrWrTRd Minimum delay between a write followed by a read to different ranks on the same DIMM 000 21 001 25 23 RW 0 010 011 4 100 5 101 6 110 27 111 tsrWrTRd Minimum delay between a write followed by a read to the same rank 0000 10 0001 11 0010 12 0011 13 0100 14 22 19 RW 0 0101 15 0110 16 0111 17 1000 18 1001 19 1010 20 1011 21 1100 22 tddRdTWr Minimum delay between Read followed by a write to different DIMMs 00022 00123 18 15 RW 0 010 4 011 5 100 6 101 7 110 8 111 9 Datasheet Volume 2 245 246 Processor Uncore Configuration Registers Device 4 5 Function 0 Offset 80h Access as a DWord Bit Attr Default Description tdrRdTWr Minimum delay between Read followed by a write to different ranks on the same DIMM 000 001 14 11 RW 0 010 011 5 100 6 101 7 110 8 111 9 tsrRdTWr Minimum delay between Read followed by a write to the same rank 000 RSVD 001 RSVD 10 7 RW 0 010 RSVD 011 5 100 6 101 7 110 8 111 9 tddRdTRd Minimum delay between reads to different DIMMs 000 2 001 3 6 4 RW 0 010 4 011 5 100 6 101 7 110 8 111 9 tdrRdTRd Minimum delay betwee
273. n for reads and writes roll over to zero The read or write and the increment side effect are atomic with respect to other accesses The registers provide firmware with synchronization variables semaphores that are overloaded onto the same physical registers as SR 3 4 5 15 IR 8 11 lI ncrement Registers 8 11 Register IR 8 11 Device 8 Function 1 Offset 160h 16Ch by 4 Bit Attr Default Description Increment These registers are physically mapped to scratch pad registers A read from IR n reads SR n and then increments SR n A write to IR n increments SR n while 31 0 RWLB Oh the write data is unused Increments within SR n for reads and writes roll over to zero The read or write and the increment side effect are atomic with respect to other accesses The registers provide firmware with synchronization variables semaphores that are overloaded onto the same physical registers as SR 3 4 5 16 IR 12 15 I ncrement Registers 12 15 Register IR 12 15 Device 8 Function 1 Offset 170h 17Ch by 4 Bit Attr Default Description Increment These registers are physically mapped to scratch pad registers A read from IR n reads SR n and then increments SR n A write to IR n increments SR n while 31 0 RWLB Oh the write data is unused Increments within SR n for reads and writes roll over to zero The read or write and the increment side effect are atomic with respect to other accesses The registers provide firmware with synchronization va
274. n Posted Requests for PCI Express Gen2 This register controls the number of outstanding inbound non posted requests 1 0 config memory maximum length of these requests is a CL that a Gen1 PCI Express downstream port can have for all non posted requests peer to peer or to main memory it pre allocates buffer space for The value of this parameter for the port when operating in Gen2 width is obtained by multiplying this register by 2 and 4 respectively Software programs this register based on the read RFO latency to main memory A value of 1 indicates one outstanding pre allocated request 2 indicates 2 outstanding pre allocated requests and so on If software programs a value greater than the buffer size the DMA engine supports then the maximum hardware supported value is used RO Reserved RO Reserved RO Reserved AJ us RO CO Reserved RW Enable No Snoop Write Optimization on Writes When set inbound writes to memory with NS 1 will be treated as non coherent no snoops writes on Intel QuickPath Interconnect and pipelined to the processor node Notes 1 This bit should be set to the same value as Bit 2 Enable No Snoop Optimization on reads of this register 2 This must be set for DMI port to support Isoch traffic For PCI Express ports the NS optimization must not be used and this bit should be zero RW Enable No Snoop Optimization on Reads When set
275. n Table Offset 23 8 RO Oh Reserved 7 0 RO Oh Reserved for VC Arbitration Capability VCAC DMI VCCTL DMI Port VC Control BAR DMI RCBAR Register DMIVCCTL Offset 000Ch Bit Attr Default Description 15 4 RO Oh Reserved VC Arbitration Select VCAS This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field The value 000b when written to this field will indicate the VC arbitration 3 1 RW Oh scheme is hardware fixed in the root complex This field cannot be modified when more than one VC in the LPVC group is enabled 000 Hardware fixed arbitration scheme for example Round Robin Others Reserved Refer to the latest PCI Express Base Specification for more details 0 RO Oh Reserved for Load VC Arbitration Table Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 3 6 5 DMI VCORCAP DMI VCO Resource Capability BAR DMIRCBAR Register DMIVCORCAP Offset 0010h Bit Attr Default Description 31 24 RO Oh Reserved for Port Arbitration Table Offset 23 RO 0 Reserved 22 16 RO Oh Reserved for Maximum Time Slots Reject Snoop Transactions REJ SNPT 0 Transactions with or without the No Snoop bit set within the TLP header 15 RO Oh are allowed on this VC 1 Any transaction without the No Snoop bit set within the TLP header will be rejected as an Uns
276. n fatal at the port The internal core error logic of Integrated 1 0 then decides if how to escalate the error further pins message and so forth This bit also controls the propagation of PCI Express ERR FATAL and ERR NONFATAL messages received from the port to the internal Integrated I O core error logic 0 Fatal and Non fatal error generation and Fatal and Non fatal error message forwarding is disabled Fatal and Non fatal error generation and Fatal and Non fatal error message forwarding is enabled Refer to the latest PCI Express Base Specification for details of how this bit is used in conjunction with other control bits in the Root Control register for forwarding errors detected on the PCI Express interface to the system core error logic 1 RO I DSEL Stepping Wait Cycle Control Not applicable to internal Integrated 1 0 devices Hardwired to 0 RO Parity Error Response For PCI Express DMI ports Integrated 1 0 ignores this bit and always does ECC parity checking and signaling for data address of transactions both to and from Integrated 1 0 RO VGA Palette Snoop Enable Not applicable to internal Integrated 1 0 devices Hardwired to 0 RO Memory Write and Invalidate Enable Not applicable to internal Integrated 1 0 devices Hardwired to 0 RO Special Cycle Enable Not applicable to PCI Express Hardwired to 0 RO Bus Master Enable Controls the ability of the PCI Express port in generat
277. n reads to different ranks on the same DIMM 000 2 001 3 3 1 RW 0 010 4 011 5 100 6 101 7 110 8 111 tsrRdTRd Minimum delay between reads to the same rank 0 RW 0 0 4 1 6 Datasheet Volume 2 Processor Uncore Configuration Registers intel 4 10 11 CHANNEL 0 RANK TIMING B MC CHANNEL 1 RANK TIMING B This register contains parameters that specify the rank timing used All parameters are in DCLK Device 4 5 Function 0 Offset 84h Access as a DWord Bit Attr Default Description 31 21 RO 0 Reserved B2B CAS DELAY This field controls the delay between CAS commands in DCLKS The minimum spacing is 4 DCLKS Values below 3 have no effect A value of 0 20 16 RW 0 disables the logic Setting the value between 3 31 also spaces the read data by 0 29 DCLKS The value entered is one less than the spacing required that is a spacing of 5 DCLKS between CAS commands or 1 DCLK on the read data requires a setting of 4 tddWrTWr Minimum delay between writes to different DIMMs 000 2 001 3 010 4 15 13 RW 0 011 5 100 6 10127 110 8 11129 tdrwrTWr Minimum delay between writes to different ranks on the same DI MM 000 22 001 3 010 4 12 10 RW 0 011 5 100 6 101 27 110 28 11129 tsrWrTWr 9 RW 0 Minimum delay between writes to the same rank 0 24 1 26 tRRD 8 6 RW 0 Specifies the minimum time between activate commands to the same rank tFAW 5 0 RW 0 Four Activate Wi
278. n the chipset other than reading or writing the contents of this register Base TXT TXT Offset 0030h Base TXT PR Offset 0030h Base TXT PB noWROffset 0030h Bit Attr Default Description ERRORCODE 31 0 31 0 RWS Oh This register is a scratch pad register and is defined by the software usage model TXT CMD RESET I ntel TXT System Reset Command Register When this command is invoked the chipset resets the entire platform General Behavioral Rules This is a write only register This register is only available in the private Intel TXT configuration space Accesses to this register are done with 1 byte writes The data bits associated with this command are undefined and have no specific meaning Base TXT TXT Offset 0038h Base TXT PR Offset 0038h Bit Attr Default Description 7 0 WO Oh N A Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers L D 3 6 1 7 TXT CMD CLOSE_PRIVATE Intel TXT Close Private Command Register The processor that authenticates the SEXIT code does this to prevent the Intel TXT Private configuration space from being accessed using standard memory read write cycles General Behavioral Rules This is a write only register This register is only available in the Private Intel TXT configuration space Accesses to this register are done with 1 byte writes The data bits associated with thi
279. n the processor 1 0 address space the Configuration Address CONFIG ADDRESS Register and the Configuration Data CONFIG DATA Register The Configuration Address Register enables disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 3 1 Processor Integrated 1 Configuration Registers Processor 110 Devices PCI Bus The processor Integrated I O contains the following PCI devices within a single intel physical component The configuration registers for the devices are mapped as devices residing on PCI Bus O Device 0 DMI Root Port Logically this appears as a PCI device residing on PCI Bus 0 Device 0 contains the standard PCI header registers extended PCI configuration registers and DMI device specific configuration registers Device 3 PCI Express Root Port 1 Logically this appears as a virtual PCI to PCI bridge residing on PCI Bus 0 and is compliant with the PCI Express Local Bus Specification Revision 1 0 Device 3 contains the standard PCI Express PCI configuration registers including PCI Express Memory Address Mapping registers It also contains the extended PCI Express configuration space that include PCI Express error status control registers and I sochronous and Virtual Channel controls Device 5 PCI Express
280. nal bus number of IIOBUSNO or PBN register and is within LCFGBUS BASE LCFGBUS LIMIT and none of the PCle ports is positively decoded and DMI is the subtractive decode port Forward to DMI Forward as Type 01 1 depending on secondary bus number of the port Inbound Configuration enabled and bus is between 1 255 and Bus number does not match the internal bus number of IIOBUSNO or PBN register and is within LCFGBUS BASE LCFGBUS LIMIT and none of the PCle ports is positively decoded and DMI is not the subtractive decode port Master Abort Notes 1 When forwarding Type 0 accesses to DMI any device number the configuration transaction is allowed forwarded Datasheet Volume 2 299 System Address Map intel 5 8 3 300 Intel VT d Address Map Implications Intel VT d applies only to inbound memory transactions Inbound 1 0 and configuration transactions are not affected by Intel VT d Inbound I O configuration and message decode and forwarding happens the same whether Intel VT d is enabled or not For memory transaction decode the host address map in Intel VT d corresponds to the address map discussed earlier in the chapter and all addresses after translation are subject to the same address map rule checking and error reporting as in the non Intel VT d mode There is not a fixed guest address that IIO Intel VT d hardware can rely upon except that the guest domain addresses can
281. nction 4 contains miscellaneous control status registers on power management and throttling Device 16 Intel QuickPath Interconnect Device 16 Function 0 contains the Intel QuickPath Interconnect configuration registers for Intel QuickPath Interconnect Link Device 16 Function 1 contains the routing and protocol Processor Uncore Devices PCI Bus FFh The processor Uncore contains the following devices within a single physical component The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket Bus number is derived by the maximum bus range setting and processor socket number Device 0 Generic processor non core Device 0 Function 0 contains the generic non core configuration registers for the processor and resides at DID Device ID of 2C50 7h Device 0 Function 1 contains the System Address Decode registers and resides at DID of 2C81h Device 2 Intel QuickPath Interconnect Device 2 Function 0 contains the Intel QuickPath Interconnect configuration registers for Intel QuickPath Interconnect Link 0 and resides at DID of 2C90h Device 2 Function 1 contains the physical layer registers for Intel QuickPath Interconnect Link 0 and resides at DID of 2C91h Device 3 Integrated Memory Controller Device 3 Function 0 contains the general registers for the Integrated Memory Controller and resides at DID of 2C98h Device 3 Function 1 contains the Target Ad
282. ndow Specifies the time window in which four activates are allowed the same rank Datasheet Volume 2 247 intel 4 10 12 Processor Uncore Configuration Registers MC CHANNEL O BANK TIMING MC CHANNEL 1 BANK TIMING This register contains parameters that specify the bank timing parameters These values are in DCLK The values in these registers are encoded where noted All of these values apply to commands to the same rank only Device 4 5 Function 0 Offset 88h Access as a DWord Bit Attr Default Description 31 22 RO 0 Reserved 21 17 RW 0 tWTPr Minimum Write CAS to Precharge command delay 16 13 RW 0 tRTPr Minimum Read CAS to Precharge command delay 12 9 RW 0 tRCD Minimum delay between Activate and CAS commands 8 4 RW 0 tRAS Minimum delay between Activate and Precharge commands 3 0 RW 0 tRP Minimum delay between Precharge command and Activate command 4 10 13 MC CHANNEL O REFRESH TIMING 248 MC CHANNEL 1 REFRESH TIMING This register contains parameters that specify the refresh timings Units are in DCLK Device 4 5 Function O Offset 8Ch Access as a DWord Bit Attr Default Description 31 30 RO 0 Reserved tTHROT OPPREF The minimum time between two opportunistic refreshes The ranges should be within tRFC 3 to 4 tRFC Zero is an invalid encoding A value of 1 should be programmed to disable the throttling of opportunistic refreshes By s
283. ned to 13 ROS Oh When set this bit indicates that the has sent the DMI translated Req gt C7 message to the PCH When set this bit indicates that the has sent the DMI translated Req gt C6 12 ROS Oh message to the PCH When set this bit indicates that the has sent the DMI translated Req gt C3 11 ROS Oh message to the PCH 10 ROS Oh When set this bit indicates that the PCH has acknowledged that it is in C7 9 ROS Oh When set this bit indicates that the PCH has acknowledged that it is in C6 8 ROS Oh Indicates that the PCH has acknowledged that it is in C3 7 2 RV 00h Reserved 1 ROS Oh Set when the Integrated 1 0 detects Req CO message on Intel QuickPath Interconnect Can remain set until the next Req C3 6 7 message Indicates that the PCH has acknowledged the ReqCO message by returning the 0 ROS Oh InCO Ack message on DMI Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 4 7 4 CTSTS Throttling Status Register Register CTSTS Device 8 Function 3 Offset F4h Bit Attr Default Description 7 2 RV 00h Reserved Integrated O Throttling Event 1 RW1CS 0 This bit is asserted when a high temperature situation is signalled from the processor uncore logic and reset when de asserted 0 RV 0 Reserved 3 4 7 5 CTCTRL Throttling Control Register Register CTCTRL Device 8 Function 3 Offset F7h Bit Attr Default Desc
284. nfiguration The top of main memory below 4 GB is defined by the Top of Low Memory TOLM Memory between 4 GB and TOHM is extended system memory Since the platform may contain multiple processors the memory space is divided amongst the processors There may be memory holes between each processor s memory regions These system memory regions are either coherent or non coherent A set of range registers the define a non coherent memory region NcMem Base NcMem Limit within the system DRAM memory region shown above System DRAM memory region outside of this range but within the DRAM region shown in table above is considered coherent For inbound transactions positively decodes these ranges using a couple of software programmable range registers Refer to Table 5 8 for details of inbound decoding towards system memory For outbound transactions it would be an error for to receive non coherent accesses to these addresses from Intel QuickPath Interconnect but does not explicitly check for this error condition but would rather forward such accesses to the subtractive decode port if one exists downstream by virtue of subtractive decoding else it is master aborted Refer to Section 5 8 1 for further details Datasheet Volume 2 System Address Map L 5 2 3 Figure 5 2 5 2 3 1 VGA SMM and Legacy C D E F Regions Figure 5 2 shows the memory address regions below 1 MB These regions are legacy access ra
285. nge caused by the OPEN or CLOSE command TXT LOCALI TY1 OPEN STS This bit is set when the TXT CMD OPEN LOCALITY1 command is seen by the chipset It is cleared on reset or when TXT CMD CLOSE LOCALITY1 is seen 15 RO 0 This bit can be used by sw as a positive indication that the command has taken effect Note that hardware should not set or clear this bit until the internal hardware will guarantee that incoming cycles will be decoded based on the state change caused by the OPEN or CLOSE command Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers Sheet 2 of 2 Base TXT_TXT Offset 0000h Base TXT_PR Offset 0000h Base TXT_PB Offset 0000h Bit Attr Default Description TXT LOCALI TY3 OPEN STS This bit is set when the TXT CMD OPEN LOCALITY3 command is seen by the chipset It is cleared on reset or when TXT CMD CLOSE LOCALITY3 is seen 14 RO 0 This bit can be used by sw as a positive indication that the command has taken effect Note that hardware should not set or clear this bit until the internal hardware will guarantee that incoming cycles will be decoded based on the state change caused by the OPEN or CLOSE command 13 RV 0 Reserved 12 RV 0 Reserved TXT MEM CONFI G OK STS TXTMCONFOKSTS This bit indicates whether the chipset has received and accepted the TXT CMD MEM CONFIG CHECKED TXT command This bit is cleared by PCI reset or
286. nges VGA SMM and Legacy C D E F Regions BIOS Shadow 1MB RAM accesses Controlled at 16K 7 granularity in CPU 660000 768 KB Source decoder Controlled by VGA SMM 0B8000h I 736 KB VGA Enable Regions 0BO000h 704 KB and SMM Enable in CPU 0A0000h 640 KB Key VGA SMM Low BIOS System Memory DOS VGA SMM Memory Space Address Region From To VGA 000_000A_0000h 000_000B_FFFFh This legacy address range is used by video cards to map a frame buffer or a character based video buffer By default accesses to this region are forwarded to main memory by the processor However once firmware figures out where the VGA device is in the system it sets up the processor s source address decoders to forward these accesses to the IIO Within IIO if the VGAEN bit is set in the PCI bridge control register BCTRL of a PCle port then transactions within the VGA space defined above are forwarded to the associated port regardless of the settings of the peer to peer memory address ranges of that port If none of the PCle ports have the VGAEN bit set note that per the address map constraints the VGA memory addresses cannot be included as part of the normal peer to peer bridge memory apertures in the root ports then these accesses are forwarded to the subtractive decode port Also refer to the PCI PCI Bridge 1 2 Specificati
287. not go beyond the guest address width specified using the GPA LIMIT register that is it is OS dependent converts all incoming memory guest addresses to host addresses and then applies the same set of memory address decoding rules as described earlier addition to the address map and decoding rules previously discussed also supports an additional memory range called the VTBAR range and this range is used to handle accesses to Intel VT d related chipset registers Only aligned DWord QWord accesses are allowed to this region Only outbound and SMBus J TAG accesses are allowed to this range and also these can only be accesses outbound from Intel QuickPath Interconnect Inbound accesses to this address range are completer aborted by the 110 Datasheet Volume 2
288. not master aborted PCI Express DMI Configuration Registers This section covers the configuration space registers for PCI Express and DMI The first part of this section describes the standard PCI header space from Oh to 3Fh The second part describes the device specific region from 40h to FFh The third part describes the PCI Express enhanced configuration region Other Register Notes Note that in general all register bits in the standard PCI header space offset Oh 3Fh or in any OS visible capability registers that control the address decode like MSE 5 VGAEN or otherwise control transaction forwarding must be treated as dynamic bits in the sense that these register bits could be changed by the OS when there is traffic flowing through the IIO Note that the address register themselves can be Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers treated as static in the sense that they will not be changed without the decode control bits being clear Registers outside of this standard space will be noted as dynamic when appropriate 3 3 2 Configuration Register Map Figure 3 1 DMI Port Device 0 and PCI Express Root Ports Type 1 Configuration Space PM Capability F PCIE Capability M SI Capability Bl SVID SDID Capability CAP PTR P2P FFFh 100h Extended Configuration Space PCI Device PCI Header Dependent
289. ntegrated 1 0 drives 1 5 Hz square wave 11 Off When this register is written the event is signaled using the virtual pins of the Integrated 1 0 over a dedicated SMBus port Integrated I O does not generated the Attention Indicator On Off Blink messages on PCI Express when this field is written to by software 5 0 RV 00h Reserved Datasheet Volume 2 69 Processor Integrated 1 Configuration Registers intel 3 3 4 25 ROOTCON PCI Express Root Control Register The PCI Express Root Control register specifies parameters specific to the root complex port Sheet 1 of 2 Register ROOTCON Device 0 DMI 3 5 PCI e Function O Offset ACh Bit Attr Default Description 15 5 RV Oh Reserved CRS Software Visibility Enable When set to 1 this bit enables the Root Port to return Configuration Request 4 RW Oh Retry Status CRS Completion Status to software If 0 retry status cannot be returned to software Root ports that do not implement this capability must hardwire this bit to Ob PME Interrupt Enable This field controls the generation of MSI interrupts and Intx messages for PME Oh messages 0 Disables interrupt generation for PME messages 1 Enables interrupt generation upon receipt of a PME message as reflected in the PME status bit of the Root Status Register System Error on Fatal Error Enable This field enables notifying the internal core error logic of occurrence o
290. ntrols the duration of ODT activation BL 2 2 19 16 RW 4 MCODT DELAY Controls the delay from Rd CAS to ODT activation This value is tCAS 1 ODT_RD_DURATION 1512 RW 5 Controls the duration of Rd ODT activation This value is BL 2 2 1L8 RW 0 ODT RD DELAY Controls the delay from Rd CAS to ODT activation This value is tCAS tWL 7 4 RW 5 ODT_WR_DURATION Controls the duration of Wr ODT activation value is BL 2 2 3 0 RW 0 ODT_WR_ DELAY Controls the delay from Wr CAS to ODT activation This value is always 0 Datasheet Volume 2 251 intel Processor Uncore Configuration Registers 4 10 18 MC CHANNEL 0 ODT PARAMS2 MC CHANNEL 1 ODT PARAMS2 This register contains parameters that specify Forcing ODT on Specific ranks Device 4 5 Function 0 Offset AOh Access as a DWord Bit Attr Default Description 31 10 RO 0 Reserved 9 RW 0 MCODT_ Writes Drive MC ODT on reads and writes 8 RW 0 FORCE_MCODT Force ODT to always be asserted 7 RW 0 FORCE_ODT7 Force ODT for Rank 7 to always be asserted 6 RW 0 FORCE ODTS6 Force ODT for Rank 6 to always be asserted 5 RW 0 FORCE_ODTS Force ODT for Rank 5 to always be asserted 4 RW 0 FORCE_ODT4 Force ODT for Rank 4 to always be asserted 3 RW 0 FORCE ODT3 Force ODT for Rank to always be asserted 2 RW 0 FORCE ODT2 Force ODT for Rank 2 to always be asserted 1 RW 0 FORCE_ODT1 Force ODT for R
291. o PCI and PCI Express configuration space see Section 2 5 1 0 Mapped Registers Internal configuration registers residing within the processor are partitioned into the device register sets as indicated in Section 2 1 1 and Section 2 1 2 The processor internal registers 1 Mapped Configuration and PCI Express Extended Configuration registers are accessible by the Host processor The registers that reside within the lower 256 bytes of each device can be accessed as byte word 16 bit or DWord 32 bit quantities with the exception of CONFIG ADDRESS which can only be accessed as a DWord All multi byte numeric fields use little endian ordering that is lower addresses contain the least significant parts of the field Registers that reside in bytes 256 through 4095 of each device may only be accessed using memory mapped transactions in DWord 32 bit quantities Some of the processor registers described in this section contain reserved bits these bits are labeled Reserved Software must not modify reserved fields On reads software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value On writes software must ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and then written back Note that the software does not need to perform read merge and w
292. o Section 5 8 1 and Section 5 8 2 Datasheet Volume 2 System Address Map 5 2 1 Figure 5 1 System Address Map System address Map TOCM Privileged 2 51 CSR 2146 Not Used 2 4 Reserved MMIOH relocatable TOHM TOCM DRAM High 240 Memory 1_0000_0000 High Memory 4GB Low Memory 1 MB IRI Compatibility Area F_FFFF E and F 128 K segments E_0000 C and D 128 K Areas are not drawn to scale 0000 VGA SMM 128 0000 640 K 0 variable variable N X 64 MB 0 0000 diis 16MB FEFO 0000 IntA Rsvd 1MB FEEO 0000 LocalxAPIC 1MB FEDO 0000 LegacyLT TPM 1MB FECO 0000 I OxAPIC 1MB LocalCSR CPUOn 1MB FEB0_0000 dirROM Pseg FEA0_0000 Misc CPEI etc 2MB FE80_0000 MMIOL relocatable variable FD00_0000 CPUCSR 16MB 00 0000 Express 64 MMCFG 256 MB relocatable TOLM DRAM Low NOR 64 MB Memory TSeg 512 programmable 8 MB DRAM uns 8MB 10_0000 emory Datasheet Volume 2 277 System Address Map intel 5 2 2 278 System DRAM Memory Regions Address Region From To 640 KB MS DOS Memory 000_0000_0000h 000_0009_FFFFh 1 MB to Top of Low Memory 000_0010_0000h TOLM Bottom of High Memory to Top of 4 GB TOHM High Memory These address ranges are always mapped to system DRAM memory regardless of the system co
293. oder Registers 190 Device 3 Function 2 Memory Controller Test Registers 191 Device 3 Function 4 Integrated Memory Controller Test Registers 192 Device 4 Function 0 Integrated Memory Controller Channel 0 Control Registers sse cid EBEE EPKEN E E PPSP REEE RI RE RUE 193 Device 4 Function 1 Integrated Memory Controller Channel 0 Address Registers secre ee reiten rer dada vae Pete a ra Ves vee ei idu i e Fd p 194 Device 4 Function 2 Integrated Memory Controller Channel 0 Rank ecc 195 Datasheet Volume 2 13 ntel 4 13 Device 4 Function 3 Integrated Memory Controller Channel 0 Thermal Control Register Sissin enen TE es TEO 196 4 14 Device 5 Function 0 Integrated Memory Controller Channel 1 Control Registers iere tem RP ERE be cake 197 4 15 Device 5 Function 1 Integrated Memory Controller Channel 1 Address cus teer t e eae RE X E EPA 198 4 16 Device 5 Function 2 Integrated Memory Controller Channel 1 Rank Registers LI IU ERI MEE E 199 4 17 Device 5 Function 3 Integrated Memory Controller Channel 1 Thermal Control 111 111 nenne eem emen 200 4 18 Padscan Accessible
294. odes all inbound accesses to system memory using two contiguous address ranges 0 TOLM 4 GB TOHM and there cannot be holes created inside of those ranges that are allocated to other system resources in the gap below 4 GB address line The only exception to this is the hole created the low system DRAM memory range using the VGA memory address comprehends this and does not forward these VGA memory regions to system memory Non Coherent Address Space supports one coarse main memory range which be treated as non coherent by 110 that is inbound accesses to this region are treated as non coherent This address range has to be a subset of one of the coarse memory ranges that decodes towards system memory Inbound accesses to the NC range are not snooped on Intel QuickPath Interconnect Datasheet Volume 2 System Address Map L 5 8 5 8 1 5 8 1 1 Address Decoding In general software needs to guarantee that for a given address there can only be a single target in the system Otherwise it is a programming error and results are undefined The one exception is that VGA addresses would fall within the inbound coarse decode memory range The IIO inbound address decoder handles this conflict and forwards the VGA addresses to only the VGA port in the system and not system memory Outbound Address Decoding This section covers address decoding that performs on a transaction from Intel QuickPath
295. oes not support 1 setting of the SNP field in the page table 1010h entries 7 RW 1 offset 1 Hardware supports the 1 setting of the SNP field in the page table entries 10h supports snoop override only for the non isochronous Intel VT d engine 6 RV 1 Reserved Caching hints 5 RO 1 supports caching hints 4 RO 0 Reserved 3 RWO 1 Interrupt Remapping Support supports this 0 offset Reserved 1010h 2 1 offset 10h 1 RWO 1 Queued invalidation Support supports this Coherency Support BIOS can write to this bit to indicate to hardware to either snoop or not snoop 0 RWO 0 the DMA Interrupt table structures in memory root context pd pt irt Note that this bit is expected to be always set to 0 for the Isochronous Intel VT d engine Datasheet Volume 2 143 intel 3 5 2 4 144 Processor Integrated 1 Configuration Registers GLBCMD 0 1 Global Command Register Register GLBCMD 0 1 Addr MMIO BAR VTBAR Offset 18h 1018h Bit Attr Default Description 31 RV 0 Reserved Set Root Table Pointer Software sets this field to set update the root entry table pointer used by hardware The root entry table pointer is specified through the Root entry Table 30 RW 0 Address register Hardware reports the status of the root table pointer set operation through the RTPS field in the Global Status register Clearing this bit has no effect 29 RO 0 Reserved N A
296. olume 2 287 intel 5 5 2 SMM Space Restrictions System Address Map If any of the following conditions are violated the results of SMM accesses are unpredictable and may cause the system to hang 1 The Compatible SMM space must not be set up as cacheable 2 High or TSEG SMM transaction address space must not overlap address space assigned to system DRAM or to any PCI devices including DMI Interface and PCI Express and graphics devices This is a BIOS responsibility 3 Both D OPEN and D CLOSE must not be set to 1 at the same time 4 When TSEG SMM space is enabled the TSEG space must not be reported to the OS as available DRAM This is a BIOS responsibility 5 Any address translated through the GMADR TLB must not target DRAM from A 0000h F FFFFh 5 5 3 SMM Space Combinations When High SMM is enabled G SMRAME 1 SMRAM 1 the Compatible SMM space is effectively disabled Processor originated accesses to the Compatible SMM space are forwarded to PCI Express if VGAEN 1 also depends on MDAP otherwise they are forwarded to the DMI Interface PCI Express and DMI Interface originated accesses are never allowed to access SMM space Table 5 2 SMM Space Table Global Enable High Enable TSEG Enable Compatible C High H TSEG T G SMRAME H SMRAM EN TSEG EN Range Range Range 0 X X Disable Disable Disable 1 0 0 Enable Disable Disable 1 0 1 Enable Disable Enable 1 1 0 Disa
297. on Extended Capability I D ECI D 15 0 RO 0002h Value of 0002 h identifies this linked list item capability structure as being for PCI Express Virtual Channel registers DMI VCCAP1 DMI Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with the DMI port BAR DMI RCBAR Register DMIVCCAP1 Offset 0004h Bit Attr Default Description 31 7 RV 0 Reserved Low Priority Extended VC Count LPEVCC Indicates the number of extended Virtual Channels in addition to the 6 4 RO 0 default VC belonging to the low priority VC LPVC group that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration 3 RO 0 Reserved Extended VC Count EVCC Indicates the number of extended Virtual Channels in addition to the default VC supported by the device The Private Virtual Channel is not included in this count 2 0 RWO 001b Datasheet Volume 2 85 intel 3 3 6 3 3 3 6 4 86 Processor Integrated 1 Configuration Registers DMI VCCAP2 DMI Port VC Capability Register 2 This register Describes the configuration of PCI Express Virtual Channels associated with this port BAR DMI RCBAR Register DMIVCCAP2 Offset 0008h Bit Attr Default Description 31 24 RO Oh Reserved for VC Arbitratio
298. on Sticky 0 Disable 1 Enable stall initialization until this bit is cleared 15 8 RO Reserved 7 6 RWST LLR_TIMEOUT Link Level Retry LLR timeout value in flit cycles Sticky Late action 00 4095 01 1023 10 255 11 63 218 Datasheet Volume 2 Processor Uncore Configuration Registers Device 2 Function 0 Offset 48h Access as a DWord Bit Type Default Description LLR_TO_LINK_RESET Consecutive LLRs to Link Reset Sticky Late action 00 up to 16 5 4 RWST 0 01 up to 8 10 up to 4 11 0 disable LLR if CRC error immediate error condition LINK_RESET_FROM_LLR Consecutive Link Reset from LLR till error condition only applies if LLR enabled Sticky Late action 3 2 RWST 0 00 up to2 01 uptol 10 up to 0 11 Reserved LINK HARD RESET Link Hard Reset 1 RW 0 Re initialize resetting values in sticky registers Write 1 to reset this link This is a destructive reset When reset asserts register clears to Oh LINK SOFT RESET Link Soft Reset 0 RW 0 Re initialize without resetting sticky registers Write 1 to reset this link This is a destructive reset When reset asserts register clears to Oh Datasheet Volume 2 219 tel Processor Uncore Configuration Registers 4 7 Integrated Memory Controller Control Registers 4 7 1 MC CONTROL Primary control register Device 3 Function O Of
299. on These bits correspond to System Address 8 7 6 OFFSET 23 0 RW 0 This value should be subtracted from the current system address to create a contiguous address space within a channel BITS 9 0 ARE RESERVED AND MUST ALWAYS BE SET TO 0 Datasheet Volume 2 263 m t D Processor Uncore Configuration Registers 4 11 4 264 SAG 1 0 MC SAG 1 1 MC SAG CH1 2 SAG 1 3 MC SAG 1 4 MC SAG CHI 5 MC SAG 1 6 5 1 7 Channel Segment Address Registers For each of the 8 interleave ranges they specify the offset between the System Address and the Memory Address and the System Address bits used for level 1 interleave which should not be translated to Memory Address bits The first stage of Memory Address calculation using System Address and the contents of these registers is done by the following algorithm m 39 16 SystemAddress 39 16 25 complement Offset 23 0 m 15 6 SystemAddress 15 6 If Removed 2 Bit 8 removed If Removed 1 Bit 7 removed If Removed 0 Bit 6 removed MemoryAddress 36 6 m 36 6 Removed Div3 Interleave 000 0 None 001 0 2 way 011 0 4 way 000 1 3 way 001 1 6 way All other combinations are not supported Device 5 Function 1 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch Access as a DWord Bit Attr Default Description 31 28 RO 0 Reserved DIVBY3 E RW This bit tells us that the rule is a 3 or
300. on the PCI Type 0 configuration conventions processor registers appear on the PCI bus assigned for the processor socket Bus number is derived by the max bus range setting and processor socket number Table 4 1 Functions Specifically Handled by the Processor Component Register Group DID Device Function Intel QuickPath Architecture Generic Non core 2C51h 0 0 Registers Intel QuickPath Architecture System Address Decoder 2C81h 1 Intel QuickPath Interconnect Link 0 2C90h 0 Intel QuickPath Interconnect Physical 0 2C91h 1 Integrated Memory Controller Registers 2C98h 3 0 Integrated Memory Controller Target Address Decoder 2C99h 1 Integrated Memory Controller Test Registers 2C9Ch 4 Processor Integrated Memory Controller Channel 0 Control 2CAOh 4 0 Integrated Memory Controller Channel 0 Address 2CA1h 1 Integrated Memory Controller Channel 0 Rank 2CA2h 2 Integrated Memory Controller Channel 0 Thermal 2CA3h 3 Control Integrated Memory Controller Channel 1 Control 2CA8h 5 0 Integrated Memory Controller Channel 1 Address 2CA9h 1 Integrated Memory Controller Channel 1 Rank 2CAAh 2 Integrated Memory Controller Channel 1 Thermal 2CABh 3 Control 184 Datasheet Volume 2 Processor Uncore Configuration Registers 4 3 Table 4 2 Detailed Configuration Space Maps Device 0 Function 0 Generic Non core Registers DID VID
301. on From To Legacy HPET TXT TPM Others FEDO 0000h FEDF FFFFh This region covers the High performance event timers TXT registers TPM region and so forth in the PCH All inbound peer to peer accesses to this region are completer aborted by Datasheet Volume 2 System Address Map L 5 2 5 6 5 2 5 7 5 2 5 8 5 2 5 9 Local XAPI C Address Region From To Local XAPIC FEEO 0000h FEEF FFFFh The processor Interrupt space is the address used to deliver interrupts to the processor s Message Signaled Interrupts MSI from PCle devices that target this address are forwarded as Spclnt messages to the processor The processors may also use this region to send inter processor interrupts from one processor to another But is never a recipient of such an interrupt Inbound reads to this address are considered errors are completer aborted by 110 Outbound accesses to this address are considered as errors but does not explicitly check for this error condition but simply forwards the transaction subtractively to its subtractive decode port if one exists downstream High BI OS Area The top 2 MB FFEO 0000h FFFF FFFFh of the PCI Memory Address Range is reserved for System BIOS High BIOS extended BIOS for PCI devices and the A20 alias of the system BIOS The processor begins execution from the High BIOS after reset This region is mapped to DMI Interface so
302. on for further details on the VGA decoding Note that only one VGA device may be enabled per system partition The VGAEN bit in the PCle bridge control register must be set only in one PCle port in a system partition does not support the MDA monochrome display adapter space independent of the VGA space Datasheet Volume 2 279 m System Address Map intel 5 2 3 2 5 2 4 Note 280 The VGA memory address range can also be mapped to system memory in SMM IIO is totally transparent to the workings of this region in the SMM mode All outbound and inbound accesses to this address range are always forwarded to the VGA device by the 110 Refer to Table 5 7 and Table 5 8 for further details of inbound and outbound VGA decoding C D E F Segments The E F region is used for BIOS flash in the early stages of the boot flow and could be mapped to any firmware hub port 2 system E F could also be used to address DRAM from 1 0 device processors have registers to select between addressing BIOS flash and DRAM IIO does not explicitly decode the E F region in the outbound direction and relies on subtractive decoding to forward accesses to this region to the legacy PCH through DMI does not explicitly decode inbound accesses to the E F address region It is expected that the DRAM low range that decodes will be setup to cover the E F address range By virtue of that will forward inbound accesses to the E F seg
303. on granularity through this IIRG field Following are the encoding for the 3 bit field 000 Reserved ignores the invalidation request and reports invalidation complete by clearing the IVT field and reporting 00 in the AIG field 001 Global Invalidation request 010 Domain selective invalidation request The target domain ID must be specified in the DID field 011 Page selective invalidation request The target address mask and invalidation hint must be specified in the Invalidate Address register the domain ID must be provided the DID field 101 111 Reserved 110 ignores the invalidation request and completes the invalidation by clearing the IVT field and reporting 000 in the IAIG field 59 57 RO IOTLB Actual I nvalidation Granularity 1 Hardware reports the granularity at which an invalidation request was proceed through the AIG field at the time of reporting invalidation completion by clearing the IVT field The following are the encoding for the 3 bit IAIG field 000 Reserved This indicates hardware detected an incorrect invalidation request and ignored the request 001 Global Invalidation performed sets this in response to a global invalidation request 010 Domain selective invalidation performed using the domain ID that was specified by software in the DID field 110 sets this in response to a domain selective IOTLB invalidation request 011 IIO sets this
304. ondary and subordinate bus number both inclusive of an Express port is forwarded to the express port I OBAS 1 O Base Register The 1 0 Base register defines an address range that is used by the PCI Express port to determine when to forward 1 transactions from one interface to the other using the following formula IO 5 lt A 15 12 x IO LIMIT The bottom of the defined 1 0 address range will be aligned to a 4 KB 1 KB if EN1K bit is set Refer to the IIOMISCCTRL register for the definition of EN1K bit boundary while the top of the region specified by IO LIMIT will be one less than a 4 KB 1 KB if EN1K bit is set multiple Setting the 1 0 limit less than 1 0 base disables the 1 0 range altogether Register 5 Device 3 5 PCI e Function O Offset 1Ch Bit Attr Default Description 7 4 RW Oh 1 Base Address Corresponds to A 15 12 of the 1 addresses at the PCI Express port When is set Refer to 5 register for definition of EN1K 3 2 RWL Oh bit these bits become RW and allow for 1 K granularity of I O addressing otherwise these are RO 1 Address Capability O RO oh Integrated I O supports only 16 bit addressing In general the I O base register will not be programmed by software without clearing the IOSE bit first Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers L D 3 3 3
305. onditions occurs 8 RW1C 0 e The PCI Express port receives a Completion from PCI Express marked poisoned e The PCI Express port poisons a packet with data If the Parity Error Response Enable bit in Bridge Control Register is cleared this bit is never set 7 RO 0 Fast Back to Back Transactions Capable Not applicable to PCI Express Hardwired to 0 6 RO 0 Reserved 5 RO 0 66 MHz Capability Not applicable to PCI Express Hardwired to 0 4 0 RO Oh Reserved 46 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers L D 3 3 3 21 Note 3 3 3 22 MBAS Memory Base The Memory Base and Memory Limit registers define a memory mapped 1 0 non prefetchable address range 32 bit addresses and the Integrated 1 directs accesses in this range to the PCI Express port based on the following formula MEMORY BASE lt A 31 20 lt MEMORY LIMIT The upper 12 bits of both the Memory Base and Memory Limit registers are read write and corresponds to the upper 12 address bits A 31 20 of 32 bit addresses Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary and the top of the defined memory address range will be one less than a 1 MB boundary Register MBAS Device 3 5 PCle Function 0 Offset 20h Bit Attr Default Description Memory Base Address 15 4 RW Oh This field corresponds to A 31 20 of the memory address on the PCI Express port 3 0 RO Oh Reserve
306. onfiguration Registers 3 7 1 3 7 1 1 3 7 1 2 3 7 1 3 intel Intel QuickPath Interconnect Link Layer Registers The link layer register are defined for the coherent link There is a special attribute on some link layer registers to handle the link layer specific reset The link layer only has hard and soft resets N attribute indicates that the register is reset on a link layer hard reset NN indicates that the register is reset on any link layer reset hard or soft SVI D Subsystem Vendor ID Register SVID Device 16 Function 0 1 Offset 2Ch Bit Attr Default Description Subsystem Vendor Identification 7 0 RWO 00h This field is programmed during boot up to indicate the vendor of the system board After it has been written once it becomes read only SI D Subsystem Device ID Register SID Device 16 Function 0 1 Offset 2Eh Bit Attr Default Description 7 0 RWO 00h Subsystem Identification Number Assigned by the subsystem vendor to uniquely identify the subsystem CAPPTR Capability Pointer The CAPPTR provides the offset to the location of the first device capability in the capability list Register CAPPTR Device 16 Function 0 1 Offset 34h Bit Attr Default Description 7 0 RO 00h F 0 1 Capability Pointer Points to the first capability structure for the device Datasheet Volume 2 177 intel
307. ormance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Active Management Technology requires the computer system to have an Intel R AMT enabled chipset network hardware and software as well as connection with a power source and a corporate network connection Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality It may also require modifications of implementation of new business processes With regard to notebooks Intel AMT may not be available or certain capabilities may be limited over a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see www intel com technology platform technology intel amt Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other
308. ort if an Assert_PMEGPE message was sent earlier from the root port 31 Disable LOs on Transmitter RW 0 When set Integrated I O never puts its tx in LOs state even if OS enables it using the Link Control register 30 RV 0 Reserved 29 cfg_to_en RW 1 Disables enables configuration timeouts independently of other timeouts 28 RO 0 Reserved Datasheet Volume 2 81 Processor Integrated 1 Configuration Registers Sheet 2 of 3 Register MISCCTRLSTS Device 0 DMI 3 5 PCle Function 0 Offset 188h Bit Attr Default Description System Interrupt Only on Link BW Management Status 27 RWS 0 This bit when set will disable generating MSI interrupt on link bandwidth speed and or width and management changes even if MSI is enabled that is will disable generating MSI when LNKSTS Bits 15 and 14 are set Disable EOI Broadcast to this PCI Express link 26 RW 0 When set EOI message will not be broadcast down this PCI Express link When clear the port is a valid target for EOI broadcast Peer to Peer Memory Write Disable 25 RW 0 When set peer to peer memory writes are master aborted otherwise they are allowed to progress per the peer to peer decoding rules 24 RV 1 Reserved Phold Disable 23 RW 0 When set the 110 responds with unsupported request on receiving assert_phold message from PCH and results in gen
309. otherwise all addresses no distinction made are first positively decoded against all target address ranges Valid targets are PCle DMI CSR and Perf Mon device Software has the responsibility to make sure that only one target can ultimately be the target of a given address and will forward the transaction towards that target For outbound transactions when no target is positively decoded the transactions are sent to the downstream DMI port if it is indicated as the subtractive decode port In the processor the DMI is always the subtractive decode port For inbound transactions on the processor when no target is positively decoded the transactions are sent to the subtractive decode port which is DMI For positive decoding the memory decode to each PCle target is governed by Memory Space Enable MSE bit in the device PCI configuration space and 1 0 decode is covered by the 1 0 Space Enable bit in the device PCI configuration space The only exceptions to this rule are the per port external I OxAPIC address range which are decoded irrespective of the setting of the memory space enable Datasheet Volume 2 291 m System Address Map intel bit There is no decode enable bit for configuration cycle decoding towards either a PCle port or the internal CSR configuration space of IIO e The target decoding for internal VTdCSR space is based on whether the incoming CSR address is within the VTdCSR range limit is 8K plus
310. ould never generate I O requests on PCI Express with any of address bits 31 to 16 set The supports PCI configuration addressing up to 256 buses 32 devices per bus and 8 functions per device A single grouping of 256 buses 32 devices per bus and 8 functions per device is referred to as a PCI segment All configuration addressing within an and hierarchies below an must be within one segment does not support being in multiple PCI segments Refer to Section 5 8 3 for address map details when Intel VT d is enabled In debug mode some address bits in the Intel QuickPath Interconnect header are used for passing source information and hence are not decoded for forwarding transactions For the processor the is always the legacy and DMI is always the subtractive decode port Datasheet Volume 2 275 m System Address Map intel 5 2 276 The processor supports PCI Express upper pre fetchable base limit registers This allows the PCI Express unit to claim 1O accesses above 36 bits complying with the PCI Express Spec Addressing of greater than 8 GB is allowed on either the DMI Interface or PCI Express interface The memory controller supports a maximum of 8 GB of DRAM No DRAM memory will be accessible above 8 GB When running in internal graphics mode writes to GMADR range linear range are supported Write accesses to linear regions are supported from DMI only Write accesses to tileX and tileY regions
311. p 3 of interleaves 11 10 RO 0 Reserved 9 8 RW 0 PACKAGE2 Package for group 2 of interleaves 7 6 RO 0 Reserved 5 4 RW 0 PACKAGE1 Package for group 1 of interleaves 2 2 RO 0 Reserved 1 0 RW 0 PACKAGEO Package for group 0 of interleaves Datasheet Volume 2 217 intel Processor Uncore Configuration Registers 4 6 Intel QuickPath I nterconnect Link Registers 4 6 1 QPI QPILCL LO Intel QuickPath Interconnect Link Control Device Function Offset Access as a DWord 2 0 48h Bit Type Default Description 31 22 RO 0 Reserved 21 RW L1 MASTER Indicates that this end of the link is the L1 master This link transmitter bit is an L1 power state master and can initiate an L1 power state transition If this bit is not set then the link transmitter is an L1 power state slave and should respond to L1 transitions with an ACK or NACK If the link power state of L1 is enabled then there is one master and one slave per link The master may only issue single L1 requests while the slave can only issue single L1 Ack or L1 NAck responses for the corresponding request This link transmitter bit is an L1 power state master and can initiate an L1 power state transition If this bit is not set then the link transmitter is an L1 power state slave and should respond to L1 transitions with an ACK or NACK If the link power state of L1 is enabled there is one master and one slave per link The m
312. port peer to peer Refer to Section 5 8 3 for details of these restrictions Each IIO has a couple of configuration bus range registers LCFGBUS and GCFGBUS to support local and Datasheet Volume 2 System Address Map m L 5 5 Note 5 5 1 Table 5 1 remote peer to peer Refer to section Section 5 8 1 and Section 5 8 2 for details of how these registers are used in the inbound and outbound memory configuration message decoding Configuration transactions initiated by the processor on Intel QuickPath Interconnect can have non zero value for address bits 28 and above This is an artifact of the uncore logic in the processor 1105 outbound configuration address decoder must ignore these bits when decoding the PCle configuration space System Management Mode SMM System Management Mode uses main memory for System Management RAM SMM RAM The Processor supports Compatible SMRAM C_SMRAM High Segment HSEG and Top of Memory Segment TSEG System Management RAM space provides a memory area that is available for the Intel SMI handlers and code and data storage This memory resource is normally hidden from the system OS so that the processor has immediate access to this memory space upon entry to SMM Processor provides three SMRAM options Below 1 MB option that supports compatible Intel SMI handlers Above 1 MB option that allows new Intel SMI handlers to execute with write back cacheable SMRAM Optional TSEG are
313. port requires to complete transition from L1 to LO 000 Less than 1 us 001 1 is to less than 2 us RWO 010 010 2 is to less than 4 us 011 4 is to less than 8 us 100 8 is to less than 16 us 101 16 is to less than 32 us 110 32 is to 64 us 111 More than 64 us ll ll ll 14 12 LOs Exit Latency This field indicates the LOs exit latency that is 105 to LO for the PCI Express port 000 Less than 64 ns 001 64 ns to less than 128 ns RWO 011 010 128 ns to less than 256 ns 011 256 ns to less than 512 ns 100 512 ns to less than 1 ns 101 1 is to less than 2 ns 110 2 is to 4 ns 111 More than 4 ns ll 11 10 Active State Link PM Support This field indicates the level of active state power management supported on the given PCI Express port RWO 11 00 Disabled 01 LOs Entry Supported 10 Reserved 11 LOs and L1 Supported Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers Sheet 2 of 2 Register LNKCAP Device 0 DMI 3 5 PCle Function 0 Offset 9Ch Bit Attr Default Description Maximum Link Width This field indicates the maximum width of the given PCI Express Link attached to the port 001000 x8 9 4 RWO 010000b 010000 x16 000100 Reserved Others Reserved This is left as a RWO register for BIOS to update based on the platform usage of the links Dev 3 5 See Maximum Link Speeds Supported
314. ports or integrated devices 13 RO 0 Attention Indicator Present Does not apply to root ports or integrated devices Attention Button Present 12 RO 0 Does not apply to root ports integrated devices 11 9 RO 000 Endpoint L1 Acceptable Latency Does not apply to Integrated 1 0 8 6 RO 000 Endpoint LOs Acceptable Latency Does not apply to Integrated 1 0 5 RO 0 Extended Tag Field Supported Integrated 1 0 devices support only 5 bit tag field 4 3 RO Oh Phantom Functions Supported Integrated 1 0 does not support phantom functions Max Payload Size Supported 2 0 RO 000 Integrated I O supports 256B payloads on Express port and 128 on the reminder of the devices Datasheet Volume 2 107 intel Processor Integrated 1 Configuration Registers 3 4 3 5 DEVCTRL PCI Express Device Control Register The PCI Express Device Control register controls PCI Express specific capabilities parameters associated with the device Sheet 1 of 2 Device 8 Function 0 1 2 Offset 48h Bit Attr Default Description 15 RO Oh Reserved Max_Read_Request_Size 14 12 RO 000 The PCI Express DMI ports in Integrated 1 0 do not generate requests greater than 128B and this field is ignored Enable No Snoop 11 RO 0 Not applicable to root ports since they never set the No Snoop bit for transactions they originate not forwarded from peer to PCI Express This bit has no impact
315. ports two PCI related interfaces DMI and PCI Express The processor is responsible for routing PCI and PCI Express configuration cycles to the appropriate device that is an integrated part of the processor or to one of these two interfaces Configuration cycles to the PCH internal devices and Primary PCI including downstream devices are routed to the PCH using DMI Configuration cycles to both the PCI Express Graphics PCI compatibility configuration space and the PCI Express Graphics extended configuration space are routed to the PCI Express Graphics port device or associated link Figure 2 2 Processor Configuration Cycle Flowchart DW I O Write to CONFIG ADDRESS with bit 31 21 Read Write to CONFIG_DATA Processor Generates Type 1 Access to PCI Express Yes Bus 0 Dev Enabled amp Bus gt SEC BUS Bus lt SUB BUS in Bus 0 Dev 1 Enabled amp Processor Generates DMI 1 Configuration Cycle Device 0 Processor Generates Type 0 Access to PCI Express MCH allows cycle to go to DMI resulting in Master Abort Device 0 Functions 0 Devices 1 amp Dev 1 Enabled amp Function 0 Device 2 amp Dev 2 Enabled amp Function 0 Devices amp Dev n Enabled amp Functions 0 MCH Generates DMI Type 0 Configuration Cycle
316. pplies only to PCI Express DMI ports 0 Disables the 1 address range defined in the IOBASE and I OLIM registers of the PCI to PCI bridge header for target decode from 0 RO 0 primary side 1 Enables the I O address range defined in the IOBASE and IOLI M registers of the PCI to PCI bridge header for target decode from primary side Note that if a PCI Express DMI port s IOSE bit is clear that port can still be target of an 1 0 transaction if subtractive decoding is enabled on that port 3 4 2 4 PCI STS PCI Status Register The PCI Status register is a 16 bit status register that typically reports the occurrence of various events associated with the primary side of the virtual PCI Express device Since these devices are host bridge devices the only field that has meaning is Capabilities List Sheet 1 of 2 Register Device Function Offset PCISTS 8 0 3 06h Bit Attr Default Description 15 RO Detected Parity Error This bit is set by a device when it receives a packet on the primary side with an uncorrectable data error or an uncorrectable address control parity error The setting of this bit is regardless of the Parity Error Response bit PERRE in the PCI CMD register 14 RO Signaled System Error 0 The device did not report a fatal non fatal error 1 The device reported fatal non fatal and not correctable errors it detected on its PCI Express interface Softwa
317. preserves the cached non leaf page table entries corresponding to mappings specified by ADDR and AM fields and performs only a page selective invalidation at the leaf level 5 0 RW Address Mask supports values of 0 9 All other values result in undefined results Datasheet Volume 2 155 intel 3 5 2 29 156 Processor Integrated 1 Configuration Registers I OTLBI NV 0 1 I OTLB I nvalidate Register Register Addr BAR Offset IOTLBI NV 0 1 MMI O VTBAR 208h 1208h Bit Attr Default Description 63 RW I nvalidate I OTLB cache IVT Software requests IOTLB invalidation by setting this field Software must also set the requested invalidation granularity by programming the IIRG field Hardware clears the IVT field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field Software must read back and check the IVT field to be clear to confirm the invalidation is complete When IVT field is set software must not update the contents of this register Invalidate Address register i if it is being used nor submit new IOTLB invalidation requests 62 60 RW 1 OTLB I nvalidation Request Granularity 11 RG When requesting hardware to invalidate the OTLB by setting the IVT field software writes the requested invalidati
318. propriate configuration cycle The processor is responsible for translating and routing the processor s I O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal processor configuration registers DMI or PCI Express 2 2 2 PCI Express Configuration Mechanism PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by PCI Specification Revision 2 3 Express configuration space is divided into a PCI 2 3 compatible region which consists of the first 256 bytes of a logical device s configuration space and a PCI Express extended region that consists of the remaining configuration space The PCI compatible region can be accessed using either the Standard PCI Configuration Mechanism or using the PCI Express Enhanced Configuration Mechanism described in this section The extended configuration registers may only be accessed using the PCI Express Enhanced Configuration Mechanism To maintain compatibility with PCI configuration addressing mechanisms system software must access the extended configuration space using 32 bit operations 32 bit aligned only These 32 bit operations include byte enables allowing only appropriate bytes within the DWord to be accessed Locked transactions to the PCI Express memory mapped configuration address space are not supported All changes made using either access mechanism are equivalent The PCI Express Enhanced Configuration Mechanism ut
319. r information Register INTLIN Device 0 DMI 3 5 PCIe Function O Offset 3Ch Bit Attr Default Description Interrupt Line 7 0 RW 00h This bit is RW for devices that can generate a legacy INTx message and is needed only for compatibility purposes Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 3 3 14 INTPI N I nterrupt Pin Register The INTP register identifies legacy interrupts for INTA INTB INTC and INTD as determined by BIOS firmware Register INTPIN Device 0 DMI 3 5 PCI e Function O Offset 3Dh Bit Attr Default Description INTP Interrupt Pin defines the type of interrupt to generate for the PCI Express Gui Generate INTA 7 0 RWO Olh 010 Generate 011 Generate INTC 100 Generate INTD Others Reserved BI OS configuration Software has the ability to program this register once during boot to set up the correct interrupt for the port 3 3 3 15 PBUS Primary Bus Number Register This register identifies the bus number on the on the primary side of the PCI Express port Register PBUS Device 3 5 PCI e Function O Offset 18h Bit Attr Default Description Primary Bus Number Configuration software programs this field with the number of the bus on 7 0 RW 00h the primary side of the bridge BIOS must program this register to the correct value since Integrated I
320. re clears this bit by writing 1 to it For Express ports this bit is also set when SERR enable bit is set when a FATAL NON FATAL message is forwarded from the Express link 13 RO Received Master Abort This bit is set when a device experiences a master abort condition on a transaction it mastered on the primary interface Integrated 1 0 internal bus Note that certain errors might be detected right at the PCI Express interface and those transactions might not propagate to the primary interface before the error is detected for example accesses to memory above TOCM in cases where the PCI Express interface logic itself might have visibility into TOCM Such errors do not cause this bit to be set and are reported using the PCI Express interface error bits secondary status register Conditions that cause Bit 13 to be set include Device receives a completion on the primary interface internal bus of Integrated 1 with Unsupported Request or master abort completion Status This includes UR status received on the primary side of a Express port on peer to peer completions also Device accesses to holes the main memory address region that are detected by Intel QuickPath Interconnect Source Address Decoder e Other master abort conditions detected on the Integrated I O internal bus Datasheet Volume 2 101 Processor Integrated 1 Configuration Registers Sheet 2 of 2 Re
321. re is a single register which can be accessed in more than one way TXT STS I ntel TXT Status Register This register is used to read the status of the Intel TXT Command Status Engine functional block in the Shortened Product Name General Behavioral Rules This is a read only register so writes to this register will be ignored This register is available in both the Public and Private Intel TXT configuration spaces Sheet 1 of 2 Base TXT_TXT Offset 0000h Base TXT_PR Offset 0000h Base TXT PB Offset 0000h Bit Attr Default Description 31 18 RV Oh Reserved TXT SEQ IN PROGRESS This bit is set when the TXT SEQUENCE START msg is received from a processor 17 RO 0 This bit is cleared when the TXT SEQUENCE DONE msg is received from a processor If this bit is set and the chipset receives another TXT SEQUENCE START message then the chipset treats this as a rogue attack and does TXT_RESET and sets Rogue status bit TXT LOCALI 2 5 5 This bit is set when either the TXT CMD OPEN LOCALITY2 command or the TXT CMD OPEN PRIVATE is seen by the chipset It is cleared on reset or when 16 RO 0 either TXT CMD CLOSE LOCALITY2 or TXT CMD CLOSE PRIVATE is seen This bit can be used by sw as a positive indication that the command has taken effect Note that hardware should not set or clear this bit until the internal hardware will guarantee that incoming cycles will be decoded based on the state cha
322. ress Capability List register enumerates the PCI Express Capability structure in the PCI 3 0 configuration space Function O Register PEGCAPID Device 0 DMI 3 5 PCIe Offset 90h Bit Attr Default Description 7 0 RO 10h Capability ID Provides the PCI Express capability ID assigned by PCI SIG 3 3 4 14 PEGNXTPTR PCI Express Next Pointer Register The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3 0 configuration space Register PEGNXTPTR Device 0 DMI 3 5 PCIe Function 0 Offset 91h Bit Attr Default Description Next Ptr 7 0 RWO EOh This field is set to the PCI PM capability 56 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 3 4 15 PEGCAP PCI Express Capabilities Register The PCI Express Capabilities register identifies the PCI Express device type and associated capabilities Register PEGCAP Device 0 DMI 3 5 PCle Function 0 Offset 92h Bit Attr Default Description 15 14 RV Oh Reserved Interrupt Message Number Applies only to the root ports This field indicates the interrupt message number that is generated for 13 9 RO 00h PM HP events When there are more than one MSI interrupt Number this register field is required to contain the offset between the base Message Data and the MSI Message that is generated when the
323. ress in this region other than snoop requests from Intel QuickPath Interconnect but IIO does not explicitly check for this error condition but would rather forward such accesses to the subtractive decode port by virtue of subtractive decoding Any inbound access that decodes to be within one of the two coarse memory decode windows but has no real DRAM populated for that address will result in a master abort response on PCI Express Datasheet Volume 2 System Address Map L 5 2 4 1 Relocatable TSEG Address Region From To TSEG FEOO_0000h default FE7F_FFFFh default These are system DRAM memory regions that are used for SMM CMM mode operation 110 would completer abort all inbound transactions that target these address ranges 110 should not receive transactions that target these addresses in the outbound direction but 110 does not explicitly check for this error condition but rather subtractively forwards such transactions to the subtractive decode port of the IIO if one exists downstream else it is master aborted The location 1 MB aligned and size from 512 KB to 8 MB in can be programmed by software Figure 5 3 Pre allocated Memory Example for 64 MB DRAM 1 MB VGA 1 MB GTT Stolen and 1 MB TSEG Memory Segments Attributes Comments 0000 0000h 03CF FFFFh R W Available System Memory 61 MB 03DO 0000h 03DF FFFFh SMM Mode Only TSEG Address Range amp Pre allocated Memory
324. riables semaphores that are overloaded onto the same physical registers as SR 132 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 4 5 17 IR 16 17 I ncrement Registers 16 17 Register 18 16 17 Device 8 Function 1 Offset 180h 184h by 4 Bit Attr Default Description Increment These registers are physically mapped to scratch pad registers A read from IR n reads SR n and then increments SR n A write to IR n increments SR n while 31 0 RWLB Oh the write data is unused Increments within SR n for reads and writes roll over to zero The read or write and the increment side effect are atomic with respect to other accesses The registers provide firmware with synchronization variables semaphores that are overloaded onto the same physical registers as SR 3 4 5 18 IR 18 23 I ncrement Registers 18 23 Register 18 18 23 Device 8 Function 1 Offset 188h 19Ch by4 Bit Attr Default Description Increment These registers are physically mapped to scratch pad registers A read from IR n reads SR n and then increments SR n A write to IR n increments SR n while 31 0 RW Oh the write data is unused Increments within SR n for reads and writes roll over to zero The read or write and the increment side effect are atomic with respect to other accesses The registers provide firmware with synchronization variables semaphores that are overloaded onto
325. ription 31 18 RO Oh Reserved L1 Exit Latency EL1 NG 010 Default value of 010b indicates that the exit latency is 2 us to 4 us 14 12 RWO 7h LOs Exit Latency 11 10 RO 11 Active State Link PM Support ASLPMS LOs and L1 entry supported Max Link Width MLW 25 RO oan Indicates the maximum number of lanes supported for this link Max Link Speed MLS an Hardwired to indicate 2 5 Gb s Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 3 6 12 DMILCTRL DMI Link Control This register allows control of DMI BAR DMIRCBAR Register DMILCTRL Offset 0088h Bit Attr Default Description 15 8 RO Oh Reserved Extended Synch EXTSYNC 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Recovery state 7 RW 0 This mode provides external devices for example logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns 6 2 RO Oh Reserved Active State Power Management Support ASPMS This field controls the level of active state power management supported on the given link 1 0 RW 00b 00 Disabled 01 LOs Entry Supported 10 Reserved 11 105 and L1 Entry Supported 3 3 6 13 DMILSTS D
326. ription 7 4 RV 00h Reserved When set this bit enables Force LOs on Tx links on PCI Express when an 3 RW 1h Integrated 1 0 throttling event is signalled If not set this feature is de featured When set throttling of Integrated 1 0 Intel QuickPath Interconnect occurs 2 RW 1h when an Integrated I O throttling event is signalled If not set this feature is de featured 1 RV Oh Reserved 0 RV 0 Reserved 3 5 Intel VT d Memory Mapped Registers Intel VT d registers are all addressed using aligned DWord or aligned QWord accesses Any combination of bits is allowed within a DWord or QWord access The Intel VT d remap engine registers corresponding to the non Isochronous port represented by Device 0 occupy the first 4 K of offset starting from the base address defined by VTBAR register The Intel VT d Isochronous remap engine registers occupies the second 4 K of offset starting from the base address Figure 3 2 Base Address of Intel VT d Remap Engines Isoch VT d VT BAR 8KB Total Non Isoch VT d VT BAR 4KB VT BAR Datasheet Volume 2 137 Processor Integrated 1 Configuration Registers intel 3 5 1 Intel VT d Configuration Register Space Table 3 13 Intel VT d Memory Mapped Registers 00h FFh 1000h 10FFh VER REG 00h 80h INV QUEUE HEAD REG 84h 08h 88h CAP REG INV Q
327. ription Next Ptr 7 0 RWO 90h This field is set to 90h for the next capability list PCI Express capability structure in the chain 3 3 4 8 MSICTRL MSI Control Register Register MSICTRL Device 0 DMI 3 5 PCle Function 0 Offset 62h Bit Attr Default Description 15 9 RV 00h Reserved 8 RO 1 Reserved 64 bit Address Capable 7 RO 0 This field is hardwired to Oh since the message addresses are only 32 bit addresses for example Multiple Message Enable Applicable only to PCI Express ports Software writes to this field to indicate 3 the number of allocated messages which is aligned to a power of two When 6 4 RW 000 MSI is enabled the software will allocate at least one message the device A value of 000 indicates 1 message Any value greater than or equal to 001 indicates a message of 2 Multiple Message Capable 3 1 RO 001 Integrated I O Express ports support two messages for all their internal events MSI Enable The software sets this bit to select platform specific interrupts or transmit MSI 0 RW 0 messages 0 Disables MSI from being generated 1 MSI will be generated when appropriate conditions occur Datasheet Volume 2 53 Processor Integrated 1 Configuration Registers intel 3 3 4 9 MSIAR MSI Address Register The MSI Address Register MSIAR contains the system specific address information to route MSI interrupts f
328. rite operation for the Configuration Address Register Datasheet Volume 2 25 m t D Configuration Process and Registers 2 5 26 In addition to reserved bits within a register the processor contains address locations in the configuration space of the Host Bridge entity that are marked either Reserved or Intel Reserved The processor responds to accesses to Reserved address locations by completing the host cycle When a Reserved register location is read a zero value is returned Reserved registers can be 8 16 or 32 bits in size Registers that are marked as Intel Reserved must not be modified by system software Writes to Intel Reserved registers may cause system failure Reads from Intel Reserved registers may return a non zero value Upon a Full Reset the processor sets its entire set of internal configuration registers to predetermined default states Some register values at reset are determined by external strapping options The default state represents the minimum functionality feature set required to successfully bring up the system Hence it does not represent the optimal system configuration It is the responsibility of the system initialization software usually BIOS to properly determine the DRAM configurations operating parameters and optional system features that are applicable and to program the processor registers accordingly 1 Mapped Registers The processor contains two registers that reside i
329. rnal core error logic of occurrence of an uncorrectable error fatal or non fatal at the port The internal core error logic of Integrated 1 0 then decides if how to escalate the error further pins message and so forth This bit also controls the propagation of PCI Express ERR FATAL and ERR NONFATAL messages received from the port to the internal Integrated I O core error logic 0 Fatal and Non fatal error generation and Fatal and Non fatal error message forwarding is disabled Fatal and Non fatal error generation and Fatal and Non fatal error message forwarding is enabled Refer to the latest PCI Express Base Specification for details of how this bit is used in conjunction with other control bits in the Root Control register for forwarding errors detected on the PCI Express interface to the system core error logic 1 RO I DSEL Stepping Wait Cycle Control Not applicable to internal Integrated 1 0 devices Hardwired to 0 RO Parity Error Response For PCI Express DMI ports Integrated 1 0 ignores this bit and always does ECC parity checking and signaling for data address of transactions both to and from Integrated 1 0 RO VGA Palette Snoop Enable Not applicable to internal Integrated 1 0 devices Hardwired to 0 RO Memory Write and I nvalidate Enable Not applicable to internal Integrated 1 0 devices Hardwired to 0 RO Special Cycle Enable Not applicable to PCI Express Hardwired to 0 RO B
330. rom the root ports and is broken into its constituent fields Register MSIAR Device 0 DMI 3 5 PCle Function 0 Offset 64h Bit Attr Default Description Address MSB 31 20 RW Oh This field specifies the 12 most significant bits of the 32 bit MSI address This field is R W for compatibility reasons only Address Destination ID 19 12 RW 00h This field is initialized by software for routing the interrupts to the appropriate destination Address Extended Destination ID 11 4 RW 00h This field is not used by 1A32 processor and is used in IPF as an address extension Address Redirection Hint 3 RW Oh 0 directed 1 redirectable Address Destination Mode 2 RW Oh 0 physical 1 logical 1 0 RO Oh Reserved 54 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 3 4 10 MSI DR MSI Data Register The MSI Data Register contains all the data interrupt vector related to MSI interrupts from the root ports Register MSIDR Device 0 DMI 3 5 PCle Function 0 Offset 68h Bit Attr Default Description 31 16 RO 0000h Reserved 15 14 RW Oh Reserved 13 12 RW Oh Reserved Delivery Mode 0000 Fixed Trigger Mode can be edge or level 0001 Lowest Priority Trigger Mode can be edge or level 0010 Intel SMI PMI MCA Not supported using MSI of root port 11 8 RW Oh 0011 Reserved Not supported using MSI o
331. rotocol CFC CF8 4 O addresses used by downstream IO devices typically legacy devices The range can be further divided by various downstream ports in the IIO Each downstream port in contains a BAR to decode its 1 0 range Address that falls within this range is forwarded to its respective then subsequently to the downstream port VGA O Addresses Legacy VGA device uses up the addresses 3BOh 3BBh 3COh 3DFh Any PCIe DMI port in can be a valid target of these address ranges if the VGAEN bit in the peer to peer bridge control register corresponding to that port is set besides the condition where these regions are positively decoded within the peer to peer 1 0 address range In the outbound direction at the PCI to PCI bridge part of PCle port direction by default only decodes the bottom 10 bits of the 16 bit 1 0 address when decoding this VGA address range with the VGAEN bit set in the peer to peer bridge control register But when the VGA16DECEN bit is set in addition to VGAEN being set performs a full 16 bit decode for that port when decoding the VGA address range outbound In general on outbound accesses to this space IIO positively decodes the address ranges of all PCle ports per the peer to peer bridge decoding rules refer to the Bridge 1 2 Specification for details When no target is positively identified sends it down its subtractive decode port if one exists e
332. rough the device for example memory transactions forwarded through the Devices 0 p2p bridge to the PCI Express link 4 This bit has no impact on IO transactions forwarded through the device to the PCI Express DMI link 5 This bit has no impact on messages forwarded to through the device for example messages forwarded through a PCI to PCI bridge to PCI Express link Datasheet Volume 2 115 116 Processor Integrated 1 Configuration Registers Sheet 3 of 3 Register DEVHIDE1 Device 8 Function 0 Offset FOh Bit Attr Default Description Hide Dev3 When set hide Device 3 1 This bit has no impact on any configuration transactions that target the secondary side of a device that is a PCI to PCI bridge 2 This bit has no effect on JTAG initiated accesses to corresponding device s configuration space 3 RWL 0 3 This bit has no impact on memory transactions targeting the device or memory transactions forwarded through the device 4 This bit has no impact on IO transactions forwarded through the device to the PCI Express DMI link 5 This bit has no impact on messages forwarded to through the device for example messages forwarded through a PCI to PCI bridge to PCI Express link 2 1 RV 0 Reserved Hide DevO When set hide Device 0 1 This bit has no impact on any configuration transactions that target the secondary side of the PCI to PCI bridge 2 This bit has no effect on J
333. routes specifically Functions Handled by the Processor I ntegrated 1 110 Register Group DID Device Function Comment DMI D131h DT 0 0 PCI Express Root Port 1 D138h 3 0 x16 x8 max link width PCI Express Root Port 3 D13Ah 5 0 x8 max link width Core D155h 8 0 Address mapping Intel VT d System Management Core D156h 8 1 Semaphore and Scratchpad registers Core D157h 8 2 System control status registers Core D158h 8 3 Miscellaneous registers Intel QuickPath Interconnect Port D150h 16 0 Intel QuickPath Interconnect Link Intel QuickPath Interconnect Port D151h 16 1 Intel QuickPath Interconnect Routing and Protocol Unimplemented Devices Functions and Registers Configuration reads to unimplemented functions and devices will return all ones emulating a master abort response There is no asynchronous error reporting when a configuration read master aborts Configuration writes to unimplemented functions and devices will return a normal response to Intel QuickPath nterconnect Software should not attempt or rely on reads or writes to unimplemented registers or register bits Software should also not attempt to modify Reserved bits or any unused bits called out specifically Unimplemented registers return all zeroes when read Writes to unimplemented registers are ignored For configuration writes to these registers the completion is returned with a normal completion status
334. rror will be generated if they do not and memory aliasing will happen Device 3 Function 1 Offset 80h 84h 88h 8Ch 90h 94h 98h 9Ch Access as a DWord Bit Attr Default Description 31 20 RO 0 Reserved LI MI T DRAM rule top limit address 19 6 RW This field must be strictly greater than previous rule even if this rule is d disabled unless this rule and all following rules are disabled Lower limit is the previous rule or 0 if it is the first rule 5 3 RO 0 Reserved MODE DRAM rule interleave mode If a DRAM RULE hits a 3 bit number is used to index into the corresponding interleave list to determine which channel the DRAM belongs to This mode selects how that number is computed 2 1 RW 00 Address bits 8 7 6 01 Address bits 8 7 6 XORed with 18 17 16 10 Address bit 6 MOD3 Address 39 6 Note 6 is the high order bit 11 reserved 0 RW 0 ENABLE Enable for DRAM rule Datasheet Volume 2 227 228 intel Processor Uncore Configuration Registers TAD INTERLEAVE LIST 0 TAD INTERLEAVE LIST 1 TAD INTERLEAVE LIST 2 TAD INTERLEAVE LIST 3 TAD INTERLEAVE LIST 4 TAD INTERLEAVE LIST 5 TAD INTERLEAVE LIST 6 TAD INTERLEAVE LIST 7 TAD DRAM package assignments When the corresponding DRAM RULE hits a 3 bit number determined by mode is used to index into the Interleave List Branches to determine which channel the DRAM request belongs to
335. s 35 0 of memory addressing on its Intel QuickPath Interconnect interface 110 also supports receiving and decoding 64 bits of address from PCI Express Memory transactions received from PCI Express that go above the top of physical address space supported on Intel QuickPath Interconnect which is dependent on the Intel QuickPath Interconnect profile but is always less than or equal to 2740 for are reported as errors by The as a requester would never generate requests on PCI Express with any of Address Bits 63 to 40 set For packets that receives from Intel QuickPath Interconnect and for packets that receives from PCIe the always performs full 64 bit target address decoding This means that for the processor Bits 36 to 63 of the address must be set to all zeros in order for the target address decoder to positively decode and acknowledge the packet The supports 16 bits of I O addressing on its Intel QuickPath Interconnect interface also supports receiving and decoding the full 32 bits of I O address from PCI Express I O transactions initiated by the processor on Intel QuickPath Interconnect can have non zero value for address bits 16 and above This is an artifact of the uncore logic in the processor 110 outbound 1 address decoder must ignore them when decoding the 1 0 address space 1 0 requests received from PCI Express that are beyond 64 KB are reported as errors by IIO IIO as a requester w
336. s as a DWord Bit Attr Default Description 31 27 RO 0 Reserved Link_ Select Selects DDR channel 00 Channel 0 20725 iud 0 01 1 10 Reserved 11 Global Scan Chain 24 5 RO 0 Reserved 4 0 RW 0 Link_ Control Datasheet Volume 2 Processor Uncore Configuration Registers 4 9 5 MC_TEST_PH_CTR Memory test Control Register Device 3 Function 4 Offset 6Ch Access as a DWord Bit Attr Default Description 31 11 RO 0 Reserved 10 8 RW 0 NIT_ MODE Initialization Mode 7 0 RO 0 Reserved 4 9 6 MC TEST PH PIS Memory test physical layer initialization status Device 3 Function 4 Offset 80h Access as a DWord Bit Attr Default Description 31 30 RO 0 Reserved GLOBAL ERROR 29 RO 0 Indication that an error was detected during memory test 28 0 RO 0 Reserved Datasheet Volume 2 233 intel 4 9 7 Processor Uncore Configuration Registers MC TEST PAT GCTR Pattern Generator Control Device 3 Function 4 Offset A8h Access as a DWord Bit Attr Default Description 31 29 RO 0 Reserved EXP LOOP CNT 28 24 RW 6 Sets the length of the test defined as 2 LOOP 23 22 RO 0 Reserved ERROR_COUNT_STALL zs 9 Masks all detected errors until cleared STOP_TEST 20 RWIS 0 Force exit from Loopback Pattern DRIVE_DC_ZERO 13 Na 9 Drive 0 on lanes
337. s available for read or write in the Private Intel TXT configuration space Base TXT TXT Offset 0278h Base TXT PR Offset 0278h Base TXT PB Offset 0278h Bit Attr Default Description TXT SI NI T SI ZE 63 0 Hardware does not use the information contained in this register It is used as a mailbox between two pieces of software 63 0 RW Oh TXT MLE J OI N Intel TXT MLE Join Base Register Holds a pointer to the base address of the SVMM join code used by the RLPs General Behavioral Rules This is a read write register This register is available for read or write in the Public Intel TXT configuration space This register is available for read or write in the Private Intel TXT configuration space Base TXT_TXT Offset 0290h Base TXT_PR Offset 0290h Base TXT_PB Offset 0290h Bit Attr Default Description 63 40 RO Oh Reserved TXT MLE J OI N 39 0 Base address of the MLE join code 39 0 RW Oh Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 6 1 15 TXT HEAP BASE I ntel TXT HEAP Code Base Register This register holds a pointer to the base address for the Intel TXT Heap General Behavioral Rules This is a read write register This register is locked by TXT CMD LOCK BASE When locked this register is updated by private or Intel TXT writes but not public writes This register is available for re
338. s command are undefined and have no specific meaning Base TXT Offset 0048h Base TXT PR Offset 0048h Bit Attr Default Description 7 0 3 6 1 8 TXT VER QPIIF This register provides chipset version information Important to MLE to detect debug chipsets Base TXT Offset 0100h Base TXT PR Offset 0100h Bit Attr Default Description 7 0 chipset revision ID Datasheet Volume 2 167 intel 3 6 1 9 Note 3 6 1 10 168 Processor Integrated 1 Configuration Registers TXT I D Intel TXT Identifier Register This register holds TXT ID for General Behavioral Rules This register is available in both the Public and Private Intel TXT configuration spaces Base TXT TXT Offset 0110h Base TXT PR Offset 0110h Base TXT PB Offset 0110h Bit Attr Default Description TXT I D EXT This is an Extension onto the other ID fields 63 48 RWLBS Oh This register will be locked for access using Intel TXT public space when the TXT CMD LOCK BASE is issued When locked this register is updated by private or Intel TXT writes but not public writes TXT RID Revision ID 47 32 RO Oh This field is revision dependent Refer to the Intel Core i7 800 and i5 700 Desktop Processor Series Specification Update for the value of the Revision ID Register 31 16 RO C002h TXT DI D Device ID C002h TXT
339. s the lower 32 bits of the IIOSLPSTS register field that indicates the number of clocks that the Integrated 1 0 has been put to sleep The 31 0 ROS Oh will clear this register on entry into sleep state and will increment it for every clock that the is asleep This combined with IIOSLPSTS H provides 2744 clocks worth of monitoring or approximately 2 44 1 133 MHz 131941s 36 65 hours maximum Datasheet Volume 2 135 intel 3 4 7 2 3 4 7 3 136 Processor Integrated 1 Configuration Registers IIOSLPSTS Sleep Status High Register Register 11051 5 5 Device 8 Function 3 Offset 68h Bit Attr Default Description 31 12 RV 000h Reserved SLPDUR_H Sleep Duration High This is the upper 12 bits of the IIOSLPSTS register field that indicates the number of clocks that the has been put to sleep The will clear this 11 0 ROS Oh register on entry into sleep state and will increments it for every clock that the is asleep This combined with OSLPSTS L provides 2744 clocks worth of monitoring or approximately 2 44 1 133 MHz 131941s 36 65 hours maximum PMUSTATE Power Management State Register Register PMUSTATE Device 8 Function 3 Offset D8h Bit Attr Default Description 15 RV 00h Reserved 14 ROS Oh Ced set this bit indicates that Intel QuickPath Interconnect has transitio
340. s which may include adjacent sections of the scan chain For example if section 18 which has 11 bits is read out the data register will return section 18 in the lower portion of the 32 bit data register along with data from adjacent sections 9 and 1 in the scan chain The index in this case would be 5271 5261 18 38 11 1 Refer to Figure 4 1 230 Datasheet Volume 2 Processor Uncore Configuration Registers intel A write operation is performed by writing the payload in the data register including mask and halt bits The appropriate scan chain is selected in the scan chain select register The index offset length of section 1 is written into the control register along with the write bit The write is complete when the write bit is cleared The write is complete when the write bit in the control register is cleared by the Integrated Memory Controller For optimization adjacent sections that fit within 32 bits may be written together For example a write to adjacent sections 40 length 11 bits 51 length 11 bits and 62 length 8 bits can be written in one write operation because they area total of 30 bits which fits in the data register without overlap into other sections Section 40 would be shifted eft by 30 bits into the data register Section 51 would be shifted left 20 bits into the data register Section 62 would be shifted left by 8 bits into the data register Bit positions 31 and 30 would be left over as zeros in the data reg
341. se Specification for complete details of how this bit is used in conjunction with other bits to UR errors Fatal Error Reporting Enable This bit applies only to the PCI Express DMI ports The bit controls the reporting of fatal errors that Integrated I O detects the PCI Express DMI interface 0 Reporting of Fatal error detected by device is disabled 2 RO 0 1 Reporting of Fatal error detected by device is enabled Refer to the latest PCI Express Base Specification for complete details of how this bit is used in conjunction with other bits to report errors For the PCI Express DMI ports this bit is not used to control the reporting of other internal component uncorrectable fatal errors at the port unit in any way 108 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers Sheet 2 of 2 Device Function Offset 8 0 1 2 48h Bit Attr Default Description RO Non Fatal Error Reporting Enable This bit applies only to the PCI Express DMI ports The bit controls the reporting of non fatal errors that detects on the PCI Express DMI interface or any non fatal errors that PerfMon detect 0 Reporting of Non Fatal error detected by device is disabled 1 Reporting of Non Fatal error detected by device is enabled Refer to the latest PCI Express Base Specification for complete details of how this bit is used in conjunction with other bits to report errors For the PC
342. sor Integrated 1 Configuration Registers 3 3 4 22 LNKSTS PCI Express Link Status Register The PCI Express Link Status register provides information on the status of the PCI Express Link such as negotiated width training and so forth Sheet 1 of 2 Register Device Function Offset LNKSTS 0 DMI 3 5 PCIe 0 A2h Bit Attr Default Description 15 RW1C Link Autonomous Bandwidth Status This bit is set to 1 by hardware to indicate that hardware has autonomously changed link speed or width without the port transitioning through DL_Down status for reasons other than to attempt to correct unreliable link operation Integrated I O sets this bit when it receives eight consecutive TS1 or TS2 ordered sets with the Autonomous Change bit set Note that if the status bit is set by hardware in the same clock software clears the status bit the status bit should remain set and if MSI is enabled the hardware should trigger a new MSI 14 RW1C Link Bandwidth Management Status This bit is set to 1 by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status a A link retraining initiated by a write of 1b to the Retrain Link bit has completed b Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation Note that if the status bit is set by hardware in the same clock software clears th
343. ss on the PCI Express bridge 3 0 RO 1h Prefetchable Memory Limit Address Capability i Integrated 1 0 sets this field to 01h to indicate 64 bit capability Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 3 3 25 PMBASEU Prefetchable Memory Base Upper 32 bits The Prefetchable Base Upper 32 bits and Prefetchable Limit Upper 32 bits registers are extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers to support a 64 bit prefetchable memory address range Register PMBASEU Device 3 5 PCle Function 0 Offset 28h Bit Attr Default Description Prefetchable Upper 32 bit Memory Base Address This field corresponds to A 63 32 of the memory address that maps to the 31 0 RW 00000000h upper base of the prefetchable range of memory accesses that will be passed by the PCI Express bridge The OS should program these bits based on the available physical limits of the system 3 3 3 26 PMLI MI TU Prefetchable Memory Limit Upper 32 bits Register PMLIMITU Device 3 5 PCle Function 0 Offset 2Ch Bit Attr Default Description Prefetchable Upper 32 bit Memory Limit Address This field corresponds to A 63 32 of the memory address that maps to the 31 0 RW 00000000h upper limit of the prefetchable range of memory accesses that will be passed by the PCI Express bridge OS should program these bits based on the
344. ss range Refer to Section 5 8 1 and Section 5 8 2 for details of inbound and outbound decoding for accesses to this region For the processor LMMI OH range registers define the high memory mapped range GMMI OH BAS LI M must be set to the same value as LMMI OH BASE LI M Datasheet Volume 2 System Address Map L 5 2 6 3 5 2 7 5 3 5 3 1 BIOS Notes on Address Allocation above 4 GB The processor does not support hot added memory Hence no special BIOS actions are required for address allocation above 4 GB to maintain a hole Since IIO supports only a single contiguous address range for accesses to system DRAM above 4 GB BIOS must make sure that there is enough reserved space gap left between the top of high memory and the bottom of the MMI OH region if the system cares about memory hot add This gap can be used to address hot added memory in the system and would fit the constraints imposed by IIO decode mechanism Protected System DRAM Regions supports three address ranges for protecting various system DRAM regions that carry protected OS code or other proprietary platform information The ranges are Intel VT d protected high range Intel VT d protected low range IO Address Space There are four classes of I O addresses that are specifically decoded by the platform 1 1 addresses used for VGA controllers 2 I O addresses used for ISA aliasing 3 1 0 addresses used for the PCI Configuration p
345. ssor Uncore Configuration Registers SAD MCSEG BASE Global register for McSEG address space These are designed to look just like the cores SMRR type registers Device 0 Function 1 Offset 60h Access as a QWord Bit Type Default Description 63 40 RV 0 Reserved BASE ADDRESS 39 19 RW 0 Base address of McSEG Must be 4K aligned space must be power of 2 aligned 18 0 RO 0 Reserved SAD MCSEG MASK Global register for McSEG address space These are designed to look just like the cores SMRR type registers Device 0 Function 1 Offset 68h Access as a QWord Bit Type Default Description 63 40 RV 0 Reserved MASK 39 19 RW 0 Mask of McSEG Space must be power of 2 aligned 18 12 RO 0 Reserved ENABLE 0 15 McSeg Enabled LOCK 19 0 15 McSeg Mask register locked 9 0 RO 0 Reserved Datasheet Volume 2 Processor Uncore Configuration Registers 4 5 9 4 5 10 SAD_MESEG BASE Register for Intel Management Engine Intel ME range base address Device 0 Function 1 Offset 70h Access as a QWord Bit Attr Default Description 63 40 RV 0 Reserved BASE ADDRESS 39 19 RW 0 Base address of Intel ME SEG Must be 4 K aligned space must be power of 2 aligned 18 0 RO 0 Reserved SAD MESEG MASK Register for Intel ME mask Device 0 Function 1 Offset 78h Access as a QWord Bit Attr
346. ster 8 11 Non Sticky Register SR 8 11 Device 8 Function 1 Offset 09Ch OA8h by 4 Bit Attr Default Description Scratch Pad Non Sticky 31 0 RWLB Oh Non sticky scratch pad registers for firmware utilization 128 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 4 5 4 SR 12 15 Scratch Pad Register 12 15 Non Sticky Register SR 12 15 Device 8 Function 1 Offset OACh OB8h by 4 Bit Attr Default Description 31 0 RWLB Oh Scratch Pad Non Sticky uu Non sticky scratch pad registers for firmware utilization 3 4 5 5 SR 16 17 Scratch Pad Register 16 17 Non Sticky Register SR 16 17 Device 8 Function 1 Offset OBCh OCOh by 4 Bit Attr Default Description Scratch Pad Non Sticky 31 0 RWLB Oh Non sticky scratch pad registers for firmware utilization 3 4 5 6 SR 18 23 Scratch Pad Register 18 23 Non Sticky Register SR 18 23 Device 8 Function 1 Offset OC4h 0D8h by 4 Bit Attr Default Description Scratch Pad Non Sticky 31 0 RW Oh Non sticky scratch pad registers for firmware utilization 3 4 5 7 CWR O0 3 Conditional Write Registers 0 3 Register CWR 0 3 Device 8 Function 1 Offset ODCh OE8h by 4 Bit Attr Default Description Conditional Write These registers are physically mapped to scratch pad registers A read from
347. t If it is not set with closed page address decode will be done without setting the autoprecharge bit 1 Reserved CLOSED PAGE 0 RW 0 When set the MC supports a Closed Page policy The default is Open Page but BIOS should always configure this bit 220 Datasheet Volume 2 Processor Uncore Configuration Registers 4 7 2 4 7 3 intel MC SMI DIMM ERROR STATUS SMI DIMM error threshold overflow status register This bit is set when the per DI MM error counter exceeds the specified threshold The bit is reset by BIOS Device 3 Function O Offset 50h Access as a DWord Bit Type Default Description 31 14 RO 0 Reserved REDUNDANCY LOSS FAILING DIMM 13 12 ROS 0 The ID for the failing DIMM when redundancy is lost 11 8 Reserved DIMM_ERROR_OVERFLOW_ STATUS This 8 bit field is the per DIMM error overflow status bits The organization is as follows If there are one or two DIMMS on the channel Bit 0 DIMM 0 Ranks 0 and 1 Channel 0 Bit 1 DIMM 0 Ranks 2 and 3 Channel 0 Bit 2 DIMM 1 Ranks 0 and 1 Channel 0 Bit 3 DIMM 1 Ranks 2 and 3 Channel 0 Bit 4 DIMM 0 Ranks 0 and 1 Channel 1 Bit 5 DIMM 0 Ranks 2 and 3 Channel 1 Bit 6 DIMM 1 Ranks 0 1 Channel 1 Bit 7 DIMM 1 Ranks 2 and 3 Channel 1 7 0 RWOC 0 ll ll MC_SMI_CNTRL System Management Interrupt control register Device 3 Function 0 Offset 54h A
348. t Address 31 2 RW 0 The interrupt address is interpreted as the address of any other interrupt from a PCI Express port 1 0 RO 0 Reserved 3 5 2 12 FLTEVTUPRADDR O 1 Fault Event Upper Address Register Register FLTEVTUPADDR O 1 Addr MMI O BAR VTBAR Offset 44h 1044h Bit Attr Default Description Address 31 0 RW 0 Integrated 1 supports extended interrupt mode and hence implements this register 3 5 2 13 PMEN 0 1 Protected Memory Enable Register Register PMEN 0 1 Addr MMI O BAR VTBAR Offset 64h 1064h Bit Attr Default Description Enable Protected Memory as defined by the PROT LOW HIGH BASE and 31 RWL 0 PROT LOW HIGH LIMIT registers This bit may be locked as RO in Intel TXT mode 30 1 RV 0 Reserved Protected Region Status 0 RO 0 This bit is set by IIO whenever it has completed enabling the protected memory region per the rules stated in the Intel VT d spec Datasheet Volume 2 149 intel Processor Integrated 1 Configuration Registers 3 5 2 14 PROT LOW MEM BASE O0 1 Protected Memory Low Base Register Register PROT LOW 0 1 Addr MMI O BAR VTBAR Offset 68h 1068h Bit Attr Default Description LPD Base 2 MB aligned base address of the low protected DRAM LPD region Note that Intel VT d engine generated reads writes page walk interrupt queue 31 21 RWL 0 invalidation queue read invalidation status themselves are allowed to
349. ter Space upper 32 bits PM BASE LIMIT T Legacy internal bus number should be set to bus 0 CFGBUS 4 Variable From peer to peer Bridge Configuration Register Space for PCle bus number decode VTBAR 1 Variable Decodes the Intel VT d chipset registers Te 4 Variable From four local peer to peer Bridge Configuration Register Space of the PCle port Notes 1 This is listed as 4 1 entries because each of the 4 local peer to peer bridges have their own VGA decode enable bit and local has to comprehend this bit individually for each port and local 110 QPIPVGASAD Valid bit is used to indicate the dual has VGA port or not Summary of Outbound Memory O Configuration Decoding Throughout the tables in this section a reference to a PCle port generically refers to a standard PCle port or a DMI port Integrated 1 0 Module will support configurations cycles that originate only from the processor It may support inbound CFG for debug only Decoding of Outbound Memory Requests from Intel QuickPath I nterconnect from processor or remote Peer to Peer Address Range Conditions 110 Behavior CB_BAR ABAR MBAR VTBAR and remote CB DMA BAR peer to peer access Completer Abort I OxAPIC BAR ABAR VTBAR CB_BAR ABAR MBAR VTBAR and not Forward to that target remote peer to peer access TPM FED4_Oxxx FEDA 7xxx Forward to DMI as TXT_ cycle assuming Processor has no Intel TPM Intel TPM is not supported
350. ters 3 4 6 3 3 4 7 3 4 7 1 intel SYRE System Reset This register controls Integrated 1 0 Reset behavior Any resets produced by a write to this register must be delayed until the configuration write is completed on the initiating interface PCI Express DMI JTAG There is no SOFT RESET bit in this register That function is invoked through the DMI interface There are no Intel QuickPath Interconnect PCI Express gear ratio definitions in this register The Intel QuickPath Interconnect frequencies are specified in the FREQ register The PCI Express frequencies are automatically negotiated in band Register SYRE Device 8 Function 2 Offset OCCh Bit Attr Default Description 31 17 RV 0 Reserved 16 RV 0 Reserved 15 RV 0 Reserved 14 RV 0 Reserved 13 12 RV 0 Reserved RSTMSK 11 RW 0 0 The Integrated I O will perform the appropriate internal handshakes on RSTIN signal transitions to progress through the hard reset 1 Integrated I O ignores RST unaffected by the RST assertion CPURESET 10 RW 0 1 Integrated 1 0 asserts internal reset The clears this bit when the CPURESET timer elapses 9 1 RV 0 Reserved 0 RV 0 Reserved Miscellaneous Registers Dev 8 F 3 IIOSLPSTS 1 Sleep Status Low Register Register lIIOSLPSTS L Device 8 Function 3 Offset 64h Bit Attr Default Description SLPDUR L Sleep Duration Low This i
351. ters contain the initial read credits available for issuing memory reads TAD read credit counters are loaded with the corresponding values at reset and anytime this register is written BIOS must initialize this register with appropriate values depending on the level of Isoch support in the platform It is illegal to write this register while TAD is active has memory requests outstanding as the write will break TAD s outstanding credit count values Register programming rules Total read credits CRDT_RD CRDT_RD_HIGH CRDT_RD_CRIT must not exceed 31 CRDT RD HIGH value must correspond to the number of high RTIDs reserved at the IIH CRDT RD CRIT value must correspond to the number of critical RTIDs reserved at the IIH CRDT RD HIGH CRDT RD must be less than or equal to 13 CRDT RD HIGH CRDT RD CRIT must be less than or equal to 8 CRDT RD CRIT must be less than or equal to 6 Set CRDT RD to 16 CRDT RD CRIT CRDT RD HIGH Maxfor CRDT RD is 15 f Isoch not enabled then CRDT RD HIGH and CRDT RD CRIT are set to O Device 3 Function O Offset 70h Access as a DWord Bit Attr Default Description 31 21 RO 0 Reserved 20 16 RW 3 CRDT_RD_CRIT Critical Read Credits 15 13 RO 0 Reserved CRDT_RD_HIGH 12 8 High Read Credits 7 5 RO 0 Reserved 4 0 RW 13 CRDT RD Normal Read Credits Datasheet Volume 2 225 m L D Processor Uncore Configuration Reg
352. th the appropriate address and destination RANK The command is then issued directly to the DIMM Care must be taken in using this register as there is no enforcement of timing parameters related to the action taken by a DDR3CMD write This register has no effect after CONROL INIT DONE is set Device 4 5 Function O Offset 60h Access as a DWord Bit Attr Default Description 31 29 RO 0 Reserved 28 RW 0 PRECHARGE VALID Indicates current command is for a precharge command 27 RW 0 ACTI VATE_VALID Indicates current command is for an activate command 26 RW 0 Reserved WR_VALID 25 RW 0 Indicates current command is for a write CAS Bit is cleared by hardware on issuance RD_VALID 24 RW 0 Indicates current command is for a read CAS Bit is cleared by hardware on issuance MRS VALID 23 RW 0 Indicates current command is an MRS command Bit is cleared by hardware on issuance RANK 22 20 RW 0 Destination rank for command MRS BA 19 16 RW 0 Bank address portion of the MRS command The MRS BA field corresponds to BA 3 0 MRS ADDR 15 0 RW 0 Address used by the MRS command Datasheet Volume 2 241 intel 4 10 6 4 10 7 242 Processor Uncore Configuration Registers MC CHANNEL 0 REFRESH THROTTLE SUPPORT MC CHANNEL 1 REFRESH THROTTLE SUPPORT This register supports Self Refresh and Thermal Throttle functions Device 4 5 Function O Offset 68h Access as a DWord
353. that the upper subset of this region aliases to 16 MB to 256 KB range The actual address space required for the BIOS is less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that full 2 MB must be considered INTA Rsvd Address Region From To I ntA Others FEFO 0000h FEFF FFFFh This region accommodates architecture specific address regions All inbound accesses to this address region are completer aborted by the All outbound accesses to this address region are subtractively sent to the subtractive decode port of the IIO if one exists downstream Firmware Address Region From To HIGHBIO 00 0000h FFFF FFFFh This ranges starts at FFOO_0000h and ends at FFFF FFFFh It is used for BIOS Firmware Outbound accesses within this range are forwarded to firmware hubs Refer to Section 5 8 1 2 for firmware decoding details in During boot initialization 110 with firmware connected south of it will communicate this on all Intel QuickPath Interconnect ports so that processor hardware can configure the path to firmware does not support accesses to this address range inbound that is those inbound transactions are aborted and a completer abort response is sent back Datasheet Volume 2 283 System Address Map intel 5 2 6 5 2 6 1 5 2 6 2 284 Address Regions above 4 GB High System Memory Address Region From To
354. the base VTBAR e Each PCle DMI port in has one special address range No loopback supported that is a transaction originating from a port is never sent back to the same port and the decode ranges of originating port are ignored in address decode calculations 5 8 1 2 FWH Decoding This section talks about how allows for access to flash memory that is resident below the FWH accesses using an IIO are allowed only from Intel QuickPath Interconnect No accesses from J TAG PCI e indicates presence of bootable FWH to processor if it is with a FWH that contains the boot code below the legacy PCH connected to it All FWH addresses 4 GB 4 GB 16 MB and 1 MB 1 MB 128 K that do not positively decode to PCle ports are subtractively forwarded to its legacy decode port When receives a transaction from Intel QuickPath Interconnect within 4 GB 4 GB 16 MB or 1 MB 1 MB 128 K and there is no positive decode hit against any of the other valid targets if there is a positive decode hit to any of the other valid targets the transaction is sent to that target then the transaction is forwarded to DMI 5 8 1 3 Other Outbound Target Decoding e Other address ranges besides CSR FWH that need to be decoded per PCI e DMI port include the standard peer to peer bridge decode ranges MMIOL 1 0 VGA CONFIG Refer to PCI PCI Bridge 1 2 Specification and PCI
355. the same physical registers as SR Datasheet Volume 2 133 3 4 6 3 4 6 1 3 4 6 2 134 intel Processor Integrated 1 Configuration Registers System Control Status Registers Device 8 Function 2 SYSMAP System Error Event Map Register This register maps the error severity detected by the to one of the system events Register SYSMAP Device 8 Function 2 Offset 09Ch Bit Attr Default Description 31 7 RV 0 Reserved Severity 1 Error Map 010 Generate NMI ds RWS ane 001 Generate SMI 000 No Inband Message 3 RV 0 Reserved Severity 0 Error 010 Generate NMI 2 0 RWS 010 001 5 000 Inband Message GENMCA Generate MCA This register is used to generate an Intel Scalable Memory Interconnect Intel SMI interrupt to the processor by firmware Register GENMCA Device 8 Function 2 Offset OC4h Bit Attr Default Description 31 1 RO 0 Reserved Generate Intel SMI When this bit is set and transition from 0 to 1 Integrated I O dispatches a 0 RWS 0 MCA interrupt defined in the error MCA configuration register to the processor This bit is cleared by hardware when Integrated 1 0 has dispatched MCA to the Intel QuickPath Interconnect link This bit should never be set since the processor does not support MCA Datasheet Volume 2 Processor Integrated 1 110 Configuration Regis
356. tion 15 11 RV 0 Reserved by PCI SIG INTxDisable Interrupt Disable Controls the ability of the PCI Express port to generate INTx messages If this device does not generate interrupts this bit is not implemented and is RO 10 RO 0 If this device generates interrupts this bit is RW and this bit disables the device function from asserting INTx A value of 0 enables the assertion of its INTx signal A value of 1 disables the assertion of its INTx signal Legacy Interrupt mode is enabled 1 Legacy Interrupt mode is disabled FB2B Fast Back to Back Enable 9 RO 0 This bit controls whether or not the master can do fast back to back writes Since this device is strictly a target this bit is not implemented This bit is hardwired to 0 Writes to this bit position have no effect SERRE SERR Message Enable This bit is a global enable bit for this devices SERR messaging This host bridge will 8 RO 0 not implement SERR messaging This bit is hardwired to 0 Writes to this bit position have no effect If SERR is used for error generation then this bit must be RW and enable disable SERR signaling IDSELWCC IDSEL Stepping Wait Cycle Control 7 RO 0 Per the PCI 2 3 specification this bit is hardwired to 0 Writes to this bit position have no effect PERRE Parity Error Response Enable 6 RO 0 Parity error is not implemented in this host bridge This bit is hardwired to 0 Writes to this bit position have no effect VGAPSE VGA palette snoop Enable 5 RO 0 Th
357. to 1b ARI is enabled for the Root Port RW 0 Completion Time out Disable 1 Disables the Completion Time out mechanism for all NP tx that issues on the PCI Express DMI link 0 Completion time out is enabled Software can change this field while there is active traffic in the root port 3 0 RW 0000b Completion Time out Value on NP Tx that I ntegrated 1 Issues PCI Express DMI Devices that support Completion Time out programmability this field allows system software to modify the Completion Time out range The following encodings and corresponding time out ranges are defined 0000b 10 ms to 50 ms 00010 Reserved Integrated 1 0 aliases to 0000b 0010b Reserved Integrated I O aliases to 0000b 0101b 16 ms to 55 ms 0110b 65 ms to 210 ms 1001b 260 ms to 900 ms 10100 1 s to 3 5 s 1101b 4 s to 13s 1110b 17 s to 64 s When the OS selects 17 s to 64 s range the CTOCTRL register further controls the time out value within that range For all other ranges selected by OS the time out value within that range is fixed in Integrated 1 hardware Software can change this field while there is active traffic in the root port 74 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers 3 3 4 30 2 Express Link Control Register 2 Register LNKCON2 Device 0 DMI 3 5 PCle
358. treats the VGA addresses as peer to peer addresses VGA 1 addresses 3BOh 3BBh 3COh 3DFh always are forwarded to the VGA 1 0 agent of the system performs only 16 bit VGA 1 0 address decode inbound Subtractively decoded inbound addresses are forwarded to the subtractive decode port of the 110 Inbound accesses to ME host visible devices HECI2 IDEr and KT Dev18 0 3 are allowed and will not be blocked by e Inbound accesses to FWH TPM VICSR CPUCSR and CPULocalCSR are blocked by 110 completer aborted Datasheet Volume 2 295 intel 5 8 2 2 Table 5 8 296 Summary of I nbound Address Decoding System Address Map Table 5 8 summarizes 10 behavior on inbound memory transactions from any PCle port Note that this table is only intended to show the routing of transactions based on the address and is not intended to show the details of several control bits that govern forwarding of memory requests from a given PCI Express port Refer to the PCI Express Base Specification 2 0 and the registers chapter for details of these control bits Inbound Memory Address Decoding Sheet 1 of 2 Address Range Conditions 110 Behavior Address in Intel ME range in DRAM class TCm over DMI Forward to Intel QuickPath Interconnect Address in Intel ME range in DRAM not class TCm over DMI Master Abort Address outside Intel ME range in DRAM Address within FEE00000h
359. troller Channel Bubble Generator Offsets for DATA FIFO Device 4 5 Function O Offset E8h Access as a DWord Bit Attr Default Description 31 17 RO 0 Reserved 16 14 RW 0 RDPTROFFSET Read FIFO pointer offset 13 10 RW 0 WRTPTROFFSET Write FIFO pointer offset 9 8 RW 0 PTROFFSET FIFO pointer offset 7 0 RW 0 BGOFFSET BG offset Datasheet Volume 2 Processor Uncore Configuration Registers intel 4 11 I ntegrated Memory Controller Channel Address Registers 4 11 1 MC CHO 0 MC DOD CHO 1 Channel 0 DIMM Organization Descriptor Register Device Function Offset 4 1 48h 4Ch 50h 54h Access as a DWord Bit Attr Default Description 31 13 RO 0 Reserved 12 10 RW RANKOFFSET Rank Offset for calculating RANK This corresponds to the first logical rank on the DIMM The rank offset is always programmed to 0 for the DIMM 0 DOD registers DIMM 0 rank offset is always 0 DIMM 1 DOD rank offset is 4 for two DIMMs per channel RW DI MMPRESENT DIMM slot is populated 8 7 RW NUMBANK This field defines the number of real not shadow banks on these DIMMs 00 Four banked 01 Eight banked 10 Sixteen banked 6 5 RW NUMRANK Number of Ranks This field defines the number of ranks on these DIMMs 00 Single Ranked 01 Double Ranked 10 Reserved 4 2 RW NUMROW Number of Rows This field
360. tus GTT Fetches are always decoded at fetch time to ensure not in SMM actually anything above base of TSEG or 640 KB 1 MB Thus they will be invalid and go to address 000C 0000h but that isn t specific to PCI Express or DMI it applies to processor or internal graphics engines Also since the GMADR snoop would not be directly to the SMM space there wouldn t be a writeback to SMM In fact the writeback would also be invalid because it uses the same translation and go to address 000C 0000h Memory Shadowing Any block of memory that can be designated as read only or write only can be shadowed into Processor DRAM memory Typically this is done to allow ROM code to execute more rapidly out of main DRAM ROM is used as a read only during the copy process while DRAM at the same time is designated write only After copying the DRAM is designated read only so that ROM is shadowed Processor bus transactions are routed accordingly Address Map Notes Memory Recovery When software recovers an underlying DRAM memory region that resides below the 4 GB address line that is used for system resources like firmware local APIC and so forth the gap below 4 GB address line it needs to make sure that it does not create system memory holes whereby all the system memory cannot be decoded with two contiguous ranges It is OK to have unpopulated addresses within these contiguous ranges that are not claimed by any system resource dec
361. tus Register Sheet 1 of 2 Register GLBSTS 0 1 Addr MMIO BAR VTBAR Offset 1Ch 101Ch Bit Attr Default Description Translation Enable Status 31 RO 0 When set this bit indicates that translation hardware is enabled and when clear indicates the translation hardware is not enabled 30 RO 0 Set Root Table Pointer Status This field indicates the status of the root table pointer in hardware 29 RO 0 Reserved N A to 28 RO 0 Reserved N A to IIO 27 RO 0 Reserved N A to IIO Queued I nvalidation I nterface Status 26 RO 0 sets this bit once it has completed the software command to enable the queued invalidation interface Till then this bit is 0 Interrupt Remapping Enable Status 25 RO 0 sets this bit once it has completed the software command to enable the interrupt remapping interface Till then this bit is 0 Interrupt Remapping Table Pointer Status This field indicates the status of the interrupt remapping table pointer in 24 RO 0 hardware This field is cleared by hardware when software sets the SIRTP field in the Global Command register This field is set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register 23 0 RV 000000h Reserved 3 5 2 6 ROOTENTRYADD 0 1 Root Entry Table Address Register RegisteR ROOTENTRYADD O 1 Addr MMIO BAR VT
362. ume 2 System Address Map Table 5 8 Inbound Memory Address Decoding Sheet 2 of 2 intel Address Range Conditions 110 Behavior Other Peer to Peer Address within LMMIOL BASE LMMI OL LI MIT or LMMI OH BASE LMMI OH LIMIT and a PCIe port positively decoded as target Forward to the PCI Express port Address within LMMIOL BASE LMMI OL LI MIT or LMMIOH BASE LMMI OH LI MI T and no PCIe port positively decoded as target Forward to DMI Address NOT within LMMI OL BASE LMMI OL LIMI T or LMMI OH BASE LI OH LI MIT but is within GMMI OL BASE GMMI OL LI MI T or GMMI OH BASE GMMI OH LI MIT Forward to Intel QuickPath Interconnect For the processor this is not applicable as GMMI OH and LMMIOH must be programmed to the same values DRAM Memory holes and other non existent 4G lt Address lt TOHM OR 0 lt Address lt TOLM AND address does not decode to any socket in Intel QuickPath Interconnect source decoder Master Abort regions Address TOCM When Intel VT d translation enabled and guest address greater than 2 GPA LIMIT All Else Forward to subtractive decode port Notes 1 Note that VTBAR range would be within the MMIOL range of that IIO never overlap with any DRAM ranges And by that token VTBAR range can 2 CB DMA BAR and I OxAPIC MBAR regions of an overlap with MMIOL MMI OH ranges of that 3 does not support gen
363. ume 2 IR 16 180h IR 17 184h IR 18 188h IR 19 18Ch IR 20 190h IR 21 194h IR 22 198h IR 23 19Ch 95 intel Processor Integrated 1 Configuration Registers Table 3 11 Core Registers Device 8 Function 2 System Control Status Registers 96 DID VID PCISTS PCICMD CCR INTPIN SVID 02Ch CAPPTR 034h INTLIN EXPCAP NXTPTR CAPID DEVCAP DEVSTS DEVCTRL RESERVEDPCI Express Header space Notes 1 CAPPTR points to the first capability block 000h SYSMAP 09Ch 040h 044h 048h 04Ch 050h 054h 058h 05Ch 060h 064h Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers Table 3 12 Core Registers Device 8 Function 3 Miscellaneous Registers DID VID PCISTS PCICMD CCR PMUSTATE D8h IOSLPSTS 1 IIOSLPSTS Datasheet Volume 2 97 intel Processor Integrated 1 Configuration Registers 3 4 2 Standard PCI Configuration Registers 3 4 2 1 VI D Vendor Identification Register Read only Vendor ID Intel value Register VID Device 8 Function 0 3 Offset 00h Bit Attr Default Description Vendor Identification Number VI D 15 0 RO PCI Standard Identification for Intel 3 4 2 2 DI D Device Identification Register Register DID Device 8 Function 0 3 Offset 02h Bit
364. unction 0 Offset 58h Access as a DWord Bit Attr Default Description 31 27 RO 0 Reserved 26 RV 0 Reserved 25 RV 0 Reserved 24 RV 0 Reserved 23 RV 0 Reserved 22 RV 0 Reserved WRDQDQS DELAY 21 17 RW 15 Specifies the delay in DCLKs between reads and writes for WRDQDQS training WRLEVEL DELAY Specifies the delay used between write CAS indications for write leveling 16 RW 0 training 0 16 DCLKs 1 2 32 DCLKs 15 RV 0 Reserved PHY_FSM_DELAY Global timer used for bounding the physical layer training If the timer 14 10 RW 0 expires the FSM will go to the next step and the counter will be reloaded with PHY FSM DELAY value Units are 2 n dclk BLOCK CKE DELAY 9 5 RW 0 Delay in ns from when clocks and command are valid to the point CKE is allowed to be asserted Units are in 2 n uclk 3 0 RW 0 RESET_ON_TI ME Reset will be asserted for the time specified Units 2 Uclk Datasheet Volume 2 239 intel 4 10 4 240 Processor Uncore Configuration Registers MC CHANNEL 0 DIMM INIT STATUS MC CHANNEL 1 DIMM INIT STATUS The initialization state is stored in this register This register is cleared on a new training command Device 4 5 Function 0 Offset 5Ch Access as a DWord Bit Attr Default Description 31 10 RO 0 Reserved RCOMP CMPLT 9 RO 0 When set indicates that RCOMP command has complete This bit is cleared by hardware on command issuance and set on
365. unction 0 2 Offset OCh Bit Attr Default Description Cacheline Size 7 0 RW 0 This register is set as RW for compatibility reasons only Cacheline size for Integrated 1 0 is always 64B hardware ignore this setting Datasheet Volume 2 103 intel 3 4 2 8 3 4 2 9 3 4 2 10 3 4 2 11 104 Processor Integrated 1 Configuration Registers HDR Header Type Register This register identifies the header layout of the configuration space Register HDR Device 8 Function 0 3 Offset OEh Bit Attr Default Description Multi function Device 7 RO 1b This bit is set to 0 for Single Function Devices and 1 for multi function devices Configuration Layout 6 0 RO 00h This field identifies the format of the configuration header layout 1 for all PCI Express ports and Type 0 for DMI devices SVI D Subsystem Vendor ID Register SVID Device 8 Function 0 3 Offset 2Ch Bit Attr Default Description Subsystem Vendor Identification 7 0 RWO Oh This field is programmed during boot up to indicate the vendor of the system board After it has been written once it becomes read only SI D Subsystem Device I D Register SID Device 8 Function 0 3 Offset 2Eh Bit Attr Default Description 7 0 RWO 00h Subsystem Identification Number Assigned by the subsystem vendor to uniquely identify the subsystem CAPPTR
366. upported Request 14 8 RO Oh Reserved Port Arbitration Capability PAC 7 0 RO Olh Having only Bit 0 set indicates that the only supported arbitration scheme for this VC is non configurable hardware fixed 3 3 6 6 DMI VCORCTL DMI VCO Resource Control Controls the resources associated with PCI Express Virtual Channel 0 BAR DMIRCBAR Register DMIVCORCTL Offset 0014h Bit Attr Default Description 31 RO 1 Virtual Channel 0 Enable VCOE For VCO this is hardwired to 1 and read only as VCO can never be disabled 30 27 RO Oh Reserved Virtual Channel I D VCOI D 26 24 RO Oh Assigns a VC ID to the VC resource For VCO this is hardwired to 0 and read only 23 20 RO Oh Reserved Port Arbitration Select PAS Configures the VC resource to provide a particular Port Arbitration service 19 17 RW Oh Valid value for this field is a number corresponding to one of the asserted bits the Port Arbitration Capability field of the VC resource Because only bit 0 of that field is asserted This field will always be programmed to 1 16 8 RO Oh Reserved Traffic Class Virtual Channel 0 Map TCVCOM Indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values 7 1 RW 7Fh For example when Bit 7 is set in this field TC7 is mapped to this VC resource When more than one bit in this field is set it indicates that multiple TCs are mapp
367. us Master Enable Controls the ability of the PCI Express port in generating forwarding memory including MSI writes or I O transactions and not messages or configuration transactions from the secondary side to the primary side 0 The Bus Master is disabled When this bit is 0 Integrated I O root ports will treat upstream PCI Express memory writes reads 10 writes reads and configuration reads and writes as unsupported requests and follow the rules for handling unsupported requests This behavior is also true towards transactions that are already pending the Integrated I O root port s internal queues when the BME bit is turned off 1 Enables the PCI Express ports to generate forward memory configuration or 1 read write requests RO Memory Space Enable 0 Disables a PCI Express port s memory range registers to be decoded as valid target addresses for transactions from primary side 1 Enables a PCI Express port s memory range registers to be decoded as valid target addresses for transactions from primary side Note that if a PCI Express port s MSE bit is clear that port can still be target of any memory transaction if subtractive decoding is enabled on that port 100 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers Sheet 3 of 3 Register PCICMD Device 8 Function 0 3 Offset 04h Bit Attr Default Description Space Enable A
368. ward this region but no DMA accesses of any kind from any device is allowed toward this region when enabled This bit may be locked as RO in Intel TXT mode 20 0 RV 0 Reserved 3 5 2 15 PROT LOW MEM LIMIT 0 1 Protected Memory Low Limit Register Register PROT LOW MEM LIMI T 0 1 Addr MMI O BAR VTBAR Offset 6Ch 106Ch Bit Attr Default Description LPD Limit 2 MB aligned limit address of the low protected DRAM LPD region Note that Intel VT d engine generated reads writes page walk interrupt queue 31 21 RWL 0 invalidation queue read invalidation status themselves are allowed toward this region but no DMA accesses of any kind from any device is allowed toward this region when enabled This bit may be locked as RO in Intel TXT mode 20 0 RV 0 Reserved 3 5 2 16 PROT HIGH MEM BASE O0 1 Protected Memory High Base Register Register PROT HIGH MEM 0 1 Addr MMI O BAR VTBAR Offset 70h 1070h Bit Attr Default Description HPD Base 2 MB aligned base address of the high protected DRAM LPD region Note that Intel VT d engine generated reads writes page walk interrupt queue 63 21 RWL 0 invalidation queue read invalidation status themselves are allowed toward this region but no DMA accesses of any kind from any device is allowed toward this region when enabled This bit may be locked as RO in Intel TXT mode 20 0 RV 0 Reserved 150 Datasheet Volu
369. ween 1105 Refer to Section 5 8 3 for details of these restrictions Each has a couple of MMIOL address range registers LMMI OL and GMMIOL to support local peer to peer in the MMIOL address range Refer to Section 5 8 for details of how these registers are used in the inbound and outbound MMI OL range decoding Miscellaneous This region is used by the processor for miscellaneous functionality including an address range that software can write to generate CPEI message on Intel QuickPath Interconnect and so forth IIO aborts all inbound accesses to this region Outbound accesses to this region is not explicitly decoded by IIO and are forwarded to downstream subtractive decode port if one exists by virtue of subtractive decoding else it is master aborted Address Region From To Misc FE80 0000h FE9F FFFFh Processor Local CSR On die ROM and Processor PSeg Address Region From To processor Local CSR and PSeg FEBO 0000h FEBF FFFFh This region accommodates processor s local CSRs on die ROM and PSeg IIO will block all inbound accesses from PCle to this address region and return a completer abort response Outbound accesses to this address range are not part of the normal programming model and subtractively sends such accesses to the subtractive decode port of the IIO if one exists downstream else Master Abort Legacy HPET TXT TPM Others Address Regi
370. when forwarding to DMI Type 0 transaction with any device number is required to be forwarded by IIO unlike the standard PCI Express root ports Table 5 7 details behavior when no target has been positively decoded for an outgoing 1 transaction from Intel QuickPath Interconnect Inbound Address Decoding Subtractive Decoding of Outbound 1 Requests from Intel QuickPath I nterconnect Conditions 110 Behavior ange No valid target decoded and one of the Forward to downstream subtractive Any 1 0 A address not downstream ports is the subtractive decode port decode port positively No valid target decoded and none of the decoded downstream ports is the subtractive decode port Master Abort Datasheet Volume 2 System Address Map L 5 8 2 Inbound Address Decoding This section covers the decoding that is done on any transaction that is received on a PCle or DMI 5 8 2 1 Overview All inbound addresses that fall above the top of Intel QuickPath Interconnect physical address limit are flagged as errors by IIO Top of Intel QuickPath Interconnect physical address limit is dependent on the Intel QuickPath Interconnect profile e Inbound decoding towards main memory in happens in two steps The first step involves a coarse decode towards main memory using two separate system memory window ranges 0 TOLM 4 GB TOHM that can be setup by software These ranges are non overlapping The se
371. y Interrupt Mode Enable Disable 9 RO 0 Fast Back to Back Enable Not applicable Hardwired to 0 SERR Enable For PCI Express DMI ports this field enables notifying the internal core error logic of occurrence of an uncorrectable error fatal or non fatal at the port The internal core error logic of Integrated 1 0 then decides if how to escalate the error further pins message and so forth This bit also controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL messages received from the port to the internal Integrated 1 0 core error 8 RW 0 logic 0 Fatal and Non fatal error generation and Fatal and Non fatal error message forwarding is disabled 1 Fatal and Non fatal error generation and Fatal and Non fatal error message forwarding is enabled Refer to the latest PCI Express Base Specification for details of how this bit is used in conjunction with other control bits in the Root Control register for forwarding errors detected on the PCI Express interface to the system core error logic I DSEL Stepping Wait Cycle Control 7 RO 0 Not applicable to Processor Integrated 1 0 devices Hardwired to 0 Parity Error Response For PCI Express DMI ports Processor Integrated 1 ignores this bit and 6 RW 0 always does ECC parity checking and signaling for data address of transactions both to and from 110 This bit though affects the setting of Bit 8 in the PCISTS register VGA Palette Snoop Enable 5 RO 0 Not applicable to Processor Integrate
372. ze aligned Reads of this field returns value that was last programmed to it 1A32 Extended Interrupt Enable mode is not supported 32 system is 11 RO 0 operating in legacy 32 interrupt mode Hardware interprets only 8 bit APICID in the Interrupt Remapping Table entries 10 4 RV 0 Reserved Size This field specifies the size of the interrupt remapping table The number of entries in the interrupt remapping table is 2 1 where X is the value programmed in this field 3 0 RW 0 154 Datasheet Volume 2 Processor Integrated 1 110 Configuration Registers intel 3 5 2 27 FLTREC 10 7 0 Fault Record Register FLTREC 10 register is for the Isochronous Intel VT d engine and 7 0 registers are for non isochronous Intel VT d engine Register FLTREC 10 7 0 Addr MMI O BAR VTBAR Offset 1100h 170h 160h 150h 140h 130h 120h 110h 100h Bit Attr Default Description Fault F Hardware sets this field to indicate a fault is logged in this fault recording 127 RW1CS 0 register When this field is set hardware may collapse additional faults from the same requestor SID Software writes the value read from this field to clear it 126 RO Reserved 125 124 RO Reserved 123 104 RV Reserved Fault Reason 103 96 ROS 0 Reason for the first translation fault See Intel VT d specification for details This field is only valid when Fault bit is set 95 80 R
373. zed errata are available on request ntel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology security Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality perf
374. zen to commands not requiring a locked DLL Slow exit precharge powerdown is not supported tXSDLL 20 11 RW 0 Minimum delay between the exit of self refresh and commands that require a locked DLL tXS 10 3 RW 0 Minimum delay between the exit of self refresh and commands not requiring a DLL tCKE 257 RN 0 minimum pulse width Datasheet Volume 2 249 intel 4 10 15 4 10 16 250 Processor Uncore Configuration Registers MC CHANNEL 0 20 TIMING MC CHANNEL 1 ZQ TIMING This register contains parameters that specify ZQ timing All units are DCLK unless otherwise specified The register encodings are specified where applicable Device 4 5 Function 0 Offset 94h Access as a DWord Bit Attr Default Description 31 RO 0 Reserved Parallel ZQ 30 RW 1 Enable ZQ calibration to different ranks in parallel 29 RW 1 tZQenable n Enable the issuing of periodic ZQCS calibration commands ZQ_Interval 28 8 RW 20910 Nominal interval between periodic ZQ calibration increments of tZQCS Specifies ZQCS cycles in increments of 16 This is the minimum delay 7 5 RW 4 between ZQCS and any other command This register should be programmed to at least 64 16 4 100 to conform to the DDR3 specification tZQI nit Specifies ZQI nit cycles in increments of 32 This is the minimum delay 4 0 RW 0 between ZQCL and any other command This register should be programmed to at least 512 32 16 10000

Intel Core Core™ i5-750 Processor (8M Cache, 2.66 GHz)

Contents

Download Pdf Manuals

Related Search

Related Contents

Intel Core Core&trade; i5-750 Processor (8M Cache, 2.66 GHz)

Contents

Download Pdf Manuals

Related Search

Related Contents

Intel Core Core™ i5-750 Processor (8M Cache, 2.66 GHz)