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Intel Xeon W3520

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1. Fo Pin Name osi Direction pui Pin Name pore Direction AU3 RSVD AV26 VSS GND AU30 VCC PWR AV27 VCC PWR AU31 VCC PWR AV28 VCC PWR AU32 VSS GND AV29 VSS GND AU33 VCC PWR AV3 VTT_VID2 CMOS O AU34 VCC PWR AV30 VCC PWR AU35 VSS GND AV31 VCC PWR AU36 VSS GND AV32 VSS GND AU37 QPI_DRX_DN 0 QPI AV33 VCC PWR AU38 QPI_DRX_DP 1 QPI AV34 VCC PWR AU39 QPI_DRX_DP 7 QPI AV35 RSVD AU4 RSVD AV36 QPI_DRX_DP 2 QPI 040 QPI DRX DP 9 AV37 QPI_DRX_DN 2 QPI AU41 QPI_DRX_DN 9 QPI AV38 QPI_DRX_DN 1 QPI 042 QPI_DRX_DP 10 QPI AV39 vss GND AU43 VSS GND AV4 vss GND AU5 VSS GND AV40 QPI_DRX_DN 8 QPI AU6 RSVD AV41 vss GND AU7 RSVD AV42 RSVD AU8 RSVD AV43 RSVD AU9 VCC PWR AV5 RSVD AV1 RSVD AV6 VTT_VID4 CMOS O AV10 VCC PWR AV7 RSVD AV11 VSS GND AV8 RSVD AV12 VCC PWR AV9 VCC PWR AV13 VCC PWR AW1 VSS GND AV14 VSS GND AW10 VCC PWR AV15 VCC PWR AW11 vss GND AV16 VCC PWR AW12 VCC PWR AV17 VSS GND AW13 VCC PWR AV18 VCC PWR AW14 VSS GND AV19 VCC PWR AW15 VCC PWR AV2 RSVD AW16 VCC PWR AV20 VSS GND AW17 VSS GND AV21 VCC PWR AW18 VCC PWR AV22 VSS GND AW19 VCC PWR AV23 VSS GND AW2 RSVD AV24 VCC PWR AW20 VSS GND AV25 VCC PWR AW21 VCC PWR Intel Xeon Processor 3500 Series Datasheet Volume 1 63 n tel Intel Xeon Processor 3500 Series Land Listing
2. yc Pin Name pad Direction A10 DDRO MA 13 CMOS O A14 VDDQ PWR A15 DDRO_RAS CMOS O A16 DDRO BA 1 CMOS O A17 DDR2 BA 0 CMOS O A18 DDR2 MA O CMOS 19 VDDQ PWR A20 DDRO_MAI 0 CMOS O A24 VDDQ PWR A25 DDRO MA 7 CMOS A26 DDRO MA 11 CMOS 27 RSVD A28 DDRO MA 14 CMOS O A29 VDDQ PWR A30 DDRO_CKE 1 CMOS 1 RSVD A35 VSS GND A36 DDRO_ECC 1 CMOS 1 0 A37 DDRO_ECC 5 CMOS 1 0 A38 DDRO_DQ 26 CMOS 1 0 A39 vss GND A4 VSS GND A40 RSVD A41 VSS GND A5 BPM 1 GTL 1 0 A6 vss GND A7 DDRO_CS 5 CMOS O A8 DDR1_CS 1 CMOS O A9 VDDQ PWR AA10 VTTD PWR AA11 VTTD PWR AA3 vss GND AA33 VTTD PWR AA34 VSS GND AA35 DDR1 DQ 4 CMOS 1 0 AA36 DDR1_DQ 1 CMOS 1 0 AA37 DDR1 DQ O0 CMOS 1 0 AA38 vss GND 56 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 2 of 36 Land Pin Name Butrer Direction No Type AA39 vss GND AA4 BCLK ITP DN CMOS O AA40 RSVD AA41 RSVD AA5 BCLK ITP DP CMOS O AA6 VDDPWRGOOD Asynch 7 DDR1_DQ 62 CMOS 1 0 AA8 amp DDR_COMP 0 Analog AAQ VSS GND AB10 VTTD PWR AB11 VTTD PWR AB3 RSVD AB33 VTTD PWR AB34 VTTD PWR AB35 VTTPWRGOOD Asynch AB36 DDR1_DQ 5 CMOS 1 0 AB37 VSS GND AB38 QPI_DTX_DN 17 QPI O AB39 QPI_DTX_DP 17 QPI O AB4 VSS GND
3. 103 8 4 2 Variable Speed Fani ei ch ki yak kab Aa kra W y RA h A AA ah y Yu k A Wan 105 Figures 1 1 High Level View of Processor 1 9 2 1 Active ODT for a Differential Link kk 13 2 2 Input Device HySteresis risers eee nee nemen nnns 21 2 3 VCC Static and Transient Tolerance Load Lines 25 2 4 Static and Transient Tolerance Load e 27 2 5 Overshoot Example Waveform sss nemen senem en nens 30 3 1 Processor Package Assembly 5 31 3 2 Processor Package Drawing Sheet 1 of 2 ieee center mmn 32 3 3 Processor Package Drawing Sheet 2 of 2 33 3 4 Processor Top Side 5 eee UNET VEDERNE R EDEA 35 3 5 Processor Land Coordinates and Quadrants Bottom View 36 6 1 Processor Thermal Profile eric es n bidiya ba yan lain Mar NA 81 6 2 Thermal Test Vehicle TTV Case Temperature TCASE Measurement Location 83 6 3 Frequency and Voltage Ordering 0 cece eee 86 Jl Power States sr XR 94 8 1 Mechanical Representation of
4. 37 4 1 Intel Xeon Processor 3500 Series Land Assignments 37 4 1 1 Land Listing by Land nnne nnn 38 4 1 2 Land Listing by Land NumbDer Mh lhWkk K lk kk kk kk kk mmm menm 56 5 Signal D firlitionS i LE 75 5 l Signal Definitions erm cce roca e a e enne d da dada lana Van ban hanan dla nehin Re 75 6 Thermal Specifications iine ree kk kk kk kk kk kak ka kaka kk 79 6 1 Package Thermal 5 e emen ens 79 6 1 1 Thermal Sp edcifica ONS s sirrinin eee nan ba bib k eem 79 6 3 2 Thermal Metrology eere terrere neta be FP r l SEE RH 83 6 2 Processor Thermal eene nennen nennen nn nn nnn ka 84 6 2 1 Processor Temperature esses nene senses nnn n nn nn 84 6 2 2 Adaptive Thermal kk kk kk ka kak k kk enn 84 6 2 3 THERMTRIP Signal iiss takai bala na W n ah nnne da kann j d ka ES 87 6 3 Platform Environment Control Interface PECI cesse 88 6 3 1 Introduction en 88 6 3 2 PECI Specifications tolan zanay obese weak Ad wla iq lur nU RI FEM FINA ERR ihe 89 6 4 Storage Conditions Specifications 90 Intel Xeon Processor 3500 Ser
5. Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 17 of 36 Sheet 18 of 36 Butter Direction Land Pin Name Buffer Direction No Type No Type AW22 VSS GND AY20 VSS GND AW23 VSS GND AY21 VCC PWR AW24 VCC PWR AY22 vss GND AW25 VCC PWR AY23 vss GND AW26 VSS GND AY24 VCC PWR AW27 VCC PWR AY25 VCC PWR AW28 VCC PWR AY26 vss GND AW29 VSS GND AY27 VCC PWR AW3 RSVD AY28 VCC PWR AW30 VCC PWR AY29 VSS GND vcc ewR ays RSVD AW32 VSS GND AY30 VCC PWR AW33 VCC PWR AY31 VCC PWR AW34 VCC PWR AY32 VSS GND AW35 VSS GND AY33 VCC PWR AW36 QPI_DRX_DP 3 QPI AY34 VCC PWR AW37 QPI_DRX_DP 5 QPI 5 RSVD AW38 QPI_DRX_DN 5 QPI AY36 QPI_DRX_DN 3 QPI AW39 RSVD AY37 vss GND AWA RSVD AY38 QPI DRX DNI 6 QPI AW40 QPI_DRX_DP 8 AY39 RSVD AW41 RSVD AY4 RSVD AW42 RSVD AY40 RSVD AWS RSVD AY41 RSVD AW6 VSS GND AY42 VSS GND AW7 RSVD 5 RSVD AW8 vss GND AY6 RSVD AW9 VCC PWR AY7 VSS GND AY10 VCC PWR AY8 RSVD AY11 VSS GND AY9 VCC PWR AY12 VCC PWR B10 DDRO_CS 1 CMOS AY13 VCC PWR B11 DDRO_ODT 2 CMOS AY14 vss GND B12 VDDQ PWR AY15 VCC PWR B13 DDRO_WE CMOS AY16 VCC PWR B14 DDR1_MA 13 CMOS 17 vss GND B15 DDRO CS 4 CMOS 18 VCC PWR B16 DDRO BA 0 CMOS jPWR B7 VDDQ PWR AY2 VSS GND B18 RSVD
6. 20 2 9 1 DC Characteristics sis enr ERRARE NERVAE WA ARR a RN RR Ayr nan n 20 2 9 2 Input Device Hysteresis sss kk kk kk kk kaka kk kaka nn nnn 21 2 10 Absolute Maximum and Minimum Ratings k kh h Khkkk kk kk kk kk kk kk kk kk kk kk ka 21 2 11 Processor DC Specifications sss kk kk kk kk nennen nnn ka 22 2 11 1 DC Voltage and Current Specification 0c eee eee ee m 23 2 11 2 VCC Overshoot Specification kk kk kk meme nnn 29 2 11 3 Die Voltage Validation cesses nme 30 3 Package Mechanical Specifications s sss 31 3 1 Package Mechanical e enemies 31 3 2 Processor Component Keep Out 2 menm nnn 34 3 3 Package Loading Specifications kk kk memes 34 3 4 Package Handling Guidelines sss memes 34 3 5 Package Insertion 5 lt memes ens 34 3 6 Processor Mass Specification sss memes eme mese ens 35 3 7 Processor Materials erre khe ba SERRA TONER TEERUFCREU RET RE j Wak kirdan j FERRE LER a 35 3 8 Processor Markings REM RA FRI RR ae 35 3 9 Processor Land Coordinates xaneka h kan hae wala Waaa Ki need na E kwa sa ala DER 36 4 Intel Xeon Processor 3500 Series Land
7. 64 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 19 of 36 intel Table 4 2 Land Listing by Land Number Sheet 20 of 36 Land Pin Name B ffer Direction Land Pin Name Buffer Direction No Type No Type B19 DDRO_MA 10 CMOS 0 BA16 VCC PWR B2 VSS GND 17 vss GND B20 RSVD BA18 VCC PWR B21 DDRO_MA 1 CMOS 0 BA19 VCC PWR B22 VDDQ PWR BA20 vss GND B23 DDRO_MA 4 CMOS 0 BA24 VCC PWR B24 DDRO MA S CMOS 0 BA25 VCC PWR B25 DDRO MA 8 CMOS 0 BA26 vss GND B26 DDRO MA 12 CMOS 0 BA27 VCC PWR B27 VDDQ PWR BA28 VCC PWR B28 RSVD BA29 vss GND B29 DDRO MA 15 CMOS 0 BA3 VSS GND B3 BPM 0 GTL 1 0 BA30 VCC PWR B30 DDRO CKE 2 CMOS BA35 jVss GND B31 DDRO CKE 3 CMOS Jo BA36 DRX DP 4 QPI B32 VDDQ PWR BA37 B33 RSVD BA38 DRX DP 6 QPI B34 DDRO ECC 6 CMOS 1 0 BA39 J VSS GND BA4 RSVD Be RSVD BA40 RSVD B nav BA5 vss GND B37 VSS GND ER B38 DDRO_DQ 31 CMOS 1 0 BAT ae B39 DDRO DOS P 3 CMOS 1 0 BAB Rev B4 BPM 3 GTL 1 0 BAG BWR B40 DDRO_DQS_N 3 CMOS 1 0 er BUR B41 PRDY GTL 0 en REV Bez yaa one C12 DDRO_CAS CMOS B5 DDR
8. Notes 1 80 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified Icc Refer to the loadline specifications in Chapter 2 E Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at the TCC activation temperature These specifications are based on initial silicon characterization These specifications may be further updated as more characterization data becomes available Power specifications are defined at all VIDs found in Table 2 1 The processor may be shipped under multiple VIDs for each frequency Target ca Using the processor TTV C W is based on a Tawpient Of 39 Processor idle power is specified under the lowest possible idle state processor package C6 state Achieving processor package C6 state is not supported by all chipsets See Intel X58 Express Chipset specifications for more details Intel Xeon Processor 3500 Series Datasheet Volume 1 Thermal Specifications Figure 6 1 Processor Thermal Profile TTV Tcase in C 70 0 y 43 2 0 19 P 55 0 45 0 40 0 60 70 TTV Power W 80 90 100 110 120 130 Notes 1 Refer to Table 6 2 for discrete
9. PWR AD39 QPI_DTX_DN 14 QPI O AF34 VTTA PWR AD4 RSVD AF35 VSS GND AD40 QPI_DTX_DP 14 QPI O AF36 VTTD PWR AD41 VSS GND AF37 VTTD PWR AD42 QPI_DTX_DP 12 QPI O AF38 vss GND AD43 VSS GND AF39 QPI DTX DP 1 QPI O AD5 RSVD AF4 RSVD AD6 RSVD AF40 QPI_DTX_DN 19 QPI O AD7 RSVD AF41 vss GND AD8 RSVD AF42 QPI_CLKTX_DN AD9 VTTD PWR AF43 QPI DTX DP 10 1 RSVD AF5 VSS GND AE10 VTTA PWR AF6 RSVD AE11 VTTA PWR AF7 VIT VID3 CMOS O AE2 VSS GND AF8 VTTD PWR Intel Xeon Processor 3500 Series Datasheet Volume 1 57 intel Table 4 2 Land Listing by Land Number Sheet 5 of 36 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 6 of 36 Dan Pin Name patter Direction Buffer Direction No Type No Type AF9 VTTD PWR AH43 QPI_DTX_DN 8 QPI 0 AG1 RSVD AH5 FC_AH5 AG10 TMS TAP AH6 RSVD 11 VSS GND AH7 VSS GND AG2 RSVD AH8 RSVD AG3 VSS GND AH9 TRST TAP AG33 VSS GND AJ1 RSVD AG34 VTTA PWR AJ10 TDO TAP 0 AG35 PROCHOT GTL 1 0 AJ11 VCC PWR AG36 SKTOCC GTL O AJ2 RSVD AG37 THERMTRIP GTL O AJ 3 RSVD AG38 QPI_DTX_DP 0 QPI O AJ33 VCC PWR AG39 QPI_DTX_DN 1 O AJ34 VSS GND AG4 RSVD AJ35 BCLK_DP CMOS 40 QPI_DTX_DP 9 QPI AJ36 VSS GND AG41 QPI_DTX_DN 9 QPI AJ37 RSVD AG42 QPI CLKTX DP
10. n tel Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 25 of 36 Sheet 26 of 36 Butter Direction Land Pin Name Buffer Direction No Type No Type F9 VSS GND G5 DDR1 DQ 46 CMOS 1 0 G1 DDRO_DQ 44 CMOS 1 0 G6 DDR1 DQS N 5 CMOS 1 0 G10 DDR2 DQ 37 CMOS 1 0 G7 VSS GND G11 DDR2 DQ 36 CMOS 1 0 G8 DDR1 DQ 37 CMOS 1 0 G12 vss GND G9 DDR1 DQ 44 CMOS 1 0 G13 DDR1_WE CMOS H1 DDRO DQ 41 CMOS 1 0 G14 DDR1_RAS CMOS 0 H10 VSS GND G15 DDRO_CS 0 CMOS H11 RSVD G16 DDR2_CS 0 CMOS H12 DDR2 DQ 38 CMOS 1 0 G17 VDDQ PWR H13 DDR2 DQ 34 CMOS 1 0 Gig DDR2 m2 cmos Jo H4 DDR1 MA 10 CMOS 0 G19 DDR1_CLK_P 1 CLOCK 0 H15 VDDQ PWR G2 vss GND H16 RSVD G20 DDR1 CLK N 1 CLOCK H17 DDR2 MA 10 CMOS G21 DDR2_CLK_N 2 CLOCK H18 DDR1_CLK_P 3 CLOCK 622 VDDQ PWR H19 DDR1_CLK_N 3 CLOCK G23 DDR2_MA 12 CMOS 2 DDRO DQ 40 CMOS 1 0 G24 DDR1 MA 9 CMOS H20 VDDQ PWR G25 DDR2 MA 15 CMOS H21 DDR2_CLK_P 2 CLOCK G26 DDR2_CKE 1 CMOS 22 DDR2 MA 9 CMOS G27 VDDQ PWR H23 DDR2 MA 11 CMOS 0 G28 RSVD H24 DDR2_MA 14 CMOS G29 DDR2 DQS P 8 CMOS 1 0 H25 VDDQ PWR G3 DDRO_DQ 35 CMOS 1 0 H26 DDR1_MA 14 CMOS G30 DDR2 DQS N 8 CMOS 1 0 H27 DDR1_BA 2 CMOS G31 RSVD H28 DDR1_CKE 0 CMOS G32 vss GN
11. 96 If Intel QPI L1 has been granted the processor will disable some clocks and PLLs and for processors with an integrated memory controller the DRAM will be put into self refresh Package C6 State The package will enter the C6 low power state when all cores are in the C6 or lower power state and the processor has been granted permission by the other component s in the system to enter the C6 state The package will also enter the C6 state when all cores are in an idle state lower than C6 but the other component s have only granted permission to enter C6 If Intel QPI L1 has been granted the processor will disable some clocks and PLLs and the shared cache will enter a deep sleep state Additionally for processors with an integrated memory controller the DRAM will be put into self refresh Sleep States The processor supports the ACPI sleep states SO S1 S3 and S4 S5 as shown in For information on ACPI S states and related terminology refer to ACPI Specification The S state transitions are coordinated by the processor in response PM Request PMReq messages from the chipset The processor itself will never request a particular S state Processor S States S State Power Reduction Allowed Transitions S0 Normal Code Execution S1 via PMReq S1 Cores in CIE like state processor responds with SO via reset or PMReq CmpD S1 message S3 S4 via PMReq 53 Memory put into self refresh processor respo
12. Sheet 6 of 36 Land Name pos T Direction Land Name ro poe Direction DDR1 BA 2 H27 CMOS O DDR1_DQ 28 J34 CMOS 1 0 DDR1_CAS E14 CMOS O DDR1_DQ 29 H34 CMOS 1 0 DDR1_CKE 0 H28 CMOS O DDR1_DQ 3 Y34 CMOS 1 0 DDR1_CKE 1 E27 CMOS O DDR1_DQ 30 L32 CMOS 1 0 DDR1_CKE 2 D27 CMOS O DDR1_DQ 31 K30 CMOS 1 0 DDR1_CKE 3 C27 CMOS O DDR1_DQ 32 E9 CMOS 1 0 DDR1 CLK N 0 D21 CLOCK O DDR1_DQ 33 E8 CMOS 1 0 DDR1_CLK_N 1 G20 CLOCK O DDR1 DQ 34 E5 CMOS 1 0 DDR1_CLK_N 2 L18 CLOCK O DDR1 DQ 35 F5 CMOS DDR1_CLK_N 3 H19 CLOCK O DDR1 DQ 36 F10 CMOS 1 0 DDR1_CLK_P 0 C21 CLOCK O DDR1_DQ 37 G8 CMOS 1 0 DDR1_CLK_P 1 G19 CLOCK O DDR1_DQ 38 D6 CMOS DDR1_CLK_P 2 K18 CLOCK O DDR1_DQ 39 F6 CMOS 1 0 DDR1_CLK_P 3 H18 CLOCK O DDR1 DQ 4 AA35 CMOS 1 0 DDR1_CS 0 D12 CMOS O DDR1_DQ 40 H8 CMOS 1 0 DDR1_CS 1 A8 CMOS O DDR1 DQ 41 J6 CMOS DDR1_CS 4 C17 CMOS O DDR1 DQ 42 G4 CMOS 1 0 DDR1_CS 5 E10 CMOS O DDR1 DQ 43 H4 CMOS 1 0 DDR1 DQ O0 AA37 CMOS 1 0 DDR1 DQ 44 G9 CMOS DDR1_DQ 1 AA36 CMOS DDR1 DQ 45 H9 CMOS DDR1_DQ 10 P39 CMOS DDR1 DQ 46 G5 CMOS 1 0 DDR1_DQ 11 N39 CMOS 1 0 DDR1 DQ 47 J5 CMOS DDR1 DQ 12 R34 CMOS 1 0 DDR1_DQ 48 K4 CMOS 1 0 DDR1_DQ 13 R35 CMOS DDR1 DQ 49 K5 CMOS 1 0 DDR1 DQ 14 N37 CMOS 1 0 DDR1_DQ 5 AB36 CMOS 1 0 DDR1 DQ 15 N38 CMOS DDR1_DQ 50 R5 CMOS DDR1
13. VDDQ B12 PWR VDDQ M27 PWR VDDQ B17 PWR VID 0 MSID 0 AL10 CMOS 1 0 VDDQ B22 PWR VID 1 MSID 1 AL9 CMOS 1 0 VDDQ B27 PWR VID 2 MSID 2 AN9 CMOS 1 0 e2 m AM10 CMOS VDDQ B7 PWR VID 41 CSC 1 AN10 CMOS 1 0 50 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing n tel Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 27 of 36 Sheet 28 of 36 Land Name pos T Direction Land Name Fon Re Direction viDSI CSC2 amo cmos vss AGO GND VID 6 AP8 CMOS vss AH1 GND VID 7 8 CMOS vss AH34 GND VSS A35 GND VSS AH37 GND VSS A39 GND VSS AH39 GND VSS A4 GND VSS AH7 GND vss A41 GND VSS AJ 34 GND VSS A6 GND VSS AJ 36 GND VSS AA3 GND VSS AJ 41 GND vss Haaa ono VSS AJ 5 GND VSS AA38 GND VSS AK10 GND VSS AA39 GND VSS AK14 GND vss Aaag ono AK17 GND vss AB37 GND vss AK20 GND VSS AB4 GND VSS AK22 GND VSS AB40 GND VSS AK23 GND VSS AB42 GND VSS AK26 GND VSS AB7 GND VSS AK29 GND VSS AC2 GND VSS AK3 GND VSS AC36 GND VSS AK32 GND VSS 5 GND vss AK34 GND vss AC7 GND VSS AK39 GND VSS AC9 GND VSS AK43 GND VSS AD11 GND vss AK9 GND vss AD33 cnn ALI GND vss AD37 GND vss AL11 GND VSS AD41 GND VSS AL14 GND VSS AD43 GND VSS AL17 GND VSS AE2 GN
14. A37 CMOS 1 0 DDRO_DQ 53 N3 CMOS 1 0 DDRO_ECC 6 B34 CMOS 1 0 DDRO_DQ 54 R4 CMOS 1 0 DDRO_ECC 7 C34 CMOS 1 0 DDRO_DQ 55 T3 CMOS 1 0 DDRO MA 0 A20 CMOS O DDRO_DQ 56 U4 CMOS 1 0 DDRO MA 1 B21 CMOS O DDRO_DQ 57 V1 CMOS 1 0 DDRO MA 10 B19 CMOS O DDRO_DQ 58 Y2 CMOS 1 0 DDRO MA 11 A26 CMOS O DDRO_DQ 59 Y3 CMOS 1 0 DDRO MA 12 B26 CMOS O DDRO_DQ 6 U41 CMOS 1 0 DDRO MA 13 A10 CMOS O DDRO_DQ 60 U1 CMOS 1 0 DDRO MA 14 A28 CMOS O DDRO_DQ 61 U3 CMOS 1 0 DDRO MA 15 B29 CMOS O DDRO_DQ 62 v4 CMOS 1 0 DDRO MA 2 C23 CMOS O DDRO_DQ 63 WA CMOS 1 0 DDRO MA 3 D24 CMOS DDRO_DQ 7 T42 CMOS 1 0 DDRO MA 4 B23 CMOS O DDRO DQ 8 N41 CMOS 1 0 DDRO MA 5 B24 CMOS O DDRO_DQ 9 N43 CMOS 1 0 DDRO MA 6 C24 CMOS O DDRO DQS NIO U43 CMOS 1 0 DDRO MA 7 A25 CMOS O DDRO_DQS_N 1 M41 CMOS 1 0 DDRO MA 8 B25 CMOS O DDRO DQS NI2 G41 CMOS 1 0 DDRO MA 9 C26 CMOS O DDRO DQS NI 3 B40 CMOS 1 0 DDRO_ODT 0 F12 CMOS O DDRO DQS NI4 E4 CMOS 1 0 DDRO_ODT 1 C9 CMOS O DDR0_DQS_N 5 K3 CMOS 1 0 DDRO_ODT 2 B11 CMOS O DDRO DQS NI6 R3 CMOS 1 0 DDRO_ODT 3 C7 CMOS O DDRO_DQS_N 7 W1 CMOS 1 0 DDRO_RAS A15 CMOS O DDRO DQS N 8 D35 CMOS 1 0 DDRO_RESET D32 CMOS O DDRO DQS P 0 T43 CMOS 1 0 DDRO_WE B13 CMOS O DDRO DQS P 1 L41 CMOS 1 0 DDR1 BA 0 C18 CMOS O DDRO DQS P 2 F41 CMOS 1 0 DDR1 BA 1 K13 CMOS O 39 Intel Xeon Processor 3500 Series Land Listing intel Table 4 1 Land Listing by Land Name Sheet 5 of 36 Table 4 1 Land Listing by Land Name
15. AB40 VSS GND AB41 COMPO Analog AB42 vss GND AB43 QPI_DTX_DN 13 QPI O AB5 RSVD AB6 RSVD AB7 VSS GND AB8 VTTD PWR AB9 VTTD PWR AC1 DDR_COMP 2 Analog AC10 VTTD PWR AC11 VTTD PWR AC2 vss GND AC3 RSVD AC33 VTTD PWR AC34 VTTD PWR AC35 VTTD PWR AC36 vss GND Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 3 of 36 intel Table 4 2 Land Listing by Land Number Sheet 4 of 36 Pin Name Direction n Pin Name E ewa Direction AC37 CAT_ERR GTL 1 0 AE3 RSVD AC38 QPI_DTX_DN 16 QPI O AE33 VTTA PWR AC39 QPI_DTX_DP 16 QPI O AE34 VTTD PWR AC4 RSVD AE35 VTTD PWR AC40 QPI_DTX_DN 15 QPI O AE36 VTT_SENSE Analog AC41 QPI_DTX_DP 15 QPI O AE37 VSS SENSE VIT Analog AC42 QPI_DTX_DN 12 QPI O AE38 QPI_DTX_DN 18 QPI O AC43 QPI_DTX_DP 13 QPI O AE39 VSS GND AC5 VSS GND AE4 RSVD AC6 RSVD AE40 QPI_DTX_DP 19 QPI O AC7 VSS GND AE41 QPI_DTX_DN 11 QPI O AC8 RSVD AE42 QPI_DTX_DP 11 QPI O AC9 vss GND AE43 QPI_DTX_DN 10 QPI O AD1 RSVD AES RSVD AD10 VTTA PWR AE6 RSVD AD11 VSS GND AE7 VSS GND AD2 RSVD AE8 VTTD PWR AD3 RSVD AE9 VTTD PWR AD33 VSS GND AF1 RSVD AD34 VTTD PWR AF10 DBR Asynch AD35 VTTD PWR AF11 VTTA PWR AD36 VTTD PWR AF2 RSVD AD37 vss GND AF3 RSVD AD38 QPI DTX DP 18
16. See Table 2 9 for details on Vrr Voltage Identification and Table 2 9 and Figure 2 4 for details on the Vrr Loadline loc max Specification is based on the Vcc wax loadline Refer to Figure 2 3 for details This spec is based on a processor temperature as reported by the DTS of less than or equal to Tcontrol 25 Intel Xeon Processor 3500 Series Datasheet Volume 1 23 n tel Electrical Specifications Table 2 8 Vcc Static and Transient Tolerance Icc Vcc Max V Vcc V min V Notes 0 VID 0 000 VID 0 019 VID 0 038 1 2 3 5 VID 0 004 VID 0 023 VID 0 042 1 2 10 VID 0 008 VID 0 027 VID 0 046 1 2 3 15 VID 0 012 VID 0 031 VID 0 050 1 2 20 VID 0 016 VID 0 035 VID 0 054 1 2 3 25 VID 0 020 VID 0 039 VID 0 058 1 2 30 VID 0 024 VID 0 043 VID 0 062 1 2 3 35 VID 0 028 VID 0 047 VID 0 066 1 2 3 40 VID 0 032 VID 0 051 VID 0 070 1 2 3 45 VID 0 036 VID 0 055 VID 0 074 1 2 3 50 VID 0 040 VID 0 059 VID 0 078 1 2 3 55 VID 0 044 VID 0 063 VID 0 082 1 2 3 60 VID 0 048 VID 0 067 VID 0 086 1 2 3 65 VID 0 052 VID 0 071 VID 0 090 1 2 3 70 VID 0 056 VID 0 075 VID 0 094 1 2 3 75 VID 0 060 VID 0 079 VID 0 098 1 2 3 78 VID 0 062 VID 0 081 VID 0 100 1 2 3 85 VID 0 068 VID 0 087 VID 0 106 1 2 3 90 VID 0 072 VID 0 091 VID 0 110
17. Type K33 RSVD L3 DDRO_DQ 46 CMOS 1 0 K34 RSVD L30 DDR1 DQS P 3 CMOS 1 0 K35 DDR1_DQ 18 CMOS 1 0 L31 DDR1 DQS N 3 CMOS 1 0 K36 VSS GND L32 DDR1_DQ 30 CMOS 1 0 K37 RSVD L33 DDR1_DQ 25 CMOS 1 0 K38 DDR2_DQ 23 CMOS 1 0 L34 VSS GND K39 DDR2_DQS_N 2 CMOS 1 0 L35 DDR1 DQS P 2 CMOS 1 0 K4 DDR1 DQIAS CMOS 1 0 L36 DDR1 DQS N 2 CMOS 1 0 K40 DDR2_DQS_P 2 CMOS 1 0 L37 RSVD K41 VSS GND L38 RSVD k42 Doo ju VSS GND K43 DDRO_DQ 11 CMOS 1 0 L4 VSS GND K5 DDR1_DQ 49 CMOS 1 0 L40 DDR2_DQ 22 CMOS 1 0 K6 VSS GND L41 DDRO DQS P 1 CMOS 1 0 K7 DDR2 DQS N 5 CMOS 1 0 L42 DDRO_DQ 15 CMOS 1 0 K8 RSVD L43 DDRO DQ 14 CMOS 1 0 K9 RSVD L5 DDR1 DQS N 6 CMOS 1 0 L1 DDRO DQ 42 CMOS 1 0 L6 DDR1_DQS_P 6 CMOS 1 0 L10 DDR2_DQ 40 CMOS 1 0 L7 DDR2 DQS P 5 CMOS 1 0 L11 DDR2 DQ 44 CMOS 1 0 L8 DDR2 DQI 46 CMOS 1 0 L12 DDR2 DQ 39 CMOS 1 0 L9 VSS GND L13 DDR2 DQ 35 CMOS 1 0 M1 DDRO DQ 43 CMOS 1 0 L14 VDDQ PWR M10 DDR2_DQ 45 CMOS 1 0 L15 RSVD M11 VCC PWR L16 DDR2_ODT 0 CMOS M12 vss GND L17 RSVD M13 VCC PWR L18 DDR1_CLK_N 2 CLOCK M14 vss GND L19 VDDQ PWR M15 VCC PWR L2 DDRO DQ 47 CMOS 1 0 M16 vss GND L20 DDR2_CLK_P 1 CLOCK 17 VDDQ PWR L21 DDR2 CLK N 3 CLOCK M18 vss GND L22 DDR2_CLK_P 3 CLOCK M19 VCC PWR L23 DDR_VREF Analog M2 VSS GND L24 VDDQ PWR M20 vss GND L25 DDR2 MA 8 CMOS M21 VCC PWR L26 DDR2_BA 2 CMOS M22 vss GND L27 DDR2_CKE 3 CMOS M23 VCC PWR L28 DDR1 MA 3 CMOS M24 vss GND L29
18. the operating frequency and voltage transition back to the normal system operating point via the intermediate VI D frequency points Transition of the VID code will occur first to insure proper operation as the frequency is increased Refer to Table 6 3 for an illustration of this ordering Intel Xeon Processor 3500 Series Datasheet Volume 1 85 n tel Thermal Specifications Figure 6 3 6 2 2 2 6 2 2 3 86 Frequency and Voltage Ordering Temperature fmax 22222242 Frequency VID fax VIDE T pec VID 777777 VID B PROCHOT Clock Modulation Clock modulation is a second method of thermal control available to the processor Clock modulation is performed by rapidly turning the clocks off and on at a duty cycle that should reduce power dissipation by about 50 typically a 30 50 duty cycle Clocks often will not be off for more than 32 microseconds when the TCC is active Cycle times are independent of processor frequency The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified It is possible for software to initiate clock modulation with configurable duty cycles A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the
19. 1 F33 CMOS 1 0 QPI_CLKTX_DN AF42 QPI O DDR2_ECC 2 E29 CMOS 1 0 QPI_CLKTX_DP AG42 QPI O DDR2_ECC 3 E30 CMOS 1 0 QPI_CMP 0 AL43 Analog DDR2_ECC 4 J31 CMOS 1 0 QPI_DRX_DN 0 AU37 QPI DDR2_ECC 5 J30 CMOS 1 0 QPI_DRX_DN 1 AV38 QPI DDR2_ECC 6 F31 CMOS 1 0 QPI_DRX_DN 10 AT42 QPI DDR2_ECC 7 F30 CMOS 1 0 QPI_DRX_DN 11 AR43 QPI DDR2 MA 0 A18 CMOS O QPI_DRX_DN 12 AR40 QPI DDR2 MA 1 K17 CMOS O QPI_DRX_DN 13 AN42 QPI DDR2 MA 10 H17 CMOS O QPI_DRX_DN 14 AM43 QPI DDR2 MA 11 H23 CMOS O QPI_DRX_DN 15 AM40 QPI DDR2_MA 12 G23 CMOS O QPI_DRX_DNI 16 AM41 QPI DDR2 MA 13 F15 CMOS O QPI_DRX_DN 17 AP40 QPI DDR2 MA 14 H24 CMOS O QPI_DRX_DN 18 AP39 QPI DDR2 MA 15 G25 CMOS O QPI_DRX_DN 19 AR38 QPI DDR2 MA 2 G18 CMOS O QPI_DRX_DN 2 AV37 QPI DDR2 MA 3 J20 CMOS O QPI DRX DNI 3 AY36 QPI DDR2 MA 4 F20 CMOS O QPI DRX DN 4 BA37 QPI DDR2 MA 5 K23 CMOS O QPI DRX DN 5 AW38 QPI DDR2 MA 6 K22 CMOS O QPI_DRX_DN 6 AY38 QPI DDR2 MA 7 J24 CMOS O QPI DRX DN 7 AT39 QPI DDR2 MA 8 L25 CMOS O QPI_DRX_DN 8 AV40 QPI DDR2 MA 9 H22 CMOS O QPI_DRX_DN 9 AU41 QPI DDR2_ODT 0 L16 CMOS O QPI_DRX_DP 0 AT37 QPI DDR2_ODT 1 F13 CMOS O QPI_DRX_DP 1 AU38 QPI DDR2_ODT 2 D15 CMOS O QPI_DRX_DP 10 AU42 QPI DDR2_ODT 3 D10 CMOS O QPI_DRX_DP 11 AT43 QPI DDR2_RAS D17 CMOS O QPI_DRX_DP 12 AT40 QPI DDR2_RESET E32 CMOS O QPI_DRX_DP 13 AP42 QPI DDR2_WE C16 CMOS O QPI_DRX_DP 14 AN43 QPI
20. 1 2 3 95 VID 0 076 VID 0 095 VID 0 114 1 2 3 100 VID 0 080 VID 0 099 VID 0 118 1 2 3 105 VID 0 084 VID 0 103 VID 0 122 1 2 3 110 VID 0 088 VID 0 107 VID 0 126 1 2 3 115 VID 0 092 VID 0 111 VID 0 130 1 2 3 120 VID 0 096 VID 0 115 VID 0 134 1 2 3 125 VID 0 100 VID 0 119 VID 0 138 1 2 3 130 VID 0 104 VID 0 123 VID 0 142 1 2 3 135 VID 0 108 VID 0 127 VID 0 146 1 2 3 140 VID 0 112 VID 0 131 VID 0 150 1 2 3 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits See Section 2 11 2 for Vcc overshoot specifications 2 This table is intended to aid in reading discrete points on Figure 2 3 3 loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC SENSE and VSS SENSE lands 24 Intel Xeon Processor 3500 Series Datasheet Volume 1 Electrical Specifications Figure 2 3 Vcc Static and Transient Tolerance Load Lines Table 2 9 Icc A VID VID VID VID VID VID VID VID VID VID VID VID VID VID VID 0 000 0 013 0 025 0 038 0 050 0 063 0 075 0 088 0 100 0 113 0 125 0 138 0 150 0 163 0 175 30 40 Typical 50 60 70 a Vcc Minimum 90 100 110 Vr1 Vo
21. 2 AK38 QPI O RSVD P1 QPI_DTX_DN 3 AJ39 QPI O RSVD V3 QPI_DTX_DN 4 AJ 40 QPI O RSVD B35 QPI_DTX_DN 5 AK41 QPI O RSVD V42 QPI_DTX_DN 6 AH42 QPI O RSVD N42 QPI_DTX_DN 7 AJ 42 QPI O RSVD H42 QPI_DTX_DN 8 AH43 QPI O RSVD D39 QPI_DTX_DN 9 AG41 QPI O RSVD D5 QPI_DTX_DP 0 AG38 QPI O RSVD J2 QPI_DTX_DP 1 AF39 QPI O RSVD P2 QPI DTX DP 10 AF43 QPI O RSVD V2 QPI_DTX_DP 11 AE42 QPI O RSVD B36 QPI_DTX_DP 12 AD42 QPI O RSVD V43 DTX DP 13 AC43 QPI O RSVD B20 QPI DTX DP 14 AD40 QPI O RSVD D25 QPI DTX DP 15 AC41 QPI O RSVD B28 QPI DTX DP 16 AC39 QPI O RSVD A27 QPI DTX DP 17 AB39 QPI O RSVD E15 QPI_DTX_DP 18 AD38 QPI O RSVD E13 QPI DTX DP 19 AE40 QPI O RSVD C14 DTX DP 2 AK37 QPI O RSVD E12 QPI_DTX_DP 3 AJ 38 QPI O RSVD P37 QPI_DTX_DP 4 AH40 QPI O RSVD E35 44 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Sheet 15 of 36 intel Table 4 1 Land Listing by Land Name Sheet 16 of 36 Land Name pode Direction Land Name ne Direction RSVD K37 RSVD V6 RSVD K33 RSVD H31 RSVD F7 RSVD U35 RSVD J7 RSVD B18 RSVD M4 RSVD F21 RSVD Y5 RSVD J25 RSVD AA41 RSVD F23 RSVD P36 RSVD A31 RSVD L37 RSVD A40 RSVD K34 RSVD AB3 RSVD F8 RSVD AB6 RSVD H7 RSVD AC3 RSVD M5 RSVD AC
22. 2 11 DDR3 Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes Input Low Voltage _ 0 43 Vppo V 2 4 Vin Input High Voltage 0 57 Vppg V 3 Output Low Voltage 2 Ron Vou Ron Rune TERM M Output High Voltage m Vppo Vppo 2 B RVI TERM DDR3 Clock Buffer On RoN Resistance 2 31 DDR3 Command Buffer Ron On Resistance 16 24 DDR3 Reset Buffer On Ron Resistance 25 75 Q DDR3 Control Buffer On Ron Resistance 21 31 DDR3 Data Buffer Ron Resistance 21 E 31 lu Input Leakage Current N A N A 1 mA DDR_COMPO COMP Resistance 99 100 101 Q 5 DDR_COMP1 COMP Resistance 24 65 24 9 25 15 Q 5 DDR_COMP2 COMP Resistance 128 7 130 131 30 Q 5 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value Intel Xeon Processor 3500 Series Datasheet Volume 1 27 Electrical Specifications 4 and Voy may experience excursions above Vppo However input signal drivers must comply with the signal quality specifications 5 COMP resistance must be provided on the system board with 1 resistors See the applicable
23. 9 G24 CMOS O DDR1_DQS_N 3 L31 CMOS 1 0 DDR1_ODT 0 D11 CMOS O DDR1 DQS N 4 D7 CMOS 1 0 DDR1_ODT 1 C8 CMOS O DDR1_DQS_N 5 G6 CMOS 1 0 DDR1_ODT 2 D14 CMOS O DDR1 DQS N 6 L5 CMOS 1 0 DDR1_ODT 3 F11 CMOS O DDR1 DQS N 7 Y9 CMOS 1 0 DDR1_RAS G14 CMOS O DDR1 DQS N 8 G34 CMOS 1 0 DDR1_RESET D29 CMOS O DDR1_DQS_P 0 Y38 CMOS 1 0 DDR1_WE G13 CMOS O DDR1_DQS_P 1 R38 CMOS 1 0 DDR2 BA 0 A17 CMOS O DDR1_DQS_P 2 L35 CMOS 1 0 DDR2 BA 1 F17 CMOS O DDR1 DQS P 3 L30 CMOS 1 0 DDR2_BA 2 L26 CMOS O DDR1 DQS P 4 E7 CMOS 1 0 DDR2_CAS F16 CMOS O DDR1 DQS P 5 H6 CMOS 1 0 DDR2_CKE 0 J26 CMOS O DDR1 DQS P 6 L6 CMOS 1 0 DDR2_CKE 1 G26 CMOS DDR1 DQS P 7 Y8 CMOS 1 0 DDR2_CKE 2 D26 CMOS O DDR1_DQS_P 8 G33 CMOS 1 0 DDR2_CKE 3 L27 CMOS O DDR1_ECC 0 D36 CMOS 1 0 DDR2_CLK_N 0 J21 CLOCK O DDR1_ECC 1 F36 CMOS 1 0 DDR2 CLK N 1 K20 CLOCK DDR1_ECC 2 E33 CMOS 1 0 DDR2_CLK_N 2 G21 CLOCK O DDR1_ECC 3 G36 CMOS 1 0 DDR2 CLK N 3 L21 CLOCK DDR1_ECC 4 E37 CMOS 1 0 DDR2_CLK_P 0 J22 CLOCK O DDR1_ECC 5 F37 CMOS 1 0 DDR2_CLK_P 1 L20 CLOCK O DDR1_ECC 6 E34 CMOS 1 0 DDR2_CLK_P 2 H21 CLOCK O DDR1_ECC 7 G35 CMOS 1 0 DDR2_CLK_P 3 L22 CLOCK O DDR1_MA 0 J14 CMOS O DDR2_CS 0 G16 CMOS O DDR1 MA 1 J16 CMOS O DDR2_CS 1 K14 CMOS O DDR1 MA 10 H14 CMOS O DDR2_CS 4 E17 CMOS O DDR1_MA 11 E23 CMOS O DDR2_CS 5 D9 CMOS O DDR1 MA 12 E24 CMOS O DDR2 DQ 0 W34 CMOS 1 0 DDR1 MA 13 B14 CMOS O DDR2_DQ 1 W35 CMOS 1 0 DDR1 MA 14 H26 CMOS O DDR2_DQ 10 R39
24. BIOS configurable value that determines the time in milliseconds over which the DTS temperature values are averaged Short averaging times will make the averaged temperature values respond more quickly to DTS Intel Xeon Processor 3500 Series Datasheet Volume 1 Bi Thermal Specifications n tel 6 3 2 6 3 2 1 6 3 2 2 Table 6 4 6 3 2 3 changes Long averaging times will result in better overall thermal smoothing but also incur a larger time lag between fast DST temperature changes and the value read via PECI Refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 for further details on the Data Filter and the Thermal Averaging Constant Within the processor the DTS converts an analog signal into a digital value representing the temperature relative to TCC activation The conversions are in integers with each single number change corresponding to approximately 1 C DTS values reported via the internal processor MSR will be in whole integers As a result of the averaging function described above DTS values reported over PECI will include a 6 bit fractional value Under typical operating conditions where the temperature is close to Tcontrol the fractional values may not be of interest But when the temperature approaches zero the fractional values can be used to detect the activation of the TCC An averaged temperature value between 0 and 1 can only occur if the TCC has been activate
25. Burren Direction No Type No Type v9 DDR1_DQ 60 CMOS 1 0 Y1 VSS GND W1 DDRO_DQS_NI 7 CMOS 1 0 Y10 DDR1 DQ 58 CMOS W10 DDR1 DQ 59 CMOS 1 0 11 VSS GND W11 VCC PWR Y2 DDRO DQ 58 CMOS 1 0 W2 DDRO DQS P 7 CMOS 1 0 Y3 DDRO_DQ 59 CMOS 1 0 W3 VSS GND Y33 vss GND W33 VCCPLL PWR Y34 DDR1_DQ 3 CMOS 1 0 w34 DDR2_DQ 0 CMOS 1 0 Y35 DDR1_DQ 2 CMOS 1 0 w35 DDR2_DQ 1 CMOS 1 0 Y36 vss GND W36 DDR2 DQS NIO CMOS 1 0 Y37 DDR1_DQS_N 0 CMOS 1 0 W37 DDR2 DQS P 0 CMOS 1 0 Y38 DDR1_DQS_P 0 CMOS 1 0 w38 vss GND Y39 DDR1 DQI7 CMOS 1 0 W39 DDR2_DQ 12 CMOS 1 0 Y4 RSVD WA DDRO_DQ 63 CMOS 1 0 Y40 DDR1 DQI6 CMOS 1 0 W40 DDRO DQ 4 CMOS 1 0 Y41 VSS GND W41 DDRO_DQ 0 CMOS 1 0 Y5 RSVD W42 DDRO_DQ 5 CMOS Y6 VSS GND W43 VSS GND Y7 DDR_COMP 1 Analog w5 DDR1 DQ 61 CMOS Y8 DDR1 DQS P 7 CMOS 1 0 W6 DDR1 DQ 56 CMOS Y9 DDR1_DQS_NI 7 CMOS 1 0 W7 DDR1 DQ 57 CMOS 1 0 W8 VSS GND w9 DDR1_DQ 63 CMOS 1 0 73 74 Intel Xeon Processor 3500 Series Land Listing Intel Xeon Processor 3500 Series Datasheet Volume 1 Signal Definitions 5 5 1 Signal Definitions Signal Definitions Table 5 1 Signal Definitions Sheet 1 of 4 Name Type Description Notes BCLK DN Differential bus clock input to the processor BCLK_DP BCLK_ITP_DN O Buffered differential bus clock pair to ITP BCLK_ITP_DP BPM 7 0 1 0 BPM 7 0 are breakpoint and performance mo
26. CMOS 1 0 DDR1 MA 15 F26 CMOS O DDR2_DQI 11 T36 CMOS 1 0 DDR1 MA 2 J17 CMOS O DDR2_DQ 12 w39 CMOS 1 0 41 intel Table 4 1 Land Listing by Land Name Sheet 9 of 36 Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Sheet 10 of 36 Land Name pow T Direction Land Name ro poe Direction DDR2 DQI 13 v39 CMOS 1 0 DDR2_DQ 49 N6 CMOS 1 0 DDR2 DQ 14 T41 CMOS 1 0 DDR2_DQ 5 V34 CMOS DDR2 DQ 15 R40 CMOS DDR2 DQ 50 P9 CMOS 1 0 DDR2_DQ 16 M39 CMOS 1 0 DDR2_DQ 51 P10 CMOS 1 0 DDR2_DQ 17 M40 CMOS DDR2_DQ 52 N8 CMOS 1 0 DDR2 DQ 18 J40 CMOS 1 0 DDR2 DQ 53 N7 CMOS 1 0 DDR2_DQ 19 J39 CMOS 1 0 DDR2_DQ 54 R10 CMOS 1 0 DDR2_DQ 2 36 CMOS 1 0 DDR2_DQ 55 R9 CMOS 1 0 DDR2_DQ 20 P40 CMOS 1 0 DDR2_DQ 56 U5 CMOS 1 0 DDR2_DQ 21 N36 CMOS 1 0 DDR2_DQ 57 U6 CMOS 1 0 DDR2_DQ 22 L40 CMOS 1 0 DDR2_DQ 58 T10 CMOS 1 0 DDR2_DQ 23 K38 CMOS 1 0 DDR2_DQ 59 U10 CMOS 1 0 DDR2_DQ 24 G40 CMOS 1 0 DDR2_DQ 6 V37 CMOS 1 0 DDR2_DQ 25 F40 CMOS 1 0 DDR2_DQ 60 T6 CMOS 1 0 DDR2_DQ 26 J37 CMOS 1 0 DDR2_DQ 61 T7 CMOS 1 0 DDR2_DQ 27 H37 CMOS 1 0 DDR2_DQ 62 v8 CMOS 1 0 DDR2_DQ 28 H39 CMOS 1 0 DDR2_DQ 63 U9 CMOS 1 0 DDR2_DQ 29 G39 CMOS 1 0 DDR2 DQI7 V38 CMOS 1 0 DDR2_DQ 3 U36 CMOS 1 0 DDR2_DQ 8 U38 CMOS 1 0 DDR2_DQ 30 F38 CMOS 1 0 DDR2_DQ 9 U39 CMOS
27. DDRO DQS N 8 CMOS 1 0 C4 DDRO DQ 33 CMOS 1 0 D36 DDR1 ECC O CMOS 1 0 C40 VSS GND D37 DDRO_DQ 27 CMOS 1 0 C41 DDRO_DQ 25 CMOS 1 0 D38 vss GND C42 PREQ GTL 039 RSVD C43 VSS GND D4 RSVD C5 vss GND D40 DDRO_DQ 24 CMOS 1 0 C6 DDRO DQ 37 CMOS 1 0 D41 DDRO_DQ 28 CMOS 1 0 C7 DDRO ODT 3 CMOS D42 DDRO_DQ 29 CMOS 1 0 C8 DDR1_ODT 1 CMOS D43 vss GND C9 DDRO_ODT 1 CMOS D5 RSVD D1 BPM 4 GTL 1 0 D6 DDR1 DQ 38 CMOS 1 0 D10 DDR2_ODT 3 CMOS D7 DDR1 DQS N 4 CMOS 1 0 011 DDR1_ODT 0 CMOS D8 vss GND D12 DDR1_CS 0 CMOS D9 DDR2 CS 5 CMOS D13 VDDQ PWR 1 VSS GND D14 DDR1_ODT 2 CMOS 10 DDR1_CS 5 CMOS D15 DDR2_ODT 2 CMOS 0 E11 VDDQ PWR D16 RSVD E12 RSVD D17 DDR2_RAS CMOS 1 RSVD pis voio jpn En DDR1_CAS CMOS 0 D19 DDRO_CLK_P 1 CLOCK 15 RSVD 66 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 23 of 36 intel Table 4 2 Land Listing by Land Number Sheet 24 of 36 B ffer Direction rand Pin Name Bufer Direction No Type No Type E16 VDDQ PWR F12 DDRO_ODT 0 CMOS O E17 DDR2_CS 4 CMOS F13 DDR2_ODT 1 CMOS O E18 DDRO_CLK_N 2 CLOCK O F14 VDDQ PWR E19 DDRO_CLK_N 3 CLOCK F15 DDR2
28. FC_AH5 AH5 QPI_DRX_DP 15 AN40 QPI ISENSE AK8 Analog QPI_DRX_DP 16 AM42 QPI AH36 Asynch 1 0 QPI_DRX_DP 17 AP41 QPI PRDY B41 GTL O QPI_DRX_DP 18 AN39 QPI PREQ C42 GTL QPI_DRX_DP 19 AP38 QPI PROCHOT AG35 GTL 1 0 QPI_DRX_DP 2 AV36 QPI PSI AP7 CMOS O QPI_DRX_DPI 3 AW36 QPI QPI_CLKRX_DN AR42 QPI QPI_DRX_DP 4 BA36 QPI QPI_CLKRX_DP AR41 QPI QPI_DRX_DP 5 AW37 QPI intel Table 4 1 Land Listing by Land Name Sheet 13 of 36 Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Sheet 14 of 36 Land Name pow T Direction Land Name ro posi Direction QPI DRX DP 6 BA38 QPI QPI DTX DP 5 AK40 QPI QPI_DRX_DP 7 AU39 QPI QPI_DTX_DP 6 AH41 QPI O QPI_DRX_DP 8 AW40 QPI QPI_DTX_DP 7 AK42 QPI O QPI_DRX_DP 9 AU40 QPI QPI DTX DP 8 AJ43 QPI QPI_DTX_DN 0 AH38 QPI QPI DTX DP 9 AG40 QPI QPI_DTX_DN 1 AG39 QPI O RESET AL39 Asynch QPI_DTX_DN 10 AE43 QPI O RSVD AB5 QPI_DTX_DN 11 AE41 QPI 0 RSVD C13 QPI_DTX_DN 12 AC42 QPI O RSVD B9 QPI_DTX_DN 13 AB43 QPI 0 RSVD C11 QPI_DTX_DN 14 AD39 QPI 0 RSVD B8 QPI_DTX_DN 15 AC40 QPI 0 RSVD M43 QPI_DTX_DN 16 AC38 QPI O RSVD G43 QPI_DTX_DN 17 AB38 QPI 0 RSVD C39 DTX DN 18 AE38 QPI O RSVD D4 QPI_DTX_DN 19 AF40 QPI 0 RSVD J1 QPI_DTX_DN
29. Figure 8 1 shows a mechanical representation of a boxed processor Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platforms and chassis Refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 for further guidance Contact your local Intel Sales Representative for this document Mechanical Representation of the Boxed Processor AD y neal Note The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Intel Xeon Processor 3500 Series Datasheet Volume 1 99 n tel Boxed Processor Specifications 8 2 8 2 1 Figure 8 2 100 Mechanical Specifications Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor The boxed processor will be shipped with an unattached fan heatsink Figure 8 1 shows a mechanical representation of the boxed processor Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 8 2 Side View and Figur
30. GND VSS M2 GND VSS W43 GND VSS M20 GND VSS W8 GND VSS M22 GND VSS Y1 GND VSS M24 GND VSS Y11 GND VSS M26 GND VSS Y33 GND vss Ima Y36 GND VSS M30 GND VSS Y41 GND 54 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Sheet 35 of 36 intel Table 4 1 Land Listing by Land Name Sheet 36 of 36 Land Buffer Land Buffer Land Name No Type Direction Land Name No Type Direction VSS Y6 GND VTTD AB34 PWR VSS_SENSE AR8 Analog VTTD AB8 PWR VSS SENSE VIT AE37 Analog VTTD AB9 PWR VTT SENSE AE36 Analog VTTD AC10 PWR VIT VID2 AV3 CMOS O VTTD AC11 PWR VIT VID3 AF7 CMOS O VTTD AC33 PWR VTT_VID4 AV6 CMOS O VTTD AC34 PWR VTTA AD10 PWR VTTD AC35 PWR VTTA AE10 PWR VTTD AD34 PWR VTTA AE11 PWR VTTD AD35 PWR VTTA AE33 PWR VTTD AD36 PWR VTTA AF11 PWR VTTD AD9 PWR VTTA AF33 PWR VTTD AE34 PWR VTTA AF34 PWR VTTD AE35 PWR VTTA AG34 PWR VTTD AE8 PWR VTTD AA10 PWR VTTD AE9 PWR VTTD AA11 PWR VTTD AF36 PWR VTTD AA33 PWR VTTD AF37 PWR VTTD AB10 PWR VTTD AF8 PWR VTTD AB11 PWR VTTD AF9 PWR VTTD AB33 PWR VTTPWRGOOD AB35 Asynch Intel Xeon Processor 3500 Series Datasheet Volume 1 55 intel 4 1 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 1 of 36
31. Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper Processor Markings Figure 3 4 shows the topside markings on the processor This diagram is to aid in the identification of the processor Processor Top Side Markings INTEL 07 PROCH BRAND SLxxx COO SPEED CACHE INTC FMB FPO Intel Xeon Processor 3500 Series Datasheet Volume 1 35 n tel Package Mechanical Specifications 3 9 Processor Land Coordinates Figure 3 5 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Figure 3 5 Processor Land Coordinates and Quadrants Bottom View I 2 gooooooooooooooooO OOOOOOO OQOOOOOOOOOOOOOOOOODOOOOOOOOOOOOOOOOOOOOO Seen 22229 9 9 92 5 92f 0 9 92 2 9 lt 7 C 2 7 7 9 2 2 C2C2CnCo OOOOOOCOOOOOOCOOOOCOOOOCOCQOOOOOCOOCOOOCOOOCOOOCOOOCOOOCOCOOCO tp COODOOOOOOOOCOOOOOOOOOCOCXp9OOOOOOOOOOOOOOCOOOOCOOCO OOOOOOCOOOOOOOOOOCOOCOOCOCXpOOOOOCOOCOOOOOOOOOOOCOOCOOCO OOOOOOOOOOOOOOOOOOOCOCXPOOOOOOOOOOOOCOOOOOOOOO CIOS OOOO OOOO OOOO COCO CUE OOOO OC OO OOOO OOOO OOOO OOOOCOOCOOOCOOOOOOOOOCOOOCXpOOOCOOOOCOOOCOOOOOCOOCOOOOCOO GOGO OOO OOOO OC OO OOO OOO OOOO OO OOOO OOOO OOOO OOO OOOOCOOCOOOOOOOOOCOOOCOOCOCQOOCOCOOCOOCOOCOOOOCOOOCOOCOOCOOOCO OVO OOOOOOOCOOC CO OOOOOOOOOOOOOOOOOCOOO OOOOOOOOOOOOOOOOOOOCO OOO OOOO OOOO OO OOO
32. Keepout Requirements top view R60 0 mm Figure 8 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements side view 104 Intel Xeon Processor 3500 Series Datasheet Volume 1 Boxed Processor Specifications n tel 8 4 2 Figure 8 9 Table 8 2 Variable Speed Fan If the boxed processor fan heatsink 4 pin connector is connected to a 3 pin motherboard header it will operate as follows The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures This allows the processor fan to operate at a lower speed and noise level while internal chassis temperatures are low If internal chassis temperature increases beyond a lower set point the fan speed will rise linearly with the internal temperature until the higher set point is reached At that point the fan speed is at its maximum As fan speed increases so does fan noise levels Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point These set points represented in Figure 8 9 and Table 8 2 can vary by a few degrees from fan heatsink to fan heatsink The internal chassis temperature should be kept below 40 Meeting the processor s temperature specification see Chapter 6 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power header to ensure proper ope
33. Processor I O supply current for DDR3 5 1 A 7 while 53 Icc vcceLL PLL supply current DC AC specification 1 1 Notes 1 2 oO Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with characterized data from silicon measurements at a later date Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and can not be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Please note this differs from the VID employed by the processor during a power management event Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States The voltage specification requirements are measured across VCC_SENSE and VSS_ SENSE lands at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe Refer to Table 2 8 and Figure 2 3 for the minimum typical and maximum Vcc allowed for a given current The processor should not be subjected to any Vcc and Icc combination wherein Veg exceeds Vcc max for a given current E
34. VCC AV9 PWR VCC BA16 PWR VCC AW10 PWR VCC BA18 PWR VCC AW12 PWR VCC BA19 PWR VCC AW13 PWR VCC BA24 PWR Intel Xeon Processor 3500 Series Datasheet Volume 1 49 m e n tel Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 25 of 36 Sheet 26 of 36 Land Name pow T Direction Land Name ro poss Direction VCC BA25 PWR VDDQ C10 PWR VCC BA27 PWR VDDQ C15 PWR VCC BA28 PWR VDDQ C20 PWR VCC BA30 PWR VDDQ C25 PWR VCC BA9 PWR VDDQ C30 PWR VCC M11 PWR VDDQ D13 PWR VCC M13 PWR VDDQ D18 PWR VCC M15 PWR VDDQ D23 PWR VCC M19 PWR VDDQ D28 PWR VCC M21 PWR VDDQ E11 PWR Ivec Ia E16 PWR VCC M25 PWR VDDQ E21 PWR VCC M29 PWR VDDQ E26 PWR VCC M31 PWR VDDQ E31 PWR VCC M33 PWR VDDQ F14 PWR VCC N11 PWR VDDQ F19 PWR VCC N33 PWR VDDQ F24 PWR VCC R11 PWR VDDQ G17 PWR VCC R33 PWR VDDQ G22 PWR VCC T11 PWR VDDQ G27 PWR VCC T33 PWR VDDQ H15 PWR VCC w11 PWR VDDQ H20 PWR VCC_SENSE ARQ Analog VDDQ H25 PWR VCCPLL U33 PWR VDDQ J18 PWR VCCPLL v33 PWR VDDQ J23 PWR VCCPLL W33 PWR VDDQ J28 PWR VCCPWRGOOD AR7 Asynch VDDQ K16 PWR VDDPWRGOOD AAG Asynch VDDQ K21 PWR VDDQ 14 PWR VDDQ K26 PWR VDDQ A19 PWR VDDQ L14 PWR VDDQ A24 PWR VDDQ L19 PWR VDDQ A29 PWR VDDQ L24 PWR VDDQ AQ PWR VDDQ M17 PWR
35. VID 7 Intel Xeon Processor 3500 Series Datasheet Volume 1 16 m Electrical Specifications n tel Table 2 1 Voltage Identification Definition Sheet 3 of 3 VID VID VID VID VID VID VID VID v VID VID VID VID VID VID VID VID v 7 6 5 4 3 2 1 0 GC MAX 7 6 5 4 3 2 1 0 CC MAX 0 1 0 0 1 1 1 1 1 11875 1 0 1 0 1 0 1 0 0 55000 0 1 0 1 0 0 0 0 1 11250 1 0 1 0 1 0 1 1 0 54375 0 1 0 1 0 0 0 1 1 10625 1 0 1 0 1 1 0 0 0 53750 0 1 0 1 0 0 1 0 1 10000 1 0 1 0 1 1 0 1 0 53125 0 1 0 1 0 0 1 1 1 09375 1 0 1 0 1 1 1 0 0 52500 0 1 0 1 0 1 0 0 1 08750 1 0 1 0 1 1 1 1 0 51875 0 1 0 1 0 1 0 1 1 08125 1 0 1 1 0 0 0 0 0 51250 0 1 0 1 0 1 1 0 1 07500 1 0 1 1 0 0 0 1 0 50625 0 1 0 1 0 1 1 1 1 06875 1 0 1 1 0 0 1 0 0 50000 0 1 0 1 1 0 0 0 1 06250 1 1 1 1 1 1 1 0 OFF 0 1 0 1 1 0 0 1 1 05625 1 1 1 1 1 1 1 1 OFF 0 1 0 1 1 0 1 0 1 05000 Table 2 2 Market Segment Selection Truth Table for MS ID 2 0 MSI D2 MSID1 MSIDO Description 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Intel Xeon Processor 3500 Series 1 1 1 Reserved Notes 1 The MSID 2 0 signals are provided to indicate the Market Segment for the processor and may be used for futu
36. Vp Positive edge threshold voltage 0 550 0 725 Vip V High level output source 6 0 source 0 75 m Low level output sink lsi 0 5 1 0 A sink VoL 0 25 m leak High impedance state leakage to Vrrp N A 100 uA 2 Vieak Vou High impedance leakage GND N A 100 UA 2 Vieak Vou Cbus Bus capacitance per node N A 10 pF Vnoise Signal noise immunity above 300 MHz 0 1 Vrrp N A Vp p Notes 1 supplies the interface behavior does not affect V rp min max specifications 2 leakage specification applies to powered devices on the bus Intel Xeon Processor 3500 Series Datasheet Volume 1 m Electrical Specifications n tel 2 9 2 Figure 2 2 2 10 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 2 2 as a guide for input buffer design Input Device Hysteresis Vro Maximum Vp PECI High Range Minimum Vp Minimum V all Input Hysteresis Signal Range Maximum Vy Minimum PECI Ground Absolute Maximum and Minimum Ratings Table 2 6 specifies absolute maximum and minimum ratings which lie outside the functional limits of the processor Only within specified operation limits can functionality and long term reliability be expected At conditions outside fun
37. a function of by the following equation 0 19 43 2 TAMBIENT 0 0077 82 Intel Xeon Processor 3500 Series Datasheet Volume 1 Thermal Specifications n tel 6 1 2 Thermal Metrology The minimum and maximum TTV case temperatures Tease are specified in Table 6 1 and Table 6 2 and are measured at the geometric top center of the thermal test vehicle integrated heat spreader IHS Figure 6 2 illustrates the location where Tease temperature measurements should be made For detailed guidelines on temperature measurement methodology and attaching the thermocouple refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 Figure 6 2 Thermal Test Vehicle TTV Case Temperature Tcase Measurement Location B Measure Tcase geometric center of the top surface of the IHS H m H LID Notes C3 Max 2 3 mm Min 2 2 mm C4 Max 2 3 mm Min 2 2 mm Refer to the appropriate Thermal and Mechanical Design Guide see Section 1 2 for instructions on thermocouple installation on the processor TTV package 1 Figure is not to scale and is for reference only 2 B1 Max 45 07 mm Min 44 93 mm 3 B2 Max 42 57 mm Min 42 43 mm 4 Max 39 1 mm Min 38 9 mm 5 C2 Max 36 6 mm Min 36 4 mm 6 7 8 Intel Xeon Processo
38. a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket The boxed processor will ship with the heatsink attach clip assembly Electrical Requirements Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12 V power supply A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard The power cable connector and pinout are shown in Figure 8 5 Baseboards must provide a matched power header to support the boxed processor Table 8 1 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL The boxed processor s fanheat sink requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification and location should be documented in the platform documentat
39. aka kaka waki a 56 5 1 Signal Definitions an a n R Haa W ka n nA d n ba ka EUR E LEE aa n da ni 75 6 1 Processor Thermal lt nee aka k 80 6 2 Processor Thermal Profile i ikak aka kla kk k kaka ya ak aa a kla klan ka aka a kare a aa ak aa kalan ens 81 6 3 Thermal Solution Performance above 82 6 4 Supported Command Functions and 89 6 5 GetTempO Error Codes 0 nnne nan Aa nil nn nnn 90 6 6 Storage Condition Ratings si Ra e eminens 90 7 1 Power On Configuration Signal Options sss 93 7 2 Coordination of Thread Power States at the Core 94 7 3 Processor S States cocos rh danay ahaa a k l ha o xin Ay d ran nad kn da nA K aa daw WA a w da n Dilana E alan 96 8 1 Fan Heatsink Power and Signal 103 8 2 Fan Heatsink Power and Signal 105 Intel Xeon Processor 3500 Series Datasheet Volume 1 5 intel Intel Xeon Processor 3500 Series Features Available at 3 20 GHz 2 93 GHz and 2 66 GHz Enhanced Intel Speedstep Technology Supports Int
40. and Shared Cache with respect to Vss Voltage for the digital portion of the integrated 1 35 V 3 VTD memory controller Intel QPI link and Shared Cache with respect to Vss V Processor 1 0 supply voltage for DDR3 with 1 875 V DDQ respect to Vss VecPLL Processor PLL voltage with respect to Vss 1 65 1 89 V 1 Processor case temperature See See C CASE Chapter 6 Chapter 6 T Storage temperature See See C STORAGE Chapter 6 Chapter 6 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Vrra Vrrp should be derived from the same VR Processor DC Specifications The processor DC specifications in this section are defined at the processor pads unless noted otherwise See Chapter 4 for the processor land listings and Chapter 5 for signal definitions Voltage and current specifications are detailed in Table 2 7 For platform planning refer to Table 2 8 which provides Vcc static and transient tolerances This same information is presented graphically in Figure 2 3 The DC specifications for the DDR3 signals are listed in Table 2 11 Control Sideband and Test Access Port TAP are listed in Table 2 12 through Table 2 15 Table 2 7 through Table 2 15 list the DC specifications for the processor and are valid only while meeting specifications for
41. case temperature Tease as specified in Chapter 6 Thermal Specifications clock frequency and input voltages Care should be taken to read all notes associated with each parameter Intel Xeon Processor 3500 Series Datasheet Volume 1 Electrical Specifications n tel 2 11 1 DC Voltage and Current Specification Table 2 7 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 1 VID VID range 0 8 1 375 V 2 Processor Vcc for processor core Number Vec W3570 3 20 GHz See Table 2 8 and Figure 2 3 3 4 W3540 2 93 GHz W3520 2 66 GHz Voltage for the analog portion of the Vita integrated memory controller Intel OPI See Table 2 10 and Figure 2 4 V 5 link and Shared Cache Voltage for the digital portion of the Vttp integrated memory controller Intel OPI See Table 2 9 and Figure 2 4 V 5 link and Shared Cache VDDQ Processor I O supply voltage for DDR3 1 425 1 5 1 575 V V PLL supply voltage DC AC 1 71 1 8 1 89 V CCPLL specification Processor Icc for processor Number lec W3570 3 20 GHz 145 A 6 W3540 2 93 GHz 145 W3520 2 66 GHz 145 Current for the analog portion of the 1 integrated memory controller Intel _ _ 5 A link and Shared Cache Current for the digital portion of the l rp integrated memory controller Intel 23 A link and Shared Cache Processor I O supply current for DDR3 6 A S3
42. from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state VCCPWRGOOD can be driven inactive at any time but BCLK and power must again be stable before a subsequent rising edge of VCCPWRGOOD In addition at the time VCCPWRGOOD is asserted RESET must be active The PWRGOOD signal must be supplied to the processor It should be driven high throughout boundary scan operation VDDPWRGOOD VDDPWRGOOD is an input that indicates the Vppo power supply is good The processor requires this signal to be a clean indication that the Vppg power supply is stable and within specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the Vddq supply is turned on until it comes within specification The signals must then transition monotonically to a high state The PwrGood signal must be supplied to the processor VID 7 6 VID 5 3 CSC 2 0 VID 2 0 MSID 2 0 1 0 VID 7 0 Voltage ID are used to support automatic selection of power supply voltages Vcc The voltage supply for these signals must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals become valid The VR must supply the voltage that is requested by the signals or disable itself VID7 and VID6 should be tied separately to
43. hysteresis timer has expired the TCC goes inactive and clock modulation ceases Immediate Transiton to combined TM1 and TM2 As mentioned above when the TCC is activated the processor will sequentially step down the ratio multipliers and VIDs in an attempt to reduce the silicon temperature If the temperature continues to increase and exceeds the TCC activation temperature by approximately 5 C before the lowest ratio VID combination has been reached then the processor will immediately transition to the combined TM1 TM2 condition The processor will remain in this state until the temperature has dropped below the TCC activation point Once below the TCC activation temperature TM1 will be discontinued and TM2 will be exited by stepping up to the appropriate ratio VID state Intel Xeon Processor 3500 Series Datasheet Volume 1 m Thermal Specifications n tel 6 2 2 4 6 2 2 5 6 2 3 Critical Temperature Flag If TM2 is unable to reduce the processor temperature then TM1 will be also be activated TM1 and TM2 will then work together to reduce power dissipation and temperature It is expected that only a catastrophic thermal solution failure would create a situation where both TM1 and TM2 are active If TM1 and TM2 have both been active for greater than 20 ms and the processor temperature has not dropped below the TCC activation point then the Critical Temperature Flag in the A32 THERM STATUS MSR will be set This flag is an
44. indicator of a catastrophic thermal solution failure and that the processor cannot reduce its temperature Unless immediate action is taken to resolve the failure the processor will probably reach the Thermtrip temperature see Section 6 2 3 Thermtrip Signal within a short time To prevent possible permanent silicon damage Intel recommends removing power from the processor within second of the Critical Temperature Flag being set PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor core temperature has exceeded its specification If Adaptive Thermal Monitor is enabled note it must be enabled for the processor to be operating within specification the TCC will be active when PROCHOTZ is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Although the PROCHOTZ signal is an output by default it may be configured as bi directional When configured in bi directional mode it is either an output indicating the processor has exceeded its TCC activation temperature or it can be driven from an external source for example a voltage regulator to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that one or more cores has reached its maximum safe operating
45. interconnect Intel Interconnect Built In Self Test Intel IBIST toolbox built in 1366 land Package ECC and DCA Direct Cache Access Intel Xeon Processor 3500 Series Datasheet Volume 1 Revision History intel Revision Number Description Date 321332 001 Public release March 2009 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Datasheet Volume 1 Introduction 1 Figure 1 1 Note Intel Xeon Processor 3500 Series Datasheet Volume 1 intel Introduction The Intel Xeon Processor 3500 Series are intended for Uni processor UP and workstation systems Several architectural and microarchitectural enhancements have been added to this processor including four processor cores in the processor package and increased shared cache The Intel Xeon Processor 3500 Series is the first multi core processor to implement key new technologies Integrated memory controller Point to point link interface based on Intel QuickPath Interconnect Intel QPI Figure 1 1 shows the interfaces used with these new technologies High Level View of Processor Interfaces Processor Intel QuickPath Interconnect Intel In this document the Intel Xeon Processor 3500 Series will be referred to as the processor The processor is optimized for performance with the power efficiencies of a low powe
46. noise Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage The 4th wire PWM solution provides better control over chassis acoustics This is achieved by more accurate measurement of processor die temperature through the processor s Digital Thermal Sensors DTS and PECI Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the Ath pin of the connector labeled as CONTROL The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures If the new 4 pin active fan heat sink solution is connected to an older 3 pin baseboard processor fan header it will default back to a thermistor controlled Under thermistor controlled mode the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet For more details on specific motherboard requirements for 4 wire based fan speed control see the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 Intel Xeon Processor 3500 Series Datasheet Volume 1
47. platform design guide for implementation details DDR COMP 2 0 resistors are to Vss Table 2 12 RESET Signal DC Specifications Table 2 14 Symbol Parameter Min Typ Max Units Notes Input Low Voltage _ _ 0 40 V ra V 2 Vin Input High Voltage 0 80 Vita _ _ 2 4 lu Input Leakage Current x 200 HA 3 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vma referred to in these specifications refers to instantaneous V ra 3 For Vin between V Measured when the driver is tristated 4 and Voy may experience excursions above Vr Table 2 13 TAP Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes VIL Input Low Voltage _ _ 0 40 x Vita V 2 Vin Input High Voltage 0 75 Vita _ _ 2 4 VoL Output Low Voltage K Vita Ron V 2 Ron Rsys term Vou Output High Voltage VITA V 2 4 Ron Buffer on Resistance 10 18 Q lu Input Leakage Current x 200 HA 3 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vr referred to in these specifications refers to instantaneous Vrra 3 For Vin between V and Measured when the driver is tristated 4 Vin and Voy may experience excursions above Vr PWRGOOD Signal Group DC Specification
48. points that constitute the thermal profile 2 Refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 for system and environmental implementation details 3 The thermal profile is based on data from the Thermal Test Vehicle TTV Table 6 2 Processor Thermal Profile Intel Xeon Processor 3500 Series Datasheet Volume 1 Power TcasE MAX Power TcasE MAX Power TcasE MAX Power Tcase MAX W W W W 0 43 2 34 49 7 68 56 1 100 62 2 2 43 6 36 50 0 70 56 5 102 62 6 4 44 0 38 50 4 72 56 9 104 63 0 6 44 3 40 50 8 74 57 3 106 63 3 8 44 7 42 51 2 76 57 6 108 63 7 10 45 1 44 51 6 78 58 0 110 64 1 12 45 5 46 51 9 80 58 4 112 64 5 14 45 9 48 52 3 82 58 8 114 64 9 16 46 2 50 52 7 84 59 2 116 65 2 18 46 6 52 53 1 86 59 5 118 65 6 20 47 0 54 53 5 88 59 9 120 66 0 22 47 4 56 53 8 90 60 3 122 66 4 24 47 8 58 54 2 92 60 7 124 66 8 26 48 1 60 54 6 94 61 1 126 67 1 28 48 5 62 55 0 96 61 4 128 67 5 30 48 9 64 55 4 98 61 8 130 67 9 32 49 3 66 55 7 81 n tel Thermal Specifications 6 1 1 1 Specification for Operation Where Digital Thermal Sensor Exceeds When the DTS value is less than the fan speed control algorithm can reduce the speed of the thermal solution fan This remains the same as with the previous guidance for fan speed control Duri
49. reflow are specified in by applicable JEDEC standard and MAS document Non adherence may affect processor reliability 3 TABSOLUTE STORAGE applies to the unassembled component only and does not apply to the shipping media moisture barrier bags or desiccant 4 ntel amp branded board products are certified to meet the following temperature and humidity limits that are given as an example only Non Operating Temperature Limit 40 C to 70 C amp Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C Post board attach storage temperature limits are not specified for non Intel amp branded boards Intel Xeon Processor 3500 Series Datasheet Volume 1 Thermal Specifications n tel The J EDEC J J STD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by TSUSTAINED and customer shelf life in applicable intel box and bags Intel Xeon Processor 3500 Series Datasheet Volume 1 91 92 Thermal Specifications Intel Xeon Processor 3500 Series Datasheet Volume 1 Features 7 7 1 Table 7 1 7 2 intel Features Power On Configuration POC Several configuration options can be configured by hardware For electrical specifications on these options refer to Chapter 2 Note that request to ex
50. temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC for all cores TCC activation when PROCHOT is asserted by the system will result in the processor immediately transitioning to the minimum frequency and corresponding voltage using Freq VID control Clock modulation is not activated in this case The TCC will remain active until the system de asserts PROCHOT Use of PROCHOTZ in bi directional mode allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power THERMTRI P Signal Regardless of whether or not Adaptive Thermal Monitor is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Intel Xeon Processor 3500 Series Datasheet Volume 1 87 n tel Thermal Specifications 6 3 6 3 1 6 3 1 1 6 3 1 2 Note 88 Table 5 1 THERMTRIP activation is independent of processor activity The temperature at which THERMTRI
51. the temperature is accomplished through an internal thermal sensor Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To further protect the processor its core voltage Vcc Vita Vrrp and Vppo must be removed following the assertion of THERMTRIP Once activated THERMTRIP remains latched until RESET is asserted While the assertion of the RESET signal may de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted after RESET is de asserted Notes TMS TMS Test Mode Select is a specification support signal used by debug tools TRST VCC TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset Power for processor core VCC_SENSE VSS_SENSE VCC SENSE and VSS SENSE provide an isolated low impedance connection to the processor core power and ground They can be used to sense or measure voltage near the silicon VCCPLL Power for on die PLL filter VCCPWRGOOD VCCPWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that BCLK Vcc Vrra and Vqrp supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches
52. vss GND M25 VCC PWR 70 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 31 of 36 intel Table 4 2 Land Listing by Land Number Sheet 32 of 36 po Pin Name B ffer Direction Bufer Direction No Type No Type M26 VSS GND N41 DDRO_DQ 8 CMOS 1 0 M27 VDDQ PWR N42 RSVD M28 vss GND N43 DDRO_DQ 9 CMOS 1 0 M29 VCC PWR N5 VSS GND M3 DDRO_DQ 52 CMOS 1 0 N6 DDR2_DQ 49 CMOS 1 0 M30 vss GND N7 DDR2_DQ 53 CMOS 1 0 M31 VCC PWR N8 DDR2_DQ 52 CMOS 1 0 M32 vss GND N9 DDR2_DQ 43 CMOS 1 0 M33 VCC PWR Pl RSVD M34 DDR1_DQ 17 CMOS 1 0 P10 DDR2 DQ 51 CMOS 1 0 M35 DDR1 DQ 16 CMOS 1 0 P11 VSS GND M36 DDR1_DQ 21 CMOS 1 0 P2 RSVD M37 VSS GND P3 VSS GND M38 RSVD P33 VSS GND M39 DDR2_DQ 16 CMOS 1 0 P34 DDR1_DQ 8 CMOS 1 0 M4 RSVD P35 DDR1_DQ 9 CMOS 1 0 M40 DDR2_DQ 17 CMOS P36 RSVD M41 DDRO_DQS_N 1 CMOS 1 0 P37 RSVD M42 vss GND P38 vss GND M43 RSVD P39 DDR1 DQ 10 CMOS 1 0 M5 RSVD P4 RSVD M6 DDR1_DQ 53 CMOS 1 0 P40 DDR2_DQ 20 CMOS 1 0 M7 VSS GND P41 DDRO DQ 13 CMOS M8 DDR2 DQ 47 CMOS 42 DDRO DQ 12 CMOS 1 0 M9 DDR2_DQ 42 CMOS 1 0 P43 vss GND N1 DDRO DQ 48 CMOS 1 0 P5 DDR2 DQS N 6 CMOS 10 vss GND P6 DDR2_DQS_P 6 CMOS
53. 0975 12 VID 0 0405 VID 0 0720 VID 0 1035 13 VID 0 0465 VID 0 0780 VID 0 1095 14 VID 0 0525 VID 0 0840 VID 0 1155 15 VID 0 0585 VID 0 0900 VID 0 1215 16 VID 0 0645 VID 0 0960 VID 0 1275 17 VID 0 0705 VID 0 1020 VID 0 1335 18 VID 0 0765 VID 0 1080 VID 0 1395 19 VID 0 0825 VID 0 1140 VID 0 1455 20 VID 0 0885 VID 0 1200 VID 0 1515 21 VID 0 0945 VID 0 1260 VID 0 1575 22 VID 0 1005 VID 0 1320 VID 0 1635 23 VID 0 1065 VID 0 1380 VID 0 1695 24 VID 0 1125 VID 0 1440 VID 0 1755 25 VID 0 1185 VID 0 1500 VID 0 1815 26 VID 0 1245 VID 0 1560 VID 0 1875 27 VID 0 1305 VID 0 1620 VID 0 1935 28 VID 0 1365 VID 0 1680 VID 0 1995 Notes 1 The Iy listed in this table is a sum of Irra and I rp 2 The loadlines specify voltage limits at the die measured at the VIT SENSE VSS SENSE VTT lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VIT SENSE and VSS SENSE VIT lands 26 Intel Xeon Processor 3500 Series Datasheet Volume 1 Electrical Specifications n tel Figure 2 4 Static and Transient Tolerance Load Line Itt A sum of Itta and Ittd 0 5 10 15 20 25 0 0500 0 0375 0 0250 0 0125 0 0000 0 0125 t 0 0250 0 0375 0 0500 0 0625 0 0750 0 0875 0 1000 125 250 Vtt Minimum 375 500 625 750 0 1875 0 2000 0 2125 Vtt Typical Table
54. 1 Introduction 1 2 Table 1 1 intel Unit Interval UI Signaling convention that is binary and unidirectional In this binary signaling one bit is sent for every edge of the forwarded clock whether it is a rising edge or a falling edge If a number of edges are collected at instances ty tp tn tk then the UI at instance n is defined as Ul ta tn 1 Jitter Any timing variation of a transition edge or edges from the defined Unit Interval Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any 1 05 biased or receive any clocks OEM Original Equipment Manufacturer References Material and concepts available in the following documents may be beneficial when reading this document References Document Reference Notes Intel Xeon Processor 3500 Series Specification Update 321333 1 Intel Xeon Processor Series Datasheet Volume 2 321344 1 Intel Xeon Processor 3500 Series and LGA1366 Socket 321461 1 Thermal and Mechanical Design Guide Note 1 Document is available publicly at http www intel com Intel Xeon Processor 3500 Series Datasheet Volume 1 11 12 Introduction Intel Xeon Processor 3500 Series Datasheet Vol
55. 1 0 DDR2_DQ 31 E38 CMOS 1 0 DDR2 DQS NIO0 W36 CMOS 1 0 DDR2_DQ 32 K12 CMOS 1 0 DDR2 DQS NI1 T38 CMOS 1 0 DDR2_DQ 33 J12 CMOS 1 0 DDR2 DQS NI2 K39 CMOS 1 0 DDR2_DQ 34 H13 CMOS 1 0 DDR2 DQS NI3 E40 CMOS 1 0 DDR2_DQ 35 L13 CMOS 1 0 DDR2 DQS NI4 J9 CMOS 1 0 DDR2_DQ 36 G11 CMOS 1 0 DDR2 DQS NI 5 K7 CMOS 1 0 DDR2_DQ 37 G10 CMOS 1 0 DDR2 DQS NI6 P5 CMOS 1 0 DDR2_DQ 38 H12 CMOS 1 0 DDR2 DQS NI7 T8 CMOS 1 0 DDR2_DQ 39 L12 CMOS 1 0 DDR2 DQS NI8 G30 CMOS 1 0 DDR2_DQ 4 U34 CMOS 1 0 DDR2_DQS_P 0 W37 CMOS 1 0 DDR2 DQ 40 L10 CMOS 1 0 DDR2 DQS P 1 T37 CMOS 1 0 DDR2 DQ 41 K10 CMOS 1 0 DDR2_DQS_P 2 K40 CMOS 1 0 DDR2_DQ 42 M9 CMOS 1 0 DDR2_DQS_P 3 E39 CMOS 1 0 DDR2_DQ 43 N9 CMOS 1 0 DDR2_DQS_P 4 J10 CMOS 1 0 DDR2 DQ 44 L11 CMOS DDR2 DQS P 5 L7 CMOS 1 0 DDR2_DQ 45 M10 CMOS 1 0 DDR2_DQS_P 6 P6 CMOS 1 0 DDR2_DQ 46 L8 CMOS 1 0 DDR2_DQS_P 7 U8 CMOS 1 0 DDR2_DQ 47 M8 CMOS 1 0 DDR2_DQS_P 8 G29 CMOS 1 0 DDR2_DQ 48 P7 CMOS 1 0 DDR2_ECC 0 H32 CMOS 1 0 42 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Sheet 11 of 36 intel Table 4 1 Land Listing by Land Name Sheet 12 of 36 Intel Xeon Processor 3500 Series Datasheet Volume 1 Land Name T Direction Land Name n ne Direction DDR2 ECC
56. 1 0 N11 VCC PWR P7 DDR2 DQ 48 CMOS 1 0 N2 DDRO_DQ 49 CMOS 1 0 P8 vss GND N3 DDRO_DQ 53 CMOS 1 0 P9 DDR2_DQ 50 CMOS 1 0 N33 VCC PWR R1 VSS GND N34 DDR1_DQ 20 CMOS 1 0 R10 DDR2_DQ 54 CMOS 1 0 N35 VSS GND R11 VCC PWR N36 DDR2_DQ 21 CMOS 1 0 R2 DDRO_DQS_P 6 CMOS 1 0 N37 DDR1 DQ 14 CMOS 1 0 R3 DDRO DQS N 6 CMOS 1 0 N38 DDR1 DQ 15 CMOS 1 0 R33 VCC PWR N39 DDR1_DQ 11 CMOS R34 DDR1_DQ 12 CMOS 1 0 N4 RSVD R35 DDR1_DQ 13 CMOS 1 0 N40 vss GND R36 vss GND Intel Xeon Processor 3500 Series Datasheet Volume 1 71 n tel Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 33 of 36 Sheet 34 of 36 Land Pin Name Butar Direction Land Pin Name Buffer Direction No Type No Type R37 DDR1_DQS_N 1 CMOS 1 0 U3 DDRO DQ 61 CMOS 1 0 R38 DDR1 DQS P 1 CMOS 1 0 U33 VCCPLL PWR R39 DDR2 DQ 10 CMOS 1 0 U34 DDR2 DQ 4 CMOS 1 0 R4 DDRO DQ 54 CMOS 1 0 U35 RSVD R40 DDR2 DQ 15 CMOS 1 0 U36 DDR2 DQ 3 CMOS 1 0 R41 VSS GND U37 VSS GND R42 DDRO DQ 3 CMOS 1 0 U38 DDR2 DQ 8 CMOS 1 0 R43 DDRO_DQ 2 CMOS 1 0 U39 DDR2 DQ 9 CMOS 1 0 R5 DDR1 DQ 50 CMOS 1 0 U4 DDRO DQ 56 CMOS 1 0 R6 VSS GND U40 RSVD R7 DQI55 cmos ua DDRO_DQI6 CMOS 1 0 R8 DDR1 DQ 54 CMOS 1 0 U42 VSS GND R9 DDR2 DQ 55 CMOS 1 0 U43 DDRO DQS N 0 CMOS 1 0 T1 DDRO_DQ
57. 1 0 0 1 1 55625 0 1 1 0 0 1 0 0 0 98750 0 0 0 0 1 0 1 1 55000 0 1 1 0 0 1 0 1 0 98125 0 0 0 0 1 0 1 1 1 54375 0 1 1 0 0 1 1 o 0 97500 0 0 0 0 1 1 0 1 53750 0 1 1 0 0 1 1 1 0 96875 0 0 0 0 1 1 0 1 1 53125 0 1 1 0 1 0 0 0 0 96250 0 0 0 0 1 1 1 1 52500 0 1 1 0 1 0 0 1 0 95626 0 0 0 0 1 1 1 1 1 51875 0 1 1 0 1 0 1 0 0 95000 0 0 0 1 0 0 0 1 51250 0 1 1 0 1 0 1 1 0 94375 0 0 0 1 0 0 0 1 1 50625 0 1 1 0 1 1 0 0 0 93750 0 0 0 1 0 0 1 1 50000 0 1 1 0 1 1 0 1 0 93125 0 0 0 1 0 0 1 1 1 49375 0 1 1 0 1 1 1 0 0 92500 0 0 0 1 0 1 0 1 48750 0 1 1 0 1 1 1 1 0 91875 0 0 0 1 0 1 0 1 1 48125 0 1 1 1 0 0 0 0 0 91250 0 0 0 1 0 1 1 1 47500 0 1 1 1 0 0 0 1 0 90625 0 0 0 1 0 1 1 1 1 46875 0 1 1 1 0 0 1 0 90000 0 0 0 1 1 0 0 0 1 46250 0 1 1 1 0 0 1 1 0 89375 0 0 0 1 1 0 0 1 1 45625 0 1 1 1 0 1 0 0 0 88750 0 0 0 1 1 0 1 1 45000 0 1 1 1 0 1 0 1 0 88125 0 0 0 1 1 0 1 1 1 44375 0 1 1 1 0 1 1 0 0 87500 0 0 0 1 1 1 0 1 43750 0 1 1 1 0 1 1 1 0 86875 0 0 0 1 1 1 0 1 1 43125 0 1 1 1 1 0 0 0 0 86250 0 0 0 1 1 1 1 1 42500 0 1 1 1 1 0 0 1 0 85625 Intel Xeon Processor 3500 Series Datasheet Volume 1 15 Electrical Specifications intel Sheet 2 of 3 inition Voltage dentification Def Table 2 1 MAX 0 85000 0 84374 0 83750 0 83125 0 82500 0 81875 0 81250 0 80625 0 80000 0 79375 0 78750 0 781
58. 12 DDR2_DQ 33 CMOS 1 0 19 DDR2 DQS NI4 CMOS 1 0 J13 VSS GND K1 VSS GND j14 DDR1 MA 0 CMOS O K10 DDR2 DQ 41 CMOS 1 0 J15 RSVD K11 VSS GND J16 DDR1 MA 1 CMOS O K12 DDR2_DQ 32 CMOS 17 DDR1 MA 2 CMOS K13 DDR1 BA 1 CMOS O J18 VDDQ PWR K14 DDR2_CS 1 CMOS O J19 DDRO_CLK_P 0 CLOCK O K15 RSVD J2 RSVD K16 VDDQ PWR J20 DDR2 MA 3 CMOS O K17 DDR2 MA 1 CMOS O J21 DDR2_CLK_N O CLOCK K18 DDR1_CLK_P 2 CLOCK J22 DDR2_CLK_P 0 CLOCK K19 DDRO CLK N O CLOCK J23 VDDQ PWR K2 DDRO DQS P 5 CMOS 24 DDR2 MA 7 CMOS O K20 DDR2 CLK N 1 CLOCK O J25 RSVD K21 VDDQ PWR J26 DDR2_CKE 0 CMOS O K22 DDR2 MA 6 CMOS O J27 DDR1 MA 6 CMOS K23 DDR2 MA 5 CMOS J28 VDDQ PWR K24 RSVD J29 RSVD K25 RSVD J3 VSS GND K26 VDDQ PWR J30 DDR2_ECC 5 CMOS 1 0 K27 RSVD J31 DDR2_ECC 4 CMOS K28 DDR1_MA 4 CMOS O J32 DDR1_DQ 27 CMOS 1 0 K29 RSVD J33 vss GND K3 DDRO DQS NI 5 CMOS 1 0 J34 DDR1_DQ 28 CMOS 1 0 K30 DDR1_DQ 31 CMOS 1 0 J35 DDR1_DQ 19 CMOS 1 0 K31 VSS GND J36 DDR1_DQ 22 CMOS 1 0 K32 DDR1_DQ 26 CMOS 1 0 Intel Xeon Processor 3500 Series Datasheet Volume 1 69 n tel Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 29 of 36 Sheet 30 of 36 Butter Direction tand Pin Name Buffer Direction No Type No
59. 2 MSID 2 CMOS 1 0 AP5 vss GND AP1 VSS GND AP6 VSS GND AP10 VSS GND AP7 PSI CMOS O AP11 vss GND AP8 VID 6 CMOS O AP12 VCC PWR AP9 VID 5 CSC 2 CMOS 1 0 AP13 VCC PWR AR1 RSVD AP14 VSS GND AR10 VCC PWR AP15 VCC PWR AR11 VSS GND AP16 VCC PWR AR12 VCC PWR AP17 VSS GND AR13 VCC PWR AP18 VCC PWR AR14 VSS GND AP19 VCC PWR AR15 VCC PWR AP2 RSVD AR16 VCC PWR AP20 VSS GND AR17 VSS GND AP21 VCC PWR AR18 VCC PWR AP22 VSS GND AR19 VCC PWR AP23 VSS GND AR2 VSS GND AP24 VCC PWR AR20 VSS GND AP25 VCC PWR AR21 VCC PWR AP26 VSS GND AR22 VSS GND AP27 VCC PWR AR23 VSS GND AP28 VCC PWR AR24 VCC PWR AP29 VSS GND AR25 VCC PWR AP3 RSVD AR26 VSS GND AP30 VCC PWR AR27 VCC PWR AP31 VCC PWR AR28 VCC PWR AP32 VSS GND AR29 VSS GND AP33 VCC PWR AR3 VSS GND AP34 VCC PWR AR30 VCC PWR AP35 VSS GND AR31 VCC PWR AP36 VSS GND AR32 VSS GND AP37 VSS GND AR33 VCC PWR AP38 QPI_DRX_DP 19 QPI AR34 VCC PWR AP39 QPI_DRX_DN 18 QPI AR35 VSS GND APA RSVD AR36 RSVD Intel Xeon Processor 3500 Series Datasheet Volume 1 61 n tel Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 13 of 36 Sheet 14 of 36 Butter Direction Land Pin Name Buffer Direction No Type No Type AR37 RSVD AT33 VCC PWR AR38 QPI_DRX_DN 19 QPI AT34 VCC PWR A
60. 2 GND vss AP1 GND vss AT35 GND vss AP10 GND VSS AT38 GND VSS AP11 GND VSS AT41 GND VSS AP14 GND VSS AT7 GND VSS AP17 GND VSS AT8 GND VSS AP20 GND VSS AUI GND VSS AP22 GND VSS AU11 GND VSS AP23 GND VSS AU14 GND vss AP26 j AU17 GND VSS AP29 GND VSS AU20 GND 52 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing n tel Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 31 of 36 Sheet 32 of 36 Land Name Pt T Direction Land Name ne noe Direction au2 cND Y22 GND vss AU23 GND vss AY23 GND VSS AU26 GND VSS AY26 GND VSS AU29 GND VSS AY29 GND VSS AU32 GND VSS AY32 GND VSS AU35 GND VSS AY37 GND VSS AU36 GND VSS AY42 GND VSS AU43 GND VSS AY7 GND vss AUS GND VSS B2 GND vs wu ono j B37 GND VSS AV14 GND vss B42 GND vss AV17 GND vss 11 GND av2o0 cND BA14 GND vss AV22 GND vss BA17 GND VSS AV23 GND VSS BA20 GND VSS AV26 GND VSS BA26 GND VSS AV29 GND VSS BA29 GND VSS AV32 GND VSS BA3 GND VSS AV39 GND VSS BA35 GND VSS AV4 GND VSS BA39 GND VSS AV41 GND vss BA5 GND VSS AW1 GND VSS C35 GND VSS AW11 GND vss C40 GND VSS AW14 GND vss C43 GND vss Tawiz cnn C5 GND vss AW20 GND vss D3 GND VSS AW22 GND VSS D33 GND VSS AW23 GND VSS D38 GND V
61. 25 0 77500 0 76875 0 76250 0 75625 0 75000 0 74375 0 73750 0 73125 0 72500 0 71875 0 71250 0 70625 0 70000 0 69375 0 68750 0 68125 0 67500 0 66875 0 66250 0 65625 0 65000 0 64375 0 63750 0 63125 0 62500 0 61875 0 61250 0 60625 0 60000 0 59375 0 58750 0 58125 0 57500 0 56875 0 56250 0 55625 0 0 T 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID VID VID VID VID VID VID 1 Vcc MAX 1 41875 1 41250 1 40625 1 40000 1 39375 1 38750 1 38125 1 37500 1 36875 1 36250 1 35625 1 35000 1 34375 1 33750 1 33125 1 32500 1 31875 1 31250 1 30625 1 30000 1 29375 1 28750 1 28125 1 27500 1 26875 1 26250 1 25625 1 25000 1 24375 1 23750 1 23125 1 22500 1 21875 1 21250 1 20625 1 20000 1 19375 1 18750 1 18125 1 17500 1 16875 1 16250 1 15625 1 15000 1 14375 1 13750 1 13125 1 12500 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 VID VID VID VID VID VID VID
62. 4 RSVD Y4 RSVD AC6 RSVD F35 RSVD AC8 RSVD 40 RSVD AD1 RSVD D20 RSVD AD2 RSVD C22 RSVD AD3 RSVD E25 RSVD AD4 RSVD F25 RSVD AD5 RSVD D16 RSVD AD6 RSVD H16 RSVD AD7 RSVD L17 RSVD AD8 RSVD J15 RSVD AE1 RSVD T40 RSVD AE3 RSVD L38 RSVD AE4 RSVD G38 RSVD AE5 RSVD 11 RSVD AE6 RSVD K8 RSVD AF1 RSVD P4 RSVD AF2 RSVD v7 RSVD AF3 RSVD G31 RSVD AF4 RSVD T35 RSVD AF6 RSVD U40 RSVD AG1 RSVD M38 RSVD AG2 RSVD H38 RSVD AG4 RSVD H11 RSVD AG5 RSVD K9 RSVD AG6 RSVD N4 RSVD AG7 Intel Xeon Processor 3500 Series Datasheet Volume 1 45 m e n tel Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 17 of 36 Sheet 18 of 36 Land Name pow Direction Land Name row poss Direction RSVD AG8 RSVD AN2 RSVD AH2 RSVD AN36 RSVD AH3 RSVD AN38 RSVD AH4 RSVD AN4 RSVD AH6 RSVD ANS RSVD AH8 RSVD AN6 RSVD AJ1 RSVD AP2 RSVD AJ2 RSVD AP3 RSVD AJ3 RSVD AP4 RSVD AJ 37 RSVD AR1 Rvo jaa RSVD AR36 RSVD AJ 6 RSVD AR37 RSVD AJ 7 RSVD AR4 RSVD AJ8 RSVD AR5 RSVD AK1 RSVD AR6 RSVD AK2 RSVD AT1 RSVD AK35 RSVD AT2 RSVD AK36 RSVD AT3 RSVD AK4 RSVD AT36 RSVD 5 RSVD AT4 RSVD AK6 RSVD ATS RSVD AL3 RSVD AT6 RSVD AL38 RSVD AU2 RSVD ALA RSVD AU3 RSVD AL40 RSVD AU4 RSVD 141 RSVD AUG RSVD 15 RSVD AU7 RSVD AL6 RSVD AU8 RSVD AL8 RSVD AV1 RSVD AM1 R
63. 50 CMOS 1 0 U5 DDR2_DQ 56 CMOS 1 0 T10 DDR2 DQI 58 CMOS 1 0 U6 DDR2 DQ 57 CMOS 1 0 T11 VCC PWR U7 VSS GND T2 DDRO DQI 51 CMOS 1 0 U8 DDR2 DQS P 7 CMOS 1 0 T3 DDRO_DQ 55 CMOS 1 0 U9 DDR2 DQ 63 CMOS 1 0 T33 VCC PWR 1 DDRO DQ 57 CMOS 1 0 T34 VSS GND V10 VSS GND T35 RSVD 11 RSVD T36 DDR2_DQ 11 CMOS 1 0 v2 RSVD T37 DDR2_DQS_P 1 CMOS 1 0 v3 RSVD T38 DDR2_DQS_N 1 CMOS 1 0 v33 VCCPLL PWR T39 VSS GND V34 DDR2 DQ 5 CMOS 1 0 T4 VSS GND v35 VSS GND T40 RSVD DDR2_DQ 2 CMOS 1 0 T41 DDR2 DQ 14 CMOS 1 0 v37 DDR2 DQ 6 CMOS 1 0 T42 DDRO_DQ 7 CMOS 1 0 v38 DDR2 DQ 7 CMOS 1 0 T43 DDRO_DQS_P 0 CMOS 1 0 v39 DDR2_DQ 13 CMOS 1 0 T5 DDR1 DQI 51 CMOS 1 0 v4 DDRO DQ 62 CMOS 1 0 T6 DDR2 DQI 60 CMOS 1 0 40 vss GND T7 DDR2_DQ 61 CMOS 1 0 41 DDRO DQ 1 CMOS 1 0 T8 DDR2 DQS NI 7 CMOS 1 0 42 RSVD T9 VSS GND v43 RSVD U1 DDRO DQ 60 CMOS 1 0 V5 VSS GND U10 DDR2 DQ 59 CMOS 1 0 V6 RSVD ui rsvo 1 Tv RSVD U2 vss GND v8 DDR2_DQ 62 CMOS 1 0 72 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 35 of 36 intel Table 4 2 Land Listing by Land Number Sheet 36 of 36 Intel Xeon Processor 3500 Series Datasheet Volume 1 B ffer Direction
64. 8 Type 1 0 Description Differential pair ECC Check Bit Strobe Differential strobes latch data ECC for each DRAM Different numbers of strobes are used depending on whether the connected DRAMs are x4 x8 Driven with edges in center of data receive edges are aligned with data edges Notes DDR 0 1 2 _ECC 7 0 1 0 Check Bits An Error Correction Code is driven along with data on these lines for DIMMs that support that capability DDR 0 1 2 _MA 15 0 Selects the Row address for Reads and writes and the column address for activates Also used to set values for DRAM configuration registers DDR 0 1 2 _ODT 3 0 Enables various combinations of termination resistance in the target and non target DIMMs when data is read or written DDR 0 1 2 _RAS Row Address Strobe DDR 0 1 2 _RESET Resets DRAMs Held low on power up held high during self refresh otherwise controlled by configuration register DDR 0 1 2 _WE Write Enable ISENSE PECI 1 0 Current sense from VRD11 1 PECI Platform Environment Control Interface is the serial sideband interface to the processor and is used primarily for thermal power and error management Details regarding the PECI electrical specifications protocols and functions can be found in the Platform Environment Control Interface Specification PRDY PRDY is a processor output used by debug tools to determine processor debug readiness PR
65. C AP18 PWR VCC AT30 PWR pun VCC AT31 PWR VCC AP21 PWR VCC AT33 PWR 48 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing n tel Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 23 of 36 Sheet 24 of 36 Land Name pon T Direction Land Name Fon RE Direction Ivc pwr VCC AW15 PWR VCC AT9 PWR VCC AW16 PWR VCC AU10 PWR VCC AW18 PWR VCC AU12 PWR VCC AW19 PWR VCC AU13 PWR VCC AW21 PWR VCC AU15 PWR VCC AW24 PWR VCC AU16 PWR VCC AW25 PWR VCC AU18 PWR VCC AW27 PWR VCC AU19 PWR VCC AW28 PWR vwc Au21 PWR vcc AW30 PWR VCC AU24 PWR VCC AW31 PWR VCC AU25 PWR VCC AW33 PWR vec az VCC AW34 PWR VCC AU28 PWR VCC AW9 PWR VCC AU30 PWR VCC AY10 PWR VCC AU31 PWR VCC AY12 PWR VCC AU33 PWR VCC AY13 PWR VCC AU34 PWR VCC AY15 PWR VCC AU9 PWR VCC AY16 PWR VCC AV10 PWR VCC AY18 PWR VCC AV12 PWR VCC AY19 PWR VCC AV13 PWR VCC AY21 PWR VCC AV15 PWR VCC AY24 PWR VCC AV16 PWR VCC AY25 PWR vee as VCC AY27 PWR VCC AV19 PWR VCC AY28 PWR VCC AV21 PWR VCC AY30 PWR VCC AV24 PWR VCC AY31 PWR VCC AV25 PWR VCC AY33 PWR VCC AV27 PWR VCC AY34 PWR VCC AV28 PWR VCC AYO PWR VCC AV30 PWR VCC BA10 PWR VCC AV31 PWR VCC BA12 PWR VCC AV33 PWR VCC BA13 PWR VCC AV34 PWR VCC BA15 PWR
66. CC PWR AL28 VCC PWR AK32 VSS GND AL29 VSS GND AK33 VCC PWR AL3 RSVD AK34 VSS GND AL30 VCC PWR AK35 RSVD AL31 VCC PWR AK36 RSVD AL32 VSS GND AK37 QPI_DTX_DP 2 QPI AL33 VCC PWR AK38 QPI_DTX_DN 2 QPI O AL34 VCC PWR AK39 VSS GND AL35 VSS GND AK4 RSVD AL36 VSS GND AK40 QPI_DTX_DP 5 QPI AL37 vss GND AK41 QPI_DTX_DN 5 QPI AL38 RSVD AK42 QPI_DTX_DP 7 QPI O AL39 RESET Asynch AK43 vss GND AL4 RSVD AK5 RSVD AL40 RSVD AK6 RSVD AL41 RSVD AK7 RSVD AL42 VSS GND AK8 ISENSE Analog 1 43 QPI_CMP 0 Analog AK9 VSS GND AL5 RSVD AL1 VSS GND AL6 RSVD AL10 VID 0 MSID 0 CMOS 1 0 AL7 vss GND AL11 vss GND AL8 RSVD AL12 VCC PWR AL9 VID 1 MSID 1 CMOS 1 0 AL13 VCC PWR AM1 RSVD AL14 VSS GND AM10 VID 3 CSC 0 CMOS 1 0 AL15 VCC PWR AM11 VSS GND Intel Xeon Processor 3500 Series Datasheet Volume 1 59 intel Table 4 2 Land Listing by Land Number Sheet 9 of 36 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 10 of 36 Land Pin Name Butter Direction Land Pin Name Buffer Direction No Type No Type AM12 VCC PWR AM9 VSS GND AM13 VCC PWR AN1 RSVD AM14 VSS GND AN10 VID 4 CSC 1 CMOS 1 0 AM15 VCC PWR AN11 VSS GND AM16 VCC PWR AN12 VCC PWR AM17 VSS GND AN13 VCC PWR AM18 VCC PWR AN14 VSS GND AM19 VCC PWR AN15 VCC PWR AM2 RSVD AN16 VCC PWR AM20 V
67. CK O DDRO_DQ 35 G3 CMOS 1 0 DDRO CLK P O J19 CLOCK o DDRO_DQ 36 B6 CMOS 1 0 DDRO_CLK_P 1 D19 CLOCK DDRO_DQ 37 C6 CMOS 1 0 DDRO_CLK_P 2 F18 CLOCK DDRO_DQ 38 F3 CMOS 1 0 DDRO_CLK_P 3 E20 CLOCK DDRO_DQ 39 F2 CMOS 1 0 DDRO_CS 0 G15 CMOS DDRO_DQ 4 w40 CMOS 1 0 DDRO_CS 1 B10 CMOS 0 DDRO_DQ 40 H2 CMOS 1 0 DDRO_CS 1 4 B15 CMOS DDRO_DQ 41 H1 CMOS 1 0 38 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Sheet 3 of 36 intel Table 4 1 Land Listing by Land Name Sheet 4 of 36 Intel Xeon Processor 3500 Series Datasheet Volume 1 Land Name pen T Direction Land Name n Re Direction DDRO DQ 42 L1 CMOS 1 0 DDRO DQS P 3 B39 CMOS 1 0 DDRO_DQ 43 M1 CMOS 1 0 DDRO DQS P 4 E3 CMOS 1 0 DDRO_DQ 44 G1 CMOS 1 0 DDRO DQS P 5 K2 CMOS 1 0 DDRO_DQ 45 H3 CMOS 1 0 DDRO DQS P 6 R2 CMOS 1 0 DDRO_DQ 46 L3 CMOS 1 0 DDRO DQS P 7 W2 CMOS 1 0 DDRO_DQ 47 L2 CMOS 1 0 DDRO_DQS_P 8 D34 CMOS 1 0 DDRO_DQ 48 N1 CMOS 1 0 DDRO_ECC 0 C36 CMOS 1 0 DDRO_DQ 49 N2 CMOS 1 0 DDRO_ECC 1 A36 CMOS 1 0 DDRO_DQ 5 W42 CMOS 1 0 DDRO_ECC 2 F32 CMOS 1 0 DDRO_DQ 50 T1 CMOS 1 0 DDRO_ECC 3 C33 CMOS 1 0 DDRO_DQ 51 T2 CMOS 1 0 DDRO_ECC 4 C37 CMOS 1 0 DDRO_DQ 52 M3 CMOS 1 0 DDRO_ECC 5
68. D H29 RSVD G33 DDR1 DQS P 8 CMOS 1 0 H3 DDRO DQ 45 CMOS 1 0 G34 DDR1 DQS N 8 CMOS 1 0 H30 vss GND G35 DDR1_ECC 7 CMOS 1 0 H31 RSVD G36 DDR1 ECC 3 CMOS 1 0 H32 DDR2 ECC O CMOS 1 0 G37 VSS GND H33 DDR1_DQ 24 CMOS 1 0 G38 RSVD H34 DDR1_DQ 29 CMOS 1 0 G39 DDR2_DQ 29 CMOS 1 0 H35 VSS GND G4 DDR1_DQ 42 CMOS 1 0 H36 DDR1_DQ 23 CMOS 1 0 G40 DDR2_DQ 24 CMOS 1 0 H37 DDR2_DQ 27 CMOS 1 0 G41 DDRO DQS N 2 CMOS 1 0 H38 RSVD ca2 vss DDR2_DQ 28 CMOS 1 0 G43 RSVD H4 DDR1 DQ 43 CMOS 1 0 68 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 27 of 36 intel Table 4 2 Land Listing by Land Number Sheet 28 of 36 Pin Name B ffer Direction Bufer Direction o Type No Type H40 VSS GND J37 DDR2_DQ 26 CMOS 1 0 H41 DDRO_DQ 16 CMOS J38 VSS GND H42 RSVD J39 DDR2_DQ 19 CMOS 1 0 H43 DDRO_DQ 17 CMOS 1 0 J4 DDR1 DQ 52 CMOS H5 VSS GND J40 DDR2 DQ 18 CMOS 1 0 H6 DDR1 DQS P 5 CMOS 1 0 J41 DDRO_DQ 21 CMOS 1 0 H7 RSVD J42 DDRO DQ 20 CMOS 1 0 H8 DDR1_DQ 40 CMOS 1 0 J43 VSS GND H9 DDR1 DQ 45 CMOS 5 DDR1 DQ 47 CMOS 1 0 J1 RSVD J6 DDR1 DQ 41 CMOS 1 0 J10 DDR2 DQS P 4 CMOS 1 0 J7 RSVD Jii RSVD J8 VSS GND J
69. D VSS AL2 GND VSS AE39 GND VSS AL20 GND VSS AE7 GND VSS AL22 GND VSS AF35 GND VSS AL23 GND VSS AF38 GND VSS AL26 GND VSS AF41 GND VSS AL29 GND VSS AF5 GND VSS AL32 GND VSS AG11 GND VSS AL35 GND VSS AG3 GND VSS AL36 GND VSS AG33 GND VSS AL37 GND VSS AG43 GND VSS AL42 GND Intel Xeon Processor 3500 Series Datasheet Volume 1 m e n tel Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 29 of 36 Sheet 30 of 36 Land Name pow T Direction Land Name ro posse Direction VSS AL7 GND VSS AP32 GND VSS AM11 GND VSS AP35 GND VSS AM14 GND VSS AP36 GND VSS AM17 GND VSS AP37 GND VSS AM20 GND VSS AP43 GND VSS AM22 GND VSS AP5 GND VSS AM23 GND VSS AP6 GND VSS AM26 GND VSS AR11 GND VSS AM29 GND VSS AR14 GND VSS AM32 GND VSS AR17 GND juss fams vss AR2 GND VSS AM37 GND VSS AR20 GND VSS AM39 GND VSS AR22 GND VSS 5 GND vss AR23 GND VSS AM9 GND VSS AR26 GND VSS AN11 GND VSS AR29 GND VSS AN14 GND VSS AR3 GND VSS AN17 GND VSS AR32 GND VSS AN20 GND VSS AR35 GND VSS AN22 GND VSS AR39 GND VSS AN23 GND VSS AT11 GND VSS AN26 GND VSS AT14 GND VSS AN29 GND VSS AT17 GND VSS AN3 GND VSS AT20 GND VSS AN32 GND VSS AT22 GND VSS AN35 GND VSS AT23 GND VSS AN37 GND VSS AT26 GND VSS AN41 GND VSS AT29 GND vss AN7 GND vss AT3
70. DQ 16 M35 CMOS DDR1 DQ 51 T5 CMOS 1 0 DDR1_DQ 17 M34 CMOS DDR1_DQ 52 J4 CMOS DDR1 DQ 18 K35 CMOS DDR1 DQ 53 M6 CMOS 1 0 DDR1 DQ 19 J35 CMOS DDR1_DQ 54 R8 CMOS 1 0 DDR1_DQ 2 Y35 CMOS DDR1 DQ 55 R7 CMOS 1 0 DDR1 DQ 20 N34 CMOS 1 0 DDR1 DQ 56 W6 CMOS 1 O DDR1_DQ 21 M36 CMOS 1 0 DDR1 DQ 57 W7 CMOS 1 O DDR1_DQ 22 J36 CMOS 1 0 DDR1_DQ 58 Y10 CMOS 1 0 DDR1_DQ 23 H36 CMOS 1 0 DDR1_DQ 59 W10 CMOS 1 0 DDR1 DQ 24 H33 CMOS 1 0 DDR1_DQ 6 Y40 CMOS 1 0 DDR1_DQ 25 L33 CMOS 1 0 DDR1_DQ 60 v9 CMOS 1 0 DDR1_DQ 26 K32 CMOS 1 0 DDR1 DQ 61 W5 CMOS DDR1_DQ 27 J32 CMOS DDR1 DQ 62 AAT CMOS 40 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Sheet 7 of 36 intel Table 4 1 Land Listing by Land Name Sheet 8 of 36 Intel Xeon Processor 3500 Series Datasheet Volume 1 Land Name x T Direction Land Name n Re Direction DDR1 DQ 63 W9 CMOS 1 0 DDR1 MA 3 L28 CMOS O DDR1_DQ 7 Y39 CMOS 1 0 DDR1 MA 4 K28 CMOS O DDR1_DQ 8 P34 CMOS 1 0 DDR1 MA 5 F22 CMOS O DDR1 DQ 9 P35 CMOS 1 0 DDR1 MA 6 J27 CMOS O DDR1_DQS_N 0 Y37 CMOS 1 0 DDR1 MA 7 D22 CMOS O DDR1_DQS_N 1 R37 CMOS 1 0 DDR1 MA 8 E22 CMOS O DDR1 DQS NI2 L36 CMOS 1 0 DDR1 MA
71. EQ 1 0 PREQ is used by debug tools to request debug operation of the processor PROCHOT 1 0 PROCHOT will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled This signal can also be driven to the processor to activate the Thermal Control Circuit This signal does not have on die termination and must be terminated on the system board PSI RESET Processor Power Status Indicator signal This signal is asserted when maximum possible processor core current consumption is less than 20A Assertion of this signal is an indication that the VR controller does not currently need to be able to provide I CC above 20 and the VR controller can use this information to move to more efficient operation point This signal will de assert at least 3 3 us before the current consumption will exceed 20A The minimum PSI assertion and de assertion time is 1 BCLK Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents Note Some PLL QPI and error states are not effected by reset and only VCCPWRGOOD forces them to a known state For a power on Reset RESET must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications RESET must not be k
72. Intel Xeon Processor 3500 Series Datasheet Volume 1 March 2009 Document Number 321332 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL LIFE SAVING OR LIFE SUSTAINING APPLICATIONS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Xeon Processor 3500 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not acr
73. Intel SpeedStep Technology allows the operating system to reduce power consumption when performance is not needed Execute Disable Bit Execute Disable allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Intel Architecture Software Developer s Manual for more detailed information Refer to http developer intel com for future reference on up to date nomenclatures Intel 64 Architecture An enhancement to Intel s A 32 architecture allowing the processor to execute operating systems and applications written to take advantage of Intel 64 Further details on Intel 64 architecture and programming model be found at http developer intel com technology intel64 Intel virtualization Technology Intel VT A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions Intel VT provides a foundation for widely deployed virtualization solutions and enables a more robust hardware assisted virtualization solution More information can be found at http www intel com technology virtualization Intel Xeon Processor 3500 Series Datasheet Volume
74. MA 13 CMOS O E2 BPM 7 GTL 1 0 F16 DDR2_CAS CMOS O E20 DDRO_CLK_P 3 CLOCK O F17 DDR2 BA 1 CMOS O E21 VDDQ PWR F18 DDRO_CLK_P 2 CLOCK O E22 DDR1 MA 8 CMOS F19 VDDQ PWR E23 DDR1 MA 11 CMOS F2 DDRO DQI 39 CMOS 1 0 E24 DDR1 MA 12 CMOS O F20 DDR2 MA 4 CMOS O E25 RSVD F21 RSVD E26 VDDQ PWR F22 DDR1 MA 5 CMOS O E27 DDR1_CKE 1 CMOS O F23 RSVD E28 RSVD F24 VDDQ PWR E29 DDR2_ECC 2 CMOS 1 0 F25 RSVD E3 DDRO DQS P 4 CMOS 1 0 F26 DDR1 MA 15 CMOS O E30 DDR2_ECC 3 CMOS 1 0 F27 RSVD E31 VDDQ PWR F28 RSVD E32 DDR2_RESET CMOS O F29 VSS GND E33 DDR1_ECC 2 CMOS 1 0 F3 DDRO_DQ 38 CMOS 1 0 E34 DDR1_ECC 6 CMOS 1 0 F30 DDR2_ECC 7 CMOS 1 0 E35 RSVD F31 DDR2_ECC 6 CMOS 1 0 E36 vss GND F32 DDRO_ECC 2 CMOS 1 0 E37 DDR1_ECC 4 CMOS 1 0 F33 DDR2_ECC 1 CMOS 1 0 E38 DDR2_DQ 31 CMOS 1 0 F34 vss GND E39 DDR2 DQS P 3 CMOS 1 0 F35 RSVD E4 DDRO DQS N 4 CMOS 1 0 F36 DDR1_ECC 1 CMOS 1 0 E40 DDR2_DQS_N 3 CMOS F37 DDR1_ECC 5 CMOS 1 0 E41 vss GND F38 DDR2_DQ 30 CMOS 1 0 E42 DDRO_DQ 18 CMOS 1 0 F39 vss GND E43 DDRO_DQ 19 CMOS F4 VSS GND ES DDR1 DQ 34 CMOS 1 0 F40 DDR2 DQ 25 CMOS 1 0 E6 VSS GND F41 DDRO DQS P 2 CMOS 1 0 E7 DDR1 DQS P 4 CMOS 1 0 F42 DDRO DQ 23 CMOS 8 DDR1_DQ 33 CMOS 1 0 F43 DDRO_DQ 22 CMOS 1 0 E9 DDR1_DQ 32 CMOS 1 0 FS DDR1 DQ 35 CMOS Fl DDRO_DQ 34 CMOS 1 0 F6 DDR1_DQ 39 CMOS 1 0 F10 DDR1_DQ 36 CMOS F7 RSVD F11 DDR1_ODT 3 CMOS O F8 RSVD Intel Xeon Processor 3500 Series Datasheet Volume 1 67
75. O DQ 32 CMOS 1 0 T RED B6 DDRO DQ 36 CMOS 1 0 E BT VDDQ PWR C15 VDDQ PWR B8 RSVD C16 DDR2_WE CMOS 0 E fe c17 DDR1_CS 4 CMOS O BATO WI PWR C18 DDR1_BA 0 CMOS BATI j V33 GND C19 DDRO CLOCK lo A Vo we C2 BPM 2 GTL 1 0 BA13 VCC PWR EST que PIR BAl4 VSS GND c21 DDR1_CLK_P 0 CLOCK lo BA15 VCC PWR SCUE Intel Xeon Processor 3500 Series Datasheet Volume 1 65 n tel Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 21 of 36 Sheet 22 of 36 Butter Direction Land Pin Name Buffer Direction No Type No Type C23 DDRO MA 2 CMOS D2 BPM 6 GTL 1 0 C24 DDRO MA 6 CMOS D20 RSVD C25 VDDQ PWR D21 DDR1 CLK CLOCK 0 C26 DDRO MA 9 CMOS D22 DDR1 MA 7 CMOS 0 C27 DDR1_CKE 3 CMOS D23 VDDQ PWR C28 DDRO BA 2 CMOS 0 D24 DDRO MA 3 CMOS 29 DDRO_CKE 0 CMOS D25 RSVD C3 BPM 5 GTL 1 0 D26 DDR2_CKE 2 CMOS C30 VDDQ PWR D27 DDR1_CKE 2 CMOS C31 RSVD D28 VDDQ PWR c32 ryo 29 DDR1_RESET CMOS 0 C33 DDRO ECC 3 CMOS 1 0 D3 vss GND C34 DDRO ECQ 7 CMOS 1 0 D30 RSVD C35 vss GND D31 RSVD C36 DDRO ECC O CMOS 1 0 D32 DDRO_RESET CMOS C37 DDRO ECC 4 CMOS 1 0 D33 vss GND C38 DDRO DQ 30 CMOS 1 0 D34 DDRO DQS P 8 CMOS 1 0 C39 RSVD D35
76. O OC OOOO OOO OOO OOO OOOO OOOO OOOOOOCOOOOOCOOOOOOOOCOOOCQOOCOOOOCOOOOCOOOOCOOCOOOCOO CIOODOOOOOOCOOCOOCOOOOCOOCOCXDOOOOOOOOOOCOOCOOOCOOCOOOOOCO COOOOOOOOOOCOOOOCOOCOOCOOCOOCOOCOOCOOOOOCOOOCOOOOOOOO POOOOOOOOOOOOOOOOCOOCOCXpPOOOOOOOOOOOOOOOOOOOCOCO e ODDOOOOOOOOODOOOO00OOOOOOCOOOOCOOCOOOOOOCOOCOOCOO QOOOOOOOOOOOOOOOOOqQOCOOCOOOOOOOCOOOOOOOOQO OOOOOOO OOOOOOOO 36 Intel Xeon Processor 3500 Series Datasheet Volume 1 e Intel Xeon Processor 3500 Series Land Listing n te D 4 Intel Xeon Processor 3500 Series Land Listing 4 1 Intel Xeon Processor 3500 Series Land Assignments This section provides sorted land list in Table 4 1 and Table 4 2 Table 4 1 is a listing of all processor lands ordered alphabetically by land name Table 4 2 is a listing of all processor lands ordered by land number Intel Xeon Processor 3500 Series Datasheet Volume 1 37 m e n tel Intel Xeon Processor 3500 Series Land Listing 4 1 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 1 of 36 Sheet 2 of 36 Land Name reba psal Direction La
77. OOD VDDPWRGOOD VTTPWRGOOD have ODT in package with a 10 to 20 pulldown to Vss TRST has ODT in package with a 1 to 5 pullup to 4 5 All DDR signals are terminated to VDDQ 2 6 DDR 0 1 2 refers to DDR3 Channel 0 DDR3 Channel 1 and DDR3 Channel 2 7 While TMS and TDI do not have On Die Termination these signals are weakly pulled up using a 1 5 kQ resistor to Vrr 8 While TCK does not have On Die Termination this signal is weakly pulled down using a 1 5 resistor to All Control Asynchronous signals required to be asserted deasserted for at least eight BCLKs for the processor to recognize the proper signal state See Section 2 11 for the DC specifications See Chapter 6 for additional timing requirements for entering and leaving the low power states Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor be first in the TAP chain and followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level Intel Xeon Processor 3500 Series Datasheet Volume 1 19 2 9 1 Table 2 5 20 Electrical Specifications Pla
78. P asserts is not user configurable and is not software visible Platform Environment Control I nterface Introduction The Platform Environment Control Interface PECI is a one wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices The processor implements a PECI interface to allow communication of processor thermal and other information to other devices on the platform The processor provides a digital thermal sensor DTS for fan speed control The DTS is calibrated at the factory to provide a digital representation of relative processor temperature Instantaneous temperature readings from the DTS are available via the 1432 THERM STATUS MSR averaged DTS values are read via the interface The PECI physical layer is a self clocked one wire bus that begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on whether the bit value is a logic 0 or logic 1 PECI also includes variable data transfer rate established with every message The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components Bus speed error checking and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information Fan S
79. QPI AJ 38 QPI_DTX_DP 3 QPI AG43 VSS GND AJ39 QPI DTX DN 3 QPI O AG5 RSVD AJ4 RSVD AG6 RSVD AJ 40 QPI_DTX_DN 4 QPI O AG7 RSVD AJ41 VSS GND AG8 RSVD AJ42 QPI_DTX_DN 7 QPI AG9 VSS GND AJ 43 QPI DTX DP 8 QPI O AH1 VSS GND AJ5 VSS GND AH10 TCK TAP AJ6 RSVD AH11 VCC PWR AJ7 RSVD AH2 RSVD AJ8 RSVD AH3 RSVD AJ9 TDI TAP AH33 VCC PWR AK1 RSVD AH34 VSS GND AK10 VSS GND AH35 BCLK DN CMOS 11 VCC PWR AH36 PECI Asynch 1 0 AK12 VCC PWR AH37 VSS GND AK13 VCC PWR AH38 QPI_DTX_DN 0 QPI O AK14 VSS GND AH39 VSS GND AK15 VCC PWR AH4 RSVD AK16 VCC PWR AH40 QPI_DTX_DP 4 QPI O AK17 VSS GND AH41 QPI_DTX_DP 6 QPI AK18 VCC PWR AH42 QPI_DTX_DN 6 O AK19 VCC PWR 58 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 7 of 36 intel Table 4 2 Land Listing by Land Number Sheet 8 of 36 pog Pin Name orien Direction pui Pin Name ponen Direction AK2 RSVD AL16 VCC PWR AK20 VSS GND AL17 VSS GND AK21 VCC PWR AL18 VCC PWR AK22 VSS GND AL19 VCC PWR AK23 VSS GND AL2 VSS GND AK24 VCC PWR AL20 VSS GND AK25 VCC PWR AL21 VCC PWR AK26 VSS GND AL22 VSS GND AK27 VCC PWR AL23 VSS GND AK28 VCC PWR AL24 VCC PWR AK29 VSS GND AL25 VCC PWR AK3 VSS GND AL26 VSS GND AK30 VCC PWR AL27 VCC PWR AK31 V
80. R39 VSS GND AT35 VSS GND AR4 RSVD AT36 RSVD AR40 QPI DRX DN 12 QPI AT37 QPI_DRX_DP 0 QPI AR41 QPI_CLKRX_DP QPI 8 vss GND AR42 QPI_CLKRX_DN QPI 9 QPI DRX DNI 7 QPI QPI_DRX_DN 11 QPI ATA RSVD AR5 RSVD AT40 QPI_DRX_DP 12 QPI AR6 RSVD AT41 vss GND AR7 vccewnagoopn j Aasynh i A142 QPI_DRX_DN 10 QPI AR8 VSS_ SENSE Analog AT43 QPI_DRX_DP 11 QPI ARQ VCC_SENSE Analog AT5 RSVD AT1 RSVD AT6 RSVD AT10 VCC PWR AT7 VSS GND AT11 vss GND AT8 vss GND AT12 VCC PWR AT9 VCC PWR AT13 VCC PWR AU1 VSS GND AT14 VSS GND AU10 VCC PWR AT15 VCC PWR AU11 VSS GND AT16 VCC PWR AU12 VCC PWR AT17 VSS GND AU13 VCC PWR AT18 VCC PWR AU14 VSS GND AT19 VCC PWR AU15 VCC PWR AT2 RSVD AU16 VCC PWR AT20 VSS GND AU17 VSS GND AT21 VCC PWR AU18 VCC PWR AT22 VSS GND AU19 VCC PWR AT23 VSS GND AU2 RSVD AT24 VCC PWR AU20 VSS GND AT25 VCC PWR AU21 VCC PWR AT26 VSS GND AU22 VSS GND AT27 VCC PWR AU23 VSS GND AT28 VCC PWR AU24 VCC PWR AT29 VSS GND AU25 VCC PWR AT3 RSVD AU26 VSS GND AT30 VCC PWR AU27 VCC PWR vcc ewa ass Ive PWR AT32 vss GND AU29 VSS GND 62 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 15 of 36 intel Table 4 2 Land Listing by Land Number Sheet 16 of 36
81. SS AW26 GND VSS D43 GND VSS AW29 GND VSS D8 GND VSS AW32 GND VSS E1 GND VSS AW35 GND VSS E36 GND VSS AW6 GND VSS E41 GND VSS AW8 GND vss E6 GND vss AY11 GND VSS F29 GND VSS AY14 GND VSS F34 GND VSS AY17 GND VSS F39 GND VSS AY2 GND VSS F4 GND VSS AY20 GND VSS F9 GND Intel Xeon Processor 3500 Series Datasheet Volume 1 53 m e n tel Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 33 of 36 Sheet 34 of 36 Land Name pow T Direction Land Name row poss Direction VSS G12 GND VSS M32 GND VSS G2 GND VSS M37 GND VSS G32 GND VSS M42 GND VSS G37 GND VSS M7 GND VSS G42 GND VSS N10 GND VSS G7 GND VSS N35 GND VSS H10 GND VSS N40 GND VSS H30 GND VSS N5 GND VSS H35 GND VSS P11 GND VSS H40 GND VSS P3 GND vss HS GND vss P33 GND VSS J13 GND VSS P38 GND VSS J3 GND VSS P43 GND VSS J33 GND VSS P8 GND VSS J38 GND VSS R1 GND VSS J43 GND VSS R36 GND VSS J8 GND VSS R41 GND VSS K1 GND VSS R6 GND VSS K11 GND VSS T34 GND VSS K31 GND VSS T39 GND VSS K36 GND VSS T4 GND VSS K41 GND VSS T9 GND VSS K6 GND VSS U2 GND VSS L29 GND VSS U37 GND VSS L34 GND VSS U42 GND VSS L39 GND VSS U7 GND VSS L4 GND vss V10 GND VSS L9 GND VSS v35 GND vss M12 GND vss v40 GND vss M14 GND vss V5 GND vss M16 GND VSS W3 GND VSS M18 GND VSS W38
82. SS GND AN17 VSS GND AM21 VCC PWR AN18 VCC PWR AM22 VSS GND AN19 VCC PWR AM23 VSS GND AN2 RSVD AM24 VCC PWR AN20 VSS GND AM25 VCC PWR AN21 VCC PWR AM26 VSS GND AN22 VSS GND AM27 VCC PWR AN23 VSS GND AM28 VCC PWR AN24 VCC PWR AM29 VSS GND AN25 VCC PWR AM3 RSVD AN26 VSS GND AM30 VCC PWR AN27 VCC PWR AM31 VCC PWR AN28 VCC PWR AM32 VSS GND AN29 VSS GND AM33 VCC PWR AN3 VSS GND AM34 VCC PWR AN30 VCC PWR AM35 VSS GND AN31 VCC PWR AM36 RSVD AN32 VSS GND AM37 VSS GND AN33 VCC PWR AM38 RSVD AN34 VCC PWR AM39 VSS GND AN35 VSS GND AM4 RSVD AN36 RSVD AM40 QPI_DRX_DN 15 QPI AN37 VSS GND AM41 QPI_DRX_DN 16 QPI AN38 RSVD AM42 QPI_DRX_DP 16 QPI AN39 QPI_DRX_DP 18 QPI AM43 QPI_DRX_DN 14 QPI ANA RSVD AM5 vss GND AN40 QPI_DRX_DP 15 QPI AM6 RSVD AN41 VSS GND AM7 RSVD AN42 QPI_DRX_DN 13 QPI 8 RSVD AN43 QPI_DRX_DP 14 QPI 60 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 2 Land Listing by Land Number Sheet 11 of 36 intel Table 4 2 Land Listing by Land Number Sheet 12 of 36 n Pin Name vv Direction posed Direction AN5 RSVD AP40 QPI_DRX_DN 17 QPI AN6 RSVD AP41 QPI_DRX_DP 17 QPI 7 VSS GND AP42 QPI_DRX_DP 13 QPI 8 VID 7 CMOS O AP43 vss GND AN9 VID
83. SVD AV2 RSVD AM2 RSVD AV35 RSVD AM3 RSVD AV42 RSVD AM36 RSVD AV43 RSVD AM38 RSVD AV5 RSVD AMA RSVD AV7 RSVD AM6 RSVD AV8 RSVD AM7 RSVD AW2 Rvo amem RSVD AW3 RSVD AN1 RSVD AW39 46 Intel Xeon Processor 3500 Series Datasheet Volume 1 Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Sheet 19 of 36 intel Table 4 1 Land Listing by Land Name Sheet 20 of 36 Land Name po pomi Direction Land Name Fn Direction RSVD AW4 SKTOCC AG36 GTL O RSVD AW41 TCK AH10 TAP RSVD AW42 TDI AJ 9 TAP RSVD AWS TDO AJ 10 TAP O RSVD AW7 THERMTRIP AG37 GTL O RSVD AY3 TMS AG10 TAP RSVD AY35 TRST AH9 TAP RSVD AY39 VCC AH11 PWR RSVD AY4 VCC AH33 PWR RSVD AY40 VCC AJ11 PWR RSVD AY41 VCC AJ 33 PWR RSVD AY5 VCC AK11 PWR RSVD AY6 VCC AK12 PWR RSVD AY8 VCC AK13 PWR RSVD B33 VCC AK15 PWR RSVD BA4 VCC AK16 PWR RSVD BA40 VCC AK18 PWR RSVD BA6 VCC AK19 PWR RSVD BA7 VCC AK21 PWR RSVD BA8 VCC AK24 PWR RSVD C31 VCC AK25 PWR RSVD C32 VCC AK27 PWR RSVD D30 VCC AK28 PWR RSVD D31 VCC AK30 PWR RSVD E28 VCC AK31 PWR RSVD F27 VCC AK33 PWR RSVD F28 VCC AL12 PWR RSVD G28 VCC AL13 PWR RSVD H29 VCC AL15 PWR RSVD J29 VCC AL16 PWR RSVD K15 VCC AL18 PWR RSVD K24 VCC AL19 PWR RSVD K25 VCC AL21 PWR RSVD K27 VCC AL24 PWR RSVD K29
84. VCC AL25 PWR RSVD L15 VCC AL27 PWR RSVD U11 VCC AL28 PWR RSVD V11 VCC AL30 PWR RSVD AK7 VCC AL31 PWR Intel Xeon Processor 3500 Series Datasheet Volume 1 47 m e n tel Intel Xeon Processor 3500 Series Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 21 of 36 Sheet 22 of 36 Land Name pos T Direction Land Name ro poss Direction VCC AL33 PWR VCC AP24 PWR VCC AL34 PWR VCC AP25 PWR VCC AM12 PWR VCC AP27 PWR VCC AM13 PWR VCC AP28 PWR VCC AM15 PWR VCC AP30 PWR VCC AM16 PWR VCC AP31 PWR VCC AM18 PWR VCC AP33 PWR VCC AM19 PWR VCC AP34 PWR VCC AM21 PWR VCC AR10 PWR VCC AM24 PWR VCC AR12 PWR vcc ams vcc AR13 PWR VCC AM27 PWR VCC AR15 PWR VCC AM28 PWR VCC AR16 PWR VCC AM30 PWR VCC AR18 PWR VCC AM31 PWR VCC AR19 PWR VCC AM33 PWR VCC AR21 PWR VCC AM34 PWR VCC AR24 PWR VCC AN12 PWR VCC AR25 PWR VCC AN13 PWR VCC AR27 PWR VCC AN15 PWR VCC AR28 PWR VCC AN16 PWR VCC AR30 PWR VCC AN18 PWR VCC AR31 PWR VCC AN19 PWR VCC AR33 PWR VCC AN21 PWR VCC AR34 PWR VCC AN24 PWR VCC AT10 PWR VCC AN25 PWR VCC AT12 PWR VCC AN27 PWR VCC AT13 PWR VCC AN28 PWR VCC AT15 PWR VCC AN30 PWR VCC AT16 PWR VCC AN31 PWR VCC AT18 PWR VCC AN33 PWR VCC AT19 PWR VCC AN34 PWR VCC AT21 PWR VCC AP12 PWR VCC AT24 PWR VCC AP13 PWR VCC AT25 PWR VCC AP15 PWR VCC AT27 PWR VCC AP16 PWR VCC AT28 PWR VC
85. Vss using a 1 kQ resistor during reset This value is latched on the rising edge of VITTPWRGOOD MSID 2 0 MSID 2 0 is used to indicate to the processor whether the platform supports a particular TDP A processor will only boot if the MSID 2 0 pins are strapped to the appropriate setting on the platform see Table 2 2 for MSID encodings In addition MSID protects the platform by preventing a higher power processor from booting in a platform designed for lower power processors CSC 2 0 Current Sense Configuration bits for ISENSE gain setting This value is latched on the rising edge of VTTPWRGOOD Vita Power for analog portion of the integrated memory controller and Shared Cache Power for the digital portion of the integrated memory controller and Shared Cache Intel Xeon Processor 3500 Series Datasheet Volume 1 77 Bi intel E Table 5 1 Signal Definitions Sheet 4 of 4 Name Type Description Notes VIT VID 4 2 O VTT_VID 2 4 VTT Voltage ID are used to support automatic selection of power supply voltages Vr VTT SENSE O VTT_SENSE and VSS_SENSE_VTT provide an isolated low impedance VSS SENSE VTT 0 connection to the processor Vrr voltage and ground They can used to sense or measure voltage near the silicon VTTPWRGOOD The processor requires this input signal be a clean indication that the V power supply is stable and within specifica
86. Yc that meets the TTV thermal profile specifications A single integer change in the PECI value corresponds to approximately 1 C change in processor temperature Although each processors DTS is factory calibrated the accuracy of the DTS will vary from part to part and may also vary slightly with temperature and voltage In general each integer change in PECI should equal a temperature change between 0 9 C and 1 1 C Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP instead of the maximum processor power consumption The Adaptive Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature refer to Section 6 2 Refer to the appropriate processor Thermal and Mechanical Design Guide see Section 1 2 for details on system thermal solution design thermal profiles and environmental considerations Table 6 1 Processor Thermal Specifications Cora Thermal Idle Minimum Maximum TTV TOM Processor F Design Power Power TTV TcAsE TcasE 9 Notes requency W cw C Processor TTV c W W3570 3 20 GHz 130 12 5 0 222 W3540 2 93 GHz 130 12 5 0 222 Doom W3520 2 66 GHz 130 15 5 0 222
87. as entered via MWAIT Thread and Core Power State Descriptions Individual threads may request low power states Core power states are automatically resolved by the processor as shown in Table 7 2 Coordination of Thread Power States at the Core Level Thread1 State Core State CO c 1 C3 C6 CO co co co co Threado C1 CO c c c State C3 co cil C3 C3 C6 CO cil C3 C6 Notes 1 If enabled state will be CIE CO State This is the normal operating state in the processor C1 C1E State C1 CIE is a low power state entered when all threads within a core execute a HLT or MWAIT CIE instruction The processor thread will transition to the CO state upon occurrence of an interrupt or an access to the monitored address if the state was entered via the MWAIT instruction RESET will cause the processor to initialize itself A System Management Interrupt SMI handler will return execution to either Normal state or the C1 state See the Intel 64 and IA 32 Architectures Software Developer s Manuals Volume 111 System Programmer s Guide for more information Intel Xeon Processor 3500 Series Datasheet Volume 1 Features 7 2 1 3 7 2 1 4 7 2 2 7 2 2 1 7 2 2 2 7 2 2 3 intel While in C1 C1E state the processor will process bus snoops and snoops from the other threads C3 State Individual threads of the processor can enter the state by initiatin
88. by multiplying the ratio by 133 MHz PLL Power Supply An on die PLL filter solution is implemented on the processor Refer to Table 2 7 for DC specifications Voltage Identification VID The voltage set by the VID signals is the reference voltage regulator output voltage to be delivered to the processor VCC pins VID signals are CMOS push pull drivers Refer to Table 2 15 for the DC specifications for these signals The VID codes will change due to temperature and or current load changes in order to minimize the power of the part A voltage range is provided in Table 2 7 The specifications have been set such that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during manufacturing such that two devices at the same core frequency may have different default VID settings This is reflected by the VID range values provided in Table 2 1 Intel Xeon Processor 3500 Series Datasheet Volume 1 Electrical Specifications n tel The processor uses eight voltage identification signals VID 7 0 to support automatic selection of voltages Table 2 1 specifies the voltage level corresponding to the state of VID 7 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 7 0 11111111 or the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable i
89. ctional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from Electro Static Discharge ESD precautions should always be taken to avoid high static voltages or electric fields Intel Xeon Processor 3500 Series Datasheet Volume 1 21 n tel Electrical Specifications Table 2 6 2 11 22 Processor Absolute Minimum and Maximum Ratings Symbol Parameter Min Max Unit Notes 2 Vcc Processor Core voltage with respect to Vss 0 3 1 55 V Voltage for the analog portion of the integrated 1 35 V 3 memory controller Intel QPI link
90. d during the averaging window As TCC activation time increases the fractional value will approach zero Fan control circuits can detect this situation and take appropriate action as determined by the system designers Of course fan control chips can also monitor the Prochot pin to detect TCC activation via a dedicated input pin on the package Further details on how the Thermal Averaging Constant influences the fractional temperature values are available in the Thermal Design Guide PECI Specifications PECI Device Address The PECI register resides at address 30h PECI Command Support The processor supports the PECI commands listed in Table 6 4 Supported PECI Command Functions and Codes Command Code Comments Function This command targets a valid PECI device address followed by zero Ping n a Write Length and zero Read Length Write Length 1 GetTempO 01h Read Length 2 Returns the temperature of the processor in Domain 0 PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios wh
91. d terms are explained here for clarification Intel Xeon Processor 3500 Series The entire product including processor substrate and integrated heat spreader IHS 1366 land LGA package The Intel Xeon Processor 3500 Series is available in a Flip Chip Land Grid Array FC LGA package consisting of the processor mounted on a land grid array substrate with an integrated heat spreader IHS LGA1366 Socket The processor in the LGA 1366 package mates with the system board through this surface mount 1366 contact socket DDR3 Double Data Rate 3 Synchronous Dynamic Random Access Memory SDRAM is the name of the new DDR memory standard that is being developed as the successor to DDR2 SRDRAM Intel QuickPath I nterconnect I ntel Intel is a cache coherent point to point link based electrical interconnect specification for Intel processors and chipsets Integrated Memory Controller A memory controller that is integrated into the processor die Integrated Heat Spreader I HS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC signal quality mechanical and thermal are satisfied Enhanced Intel SpeedStep Technology Enhanced
92. e 6 3 for the required thermal solution performance table when DTS values are greater than TcontroL Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system When the DTS value is less than Tcontrol the thermal solution performance is not defined and the fans may be slowed down This is unchanged from the prior specification For more details on thermal solution design refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 The processors implement a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Digital Temperature Sensor DTS The DTS can be read via the Platform Environment Control Interface PECI as described in Intel Xeon Processor 3500 Series Datasheet Volume 1 79 n tel Thermal Specifications Section 6 3 The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 6 2 Processor Thermal Features Systems that implement fan speed control must be designed to use this data Systems that do not alter the fan speed only need to guarantee the thermal solution provides the
93. e 8 3 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 8 7 and Figure 8 8 Note that some figures have centerlines shown marked with alphabetic designations to clarify relative dimensioning Space Requirements for the Boxed Processor side view 104 0 4 09 81 3 3 20 10 1 27 0 40 1 06 Intel Xeon Processor 3500 Series Datasheet Volume 1 Boxed Processor Specifications n tel Figure 8 3 Space Requirements for the Boxed Processor top view 104 0 4 09 i 104 0 4 09 1 Notes 1 Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation Figure 8 4 Space Requirements for the Boxed Processor overall view Intel Xeon Processor 3500 Series Datasheet Volume 1 101 n tel Boxed Processor Specifications 8 2 3 8 3 8 3 1 Figure 8 5 102 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams See Chapter 6 and the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 for details on the processor weight and heatsink requirements Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembiy The boxed processor thermal solution requires
94. ecute BIST is not selected by hardware but is passed across the Intel QPI link during initialization The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset and a power on reset Power On Configuration Signal Options Configuration Option Signal MSID VID 2 0 MSID 2 0 2 CSC VID 5 3 CSC 2 0 2 Notes 1 Latched when VITPWRGOOD is asserted and all internal power good conditions are met 2 See the signal definitions in Table 6 1 for the description of MSID and CSC Clock Control and Low Power States The processor supports low power states at the individual thread core and package level for optimal power management The processor implements software interfaces for requesting low power states MWAIT instruction extensions with sub state hints the HLT instruction for C1 and CIE and P LVLx reads to the ACPI P BLK register block mapped in the processor s 1 0 address space The P LVLx I O reads are converted to equivalent MWAIT C state requests inside the processor and do not directly result in I O reads to the system The P LVLx I O Monitor address does not need to be set up before using the P LVLx 1 0 read interface Software may make C state requests by using a legacy method involving I O reads from the ACPI defin
95. ed processor clock control registers referred to as P LVLx This feature is designed to provide legacy support for operating systems that initiate C state transitions via access to pre defined registers The base P LVLx register is P LVL2 corresponding to a C3 request P LVL3 is C6 P LVLx is limited to a subset of C states For Example P LVL8 is not supported and will not cause 1 0 redirection to a C8 request Instead it will fall through like a normal I O instruction The range of I O addresses that may be converted into C state requests is also defined in the IO CAPTURE MSR in the C state Range field This field maybe written by BIOS to restrict the range of I O addresses that are trapped and redirected to MWAIT instructions Note that when 1 0 instructions are used no MWAIT substates can be defined as therefore the request defaults to have a sub state or zero but always assumes the break on F 0 control that can be selected using ECX with an MWAIT instruction Intel Xeon Processor 3500 Series Datasheet Volume 1 93 intel Figure 7 1 7 2 1 Table 7 2 7 2 1 1 7 2 1 2 94 Power States MWAIT C1 HLT MWAIT C6 C6 2 MWAIT C1 HLT C1E enabled MWAIT C3 1 No transition to CO is needed to service a snoop when in C1 or C1E 2 Transitions back to CO occur on an interrupt or on access to monitored address if state w
96. eing stored The specified storage conditions are for component level prior to board attach see following notes on post board attach limits Table 6 6 specifies absolute maximum and minimum storage temperature limits which represent the maximum or minimum device condition beyond which damage latent or otherwise may occur The table also specifies sustained storage temperature relative humidity and time duration limits At conditions outside sustained limits but within absolute maximum and minimum ratings quality amp reliability may be affected Storage Condition Ratings Symbol Parameter Min Max Notes Tabs storage The non operating device storage 55 C 125 C 1 2 3 temperature beyond which damage latent or otherwise may occur when subjected to for any length of time Tsustained storage The ambient storage temperature limit in 5 40 4 5 shipping media for a sustained period of time RHsustained storage The maximum device storage relative 60 24 C 60 24 C 5 6 humidity for a sustained period of time Timesustained storage A prolonged or extended period of time 0 months 6 months 6 typically associated with customer shelf life Notes 1 Refers to a component device that is not assembled a board or socket that is not to be electrically connected to a voltage reference or 1 0 signals 2 Specified temperatures are based on data collected Exceptions for surface mount
97. el 64 Architecture Multiple low power states 8 way cache associativity provides improved cache hit rate on load store operations System Memory Interface Supports Intel virtualization Technology Intel Turbo Boost Technology Supports Execute Disable Bit capability Binary compatible with applications running on previous members of the Intel microprocessor line Intel wide Dynamic Execution Very deep out of order execution Enhanced branch prediction Optimized for 32 bit applications running on advanced 32 bit operating systems Intel Smart Cache 8 MB Level 3 cache Intel Advanced Digital Media Boost Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance New accelerators for improved string and text processing operations Power Management capabilities System Management mode Memory controller integrated in processor package 3 channels 2 DIMMs channel supported 6 total 24 GB maximum memory supported Support unbuffered DIMMs only Single Rank and Dual Rank DIMMs supported DDR3 speeds of 800 1066 MHz supported 512 Mb 1 Gb 2 Gb Technologies Densities supported e Intel QuickPath Interconnect Intel Fast narrow unidirectional links Concurrent bi directional traffic Error detection via CRC Error correction via Link level retry Packet based protocol Point to point cache coherent
98. ept asserted for more than 10 ms while VCCPWRGOOD is asserted RESET must be held deasserted for at least one millisecond before it is asserted again RESET must be held asserted before VCCPWRGOOD is asserted This signal does not have on die termination and must be terminated on the system board RESET is a common clock signal SKTOCC SKTOCC Socket Occupied will be pulled to ground on the processor package There is no connection to the processor silicon for this signal System board designers may use this signal to determine if the processor is present TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support TESTLOW 76 TESTLOW must be connected to ground through a resistor for proper processor operation Intel Xeon Processor 3500 Series Datasheet Volume 1 Signal Definitions Table 5 1 Signal Definitions Sheet 3 of 4 intel Name THERMTRIP Type O Description Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur Measurement of
99. ere the PECI is know to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not ensured to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI Intel Xeon Processor 3500 Series Datasheet Volume 1 89 6 3 2 4 Table 6 5 6 4 Table 6 6 90 Thermal Specifications To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host controller should take action to protect the system from possible damaging states If the Host controller cannot complete a valid PECI transactions of GetTemp0 with a given PECI device over 3 consecutive failed transactions or a one second max specified interval then it should take appropriate actions to protect the corresponding device and or other system components from overheating The host controller may also implement an alert to software in the event of a critical or continuous fault condition PECI GetTempO Error Code Support The error codes supported for the processor GetTemp command are listed in Table 6 5 GetTempO Error Codes Error Code Description 8000h General sensor error Storage Conditions Specifications Environmental storage condition limits define the temperature and relative humidity limits to which the device is exposed to while b
100. ermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result a Tease that exceeds the specified maximum temperature and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the appropriate processor Thermal and Mechanical Design Guide see Section 1 2 for information on designing a compliant thermal solution Intel Xeon Processor 3500 Series Datasheet Volume 1 m Thermal Specifications n tel 6 2 2 1 The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines The following sections provide more details on the different TCC mechanisms used by the Intel Xeon Processor 3500 Series Frequency VID Control When the Digital Temperature Sensor DTS reaches a value of 0 DTS temperatures reported via may not equal zero when PROCHOT is activated see Section 6 3 for further details the TCC will be activated and the PROCHOT signal will be asserted This indicates the processors temperature has met or exceeded the factory calibrated trip temperature and it will take action to reduce the temperature Upon activation of the TCC the processor will stop the core clocks reduce the core rat
101. essor power planes while all VSS lands must be connected to the system ground plane The processor VCC lands must be supplied with the voltage determined by the processor Voltage I Dentification VID signals Table 2 1 specifies the voltage level for the various VIDs Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cgu k such as electrolytic capacitors supply current during longer lasting changes in current demand such as coming out of an idle condition Similarly capacitors act as a storage well for current when entering an idle condition from a running condition Care must be taken in the baseboard design to Intel Xeon Processor 3500 Series Datasheet Volume 1 13 n tel Electrical Specifications 2 3 1 2 4 2 4 1 2 5 14 ensure that the voltage provided to the processor remains within the specifications listed in Table 2 7 Failure to do so can result in timing violations or reduced lifetime of the processor Vec VITA VTD VDDQ Decoupling Voltage regulator solutions need to provide bulk capacitance and the baseboard designer must assure a low interconnect resistance from the regulator to the LGA1366 socket Bulk decoupling must be provided o
102. ew values on the VID pins and the PLL then locks to the new frequency If the target frequency is lower than the current frequency the PLL locks to the new frequency and the Vcc is changed through the VID pin mechanism Software transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition completes The processor controls voltage ramp rates internally to ensure smooth transitions Low transition latency and large number of transitions possible per second Processor core including shared cache is unavailable for less than 5 us during the frequency transition 97 98 Features Intel Xeon Processor 3500 Series Datasheet Volume 1 Boxed Processor Specifications n tel 8 8 1 Note Note Figure 8 1 Boxed Processor Specifications Introduction The processor will also be offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from baseboards and standard components The boxed processor will be supplied with a cooling solution This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor This chapter is particularly important for OEMs that manufacture baseboards for system integrators Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets
103. fications The processor thermal specification uses the on die Digital Thermal Sensor DTS value reported via the PECI interface for all processor temperature measurements The DTS is a factory calibrated analog to digital thermal sensor As a result it will no longer be necessary to measure the processors case temperature Consequently there will be no need for a Thermal Profile specification defining the relationship between the processors TcAse and power dissipation Note Unless otherwise specified the term DTS refers to the DTS value returned by from the PECI interface gettemp command Note A thermal solution that was verified compliant to the processor case temperature thermal profile at the customer defined boundary conditions is expected to be compliant with this update No redesign of the thermal solution should be necessary A fan speed control algorithms that was compliant to the previous thermal requirements is also expected to be compliant with this specification The fan speed control algorithm can be updated to utilize the additional information to optimize acoustics To allow the optimal operation and long term reliability of Intel processor based systems the processor thermal solution must deliver the specified thermal solution performance in response to the DTS sensor value The thermal solution performance will be measured using a Thermal Test Vehicle TTV See Table 6 1 and Figure 6 1 for the TTV thermal profile and Tabl
104. g a P_LVL2 1 0 read to the P_BLK or an MWAIT C3 instruction Before entering core C3 the processor flushes the contents of its caches Except for the caches the processor core maintains all its architectural state while in the C3 state All of the clocks in the processor core are stopped in the C3 state Because the core s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the Intel QPI Link or when another logical processor in the same package accesses cacheable memory The processor core will transition to the CO state upon occurrence of an interrupt RESET will cause the processor core to initialize itself C6 State Individual threads of the processor can enter the C6 state by initiating a P_LVL3 read to the P_BLK or an MWAIT C6 instruction Before entering Core C6 the processor saves core state data such as registers to the last level cache This data is retired after exiting core C6 The processor achieves additional power savings in the core C6 state Package Power State Descriptions The package supports CO C3 and C6 power states Note that there is no package C1 state The package power state is automatically resolved by the processor depending on the core power states and permission from the rest of the system as described in the following sections Package CO State This is the normal operating state for the processor The processor remains in the Normal state when a
105. hoot events at the processor must meet the specifications in Table 2 16 when measured across the SENSE and VSS SENSE lands Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope 8 30 Intel Xeon Processor 3500 Series Datasheet Volume 1 Package Mechanical Specifications n tel 3 Figure 3 1 3 1 Package Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array package that interfaces with the motherboard via an LGA1366 socket The package consists of a processor mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 for complete details on the LGA1366 socket The package components shown in Figure 3 1 include the following ntegrated Heat Spreader IHS Thermal Interface Material TI M Processor core die Package substrate Capacitors Processor Package Assembly Sketch TIM IHs i Capacitors i eee LGA1366 Socket System Boar Note 1 Socket and motherboard are included for reference and are n
106. ies Datasheet Volume 1 3 intel F atures DULUTH 93 7 1 Power On Configuration kk kk kk kk nennen kk kk kk kk kk kk 93 7 2 Clock Control and Low Power StateS Mk hKk K WM kllklk kk kk kk kk kak k ya ka 93 7 2 1 Thread and Core Power State Descriptions 94 7 2 2 Package Power State mene 95 TP BN DD LIEU 96 7 4 ACPI P States Intel Turbo Boost Technology urne yin e a mer aor err 96 7 5 Enhanced Intel SpeedStep Technology es eee 97 Boxed Processor Specifications sess emen 99 SL BhotrodHctiofis cisci asine nda a Pens oes acras atado aan euge io ia a do detras mm 99 8 2 Mechanical Specifications scii re coa teer angina aa We ana ER XR RR E EAR S b na 100 8 2 1 Boxed Processor Cooling Solution 100 8 2 2 Boxed Processor Fan Heatsink Weight 102 8 2 3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly 102 8 3 Electrical Requirements nine ERRARE Fe UNE ibn 102 8 3 1 Fan Heatsink Power eee enna emer 102 8 4 Thermal SPeciiCationsS ei ke Ro Ex h n n na waned Warna ines 103 8 4 1 Boxed Processor Cooling
107. ink and processor interface 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement Package Handling Guidelines Table 3 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 70 Ibs Tensile 25 Ibs Torque 35 in bs Package Insertion Specifications The processor can be inserted into and removed from an LGA1366 socket 15 times The Socket should meet the LGA1366 requirements detailed in the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 Intel Xeon Processor 3500 Series Datasheet Volume 1 m e Package Mechanical Specifications n te D 3 6 3 7 Table 3 3 3 8 Figure 3 4 Processor Mass Specification The typical mass of the processor is 35g This mass weight includes all the components that are included in the package Processor Materials Table 3 3 lists some of the package components and associated materials Processor Materials Component Material Integrated
108. io multiplier by 1 ratio and restart the clocks All processor activity stops during this frequency transition which occurs within 2 us Once the clocks have been restarted at the new lower frequency processor activity resumes while the voltage requested by the VID lines is stepped down to the minimum possible for the particular frequency Running the processor at the lower frequency and voltage will reduce power consumption and should allow the processor to cool off If after 1ms the processor is still too hot the temperature has not dropped below the TCC activation point DTS still 0 and PROCHOT is still active then a second frequency and voltage transition will take place This sequence of temperature checking and Frequency VI D reduction will continue until either the minimum frequency has been reached or the processor temperature has dropped below the TCC activation point If the processor temperature remains above the TCC activation point even after the minimum frequency has been reached then clock modulation described below at that minimum frequency will be initiated There is no end user software or hardware mechanism to initiate this automated TCC activation behavior A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near the TCC activation temperature Once the temperature has dropped below the trip temperature and the hysteresis timer has expired
109. ion or on the system board itself Figure 8 6 shows the location of the fan power connector relative to the processor socket The baseboard power header should be positioned within 110 mm 4 33 inches from the center of the processor socket Boxed Processor Fan Heatsink Power Cable Connector Description Pin Signal Straight square pin 4 pin terminal housing with 1 polarizing ribs and friction locking ramp e 0 100 pitch 0 025 square pin width 4 CONTROL Match with straight pin friction lock header on mainboard l 1234 Intel Xeon Processor 3500 Series Datasheet Volume 1 Boxed Processor Specifications n tel Table 8 1 Figure 8 6 8 4 8 4 1 Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes 12 V 12 volt fan power supply 10 8 12 13 2 V IC Peak steady state fan current draw 3 0 A Average steady state fan current draw 2 0 A SENSE SENSE frequency 2 pulses per fan 1 revolution CONTROL 21 25 28 kHz 2 3 1 Baseboard should pull this pin up to 5V with a resistor 2 Open drain type pulse width modulated 3 Fan will have pull up resistor for this signal to maximum of 5 25 V Baseboard Power Header Placement Relative to Processor Socket R110 4 33 Thermal Specifications This sec
110. istered trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2009 Intel Corporation 2 Intel Xeon Processor 3500 Series Datasheet Volume 1 Contents 1 9 1 4 Terminology sucer teen tena E n tind e ta irae ER ER MERE 10 1 2 Eee ia ase ssa Gide na dne d a E Oa wa RR e na ada n KC han 11 2 Electrical 5 aka kk 13 2 1 Intel Differential Signaling L hkhll klll lllkl kk kk memes 13 2 2 Power and Ground 13 2 3 Decoupling G ldelln6es reb osea saa ad ee W a na n 13 2 3 1 VITA VTTD VDDQ 14 2 4 Processor Clocking BCLK DP BCLK_DN kaka kaka kk kk ke 14 2 4 1 PLL Power Supply entere hin e n ke nie hin n Ge n k b Rada URN n 14 2 5 Voltage Identification VID kk kk kk kk menm 14 2 6 Reserved or Unused 5190 5 17 2 7 SIONAL ar a 18 2 8 Test Access Port enne 19 2 9 Platform Environmental Control Interface DC
111. le ended Asynchronous GTL Bi PROCHOT directional Single ended Asynchronous GTL Output THERMTRIP Single ended CMOS Input Output VID 7 6 VID 5 3 CSCI 2 0 VID 2 0 MSID 2 0 VIT VID 4 2 Xeon Processor 3500 Series Datasheet Volume 1 Electrical Specifications n tel Table 2 3 Table 2 4 2 8 Signal Groups Sheet 2 of 2 Signal Group Type Signals Single ended CMOS Output VIT VID 4 2 Single ended Analog Input ISENSE Reset Signal Single ended Reset Input RESET PWRGOOD Signals Single ended Asynchronous Input VCCPWRGOOD VTTPWRGOOD VDDPWRGOOD Power Other Power VCC VTTA VTTD VCCPLL VDDQ Asynchronous CMOS Output PSI Sense Points VCC_SENSE VSS_SENSE Other SKTOCC DBR Notes Notes 1 Refer to Chapter 5 for signal descriptions 2 DDR 0 1 2 refers to DDR3 Channel 0 DDR3 Channel 1 and DDR3 Channel 2 Signals with ODT DRX DP 19 0 DN 19 0 QPI_DTX_DP 19 0 DTX DN 19 0 QPI_CLKRX_D N P QPI_CLKTX_D N P DDR 0 1 2 _DQ 63 0 DDR 0 1 2 _DQS_ N P 7 0 DDR 0 1 2 _ECC 7 0 DDR 0 1 2 PAR ERRZ 0 2 VDDPWRGOOD BCLK ITP D N P PECI BPM 7 0 PREQ TRST VCCPWRGOOD VITPWRGOOD Notes 1 Unless otherwise specified signals have ODT in the package with 50 Q pulldown to Vss 2 PREQ BPM 7 0 TDI TMS and BCLK ITP D N P have ODT in package with 35 Q pullup to Vr 3 VCCPWRG
112. ltage via the VID signals This combination of lower frequency and VID results in a reduction of the processor power consumption The second method clock modulation known as Intel Thermal Monitor 1 TM1 in previous generation processors reduces power consumption by modulating starting and stopping the internal processor core clocks The processor intelligently selects the appropriate TCC method to use ona dynamic basis BIOS is not required to select a specific method as with previous generation processors supporting TM1 or TM2 The temperature at which Adaptive Thermal Monitor activates the Thermal Control Circuit is factory calibrated and is not user configurable Snooping and interrupt processing are performed in the normal manner while the TCC is active When the TCC activation temperature is reached the processor will initiate TM2 in attempt to reduce its temperature If TM2 is unable to reduce the processor temperature then TM1 will be also be activated TM1 and TM2 will work together clocks will be modulated at the lowest frequency ratio to reduce power dissipation and temperature With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable An under designed th
113. ltage Identification VID Definition VTT VR VID Input _ VID7 VID6 VIDS VIDA VID3 VID2 VID1 VIDO 0 1 0 0 0 0 1 0 1 220 V 0 1 0 0 0 1 1 0 1 195 V 0 1 0 0 1 0 1 0 1 170 V 0 1 0 0 1 1 1 0 1 145 V 0 1 0 1 0 0 1 0 1 120 V 0 1 0 1 0 1 1 0 1 095 V 0 1 0 1 1 0 1 0 1 070 V 0 1 0 1 1 1 1 0 1 045 V Notes 1 This is a typical voltage see Table 2 10 for VIT_Max and VTT_Min voltage Table 2 10 Vrr Static and Transient Tolerance Sheet 1 of 2 Intel Xeon Processor 3500 Series Datasheet Volume 1 120 130 140 A Vrr_ V Typ V Vrr Min V Notes 0 VID 0 0315 VID 0 0000 VID 0 0315 1 VID 0 0255 VID 0 0060 VID 0 0375 2 VID 0 0195 VID 0 0120 VID 0 0435 3 VID 0 0135 VID 0 0180 VID 0 0495 4 VID 0 0075 VID 0 0240 VID 0 0555 5 VID 0 0015 VID 0 0300 VID 0 0615 25 n tel Electrical Specifications Table 2 10 V7 Static and Transient Tolerance Sheet 2 of 2 A Vrr_ V Typ V Vrr_ Min V Notes 6 VID 0 0045 VID 0 0360 VID 0 0675 7 VID 0 0105 VID 0 0420 VID 0 0735 8 VID 0 0165 VID 0 0480 VID 0 0795 9 VID 0 0225 VID 0 0540 VID 0 0855 10 VID 0 0285 VID 0 0600 VID 0 0915 11 VID 0 0345 VID 0 0660 VID 0
114. n ODT resistors There are some signals that do not have ODT and need to be terminated on the board The signals that have ODT are listed in Table 2 4 Signal Groups Sheet 1 of 2 Signal Group Type Signals System Reference Clock Differential Clock Input BCLK_DP BCLK_DN Intel QPI Signal Groups Differential Intel QPI Input QPI_DRX_DIN P 19 0 QPI_CLKRX_DP QPI_CLKRX_DN Differential Intel QPI Output QPI DTX D N P 19 0 QPI_CLKTX_DP QPI CLKTX DN DDR3 Reference Clocks Differential DDR3 Output DDR 0 1 2 _CLK D P 3 0 DDR3 Command Signals Single ended CMOS Output DDR 0 1 2 _ RAS DDR 0 1 2 _CAS DDR 0 1 2 _WE DDR 0 1 2 MA 15 0 DDR 0 1 2 _BA 2 0 Single ended Asynchronous Output DDR 0 1 2 _RESET DDR3 Control Signals Single ended CMOS Output DDR 0 1 2 _CS 5 4 DDR 0 1 2 _CS 1 0 DDR 0 1 2 _ODT 3 0 DDR 0 1 2 _CKE 3 0 DDR3 Data Signals Inte Single ended CMOS Bi directional DDR 0 1 2 _DQ 63 0 DDR 0 1 2 _ECC 7 0 Differential CMOS Bi directional DDR 0 1 2 _DQS_ N P 7 0 TAP Single ended TAP Input TCK TDI TMS TRST Single ended GTL Output TDO Control Sideband Single ended Asynchronous GTL Output PRDY Single ended Asynchronous GTL Input PREQ Single ended GTL Bi directional CAT_ERR BPM 7 0 Single Ended Asynchronous Bi directional PECI Single Ended Analog Input COMPO QPI_CMP 0 DDR_COMP 2 0 Sing
115. n the baseboard to handle large current swings The power delivery solution must insure the voltage and current specifications are met as defined in Table 2 7 Processor Clocking BCLK_DP BCLK_DN The processor core Intel QPI and integrated memory controller frequencies are generated from BCLK_DP and BCLK_DN Unlike previous processors based on front side bus architecture there is no direct link between core frequency and Intel QPI link frequency such as no core frequency to Intel QPI multiplier The processor maximum core frequency Intel QPI link frequency and integrated memory controller frequency are set during manufacturing It is possible to override the processor core frequency setting using software This permits operation at lower core frequencies than the factory set maximum core frequency The processor s maximum non turbo core frequency is configured during power on reset by using values stored internally during manufacturing The stored value sets the highest core multiplier at which the particular processor can operate If lower max non turbo speeds are desired the appropriate ratio can be configured via the CLOCK_FLEX_MAX MSR The processor uses differential clocks BCLK_DP BCLK_DN Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK_DP BCLK_DN input with exceptions for spread spectrum clocking The processor core frequency is determined
116. nd Name n polis Direction BCLK DN AH35 CMOS DDRO_CS 5 A7 CMOS O BCLK_DP AJ35 CMOS DDRO_DQ 0 W41 CMOS 1 0 BCLK ITP DN AAA CMOS DDRO_DQ 1 v41 CMOS 1 0 BCLK_ITP_DP AA5 CMOS 0 DDRO_DQ 10 K42 CMOS 1 0 BPM 0 B3 GTL 1 0 DDRO_DQ 11 K43 CMOS 1 0 BPM 1 A5 GTL 1 0 DDRO_DQ 12 P42 CMOS 1 0 BPM 2 C2 GTL 1 0 DDRO DQ 13 P41 CMOS 1 0 Tspm i3 B4 GL io DDRO_DQI14 L43 CMOS 1 0 BPM 4 D1 GTL 1 0 DDRO DQ 15 L42 CMOS 1 0 BPM 5 C3 GTL 1 0 DDRO DQ 16 H41 CMOS 1 0 6 D2 io DDRO_DQI17 H43 CMOS 1 0 BPM 7 E2 GTL 1 0 DDRO DQ 18 E42 CMOS 1 0 CAT_ERR AC37 GTL 1 0 DDRO_DQ 19 E43 CMOS 1 0 COMPO AB41 Analog DDRO_DQ 2 R43 CMOS 1 0 DBR AF10 Asynch DDRO_DQ 20 J42 CMOS 1 0 DDR COMP O0 Analog DDRO_DQ 21 J41 CMOS 1 0 DDR COMP 1 Y7 Analog DDRO DQI 22 F43 CMOS 1 0 DDR_COMP 2 AC1 Analog DDRO_DQ 23 F42 CMOS 1 0 DDR_VREF L23 Analog DDRO DQ 24 D40 CMOS 1 0 DDRO BA 0 B16 CMOS DDRO_DQ 25 C41 CMOS 1 0 DDRO BA 1 A16 CMOS DDRO_DQ 26 A38 CMOS 1 0 DDRO_BA 2 C28 CMOS DDRO_DQ 27 D37 CMOS 1 0 DDRO_CAS C12 CMOS DDRO DQI28 D41 CMOS 1 0 DDRO_CKE 0 C29 CMOS DDRO_DQ 29 D42 CMOS 1 0 DDRO_CKE 1 A30 CMOS DDRO DQI 3 R42 CMOS 1 0 DDRO_CKE 2 B30 CMOS DDRO_DQ 30 C38 CMOS 1 0 DDRO_CKE 3 B31 CMOS DDRO DQI 31 B38 CMOS 1 0 DDRO_CLK_N 0 K19 CLOCK O DDRO_DQ 32 B5 CMOS 1 0 DDRO CLK N 1 C19 CLOCK DDRO_DQ 33 C4 CMOS 1 O DDRO CLK N 2 E18 CLOCK DDRO_DQ 34 Fl CMOS 1 0 DDRO CLK N 3 E19 CLO
117. nds with SO via reset CmpD S3 message S4 S5 Processor responds with CmpD S4 S5 message SO via reset Notes 1 Ifthe chipset requests an S state transition which is not allowed a machine check error will be generated by the processor ACPI P States Intel Turbo Boost Technology The processor supports ACPI P States A new feature is that the PO ACPI state will be a request for Intel Turbo Boost Technology This technology opportunistically and automatically allows the processor to run faster than its marked frequency if the processor is operating below power thermal and current specifications Maximum turbo frequency is dependant on the processor component and number of active cores No special hardware support is necessary for Intel Turbo Boost Technology BIOS and the operating system can enable or disable Intel Turbo Boost Technology Intel Xeon Processor 3500 Series Datasheet Volume 1 Features intel 7 5 Enhanced Intel SpeedStep Technology The processor features Enhanced Intel SpeedStep Technology Following are the key features of Enhanced Intel SpeedStep Technology Intel Xeon Processor 3500 Series Datasheet Volume 1 Multiple voltage and frequency operating points provide optimal performance at the lowest power Voltage and frequency selection is software controlled by writing to processor MSRs If the target frequency is higher than the current frequency Vcc is ramped up in steps by placing n
118. ng operation where the DTS value is greater than Tcontro_ the fan speed control algorithm must drive the fan speed to meet or exceed the target thermal solution performance cA shown in Table 6 3 The ability to monitor the inlet temperature TAMBIENT is required to fully implement the specification as the target Yc is explicitly defined for various ambient temperature conditions See the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 for details on characterizing the fan speed to ca and ambient temperature measurement Table 6 3 Thermal Solution Performance above TcoNTROL TAMBI ENT Yca at DTS TcoNTROL Yca at DTS 13 43 2 0 190 0 190 42 0 0 206 0 199 41 0 0 219 0 207 40 0 0 232 0 215 39 0 0 245 0 222 38 0 0 258 0 230 37 0 0 271 0 238 36 0 0 284 0 245 35 0 0 297 0 253 34 0 0 310 0 261 33 0 0 323 0 268 32 0 0 336 0 276 31 0 0 349 0 284 30 0 0 362 0 292 29 0 0 375 0 299 28 0 0 388 0 307 27 0 0 401 0 315 26 0 0 414 0 322 25 0 0 427 0 330 24 0 0 440 0 338 23 0 0 453 0 345 22 0 0 466 0 353 21 0 0 479 0 361 20 0 0 492 0 368 19 0 0 505 0 376 18 0 0 519 0 384 Notes 1 The ambient temperature is measured at the inlet to the processor thermal solution 2 This column can be expressed as a function of Tawpient by the following equation Yea 0 19 43 2 TAMBIENT 0 013 3 This column can be expressed as
119. nitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 7 0 should be connected in a wired OR topology between all packages on a platform The end points for the wired OR connections must be terminated CAT_ERR 1 0 Indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable machine check errors and other internal unrecoverable error Since this is an 1 0 pin external agents are allowed to assert this pin which will cause the processor to take a machine check exception COMPO Impedance compensation must be terminated on the system board using precision resistor QPI_CLKRX_DN Intel received clock is the input clock that corresponds to the received data QPI_CLKRX_DP QPI_CLKTX_DN O Intel QPI forwarded clock sent with the outbound data QPI_CLKTX_DP O QPI_CMP 0 1 Must be terminated the system board using a precision resistor QPI_DRX_DN 19 0 l QPI_DRX_DN 19 0 and QPI_DRX_DP 19 0 comprise the differential receive DRX DP 19 0 data for the QPI port The inbound 20 lanes are connected to another component s outbound direction QPI_DTX_DN 19 0 O QPI_DTX_DN 19 0 and QPIQPI_DTX_DP 19 0 comprise the differential DTX DP 19 0 O transmit data for the QPI port The outbound 20 lanes are connected to another component
120. ns Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 3 2 and Figure 3 3 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical maximum load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solution Processor Loading Specifications Parameter Maximum Notes Static Compressive Load 934 N 210 Ibf 1 2 3 Dynamic Compressive Load 1834 N 410 Ibf max static 1 3 4 compressive dynamic load Notes 1 These specifications apply to uniform compressive loading in a direction normal to the processor IHS 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heats
121. oss different processor families See http www intel com products processor_number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details Hyper Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see http www intel com products ht hyperthreading_more htm Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Intel Virtualization Technology requires a computer sys
122. ot part of processor package Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 3 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include Package reference with tolerances total height length width and so forth e IHS parallelism and tilt Land dimensions Top side and back side component keep out dimensions Reference datums All drawing dimensions are in mm Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 Intel Xeon Processor 3500 Series Datasheet Volume 1 31 Package Mechanical Specifications intel Sheet 1 of 2 Processor Package Drawi 2 3 Figure WON OA ON lt AN _NASSSNSSSSSSSSSSS Intel Xeon Processor 3500 Series Datasheet Volume 1 32 intel Package Mechanical Specifications Processor Package Drawing Sheet 2 of 2 Figure 3 3 X 1 33 Intel Xeon Processor 3500 Series Datasheet Volume 1 3 3 Table 3 1 3 4 Table 3 2 3 5 34 Package Mechanical Specificatio
123. otherwise noted all specifications in this table apply to all processor frequencies 2 Vma referred to in these specifications refers to instantaneous 3 For Vin between 0 V and Vrra Measured when the driver is tristated 4 Voy may experience excursions above Vr 5 COMP resistance must be provided on the system board with 1 resistors See the applicable platform design guide for implementation details COMPO resistors are to Vss 2 11 2 Vcc Overshoot Specification The processor can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC SENSE and VSS SENSE lands Table 2 16 Vcc Overshoot Specifications Symbol Parameter Min Max Units Figure Notes Vos MAX Magnitude of Vccp overshoot above VID 50 mV 2 5 Tos MAX Time duration of Vccp overshoot above VID 25 us 2 5 Intel Xeon Processor 3500 Series Datasheet Volume 1 29 n tel Electrical Specifications Figure 2 5 Vcc Overshoot Example Waveform Example Overshoot Waveform Voltage V Time Tos Overshoot time above VID Vos Overshoot above VID 2 11 3 Die Voltage Validation Core voltage Vcc overs
124. peed Control with Digital Thermal Sensor Fan speed control solutions use a value stored in the static variable The DTS temperature data which is delivered over PECI in response to a GetTemp0 command is compared to this Tcontrot reference The DTS temperature is reported as a relative value versus an absolute value The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT Therefore as the temperature approaches TCC activation the value approaches zero degrees Processor Thermal Data Sample Rate and Filtering The processor digital thermal sensor DTS provides an improved capability to monitor device hot spots which inherently leads to more varying temperature readings over short time intervals To reduce the sample rate requirements on PECI and improve thermal data stability vs time the processor DTS implements an averaging algorithm that filters the incoming data This filter is expressed mathematically as PECI t t 1 1 2 X Temp PECI t 1 Where PECI t is the new averaged temperature PECI t 1 is the previous averaged temperature Temp is the raw temperature data from the DTS X is the Thermal Averaging Constant TAC Only values read via the PECI interface are averaged Temperature values read via the IA32 THERM STATUS MSR are not averaged The Thermal Averaging Constant is a
125. r microarchitecture This document provides DC electrical specifications differential signaling specifications pinout and signal definitions package mechanical specifications and thermal requirements and additional features pertinent to the implementation and operation of the processor For information on register descriptions refer to the Intel Xeon Processor 3500 Series Datasheet Volume 2 The processor is a multi core processor built on the 45 nm process technology that uses up to 130 W thermal design power TDP The processor features an Intel QPI point to point link capable of up to 6 4 GT s 8 MB Level 3 cache and an integrated memory controller The processor supports all the existing Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Streaming SIMD Extensions 4 SSE4 The processor supports several Advanced Technologies Intel 64 Technology Intel 64 Enhanced Intel SpeedStep Technology Intel Virtualization Technology Intel VT Intel Turbo Boost Technology and Intel Hyper Threading Technology intel 1 1 10 Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to low level For example when RESET is low a reset has been requested Conversely when VTTPWRGOOD is high the Vz power rail is stable N and _P after a signal name refers to a differential pair Commonly use
126. r 3500 Series Datasheet Volume 1 83 n tel Thermal Specifications 6 2 6 2 1 Note 6 2 2 84 Processor Thermal Features Processor Temperature A new feature in the Intel Xeon Processor 3500 Series is a software readable field in the 1A32_TEMPERATURE_TARGET register that contains the minimum temperature at which the TCC will be activated and PROCHOT will be asserted The TCC activation temperature is calibrated on a part by part basis and normal factory variation may result in the actual TCC activation temperature being higher than the value listed in the register TCC activation temperatures may change based on processor stepping frequency or manufacturing efficiencies There is no specified correlation between DTS temperatures and processor case temperatures therefore it is not possible to use this feature to ensure the processor case temperature meets the Thermal Profile specifications Adaptive Thermal Monitor The Adaptive Thermal Monitor feature provides an enhanced method for controlling the processor temperature when the processor silicon exceeds the Thermal Control Circuit TCC activation temperature Adaptive Thermal Monitor uses TCC activation to reduce processor power via a combination of methods The first method Frequency VID control similar to Thermal Monitor 2 TM2 in previous generation processors involves the processor reducing its operating frequency via the core ratio multiplier and input vo
127. ration of the variable speed fan for the boxed processor Refer to Table 8 1 for the specific requirements Boxed Processor Fan Heatsink Set Points Higher Set Point Highest Noise Level 3 Lower Set Point i Lowest Noise Level X TT 7 Internal Chassis Temperature Degrees Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point Boxed Processor Fan Speed Notes X lt 30 When the internal chassis temperature is below or equal to this set point the fan operates at its lowest speed Recommended maximum internal chassis temperature for nominal operating environment Z gt 40 When the internal chassis temperature is above or equal to this set point the fan operates at its highest speed Recommended maximum internal chassis temperature for worst case operating environment 1 Set point variance is approximately 1 C from fan heatsink to fan heatsink Intel Xeon Processor 3500 Series Datasheet Volume 1 105 106 n tel Boxed Processor Specifications If the boxed processor fan heatsink 4 pin connector is connected to a 4 pin motherboard header and the motherboard is designed with a fan speed controller with PWM output CONTROL see Table 8 1 and remote thermal diode measurement capability the boxed processor will operate as follows As processor power has increased the required thermal solutions have generated increasingly more
128. re processor compatibility or for keying 2 6 Reserved or Unused Signals All Reserved RSVD signals must remain unconnected Connection of these signals to Vcc Vita Vro Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a land listing of the processor and the location of all Reserved signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level except for unused integrated memory controller inputs outputs and bi directional pins which may be left floating Unused active high inputs should be connected through a resistor to ground Vss Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Intel Xeon Processor 3500 Series Datasheet Volume 1 17 Table 2 3 18 Signal Groups Electrical Specifications Signals are grouped by buffer type and similar characteristics as listed in Table 2 3 The buffer type indicates which signaling technology and specifications apply to the signals All the differential signals and selected DDR3 and Control Sideband signals have On Die Terminatio
129. s Symbol Parameter Min Typ Max Units Notes Input Low Voltage for VCCPWRGOOD Vit land VITPWRGOOD Signals 0 25 Li 2 5 Vi Input Low Voltage for VODDPWRGOOD 0 29 V 6 Signal Input High Voltage for VCCPWRGOOD and VITPWRGOOD Signals 0 75 Vira ii 2 5 V Input High Voltage for VDDPWRGOOD 0 87 V 5 IH i 2 Signal Ron Buffer on Resistance 10 _ 18 Q lu Input Leakage Current x 200 uA 4 Notes 28 eur Bw mp Unless otherwise noted all specifications in this table apply to all processor frequencies The Va referred to in these specifications refers to instantaneous Vr aq For Vin between 0 V Vrra Measured when the driver is tristated Vin and may experience excursions above This spec applies to VCCPWRGOOD and VTTPWRGOOD This specification applies to VDDPWRGOOD Intel Xeon Processor 3500 Series Datasheet Volume 1 Electrical Specifications Table 2 15 Control Sideband Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes ViL Input Low Voltage _ 0 64 Vita V 2 Vin Input High Voltage 0 76 Vita V 2 VoL Output Low Voltage Vita Ron Ron V 2 4 sys term Vou Output High Voltage xx V 2 4 Ron Buffer on Resistance 10 18 Buffer on Resistance for Q Ron VID 7 0 100 lu Input Leakage Current x 200 uA 3 COMPO COMP Resistance 49 4 49 9 50 40 Q 5 Notes 1 Unless
130. s inbound direction DBR DBR is used only systems where debug port is implemented the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DDR COMP 2 0 Must be terminated on the system board using precision resistors DDR_VREF Voltage reference for DDR3 DDR 0 1 2 _BA 2 0 Defines the bank which is the destination for the current Activate Read Write 1 or Precharge command DDR 0 1 2 _CAS O Column Address Strobe DDR 0 1 2 _CKE 3 0 Clock Enable DDR 0 1 2 _CLK_N 2 0 O Differential clocks to the DIMM All command and control signals are valid on the DDR 0 1 2 _CLK_P 2 0 rising edge of clock DDR 0 1 2 _CS 1 0 O Each signal selects one rank as the target of the command and address DDR 0 1 2 _CS 5 4 DDR 0 1 2 _DQ 63 0 1 0 DDR3 Data bits DDR 0 1 2 _DQS_N 7 0 1 0 Differential pair Data Strobe x8 Differential strobes latch data for each DRAM DDR 0 1 2 DQS P 7 0 Different numbers of strobes are used depending on whether the connected DRAMs x4 x8 Driven with edges center of data receive edges are aligned with data edges Intel Xeon Processor 3500 Series Datasheet Volume 1 75 intel Table 5 1 Signal Definitions Signal Definitions Sheet 2 of 4 Name DDR 0 1 2 _DQS_N 8 DDR 0 1 2 _DQS_P
131. t least one of its cores is in the CO or C1 state or when another component in the system has not granted permission to the processor to go into a low power state Individual components of the processor may be in low power states while the package in CO Package C1 C1E State The package will enter the C1 C1E low power state when at least one core is in the C1 CIE state and the rest of the cores in the C1 C1E or lower power state The processor will also enter the C1 C1E state when all cores are in a power state lower than C1 C1E but the package low power state is limited to C1 C1E using the PMG_CST_CONFIG_CONTROL MSR In the CIE state the processor will automatically transition to the lowest power operating point lowest supported voltage and associated frequency When entering the C1E state the processor will first switch to the lowest bus ratio and then transition to the lower VID No notification to the system occurs upon entry to C1 CIE Package C3 State The package will enter the C3 low power state when all cores are in the C3 or lower power state and the processor has been granted permission by the other component s in the system to enter the C3 state The package will also enter the C3 state when all cores are in an idle state lower than C3 but other component s in the system have only granted permission to enter C3 Intel Xeon Processor 3500 Series Datasheet Volume 1 95 intel 7 2 2 4 7 3 Table 7 3 7 4
132. tem with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain computer system software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability Intel Turbo Boost Technology performance varies depending on hardware software and overall system configuration Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology For more information see www intel com Enhanced Intel SpeedStep Technology See the http processorfinder intel com or contact your Intel representative for more information Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel Pentium Intel Xeon Intel Atom Enhanced Intel SpeedStep Technology Intel Turbo Boost Technology Intel Hyper Threading Technology Intel Virtualization Technology Intel Advanced Digital Media Boost and the Intel logo are trademarks or reg
133. tform Environmental Control I nterface DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices The processor contains a Digital Thermal Sensor DTS that reports a relative die temperature as an offset from Thermal Control Circuit TCC activation temperature Temperature sensors located throughout the die are implemented as analog to digital converters calibrated at the factory PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control More detailed information may be found in the Platform Environment Control Interface PECI Specification DC Characteristics The interface operates at a nominal voltage set by Vrp The set of DC electrical specifications shown in Table 2 5 is used with devices normally operating from a Vrrp interface supply Vrrp nominal levels will vary between processor families All devices will operate at the Vrp level determined by the processor installed in the system For specific nominal Vrp levels refer to Table 2 7 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 150 ViTD V Vnysteresis Hysteresis 0 1 Vip N A V Vn Negative edge threshold voltage 0 275 Vip 0 500 Vip V
134. the Boxed 99 8 2 Space Requirements for the Boxed Processor side view 100 8 3 Space Requirements for the Boxed Processor top view 101 8 4 Space Requirements for the Boxed Processor overall view 101 8 5 Boxed Processor Fan Heatsink Power Cable Connector Description 102 8 6 Baseboard Power Header Placement Relative to Processor 103 8 7 Boxed Processor Fan Heatsink Airspace Keepout Requirements top view 104 8 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements side view 104 8 9 Boxed Processor Fan Heatsink Set lt kk kk ee eee ene kak ka 105 Intel Xeon Processor 3500 Series Datasheet Volume 1 Tables 1 1 Referencesi yk ke be da a cine H b kend NR UI RIEN D ci Wake MEM T nd ead ae 11 2 1 Voltage Identification 15 2 2 Market Segment Selection Truth Table for MS 10 2 0 17 2 3 Signal Ayan nan k Tir dada rha ny RApEN IER an olka bab ayn ha behya E 18 2 4 Signals With O Dis Hada a n w R ed hi MI ID M nea AWAT 19 2 5 PECI DG Electrical LMS sa sis sin s Xi
135. tion describes the cooling requirements of the fan heatsink solution used by the boxed processor Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Chapter 6 of this document The boxed processor fan heatsink is able to keep the processor temperature within the specifications see Table 6 1 in chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 8 7 and Figure 8 8 illustrate an acceptable airspace clearance for the fan heatsink The air temperature entering the fan should be kept below 40 2C Again meeting the processor s temperature specification is the responsibility of the system integrator Intel Xeon Processor 3500 Series Datasheet Volume 1 103 m n tel Boxed Processor Specifications Figure 8 7 Boxed Processor Fan Heatsink Airspace
136. tions Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state Note that it is not valid for VITTPWRGOOD to be deasserted while VCCPWRGOOD is asserted Notes 1 DDR 0 1 2 refers to DDR3 Channel 0 DDR3 Channel 1 and DDR3 Channel 2 8 78 Intel Xeon Processor 3500 Series Datasheet Volume 1 Bi Thermal Specifications n tel 6 Thermal Specifications 6 1 Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within its operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader IHS This section provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 6 1 1 Thermal Speci
137. tself The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the loadline It should be noted that a low to high or high to low voltage state change will result in as many VID transitions as necessary to reach the target core voltage Transitions above the maximum specified VID are not permitted Table 2 8 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 8 The VR used must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 7 and Table 2 8 Table 2 1 Voltage Identification Definition Sheet 1 of 3 VID VI D VID VID VID vy VID VID VID VID VID VID VID VID y 7 6 5 4 3 2 1 0 CC MAX 7 6 5 4 3 2 1 0 CC MAX 0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 0 1 1 1 04375 0 0 0 0 0 0 0 1 OFF 0 1 0 1 1 1 0 0 1 03750 0 0 0 0 0 0 1 0 1 60000 0 1 0 1 1 1 0 1 1 03125 0 0 0 0 0 0 1 1 1 59375 0 1 0 1 1 1 1 0 1 02500 0 0 0 0 0 1 0 1 58750 0 1 0 1 1 1 1 1 1 01875 0 0 0 0 0 1 0 1 1 58125 0 1 1 0 0 0 0 0 1 01250 0 0 0 0 0 1 1 1 57500 0 1 1 0 0 0 0 1 1 00625 0 0 0 0 0 1 1 1 1 56875 0 1 1 0 0 0 1 0 1 00000 0 0 0 0 1 0 0 1 56250 0 1 1 0 0 0 1 1 0 99375 0 0 0 0
138. ume 1 Bi Electrical Specifications n tel 2 2 1 Figure 2 1 2 2 2 3 Electrical Specifications Intel QPI Differential Signaling The processor provides an Intel QPI port for high speed serial transfer between other Intel QPI enabled components The Intel port consists of two unidirectional links for transmit and receive Intel QPI uses a differential signalling scheme where pairs of opposite polarity D_P D_N signals are used On die termination ODT is provided on the processor silicon and termination is to Vss Intel chipsets also provide ODT thus eliminating the need to terminate the Intel QPI links on the system board Intel strongly recommends performing analog simulations of the Intel QPI interface Figure 2 1 illustrates the active ODT Signal listings are included in Table 2 3 and Table 2 4 See Chapter 5 for the pin signal definitions All Intel QPI signals are in the differential signal group Active ODT for a Differential Link Example Signal Ry Power and Ground Lands For clean on chip processor core power distribution the processor has 210 VCC pads and 119 VSS pads associated with Vcc 8 VITA pads and 5 VSS pads associated with V ra 28 VITD pads 17 VSS pads associated with Vrp 28 VDDQ pads and 17 VSS pads associated with Vppo and 3 VCCPLL pads All VTTD VDDQ and VCCPLL lands must be connected to their respective proc
139. z erre kon dawn a a dabana kn Rx xwand REN WED Dada 20 2 6 Processor Absolute Minimum and Maximum Ratings sse 22 2 7 Voltage and Current 5 ce kk kk kaka ka 23 2 8 Static and Transient Tolerance 0 cece entered 24 2 9 Voltage Identification VID menm emn 25 2 10 VIT Static and Transient kk kk ka kk ke 25 2 11 DDR3 Signal Group DC 5 mmm 27 2 12 RESET Signal DC 5 een enn 28 2 13 TAP Signal Group DC Specifications i sss memes 28 2 14 PWRGOOD Signal Group DC 28 2 15 Control Sideband Signal Group DC 29 2 16 VCC Overshoot Specifications ccc 29 3 1 Processor Loading Specifications 1 1 00 cece ee eee 34 3 2 Package Handling ene memes 34 353 PlrOce550f MateTial Ss ca ga naka paka bn Lao ee NE 35 4 1 Land Listing by Land meses E na A enin a d n 38 4 2 Listing by Land Num DOL aba a R3 ala lana a kk Ki

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