ADATA Extreme Edition DDR3 1600X 2GB-kit
Contents
1. 128 95 076 77 gt 2 CO 12 00 472 44 5 ol sar 140 eL Hole NES 22 489 98 00 2 von 4 00 1850 39 71 00 9 795 28 2 1 9C203 4x2 X 47 0061850 39 1 00 39 37 gt 2 2 lt 00 gt lt IAE 2 10682 68 4X S v NM zo P Note Y 1 Tolerance 0 15mm 5 91 mils ix sr ei t9 00 2 50 98 43 S e gt 0 50419 69 min 1 27 0 10 50 00 3 94 0 20 gt 0 89 0 05 m 5 00 196 85 0 05MMCMin 637 50 1 97 J 1 50 0 10 a 59 06 3 94 gt z VIEW C C Detail eo a Detail B OPTIONAL MI64G1A08 DDR3 1600X CL 7 1GB 128Mx8_ Pb free Rev 1 2008 10 13 Page 6 of 62. VREFCA V ODTO On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device MI64G1A08 DDR3 1600X CL 7 1GB 128Mx8_ Pb free 1 2008 10 13 3 016 Block Diagram e DATA _ 50 0050 0054 0050 0054 DMO DM4 cs 005 DOQS 000 0032 DO DQ1 DQ33 002 0034 DQ DQ3 DQ35 DQ U4 004 0036 DQ 005 0037 006 0038 DQ 007 0039 10 DQS1 Vss 00 5 Vss 0051 DQS5 DM1 DM5 NL CS 005 DOS 009 0041 DQ 0010 0042 DQ 0011 0043 DQ 0013 0045 DQ DQ14 0046 DQ 0015 0047 DQ 10 DQS2 Vss 00 6 Vss 0052 0056 DN DM6 DM CS 005 DOs 0016 0048 DQ 0017 0049 DQ DQ18 DQ50 DQ 0019 0051 DQ 0020 0052 po U6 0021 0053 DQ DQ22 0054 DQ 0923 0055 DQ Vss Vss 0053 DQS7 DQS3 0057 DM3 DM7 DQ24 0056 DQ DQ25 DQ57 DQ DQ26 DQ58 DQ DQ27 DQ59 DQ DQ28 DQ60 DQ 0029 0061 DQ DQ30 0062 0031 0063 DQ Vss Vss zQ 2 gt BA0 BA2 SDRAMs UO U7 EE SPD A0 A13 A0 A13 SDRAMs UO U7 UO U7 RAS RAS SDRAMs U7 M UO 07 CAS CAS SDRAMs U0 U7 Vss UO U7 SDRAMs 00 U7 U0 U7 WE WE SDRAMs U7 CKO ODTO ODT SDRAMs U0 U7 I ORS SDRAM CKO SDRAMs UO U7 CK1 2 CK L3 Serial PD SCL Note WP SDA 1 For each DRAM a unique ZQ resistor is connected to A
3. pas 196 286 voDSPD 5r pox 77 omnc sw 157 vss 197 2v sa 38 vss 78 nsf sco 158 198 No 238 soa 39 r9 sw 159 085 199 vss 239 vss 4 vss 120 vss 20 poe 20 vr MI64G1A08 DDR3 1600X CL 7 IGB 128Mx8 Pb free Rev 2008 10 13 Page 2 of 6 Kon Pin Description NAME FUNCTION System Clock CKO Active on the positive and negative edge to sample all inputs CKO Masks system clock to freeze operation from the next clock cycle CKE should be enabled at CKEO Clock Enable least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and 50 Chip Select L U DOM Row Column address are multiplexed on the same pins A0 A13 Address Row Address A0 A13 Column Address A0 A9 Auto precharge A10 AP Selects bank to be activated during row address latch time BAO BA2 Banks Select Selects bank for read write during column address latch time Data Data and check bit inputs outputs are multiplexed on the same pins Data Strobe When high termination resistance is enabled for all DQ DQ and DM pins assuming the 000 0063 DQSO DQS7 Bi directional Data Strobe DQS0 DQS7 DMO DM7 RAS ICAS VDD VSS VREFDQ
4. 0 1 A2 SA1 MI64G1A08 DDR3 1600X CL 7 IGB 128Mx8 Pb free SA2 Rev ground The ZQ resistor is 240 Ohm 1 2008 10 13 Page 4 of 6 Kon Absolute Maximum Ratings Voltage on VDD supply relative to Vss 0 4 1 975 Voltage on VDDQ pin relative to Vss VDDQ 0 4 1 975 Voltage on any pin relative to Vss VIN Vout 0 4 1 975 Storage temperature TStg 55 100 Note DDR3 SDRAM component specification Operation Temperature Condition amm we ew e Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 5V 0 075V Tc 0 to 85 exem v eee 7 7 vw wem Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together 3 The AC peak noise on VREF may not allow VREF to deviate from VREF DC by more than 1 VDD for reference approx 15 4 For reference approx VDD 2 15mV MI64G1A08 DDR3 1600X CL 7 IGB 128Mx8 Pb free Rev 2008 10 13 Page 5 of 6 Package Dimensions i UO U1 U2 U4 05 US U7 o G 1 48 f 49 120 J B L 240 169 f 168 121 133 35 52 50 00
5. 3 9us at 85 C lt TCASE s 95 C 8 bit pre fetch On Die Termination using ODT pin Internal self calibration Internal self calibration through ZQ pin RZQ 240 ohm 1 EEPROM VDDSPD 3 3V Typical PCB Height 30 00mm 1 181 Single sided component Clock Cycle Time tCK DDR3 1333 tCK 1 5ns DDR2 1600 tCK 1 25ns Refresh to Active Refresh Command Time tRFC 110ns Lead free products are RoHS compliant Pin Assignment nf Erom pem romi Pin mont Baek Pin Baek VREFDQ 0032 421 461 NC DM8 201 pox el me tate 8 4 wo as vss 103 pos 103 vss 203 om 4 oar a vss mos 124 vss 164 204 nc 5 vss 4 noose pasa 125 165 205 vss 6 maso 46 se vss 126 166 vss 206 Dos 7 poo ar vss j 107 vss 17 207 pass 8 vss 4s No pos 128 168 meser 208 3 9 no s wo a vss par 169 209 so ceo s 130 vss 10 20 Do vss s vo je 181 im ms an vss s sa 92 vss pam 12 a oms 1 55 o mass 193 vss 13 zo wo m vss 9 vo pos 1 134 a A2 aa ves 15 mos ss an 9 v
6. DATA Memory Module Data Sheet A Wonderful Memory MI64G1A08 DDR3 1600X CL7 240 Pin XMP U DIMM 1GB 128M x 64 bits General Description The ADATA s MI64G1A068 is a 128Mx64 bits 1GB 1024MB DDR3 1600 CL7 SDRAM XMP memory module The SPD is programmed to JEDEC standard latency 1333Mbps timing of 9 9 9 24 at 1 5V The module is composed of eight 128Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glass epoxy printed circuit board The MI64G1A068 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data transactions possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features Power supply Normal VDD amp VDDQ 1 5V x 0 075V e 1 5V SSTL 15 compatible I O XMP Extreme Memory Profile support Timing Reference DDR3 1333 CL9 9 9 24 at 1 5V DDR3 1600 CL 7 7 7 20 at 1 8V XMP Profile 1 Burst Length 4 8 Programmable Additive Latency 0 CL 2 or CL 1 clock Bi directional differential data strobe DQS and DQS Differential clock input CK CK operation e DLL aligns DQ and transition with CK transition Average Refresh Period 7 8us at lower then TCASE 85 C
7. ss 15 wc 5 ao 25 Das 16 Das se 18 vss 16 voo 216 pog 7 vs 57 vo o oos 187 far as air vss 18 ca ss as vss 138 pas 178 28 002 19 so A poe 19 vss 19 29 boo vss 10 Dom 10 as 20 vss z poe ot a m vss vay pon er zat om 22 bou 62 102 mase 2 vss 182 voo 22 wo 23 vss 1 pase 143 pm 183 voo 223 vss 2 002 ea ikinc 14 vss M4 cko 24 Dow 25 Dos 65 vno 105 pos 145 vss 185 25 005 vss 66 vob 106 bos 14 002 186 voo 268 vss 2 pos 67 107 vss 147 0028 187 227 Doo 28 e 108 pos 148 vss 188 228 Do vss e 109 pasz 49 008 189 voo ze vss 30 Dam atop vss 150 009 190 BA 29 DW 5 pos 7 bw m masr 151 vss 191 21 wo s vss 72 pos ts om 192 mas 232 vss 33 moss 73 ns vss 153 18 so 23 pase s Dass za icas Dos 15 vss 194 voo 254 Dae s vss 75 v 15 pos 155 pos 195 235 vss 36 76 sinc we vss 156
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