SMART Modular 512MB DDR2 SDRAM
Contents
1. Modular Technologies January 31 2006 Extended Mode Register Table BA2 BA1 BAO A15 A14 A13 A12 A11 A10 A9 AB A7 A6 AS AA A3 A2 A1 AO Address Field E18 E17 E16 Et5 E14 E13 E12 Et1 E10 Eo EB EZ EG ES E4 E3 E2 pn Eo Extended Mode Register 01 EMR oi 0 Qoi RDQS DQS OCD Program RTT Additive latency RTT D I C DLL E17 E16 MRS mode E6 E2 RTT Nominal o o MRS 0 D ODT Disabled E0 DLL Enable o 1 EMRS 1 0 1 75 ohm 0 Enable 1 0 EMRS 2 1 D 150 ohm 1 Disable 1 1 EMRS 3 Reserved 1 1 SOohm E9 E8 E7 OCD Calibration Program E5 E4 E3 Additive Latency 0 0 0 OCD calibration mode exit maintain setting 0 0 0 0 o o 1 J Drive 1 Din 1 o 1 o J Drive 0 0 1 0 2 0 1 1 3 ust mode See page Oo 1 1 Adjust mode See page 13 1 0 0 4 1 1 1 OCD calibration default See page 13 1 0 1 Reserved 1 1 0 Reserved Qoff Optional 4 See page 13 E1 Output Driver Driver 1 1 1 Reserved Impedence Control Size Output buffer enabled 0 Normal 100 Output buffer disabled 1 Weak 60 DQS Enable E11 E10 Strobe Function Matrix RDQS Enable DQS Enable Disable RDQ EU RDQS DM RDQS DQS DQS 0 Disable O Enable DM Hi z DQS DQS RDQS 0 Disable 1 Disable DM Hi z DQs Hi z 0 Disable 1 Enable2. Edge ODTO SSTL_18 Active High On Die Termination ODT when high enables termination resistance internal to the DDR2 SDRAM When enabled ODT is only applied to each of the following pins DQ DQS and DM The ODT input will be ignored if disabled in Extended Mode Register EMRS CKEO SSTL_18 Active High Activates the DDR2 SDRAM CLK signal when high and deactivates the CLK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode CSO SSTL_18 Active Low Enables the associated DDR2 SDRAM command decoder when low and disables decoder when high When decoder is disabled new commands are ignored but previous operations continue RAS CAS SSTL_18 Active Low When sampled at the positive rising edge of the clock CAS RAS and WE define the WE operations to be executed by the SDRAM BAO BA1 SSTL_18 Bank Address define to which bank an Activate Read Write or Precharge command is being applied Bank address also determines if the Mode Register or Extended Mode Reg ister is to be accessed during a MRS or EMRS cycle Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 4 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jay
3. O Enable RDQS RDQS DQS DQS 1 Enable See page 13 1 Enable 1 Disable RDQS Hi z DQS Hi z Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 14 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 gt SMART SM646UDR26485 2 Modular Technologies January 31 2006 Commands The following Truth Tables provide a general reference of available commands For a more detailed description please refer to the device data sheets Truth Table Commands CKE BAO Function y CS RAS CAS WE 9 An A11 A10 A9 AO Notes Previous Current BAn cycle cycle Extended Mode Register Set H H L L L L BA OP Code 1 2 Refresh H H L L L H X X X X 1 Self Refresh Entry H L L L L H X X X X 1 H X X X Self Refresh Exit L H X X X X 1 7 L H H H Single Bank Precharge H H L L H L BA X L X 1 2 Precharge All Banks H H L L H L X X H X 1 Bank Activate H H L L H H BA Row Address 1 2 Write H H L H L L BA Column L Column 1 2 3 Write with Auto Precharge H H L H L L BA Column H Column 1 2 3 Read H H L H L H BA Column L Column 1 2 3 Read
4. is not allowed Each byte lane has a corresponding DQS CK and CK input slew rate must be gt 1 V ns 2 2 V ns if measured differentially The data valid window is derived by achieving other specifications typ tcK 2 toasa and ou top tup tous The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived MIN to tcp refers to the smaller of the actual clock low time and the actual clock high time as provided to the device i e this value can be greater than the minimum specification limits for tc and tcp tHP MIN is the lesser of te minimum and tcp minimum actually applied to the device CK and CK inputs READs and WRITES with no auto precharge are allowed to be issued before tras MIN is satisfied since tras lockout feature is supported in DDR2 SDRAM ViL Vig DDR2 overshoot undershoot Refer to 256MB 512MB or 1GB DDR2 SDRAM component data sheet for more detailed informa tion tpAL NWR tgp tciQ For each ofthe terms above if not already an integer round to the next highest integer tc refers to the appli cation clock period nyyg refers to the tyyg parameter stored in the MR 11 10 9 This is a minimum requirement Minimum READ to internal PRECHARGE timing is AL BL 2 providing the tgrp and tras uN have been satisfied The DDR2 SDRAM will automatically delay the internal PRECHARGE command until tras min has been satisfied Operating frequency is
5. setting EMR A6 A2 1 0 Rrr effective impedence value for 50Q RTT3 EFF 40 50 60 Q 1 setting EMR A6 A2 1 1 Deviation of VM with respect to Vppo 2 AVM 6 6 2 Notes 1 RTT1 EFF and RrTo grr are determined by applying ViH ac and Vu ac to pin under test separately then measure current l Vip Ac and Vip aAc respectively R IH AC Ga TWEFF ac d JM Ac 2 Measured voltage VM at tested pin with no load AVM E M 4 x 100 DDQ Output DC Current Drive Parameter Symbol Min Max Unit Notes Output Minimum Source DC Current loH 13 4 mA 1 3 4 Output Minimum Sink DC Current IOL 13 4 mA 2 3 4 Notes 1 For lop DC Vppa 1 7V Vout 1420mV Vout Vppo log must be less than 212 for values of VouT between Vppo and Vopo 280mV 2 Forlo DC Vppo 1 7V Vout 280mV Vourt lo_ must be less than 210 for values of Vout between DV and 280mV 3 The DC value of Vggr applied to the receiving device is set to VTT 4 The values of log DC and lo DC are based on the conditions given in Notes 1 and 2 They are used to test device drive current capability to ensure Vu min plus a noise margin and Vu max minus a noise margin are delivered to an SSTL_18 receiver The actual current values are derived by shifting the desired driver operating point along a 21 load line to define a convenient driver current for measurement Corporate Headquarters P O Box 1757 Fremont CA 94538 USA T
6. Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART Modular Technologies SM646UDR26485 2 I January 31 2006 Block Diagram CSO CKEO ODTO DQS0 w DQSOR w DMO Ww DQO w DQ1 N DQ2 N DQ3 w DQ4 Ww DQ5 N DQ6 w DQ7 w DQS1 w Das1 w DM1 w DQ8 N DQ9 N DQ10 w DOIT w DQ12 W d DQ13 w d DQ1i4 w DQ15 w DQS2 wW d DQS2 w DM2 w DQ16 w DQ17 w DQ18 w DQ19 w DQ20 w DQ21 wW d DQ22 W d DQ23 W 4 DQS3 W d DQS3 w DM3 N DQ24 W d DQ25 DQ26 W d DQ27 W d DQ28 DQ29 wW d DQ30 w DQ31 wW d4 Sit CKE ODT DQS DQS DM l O 0 1 0 1 lo 2 1 0 3 V0 4 VO5 VO6 VO7 DO Si CKE ODT DQS DQS DM l O 0 1 0 1 lo 2 1 0 3 V0 4 1 05 l O 6 y o 7 D1 Si CKE ODT DQS DQS DM l O 0 1 0 1 VO2 1 0 3 1 0 4 lO 5 1 0 6 y o 7 D2 Si CKE ODT DQS DQS DM 1 0 0 1 0 1 VO2 1 0 3 1 0 4 1 05 l O 6 VO7 D3 DQS4 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
7. DIMM Pin List Contd Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name No Name No Name 21 DQ10 51 VDDQ 81 DQ33 111 DQ57 141 DQ15 171 CKE1 NC 201 Vss 231 Vss 22 DQ11 52 CKEO 82 Vss 112 Vss 142 Vss 172 Vpp 202 DM4 232 DM7 23 Vss 53 VDD 83 DQS4 113 DQS7 143 DQ20 173 A15 NC 203 NC 233 NC 24 DQ16 54 BA2 NC 84 DQS4 114 DQS7 144 DQ21 174 A14 NC 204 Vss 234 Vss 25 DQ17 55 NC 85 Vss 115 Vss 145 Vss 175 VDDQ 205 DQ38 235 DQ62 26 Vss 56 VDDQ 86 DQ34 116 DQ58 146 DM2 176 A12 206 DQ39 236 DQ63 27 DQS2 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 Vss 237 Vss 28 DQS2 58 A7 88 Vss 118 Vss 148 Vss 178 VDD 208 DQ44 238 VDDSPD 29 Vss 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SAO 30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 Vss 240 SA1 Pin Description Table Symbol Type Polarity Function CKO CK2 SSTL_18 Positive Positive line of the differential pair of system clock inputs All DDR2 SDRAM address and Edge control inputs are sampled on the rising edge of their associated clocks Output data is ref erenced at the crossings of the clocks CKO CK2 SSTL_18 Negative Negative line of the differential pair of system clock inputs
8. burst writes BL 4 CL 1120 mA CL IDD AL 0 tek tck DD tRas fRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD4R Operating burst read current All banks open Continuous burst reads lout OmA BL 1040 mA 4 CL CL IDD AL 0 tek kapp RAS tRASmax IDD tRP tRP DD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W IDD5B Burst refresh current tck tckqppy Refresh command at every tgec ppy interval CKE 1120 mA is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD6 Self refresh current CK and CK at OV CKE x 0 2V Other control and address bus inputs 40 mA are FLOATING Data bus inputs are FLOATING IDD7 Operating bank interleave read current All bank interleaving reads lour OmA BL 4 1180 mA CL CL IDD AL taep IDD 1 tcK IDD tck tcK IDD RC tRc IDD tRRD tRRD IDD tRcD 1 tcK IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are STABLE during DESELECTs Data pattern is same as IDD4R Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 4
9. only allowed to change during self refresh mode or precharge power down mode Anytime the operating frequency is changed not including jitter the DLL is required to be reset followed by 200 clock cycles ODT turn on time taon MIN is when the device leaves high impedence and ODT resistance begins to turn on ODT turn on time taon MAX is when the resistance is fully on Both are measured from taonp ODT turn off time taoF MIN is when the device starts to turn off ODT resistance ODT turn off time taoF max is when the bus is in high impedence Both are measured from taorfp This parameter has a two clock minimum requirement at any ck tpELay is calculated from tis tox tjpj so that CKE registration LOW is guaranteed prior to CK CK being removed in a system reset condition Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 24 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART SM646UDR26485 2 Modular Technologies January 31 2006 Disclaimer No part of this document may be copied or reproduced in any form or by any means or transferred to any third party without the prior written consent of an authorized representative o
10. precharge time tRAS 45ns 2Dh 31 Module row density 512MB 80h 32 Command and Address signal input setup time 0 20ns 20h 33 Command and Address signal input hold time 0 27ns 27h 34 Data signal input setup time 0 10ns 10h 35 Data signal input hold time 0 17ns 17h 36 Write recovery time tWR 15ns 3Ch 37 Internal write to read command delay tWTR 7 5ns 1Eh 38 Internal read to precharge delay tRTP 7 5ns 1Eh 39 Memory Analysis Probe Characteristics 00h 40 Extension of tRC and tRFC None 00h 41 Device Minimum activate auto refresh time tRC 60ns 3Ch 42 Device Minimum auto refresh to active auto refresh 105ns 69h time tRFC 43 Maximum device cycle time tCK max 8ns 80h 44 Device DQS DQ skew for DQS and associated DQ 0 24ns 18h signals tDQSQ max 45 Device read data hold skew factor tQHS 0 34ns 22h 46 PLL relock time 00h 47 TCASE MAX Delta AT4gA4w Delta 95 C 1 2 C 53h 48 Psit a DRAM 60 CAN 78h 49 ATo DTO 5 4 C 2x refresh 4Bh High Temp Self Refresh 50 ATon DT2N UDIMM or AT2Q DT2Q RDIMM 5 7 C 39h 51 ATop DT2P 0 57 C 26h 52 AT3n DT3N 5 7 C 26h Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 10 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang
11. to all SDRAMs DO D7 SCL SCL SDA 7SDA WP Clock Wiring TO DS EE CKO CKO 2 SDRAM s Decoupling Capacitors CK1 CK1 3 SDRAMs Vss CK2 CK2 3 SDRAMs 2pF 1pF Il Il IT IT 2002 2002 CKO gt DDR2 SDRAMs Chi gt DDR2 SDRAMs cko CK24 1pF Il IT 2002 CK1 gt DDR2 SDRAMs CK1 J Notes 1 Ax BAx RAS CAS WEZ resistors 5 10 5 Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 7 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 gt SMART SM646UDR26485 2 Modular Technologies January 31 2006 Physical Dimensions 240 pin DIMM Module 3N 3 x Z 133 35 0 15 30 00 19 80 17 80 1 27 0 10 Detail A Detail B Detail C Front View ee HH Tul ln 0 20 0 15 x 1 50 0 10 1 00 5 re Fi 1 0 80 0 05 2 50 ka 1 00 4x Detail A Det
12. 0 when setting the mode register 2 WR minis determinedby tcx max and WR max is determined by tcx min WR in clock cycles is calculated by dividing tWR in ns by tCK in ns and rounding up to the next integer The mode register must be programmed to this value Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 12 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 gt SMART SM646UDR26485 2 Modular Technologies January 31 2006 Extended Mode Register Table Definition The extended mode register controls functions beyond those controlled by the mode register these additional functions are DLL enable disable output drive strength ODT RTT Posted CAS additive latency AL off chip driver impedance calibration OCD DQS enable disable RDQS RDQS enable disable and OUTPUT enable disable The extended mode register is programmed via the LOAD MODE LM command and will retain the stored information until it is programmed again or the device loses power Reprogramming the extended mode register will not alter the contents of the memory array provided it is performed correctly The extended mode register must be loaded when all banks ar
13. 4 870 870 8747 Fax 44 870 870 8757 20 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART Modular Technologies January 31 2006 SM646UDR26485 2 I IDD Specification Parameters and Test Conditions Contd Notes IDD specifications are tested after the device is properly initialized Input slew rate is specified by AC Parametric Test Condition IDD parameters are specified with ODT disabled Data bus consists of DQ DM DQS DQS IDD values must be met with all combinations of ERMS bits 10 and Pons 11 Definitions for IDD LOW HIGH STABLE FLOATING SWITCHING Vin ViL Ac max Vin 2 Vin Ac min inputs stable at a HIGH or LOW level inputs at VREF Vppo 2 inputs changing between HIGH and LOW every other clock cycle once per two clocks for address and control signals and inputs between HIGH and LOW every other data transfer once per clock for DQ signals not including masks of strobes IDD Testing Parameters DDR2 667 Parameter 5 5 5 Units CL IDD 5 Tm tRCD IDD 15 ns tRC IDD 60 ns tRRD IDD 7 5 ns tcK IDD 3 ns tRASmin IDD 45 ns tRASmax IDD 70000 ns tRP IDD 15 ns tRFC IDD 105 ns Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Ke
14. DDR2 SDRAM Module 64Mx8 Based 240 pin DIMM Unbuffered Non ECC Features e Standard JEDEC No of Internal Configuration ECC Banks per SDRAM 4 Cycle Time 3 0ns e Operating Voltage 1 8V e CAS Latency 3 0 4 0 5 0 Refresh 8K 64ms Posted CASZ Additive Device Physicals FBGA Latency AL 0 1 0 2 0 3 0 amp 4 0 e Lead Finish Gold Write Latency WL Read CAS Latency 1 Lengthx Height 133 35mm x 30 00mm Burst Length 4 8 e No of sides Single sided Burst Type Sequential Interleave Mating Connector Examples Vertical Molex 87705 0021 240 Pin DDR2 DIMM Pin List Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name No Name No Name 1 VREF 31 DQ19 61 A4 91 Vss 121 Vss 151 Vss 181 VDDQ 211 DM5 2 Vss 32 Vss 62 Vppa 92 DQS5 122 DQ4 152 DQ28 182 A3 212 NC 3 DQO 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 183 A1 213 Vss 4 DQ1 34 DQ25 64 Vpp 94 Vss 124 Vss 154 Vss 184 Vpp 214 DQ46 5 Vss 35 es 65 Vss 95 DQ42 125 DMO 155 DM3 185 CKO 215 DQ47 6 DQSOR 36 DQS3 66 Vss 96 DQ43 126 NC 156 NC 186 CKO 216 Vss 7 DQSO 37 DQS3 67 Vpp 97 Vss 127 Vss 157 Vss 187 VDD 217 DQ52 8 Vss 38 Vss 68 NC 98 DQ48 128 DQ6 158 DQ30 188 AO 218 DQ53 9 DQ2 39 DQ26 69 Vpp 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 Vss 10 D
15. DQS5 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 S CKE ODT DQS DQS DM 1 0 0 l O 1 lo 2 1 0 3 lO 4 1 05 l O 6 y o 7 D4 Sit CKE ODT DQS DQS DM 1 0 0 l O 1 VO2 1 0 3 lO 4 1 05 l O 6 y o 7 D5 Sit CKE ODT DQS DQS DM 1 0 0 l O 1 VO2 1 0 3 lO 4 1 05 l O 6 VO7 D6 S CKE ODT DQS DQS DM 1 0 0 l O 1 I O 2 1 0 3 lO 4 1 05 l O 6 VO7 D7 Note Unless otherwise noted data resistor values are 22 596 Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 6 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART EDS Modular Technologies g January 31 2006 5 10 A0 A13 P to all SDRAMs DO D7 BAO BA1 to all SDRAMs DO D7 SPD RAS P to all SDRAMs DO D7 EEPROM CAS to all SDRAMs DO D7 WE to all SDRAMs DO D7 SAO SA0 Vpp Vppspp ODTO gt to all SDRAMs D0 D7 SA1 7SA1 CKEO to all SDRAMs DO D7 SA2 SA2 CSO
16. ITATIONS OF LIABILITY WARRANTY AND INFRINGEMENT PROVISIONS SMART MAKES NO WARRANTIES OF ANY KIND EXPRESS STATUTORY IMPLIED OR OTHERWISE REGARDING INFORMATION SET FORTH HEREIN OR REGARDING THE FREE DOM OF THE DESCRIBED PRODUCTS FROM INTELLECTUAL PROPERTY INFRINGEMENT AND EXPRESSLY DISCLAIMS ANY SUCH WARRANTIES INCLUDING WITHOUT LIMITATION ANY EXPRESS STATUTORY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PUR POSE 1996 SMART Modular Technologies Inc All rights reserved Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 25 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903
17. Malaysia Tel 604 3992909 Fax 604 3992903 SMART SM646UDR26485 2 I Modular Technologies January 31 2006 Serial Presence Detect Table Contd Byte No Byte Description Value Supported Value in Hex 53 AT3p fast DT3P fast 2 15 C 2Bh 54 AT3P slow DT3P slow 0 675 C 1Bh 55 AT4n DT4R AT4ARAw s Sign DTARAW 14 8 C DT4W gt DT4R 4Ah 56 ATs5p DT5B 16 C 20h 57 AT7 DT7 17 C 22h 58 Psi ca PLL Not Supported 00h 59 Psi ca RED Not Supported 00h 60 AT DTPLL Not Supported 00h 61 ATrEG DTREG Toggle Rate Not Supported 00h 62 SPD data revision code 1 2 12h 63 Checksum for bytes 0 62 DEh 64 Manufacturer JEDEC ID code Infineon s ID C1h 65 71 Manufacturer JEDEC ID code Not Used 00h 72 Manufacturing location Location xxh 73 90 Manufacturer part HYS64T64000HU 3S A P No 91 Manufacturer revision code Rev 2 x 2xh 92 sus Manufacturer revision code None xxh 93 Manufacturing data Year Date Date 94 Manufacturing data Week Date Date 95 98 Assembly serial Serial Number S No 99 127 Unused storage locations 00h Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 11 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Sebe
18. Q3 40 DQ27 70 A10 AP 100 Vss 130 Vss 160 Vss 190 BA1 220 CK2 11 Vss 41 Vss 71 BAO 101 SA2 131 DQ12 161 NC 191 VDDQ 221 CK2 12 DQ8 42 NC 72 Vppo 102 NC 132 DQ13 162 NC 192 RAS 222 Vss 13 DQ9 43 NC 73 WE 103 Vss 133 Vss 163 Vss 193 CSO 223 DM6 14 Vss 44 Vss 74 CAS 104 DQS6 134 DM1 164 NC 194 VDDQ 224 NC 15 DQS1 45 NC 75 VDDQ 105 DQS6 135 NC 165 NC 195 ODTO 225 Vss 16 DQS1 46 NC 76 CS1 NC 106 Vss 136 Vss 166 Vss 196 A13 226 DQ54 17 Vss 47 Vss 77 ODT1 NC 107 DQ50 137 CK1 167 NC 197 Vpp 227 DQ55 18 NC 48 NC 78 VDDQ 108 DQ51 138 CK1 168 NC 198 Vss 228 Vss 19 NC 49 NC 79 es 109 Vss 139 Vss 169 Vss 199 DQ36 229 DQ60 20 Vss 50 Vss 80 DQ32 110 DQ56 140 DQ14 170 VDDQ 200 DQ37 230 DQ61 All specifications of this module are subject to change without notice Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 3 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART SM646UDR26485 2 I z Modular Technologies January 31 2006 240 pin DDR2
19. SMART Modular Technologies SM646UDR26485 2 I January 31 2006 Ordering Information Part Numbers Description Device Vendor SM646UDR26485 2 I 64Mx64 512MB DDR2 240 pin DIMM Unbuffered Non ECC 64Mx8 Based PC2 5300 DDR2 667 555 30 00mm 22 DQ termination Infineon Rev A HYB18T512800AF 3S Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 gt SMART SM646UDR26485 2 Modular Technologies January 31 2006 Revision History January 31 2006 Corrected the OCD Program in the EMRS on page 14 October 4 2005 Datasheet released Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 2 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 gt SMART SM646UDR26485 2 Modular Technologies January 31 2006 512MByte 64Mx64
20. Smin IDD CKE and CS are HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD1 Operating one bank active read precharge current lout OmA BL 4 CL CL IDD 680 mA AL 0 tek tck DD RC fRC DD fRAS fRASmin IDD RCD tRcD IDD CKE and CS are HIGH between valid commands Address bus inputs are SWITCHING Data pat tern is same as IDD4W IDD2P Precharge power down current All banks idle tek tckqpp CKE is LOW Other con 40 mA trol and address bus inputs are STABLE Data bus inputs are FLOATING IDD2Q Precharge quiet standby current All banks idle tek tckqpp CKE is HIGH CS is 320 mA HIGH Other control and address bus inputs are STABLE Data bus inputs are FLOATING IDD2N Precharge standby current All banks idle tc tckqpp CKE is HIGH CS is HIGH 400 mA Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD3P Active power down current All banks open tek tckqppy CKE is Fast PDN Exit 150 mA LOW Other control and address bus inputs are STABLE Data bus MRS 12 0 inputs are FLOATING Slow PDN Exit 50 mA MRS 12 1 IDD3N Active standby current All banks open ck tcK IDD tRAS tRASmax IDD tRP 400 mA tRP IDD CKE is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD4W Operating burst write current All banks open Continuous
21. a 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART Modular Technologies SM646UDR26485 2 I January 31 2006 Pin Description Table Contd Symbol Type Polarity Function A0 AQ SSTL_18 During a Bank Activate command cycle AO A13 defines the row address RAO RA13 A10 AP when sampled at the rising clock edge A11 A13 During a Read or Write command cycle A0 A9 defines the column address CAO CA9 when sampled at the rising clock edge In addition to the column address A10 AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BA1 defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle A10 AP is used in conjunction with BAO BA1 to con trol which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO or BA1 If AP is low BAO and BAT are used to define which bank to pre charge The address inputs also provide the op code during Mode Register Set com mands DQ0 DQ63 SSTL 18 Data Input Output pins DQS0 DQS7 SSTL_18 Positive SDRAM differential data strobe for input and output data Edge DQS0 DQS7 SSTL_18 Negative SDRAM differential data strobe for input and output data Edge DMO DM7 SSTL 18 Active High DM is an input mask signal for write data I
22. ail B Detail C All dimensions are in millimeters with 0 15mm tolerance unless specified otherwise Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 8 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART Modular Technologies SM646UDR26485 2 I January 31 2006 Serial Presence Detect Table Byte No Byte Description Value Supported Value in Hex 0 of bytes written into serial memory at module 128 Bytes 80h manufacturer 1 Total of bytes of SPD memory device 256 Bytes 08h 2 Fundamental memory type SDRAM DDR2 08h 3 of row address on this assembly 14 OEh 4 of column address on this assembly 10 OAh 5 of Ranks Package and Height 1 Planar 30 00mm 60h 6 Data width of this assembly 64 40h 7 Reserved 00h 8 Voltage interface standard of this assembly SSTL_18 05h 9 SDRAM cycle time from clock CAS latency of 5 0 3 0ns 30h 10 SDRAM access time from clock CAS latency of 5 0 0 45ns 45h 11 DIMM configuration type Non ECC 00h 12 Refresh rate amp type SR 7 8 82h 13 Primary SDRAM width 8 08h 14 Error checking SDRAM width 00
23. ax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 23 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 gt SMART SM646UDR26485 2 Modular Technologies January 31 2006 Notes 1 N 11 12 13 20 21 22 23 24 The AC and DC input level specifications are as defined in the SSTL_18 standard i e the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above below the DC input LOW HIGH level Command Address minimum input slew rate 1 0V ns and is referenced to the crosspoint of CK CK tjs timing is referenced to VIH ac for a rising signal and Vu ac for a fallng signal tjj timing is referenced to Vu pc for a rising signal and Vu pc for a fallng signal Der ating values for Command Address input signal slew rates 1 0V ns are TBD Data minimum input slew rate 1 0V ns and is referenced to the crosspoint of DQS DQS if differential strobe feature is enabled tps tim ing is referenced to Vi Ac for a rising signal and Vu ac for a fallng signal tpp timing is referenced to Vu pc for a rising signal and VIL DC for a fallng signal Derating values for Data input signal slew ra
24. command tRC 60 ns ACTIVE bank a to ACTIVE bank b command tRRD 7 5 ns 23 ACTIVE to READ or WRITE delay tRCD 15 ns ACTIVE to PRECHARGE command tRAS 45 70000 ns 16 Internal READ to precharge command delay tRTP 7 5 ns 19 23 Write recovery time twR 15 ns 23 Auto precharge write recovery Precharge time tDAL twrRttrp tok 18 Internal WRITE to READ command delay twTR 7 5 ns 23 PRECHARGE command period trp 15 ns LOAD MODE command cycle time tMRD 2 tck REFRESH to REFRESH command interval tRFC 105 ns 10 Average periodic refresh Interval tREFI 7 8 us 10 Exit self refresh to non READ command tXSNR trec min ns 10 Exit self refresh to READ command tXSRD 200 tck ODT turn on delay tAOND 2 2 tok ODT turn on taon tac min tac max ps 21 1000 ODT turn off delay tAOFD 2 5 2 5 tok ODT turn off tAOF tac min tac max ps 22 600 ODT turn on power down mode taoNPD tac min 2 tcK ps 2000 tac max 1000 ODT turn off power down mode tAOFPD tac min 2 5 tcK ps 2000 tac max 1000 ODT to power down entry latency tANPD 3 tok ODT power down exit latency taxPD 8 tck Exit active power down to READ command MR bit1270 tyarp 2 tok Exit active power down to READ command MR bit1271 txarps 7 AL tck Exit precharge power down to any non read command txp 2 tck CKE minimum pulse width high and low pulse width tCkE 3 tck Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 F
25. e idle and no bursts are in progress and the controller must wait the specified time pn before initiating any subsequent operation Violating either of these requirements could result in unspecified operation Notes 1 BA2and A14 A15 are reserved for future use and must be programmed to 0 when setting the mode register 2 When the adjust mode of the OCD Calibration Program is issued AL from previously set value must be applied 3 After setting the OCD Calibration Program to default OCD mode needs to be exited by setting A9 A7 to 000 4 Outputs disabled DQs DQSs DQS s RDQSs RDQS s This feature is used in conjunction with DIMM Ipp measurements when Ippq is not desired to be included If RDQS is enabled the DM function is disabled RDQS is active for reads and don t care for writes a Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 13 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART SM646UDR26485 2 I
26. ef 0 250 V 1 2 Input Low Logic Voltage VIL AC Vref 0 250 V 1 2 Input differential voltage CK and CK VID AC 0 5 Vppo 0 6 V 1 2 3 inputs Input crossing point voltage CK and VIX AC 0 5 Vppg 0 175 0 5 Vppg 0 175 V 1 2 3 CK inputs AC differential crossing point voltage Vox Ac 9 5 Vppq 0 125 0 5 Vppg 0 125 V 3 Notes 1 Input slew rate is 1V ns Inputs are not recognized as valid until Vper stabilizes 2 3 Vipis the magnitude of the difference between the input level on CK and the input level on CK 4 The value of Vix Vox is expected to equal 0 5 Vppq of the transmitting device and must track variations in the DC level of the same Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 17 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART SM646UDR26485 2 I Modular Technologies January 31 2006 ODT DC Electrical Characteristics Parameter Symbol Min Nom Max Unit Notes Rrr effective impedence value for 75Q RTT1 EFF 60 75 90 Q 1 setting EMR A6 A2 0 1 Rrr effective impedence value for 150Q RTT2 EFF 120 150 180 Q 1
27. el 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 18 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART SM646UDR26485 2 Modular Technologies January 31 2006 OCD Default Output Characteristics Vpp 1 8V 0 1V Vsg OV TA 0 to 65 C Parameter Symbol Min Nom Max Unit Notes Output Impedance 12 6 18 23 4 Q 1 2 Pull up and Pull down mismatch 0 4 Q 1 2 3 Output Slew Rate SouT 1 5 5 Vins 1 4 5 7 Output Step Size for Calibration 0 1 5 Q 6 Notes 1 Absolute specifications 0 C lt Tease lt 85 C Vppao 1 8Vx0 1V Vpp 1 8V 0 1V 2 Impedance measurement condition for output source DC current Vppa 1 7V Vout 1420mV VouT Vppa loH must be less than 23 49 for values of Vout between Vppo and Vppg 280mV Impedance mea surement condition for output sink DC current Vppq 1 7V Vout 280mV Vourt lo must be less than 23 4Q for values of Vout between OV and 280mV 3 Mismatch is absolute value between pull up and pull down both are measured at same temperature and volt age 4 Output slew rate for falling and rising edges is measured between VT1 250mV and VT1 250mV for single ended signals For differential signals output
28. f SMART Modular Technologies Inc SMART The information in this document is subject to change without notice SMART assumes no responsibil ity for any errors or omissions that may appear in this document and disclaims responsibility for any conse quences resulting from the use of the information set forth herein SMART makes no commitments to update or to keep current information contained in this document The products listed in this document are not suitable for use in applications such as but not limited to aircraft control systems aerospace equipment submarine cables nuclear reactor control systems and life support systems Moreover SMART does not recommend or approve the use of any of its products in life support devices or systems or in any application where failure could result in injury or death If a customer wishes to use SMART products in applications not intended by SMART said customer must contact an authorized SMART representative to determine SMART s willingness to support a given application The information set forth in this document does not convey any license under the copyrights patent rights trade marks or other intellectual property rights claimed and owned by SMART The information set forth in this docu ment is considered to be Proprietary and Confidential property owned by SMART ALL PRODUCTS SOLD BY SMART ARE COVERED BY THE PROVISIONS APPEARING IN SMART S TERMS AND CONDITIONS OF SALE ONLY INCLUDING THE LIM
29. h 15 Reserved 00h 16 SDRAM device attributes Burst lengths supported 4 8 OCh 17 SDRAM device attributes of banks on SDRAM 4 04h device 18 SDRAM device attributes CAS latency 3 0 4 0 5 0 38h 19 DIMM Mechanical Characteristics 2 70mm 01h 20 DIMM type information UDIMM 02h 21 SDRAM module attributes None 00h 22 SDRAM device attributes General Weak Driver 50 ODT 03h 23 SDRAM cycle time from clock CAS latency of 4 0 3 75ns 3Dh 24 SDRAM access time from clock CAS latency of 4 0 0 50ns 50h 25 SDRAM cycle time from clock CAS latency of 3 0 5 0ns 50h 26 SDRAM access time from clock CAS latency of 3 0 0 60ns 60h Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART SM646UDR26485 2 Modular Technologies January 31 2006 Serial Presence Detect Table Contd Byte No Byte Description Value Supported Value in Hex 27 Minimum row precharge time tRP 15ns 3Ch 28 Minimum row active to row active delay tRRD 7 5ns 1Eh 29 Minimum RAS to CAS delay tRCD 15ns 3Ch 30 Minimum activate
30. lvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 21 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 gt SMART SM646UDR26485 2 Modular Technologies January 31 2006 Device AC Operating Conditions 3 0ns CL 5 0 Parameter Symbol DDR2 667 Unit Notes Min Max Clock cycle time CL 5 0 Eck 3000 8000 ps 12 20 CL 4 0 3750 8000 ps 12 20 CL 3 0 5000 8000 ps 12 20 Clock high level width tcH 0 45 0 55 tck 14 Clock low level width teL 0 45 0 55 tck 14 Clock half period typ Min ps 15 teL tcH DQ output access time from CK CK tac 450 450 ps Data out high impedence window from CK CK thz tac max ps 4 5 Data out low impedence window from CK CK tz tac min tac max ps 4 6 DQ amp DM input setup time relative to DQS tps 100 ps 3 11 17 DQ amp DM input hold time relative to DQS tpH 175 ps 3 11 17 DQ amp DM input pulse width for each input tpipw 0 35 tck Data hold skew factor taHs 340 ps DQ DQS hold DQS to first DQ to go nonvalid per toH tHp taHs ps 11 13 access DQS input high pulse width tposH 0 35 tck DQS input low pulse width tposL 0 35 tok DOS output access time from CK CK tposck 400 400 ps DQS falling edge to CK rising setup time tos
31. mon mode on Vggr may not exceed 1 of the DC value Peak to peak AC noise on Vggr may not exceed 2 of Vref DC This measurement is to be taken at the nearest VREF bypass capacitor 3 Vy 7is not used on the module It is the voltage used on the system board to terminate all the signals However this supply should track the variations in DC level of VREF Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 16 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART SM646UDR26485 2 I Modular Technologies January 31 2006 Capacitance Vpp 1 8V 0 1V Tcase 25 C Parameter Symbol Min Max Unit Input Capacitance CKn CKn CcKk 3 0 6 0 pF Input Capacitance delta CKn CKn Cock 0 75 pF Input Capacitance all other input only pins C 8 0 16 0 pF Input Capacitance delta all other input only pins Cpi 2 0 pF Input Output Capacitance DQ DM DQS DQS Cio 2 5 3 5 pF Input Output Capacitance delta DQ DM DQS DQS Colo 0 5 pF AC Operating Conditions Vpp 1 8V 0 1V Vss 0V Parameter Symbol Min Max Unit Notes Input High Logic Voltage VIH AC Vr
32. nput data is masked when DM is sampled high coincident with that input data during a write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ DQS loading SA0 SA2 LVTTL Slave Address Select for EEPROM These pins are used to configure the presence detect device SDA LVTTL Serial Bus Data Line for EEPROM SDA is a bidirectional pin used to transfer addresses and data into and out of the presence detect portion of the module A resistor must be con nected from the SDA bus line to Vpp to act as pull up on the system board SCL LVTTL Serial Bus Clock for EEPROM SCL is used to synchronize the presence detect data transfer to and from the module A resistor may be connected from the SCL bus line to Vpp to act as pull up on the system board VDD Supply SDRAM positive power supply 1 8V 0 1V Vss Supply Power supply return ground VREF Supply SDRAM UO reference supply VDDQ Supply SDRAM I O Driver positive power supply 1 8V 0 1V VDDSPD Supply Serial EEPROM positive power supply wired to a separate power pin at the connector which supports operation from 1 7V to 3 6V NC No Connect DU Do not use Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 5
33. rang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 gt SMART SM646UDR26485 2 Modular Technologies January 31 2006 Mode Register Table Definition The mode register stores the data for controlling the various operating modes of DDR2 SDRAM It controls CAS latency burst length burst sequence test mode DLL reset tWR and various vendor specific options to make DDR2 SDRAM useful for vari ous applications The default value of the mode register is not defined therefore the mode register must be written after power up for proper operation The mode register is written by asserting low on CS RAS CAS WE BAO and BAM while control ling the state of address pins AO A15 The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register The mode register set command cycle time tMRD is required to complete the write operation to the mode register The mode register contents can be changed using the same command and clock cycle requirements during nor mal operation as long as all banks are in the precharge state The mode register is divided into various fields depending on functionality Burst length is defined by AO A2 with options of 4 and 8 bit burst lengths The burst length decodes are compatible with DDR SDRAM Burst address sequence type is defined by A3 CAS latency is defined by A4 A6 The DDR2 doesn t sup port half clock latency mode A7 is used for tes
34. s 0 2 tok DQS falling edge from CK rising hold time tpsH 0 2 tck DQS DQ skew DQS to last DQ valid per group per tposo 240 ps 11 13 access DQS read preamble tRPRE 0 9 1 1 tok 18 DQS read postamble tRPST 0 4 0 6 tek DQS write preamble setup time twPRES 0 ps 8 9 DQS write preamble tWPRE 0 35 tck DQS write postamble twPST 0 4 0 6 tck 7 Write command to first DQS latching transition tposs WL 025 WL 0 25 tck Address amp control input pulse width for each input tipw 0 6 tck Address and control input setup time tis 200 ps 2 17 Address and control input hold time Dt 275 ps 2 17 CAS to CAS command delay tccp 2 tok OCD Drive mode delay Fort 0 12 ns Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 22 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART Modular Technologies SM646UDR26485 2 I January 31 2006 Device AC Operating Conditions Contd 3 0ns CL5 0 Parameter Symbol DDR2 667 Unit Notes Min Max CKE low to CK CK uncertainity tpELAY 3 475 3 475 ns 24 ACTIVE to ACTIVE same bank
35. slew rate is measured between DQS DQS 500mV and DQS DQS 500mV Output slew rate is guaranteed by design but is not necessarily tested on each device 5 The absolute value of the slew rate as measured from Vu DC max to Vip DC min is equal to or greater than the slew rate as measured from Vu AC max to Vip AC min This is guaranteed by design and characteriza tion 6 This represents the step size when the OCD is near 18 at nominal conditions across all process and repre sent only the DRAM uncertainty 7 Timing skew due to DRAM output slew rate mis match between DQS DQS and associated DGs is included in tpasa and tous specification Output Slew Rate Load Diagram VTT 250 Output Vou Reference Point Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 19 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 gt SMART SM646UDR26485 2 Modular Technologies January 31 2006 IDD Specification Parameters and Test Conditions Vpp 1 8V 0 1V Vss OV TA 0 to 65 C Symbol Parameter DEL Unit IDDO Operating one bank active precharge current tc tcK IDD RC RC IDD RAS 570 mA tRA
36. t mode A8 is used for DLL reset A7 must be set to low for normal MRS opera tion Write recovery time tWR is defined by A9 A11 BA2 BA1 BAO A15 A14 A13 A12 A11 A10 A9 A8 A7 AG AS A4 A3 A2 A1 AO Address Field M18 M17 M16 M15 M14 M13 M12 M11 M10 M9 M M7 M6 MS M4 M3 M2 M1 MO Mode Register of MR o 0 PD WR DLL TM CAS Latency BT Burst Length Burst Length M2 M1 MO BL M8 DLL Reset M3 Burst Type 0 No 0 Sequential 0 1 0 4 1 Yes 1 Interleave 1 1 8 Write recovery for autoprecharge M12 Active power CAS Latency down exit time M11 M10 M9 2 l WR cycles Me m5 M4 Latency 0 Fast exit txarp 0 0 0 Reserved 0 0 0 Reserved 1 Slow exit txarRps B d 1 P BN5NS 0 0 1 Reserved x 9 e e d 2 3 amp le le le o 1 0 2 0 optional QO jo o JQ M17 M16 MRS mode 0 1 1 4 oa a0 n 8 g 1 1 3 0 0 0 MRS 1 H B 3 1 o o 40 0 1 EMRS 1 1 0 1 6 pl 5 0 1 0 EMRS 2 Reserved 1 1 0 Reserved lun Reserved 1 1 EMRS 3 Reserved 1 1 1 Reserved lui Reserved Notes 1 BA2 and A14 A15 are reserved for future use and must be programmed to
37. tes lt 1 0V ns are TBD thz and tj 7 transitions occur in the same access time windows as valid data transitions These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving thz or begins driving tj 7 This maximum value is derived from the reference test load tyz MAX will prevail over a tposck MAX tRPST MAX Condition tLZ MIN Will prevail over a tDQSCK MIN fRPRE MAX Condition The intent of the Don t Care state after completion of the postamble is the DQS driven signal should be high low or high Z and that any signal transition within the input switching region must follow valid input requirements That is if DOS transitions high above Vu pc MIN l then it must not transition low below ViH pc prior to tposH min This is not a device limit The device will operate with a negative value but system performance could be degraded due to bus turn around It is recommended that DQS be valid HIGH or LOW on or before the WRITE command The case shown DQS going from High Z to logic LOW applies when no WRITEs were previously in progress on the bus If a previous WRITE was in progress DQS could be HIGH during his time depending on tposs The refresh period is 64ms This equates to an average refresh rate of 7 8125ys However an REFRESH comand must be asserted at least once every 70 3ys or tRFc MAX issuing more than eight REFRESH commands back to back at tRFC min
38. ular Technologies January 31 2006 DC Characteristics Absolute Maximum Ratings Parameter Symbol Ratings Unit Notes Voltage on Vpp relative to Vss VDD 1 0 2 3 V Voltage on Vppq relative to Vss VDDQ 0 5 2 3 V Voltage on any pin relative to Vss Vin Vout 0 5 2 3 V Voltage on Vppspp relative to Vss VDDSPD 1 7 3 6 V Operating Temperature Ambient TOPR 0 to 65 C Operating Temperature Case TCASE 0 to 95 C 1 2 Storage Temperature TsTG 55 to 100 C Notes 1 Itis possible to operate the DRAM above Case Temperature up to 95 C 2 Above 85 C DRAM Case Temperature the Auto Refresh command interval has to be reduced to tpEr 3 9us Recommended DC Operating Conditions TA 0 to 65 C Parameter Symbol Min Typ Max Unit Notes Supply Voltage VDD 1 7 1 8 1 9 V I O Supply Voltage VDDQ 1 7 1 8 1 9 V I O Reference Voltage VREF 0 49 Vppg 0 50 Vppq 9 51 Vppa mV 1 2 I O Termination Voltage VTT VRer 0 04 VREF Vrer 0 04 V 3 SPD Voltage VDDSPD 1 7 3 6 V Input High Voltage ViH Dc Vngr 0 125 Vppo 0 3 V Input Low Voltage VIL DC 0 3 Vref 0 125 V Input Voltage Level CK CK VIN DC 0 3 Vppo 0 3 V Input Differential Voltage CK CK Vip pc 0 25 Vppo 0 6 V Ground Vss 0 0 0 V Notes 1 Vmgpzgr is expected to track variation in Vppo Vggr 0 5 x Vppg 2 Peak to peak noise non com
39. with Auto Precharge H H L H L H BA Column H Column 1 2 3 No Operation H X L H H H X X X X 1 Device Deselect H X H X X X X X X X 1 H X X X Power Down Entry H L X X X X 1 4 L H H H H X X X Power Down Exit L H X X X X 1 4 L H H H Notes 1 All DDR2 SDRAM commands are defined by states of CS RAS CAS WE and CKE at the rising edge of the clock 2 Bank addresses BAO BA1 BA2 BA determine which bank is to be operated upon For E MRS BA selects an Extended Mode Register 3 Burst reads or writes at BL 4 cannot be terminated or interrupted 4 The Power Down Mode does not perform any refresh operations The duration of power down is therefore limited by the refresh require ments The state of ODT does not affect the states described in this table The ODT function is not available during Self Refresh X means H or L but a defined logic level Self Refresh Exit is asynchronous An A12 for 256Mb A13 for 512Mb amp 1 Gb A14 for 2Gb B n BA1 for upto 512Mb BA2 for 1 Gb amp 2Gb 0 900 Corporate Headquarters P O Box 1757 Fremont CA 94538 USA Tel 510 623 1231 Fax 510 623 1434 E mail info smartm com Europe 5 Kelvin Park South Kelvin South East Kilbride G75 ORH United Kingdom Tel 44 870 870 8747 Fax 44 870 870 8757 15 Asia Pacific Plot 18 Lrg Jelawat 4 Kawasan Perindustrian Seberang Jaya 13700 Prai Penang Malaysia Tel 604 3992909 Fax 604 3992903 SMART SM646UDR26485 2 Mod
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