Transcend 1024MB DDR2 PC2-4200 CL4 FBDimm
Contents
1. 15 VSS 96 PS6 136 VIDO 176 VSS 216 SS6 97 PS6 137 DNU M_Test 177 SN8 217 SS6 98 VSS 138 VSS 178 SN8 218 VSS 99 PS7 139 RFU 179 VSS 219 SS7 100 PS7 140 RFU 180 SN9 220 SS7 101 VSS 141 VSS 181 SN9 221 VSS 102 PS8 142 SNO 182 VSS 222 SS8 103 PS8 143 SNO 183 SN10 223 SS8 104 VSS 144 VSS 184 SN10 224 VSS 105 RFU 145 SN1 185 VSS 225 RFU 106 RFU 146 SN1 186 SN11 226 RFU 107 VSS 147 VSS 187 SN11 227 VSS 108 VDD 148 SN2 188 VSS 228 SCK 109 VDD 149 SN2 189 VSS 229 SCK 110 VSS 150 VSS 190 SSO 230 VSS 111 VDD 151 SN3 191 SSO 231 VDD 112 VDD 152 SN3 192 VSS 232 VDD 113 VDD 153 VSS 193 SS1 233 VDD 114 VSS 154 SN4 194 SS1 234 VSS 115 VDD 155 SN4 195 VSS 235 VDD 116 VDD 156 VSS 196 SS2 236 VDD 117 VTT 157 SN5 197 SS2 237 VTT 118 SA2 158 SN5 198 VSS 238 VDDSPD 119 SDA 159 VSS 199 SS3 239 SAO 120 SCL 160 SN13 200 SS3 240 SA1 RFU Reserved Future Use These pin position are reserved for forwarded clocks to be used in future module implementations These pin positions are reserved for future architecture flexibility Transcend Information Inc 32. IMM number in the AMB Voltage ID these pins must be unconnected for DDR2 base Fully Buffered DIMMs VID O is VDD value OPEN 1 8V GND 1 5V VID 1 is Vcc value OPEN 1 5V GND 1 2V AMB reset signal Reserved for Future Use AMB Core Power and AMB Channel interface Power 1 5 Volt DRAM Power and AMB DRAM I O Power 1 8 Volt DRAM Address Command Clock Termination Power VDD 2 SPD Power Ground The DNU M Test pin provides an external connection R Cs A D for testing the margin of Vref which is produced by a voltage divider on the module It is not intended to be used in normal system operation and must not be connected DNU in a system This test pin may have other features on future card designs and if it does will be included in this specification at that time TS128MFB 2V5J T 240PIN DDR2 533 Fully Buffered DIMM 1GB With 64Mx8 CL4 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 81 VSS 121 VDD 161 SN13 201 VSS 82 PS4 122 VDD 162 VSS 202 SS4 83 PS4 123 VDD 163 VSS 203 SS4 84 VSS 124 VSS 164 RFU 204 VSS 85 VSS 125 VDD 165 RFU 205 VSS 86 RFU 126 VDD 166 VSS 206 RFU 87 RFU 127 VDD 167 VSS 207 RFU 88 VSS 128 VSS 168 SN12 208 VSS 89 VSS 129 VCC 169 SN12 209 VSS 90 PS9 130 VCC 170 VSS 210 SS9 91 PS9 131 VSS 171 SN6 211 SS9 92 VSS 132 VCC 172 SN6 212 VSS 93 PS5 133 VCC 173 VSS 213 SS5 94 PS5 134 VSS 174 SN7 214 SS5 95 VSS 135 VTT 175 SN7 2
3. Latency 3 4 5 Automatic DDR2 DRAM bus and channel calibration Transcend Information Inc MBIST and IBIST Test functions Hot add on and Hot Remove Capability Transparent mode for DRAM test support es coll a d ty OO OOC ry F i j oooodoooo a L PCB 09 2600 TS128MFB 2V5J T 240PIN DDR2 533 Fully Buffered DIMM 1GB With 64Mx8 CL4 Dimensions Side I IO Imn im io 1O W J K L M Millimeters 133 35 0 15 51 67 5 2 5 1 50 10 5 175 3 25 3 9 5 18 8 30 35 0 15 1 27 0 10 Refer Placement Transcend Information Inc Inches 5 250 0 006 2 0 2 64 0 197 0 098 0 059 0 039 0 204 0 128 0 118 0 374 0 74 1 2 0 006 0 050 0 004 Pin Description Symbol SCK SCK PN 13 0 PN 13 0 PS 9 0 PS 9 0 SN 13 0 SN 13 0 SS 9 0 SS 9 0 SCL SDA SA 2 0 VID 1 0 RESET RFU VCC VDD VTT VDDSPD VSS DNU M_ Test Function System Clock Input positive line System Clock Input negative line Primary Northbound Data positive lines Primary Northbound Data negative lines Primary Southbound Data positive lines Primary Southbound Data negative lines Secondary Northbound Data positive lines Secondary Northbound Data negative lines Secondary Southbound Data positive lines Secondary Southbound Data negative lines Serial Presence Detect SPD Clock Input SPD Data Input Output SPD Address Input also used to select the D
4. TS128MFB 2V5J T 240PIN DDR2 533 Fully Buffered DIMM 1GB With 64Mx8 CL4 _Description The TS128MFB72V5J T is a 128M x 72bits DDR2 533 Fully Buffered DIMM The TS128MFB72V5J T consists of 18pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA package 1 pcs AMB IC and a 2048 bits serial EEPROM on a 240 pin board The TS128MFB72V5J T is a 240pin fully buffered dual in line memory module printed circuit The Advanced Memory Buffer also allows buffering of memory traffic to support large memory capacities All memory control for the DRAM resides in the host including memory request initiation timing refresh scrubbing sparing configuration access and power management The Advanced Memory Buffer interface is responsible for handling channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the memory channel Fully Buffered DIMM provides a high memory bandwidth large capacity channel solution that has a narrow host interface Features 240pin fully buffered dual in line memory module 3 2Gb s 4 0Gb s link transfer rate 1 8V 0 1V Power Supply for DRAM VDD VDDQ 1 5V 0 075V Power Supply for AMB VCC 3 3V 0 3V Power Supply for VODDSPD Buffer point to point Link at 1 5 volt Interface with high speed differential Channel error detection amp reporting Channel fail over mode support Serial presence detect with EEPROM 4 Banks Posted CAS Programmable CAS
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