Kingston Technology ValueRAM 2GB 533MHz DDR2 ECC Fully Buffered CL4 DIMM Dual Rank, x4
Contents
1. ii N N O e Y N N N si co al o O o SS2 O 00 N N 00 N 29 e N amp N N O N e wo co Se C2 O eo e e A E NIN O amp oa A N O These pin positions are reserved for future architecture flexibility 1 The following signals are CRC bits and thus appear out of the normal sequence PN12 PN12 SN12 SN12 PN13 PN13 SN13 SN13 PS9 PS9 SS9 SS9 VALUERAMO479 001 A00 Page 2 R Kingston DIMM Connector Pin Description PinName PinDescription System Clock Input positive line nro secondary Nerhbound Daa postie Ines M so secondary Nontiwouna Data neg nes h ste secondary Southbound Data poste nes SSS AAA Ue Voltage ID These pins must be unconnected for DDR2 based Fully Buffered DIMMs VID 0 is Vpp value OPEN 1 8 V GND 1 5 V VID 1 is Vcc value OPEN 1 5 V GND 12V RESET The DNU M Test pin provides an external connection on R Cs A D for testing the margin of Vref which is produced by a voltage divider on the module It is not intended to be used in normal system operation and must not be VID 1 0 DNU M Test connected DNU in a system This test pin may have other features on future card designs and if it does will be included in this specification at that time N N d 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK frequency 2 Eight pins re2. on DIMM 1 RESET AMB reset signal No connect Many NC are connected to VDD on the DIMM to lower the impedance of the VDD power islands R Reserved for Future Use Power Ground Signals D O 3 163 1 1 1 NC FU a 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK frequency 2 TESTLO AB20 and TESTLO AC20 should be configured for debug purposes on prototype DIMMs each pin should have a zero ohm resistor pulldown to ground and an unpopulated resistor pullup to VCC These resistors can be replaced on production DIMMs with a direct connection to ground XX N S N Jal g C9 VALUERAMO479 001 A00 Page 6 Package Dimensions Units 7 millimeters E kingston 133 35 R 0 75 8 PLACES E co co 1 19 DIA o o S e a ES 0 10 s m m3 24 40 19 62 NM 16 62 R 0 5 MIN do q 4 PLACES 3 00 DIA 30 35 4 PLACES 4 30 0 21 1 30 2 15 5 20 5 A 120 0 if 2 PLACES O o DETAIL A a E o Oe R 0 75 0 a 0 10 FE PLACES CEN S 2 PLACES oo DDO Nu CJ C 0 346 8 8 MAX with heat sink Units inches millimeters 45 x 0 0071 0 18 ES 3 0 047 1 19 11 061 M 0 042 1 06 0 054 1 37 Detail A 0 046 1 17 VALUERAM0479 001 A00 Page 7
3. 2 DQ35 1 03 1 0 3 DQ39 103 103 DQS5 DQS14 DQS5 DQS14 DM CS bas DAS DM CS Das DQS DM CS Das DAS DQ40 1 0 0 1 0 0 DQ44 I O 0 DO41 1101 D5 I O 1 D23 DO45 O1 p32 DQ42 __ 99 I O 2 DO46 __ I O 2 DQ43 1 0 3 0 3 DQ47 1 0 3 DQS6 DQS15 DQS6 AHH DQS15 O DM CS Das bas BM DM CS Das Das EM CS Das Das DQ48 1 0 0 DQ52 __ 1 00 I O 0 DQ49 __ 0 1 D6 T 14 1 0 1 DQ53 ___ 1 0 1 D15 I O 1 D33 DQ50 j yo2 DQ54 J yo2 1 0 2 DQ51 103 DQ55 ___ 9 3 1 0 3 DQS7 DQS16 po DQS7 T DQS16 DM CS Das bas EM CS DAS bas DM CS Das Das B 1 0 0 0 0 Bo I O 0 DQ57 34 1 0 1 I O 1 D25 I O 1 D34 DQ58 _ 1 0 2 of I O 2 DQ62 1 0 2 DQ59 1 0 3 0 3 DQ63 I O 3 DQS8 DQS17 DQS8 DQS17 Qu CS Das Das PM CS DQS DAS DM CS Das DOS EM CS DQS DOS CBO 1 0 0 I O 0 CB4 11 00 I O 0 CB1 1 01 D8 I O 1 D26 CBS lI O1 D17 O1 D35 CB2 ___ 1 0 2 I O 2 CB6___ 1 02 1 0 2 CB3 1 0 3 1 0 3 CB lpyo35 1 0 3 PNO PN13 SNO SN13 Vit Terminators PNO PN13 SNO SN13 All address command control clock yy Vr Ves AMB PSO PS9 SS0 SS9 PSO PS9 SS0 SS9 Serial PD VDDSPD ES SPD AMB DQ0 DQ63 S0 gt CS DO D17 SCL E CBO CB7 CKEO gt CKE D0 D17 SORS Ae S SDA Vpp T DO D35 AMB DQS0 DQS17 S1 gt CS D18 D35 DQSO0 DQS17 CKE1 gt CKE D18 D35 NN SAO SA1 SA2 VREF DO D35 SCL ODT ODTO all SDRAMs T L SDA BAO BA2 all SDRAMs Notes SS E SPD A0 A15 all SDRA
4. Ki a ON Memory Module Specifications TN KVR533D2D4F4 2G 2GB 256M x 72 Bit PC2 4200 CL4 ECC 240 Pin FBDIMM Description This document describes ValueRAM s 2GB 256M x 72 bit PC2 4200 CL4 SDRAM Synchronous DRAM fully buffered ECC dual rank memory module This module is based on thirty six 128M x 4 bit 533MHz DDR2 FBGA components The module also includes an AMB device Advanced Memory Buffer The electrical and mechanical specifications are as follows Feature e FBDIMM Module 240 pin e JEDEC Standard R C H e Memory Organization 2 rank of x4 devices e DDR2 DRAM Interface SSTL 18 o DDR2 Speed Grade 533 Mbps e CAS Latency 4 4 4 o Module Bandwidth 4 2 GB s o FBDIMM Channel Peak Throughput 6 4 GB s e DRAM VDD VDDQ 1 8V e AMB VCC VCCFBD 1 5V e EEPROM VDDSPD 3 3V typical e Heat Spreader AMB only heat sink o PCB Height 30 35mm double side e RoHS Compliant VALUERAM0479 001 A00 03 01 06 Page 1 ie Kingst Ston DDR2 240 pin FBDIMM Pinout GEHE pere GERE ee Side Side Side Side Side Side Side Side Ey ETCN M Tep en CI em CINA BLU HEURE 32 PNS wa SNS fef ves fise Ves dam a 3 Y t9 Y Pos ves wo vs fef emo jus sw ffos rss fats sso Ves jji Vos Pos eno fisa sma fej Pwo ies smo fos Pos zw ss 5 Y t5 Y os Pre fos Sw e we ies Vss s de mel Me Vm t5 Yoo e en e O pun e swa pse ze ss T Y t Yoo ens per m IM or Ps TE 8 Ves res vos f P
5. Ms T i a gel RAS all SDRAMs 1 DQ to I O wiring may be changed within a nibble RESET a 2 There are two physical copies of each address command control S SCK SCK oon all SDRAMs 3 There are four physical copies of each clock VALUERAM0479 001 A00 Page 4 E kingston Architecture Advanced Memory Buffer Pin Description FB DIMMChamelSigals 89 DDR2 Interface Signals passu pat seres peste me B raso Date Saves mega ines e baspireyoMes pat seches 4 DRAM onb pose Ines These signals ae driven ow 1038 DRAM on wes o _ Barre pata Steve DRAM ony negate Ines ko A TN Ceao sazo eenas Sid Op KE Clock Enable ne prank SONT CLK 1 0 used on 9 and 18 device DIMMs CLK 3 0 used on 36 device DIMMs CLK 3 2 should be out CLK 5 0 put disabled when not in use GLK 0 DDRC C14 DDRC B18 DDRC C18 VALUERAM0479 001 A00 Page 5 ie kingston Advanced Memory Buffer Pin Description SPD Bus Interface Signals SCL Serial Presence Detect SPD Clock Input SDA SPD Data Input Output SA 2 0 SPD Address Inputs also used to select the DIMM number in the AMB Miscellaneous Signals PLLTSTO VCCAPLL Analog VCC for the PLL Tied with low pass filter to VCC 1 VSSAPLL Analog VSS for the PLL Tied to ground on the AMB die Do not tie to ground on the DIMM 1 TEST pin Leave floating on the DIMM TESTLO pin Tie to ground on the DIMM 9 BFUNC Tie to ground to set functionality as buffer
6. s js 2 Ves 12 vec fel vos 10 Vos fiso Veo f4 Pms eo 11 Ve ro ys e e 12 Veo wz Yee a2 Ves fpe 1 Yee t99 Veo se e ve E Ves ros Ves e nr pe mr s Ver ms Wer fas m ros m aj 104 551 e vor fise voo Pas Vos e vss rs we 17 RESET 137 onum rest ar ves fier ves ve Ps2 196 DADES pia is sm faj Ps2 jio 19 meu aso Reue ao PN roo sn e vos 196 2 rt lao meo so ves mo Vos 7o eso no ve e ve si eno ari sne eo Ps 20 sss 22 eno ua sno sj Pm we SNe DN RN n 2 mel wo S9 Ves wa vss fef Pse 22 24 Ves t Vos OEA CEN es Ps s e m x we oe ae os mr jus svo e vos jm ve rs 2 PNT e 5 DETON OEA eo DETS 3 27 Ves wr Vss LIE ALONE NN 86 mr 2061 Reu we e w Ge mere s Pre vs rm far cr ea ser n os PNZ ue sa Poo ves mo Vos Ye ves fff Vos ro soa zo so 00 Ves wo ves eo eno wo sw eo ves Joo ves wo scr o sa ojo ELI di ivwi re fre 9 f d RFU Reserved Future Use These pin positions are reserved for forwarded clocks to be used in future module implementations UU Z Z i Z Z SN5 Co Vss 8 Vss lt N Oo 00 co o o PS7 220 SS7 c o BES e IE amp oo te NN N uum O al co 9 co N o wo PS8 223 SS8 oO e e o O O gt N N N IN 3 e e al FU 225 RFU
7. served for forwarded clocks eight pins reserved for future architecture flexibility VALUERAM0479 001 A00 Page 3 Functional Block Diagram E kingston VSS 1 S0 DQSO DQSO x CS DAS bas CS Das DAS DM CS DAS DAS DQO 1 0 O DQ4 1 0 0 DQ1 1 0 1 DO D18 DQ5 1 0 1 D9 DQ2 1 0 2 DQ6 1 0 2 DQ3 DQ7 0 3 DQS1 DQS10 DOS DQS10 CS Das Das EM CS DAS bas DM CS DAS Das DQ8 1 0 0 0 0 DQ12 I O 0 DQ9 1 0 1 D4 I O 1 D19 DQ13 I O 1 D28 DQ10 I O 2 I O 2 DQ14 I O 2 DQ11 1 10 3 1 0 3 DQ15 1 0 3 DQS2 DQS11 DQS2 Ce DQS11 J EM CS bas bas DM CS Das DAS BM CS Das Das DQ16 1 0 0 DQ20 1 0 0 I O 0 DQ17 1 0 4 D2 DQ21 1 0 1 D11 I O 1 D29 DQ18 I O 2 DQ22 1 0 2 I O 2 DQ19 1 0 3 DQ23 1 0 3 I O 3 DQS3 DQS12 DQS3 DQS12 CS DAS DAS DQ24 DQ28 DQ25 DQ29 T can DQ27 DQS4 DQS13 DQS4 DQS13 DM CS DAS DAS DM CS DAS Das DM CS Das bas DM CS Das Das DQ32 yoo 1 0 0 DQ36 l O 0 L 1 00 DQ33 O 1 D4 I O 1 D22 DQ37 ___ 1 01 D13 1 0 1 D31 DQ34 ___ 0 2 I O 2 DQ38 j jyoo2 HL 1 0
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