Transcend 1GB DDR266 Unbuffer Non-ECC Memory
Contents
1. ns Refreshrowcycletime tRFC 75 amp ns Rowacivetime tRAS __ 45 20K ms IRAS to CAS delay 1 1 fRCD 20 ts Row active to Row active delay 20 ns Row active toRowactivedelay 15 ns Writerecoverytime WR 15 ns Last data in to Read command 1 J tCK Col Address to Col Address delay _ 1 J tk Clockcydetime CK 75 o 2 ns Clock high levelwidth n tCH _ 045 05 J Clocklowlevelwidh tct 045 05 J DQS out access time from CK CK tDQASCK 075 075 ns J J 9 Output data access ime fromCK CK 075 075 ns Data strobe edge to output data edge 1 05 ns Read Preamble tRPRE 09 11 tK Read Postamble RPST 04 06 tK 125 DQS insetuptime WPRES O0 J nms 2 DQS in hold time WPREH 025 tK 9 J DQS falling edge to CK rising setup time tDSS 02 CK DQS falling edge from CK rising holdtime tDSH 02 L CK DQS in high level width twDQSH 035 tCK 9 DQS inlowlevelwdh2. 035 tk DQS in cycle time tDSC 09 11 tek tIS 09 J ns j L tH 09 __ _ ns J J ns Mode register set cycle time tMRD 15 ns DQ amp DM setup timeto DQS HDS 05 Z X ms DQ amp DMholdtimeto DOS tDBH 05 ms DQ amp DMinputpulewidh tDPW J 175 _ mns Power down exittime PDEX 75 ts Exit self refresh to non Read command 75 ts J J Exit self refresh to read command tXSRD 200 tK Refresh interval time tREF 78 ts 1 Clockhalffperiod HP tCLmin ortCHmn ns Data hold skew factor 075 ns DQS write postambletime WPST 04 06 3 Note 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case shown DQS going from High Z to logic Low applies when no writes were previously in progress on the bus If a previous write was in progress DQS could be High at this time depending on tDQSS 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly Tr
3. issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 This combination is not defined for any function which means No Operation NOP in DDR SDRAM V Transcend Information Inc Q 184 PIN DDR266 Unbuffered DIMM TS1 28MLD64V6J 1GB With 64Mx8 CL2 5 Serial Presence Detect Specification Vendor Part 0 fof Bytes Written into Serial Memory _ 128byes _ 0 0 6 DataWidth of this Assembly 4 7 DataWidth ofthis Assembly 0 8 VDDQandinterface Standard of this Assembly _ SSTL25V 04 9 DDR SDRAM Cycle Time at CAS Latency 25 75ns 75 11 DIMM configuration type non parity Party ECC ECC 0 ___ 18 PrimaryDDRSDRAMWidth O X O B 14 Error Checking DDR SDRAM Width Back Random Column Address 0C 0 0 18 19 20 Registered address amp NO DDR SDRAM Module Attributes control inputs and on card DLL 0 2V voltage DDR SDRAM Device Attributes General tolerance DDR SDRAM Cycle Time CL 2 0 A DDR SDRAM Access from Clock CL 2 0 7 DDRSDRAMCycleTimeCl 1 5 o o DDR SDRAM Access from Clock CL 1 5 5 3 ni Oo Minimum RAS to CAS Del
4. 184 PIN DDR266 Unbuffered DIMM TS1 28MLD64V6J 1GB With 64Mx8 CL2 5 Description Placement The TS128MLD64V6J is a 128Mx64bits Double Data Rate SDRAM high density for DDR266 The TS128MLD64V6J consists of 16pcs CMOS 64Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages and a 2048 bits serial EEPROM on a 184 pin printed circuit board The TS128MLD64V6J is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e RoHS compliant products e Power supply VDD 2 5V 0 2V VDDQ 2 5V 0 2V e Max clock Freq 133MHZ Double data rate architecture two data transfers per UOO clock cycle e Differential clock inputs CK and CK e DLL aligns DQ and DQS transition with CK transition e Auto and Self Refresh 7 8us refresh interval e Data I O transactions on both edge of data strobe PCB 09 1670 e Edge aligned data output center aligned data e Serial Presence Detect SPD with serial EEPROM e SSIL 2 compatible inputs and outputs e MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequ
5. MX8 CAS an ii CAS SDRAM CSO i TETTE CK1 CK1 CKO CKO _ CK2JCK2 iilii DQO DQ7 i RAS a dA B SDRAM AO A12 BAO BA1 a DQO DQ7 l m Pt 8 CK1 CK1 CKO CKO _ LLL cK2ick2 _ F BAO BA1 RAS CAS ANE Serial EEPROM SCL SCL SDA SDA AO A1 A2 SAO SA1 SA2 RAS 64MX8 DDR CAS SDRAM AO BAO BA1 DQ0 DQ7 RAS 64MX8 DDR SDRAM BAO BA1 DQ0 DQ7 RAS 64MX8 CAS DDR WE SDRAM This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 184 PIN DDR266 Unbuffered DIMM TS1 2Z8MLD64V6J 1GB With 64Mx8 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Umit Voltage on any pin relative to Vss Voltage on VDD supply to Vss torage temperature Power dissipation hort circuit current Operating Temperature Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating condition
6. anscend Information Inc 184 PIN DDR266 Unbuffered DIMM TS1 2Z8MLD64V6J 1GB With 64Mx8 CL2 5 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low L L L 1 2 OP CODE Register Mode Register Set H Column Read amp Address Column Address Column Address Burst Stop Active Power Down Precharge Power Down Mode X X X i Write amp M H X Column Address H V X No Operation Command X Note OP Code Operand Code A0 A12 amp BAO BA1 Program keys EMRS MRS EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS Auto refresh functions are same as the CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state BAO 1 Bank select addresses If both BAO and 1 are Low at read write row active and precharge bank A is selected If both BAO is High and BA1 is Low at read write row active and precharge bank B is selected If both BAO is Low and 1 is High at read write row active and precharge bank is selected If both BAO and 1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAO and 1 are ignored and all banks are selected During burst write with auto precharge new read write command cannot be
7. as been bandwidth limited to 200MHZ 5 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same Transcend Information Inc 5 184 PIN DDR266 Unbuffered DIMM TS1 2Z8MLD64V6J 1GB With 64Mx8 CL2 5 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Parameter Symbol Max ____ Symbol Operating current One bank Active Precharge tRC tRCmin DQ DM and DQS inputs changing twice per clock cycle 2080 Address and control inputs changing once per clock cycle Operating current One bank operation One bank open Burst 4 Reads CORE HE Refer to the following page for detailed test condition Precharge power down standby current All banks idle power down mode ope 9 m CKE lt VIL max VIN VREF for DQ DQS and DM Precharge Floating standby current CS gt VIH min All banks idle gt VIH min Address and other control inputs changing once per clock IDD2F 800 mA cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode CKE lt VIL max VIN VREF for DQ DQS and DM wo 40 m Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax DQ DQS and DM inputs changing twice per clock cycle ee ee address and other control inputs changing once per
8. ay tRCD 5 Minimum active to Precharge time tRAS 2 U o Module ROW density 512MB Command Address Input Setup Time Transcend Information Inc 10 NO 22 23 24 25 26 2 28 29 30 31 32 184 PIN DDR266 Unbuffered DIMM TS1 28MLD64V6J 1GB With 64Mx8 CL2 5 33 Command AddressInputHold Time ns o 3661 Superset Information 00 O 62 SPD Data Revision Code sis 63 Checksum for Bytes 0 62 01 O Manufacturers JEDEC ID 54 Manufacturers Part Number TS128MLD64V6J Variable Variable 99 127 Manufacturer SpecificData Transcend Information Inc 11
9. clock cycle Operating current burst read Burst length 2 reads continuous burst eum ma One bank active address and control inputs changing once per clock cycle IDD4R 2520 mA 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle DQ DM and DGS inputs changing twice per clock cycle IDA ius s 50 of input data changing at every burst Auto refresh current tRC tRFC min 10 tCK for DDR266at 133Mhz distributed refresh iid SS m Self refresh current lt 0 2V External clock should be on Operating current Four bank operation Four bank interleaving with BL 4 IDD7 4600 Refer to the following page for detailed test condition Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Transcend Information Inc 6 184 PIN DDR266 Unbuffered DIMM TS1 2Z8MLD64V6J 1GB With 64Mx8 CL2 5 AC OPERATING CONDITIONS Symbol Min Max__ Unit Note nput High Logic 1 Voltage DQ DQS DM signals VIHAC VREF 031 v 3 nput Low Logic 0 Voltage DQ DQS and DM signals VILLAC VREF 0 31 Note 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device a
10. ence Sequential amp Interleave Transcend Information Inc TS128MLD64V6J 184 PIN DDR266 Unbuffered DIMM 1GB With 64Mx8 CL2 5 Dimensions Side I O in im W Millimeters 133 35 0 20 72 39 6 35 2 20 31 75 0 20 19 80 4 00 12 00 1 27 0 10 Refer Placement Transcend Information Inc Inches 5 250 0 008 2 850 0 250 0 087 1 250 0 008 0 779 0 157 0 472 0 050 0 004 Pin Identification Symbol Function A0 A12 BAO BA1 Address input DQ0 DQ63 DQS0 DQS7 CKO CKO CK1 CK1 CK2 CK2 CKEO CKE1 CS0 CS1 RAS ICAS IWE DMO DM7 VDD VDDQ VREF VDDSPD SA0 SA2 SCL SDA VSS NC Data Input Output Data strobe input output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data in Mask 2 5 Voltage power supply 2 5 Voltage Power Supply for DQS Power Supply for Reference 2 5 Voltage Serial EEPROM Power Supply Address in EEPROM serial PD Clock Serial PD Add Data input output Ground No Connection 184 PIN DDR266 Unbuffered DIMM TS1 28MLD64V6J 1GB With 64Mx8 CL2 5 Pinouts i Pin i Pin i Pin Pin Name No Name Please refer Block Diagram Transcend Information Inc 3 184 PIN DDR266 Unbuffered DIMM TS128MLD64V6J 1GB With 64Mx8 CL2 5 Block Diagram AO A12 AO A12 AO A12 BAO BA1 BAO BA1 BAO BA1 DQ0 DQ63 DQO DO7 DQO DQ7 RAS RAS 64MX8 RAS RAS 64
11. nd must track variations in the DC level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz AC OPERATING TEST CONDITIONS VDD 2 5 VDDQ 2 5 TA 0 to 70 C Parameter Unt Note Input reference voltage for Clock 1 O5VDDQ VT Input signal maximum peak swing o 15 V Input Levels VIH VIL VREFXOSINREFOS1 V Input timing measurementreferencelevel V o Output timing measurementreferencelevel YT V Output load condition S See toad Circuit VTT 0 5 VDDQ Output O 0 5 VDDQ ES CLoAD 30pF Output Load circuit Input Output CAPACITANCE Voo 2 5V Vona 2 5V TA 25 C f 1MHz Input capacitance AO A12 BAO BA1 RAS CAS ANE Input capacitance CKEO CKE1 Input capacitance CSO CS1 Input capacitance CKO CK2 CK0 CK2 Input capacitance DMO DM7 Data and DQS input output capacitance DQ0 DQ63 Transcend Information Inc 184 PIN DDR266 Unbuffered DIMM TS1 2Z8MLD64V6J 1GB With 64Mx8 CL2 5 AC Timing Parameters amp Specifications These AC characteristics were tested on the Component Paramte Symbol Min Rowcycletime 1 tRC 65
12. s Voltage referenced to Vss 0V 0 to 70 C upply voltage O Supply voltage O Reference voltage O Termination voltage nput logic high voltage nput logic low voltage nput Voltage Level CK and CK inputs nput Differential Voltage CK and CK inputs nput crossing point voltage CK and CK inputs VIX DC nput leakage current uA Output leakage current loz uA Output High Current Normal strength driver VOUT VTT 0 84V Output Low Current Normal strength driver VOUT VTT 0 84V Output High Current Half strength driver VOUT VTT 0 45V Output High Current Half strength driver IOL 8 o m Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VIT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 VID is the magnitude of the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that h
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