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Transcend 256MB SDRAM PC133 Unbuffer Non-ECC Memory

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1. 09 7149 TS32MLS64 V6D 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 Pin Identification Symbol Function A0 A11 BA1 Address input Dimensions Side Millimeters Inches 133 35 0 40 5 25040 016 B 65 67 2 585 23 49 0 925 D 8 89 0 350 E 3 00 0 118 F 29 21 0 20 1 150 0 008 G 19 80 0 788 H 15 80 0 622 l 1 27 0 10 0 050 0 004 Refer Placement Transcend Information Inc DQ0 DQ63 Data Input Output CLKO CLK3 Clock Input CKEO CKE1 Clock Enable Input CS0 CS3 Chip Select Input RAS Row Address Strobe CAS Column Address Strobe ANE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection 168PIN PC133 Unbuffered DIMM TS32M LS64V6D 256MB With 16Mx8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 000 44 86 0032 128 03 001 45 CS2 87 DQ33 129 CS3 04 DQ2 46 DQM2 88 DQ34 130 DQM6 05 DQ3 47 DQM3 89 DQ35 131 DQM7 06 Vcc 48 NC 90 Vcc 132 A13 07 DQ4 49 Vcc 91 DQ36 133 08 DQ5 50 NC 92 DQ37 134 NC 09 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 A CB6 11 008 53 CB3 95 DQ40 137 CB7 12 Vss 54 Vss 96 Vss 138 Vss
2. 0 4 V IOL 2mA Input leakage current 10 10 uA 3 Note 1 5 6V AC The overshoot voltage duration is lt 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE Voo 3 3V 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Address Ao A11 BAo BA1 CADD 45 85 pF RAS CAS WE CIN 45 85 pF CKE CKEO CKE1 CCKE 25 45 pF Clock CLKO CLK3 CCLK 15 21 pF CS 0 CS3 Ccs5 15 25 DQM DQM7 10 15 DQ 200 2063 13 18 Transcend Information Inc 5 TS32MLS64V6D 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note Operating Current ICC1 Burst Length 1 960 mA 1 One Bank Active tRC gt tRC min Precharge Standby Current Icc2P CKE lt ViL max tcc 10ns 32 mA IccePS amp CLK lt ViL max tcc 32 Precharge Standby Current ICc2N gt CS gt ViH min tcc 10ns 320 mA in non power down mode Input signals are changed one time during 20ns Icc2NS_ CKE gt ViHimin CLKxViL max tcc
3. lt 160 Input signals are stable Active Standby Current Icc3P lt tcc 10ns 80 mA iM Gown mods IccaPS CKE amp CLKsViL max 80 Active Standby Current Icc3N CKEsViH min CSsViH min tcc 10s 480 mA in non power down mode Input signals are changed one time during 20ns One Bank Active IccaNS CKE ViH min CLKxViL max 400 Input signals are stable loL 0 mA Operating Current Page Burst Bust Mode oes 4 Banks activated 1120 2CLKs Refresh Current 5 tRC2tRC min 1840 mA 2 Self Refresh Current cce C 32 lt 0 2 L 12 8 Note 2 Refresh period is 64ms 3 Unless otherwise noted input swing level is CMOS ViH ViLEVDDQ VSSQ Transcend Information Inc 1 Measured with outputs open TS32MLS64V6D 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 AC OPERATING TEST CONDITIONS vo 3 3V 0 3V 0 to 70 C Parameter Value Unit AC Input levels Vih Vil 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 uem Va la 2mA ur as e 7777 Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter
4. 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 3 F6 128 Unused Storage Locations Open FF Transcend Information Inc 11
5. Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time tRAS min 45 ns 1 tRAS max 100 us Row cycle time tRC min 65 ns 1 Last data in to row precharge tRDL min 2 CLK 2 Last data in to Active precharge tDAL min 2 CLK Last data in to new col address delay tCDL min 1 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tCCD min 1 CLK 3 Number of valid output data CAS latency 3 2 ea 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 168PIN PC133 Unbuffered DIMM TS32M LS64V6D 256MB With 16Mx8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Min Max Unit Note CLK cycle time tcc 7 5 1000 ns ns CLK to valid output delay tSAC 5 4 ns 1 2 Output data hold time tOH 3 0 ns 2 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time 155 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output
6. in Low Z tSLZ 1 ns 2 CLK to output in Hi Z tSHZ 5 4 ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf Ins If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 8 TS32MLS64V6D 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 SIMPLIFIED TRUTH TABLE COMMAND 1 CS RAS CAS WE DQM BAo 1 A11 Ao Ag Note Register Mode Register Set H X L L L L X OP CODE 1 2 Refresh Auto Refresh H H L L L H X X 3 Self Entry L 3 Refresh Exit L H L H H H X X 3 H X X X 3 Bank Active amp Row H X L L H H X V Row Address Read amp Auto Precharge Disable H X L H L H X V L Column 4 Column Address Precharge Enable H Address 4 5 Write amp Auto Precharge Disable H X L H L L X V Column 4 Column Address Precharge Enable H pen 4 5 07 A9 Burst Stop H X L H H L X X 6 Precharge Bank Selection H X L L H X V L X Both Banks X H Clock Suspend or H L H X X X X X Active Power Entry Down L V V V Exit L H X X X X X Precharge Power H L H X
7. 13 009 55 0016 97 0041 139 0048 14 0010 56 0017 98 0042 140 0049 15 0011 57 0018 99 0043 141 0050 16 0012 58 0019 100 0044 142 DQ51 17 0013 59 Vcc 101 DQ45 143 18 Vcc 60 DQ20 102 Vcc 144 DQ52 19 DQ14 61 NC 103 09046 145 20 0015 62 Vref 104 0047 146 21 CBO 63 CKE1 105 CB4 147 REGE 22 CB1 64 Vss 106 CB5 148 Vss 23 Vss 65 0021 107 Vss 149 0053 24 NC 66 DQ22 108 150 0054 25 67 0023 109 NC 151 0055 26 Vcc 68 Vss 110 Vcc 152 Vss 27 ANE 69 DQ24 111 CAS 153 DQ56 28 DQMO 70 DQ25 112 4 154 0057 29 DQM1 71 DQ26 113 DQM5 155 0058 30 CSO 72 DQ27 114 CS1 156 0059 31 73 Vcc 115 RAS 157 Vcc 32 Vss 74 DQ28 116 Vss 158 DQ60 33 75 0029 117 A1 159 0961 34 2 76 0030 118 160 0062 35 A4 77 DQ31 119 161 0063 36 78 Vss 120 7 162 Vss 37 A8 79 CLK2 121 A9 163 CLK3 38 A10 AP 80 NC 122 164 NC 39 BA1 81 NC 123 11 165 SAO 40 Vcc 82 SDA 124 Vcc 166 SAI 41 Vcc 83 SCL 125 CLK1 167 SA2 42 CLKO 84 Vcc 126 A12 168 Vcc Please refer Block Diagram Transcend Information Inc 3 TS32MLS64V6D Block Diagram 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 1 CS1 CSO B FEM E ey E DQM ICS ICS ICS ICS 100 100 2035 1 00 DOI VO 1 H UO 1 VO 1 DQ2 12 Ul 102 U9 DQ33 VO 2 m DQO 1 03 103 2032 1 03 DQ7 VO 4 Ky 104 DQ39 104 m DQ5 105 meee DQ38 VO
8. 5 DQ6 1 06 Lj 106 2037 1 06 4 204 UO 7 107 2036 DOMI DOMS A DOM CS CKE DQM ICS DOM CS CKE i DQM ICS CKE 208 100 100 2042 100 100 D e UO 1 Dod YO meee 22 VO 2 3 102 3 02 103 U10 2040 1 03 B IO 3 014 2015 VO 4 VO 4 2044 104 1 0 4 2014 IO 5 10 5 2046 105 E 5 2013 I O 6 106 2047 I O 6 I O 6 2012 107 107 2045 107 17 DQM2 DQM6 DQM CS CKE ICS DQM 5 2019 100 100 051 100 100 RBAI i Bas AW 2 2049 102 2016 1 03 1 03 Ull 2048 V0 3 U7 VO 3 015 2023 104 104 2053 104 I O 4 DQ22 5 105 2054 10 5 105 2021 1 06 IO 6 2055 106 I O 6 2020 I 07 IO7 DQM3 SSS DQM ICS CKE DQM ICS CKE 2052 DQM7 VO7 VOT DQM ICS CKE DQM ICS CKE DQ24 100 1 00 2058 9 2 100 Do2 VO 1 VO 1 DOS 19 VO 1 0027 093 04 012 0056 jos 08 016 2030 14 4 2060 TO M 14 2031 5 Ios 2061 5 0029 106 106 2062 106 2028 7 I 07 DQ63 107 7 A 101 016 VDD gt 1 01 016 01 916 RAS 01 016 VSS LL EEPROM CAS 01 016 SCL SDA WE 01 016 CLKO 12506 CLK2 U3 04 U7 U8 d SAO SA2 CLKI f CLK3 U11 U12 U15 U16 Note 1 U1 U16 are 16Mx8 SDRAM 2 DQ to I O wiring may be changed per nibble 3 Unless otherwise noted resi
9. SDRAM Device Attributes CS Latency 0 clock 01 20 SDRAM Device Attributes Write Latency 0 clock 01 21 SDRAM Module Attributes NOn ed nom redisieicd 00 amp redundant addressing 10 voltage tolerance 22 SDRAM Device Attributes General Bust Bead 0E precharge all auto precharge 23 SDRAM Cycle Time CAS Latency of 2 10ns 24 SDRAM Access Time from Clock CAS Latency of 2 6ns 60 25 SDRAM Cycle Time CAS Latency of 1 00 26 SDRAM Access Time from Clock CAS Latency of 1 00 27 Minimum Row Precharge Time t RP 20ns 14 28 Minimum Row Active to Row Activate RRD 15ns OF 29 Minimum RAS to CAS Delay t RCD 20ns 14 30 Minimum Activate Precharge Time RAS 45ns 2D 31 Module Row Density 2 rows of 128MB 20 32 Command and Address Signal input Setup Time 1 5ns 15 33 Command and Address Signal input Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 jData Signal Hold Time 0 8ns 08 36 61 Information 00 62 SPD Data Revision Code JEDEC2 02 63 Checksum for Bytes 0 62 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend 7 4 72 Manufacturing Location 54 73 90 Manufacturers Part Number TS32MLS64V6D 54 53 33 32 40 4 53 36 34 56 36 44 Transcend Information Inc 10 168PIN PC133 Unbuffered DIMM TS32M LS64V6D 256MB With 16Mx8 CL3 20 20 20 20 20 20
10. TS32MLS64V6D 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 Description The TS32MLS64V6D is a 32M bit x 64 Synchronous Dynamic RAM high density for PC 133 TS32MLS64V6D consists of 16pcs CMOS 16Mx8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS32MLS64V6D is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e RoHs Compliant Product e Performance Range PC 133 e Conformed to JEDEC Standard Spec Burst Mode Operation Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write Serial Presence Detect SPD with serial EEPROM LVTTL compatible inputs and outputs Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave All inputs are sampled at the positive going edge of system clock Transcend Information Inc Placement DE
11. X X X X Down Mode EON L H H X X X X Exit L V V V DQM H X V X 7 No Operation Command H X H X X X X X L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state BAo BAt Bank select address If both BAo and are Low at read write row active and precharge bank is selected If both BAo is Low and 1 is High at read write row active and precharge bank B is selected If both BAo is High and 1 is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BAi are ignored and both banks are selected During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DQM sampled at positive going edged of a CLK masks the data
12. in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend Information Inc 9 TS32MLS64V6D Serial Presence Detect Specification 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 12 0 4 of Column Addresses this Assembly 10 0 5 of Module Rows this Assembly 2 rows 02 6 Data Width of this Assembly 64bits 40 7 Data Width of this Assembly 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time CAS latency of 3 7 5ns 75 10 SDRAM Access Time from Clock CAS latency of 3 5 4ns 54 11 _ DIMM configuration type non parity ECC None 00 12 Rate Type 15 625us Self Refresh 80 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width None 00 15 Min Clock Delay for Back to Back Random Address tCCD 1CLK 01 16 SDRAM Device Attributes Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 SDRAM Device Attributes of banks on SDRAM device 4 bank 04 18 SDRAM Device Attributes CAS Latency 2 3 06 19
13. ster values are 10 Ohms 5 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 168PIN PC133 Unbuffered DIMM TS32M LS64V6D 256MB With 16Mx8 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TsTG 55 150 Power dissipation PD 16 Short circuit current los 50 mA Operating temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDDQ 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 24 V 2 Output low voltage VOL

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