Transcend 256MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory
Contents
1. Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly A0 A12 OD 4 of Column Addresses on this Assembly A0 A8 09 5 of Module Banks on this Assembly 2 banks 02 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC DIMM 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X16 10 14 Error Checking SDRAM Width 0 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 amp 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec R W Burst OE 23 SDRAM Cycle Time 2 highest CL 10ns AO 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module2. Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6G 256MB With 16MX16 CL3 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn CS RAS CAS WE DQM BAo 1 A10 AP A12 A11 Ao Ag Note Register Mode Register Set H x L L L L x OP CODE 1 2 Auto Refresh H H L L L H x x 3 Entry L 3 Refresh Self L H H H 3 Refresh i e Exit L H H X X X x x 3 Bank Active amp Row Addr H X L L H H X V Row Address Auto Precharge Disable L Column 4 Read amp H x L H L H xX V Address Column Address Auto Precharge Enable H Ao As Bie i Auto Precharge Disable L Column 4 Write amp H x L H L L X V Address Column Address Auto Precharge Enable H AAs 4 5 Burst Stop H X L H H L X 6 Bank Selection V L xX L L H L xX X Frecharge Both Banks H X H H X X X Clock Suspend or Entry H L X X Active Power Down L V V V Exit L H X X X X X H X X X Entry H L x Precharge Power L H H H x Down Mode i X y 7 Exit L H x V V V DQM H X V X 7 No Operation Command H x H X X X x x L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 BAo BA1 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refres
3. 128MB 20 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 Transcend information Inc 10 TS32MSS64V6G 144PIN PC133 Unbuffered SO DIMM 256MB With 16MX16 CL3 62 SPD Data Revision Code VER1 2 12 63 Checksum for Bytes 0 62 BA BA 64 71 Manufacturers JEDEC ID Dode per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 33 32 4D 53 73 90 Manufacturers Part Number TS32MSS64V6G 53 36 34 56 36 47 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 28 amp 3 Clock 0 1 C6 128 Unused Storage Locations Open FF Transcend information Inc 11
4. 76 Vss 124 DQ57 29 AO 77 CB2 125 DQ26 30 A3 78 CB6 126 DQ58 31 A1 79 CB3 127 DQ27 32 A4 80 CB7 128 DQ59 33 A2 81 Vcc 129 Vcc 34 A5 82 Vcc 130 Vcc 35 Vss 83 DQ16 131 DQ28 36 Vss 84 DQ48 132 DQ60 37 DQ8 85 DQ17 133 DQ29 38 DQ40 86 DQ49 134 DQ61 39 DQ9 87 DQ18 135 DQ30 40 DQ41 88 DQ50 136 DQ62 41 DQ10 89 DQ19 137 DQ31 42 DQ42 90 DQ51 138 DQ63 43 DQ11 91 Vss 139 Vss 44 DQ43 92 Vss 140 Vss 45 Vcc 93 DQ20 141 SDA 46 Vcc 94 DQ52 142 SCL 47 DQ12 95 DQ21 143 Vcc 48 DQ44 96 DQ53 144 Vcc Please refer Block Diagram Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6G 256MB With 16MX16 CL3 Block Diagram ICS1 ICSO ICS ICS ICS DM0 Ww DM DM DM2 vw DM Q0 w 1 00 H 1 08 DQ 16 aw 1 00 DOL w 101 09 DO 17 aw 1 01 Q2 w 1 02 H 1 0 10 DQ 18 aw 1 02 Q3 WH 1 03 0 11 DQ 19 aw 1 03 Q4 WH 1 04 H 1 0 12 DQ 20 aw 104 Q5 AW 1 05 1013 DQ 21 wr 1 05 Q6 WH 1 06 0 14 Q22 1 06 Q7 WH 1 07 10 15 Q BWA 1 07 Ul US U3 DM4 WN DM DM DM6 W DM DQ 32 W _ 1 08 0 0 DQ 48 VW _ 1 0 8 DQ 33 WN 1 09 0 DQ49 WS 1 09 DQ 34 V 1 0 10 H 102 DQ50 W _ 1 0 10 DQ 35 WM 1 0 11 103 DQ 51 V 1 011 DQ 36 W _ 1 012 H 1 0 4 DQ 52 WN 1 0 12 DQ37 WY 1 013 0 5 DQ 3 WH 1 013
5. Select Input RAS Row address strobe ICAS Column address strobe WE Write Enable DQM0 7 DQM Vcc Power Supply Vss Ground SDA Serial Address Data I O SCL Serial Clock NC No Connection Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6G 256MB With 16MX16 CL3 Dimension Ohm Prt he PCB 09 6757 Side Millimeters Inches A 67 60 0 200 2 661 0 008 B 32 80 1 291 C 23 20 0 913 D 4 60 0 181 E 3 30 0 130 F 2 50 0 098 G 4 00 0 157 H 6 00 0 236 20 00 0 787 J 29 21 0 200 1 150 0 008 K 1 00 0 100 0 039 0 004 Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6G 256MB With 16MX16 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 Vss 49 DQ13 97 DQ22 02 Vss 50 DQ45 98 DQ54 03 DQO 51 DQ14 99 DQ23 04 DQ32 52 DQ46 100 DQ55 05 DQ1 53 DQ15 101 Vcc 06 DQ33 54 DQ47 102 Vcc 07 DQ2 55 Vss 103 A6 08 DQ34 56 Vss 104 A7 09 DQ3 57 CBO 105 A8 10 DQ35 58 CB4 106 BAO 11 Vcc 59 CB1 107 Vss 12 Vcc 60 CB5 108 Vss 13 DQ4 61 CLKO 109 AQ 14 DQ36 62 CKEO 110 BA1 15 DQ5 63 Vcc 111 A10 16 DQ37 64 Vcc 112 A11 17 DQ6 65 RAS 113 Vcc 18 DQ38 66 CAS 114 Vcc 19 DQ7 67 WE 115 DQM2 20 DQ39 68 CKE1 116 DQM6 21 Vss 69 CSO 117 DQM3 22 Vss 70 A12 118 DQM7 23 DQMO 71 1CS1 119 Vss 24 DQM4 72 A13 120 Vss 25 DQM1 73 NC 121 DQ24 26 DQM5 74 CLK1 122 DQ56 27 Vcc 75 Vss 123 DQ25 28 Vcc
6. in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccD min 1 CLK 3 Number of valid output data 2 ea 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6G 256MB With 16MX16 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Unit Note Min Max CLK cycle time tcc 7 5 1000 ns 1 SLK yaa tsac 5 4 ns 1 2 output delay Output data hold time tOH 3 0 ns 2 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output in Hi Z tSHZ 5 4 ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter
7. voo 3 3V TA 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance A0 A12 BAO BA1 CIN1 25 45 pF Input capacitance RAS CAS WE CIN2 25 45 pF Input capacitance CKEO CKE 1 CIN3 15 25 pF Input capacitance CLKO CLK1 CIN4 15 21 pF Input capacitance CSO CS1 CIN5 15 25 pF Input capacitance DQM0 DQM7 CIN6 10 12 pF Data input output capacitance DQ0 DQ63 COUT 10 12 pF Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS32MSS64V6G 256MB With 16MX16 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note l Burst Length 1 Operating Curent Ioct tRC gt tRC min 740 mA 1 One Bank Active loL OmA Precharge Standby Current CC2P CKEs lt ViL max tcc 10ns 16 a in power down mode Icc2PS CKE amp CLK lt ViL max tcc 16 Icc2N CREE Vine E SZV ee 128 Precharge Standby Current Input signals are changed one time during 20ns w in non power down mode CKE gt VIH MmIn CLK lt ViL max tec Icc2NS 112 Input signals are stable Active Standby Current Icc3P CKE lt VIL max tcc 10ns 48 ies in power down mode Icc3PS CKE amp CLK lt ViL max tcc lt 48 Icc3N CRE Vintnin a iea 10ns 280 Active Standby Current Input signals are changed one time during 20ns in non power down mode x lt 2 mA One Bank Active Icc3NS PAA ee 240 Inp
8. Q38 WN 1 0 14 0 6 DQ 54 WM 1 0 14 Q39 W _ 1 0 15 07 DQ55 W _ 1 0 15 ICS ICS ICS ICS DM1 WY DM DI DM3 W 4 DM D DQ8 v 0 108 Dem 100 108 DQ9 v 101 H 1 09 D 25 w 1 01 0 9 DQ 10 W _ 102 O 10 DO 2 W _ 1 0 2 1010 DQ UW 1 03 JO 1l DO27 W _ 1 03 1011 12M 1 04 JO 12 w 1 04 10 12 DQ 1 WH 1 05 H 1 0 13 OO A 105 1013 DQ 14W 1 06 1014 DO30 VW _ 1 0 6 10 14 Q 15 WS 1 07 0 15 DQ 31 W 1 07 0 15 U2 U6 U4 U8 DM5 WS DM D DM7 w DM D DQ 40 vw 108 0 0 DQ 56 WM 1 08 10 0 DQ 41 w 1 09 O Q 57 WM 1 09 O DO a2 Ww 1 010 J02 DO 58 w 1 010 10 2 DOB 1 011 1 03 DQ 59 WN 1 011 103 DO 44 wW _ 1 0 12 10 4 DQ 60 WM 1 0 12 10 4 D 45 WW 1 013 H vos DQ 61 W 1 013 105 DO 46 VW 1 0 14 0 6 DQ 62 W 1 0 14 106 DQ 47 VW 1 015 107 DQ 63 WW 1 0 15 107 A0 A12 ww U1 U8 BAOQ BA1 w gt U1 U8 CKEO w gt U1 U4 SCL SDA CKE w gt U5 U8 RAS w gt U1 U8 ICAS w gt U1 U8 IWE w gt U1 U8 gt Pat CK U1 U4 VDD VDDQ gt U1 U8 a CK1 US U8 olu Note VSS gt Ul U8 1 DQ resistors 10 Ohms 5 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Tra
9. TS32MSS64V6G 144PIN PC133 Unbuffered SO DIMM 256MB With 16MX16 CL3 Description The TS32MSS64V6G Dynamic RAM high density memory module The TS32MSS64V6G consists of 8 pieces of CMOS 16Mx16bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 144 pin printed circuit board The TS32MSS64V6G is a Dual In Line Memory Module and is intended for mounting into is a 32Mx64 Synchronous 144 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Burst Mode Operation e Auto and Self Refresh e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock e DRAM Brand Promos e Operating Temperature TA 0 70 C Pin Identification Symbol Function A0 A12 Address inputs BAO BA1 Select Bank DQ0 DQ63 Data inputs outputs CLKO CLK1 Clock Input CKEO CKE1 Clock Enable Input CS0 CS1 Chip
10. h of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 is ignored and all banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc TS32MSS64V6G Serial Presence Detect Specification 144PIN PC133 Unbuffered SO DIMM 256MB With 16MX16 CL3 Serial Presence Detect
11. nscend information Inc TS32MSS64V6G ABSOLUTE MAXIMUM RATINGS 144PIN PC133 Unbuffered SO DIMM 256MB With 16MX16 CL3 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 8 W Short circuit current los 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V IOH 2MA Output low voltage VOL 0 4 V IOL 2MA Input leakage current ILI 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt Vin lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri state output CAPACITANCE
12. ut signals are stable IOL 0 mA eee ia loc4 Page Burst 860 mA 1 tcecp 2CLKs Refresh current Icc5 tRC 2 tRc min 1000 mA 2 Self Refresh Current ICC6 CKE lt 0 2V 24 mA Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Transcend information Inc 144PIN PC133 Unbuffered SO DIMM 256MB With 16MX16 CL3 TS32MSS64V6G AC OPERATING TEST CONDITIONS voo 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 3 3V 1200 Ohm Output Von DC 2 4V loH 2MA Vo DC 0 4V loL 2mA 50pF 870 Ohm Output O 20500A Vtt 1 4V 50 Ohm 50pPF e Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time etal o ns tRAS max 100 us Row cycle time Operation tRC min 65 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data
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