Transcend 256MB DDR266 ECC Unbuffer Memory
Contents
1. opam f annn o gt to o H gt gt ec lt F gt PCB 09 1677 Transcend Information Inc TS32MLD 2V6F5 184PIN DDR266 ECC Unbuffered DIMM 256MB With 32Mx8 CL2 5 Dimensions Side A I O n m O JO W Millimeters 133 35 0 20 72 39 6 35 2 20 30 48 0 20 19 80 4 00 12 00 1 27 0 10 Refer Placement Inches 5 250 0 008 2 850 0 250 0 087 1 200 0 008 0 779 0 157 0 472 0 050 0 004 Pin Identification Symbol Function AO A12 BAO BA1 Address input DQ0 DQ63 CB0O CB7 Data Input Output DQS0 DQS8 Data strobe input output CKO CKO CK1 CK1 CK2 CK2 Clock Input CKEO Clock Enable Input CSO Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe IWE Write Enable DM0 DM8 Data in Mask VDD 2 5 Voltage power supply VDDQ 2 5 Voltage Power Supply for DQS VREF Power Supply for Reference 2 5 Voltage Serial EEPROM Power VDDSPD Supply SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection Transcend Information Inc TS32MLD 2V6F5 Pinouts Pin No Name VREF 02 DQO 03 VSS 04 DQ1 05 DQSO 06 DQ2 07 VDD 08 DQ3 09 NC 10 NC 11 VSS 12 DQ8 13 DQ9 14 DQS1 15 VDDQ 16 CK1 17 CK1 18 VSS 19 DQ10 20 DQ11 21 CKEO 22 VDDQ 23 DQ16 24 DQ17 25 DQS2 26 VSS 27 A9 28 DQ18 29 A7 30 VDDQ 31 DQ19 32 A5 33 DQ24 34 VSS 35 DQ252. 36 DQS3 37 A4 38 VDD 39 DQ26 40 DQ27 41 A2 42 VSS 43 A1 44 CBO 45 CB1 46 VDD Pin Name DQS8 AO CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BAO DQ35 DQ40 VDDQ IWE DQ41 ICAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS ICK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 184PIN DDR266 ECC Unbuffered DIMM 256MB With 32Mx8 CL2 5 Name VSS DQ4 DQ5 VDDQ DMO DQ6 DQ7 Pin 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Name VSS DM8 A10 CB6 VDDQ CB7 VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 RAS DQ45 VDDQ CSO CS1 DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 A13 VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SAO SA1 SA2 VDDSPD Please refer Block Diagram Transcend Information Inc TS32MLD 2V6F5 256MB 184 PIN DDR266 DDR SDRAM DIMM With 32Mx8 2 5VOLT Block Diagram IC80 DESO DOs4 DMO DM4 DM CS DOS DQ 1100 DGS ENSI Be DOB DOS yos Ul Bese DO 104 DO37 DOs 105 DOB3 DOO 106 DOB36 DO 107 DOB DQSI DOSS DMI DMs ICS DOS Dal Det D DOW DOIS DB DOI U2 DOR DOI DAI DOI DOI DO DOD DO DOM DQS2 DQS6 DM2 il DM6 DM CS DQS DQ19 W 1 00 DQ5I D3 AW 101 D DQW2 W 1O02 U3 DQ55 DOB AWM
3. Voltage on any pin relative to Vss VIN VOUT 0 5 3 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 3 6 V Storage temperature TSTG 55 150 C Power dissipation PD 13 5 W Short circuit current los 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Max Unit Note Supply voltage VDD 2 3 2 7 V I O Supply voltage VDDQ 2 3 2 7 V I O Reference voltage VREF Voba 2 50mV Vpba 2 50mV V 1 I O Termination voltage VTT VREF 0 04 VREF 0 04 V 2 Input logic high voltage VIH DC VREF 0 15 VDDQ 0 3 V 4 Input logic low voltage VIL DC 0 3 VREF 0 15 V 4 Input Voltage Level CK and CK inputs VIN DC 0 3 VDDQ 0 3 V Input Differential Voltage CK and CK inputs VID DC 0 3 VDDQ 0 6 V 3 Input crossing point voltage CK and CK inputs VIX DC 1 15 1 35 V 5 Input leakage current lI 2 2 uA Output leakage current lOZ 5 5 uA Output High Current Normal strength driver IOH 16 8 mA VOUT VTT 0 84V Output Low Current Normal strength driver IOL 16 8 mA VOUT VTT 0 84V Output High Current Half strength
4. Operand Code AO A12 amp BAO BA1 Program keys EMRS MRS 2 EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS 3 Auto refresh functions are same as the CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAO BA1 Bank select addresses If both BAO and BA1 are Low at read write row active and precharge bank A is selected If both BAO is High and BA1 is Low at read write row active and precharge bank B is selected If both BAO is Low and BA1 is High at read write row active and precharge bank C is selected If both BAO and BA1 are High at read write row active and precharge bank D is selected 5 If A10 AP is High at row precharge BAO and BA1 are ignored and all banks are selected 6 During burst write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 This combination is not defined for any function which means No Operation NOP in DDR SDRAM Co eo Transcend Information Inc 9 256MB 184 PIN DDR266 DDR SDRAM TS32MLD 2V6F5 DIMM With 32Mx8 2 5VOLT Serial Presence Detect Speci
5. 1 5 00 27 Minimum Row Precharge Time tRP 20ns 50 28 Minimum Row Active to Row Activate delay tRRD 15ns 3C 29 Minimum RAS to CAS Delay tRCD 20ns 50 30 Minimum active to Precharge time tRAS 45ns 2D 31 Module ROW density 256MB 40 32 Command Address Input Setup Time 0 9ns 90 33 Command Address Input Hold Time 0 9ns 90 34 Data Signal Input Setup Time 0 5ns 50 35 Data Signal Input Hold Time 0 5ns 50 36 61 Superset Information 00 62 SPD Data Revision Code 00 Transcend Information Inc 10 256MB 184 PIN DDR266 DDR SDRAM TS32MLD 2V6F5 DIMM With 32Mx8 2 5VOLT 63 Checksum for Bytes 0 62 D1 64 71 Manufacturers JEDEC ID Transcend 7F 4F 72 Manufacturing Location T 54 54 53 33 32 4D 4C 73 90 Manufacturers Part Number TS32MLD72V6F5 44 37 32 56 36 46 35 20 20 20 20 20 91 92 Revision Code z 7 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific Data 128 255 Unused Storage Locations Undefined Transcend Information Inc 11
6. 103 DOs DQ1I W 1 04 DQ53 DOW 105 DQ52 DQI6 W 1 06 po49 DQ0 W 107 D4 DQS3 DQS7 DM3 j DM7 DM CS DQS DRI w v00 DQ59 DQ27 W 1O01 DQ63 DQ26 w 102 U4 DQ58 DQO w 103 DQ62 DQI W _ 1104 DQ57 DQ25 w 105 DQ56 DQ28 w 106 DQ DQ24 w 107 DQ DQS8 DM8 il VDD VDDQ CS DQS CB7 CB3 CB6 CB2 US CBI CBO U4 U1 U7 CBS CB4 Cap Cap Cap BAO BA 120 1o Ww u pe A Aa naw p ua O2 ICLKO0 1 2 RAS W n U1 U9 ICAS W P U1 U9 IWE W 1 09 CKE0 U U9 U6 U3 U9 Cap Cap Cap Note all CLK cap are 1 5pf VDDSPD VREF US U2 U8 DM 100 I 01 102 1 03 1 04 I 05 1 06 CS DQS U6 EEPROM a Cs U1 U9 Note 1 U1 U9 are 32Mx8 DDR SDRAM 2 DQ DQS DM DQS resistances 220hm 3 BAx Ax RAS CAS WE resistances 3 30hm 4 All bypass cap are 0 luf except C58 Cap Cap Cap and C59 are 2 2uf m EEPROM L SAO SAI SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 256MB 184 PIN DDR266 DDR SDRAM TS32MLD 2V6F5 DIMM With 32Mx8 2 5VOLT ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit
7. 45 0 55 tCK Clock low level width tCL 0 45 0 55 tCK DQS out access time from CK CK tDQSCK 0 75 0 75 ns Output data access time from CK CK tAC 0 75 0 75 ns Data strobe edge to output data edge tDQSQ 0 5 ns Read Preamble tRPRE 0 9 1 1 tCK Read Postamble tRPST 0 4 0 6 tCK CK to valid DQS in tDQSS 0 75 1 25 tCK DQS in setup time tWPRES 0 ns 2 DQS in hold time tWPREH 0 25 tCK DQS falling edge to CK rising setup time tDSS 0 2 tCK DQS falling edge from CK rising hold time tDSH 0 2 tCK DQS in high level width tDQSH 0 35 tCK DQS in low level width tDQSL 0 35 tCK DQS in cycle time tDSC 0 9 1 1 tCK Address and Control input setup time tIS 0 9 ns Address and Control input hold time tlH 0 9 ns Data out high impedance time from CK CK tHZ 0 75 0 75 ps Data out low impedance time from CK CK tLZ 0 75 0 75 ns Mode register set cycle time tMRD 15 ns DQ amp DM setup time to DQS tDS 0 5 ns DQ amp DM hold time to DQS tDH 0 5 ns DQ amp DM input pulse width tDIPW 1 75 ns Exit self refresh to read command tXSRD 200 tCK Refresh interval time tREF 7 8 us 1 l tCLmin or ns Clock half period tHP tCHmin DQS write postamble time tWPST 0 4 0 6 tCK 3 Note 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case shown DQS going from High_Z to logic Low applies when no writes were previously in progress on the bus If a previous write was in progress DQS could be High at this time depe
8. S inputs changing twice per clock cycle Address and control inputs changing once per clock cycle Operating current One bank Active Read Precharge Burst 2 tRC tRC min CL 2 5 tCK tCK min VIN VREF fro DQ DQS and DM Percharge power down standby current All banks idle power down mode CKE lt VIL max tCK tCK min IDD2P 252 mA VIN VREF for DQ DQS and DM Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min tCK 133Mhz for DDR266 Address and other control inputs changing once per clock cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode CKE lt VIL max tCK tCK min IDD3P 405 mA VIN VREF for DQ DQS and DM Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax tCK tCK min DQ DQS and DM inputs changing twice per clock cycle address and other control inputs changing once per clock cycle IDDO 1035 mA IDD1 1350 mA IDD2F 450 mA IDD3N 585 mA Operating current burst read Burst length 2 reads continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at IDD4R 1980 mA tCK tCK min 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at tCK
9. TS32MLD 2V6F5 184PIN DDR266 ECC Unbuffered DIMM 256MB With 32Mx8 CL2 5 Description The TS32MLD72V6F5 is a 32Mx72bits Double Data Rate SDRAM high density for DDR266 The TS32MLD72V6F5 consists of 9pcs CMOS 32Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages and a 2048 bits serial EEPROM on a 184 pin printed circuit board The TS32MLD72V6F5 is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e ROHS compliant products e Burst Mode Operation e Auto and Self Refresh e All inputs except data amp DM are sampled at the positive going edge of the system clock ck e Data I O transactions on both edge of data strobe e Edge aligned data output center aligned data input e Serial Presence Detect SPD with serial EEPROM e SSTL 2 compatible inputs and outputs e Single 2 5V 0 2V power supply CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Placement e ge VV TUT w
10. driver IOH 9 mA VOUT VTT 0 45V Output High Current Half strength driver IOL 9 mA VOUT VTT 0 45V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 VID is the magnitude of the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relation to a VREF envelop that has been bandwidth limited to 200MHZ 5 The value of Vix is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same Transcend Information Inc 5 256MB 184 PIN DDR266 DDR SDRAM TS32MLD 2V6F5 DIMM With 32Mx8 2 5VOLT DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Parameter Symbol Max Unit Note Operating current One bank Active Precharge tRC tRCmin tCK tCK min DQ DM and DQ
11. fication Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type DDR SDRAM 07 3 of Row Addresses on this Assembly 13 oD 4 of Column Addresses on this Assembly 10 OA 5 of Module Rows on this Assembly 1 bank 01 6 Data Width of this Assembly 72bits 48 7 Data Width of this Assembly 0 00 8 VDDQ and Interface Standard of this Assembly SSTL 2 5V 04 9 DDR SDRAM Cycle Time at CAS Latency 2 5 7 5ns 75 10 DDR SDRAM Access Time from Clock at CL 2 5 0 75ns 75 11 DIMM configuration type non parity Parity ECC ECC 02 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary DDR SDRAM Width X8 08 14 Error Checking DDR SDRAM Width X8 08 Min Clock Delay for Back to E 13 Back Random Column Address eee a 16 Burst Lengths Supported 2 4 8 OE 17 of banks on each DDR SDRAM device 4 bank 04 18 CAS Latency supported 2 2 5 oC 19 CS Latency 0 CLK 01 20 WE Latency 1 CLK 02 Registered address amp 21 DDR SDRAM Module Attributes control inputs and 20 on card DLL 22 DDR SDRAM Device Attributes General HOE otage 00 tolerance 23 DDR SDRAM Cycle Time CL 2 0 10ns AO 24 DDR SDRAM Access from Clock CL 2 0 0 75ns 75 25 DDR SDRAM Cycle Time CL 1 5 00 26 DDR SDRAM Access from Clock CL
12. nding on tDQSS 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly Transcend Information Inc g 256MB 184 PIN DDR266 DDR SDRAM TS32MLD 2V6F5 DIMM With 32Mx8 2 5VOLT SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND CKEn 1 CKEn CS RAS CAS WE BAo 1 A1o AP Ao Ag A11 A12 Note Extended Register Mode Register Set H X L L L L OP CODE 1 2 Register Mode Register Set X L L L L OP CODE 1 2 Auto Refresh H L L L H x 3 Entry L 3 Refresh Self L H H H 3 Refresh i Exit L H H X X X X 3 Bank Active amp Row Addr H X L L H H V Row Address Auto Precharge Disable L Col 4 Read amp ger H x IL H Lln v Address Column Address Auto Precharge Enable H Ao A10 4 5 i Auto Precharge Disable L Col 4 Write amp y g H x L H L L v Address Column Address Auto Precharge Enable H Ao Ato 4 5 Burst Stop H X L H H L X 6 Bank Selection V L Precharge All Banks H X L L H L X H X Entry H Le eR Xa n X Active Power Down L V V V X Exit L H X X X X H X X X Entry H L Precharge Power L H H H Down Mode A H X X X Exit L H L V V V DM H X X 7 H X X X No Operation Command H X X L H H H Note 1 OP Code
13. tCK min DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst IDD4W 2655 mA Auto refresh current tRC tRFC min IDD5 1980 mA Self refresh current CKE lt 0 2V IDD6 27 mA Operating current Four bank operation Four bank interleaving with BL 4 IDD7 3555 mA Refer to the following page for detailed test condition Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Transcend Information Inc 6 256MB 184 PIN DDR266 DDR SDRAM TS32MLD 2V6F5 DIMM With 32Mx8 2 5VOLT AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Note Input High Logic 1 Voltage DQ DQS and DM signals VIH AC VREF 0 31 V 3 Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 31 V 3 Input Differential Voltage CK and CK inputs VID AC 0 7 VDDQ 0 6 V 1 Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 0 5 VDDQ 0 2 V 2 Note 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device and must track variations in the DC level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are rela
14. tion to a VREF envelope that has been bandwidth limited 20MHz AC OPERATING TEST CONDITIONS VDD 2 5 VDDQ 2 5 TA 0 to 70 C v nput timing measurement reference level Output timing measurement reference level VTT Output load condition See Load Circuit VIT 0 5 VDDQ mrs ZO 50o0hm 0 5 VDDQ CLoap 30pF Output Load circuit Input Output CAPACITANCE Von 2 5V Vppa 2 5V TA 25 C f 1MHz Parameter Input capacitance AO A12 BAO BA1 RAS CAS WE Input capacitance CKE0 Input capacitance CSO Input capacitance CKO CK2 Input capacitance DMO DM8 Data and DQS input output capacitance DQ0 DQ63 Data input output capacitance CBO CB7 Transcend Information Inc 7 256MB 184 PIN DDR266 DDR SDRAM TS32MLD 2V6F5 DIMM With 32Mx8 2 5VOLT AC Timing Parameters amp Specifications These AC characteristics were tested on the Component Parameter Symbol Min Max Unit Note Row cycle time tRC 65 ns Refresh row cycle time tRFC 75 ns Row active time tRAS 45 120K ns RAS to CAS delay tRCD 20 ns Row active to Row active delay tRP 20 ns Row active to Row active delay tRRD 15 ns Write recovery time tWR 15 ns Last data in to Read command tWTR 1 tCK Col Address to Col Address delay tCCD 1 tCK Clock cycle time tCK 7 5 ns Clock high level width tCH 0
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