Transcend 256MB SDRAM PC100 Unbuffer Non-ECC Memory
Contents
1. ICSO ICS ICS D7 o DQO D39 o Dao D6 o Da U1 D38 O Dai U5 D5 o DQ2 yms D37 o DQ2 song D3 o D4 D35 o Da4 D2 o DQ5 D34 o DQ5 D1 o Dae D33 O Dae Do o DOQ 3 D32 o DQ Q Q DQMO DQM4 AO An gt o gt _U0 U7 ICS ICS BAO amp 1 D15 o DQO D47 o Dao IRAS o __U0 U7 D14 o Da1 u2 D46 o DQ1 u6 D13 O DQ2 yxs D45 Oo DQ2 sone E sae D12 O DQ3 SDRAM D44 O DQ3 gpram 2 a D11 o D4 D43 o Da4 D10 o pas D42 o Das WE O __U0 U7 D9 o D _ D41 O D _ D8 o DQ7 D40 oJ DQ7 O lod g g CKEO U0 U7 bam o_ Dams o 10 ohm Every DQ Dn o _ gt pin of ICS1 O t SDRAM ICS ics VDD one 0 33uF Capacitors D23 o DQO D55 o Dao per each SDRAM D22 o DaI U3 D54 O DaI U7 vesa O S D21 Oo DQ2 yxs D53 Oo DQ2 sone D20 o DQ3 SDRAM D52 Oo DQ3 SDRAM To all SDRAMs D19 o DO4 D51 o D4 D18 o DQ5 D50 o Das D17 o pas D49 o Dae E D16 O DQ D48 O DQ J Q Q U5 U7 Dom2o DaM6 o ITA CLK 0 2 U2 U4 ICS ICS D31 O DQO D63 o DQO U6 U8 D30 o Da1 V4 D62 o pa U8 D29 o DQ2 yms D61 o DQ2 yms D28 O DQ3 spram D60 O DQ3 gspram Serial EEPROM D27 o DQ4 D59 O j DQ4 SCL SCL SDA SDA D26 o Das D58 o DQ5 WP D25 Oo Dae D57 O Dae A0 AI _A2 D24 o DQ D56 o DQ 8 SA0 SA1 SA2 Q Q 47k ohm pa2. Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly A0 A12 oD 4 of Column Addresses on this Assembly A0 A9 OA 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 T Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 10ns AO 10 SDRAM Access from Clock highest CL 6ns 60 11 DIMM configuration type non parity ECC None 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width E 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 2 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Proe te tee 0E R W Burst 23 SDRAM Cycle Time 2 highest CL 10ns AO 24 SDRAM Access from Clock Qe highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 0 00 26 SDRAM Access from Clock 3 highest CL 0 00 27 Minimum Row Precharge Time 20 14 28 Minimum Row Active to Row Activate 20 14 29 Minimum RAS to CAS Delay 20 14 30 Minimum RAS Pulse Width 50 32 31 Density of Each Bank on Module 256MB 40 32 Command Addr
3. 45 ICS2 87 DQ33 129 CS3 04 DQ2 46 DQM2 88 DQ34 130 DQM6 05 DQ3 47 DQM3 89 DQ35 131 DQM7 06 Vcc 48 NC 90 Vcc 132 A13 07 DQ4 49 Vcc 91 DQ36 133 Vcc 08 DQ5 50 NC 92 DQ37 134 NC 09 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 Vcc 101 DQ45 143 Vcc 18 Vcc 60 DQ20 102 Vcc 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 Vref 104 DQ47 146 Vref 21 CBO 63 CKE1 105 CB4 147 REGE 22 CB1 64 Vss 106 CB5 148 Vss 23 Vss 65 DQ21 107 Vss 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 Vcc 68 Vss 110 Vcc 152 Vss 27 IWE 69 DQ24 111 CAS 153 DQ56 28 DQMO 70 DQ25 112 DQM4 154 DQ57 29 DQM1 71 DQ26 113 DQM5 155 DQ58 30 CSO 72 DQ27 114 CS1 156 DQ59 31 NC 73 Vcc 115 RAS 157 Vcc 32 Vss 74 DQ28 116 Vss 158 DQ60 33 AO 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 Ad 161 DQ63 36 AG 78 Vss 120 A7 162 Vss 37 A8 79 CLK2 121 AQ 163 CLK3 38 A10 AP 80 NC 122 BAO 164 NC 39 BA1 81 NC 123 A11 165 SAO 40 Vcc 82 SDA 124 Vcc 166 SA1 41 Vcc 83 SCL 125 CLK1 167 SA2 42 CLKO 84 Vcc 126 A12 168 Vcc Please refer Block Diagram Transcend information Inc 3 TS32MLS64V8F2 168PIN PC100 Unbuffered DIMM 256MB With 32M X 8 CL2 Block Diagram
4. Unbuffered DIMM TS32MLS64V8F2 256MB With 32M X 8 CL2 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn cs RAS ICAS WE DQM Baoi AwiAP 10 N2 Note Register Mode Register Set H x L L L L x OP CODE 1 2 Refresh Auto Refresh H 3 Self Entry H L L B L H x x 3 Refresh Exit L H H H 3 L H H X X X x X 3 Bank Active amp Row Addr H x L L H H x v Row Address Read amp Auto Precharge Disable L Column 4 Column Address Auto Precharge Enable H X L H L H X V Address H Ao As 4 5 Write amp Auto Precharge Disable L Column 4 Column Address Auto Precharge Enable H X L H L L X V ple PE o A9 i Burst Stop H X L H H L X X 6 Precharge Bank Selection V L xX X Both Banks H X L b hi L X H Clock Suspend or Entry Active Power H L i x X X X Down L V V V X Exit L H x x x x x Precharge Power Entry H x x x Down Mode H L x L H H H X Exit H x x x L H X L V V V DQM H X V X 7 No Operation Command H X X X H i L H H H 3 X V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Transcend Ao A12 BAo BA1 Program keys MRS MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge wit
5. mA 2 Self Refresh Current ICC6 CKE lt 0 2V 24 mA Note 1 Measured with outputs open 2 Refresh period is 64ms Transcend information Inc 6 TS32MLS64V8F2 168PIN PC100 Unbuffered DIMM 256MB With 32M X 8 CL2 AC OPERATING TEST CONDITIONS Vpp 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 O 3 3V Vit 1 4V Output N OCN A Output O 6 Z0 50 Ohm o hr he ahr Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 20 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time IRAS min 28 ns l tRAS max 100 us Row cycle time tRc min 70 ns 1 Last data in to new col Address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to Active delay tDAL 2CLK 20ns 5 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tcCD min 1 CLK 3 Number of valid CAS latency 2 1 ea 4 output data Note 1 The minimum number of clock cycles is determined by dividing th
6. 168PIN PC100 Unbuffered DIMM TS32MLS64V8F2 256MB With 32M X 8 CL2 Description Placement The TS32MLS64V8F2 is a 32M x 64bits Synchronous Dynamic RAM high density for PC 100 CL2 The j TS32MLS64V8F2 consists of 8pcs CMOS 32Mx8 bits Synchronous DRAMSs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS32MLS64V8F2 is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies A programmable latencies allow the same device to be T useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 100 CL2 D e Conformed to JEDEC Standard Spec y fPeo fF CG e 33 554 432 words x 64 bits organization E e Burst Mode Operation C e Auto and Self Refresh i e CKE Power Down Mode po TAA Ye m e DQM Byte Masking Read Write E E ce e e S
7. 8F2 Pet ee eae CAPACITANCE TA 25 C f 1MHz Symbol ee po jo s Input capacitance Ao A12 BAo BA1 Input capacitance RAS CAS WE Input capacitance CKEO Input capacitance CLKO CLK2 Input capacitance CSO CS2 Input capacitance DQM0 DQM7 Data input output capacitance DQ0 DQ63 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition CAS Latency Value Unit Note Operating Current pe Burst Length 1 a A i i m One Bank Active IRESIRGNMIN loL OmA Precharge Standby Current ICc2P___ CKE lt VIL max tcc 10ns 16 HA in power down mode Icc2PS CKE amp CLK lt VIL max tcc 16 CKE ViH min CS gt VIH min tcc 10ns Icc2N Input signals are changed one time during 30ns 160 Precharge Standby Current mA in non power down mode i a Icc2NS TEE sae CLK lt VIL max tcc 80 nput signals are stable Active Standby Current Icc3P CKE lt VIL max tcc 10ns 48 mA in power down mode Icc3PS CKE amp CLK lt ViL max tcc 48 CKE ViH min CS gt VIH min tcc 10ns 240 IcC3N _ input signals are changed one time during 30ns Active Standby Current mA in non power down mode One Bank Active CKE gt ViH min CLK lt VIL max tcc lt 200 ICC3NS _ input signals are stable IOL 0 mA Operating Current Icc4 Page Burst mA 1 Bust Mod 2 800 ARENE tceco 2CLKs Refresh Current ICC5 tRC tRC min 1 520
8. e minimum time required with clock cycle time and then rounding off to the next higher integer ORUN Minimum delay is required to complete write All parts allow every cycle column address change In case of row precharge interrupt auto precharge and read burst stop For CL 2 tRDL 1CLK and tDAL 1CLK 20Ons is also supported Transcend recommends tRDL 2CLK and tDAL 2CLK 20ns Transcend information Inc 168PIN PC100 Unbuffered DIMM TS32MLS64V8F2 256MB With 32M X 8 CL2 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Unit Note Min Max CLK cycle time CAS latency 2 tcc 10 1000 ns 1 CLK to valid CAS latency 2 tSAC 6 ns 1 2 output delay Output data CAS latency 2 tOH 3 ns 2 hold time CLK high pulse width tCH 3 ns 3 CLK low pulse width tCL 3 ns 3 Input setup time tss 2 ns 3 Input hold time tSH 1 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output Hee CAS latency 2 tSHZ 6 ns in Hi Z Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 168PIN PC100
9. erial Presence Detect SPD with serial EEPROM on e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply A e MRS cycle with address key programs Latency Access from column address PCB 09 7309 Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock Transcend information Inc l TS32MLS64V8F2 168PIN PC100 Unbuffered DIMM 256MB With 32M X 8 CL2 Pin Identification Symbol Function AO A12 BAO BA1 Address input Dimensions Side Millimeters Inches 133 35 0 40 5 250 0 016 B 65 67 2 585 C 23 49 0 925 D 8 89 0 350 E 3 00 0 118 F 31 75 0 20 1 250 0 008 G 19 80 0 788 H 15 80 0 622 1 27 0 10 0 050 0 004 Refer Placement Transcend information Inc DQ0 DQ63 Data Input Output CLKO CLK2 Clock Input CKEO Clock Enable Input CSO CS2 Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe IWE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Volt Power Supply Vss Ground NC No Connection 168PIN PC100 Unbuffered DIMM TS32MLS64V8F2 256MB With 32M X 8 CL2 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 DQO 44 NC 86 DQ32 128 CKEO 03 DQ1
10. ess Setup Time 2ns 20 33 Command Address Hold Time ins 10 34 Data Signal Setup Time 2ns 20 35 Data Signal Hold Time ins 10 36 61 Superset Information 00 62 SPD Data Revision Code Version 1 2 12 63 Checksum for Bytes 0 62 39 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 33 32 4D 4C 73 90 Manufacturers Part Number TS32MLS64V8F2 53 36 34 56 38 46 32 20 20 20 20 20 Transcend information Inc 10 168PIN PC100 Unbuffered DIMM TS32MLS64V8F2 256MB With 32M X 8 CL2 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 2 A6 128 Unused Storage Locations Open FF Transcend information Inc 11
11. hout row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 is ignored and both banks are selected During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 information Inc 9 TS32MLS64V8F2 Serial Presence Detect Specification 168PIN PC100 Unbuffered DIMM 256MB With 32M X 8 CL2 Serial Presence Detect
12. m3o pam7 o This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 168PIN PC100 Unbuffered DIMM TS32MLS64V8F2 256MB With 32M X 8 CL2 ABSOLUTE MAXIMUM RATINGS Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Symbol Min Typ Max Unit Note Supply voltage VoD Input high voltage Vi Input low voltage vw os o o8 v Output high voltage vow 24 v ton 2ma Output low voltage VOL iS E a ee ee IOL 2mA 8 a ua 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs Transcend information Inc 5 TS32MLS64V
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