Transcend 512MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory
Contents
1. Parameter Symbol Test Condition CAS Latency Value Typ Unit Note Operating Current Burst Length 1 One Bank Active ie REIN loL 0mA Precharge Standby Current CC2P CKExViL max tcc 12ns 16 vA in power down mode Icc2PS_ CKE amp CLK lt ViL max tcc CKE ViH min CS ViH min tcc 12ns ICC2N Input signals are changed one time during 20ns 320 Precharge Standby Current mA in non power down mode gt CLK ViL max tec ICC2NS P nput signals are stable Active Standby Current Icc3P CKE lt VIL max tcc 12ns 160 mA in power down mode IccaPS amp CLK lt ViL max tcc e Icc3N CKE ViH min CS ViH min tcc 12ns Active Standby Current Input signals are changed one time during 20ns 400 in non power down mode HA Icc3NS CKE ViH min CLK lt ViL max tec Input signals are stable loL 0 mA erie oe Icc4 Page Burst 3 1200 1 2CLKs 2 Refresh Current ICC5 tRC2tRC min 3 840 mA 2 Self Refresh Current ICC6 CKE lt 0 2V 48 mA Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap 6 Transcend information Inc TS64MSS64V6L 144PIN PC133 Unbuffered SO DIMM AC OPERATING TEST CONDITIONS VDD 3 3V 0 3V TA 0 to 65 C 512MB With 32M X 8 CL32. Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 o omy ES Ya DG A etm rur c d 7777 TT 77 Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit AC Characteristics TA 0 to 65 C VDD 3 3V 0 3V Vss 0V Parameter Symbol Value Unit Note System clock cycle time tck 7 5 ns 1 CK high pulse width tCKH 2 5 ns 1 CK low pulse width tcKL min 2 5 ns 1 Access time from CK tac 5 4 ns 1 2 Data out hold time toH 3 0 ns 1 2 CK to Data out low impedance Lz 0 0 ns 1 2 CK to Data out high impedance tHz 3 0 ns 1 Input setup time Tas tcs tos tcEs 1 5 ns 1 CKE setup time for power down exit tcEsP 2 0 ns 1 Input hold time tcH tDH tcEH 0 8 ns 1 Ref Active to Ref Active command period TRC min 70 0 ns 1 Active to precharge command period TRAS min 45 0 ns 1 Active command to column command same bank tRCD 20 0 ns 1 Precharge to active command period tRP 20 0 ns 1 Write recovery or data in to precharge lead time tDPL 15 0 ns 1 Active a to Active b command period tRRD 15 0 ns 1 Transition time rise and fall tr min 1 0 ns Refresh period TREF max 64 0 ms Note 2 Access time is measured at 1 5V Load condition is CL 50 pF Transcend information Inc 1 AC measurement assumes tT 1ns Reference level for
3. ICAS 32Mx8 Wwe SDRAM A0 A12 BA0 1 DQ0 DQ7 RAS EEPROM SCL SCL AO A1 SDA A2 144PIN PC133 Unbuffered SO DIMM A0 A12 BA0 1 DQ0 DQ7 RAS ICAS 32Mx8 WE SDRAM A0 A12 BA0 1 DQ0 DQ7 RAS ICAS 32Mx8 ICS CLK CKE A0 A12 BA0 1 DQ0 DQ7 RAS SDA 512MB With 32M X 8 CL3 A0 A12 BA0 1 DQ0 DQ7 RAS ICAS 32 8 wg SDRAM ICS CLK A0 A12 BA0 1 DQ0 DQ7 ICAS 32Mx8 A0 A12 BA0 1 DQ0 DQ7 RAS ICAS 32Mx8 A0 A12 BA0 1 DQ0 DQ7 ICAS 32Mx8 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS64MSS64V6L 512MB With 32M X 8 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 to 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 to 4 6 V Storage temperature TsTG 55 to 125 C Power dissipation PD 12 7 W Short circuit current los 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to rec
4. timing of input signals is 1 5V 144PIN PC133 Unbuffered SO DIMM TS64MSS64V6L 512MB With 32M X 8 CL3 SIMPLIFIED TRUTH TABLE e eee a n o ve vn s ri n Refresh Refresh Entry st aa Pht EE T Nm Column Address Ao As Bank Active amp Row Addr Read amp Auto Precharge Disable Column Address Auto Precharge Enable Bank Selection H Both Banks cnm x X ERES um Write amp Auto Precharge Disable Column Column Address Auto Precharge Enable z EIE H bebe bets Precharge Power Down Mode V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and prech
5. 64MSS64V6L 53 36 34 56 36 4C 20 20 20 20 20 20 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 amp 3 Clock 0 1 C6 128 Unused Storage Locations Open FE 10 Transcend information Inc
6. SA2 SCL SDA Vcc Vss NC Data Input Output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data DQ Mask Address in EEPROM Serial PD Clock Serial PD Add Data input output 3 3 Voltage Power Supply Ground No Connection Pin Identification Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS64MSS64V6L 512MB With 32M X 8 CL3 Dimension gt 09 2260 Millimeters Inches A 67 60 0 20 2 661 0 008 32 80 1 291 23 20 0 913 4 60 0 181 3 30 0 130 2 50 0 098 4 00 0 157 6 00 0 236 20 00 0 787 29 21 0 20 1 150 0 008 1 00 0 10 0 040 0 004 I m jo c Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS64MSS64V6L 512MB With 32M X 8 Pinouts Pin Pin Pin Pi Pin Pin Pin Pin Pin Pin No Name No No TR i TIR Name No Name 97 Please refer Block Diagram Transcend information Inc TS64MSS64V6L Block Diagram A0 A12 BAO BA1 D0 D63 RAS ICAS IWE CSO CLKO CKEO CLK1 ICS1 CKE1 A0 A12 BAO0 1 DQ0 DQ7 RAS ICAS 32Mx8 A0 A12 BA0 1 DQ0 DQ7 RAS ICAS 32Mx8 A0 A12 BAO0 1 ICAS 32Mx8 A0 A12 BA0 1 DQ0 DQ7 RAS A0 A12 BA0 1 DQ0 DQ7 A0 A12 BA0 1 DQ0 DQ7 RAS
7. TS64MSS64V6L 144PIN PC133 Unbuffered SO DIMM 512MB With 32M X 8 CL3 Description The TS64MSS64VEL is a 64M bit x 64 Synchronous Dynamic RAM Small Outline Dual In line Memory Module S O DIMM mounted 16 pieces of 256 Mbit SDRAM sealed in STSOP package and 1 piece of serial EEPROM 2 kbit for Presence Detect PD An outline of the products is 144 pin Zig Zag Dual tabs socket type compact and thin package Therefore they make high Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 e Conformed to JEDEC Standard 2 clocks e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock e DRAM brand Promos e Operating Temperature TA 0 70 C Function A0 A12 BAO BA1 Address input Symbol DQ0 DQ63 CLKO CLK1 CKEO CKE1 CS0 CS3 RAS ICAS NE DQM0 DQM7 SA0
8. arge bank D is selected If A10 AP is High at row precharge BAo BA1 is ignored and both banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc TS64MSS64V6L Serial Presence Detect Specification 144PIN PC133 Unbuffered SO DIMM 512MB With 32M X 8 CL3 Serial Presence Detect Byte No Function Described es ae Vendor Part 0 Number of Bytes Written into Serial Memory 128bytes 80 1 Total Number of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 Number of Row Addresses on this Assembly 13 OD 4 Number of Column Addresses on this Assembly 10 OA 5 Number of Module Banks on this Assembly 2 bank 02 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM co
9. nfiguration type non parity ECC Non parity 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width None 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 OF 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 amp 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General SUE UN OE 23 SDRAM Cycle Time 25 highest CL 10ns AO 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20 14 30 Minimum RAS Pulse Width 45ns 2D Transcend information Inc TS64MSS64V6L 144PIN PC133 Unbuffered SO DIMM 512MB With 32M X 8 CL3 31 Density of Each Bank on Module 1row of 256MB 40 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code Intel Ver1 2 12 63 Checksum for Bytes 0 62 53 64 71 Manufacturers JEDEC ID Dode per JEP 108E Transcend TF AF 72 Manufacturing Location T 54 54 53 36 34 40 53 73 90 Manufacturers Part Number TS
10. ommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 5 0 0 8 V 2 Output high voltage VOH 2 4 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current liL 10 10 uA 3 output leakage current loL 10 E 10 uA Note 1 VIH max 2 0V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs 4 Dout is disabled OV x Vour x VDDQ CAPACITANCE VDD 3 3V 0 3V 0 C 70 C Symb Mn Max Input capacitance Ao A12 BAo 1 Input capacitance RAS CAS Input capacitance CKEO CKE1 Input capacitance CLKO CLK3 Input capacitance 50 CS2 Input capacitance DQMO DQM7 Data input output capacitance DQ0 DQ63 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS64MSS64V6L 512MB With 32M X 8 CL3
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