Transcend 512MB DDR DDR400 Unbuffer Non-ECC Memory
Contents
1. A0 A12 AO A12 AO0 A12 AO A12 AO A12 BAO BA1 BAO BA1 BAO BA1 BAO BA1 DQ0 DQ63 ai DQ0 DQ7 me DQ7 DQ0 DQ7 RAS au RAS 32Mx8 ieee 32MX8 RAS 32Mx8 DDR CAS CAS_ SDRAM E Hr pHs E CSO ICS a CKEO DM1 DQs1 CK1 CK1 CKO CKO CK2 CK2 AO A12 AO0 A12 AO A12 BAO BA1 ai DQ0 DQ7 au RAS AO A12 A0 A12 BAO BA1 BAO BA1 a DQ0 DQ7 ae ane GRA SERRE CKO CKO Pp y O CK2 CK2 EHEHE A0 A12 X A0 A12 X A0 A12 X A0 A12 X BAO BA1 2 BAO BA1 Y BAO BA1 Q BA0 BA1 Q DQO0 DQ7 Ta eens X DQ0 DQ7 x Eea DQ7 X RAS RAS RAS RAS icas 3a oas PODR eas ee cas arate WE SDRAM mhe SDRAM Bis SDRANI me SDRAN CS Y Be oO mie N Mies oO cke 2 9 cke 2 Sticke 2 StL ycke g DM4 DM5 DM6 DM7 DQS4 DQS5 DQS6 DQS7 Serial EEPROM SCL SCL SDA SDA AO A1 A2 SAO SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 184PIN DDR400 Unbuffered DIMM TS64MLD64V4F 512MB With 32Mx8 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 0 5 3 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 3 6 V Storage temperat2. PCB 09 1670 Transcend Information Inc TS64MLD64V4F 184PIN DDR400 Unbuffered DIMM 512MB With 32Mx8 CL2 5 Pin Identification Symbol Function A0 A12 BAO BA1 Address input DQ0 DQ63 Data Input Output DQS0 DQS7 Data strobe input output CKO CKO CK2 CK2 Clock Input Dimensions Side Millimeters Inches A 133 35 0 20 5 250 0 008 B 72 39 2 850 C 6 35 0 250 D 2 20 0 087 E 31 75 0 20 1 250 0 008 F 19 80 0 779 G 4 00 0 157 H 12 00 0 472 1 27 0 10 0 050 0 004 Refer Placement Transcend Information Inc CKEO CKE1 Clock Enable Input CSO CS1 Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe INE Write Enable DMO DM7 Data in Mask VDD 2 5 Voltage power supply VDDQ 2 5 Voltage Power Supply for DQS VREF Power Supply for Reference VDDSPD 2 5 Voltage Serial EEPROM Power Supply SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection TS64MLD64V4F 184PIN DDR400 Unbuffered DIMM 512MB With 32Mx8 CL2 5 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 VREF 47 DQS8 93 VSS 139 VSS 02 DQO 48 AO 94 DQ4 140 DM8 03 VSS 49 CB2 95 DQ5 141 A10 04 DQ1 50 VSS 96 VDDQ 142 CB6 05 DQSO 51 CB3 97 DMO 143 VDDQ 06 DQ2 52 BA1 98 DQ
3. Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 VID is the magnitude of the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 5 The value of VIx is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same Transcend Information Inc 5 184PIN DDR400 Unbuffered DIMM TS64MLD64V4F 512MB With 32Mx8 CL2 5 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Parameter Symbol Max Unit Note Operating current One bank Active Precharge tRC tRCmin DQ DM and DQS inputs changing twice per clock cycle IDDO 1 440 mA Address and control inputs changing once per clock cycle Operating current One b
4. both BAO is Low and BA1 is High at read write row active and precharge bank C is selected If both BAO and BA are High at read write row active and precharge bank D is selected 5 If A10 AP is High at row precharge BAO and BA1 are ignored and all banks are selected 6 During burst write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 7 Burst stop command is valid at every burst length 8 DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 9 This combination is not defined for any function which means No Operation NOP in DDR SDRAM 10 184PIN DDR400 Unbuffered DIMM TS64MLD64V4F 512MB With 32Mx8 CL2 5 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type DDR SDRAM 07 3 of Row Addresses on this Assembly 13 oD 4 of Column Addresses on this Assembly 10 OA 5 of Module Rows on this Assembly 2 bank 02 6 Data Width of this Assembly 64ts 40 7 Data Width of this
5. from CK CK tDQSCK 0 5 0 5 ns Output data access time from CK CK tAC 0 7 0 7 ns Data strobe edge to output data edge tDQSQ 0 35 ns 13 Read Preamble tRPRE 0 9 1 1 tCK Read Postamble tRPST 0 4 0 6 tCK CK to valid DQS in tDQSS 0 72 1 25 tCK Write preamble setup time tWPRES 0 ps 5 Write preamble tWPRE 0 25 tCK Write postamble tWPST 0 4 0 6 tCK 4 DQS falling edge to CK rising setup time tDSS 0 2 tCK DQS falling edge from CK rising hold time tDSH 0 2 tCK DQS in high level width tDQSH 0 35 tCK DQS in low level width tDQSL 0 35 tCK Address and Control input setup time tIS 0 6 ns 7 10 Address and Control input hold time tIH 0 6 ns 7 10 Data out high impedance time from CK CK tHZ 06 0 6 ns 3 Data out low impedance time from CK CK tLZ 0 6 0 6 ns 3 Mode register set cycle time tMRD 10 tCK DQ amp DM setup time to DQS tDS 0 4 ns DQ amp DM hold time to DQS tDH 0 4 ns DQ amp DM input pulse width tDIPW 1 65 ns 9 Control amp Address input pulse width for each input tIPW 2 2 ns 9 Refresh interval time tREF 7 8 us 6 Output DQS valid window TQH tHP 0 55 ns 12 Clock half period tHP tCLmin tCHmin ns 11 12 Transcend Information Inc 184PIN DDR400 Unbuffered DIMM TS64MLD64V4F 512MB With 32Mx8 CL2 5 Data hold skew factor tQHS 0 5 ns 12 Auto Precharge write recovery precharge time tDAL ns 14 Exit self refresh to non READ command tXSNR 75 ns 15 Exit self refresh to READ command tXSRD 10 tC
6. 6 144 CB7 07 VDD 53 DQ32 99 DQ7 145 VSS 08 DQ3 54 VDDQ 100 VSS 146 DQ36 09 NC 55 DQ33 101 NC 147 DQ37 10 NC 56 DQS4 102 NC 148 VDD 11 VSS 57 DQ34 103 NC 149 DM4 12 DQ8 58 VSS 104 VDDQ 150 DQ38 13 DQ9 59 BAO 105 DQ12 151 DQ39 14 DQS1 60 DQ35 106 DQ13 152 VSS 15 VDDQ 61 DQ40 107 DM1 153 DQ44 16 CK1 62 VDDQ 108 VDD 154 RAS 17 CK1 63 WE 109 DQ14 155 DQ45 18 VSS 64 DQ41 110 DQ15 156 VDDQ 19 DQ10 65 ICAS 111 CKE1 157 CSO 20 DQ11 66 VSS 112 VDDQ 158 CS1 21 CKEO 67 DQS5 113 NC 159 DM5 22 VDDQ 68 DQ42 114 DQ20 160 VSS 23 DQ16 69 DQ43 115 A12 161 DQ46 24 DQ17 70 VDD 116 VSS 162 DQ47 25 DQS2 71 NC 117 DQ21 163 NC 26 VSS 72 DQ48 118 A11 164 VDDQ 27 A9 73 DQ49 119 DM2 165 DQ52 28 DQ18 74 VSS 120 VDD 166 DQ53 29 A7 75 CK2 121 DQ22 167 NC 30 VDDQ 76 CK2 122 A8 168 VDD 31 DQ19 77 VDDQ 123 DQ23 169 DM6 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VDDQ 35 DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 82 NC 128 VDDQ 174 DQ60 37 A4 83 DQ56 129 DM3 175 DQ61 38 VDD 84 DQ57 130 A3 176 VSS 39 DQ26 85 VDD 131 DQ30 177 DM7 40 DQ27 86 DQS7 132 VSS 178 DQ62 41 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VDDQ 43 A1 89 VSS 135 CB5 181 SAO 44 CBO 90 NC 136 VDDQ 182 SA1 45 CB1 91 SDA 137 CKO 183 SA2 46 VDD 92 SCL 138 CKO 184 VDDSPD Please refer Block Diagram Transcend Information Inc 184PIN DDR400 Unbuffered DIMM TS64MLD64V4F 512MB With 32Mx8 CL2 5 Block Diagram
7. Assembly 0 00 8 VDDQ and Interface Standard of this Assembly SSTL 2 04 9 DDR SDRAM Cycle Time at CAS Latency 2 5 5 0ns 50 10 DDR SDRAM Access Time from Clock at CL 2 5 0 70ns 70 11 DIMM configuration type non parity Parity ECC Non ECC 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary DDR SDRAM Width X8 08 14 Error Checking DDR SDRAM Width 00 15 Min Clock Delay for Back to a Back Random Column Address EPRICE 16 Burst Lengths Supported 2 4 8 0E 17 of banks on each DDR SDRAM device 4 bank 04 18 CAS Latency supported 2 2 5 oC 19 CS Latency 0 CLK 01 20 WE Latency 1 CLK 02 21 DDR SDRAM Module Attributes Bice Mel 20 Clock Input 22 DDR SDRAM Device Attributes General Poe eoe 00 tolerance 23 DDR SDRAM Cycle Time CL 2 0 6ns 60 24 DDR SDRAM Access from Clock CL 2 0 0 70ns 70 25 DDR SDRAM Cycle Time CL 1 5 00 26 DDR SDRAM Access from Clock CL 1 5 00 27 Minimum Row Precharge Time tRP 15ns 3C 28 Minimum Row Active to Row Activate delay tRRD 10ns 28 29 Minimum RAS to CAS Delay tRCD 15ns 3C 30 Minimum active to Precharge time tRAS 40ns 28 31 Module ROW density 256MB 40 32 Command Address Input Setup Time 0 6ns 60 33 Command Address Input Hold Time 0 6ns 60 34 Data Signal Input Setup Time 0 4ns 40 35 Data Signal Input Hold Time 0 4ns 40 36 61 Superset Information 00 62 SPD Data Revision Code 00 63 Checksum for Bytes 0 62 AB Transcend Information Inc 11 TS64MLD64V4F 184PIN DDR400 Unbuffer
8. K Note 1 VID is the magnitude of the difference between the input level on CK and the input level on CK 2 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same 3 tHZ and tLZ transitions occur in the same access time windows as valid data transitions These parameters are not referenced to a specific voltage level but specify when the device output in no longer driving HZ or begins driving LZ 4 The maximum limit for this parameter is not a device limit The device will operate with a greater value for this parameter but sys tem performance bus turnaround will degrade accordingly 5 The specific requirement is that DQS be valid HIGH LOW or at some point on a valid transition on or before this CK edge A valid transition is defined as monotonic and meeting the input slew rate specifications of the device When no writes were previously in progress on the bus DQS will be transitioning from High Z to logic LOW If a previous write was in progress DQS could be HIGH LOW or transitioning from HIGH to LOW at this time depending on tDQSS 6 A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device 7 For command address input slew rate gt 0 5 V ns 8 For CK amp CK slew rate gt 0 5 V ns 9 These parameters guarantee device timing but they are not necessarily tested on each device They may be guaranteed by device design or
9. L ne Low COMMAND CKEn 1 CKEn ics Ras icas we icas we Baon Baon aora Ao A9 A11 A12 Ao A9 A11 A12 A12 Extended poe sa e eee re Register Mode Register set _ H x t ti fT bt tb OP CODE Refresh Bank Active amp Row Addr Read amp a Fae eames area FFE eE al ee Reteh feat ot W eto a ENESE D oe Column Address Burst Stop Auto Precharge Disable Column Address Auto Precharge Enable gam Ao A9 i Auto Precharge Disable pumo Aadress Auto Precharge Enable oH Column Address Ao Ag X Precharge Banik Selection H x Le On ea fa All Banks Ee xxix cay a fo E Active Power Down Precharge Power Down Mode DM EEEN Entry SEERERED Danaa No Operation Command X Note Transcend Information Inc OP Code Operand Code AO A12 amp BAO BA1 Program keys EMRS MRS 2 EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS 3 Auto refresh functions are same as the CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAO BA1 Bank select addresses If both BAO and BA1 are Low at read write row active and precharge bank A is selected If both BAO is High and BA1 is Low at read write row active and precharge bank B is selected If
10. TS64MLD64V4F 184PIN DDR400 Unbuffered DIMM 512MB With 32Mx8 CL2 5 Description The TS64MLD64V4F is a 64Mx64bits Double Data Rate SDRAM high density for DDR400 The TS64MLD64V4F consists of 16pcs CMOS 32Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages and a 2048 bits serial EEPROM on a 184 pin printed circuit board The TS64MLD64V4F is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e RoHS compliant products e Power supply VDD 2 6V 0 1V VDDQ 2 6V 0 1V e Max clock Freq 200MHZ e Double data rate architecture two data transfers per clock cycle e Differential clock inputs CK and CK e DLL aligns DQ and DQS transition with CK transition e Auto and Self Refresh 7 8us refresh interval e Data I O transactions on both edge of data strobe e Edge aligned data output center aligned data e Serial Presence Detect SPD with serial EEPROM e SSTL 2 compatible inputs and outputs e MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Placement
11. ank operation One bank open Burst 4 Reads Refer to the following page for detailed test condition Percharge power down standby current All banks idle power down mode CKE lt VIL max VIN VREF for DQ DQS and DM Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min Address and other control inputs changing once per clock IDD2F 480 mA cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode CKE lt VIL max VIN VREF for DQ DQS and DM Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax DQ DQS and DM inputs changing twice per clock cycle address and other control inputs changing once per clock cycle Operating current burst read Burst length 2 reads continuous burst One bank active address and control inputs changing once per clock cycle IDD4R 2 080 mA 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst Auto refresh current tRC tRFC min 10 tCK for DDR400 at 200Mhz distributed refresh Self refresh current CKE lt 0 2V External clock should be on IDD6 48 mA Operating current Four bank operation Four bank interleavin
12. ed DIMM 512MB With 32Mx8 CL2 5 64 71 Manufacturers JEDEC ID Transcend TF 4F 72 Manufacturing Location T 54 54 53 36 34 4D 4C 73 90 Manufacturers Part Number TS64MLD64V4F 44 36 34 56 34 46 20 20 20 20 20 20 91 92 Revision Code 00 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific Data 00 128 255 Unused Storage Locations Undefined 00 Transcend Information Inc 12
13. g with BL 4 Refer to the following page for detailed test condition Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading capacitor IDD1 1 640 mA IDD2P 65 mA IDD3P 880 mA IDD3N 1 200 mA IDD4W 2 360 mA IDD5 2 200 mA IDD7 3 400 mA Transcend Information Inc 6 TS64MLD64V4F 184PIN DDR400 Unbuffered DIMM 512MB With 32Mx8 CL2 5 AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Note Input High Logic 1 Voltage DQ DQS and DM signals VIH AC VREF 0 31 V 3 Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 31 V 3 Input Differential Voltage CK and CK inputs VID AC 0 7 VDDQ 0 6 V 1 Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 0 5VDDQ 0 2 V 2 Note 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device and must track variations in the DC level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 2OMHz AC OPERATING TEST CONDITIONS VDD 2 6 VDDQ 2 6 TA 0 to 70 C Parameter Input refere
14. nce voltage for Clock Input signal maximum peak swing Input Levels VIH VIL Input timing measurement reference level Output timing measurement reference level Output load condition See Load C ircuit VTT 0 5 VDDQ mia ZO 50ohm Output O 0 5 VDDQ CLoan 30pF Output Load circuit be Input Output CAPACITANCE voo 2 6V Vona 2 6V TA 25 C f Input capacitance AO A12 BAO BA1 RAS CAS WE Input capacitance Input capacitance CKEO CKE1 CSO CS1 Input capacitance CKO CK2 Input capacitance DMO DM7 Data and DQS input output capacitance DQ0 DQ63 Transcend Information Inc 1MHz Min 65 42 42 27 10 10 TS64MLD64V4F 184PIN DDR400 Unbuffered DIMM 512MB With 32Mx8 CL2 5 AC Timing Parameters amp Specifications These AC characteristics were tested on the Component Parameter Symbol Min Max Unit Note Row cycle time tRC 55 ns Refresh row cycle time tRFC 65 ns Row active time tRAS 40 70K ns RAS to CAS delay tRCD 15 ns Row active to Row active delay tRP 15 ns Row active to Row active delay tRRD 10 ns Write recovery time tWR 10 ns Internal write to read command delay tWTR 2 tCK Clock cycle time tCK 5 10 ns 16 Clock high level width tCH 0 45 0 55 tCK Clock low level width tCL 0 45 0 55 tCK DQS out access time
15. tester correlation 10 Slew Rate is measured between VOH ac and VOL ac 11 Min tCL tCH refers to the smaller of the actual clock low time and the actual clock high time as provided to the device i e this value can be greater than the minimum specification limits for tCL and tCH For example tCL and tCH are 50 of the period less the half period jitter tUIT HP of the clock source and less the half period jitter due to crosstalk tUIT crosstalk into 12 tQH tHP tQHS where tHP minimum half clock period for any given cycle and is defined by clock high or clock low tCH tCL tQHS accounts for 1 The pulse duration distortion of on chip clock circuits and 2 The worst case push out of DQS on one transition followed by the worst case pull in of DQ on the next transition both of which are separately due to data pin skew and output pattern effects and p channel to n channel variation of the output drivers 13 tDQSQ Consists of data pin skew and output pattern effects and p channel to n channel variation of the output drivers for any given cycle 14 tDAL tWR tCkK tRP tCkK 15 In all circumstances tXSNR can be satisfied using X SNR tRFCmin 1 tCK 16 The only time that the clock frequency is allowed to change is during self refresh mode Transcend Information Inc TS64MLD64V4F 184PIN DDR400 Unbuffered DIMM 512MB With 32Mx8 CL2 5 SIMPLIFIED TRUTH TABLE V Valid Ee Don t Care H Logic High
16. ure TSTG 55 150 C Power dissipation PD 24 W Short circuit current los 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Max Unit Note Supply voltage VDD 2 5 2 7 V I O Supply voltage VDDQ 2 5 2 7 V I O Reference voltage VREF Voba 2 50mV VDDa 2 50mV V 1 1 O Termination voltage VTT VREF 0 04 VREF 0 04 V 2 Input logic high voltage VIH DC VREF 0 15 VDDQ 0 3 V 4 Input logic low voltage VIL DC 0 3 VREF 0 15 V 4 Input Voltage Level CK and CK inputs VIN DC 0 3 VDDQ 0 3 V Input Differential Voltage CK and CK inputs VID DC 0 3 VDDQ 0 6 V 3 Input crossing point voltage CK and CK inputs VIX DC 1 15 1 35 V 5 Input leakage current lI 2 2 uA Output leakage current loz 5 5 uA Output High Current Normal strength driver IOH 16 8 mA VOUT VTT 0 84V Output Low Current Normal strength driver IOL 16 8 mA VOUT VTT 0 84V Output High Current Half strength driver IOH 9 mA VOUT VTT 0 45V Output High Current Half strength driver IOL 9 mA VOUT VTT 0 45V Note 1
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