Transcend 512MB DDR DDR266 Non-ECC Memory
Contents
1. Note 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case shown DQS going from High_Z to logic Low applies when no writes were previously in progress on the bus If a previous write was in progress DQS could be High at this time depending on tDQSS 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly 4 For registered DIMMs tCL and tCH are gt 45 of the period including both the half period jitter tUIT HP of the PLL and the half period jitter due to crosstalk tUIT crosstalk on the DIMM 5 A write command can be applied with tRCD satisfied after this command Transcend Information Inc 9 200PIN DDR266 Unbuffered SO DIMM TS64MSD64V6F5 512MB With 32Mx8 CL2 5 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND CKEn 1 CKEn CS RAS CAS WE BAo 1 A1o AP Ao Ag A11 A12 Note Extended Register Mode Register Set X L L L L OP CODE 1 2 Register Mode Register Set X L L L L OP CODE 1 2 Auto Refresh H L L L H x 3 Entry L 3 Refresh Self L H H H 3 Refresh i Exit L H H X X X x 3 Bank Active amp Row Addr H x L L H H V Row Address2. 32Mx8 DDR DDR DDR DDR IWE SDRAM IWE SDRAM ANE SDRAM IWE SDRAM ICS M ICS yA ICS M ICS awm ii l EJE ICS1 CKE1 X X BAO BA1 O BAO BA1 O DQ0 DQ7 DQ0 DQ7 IRAS O H Ras o ICAS 32Mx8 CAS_ 32Mx8 ICAS 32Mx8 ICAS 32Mx8 DDR DDR DDR DDR IWE SDRAM IWE SDRAM IWE SDRAM IWE SDRAM CS z 9 CS n CS g CS 2 CKE 2 S CKE z g CKE 2 a CKE 4 6 DM1 DM3 DM5 DM7 Serial EEPROM DQS1 DQS3 DQS5 DQS7 SCL SCL SDA SDA AO A1 A2 SAO SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 200PIN DDR266 Unbuffered SO DIMM TS64MSD64V6F5 512MB With 32Mx8 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 0 5 3 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 3 6 V Storage temperature TSTG 55 150 C Power dissipation PD 16 W Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if A
3. lt VIL max tCK tCK min IDD2P 48 mA VIN VREF for DQ DQS and DM Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min tCK 133Mhz for DDR266 Address and other control inputs changing once per clock cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode CKE lt VIL max tCK tCK min IDD3P 480 mA VIN VREF for DQ DQS and DM Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax tCK tCK min DQ DQS and DM inputs changing twice per clock cycle address and other control DD3N 720 mA inputs changing once per clock cycle IDDO 1 000 mA IDD1 1 240 mA IDD2F 320 mA Operating current burst read Burst length 2 reads continguous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at IDD4R 1 480 mA tCK tCK min 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at tCK tCK min DQ DM and DQS inputs changing twice per clock cycle 50 of IDD4W 1 480 mA input data changing at every burst Auto refresh current tRC tRFC min IDD5 1 680 mA Self refresh current CKE lt 0 2V IDD6 48 mA Operating current Four bank operation Four bank interleav
4. 00 0 10 0 039 0 004 Refer Placement Transcend Information Inc DQ0 DQ63 Data Input Output DQS0 DQS7 Data strobe input output CKO CK1 Clock Input CKO CK1 CKEO CKE1 Clock Enable Input CS0 CS1 Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe INE Write Enable DMO DM7 Data in Mask VDD 2 5 Voltage power supply VREF Power Supply for Reference VDDSPD 2 5 Voltage Serial EEPROM Power Supply SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection 200PIN DDR266 Unbuffered SO DIMM TS64MSD64V6F5 512MB With 32Mx8 CL2 5 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 VREF 69 VDD 137 VSS 02 VREF 70 VDD 138 VSS 03 VSS 71 CBO 139 DQ35 04 VSS 72 CB4 140 DQ39 05 DQO 73 CB1 141 DQ40 06 DQ4 74 CB5 142 DQ44 07 DQ1 75 VSS 143 VDD 08 DQ5 76 VSS 144 VDD 09 VDD 77 DQS8 145 DQ41 10 VDD 78 DM8 146 DQ45 11 DQSO 79 CB2 147 DQS5 12 DMO 80 CB6 148 DM5 13 DQ2 81 VDD 149 VSS 14 DQ6 82 VDD 150 VSS 15 VSS 83 CB3 151 DQ42 16 VSS 84 CB7 152 DQ46 17 DQ3 85 DU 153 DQ43 18 DQ7 86 DU 154 DQ47 19 DQ8 87 VSS 155 VDD 20 DQ12 88 VSS 156 VDD 21 VDD 89 CK2 157 VDDD 22 VDD 90 VSS 158 ICK1 23 DQ9 91 ICK2 159 VSS 24 DQ13 92 VDD 160 CK1 25 DQS1 93 VDD 161 VSS 26 DM1 94 VDD 162 VSS 27 VSS 95 CKE1 163 DQ48 28 VSS 96 CKEO 164 DQ52 29 DQ10
5. DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 VID is the magnitude of the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ The value of VIx is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same oa Transcend Information Inc 5 200PIN DDR266 Unbuffered SO DIMM TS64MSD64V6F5 512MB With 32Mx8 CL2 5 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Parameter Symbol Max Unit Note Operating current One bank Active Precharge tRC tRCmin tCK tCK min DQ DM and DQS inputs changing twice per clock cycle Address and control inputs changing once per clock cycle Operating current One bank Active Read Precharge Burst 2 tRC tRC min CL 2 5 tCK tCK min VIN VREF fro DQ DQS and DM Percharge power down standby current All banks idle power down mode CKE
6. NON ECC 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary DDR SDRAM Width X8 08 14 Error Checking DDR SDRAM Width 00 15 Min Clock Delay for Back to 2 Back Random Column Address ESRT 16 Burst Lengths Supported 2 4 8 0E 17 of banks on each DDR SDRAM device 4 bank 04 18 CAS Latency supported 2 2 5 0C 19 CS Latency 0 CLK 01 20 WE Latency 1 CLK 02 Differential 21 DDR SDRAM Module Attributes Clock Input 20 22 DDR SDRAM Device Attributes General N ew volage 00 tolerance 23 DDR SDRAM Cycle Time CL 2 0 10ns AO 24 DDR SDRAM Access from Clock CL 2 0 0 75ns 75 25 DDR SDRAM Cycle Time CL 1 5 00 26 DDR SDRAM Access from Clock CL 1 5 00 27 Minimum Row Precharge Time tRP 20ns 50 28 Minimum Row Active to Row Activate delay tRRD 15ns 3C 29 Minimum RAS to CAS Delay tRCD 20ns 50 30 Minimum active to Precharge time tRAS 45ns 2D 31 Module ROW density 256MB 40 32 Command Address Input Setup Time 0 9ns 90 33 Command Address Input Hold Time 0 9ns 90 34 Data Signal Input Setup Time 0 5ns 50 35 Data Signal Input Hold Time 0 5ns 50 36 61 Superset Information 00 62 SPD Data Revision Code 00 63 Checksum for Bytes 0 62 Co 64 71 Manufacturers JEDEC ID Transcend TF 4F Transcend Information Inc 11 200PIN DDR266 Unbuffered SO DIMM TS64MSD64V6F5 512MB With 32Mx8 CL2 5 72 Manufacturing Location T 54 54 53 36 34 4D 53 73 90 Manufacturers Part Number TS64MSD64V6F5_ 44 36
7. and all banks are selected During burst write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in are masked at the both edges Write DM latency is 0 This combination is not defined for any function which means No Operation NOP in DDR SDRAM Transcend Information Inc 10 TS64MSD64V6F5 200PIN DDR266 Unbuffered SO DIMM 512MB With 32Mx8 CL2 5 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type DDR SDRAM 07 3 of Row Addresses on this Assembly 13 oD 4 of Column Addresses on this Assembly 10 OA 5 of Module Rows on this Assembly 2bank 02 6 Data Width of this Assembly 64bits 40 7 Data Width of this Assembly 0 00 8 VDDQ and Interface Standard of this Assembly SSTL 2 04 9 DDR SDRAM Cycle Time at CAS Latency 2 5 7 5ns 75 10 DDR SDRAM Access Time from Clock at CL 2 5 0 75ns 75 11 DIMM configuration type non parity Parity ECC
8. 200PIN DDR266 Unbuffered SO DIMM TS64MSD64V6F5 512MB With 32Mx8 CL2 5 Description Placement The TS64MSD64V6F5 is a 64M x 64bits Double Data Rate SDRAM high density for DDR266 The TS64MSD64V6F5 zE ath consists of 16pcs CMOS 32Mx8 bits Double Data Rate 5 E FE Z E 3E Z 9 2 a sa 5 E SDRAMS in 64 pin sTSOP packages and a 2048 bits serial ef Elle ee EE E WZ PE E a PE EEPROM on a 200 pin printed circuit board The 5 E SE Sije 5E z TS64MSD64V6F5 is a Dual In Line Memory Module and is E zE FIE a6 EI B intended for mounting into 200 pin edge connector sockets 5 E ZE Elle te 2 i Synchronous design allows precise cycle control with the E z E z E E z j use of system clock Data I O transactions are possible o
9. 34 56 36 46 35 20 20 20 20 20 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific Data 128 255 Unused Storage Locations Undefined Transcend Information Inc 12
10. 97 A13 165 DQ49 30 DQ14 98 DU 166 DQ53 31 DQ11 99 A12 167 VDD 32 DQ15 100 A11 168 VDD 33 VDD 101 AQ 169 DQS6 34 VDD 102 A8 170 DM6 35 CKO 103 VSS 171 DQ50 36 VDD 104 VSS 172 DQ54 37 CKO 105 AT 173 VSS 38 VSS 106 A6 174 VSS 39 VSS 107 A5 175 DQ51 40 VSS 108 A4 176 DQ55 41 DQ16 109 A3 177 D56 42 DQ20 110 A2 178 DQ60 43 DQ17 111 Al 179 VDD 44 DQ21 112 AO 180 VDD 45 VDD 113 VDD 181 DQ57 46 VDD 114 VDD 182 DQ61 47 DQS2 115 A10 183 DQS7 48 DM2 116 BA1 184 DM7 49 DQ18 117 BAO 185 VSS 50 DQ22 118 RAS 186 VSS 51 VSS 119 IWE 187 DQ58 52 VSS 120 ICAS 188 DQ62 53 DQ19 121 CSO 189 DQ59 54 DQ23 122 1CS1 190 DQ63 55 DQ24 123 DU 191 VDD 56 DQ28 124 DU 192 VDD 57 VDD 125 VSS 193 SDA 58 VDD 126 VSS 194 SAO 59 DQ25 127 DQ32 195 SCL 60 DQ29 128 DQ36 196 SA1 61 DQS3 129 DQ33 197 VDDSPD 62 DM3 130 DQ37 198 SA2 63 VSS 131 VDD 199 VDD 64 VSS 132 VDD 200 DU 65 DQ26 133 DQS4 66 DQ30 134 DM4 67 DQ27 135 DQ34 68 DQ31 136 DQ38 Please refer Block Diagram Transcend Information Inc 3 200PIN DDR266 Unbuffered SO DIMM TS64MSD64V6F5 512MB With 32Mx8 CL2 5 Block Diagram AO A12 BAO BA1 DQ0 DQ63 RAS CAS WE CSO CKEO CKO CKO Al CK1 CK1 i f ji AO A12 5 A0 A12 S AO A12 5 A0 A12 re A BAO BA1 x BAO BA1 x BAO BA1 BAO BA1 lt DQ0 DQ7 x DQ0 DQ7 x DQ0 DQ7 x DQ0 DQ7 x RAS RAS RAS RAS ICAS 32Mx8 ICAS 32Mx8 CAS 32Mx8 ICAS
11. Auto Precharge Disable L Col 4 Read amp 2 ger H x IL H Lln v Address Column Address Auto Precharge Enable H Ao As i Auto Precharge Disable L Col Write amp 2 H x L H L L v Address Column Address Auto Precharge Enable H Ao As 4 6 Burst Stop H X L H H L X 7 Bank Selection V L Precharge All Banks H X L L H L X H X 5 Entry H Le eR Xa n X Active Power Down L V V V X Exit L H X X X X H X X X Entry H L Precharge Power L H H H Down Mode X Exit H X X X L H L V V V DM H X X H X X xX No Operation Command H x x L H H H 9 Note 1 2 es SS OP Code Operand Code AO A12 amp BAO BA1 Program keys EMRS MRS EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS Auto refresh functions are same as the CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state BAO BA1 Bank select addresses If both BAO and BA1 are Low at read write row active and precharge bank A is selected If both BAO is High and BA1 is Low at read write row active and precharge bank B is selected If both BAO is Low and BA1 is High at read write row active and precharge bank C is selected If both BAO and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAO and BA1 are ignored
12. BSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Max Unit Note Supply voltage VDD 2 3 2 7 V I O Supply voltage VDDQ 2 3 2 7 V I O Reference voltage VREF VDDQ 2 50mV VDDa 2 50mV V 1 I O Termination voltage VTT VREF 0 04 VREF 0 04 V 2 Input logic high voltage VIH DC VREF 0 15 VDDQ 0 3 V 4 Input logic low voltage VIL DC 0 3 VREF 0 15 V 4 Input Voltage Level CK and CK inputs VIN DC 0 3 VDDQ 0 3 V Input Differential Voltage CK and CK inputs VID DC 0 3 VDDQ 0 6 V 3 Input crossing point voltage CK and CK inputs VIX DC 1 15 1 35 V 5 Input leakage current lI 2 2 uA Output leakage current lOZ 5 5 uA Output High Current Normal strength driver OH 16 8 mA VOUT VTT 0 84V Output Low Current Normal strength driver IOL 16 8 mA VOUT VTT 0 84V Output High Current Half strength driver IOH 9 mA VOUT VTT 0 45V Output High Current Half strength driver IOL 9 mA VOUT VTT 0 45V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate
13. dth tCH 0 45 0 55 tCK Clock low level width tCL 0 45 0 55 tCK DQS out access time from CK CK tDQSCK 0 75 0 75 ns Output data access time from CK CK tAC 0 75 0 75 ns Data strobe edge to output data edge tDQSQ 0 5 ns 4 Read Preamble tRPRE 0 9 1 1 tCK Read Postamble tRPST 0 4 0 6 tCK CK to valid DQS in tDQSS 0 75 1 25 tCK DQS in setup time tWPRES 0 ns 2 DQS in hold time tWPREH 0 25 tCK DQS falling edge to CK rising setup time tDSS 0 2 tCK DQS falling edge from CK rising hold time tDSH 0 2 tCK DQS in high level width tDQSH 0 35 tCK DQS in low level width tDQSL 0 35 tCK DQS in cycle time tDSC 0 9 1 1 tCK Address and Control input setup time tIS 0 9 ns Address and Control input hold time tlH 0 9 ns Data out high impedance time from CK CK tHZ 0 75 0 75 ns Data out low impedance time from CK CK tLZ 0 75 0 75 ns Mode register set cycle time tMRD 15 ns DQ amp DM setup time to DQS tDS 0 5 ns Transcend Information Inc g 200PIN DDR266 Unbuffered SO DIMM TS64MSD64V6F5 512MB With 32Mx8 CL2 5 DQ amp DM hold time to DQS tDH 0 5 ns DQ amp DM input pulse width tDIPW 1 75 ns Power down exit time tPDEX 7 5 ns Exit self refresh to bank active command tXSA 75 ns 5 Exit self refresh to read command tXSR 200 Cycle Refresh interval time tREF 7 8 us 1 Clock half period tHP tCLmin or ns tCHmin Data hold skew factor tQHS 0 75 Ns DQS write postamble time tWPST 0 4 TCK 3
14. ing with BL 4 IDD7 2 600 mA Refer to the following page for detailed test condition Note 1 Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading capacitor Transcend Information Inc 6 200PIN DDR266 Unbuffered SO DIMM TS64MSD64V6F5 512MB With 32Mx8 CL2 5 AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Note Input High Logic 1 Voltage DQ DQS and DM signals VIH AC VREF 0 31 V 3 Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 31 V 3 Input Differential Voltage CK and CK inputs VID AC 0 7 VDDQ 0 6 V 1 Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 0 5VDDQ 0 2 V 2 Note 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device and must track variations in the DC level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 2OMHz AC OPERATING TEST CONDITIONS VDD 2 5 VDDQ 2 5 TA 0 to 70 C Parameter Value Unit Note Input reference voltage for Clock 0 5 VDDQ V Input signal maximum peak swing 1 5 V Input Leve
15. ls VIH VIL VREF 0 31 VREF 0 31 V Input timing measurement reference level VREF V Output timing measurement reference level VTT V Output load condition See Load Circuit VTT 0 5 VDDQ Reson Output Q ZO 50ohm gt J VREF 0 5 VDDQ Croan 30pF Output Load circuit Input Output CAPACITANCE Vpp 2 5V Vopa 2 5V TA 25 C f 1MHz Parameter Symbol Min Max Unit Input capacitance AO A12 BAO BA1 RAS CAS WE CIN1 65 81 pF Input capacitance CKE0 CKE1 CIN2 42 50 pF Input capacitance CS0 CS1 CIN3 42 50 pF Input capacitance CKO CK1 CIN4 27 34 pF Input capacitance DMO DM7 CIN5 10 13 pF Data and DQS input output capacitance DQ0 DQ63 CouT1 10 13 pF Transcend Information Inc 200PIN DDR266 Unbuffered SO DIMM TS64MSD64V6F5 512MB With 32Mx8 CL2 5 AC Timing Parameters amp Specifications These AC characteristics were tested on the Component Parameter Symbol Min Max Unit Note Row cycle time tRC 65 ns Refresh row cycle time tRFC 75 ns Row active time tRAS 45 120K ns RAS to CAS delay tRCD 20 ns Row active to Row active delay tRP 20 ns Row active to Row active delay tRRD 15 ns Write recovery time tWR 15 tCK Last data in to Read command tCDLR 1 tCK Col Address to Col Address delay tCCD 1 tCK Clock cycle time tCK 7 5 ns 4 Clock high level wi
16. n E 2 2 3 2 E 2 wee we lel AE n we EF both edges of DQS Range of operation frequencies a e E SE zE SE SS D programmable latencies allow the same device to be useful 5 amp ZE E 4 A A for a variety of high bandwidth high performance memory E E E E i JE z AE C A M system applications Ee zn f 2 4 G ff gt H Features lt i gt e Power supply VDD VDDQ 2 5V 0 2V e Max clock Freq 133MHZ e Double data rate architecture two data transfers per PCB 09 1490 clock cycle e Differential clock inputs CK and CK e DLL aligns DQ and DQS transitions with CLK transition e Commands entered on each positive CLK edge e Auto and Self Refresh e Data I O transactions on both edge of data strobe e Serial Presence Detect SPD with serial EEPROM e SSTL 2 compatible inputs and outputs e MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Transcend Information Inc 1 TS64MSD64V6F5 200PIN DDR266 Unbuffered SO DIMM 512MB With 32Mx8 CL2 5 Pin Identification Symbol Function A0 A12 BA0 BA1 Address input Dimensions Side Millimeters Inches 67 60 0 20 2 661 0 008 B 47 40 1 866 C 11 40 0 449 D 4 20 0 165 E 2 15 0 085 F 1 80 0 071 G 2 55 0 100 H 4 00 0 157 20 00 0 787 J 31 75 0 20 1 250 0 008 K 1
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