Supermicro HMT325S6BFR8C-H9
Contents
1. VDD VDD Ei Cterm L Cterm Ja 2 ae Vtt Vt vit g ee L L L alssie gig 8B amp IB ER N AN N LLILBH LII hy DQS3 AMW Dos 2400hm LDQs 240ohm DQS cau Das ND LN DQS4 DO53 ERE DUE lo 1 ES 1 _ Bee DOS4 DM3 WDM oS Ba m DM awi LE OSL Au DM4 DQ 24 31 M DQ 0 7 DQ 0 7 DQ 0 7 DQ 0 7 WW DQ 32 39 D11 D3 D4 D12 z z z z i z z z S S SE S 6 6 6 6 wise ses bie wae vw g odes ws 8e Leis sus Ble T L r r r i UMS rs 1 Beet Mpa ew Cum Gs Dos aw pos IO ww noss DOSI AM DOS IDOS DQS DQS e AN DQS6 DMI AMH DM 70 W im E DM NEL DM 20 Did me DQ2. 51 DQ18 52 DQ23 103 CKO 104 CK1 155 Vss 1156 Vss NC No Connect RFU Reserved Future Use 1 TEST pin 125 is reserved for bus analysis probes and is NC on normal memory modules 2 This address might be connected to NC balls of the DRAMs depending on density either way they will be con nected to the termination resistor Rev 0 4 Jul 2010 hynix Functional Block Diagram 1GB 128Mx64 Module 1Rank of x16 SCL SCL SAO AO Temp sen Sien SA1 4 Al lt gt SDA A2 EVENT The SPD may be ZE integrated with the Temp EVENT Sensor or may be a separate component SCL SCL SA1 4 Al lt gt SDA A2 WP Ve M Vit VopSPD SPD TS VREFCA p D0 D3 VREFDQ p D0 D3 Vop 4 p D0 D3 Vss F D0 D3 SPD Temp sensor z o E sig td S S slg 13 ls 818 8 8 g Ltt AH I DQS0 Mc DoS SC DQSO PS DMO LDM aw DQ 0 7 BA 0 7 pas v upos DQS1 ER DO M DM1 A e4 UDM S DQ 8 15 AAW DQ 8 15 a ale Oo ip BIBS viv 8 Ble DQS52 1LDQS 24dohm DOS WLS 79 WN DM2 WV LDM a DQ 16 23 AM DQ 0 7 DQS3 Me HDOS DQS3 NN 1UDQS D1 z DM3 Me UDM 2 DQ 24 311 AAW DQ 8 15 S a ule Oo w ElSe vw BIS DQS4 VWs 240ohm DQs4
3. Symbol Parameter Rating Units Notes Topr Operating temperature 0 to 65 C 1 3 Hopr Operating humidity relative 10 to 90 96 1 TsrG Storage temperature 50 to 100 oc 1 Hera Storage humidity without condensation 5 to 95 K 1 PBAR Barometric Pressure operating amp storage 105 to 69 K Pascal 4 2 Note 1 Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Expousure to absolute maximum rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The designer must meet the case temperature specifications for individual module components Rev 0 4 Jul 2010 35 hynix Pin Capacitance VDD 1 5V VDDQ 1 5V 1GB HMT312S6BFR6C Pin Symbol Min Max Unit CKO CKO Cck TBD TBD pF CKE ODT CS Cem TBD TBD pF Address RAS CAS WE Ci TBD TBD pF DQ DM DOS DAS Cio TBD TBD pF 2GB HMT325S6BFR6C Pin Symbol Min Max Unit CKO CKO Cox TBD TBD pF CKE ODT CS Cota TBD TBD pF Address RAS CAS WE Ci TBD TBD pF DQ DM DOS DOS Cio TBD TBD pF 2GB HMT325S6BFR8C Pin Symbol Min Max Unit CKO CKO Cox TBD TBD pF CKE ODT CS Cem TBD TBD pF Address RAS CAS WE C TBD TBD pF DQ DM DOS DOS Cio TBD TBD pF 4GB HMT351S6BFR8C Pin Symbol Min Max Unit CKO
4. X Correction Channel IO Power Number Figure 2 Correlation from simulated Channel IO Power to actual Channel 1O Power supported by IDDQ Measurement Rev 0 4 Jul 2010 38 hynix Table 1 Timings used for I DD and I DDQ Measurement Loop Patterns DDR3 1066 DDR3 1333 DDR3 1600 Symbol Unit 7 7 7 9 9 9 11 11 11 tex 1 875 1 5 1 25 ns CL 7 9 11 nCK RCD 7 9 11 nCK liac 27 33 39 nCK RAS 20 24 28 nCK Tipp 7 9 11 nCK 1KB page size 20 20 24 nCK Trau 2KB page size 27 30 32 nCK 1KB page size 4 4 5 nCK ARRD 2KB page size 6 5 6 nCK RFC 512Mb 48 60 72 nCK Ngec 1 Gb 59 74 88 nCK REC 2 Gb 86 107 128 nCK Ngec 4 Gb 160 200 240 nCK Merc 8 Gb 187 234 280 nCK Table 2 Basic I DD and I DDQ Measurement Conditions Symbol Description ppo Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 8 AL 0 CS High between ACT and PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data IO MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 3 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 3 Ippi Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS nRCD CL see Table 1 BL
5. 10 11 Dick Supported CWL Settings 5 6 7 8 NK Rev 0 4 Jul 2010 33 hyuix Speed Bin Table Notes Absolute Specification TopeR VDDQ Vpp 1 5V 0 075 V 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When mak ing a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as require ments from CWL setting tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchro nized by the DLL all possible intermediate frequencies may not be guaranteed An application should use the next smaller JEDEC standard tCK AVG value 3 0 2 5 1 875 1 5 or 1 25 ns when calculat ing CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL where tCK AVG 3 0 ns should only be used for CL 5 calculation tCK AVG MAX limits Calculate tCK AVG tAA MAX CL SELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CL SELECTED Reserved settings are not allowed User must program a different value 5 Optional settings allow certain devices in the industry to support this setting however it is not a man 10 datory feature Refer to Hynix DIMM data sheet and or the DIMM SPD information if and how this set ting is supported Any DDR3 1066 speed bin also supports functional op
6. Es 0 0 60 wh gt 1 00 0 05 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 0 4 Jul 2010 Side 3 80mm max gt j je 1 00 0 08 mm gt le Units millimeters 51 hynix 256Mx64 HMT325S6BFR6C Front 67 60mm gt 20 gt I Si C A Ss l 4 00 0 10 l E i SPD i l Detail A i ly S Or D i Ne v pin 1 pin 403 wk 4 bd no nm al 39 00 2X1 80 0 10 ee la bey 3 00 Back U Oo O Detail of Contacts A N eo 10 o T H e c H S e b e Y F 0 45 0 03 H gt A gt 0 60 wh
7. S S o 9 z o e a Naa i 88 Peg gg 5g g com U HM gt 8 GB z E q q 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D VIII LG ee oe oF 3 BD ky hye a eo ee 9 oe 0 2 5 1 4 7 repeat Sub Loop 0 use BA 2 0 1 instead D Y 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead E k 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat Sub Loop 0 use BA 2 0 6 instead 7 28 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Table 6 IDD2NT and IDDQ2NT Measurement Loop Pattern v 2 9 D S o imimimiiz v8 2 BE relig E5 BS 38325 wei O HM gt 8 Gd E q q 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 110 0 0 0 0 0 0 0 0 0 2 D 1l1 1 1 0 0 0 0 0 F 0 3 D 1 1 1 1 0 0 0 0 0 F J oO 2 5 1 4 7 repeat Sub Loop 0 but ODT 2 0 and BA 2 0 2 1 D 9 2 8 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 8 3 12 15 repeat Sub Loop 0 but ODT 1 and BA 2 0 3 4 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 28 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 0 4 Jul 2010 45 hynix Table
8. CKO Cck TBD TBD pF CKE ODT CS Cem TBD TBD pF Address RAS CAS WE Ci TBD TBD pF DQ DM DOS DAS Cio TBD TBD pF Note 1 Pins not under test are tied to GND 2 These value are guaranteed by design and tested on a sample basis only Rev 0 4 Jul 2010 36 hynix IDD and I DDQ Specification Parameters and Test Conditions IDD and I DDQ Measurement Conditions In this chapter IDD and IDDQ measurement conditions such as test load and patterns are defined Figure 1 shows the setup and test load for IDD and IDDQ measurements IDD currents such as IDDO IDD1 IDD2N IDD2NT IDD2PO DD2P1 IDD2Q IDD3N IDD3P IDDAR IDDAW IDD5B IDD6 IDD6ET IDD6TC and IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDQ current is not included in IDD cur rents DDQ currents such as IDDQ2NT and IDDQ4R are measured as time averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDQ cur rents Attention IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2 In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using one merged power layer in Module PCB For IDD and IDDQ measurements the following definitions apply 0 and L
9. Jul 2010 14 hynix AC and DC I nput Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066 as specified in the table below DDR3 SDRAM will also support corresponding tDS values Table 41 and Table 47 in DDR3 Device Operation as well as derating tables in Table 44 of DDR3 Device Operation depending on Vih Vil AC lev els Single Ended AC and DC I nput Levels for DQ and DM DDR3 800 1066 DDR3 1333 1600 Symbol Parameter Unit Notes Min Max Min Max VIH CA DC100 DC input logic high Vref 0 100 VDD Vref 0 100 VDD V 1 VIL CA DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 V 1 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 VIL CA AC175 AC input logic low Note2 Vref 0 175 R V 1 2 VIH CA AC150 AC Input logic high Vref 0 150 Note2 Vref 0 150 Note2 V 1 2 VIL CA AC150 AC input logic low Note2 Vref 0 150 Note2 Vref 0 150 V 1 2 Reference Voltage for DQ k x A Vnetpa pc DM inputs 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD V 3 4 Notes 1 Vref 2 VrefDQ DC 2 Refer to Overshoot and Undershoot Specifications on page 27 3 The ac peak noise on Vref may not allow Vger to deviate from Vaerpo pc by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Rev 0 4 Jul 2010 15 hynix Vref Tolerances The dc tol
10. Notes 1 The swing of 0 2 x Vppg is based on approximately 50 of the static differential output high or low swing with a driver impedance of 4082 and an effective test load of 259 to Ver Vppo 2 at each of the differential outputs Rev 0 4 Jul 2010 23 hynix Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo ac and Vouac for single ended signals are shown in table and figure below Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VOL AC VOH AC Voun acy VoL Ac l DeltaTRse Single ended output slew rate for falling edge VoH AC VoL AC Vou acy VoL Ac l DeltaTFse Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test vOH AC Single Ended Output Voltage l e DQ Single Ended Output Slew Rate Definition Single Ended Output slew Rate Definition VIT vOI AC Output Slew Rate single ended DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 Parameter Symbol Min Max Min Max Min Max Min Max RER Single ended Output Slew Rate SRQse 2 5 5 2 5 5 2 5 5 TBD 5 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se S
11. VSELmax R tL xX 1 VSEL VSS or VSSQ ie a cube tee eee be eee ee Ge ai eet time Single ended requirements for differential signals Note that while ADD CMD and DQ signal requirements are with respect to Vref the single ended compo nents of differential signals have a requirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Rev 0 4 Jul 2010 19 hynix Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU DDR3 800 1066 1333 amp 1600 Symbol Parameter Unit Notes Min Max VSEH Single ended high level for strobes VDD 2 4 0 175 Note 3 V 1 2 Single ended high level for Ck CK VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DOS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if a reduced ac high or ac low level is used for a signal group then the reduced
12. 1 121 21 0 40 00 0 0 Ss repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0100 0 0 0 0 m repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 1 nRC 1 2 D D 1 0 0 0 0 0 00 0 0 F 0 2 3 1 nRC 3 4 DD 1 1 1 1 0 0 0 0 0 F 0 D 9 5i repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary 988 1 nRC nRAS PRE 0 0 1 0 0 0 0 0 0 Flo s repeat pattern 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL 43 Rev 0 4 Jul 2010 hynix Table 4 IDD1 Measurement Loop Pattern S S E S S Rala mlana U gi gg Pilg g i 8 8 3 5 3 3 amp ve r oZ 5 qT i SS 0 0 ACT 0 0 1 1 0 0 00 0 0 0 1 2 DD 1 0 0 0 0 0 00 0 0 0 3 4 DD 1 1 1 1 0 0 0 0 0 0 Vis repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 110 1 0 0 00 0 0 0 0 00000000 WM rep
13. 48 mA IDD6ET 60 60 60 mA IDD6TC 60 60 60 mA IDD7 520 680 720 mA 2GB 256M x 64 SO DI MM HMT325S6BFR6C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 340 380 380 mA IDD1 380 420 420 mA IDD2N 200 240 240 mA IDD2NT 280 320 360 mA IDD2PO 96 96 96 mA IDD2P1 120 120 120 mA IDD2Q 200 240 240 mA IDD3N 240 240 320 mA IDD3P 120 120 120 mA IDDAR 520 640 680 mA IDDAW 520 640 720 mA IDD5B 700 740 760 mA IDD6 96 96 96 mA IDD6ET 120 120 120 mA IDD6TC 120 120 120 mA IDD7 620 800 840 mA Rev 0 4 Jul 2010 49 hynix 2GB 256M x 64 SO DI MM HMT325S6BFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 360 400 440 mA IDD1 440 480 520 mA IDD2N 200 240 240 mA IDD2NT 256 280 320 mA IDD2PO 96 96 96 mA IDD2P1 120 120 120 mA IDD2Q 200 240 240 mA IDD3N 240 280 320 mA IDD3P 120 120 120 mA IDDAR 640 760 840 mA IDD4W 640 760 880 mA IDD5B 1200 1240 1280 mA IDD6 96 96 96 mA IDD6ET 120 120 120 mA IDD6TC 120 120 120 mA IDD7 880 1080 1160 mA 4GB 512M x 64 SO DI MM HMT351S6BFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 560 640 760 mA IDD1 640 720 840 mA IDD2N 400 480 480 mA IDD2NT 512 560 640 mA IDD2PO 192 192 192 mA IDD2P1 240 240 240 mA IDD2Q 400 480 480 mA IDD3N
14. 8 15 AM DA 0 7 DQ 0 7 DQ 0 7 DQ 0 7 LW DQ 48 55 D1 D9 D14 D6 z z z z S S SP S el K s S wisi smBBi fw lest ss Ble llli i se w lelsle E E EST he DQSO Ww Dos 2400hm I Lbos E Dos Sgr 4 pas 2400hm DOSO AMDOS a ee 1 DOS zm Dos 1 een DMO Me DM zwi 1 en e DM 2 WI DM MOL AW DOS7 D0 0 7 AN 1DQ 0 7 DQ 0 7 DQ 0 7 T DQ 0 7 w DM7 DO D8 D15 D7 IMA DQ156 43 z z z z 6 S a S El A E Si Se 6 6 wee sess wiles se BER WB sw sole wie 6s Bie t AAA 2400ohm 2400hm pees DOS ARE ieee SE Kos 1 ae 1 DM2 WwW Se ZANT Gi SE DM Awa NF TW DQI6 23 WA 7DQ 0 7 DQ 0 7 DQ 0 7 1 DQ 0 7 w ka D10 D13 D5 ww POS z S S Z LA 00140 47 z 3 3 S S E Mc w w 6 wee vyys ll vwe se we sess wos ses se V y e I The SPD may be integrated with the Temp Sensor or may be LR Vig een Vir a separate component v2 vi v9 V8 VoDSPD sons po j D e o D12 L6 pe VREFCA kans SIE VREFDQ D0 D15 X 89 Ll M PETETA WP gl v4 de E C cKO po 4 a D8 06 Dio D5 D7 Ee ae ScL SCL 9 pov SA0 A0 eg K p os saar ASPO ay soy a uc vm kan A Dem 5 DO 9 4 Di 4 D13 D15 d kel _ gt D8 D15 50 voo EVENT SR D8 D15 NOTES er 9v3 vit ru ODT0 p oo 1 DQ wiring may differ from that shown v2 V1 ji d however DO DM DQS and DQS rela Rank 0 m L pu v9 _ e WE oomi pos t
15. 82 AL 0 CS High between ACT RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cycling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 4 Rev 0 4 Jul 2010 39 hynix Symbol Description Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank lpp2N Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Precharge Standby ODT Current CKE High External clock On tCK CL see Table 1 BL 82 AL 0 CS stable at 1 Command Address Bank lpp2Nr Address Inputs partially toggling according to Table 6 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal toggling according to Table 6 Pattern Details see Table 6 Precharge Power Down Current Slow Exit CKE Low External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank pp2po Address Inputs stable at 0 Data lO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and R
16. Rev 0 4 Jul 2010 13 hynix AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Rating Symbol Parameter Units Notes Min Typ Max Notes 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together AC amp DC I nput Measurement Levels AC and DC Logic I nput Levels for Single Ended Signals AC and DC I nput Levels for Single Ended Command and Address Signals Single Ended AC and DC I nput Levels for Command and ADDress DDR3 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VIH CA DC100 DC input logic high Vref 0 100 VDD V 1 VIL CA DC100 DC input logic low VSS Vref 0 100 V 1 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 VIL CA AC175 AC input logic low Note2 Vref 0 175 V 1 2 VIH CA AC150 AC Input logic high Vref 0 150 Note2 V 12 VIL CA AC150 AC input logic low Note2 Vref 0 150 V 1 2 VRetCA DC Reference Voltage for ADD CMD inputs 0 49 VDD 0 51 VDD V 3 4 Notes 1 For input only pins except RESET Vref VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 27 3 The ac peak noise on Vref may not allow Vpe to deviate from Vgerca pc by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Rev 0 4
17. WW LDS eeng DM4 WA LDM d DQ 32 39 WA DQ 0 7 DQS5 AN UDQS DQS55 we UDO D2 S DM5 AN UDM z DQ 40 mA DQ 8 15 E D 2 O wig lis sw 8 Be DQs6 W7LDQS aye DQS6 Mie LDOS SS DM6 AM LDM L DQ 48 FAM DQ 0 7 DQS7 WW UDQS DQS7 W UDQs D3 DM7 AN UDM z DQ 56 63 WA DQ 8 15 S a Sie Oo ib 85s BI Vtt Rev 0 4 Jul 2010 Me AW ell CKO gt po p3 CKO gt p0 D3 cK p CKI p gt ODT1 NC 1 9 NC EVENT gt Temp Sensor RESET D0 D3 Terminated at near card edge Vtt DO D1 D2 D3 s NN Address and Control Lines NOTES 1 DQ wiring may differ from that shown however DQ DM DQS and DQS relation ships are maintained as shown Rank 0 Vtt nyni X 2GB 256Mx64 Module 2Rank of x16 SCL SCL sao AQ Temp Sensor SA1 Al with SPD S dk SDA 2 EVENT The SPD may be dL BENE integrated with t
18. commands ve are ignored but previous operations continue Rank 0 is selected by S0 Rank 1 is selected by S1 ODT 1 0 IN Active Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR3 High SDRAM mode register RAS CAS WE IN Active When sampled at the cross point of the rising edge of CK signals CAS RAS and WE i Low define the operation to be executed by the SDRAM V SECH Supply Reference voltage for SSTL15 inputs VREFCA BA 2 0 IN Selects which SDRAM internal bank of eight is activated During a Bank Activate command cycle defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read of Write com mand cycle defines the column address when sampled at the cross point of the rising A 9 0 edge of CK and falling edge of CK In addition to the column address AP is used to A10 AP invoke autoprecharge operation at the end of the burst read or write cycle If AP is high All IN autoprecharge is selected and BAO BAn defines the bank to be precharged If AP is low A12 BC autoprecharge is disabled During a Precharge command cycle AP is used in conjunction 15 13 with BAO BAn to control which bank s to precharge If AP is high all banks will be pre charged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge A12 BC is samples during READ and WRITE com mands to determine if burst chop on
19. g E 2 16 23 repeat Sub Loop 0 but BA 2 0 2 2 3 24 31 repeat Sub Loop 0 but BA 2 0 2 3 4 32 39 repeat Sub Loop 0 but BA 2 0 2 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 156 63 repeat Sub Loop 0 but BA 2 0 2 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL Rev 0 4 Jul 2010 46 hynix Table 9 IDD5B Measurement Loop Pattern a ke kel m S EE E eldskimis Pea B ieolsEBISBLiic 0 0 REF 0 0 0 1 0 0 0 0 1 12 D D 1 0 0 0 0 0 00 0 3 4 DD 1 1 1 1 0 0 00 0 5 8 repeat cycles 1 4 but BA 2 0 2 1 2 5 9 12 repeat cycles 1 4 but BA 2 0 2 D Y 13 16 repeat cycles 1 4 but BA 2 0 3 f k 17 20 repeat cycles 1 4 but BA 2 0 4 21 24 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 33 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 0 4 Jul 2010 47 hynix Table 10 IDD7 Measurement Loop Pattern ATTENTI ON Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern
20. kg 1 00 0 05 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 0 4 Jul 2010 2 55 KS 0 Side 3 80mm max gt 1 00 0 08 mm gt gt Units millimeters 52 hynix 256Mx64 HMT325S6BFR8C Front 67 60mm gt 20 gt I Si C A Ss l 4 00 0 10 l E i SPD i l Detail A i ly S Or D i Ne v pin 1 pin 403 wk 4 bd no nm al 39 00 2X1 80 0 10 ee la bey 3 00 Back U Oo O Detail of Contacts A N eo 10 o T H e c H S e b e Y F 0 45 0 03 H gt
21. us refresh interval 85 C Tease 95 C 3 9 3 9 3 9 3 9 3 9 us Rev 0 4 Jul 2010 29 hynix Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 34 Speed Bin DDR3 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data tap 15 20 ns ACT to internal read or write delay time facp 15 ns PRE command period ikp 15 ns ACT to ACT or REF command period fac 52 5 ns ACT to PRE command period has 37 5 9 tREFI ns CL 5 CWL 5 ck AvG 3 0 3 3 ns 1 2 3 4 10 CL 6 CWL 5 ck AvG 2 5 3 3 ns 1 2 3 Supported CL Settings 5 6 CK 10 Supported CWL Settings 5 cK Rev 0 4 Jul 2010 30 hynix DDR3 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 34 Speed Bin DDR3 1066F it Not CL nRCD nRP 7 7 7 ma Gs Parameter Symbol min max Internal read command to ACT to internal read or write delay time bon 13 125 PRE command period lap 13 125 ns ACT to ACT or REF i command period Be 30 022 ns ACT to PRE command Exc 37 5 9 tREFI ns period oe CWL 5 ck AVG 3 0 3 3 ns 1 2 3 4 6 10 7 CWL 6 cK AVG Reserved ns 4 Pis CWL 25 cK AV
22. z h l ple sess o SIBI ses sle DQS4 WLS IT ee SC DQ54 Am iOS L bQs DM4 AMH LDM A een oe DQ 32 39 AM DQ 0 7 DQ 0 7 pass WAubas L UDQS DQS5 WA UDas _ L UbQs DM5 NAN UDM D2 f UDM D6 DQ 40 47 AMA DO 8 15 A L 1DQ 8 15 Z z z 6 wR sw 8B fo ke vs Ble J poss WV 1005 n SCH DQS6 ANALD LD DM6 AN LDM Ds EN OEN DQ 48 55 VM DQ 0 7 DQ 0 7 R Me CS DQS7 20 S AN UDM D3 UDM D7 DQ 56 63 AM A PQ 8 15 z DQ 8 15 7 z z 6 w Esul m IIS sws 4 VE Me MM SE vi VDD VDD Rev 0 4 Jul 2010 Vtt 10 hynix 2GB 256Mx64 Module 1 Rank of x8 9 io ia 12 818 HH SCL past Dos DQS1 A pgs SA0 AO Temp seor DQ50 WA DOE DOS M DOS Sai al IW lt gt SDA DMO WA DM DM1 V DM A2 EVENT DQI0 7 V DQ 0 7 DQ 8 15 V DQ 0 7 The SPD may b i y be D4 EVENT integrated with the Temp E z Sensor or may be 6 9 a separate component kf sc SCL S Z SA0 A0 spp 6 6 io i i wlll 5s BB ma SDA T A2 WP Vig pit VDDSPD p SPD TS Dass Me DOS ZE MuherDOS VREFCA p D0 D7 AW DOS MM DOE DM2 ANA DM DM3 CIBO ZR viU VREFDQ p D0 D7 16 23 V DQ 0 7 DQ 24 31 AAALDQ 0 7 Voo rL A p D0 D7 D5 vss 1 D0 D7 SPD Temp sensor z z cko e cKO p D0 D7 a a CK1 _______p
23. 0 1 00 0 0 0 0 ees Repeat above D Command until 2 nFAW 2 nRRD 1 12 2 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 By eon er NRRD Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 7 D 1 0 0 0 0 7 00 0 0 0 0 13 IER Assert and repeat above D Command until A5 nFAW 1 if necessary a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 0 4 Jul 2010 48 hynix I DD Specifications Tcase O to 95 C Module IDD values in the datasheet are only a calculation based on the component IDD spec The actual measurements may vary according to DQ loading cap 1GB 128M x 64 SO DI MM HMT312S6BFR6C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 240 260 260 mA IDD1 280 300 300 mA IDD2N 100 120 120 mA IDD2NT 140 160 180 mA IDD2PO 48 48 48 mA IDD2P1 60 60 60 mA IDD2Q 100 120 120 mA IDD3N 120 120 160 mA IDD3P 60 60 60 mA IDDAR 420 520 560 mA IDD4W 420 520 600 mA IDD5B 600 620 640 mA IDD6 48 48
24. 480 560 640 mA IDD3P 240 240 240 mA IDDAR 840 1000 1160 mA IDD4W 840 1000 1200 mA IDD5B 1400 1480 1600 mA IDD6 192 192 192 mA IDD6ET 240 240 240 mA IDD6TC 240 240 240 mA IDD7 1081 1320 1480 mA Rev 0 4 Jul 2010 hynix Module Dimensions 128Mx64 HMT312S6BFR6C Front 67 60mm 20 i gt l l ee Xy 4 00 0 10 E l SPD l E S l 8 J l d Detail A h S D Secs Te v pin 1 pin 203 4 gt b 415 21 00 zn L i 39 00 2X1 80 0 10 e aE 3 00 Back U o O Detail of Contacts A FN e Tu to F 5 o H B Q 2 ai bu Ge Y 0 4540 03 gibt 4 gt
25. 5 0 03 A gt 0 60 WA 1 00 0 05 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 0 4 Jul 2010 2 55 ps 0 Side 3 80mm max gt 5 I 1 00 0 08 mm gt Units millimeters 54
26. 7 Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 8 AL CL 1 CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table 10 Data 10 read data burst with different data between one burst and the next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set MRO A 1 0 00B b Output Buffer Enable set MR1 A 12 0B set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RTT_Wr enable set MR2 A 10 9 10B c Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable or 1B to enable feature e Self Refresh Temperature Range SRT set MR2 A7 OB for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 0 4 Jul 2010 42 hynix Table 3 IDDO Measurement Loop Pattern l 8 9 3 S um ES z SRN mS y BZ SE EB IE BS 32 8 v 0 0 ACT 0 0 1 1 0 0100 0 0 1 2 DD 1 0 0 0 0 0 00 0 0 3 4 DD 1
27. 7 I DD4R and IDDQ4R Measurement Loop Pattern v e S g SIDlelpaleol o v8 i 2 fwase 8 8 8 2s Sk om 3 OS 8 qT 3 qd qd dc 0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 a D 1 0 0 0 0 0 00 O 0 0 0 2 3 DD 1 1 1 1 0 0 00 0 0 0 0 4 RD 0 1 0 T 0 0 000 0 F 0 00110011 5 D 1 0 0 0 0 0 000 0 F 0 2 6 7 DD 1 1 1 1 0 o o00 0 0 F0 E Y 1 8 15 repeat Sub Loop 0 but BA 2 0 1 8 k 2 16 23 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 2 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 8 IDDAW Measurement Loop Pattern Q L o m x o o lt EI pg Bg i 8 Pewee eS gE E F E om SES ERR g X 0 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 2 3 DD 1 1 1 1 1 0 00 0 0 0 0 4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011 c 5 D 1 0 0 0 1 0 00 0 0 F 0 g 2 6 7 DD 1 1 1 1 1 0 00 0 0 F 0 E 9 1 8 15 repeat Sub Loop 0 but BA 2 0 2 1
28. A gt 0 60 wh kg 1 00 0 05 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 0 4 Jul 2010 2 55 KS 0 Side 3 80mm max gt 1 00 0 08 mm gt gt Units millimeters 53 hynix 512Mx64 HMT351S6BFR8C Front 67 60mm 2 0 T gt l l l 4 0040 10 E S l l 8 l l l 8 E l l ite d Detail A etail B LI Ri Opes Seay ae nic REN G mmm 4 pin 1 pin 203 ban 21 00 gt h 39 00 gt 2 15 i 2Xb1 80 0 10 1 653010 3 00 Back O U O SPD Detail of Contacts A gt eo i eo T kal e e H S e b e Ra 0 4
29. G 2 5 3 3 ns 1 2 3 6 7 CWL 6 lck AVG Reserved ns 1 2 3 4 pies CWL 5 CK AVG Reserved ns 4 7 CWL 6 Keaue 1 875 2 5 ns 1 2 3 4 Bb CWL 5 fcK AVG Reserved ns 4 7 CWL 6 fcxave 1 875 2 5 ns 1 2 3 Supported CL Settings 5 6 7 8 lick 10 Supported CWL Settings 5 6 CK Rev 0 4 Jul 2010 31 hynix DDR3 1333 Speed Bins For specific Notes See Speed Bin Table Notes on page 34 Speed Bin DDR3 1333H CL nRCD nRP 9 9 9 unis ete Parameter Symbol min max eae E data na Mc m um ACT to internal read or Sien 13 5 _ ge write delay time 13 125 8 PRE command period lp E ns ACT to ACT or REF bc 49 5 u E command period 49 125 8 ARTS Se EH tras 36 9 tREFI ns CWL 25 ICK AVG 3 0 3 3 ns 1 2 3 4 7 10 CR CWL 6 7 Ick avG Reserved ns 4 CWL 25 ICK AVG 2 5 3 3 ns 1 2 3 7 CL26 CWL 6 ICK AVG Reserved ns 1 2 3 4 7 CWL 7 lck AVG Reserved ns 4 CWL 5 aver Reserved ns 4 1 875 2 5 CL 7 CWL 6 lck AVG ns 1 2 3 4 7 Optional CWL 7 ICK AVG Reserved ns 1 2 3 4 CWL 5 awe Reserved ns 4 CL28 CWL 6 lCK AVG 1 875 lt 2 5 ns 1 2 3 7 CWL 7 ICK AVG Reserved ns 1 2 3 4 Sr CWL 5 6 lck AvG Reserved ns 4 CWL 7 favo 1 5 lt 1 875 ns 1 2 3 4 CWL 5 6 ck AvG Reserved ns 4 CL 10 E lt 1 2 CWL 7 Fee Optional ce M Supported CL Settings 5 6 8 7 9 10 cK
30. Number Density Organization Component Composition oo HMT312S6BFR6C G7 H9 PB 1GB 128Mx64 128Mx16 H5TQ2G63BFR 4 1 HMT325S6BFR6C G7 H9 PB 2GB 256Mx64 128Mx16 H5TQ2G63BFR 8 2 HMT325S6BFR8C G7 H9 PB 2GB 256Mx64 256Mx8 H5TQ2G83BFR 8 1 HMT351S6BFR8C G7 H9 PB 4GB 512Mx64 256Mx8 H5TQ2G83BFR 16 2 Rev 0 4 Jul 2010 hynix Key Parameters CAS RAS MT s Grade ESK Latency RGD oan ERE CL tRCD tRP ns ns ns ns ns tCK DDR3 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 DDR3 1333 H9 1 5 9 13 5 13 5 36 49 5 9 9 9 DDR3 1600 PB 1 25 11 13 75 13 75 35 48 75 11 11 11 Speed Grade Frequency MHz Grade Remark CL5 CL6 CL7 CL8 CL9 CL10 CL11 G7 667 800 1066 1066 H9 667 800 1066 1066 1333 1333 PB 667 800 1066 1066 1333 1333 1600 Address Table 1GB 1Rx16 2GB 2Rx16 2GB 1Rx8 4GB 2Rx8 Refresh Method 8K 64ms 8K 64ms 8K 64ms 8K 64ms Row Address A0 A13 A0 A13 A0 A14 A0 A14 Column Address A0 A9 A0 A9 A0 A9 A0 A9 Bank Address BAO BA2 BAO BA2 BAO BA2 BAO BA2 Page Size 2KB 2KB 1KB 1KB Rev 0 4 Jul 2010 hynix Pin Descriptions Pin Name Description m Pin Name Description m CK 1 0 Clock Input positive line 2 DQ 63 0 Data Input Output 64 CK 1 0 Clock Input negative line 2 DM 7 0 Data Masks 8 CKE 1 0 Clock Enab
31. OW is defined as VIN lt Vii AC may e 1 and HIGH is defined as VIN gt Vinac may e MID LEVEL is defined as inputs are VREF VDD 2 Timing used for IDD and IDDQ Measurement Loop Patterns are provided in Table 1 e Basic IDD and IDDQ Measurement Conditions are described in Table 2 Detailed IDD and IDDQ Measurement Loop Patterns are described in Table 3 through Table 10 IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Qoff 0g Output Buffer enabled in MR1 RIT Nom RZQ 6 40 Ohm in MR1 RTT Wr RZQ 2 120 Ohm in MR2 TDQS Feature disabled in MR1 Attention The IDD and IDDQ Measurement Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started Define D CS RAS CAS WE HIGH LOW LOW LOW Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 0 4 Jul 2010 37 hynix Y Jop Y DDQ optional RESET SET DDR3 SE SDRAM CKE bas Das Att 25 Ohm CS 2 DQ DM Cl gt Vppaq 2 RAS CAS WE TDQS TDQS A BA ODT ZQ Vss Figure 1 Measurement Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test Load Ul Channel IDDQ IDDQ lO Power Simulation Simulation Simulation a
32. Q2 16 DQ6 67 DQ26 68 DQ30 119 A13 120 ODT1 171 DQS6 172 Vss 17 DQ3 18 DQ7 69 DQ27 70 DQ31 l21 1 122 NC 173 Vss 174 DQ54 19 Vss 20 Vss 71 Vss 72 Vss 123 Vpp 1124 Vpp 175 DQ50 176 DQ55 21 DQ8 22 DQ12 73 CKEO 74 CKE1 125 TEST 126 VreFCA 177 DQ51 178 Vss 23 DQ9 24 DQ13 75 Vpp 76 Vpp 127 Vss 128 Vss 179 Vss 180 DQ60 25 Vss 26 Vss 77 NC 78 A15 129 DQ32 130 DQ36 181 DQ56 182 DQ61 27 DQS1 28 DM1 79 BA2 80 A142 131 DQ33 132 DQ37 183 DQ57 184 Vss 29 DQS1 30 RESET 81 Vpp 82 Mon 133 Vss 1134 Vss 185 Vss 186 DQS7 31 Vss 32 Vss 83 A12 BC 84 All 135 DQS4 136 DM4 187 DM7 188 DQS7 33 DQ10 34 DQ14 85 A9 86 A7 137 DQS4 138 Vss 189 Vss 190 Vss 35 DQ11 36 DQ15 87 Vpp 88 Vpp 1139 Vss 140 DQ38 191 DQ58 192 DQ62 37 Vss 38 Vss 89 A8 90 A6 141 DQ34 142 DQ39 193 DQ59 194 DQ63 39 DQ16 40 DQ20 91 A5 92 A4 11143 DQ35 144 Vss 1195 Vss 196 Vss 41 DQ17 42 DQ21 931 Vpp 94 Vpp 145 Vss 146 DQ44 197 SAO 198 EVENT 43 Vss 44 Vss 195 A3 96 A2 147 DQ40 148 DQ45 199 VDDspp 200 SDA 45 DQS2 46 DM2 97 Al 98 AO M49 DQ41 150 Vss 201 SA1 202 SCL 47 DQS2 48 Vss 99 Von 100 Vpp 151 Vss 1152 DQS5 203 Vm 204 Vr 49 Vss 50 DQ22 101 CKO 102 CK1 153 DM5 154 DQS5
33. Rev 0 4 Jul 2010 40 hynix Symbol Description Operating Burst Read Current CKE High External clock On tCK CL see Table 1 BL 8 AL 0 CS High between RD Command Address Bank Address Inputs partially toggling according to Table 7 Data IO seamless read data burst with different DD4R data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 7 Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 8 AL 0 CS High between WR Command Address Bank Address Inputs partially toggling according to Table 8 Data IO seamless read data burst with different DD4W data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Pattern Details see Table 8 Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 1 BL 82 AL 0 CS High between REF Command IppsB Address Bank Address Inputs partially toggling according to Table 9 Data IO MID LEVEL DM stable at 0 Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled
34. SCL bus time to Vppspp on the system planar to act as a pullup OUT This signal indicates that a thermal event has been detected in the thermal sensing EVENT Active L device The system should guarantee the electrical level requirement is met for the dem ctive LOW EVENT pin on TS SPD part No pull up resister is provided on DI MM V Suppl Serial EEPROM positive power supply wired to a separate power pin at the connector GE pply which supports from 3 0 Volt to 3 6 Volt nominal 3 3V operation oer The RESET pin is connected to the RESET pin on the register and to the RESET pin on RESET IN the DRAM TEST Used by memory bus analysis tools unused NC on memory DIMMs Rev 0 4 Jul 2010 hyuix Pin Assignments Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Side Side Side Side Side Side Side Side 1 VrerDQ 2 Vss 53 DQ19 54 Vss 105 Vpp 106 Vpp 157 DQ42 158 DQ46 3 Vss 4 DQ4 155 Vss 56 DQ28 107 A10 AP 108 BAL 159 DQ43 160 DQ47 5 DO0 6 DQ5 57 DQ24 58 DQ29 109 BAO 110 RAS 161 Vss 162 Vss 7 DQ1 8 Vss 59 DQ25 60 Vss 111 Vpp 112 Vpp 163 DQ48 164 DQ52 9 Vss 10 DQSO 61 Vss 62 DQS3 113 WE 114 So 165 DQ49 166 DQ53 11 DMO 12 DQSO 63 DM3 64 DQS3 115 CAS 116 ODTO 167 Vss 168 Nee 13 Vss 14 Vss 65 Vss 66 Vss 117 Vpp 118 Vpp 169 DQS6 170 DM6 15 D
35. Supported CWL Settings 5 6 7 ick Rev 0 4 Jul 2010 32 hynix DDR3 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 34 Speed Bin DDR3 1600K CL nRCD nRP 11 11 11 Unit Note Parameter Symbol min max 13 75 simae RC gp a S ACT to internal read or iom 13 75 8 Se write delay time 13 125 13 75 PRE command period trp 13 125 5 ns ACT to ACT or REF D 48 75 8 WE command period 48 125 SES oo tras 35 9 tREFI ns CL 5 CWL 25 lCK AVG 3 0 3 3 ns L S S A CWL 6 7 Ick avG Reserved ns 4 CWL 25 lck AVG 2 5 3 3 ns 1 2 3 8 CL 6 CWL 6 amp xave Reserved ns 1 2 3 4 8 CWL 7 lck AVG Reserved ns 4 CWL 5 awe Reserved ns 4 CWL 6 tkavo me SE ns 1 2 3 4 8 CL 7 Optional CWL 7 ICK AVG Reserved ns 1 2 3 4 8 CWL 8 ck AvG Reserved ns 4 CWL 5 tekave Reserved ns 4 CL 8 CWL 6 lCK AVG 1 875 2 5 ns 1 2 3 8 CWL 7 lCK AVG Reserved ns 1 2 3 4 8 CWL 8 tekave Reserved ns 1 2 3 4 CWL 5 6 ck AvG Reserved ns 4 15 1 875 CL 9 CWL 7 ICK AVG Optional ns 1 2 3 4 8 CWL 8 awe Reserved ns 1 2 3 4 CWL 5 6 amp xave Reserved ns 4 CL210 CWL 7 lck AVG 1 5 1 875 ns 1 2 3 8 CWL 8 awe Reserved ns 1 2 3 4 cL 11 CME 5 67 fekvo Reserved ns 4 CWL 8 lck AVG 1 25 1 5 ns 1 2 3 Supported CL Settings 5 6 7 8 9
36. TT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Precharge Power Down Current Fast Exit jum CKE Low External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Precharge Quiet Standby Current SEN CKE High External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Active Standby Current CKE High External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank lppsN Address Inputs partially toggling according to Table 5 Data IO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 Active Power Down Current Ippap CKE Low External clock On tCK CL see Table 1 BL 8 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data lO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0
37. ea VDD Volts WA ygs Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Address and Control Overshoot and Undershoot Definition Rev 0 4 Jul 2010 27 hynix Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Clock Data Strobe and Mask DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 25 0 19 0 15 0 13 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 V ns CK CK DQ DQS Das DM See figure below for each parameter definition Maximum Amplitude Overshoot Area Undershoot Area Maximum Amplitude Time ns Clock Data Strobe and Mask Overshoot and Undershoot Definition Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 0 4 Jul 2010 28 hynix Refresh parameters by device density Refresh parameters by device density Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units RER command ANT or tRFC 90 110 160 300 350 ns REF command time Average periodic IREFI 0 C lt Tease lt 85 C 7 8 7 8 7 8 7 8 7 8
38. eat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 5 repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 1 nRC 1 2 DD 1 0 70 0 0 0 00 0 0 F 0 2 1 nRC 3 4 DDl l l l lolololololF o D Y ai repeat pattern nRC 1 4 until nRC nRCE 1 truncate if necessary 8 1 nRC nRCD RD 0 1 0 1 0 0 00 0 0 F o 00110011 s repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary 1 nRC nRAS PRE 0 O 1 0 0 0 00 0 0 F 0 T repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 0 4 Jul 2010 44 hynix Table 5 IDD2N and I DD3N Measurement Loop Pattern
39. erance limits and ac noise limits for the reference voltages ypefca and Vgerpo are illustrated in figure below It shows a valid reference voltage Vp t as a function of time Vger stands for VpercA and Vnetpo likewise Vref DC is the linear average of Vpo t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential Input Slew Rate Definition on page 22 Further more Vref t may temporarily deviate from Vger pc by no more than 1 VDD voltage VDD Vner t Ver ac noise Ret VRef DC max VDD 2 VRef DC min VRef DC Illustration of Vperpc tolerance and Vref ac noise limits The voltage levels for setup and hold time measurements Viu ac Viu pc ViL ac and Vii pc are depen dent on Vger Vref Shall be understood as Vgerpc as defined in figure above This clarifies that dc variations of Vger affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vger pc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with Vperac noise Timing and voltage effects due to ac noise on Vp up to the speci fied limit 1 of VDD are included in DRAM timings and
40. eration at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization Hynix DDR3 SDRAM devices supporting optional down binning to CL 7 and CL 9 and tAA tRCD tRP must be 13 125 ns or lower SPD settings must be programmed to match For example DDR3 1333H devices supporting down binning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600K devices supporting down binning to DDR3 1333H or DDR3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be programmed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin 35 ns 13 125 ns for DDR3 1600K For CL5 support refer to DIMM SPD information DRAM is required to support CL5 CL5 is not manda tory in SPD coding Rev 0 4 Jul 2010 34 hyuix Environmental Parameters
41. ew rate of CK CK is larger than 3 V ns 2 Refer to the table Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU on page 20 for VSEL and VSEH standard values Slew Rate Definitions for Single Ended I nput Signals See 7 5 Address Command Setup Hold and Derating on page 137 in DDR3 Device Operation for sin gle ended slew rate definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating on page 144 in DDR3 Device Operation for single ended slew rate definition for data signals Rev 0 4 Jul 2010 21 hynix Slew Rate Definitions for Differential nput Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in table and figure below Differential I nput Slew Rate Definition Measured Description x Defined by Min ax Differential input slew rate for rising edge TE T CK CK and DQS DQS VILdiffmax VIHdiffmin VIHdiffmin VILdiffmax Delta TRdiff Differential input slew rate for falling edge TP e CK CK and DQS DQS VIHdiffmin ViLdiffmax VIHdiffmin VlLdiffmax DeltaTFdiff Notes The differential signal i e CK CK and DQS DQS must be linear between these thresholds Differential nput Voltage i e DQS DQS CK CK I l l l l I E T 2 E 3 l Ldiffmax Differential Input Slew Rate Definition
42. for DQS DQS and CK CK Differential I nput Slew Rate Definition for DOS DOS and CK CK Rev 0 4 Jul 2010 22 hynix AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 VOH DC DC output high measurement level for IV curve linearity 0 8 x VDDQ V VOM DC DC output mid measurement level for IV curve linearity 0 5 X VDDQ V VoL DO DC output low measurement level for IV curve linearity 0 2 x VDDQ V VoH AC AC output high measurement level for output SR Vtr 0 1 x Vppo V 1 VoL AC AC output low measurement level for output SR Vr 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppg is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 2522 to Vrr Vppg 2 Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Differential AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 Voudift ac AC differential output high measurement level for output SR 0 2 x VDDQ V 1 VoLaiff aC AC differential output low measurement level for output SR 0 2 X VDDQ V 1
43. gt Terminated near z 2 TKI KI card edge w O w O 13 SIE z ig 218 2 5i s prc J ODT1 pc CKEI M NC EVENT p Temp Sensor RESET p D0 D7 DQS4 wh DOS DOSS wv LDOS DQS4 am DOS DQS5 AM IDOS UE DM4 AA 1DM DM5 Mt LDM 32 39 AN DQ 0 7 DQ 40 47 AAAr DQ 0 7 D6 V2 v3 V4 2 z D4 e pm e D e D S 9 S z 3 m 6 w 28 vws Be 9 12 18 FB 4 J C v2 V3 V4 DO Fe D pe D e D S DQ53 1pQs DOS A ipas DQ53 AAA DOS D057 wuer DOS DM3 A 1DM DM7 AV LDM 48 55 AA DQ 0 7 DQ 56 63 AAD 0 7 D7 t Address and Control Lines 2 6 NOTES a 1 DQ wiring may differ from that shown however DQ DM DQS and iw 8 Ble io 1518 s DQS relationships are maintained as shown Rank 0 1 Rev 0 4 Jul 2010 hynix 4GB 512Mx64 Module 2Rank of x8
44. he Temp Ka EVENT Sensor or may be a separate component SCL SCL SA0 AO SPD SA1 Al lt gt SDA A2 WP ae 4 Vit eko VDDSPD kt 9 SPD TS VREFCA t p D0 D7 VREFDQ p D0 D7 Vop ik D0 D7 Ve p D0 D7 SPD Temp sensor CKO po p3 CK1 _ D0 D7 cKO po p3 CKI p D0 D7 EVENT Temp Sensor RESET DO D7 V1 v2 v3 V4 e D e pm le D le D E V1 v2 v3 V4 DO HH D H D Lei D NOTES Address and Control Lines 1 DQ wiring may differ from that shown however DQ DM DQS and DQS relation ships are maintained as shown Rank 0 Rank 1 E 2 oot A Hin H E le Sls 8888 amp s TAE Liila LIE HH Doso Wj LD9s ST er d DQS0 ui DOE LDQS DMO AMH DM coh ete SE DQ 0 7 Me DQ 0 7 DQ 0 7 DOS Me UDOS t UDQS DOSI M UDO I UDQS DM WV qUDM DO UDM D4 DQ 8 15 MM DQ 8 15 x DQ 8 15 z z z 6 BBE sS Be io SB vs ele DQS22 WviLbQS SC BE M D S7 Me UDO D DM2 WW LDM 20a map Ge DQ 16 23 AMA DQ 0 7 DQ 0 7 DQS3 Me UDQS wem T DQS3 WAJUD0S _ ub e DM3 NNN UDM D1 Z UDM D5 DQ 24 31 AMW DQ 8 15 S DQ 8 15 A E
45. hyuix DDR3 SDRAM Unbuffered SODI MMs Based on 2Gb B die HMT312S6BFR6C HMT325S6BFR6C HMT325S6BFR8C HMT351S6BFR8C Hynix Semiconductor reserves the right to change products or specifications without notice Rev 0 4 Jul 2010 1 hynix Revision History Revision No History Draft Date Remark 0 1 Initial Release Dec 2009 Preliminary 0 2 Added IDD Speciricaion Feb 2010 Preliminary 0 3 Add supported CL5 Jun 2010 0 4 DIMM Outline Corrected Jul 2010 Rev 0 4 Jul 2010 hynix Description Hynix Unbuffered Small Outline DDR3 SDRAM DIMMs Unbuffered Small Outline Double Data Rate Syn chronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use Hynix DDR3 SDRAM devices These Unbuffered DDR3 SDRAM SODI MMs are intended for use as main memory when installed in systems such as mobile personal computers Features e VDD 1 5V 0 075V e VDDQ 1 5V 0 075V e VDDSPD 3 0V to 3 6V Functionality and operations comply with the DDR3 SDRAM datasheet 8 internal banks Data transfer rates PC3 10600 PC3 8500 or PC3 6400 Bi directional Differential Data Strobe 8 bit pre fetch Burst Length BL switch on the fly BL 8 or BC Burst Chop 4 On Die Termination ODT supported RoHS compliant This product is in compliance with the RoHS directive Ordering I nformation Part
46. in Mode Registers ODT Signal stable at 0 Pattern Details see Table 9 Self Refresh Current Normal Temperature Range Tease 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Ipb6 Low External clock Off CK and CK LOW CL see Table 1 BL 8 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Self Refresh Current Extended Temperature Range Tease 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended Jppeer CKE Low External clock Off CK and CK LOW CL see Table 1 BL 8 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Rev 0 4 Jul 2010 41 hynix Symbol Description Ipperc Auto Self Refresh Current Tease 0 95 C Auto Self Refresh ASR Enabled Self Refresh Temperature Range SRT Normal CKE Low External clock Off CK and CK LOW CL see Table 1 BL 82 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Auto Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL pp
47. ingle ended Signals For Ron RZQ 7 setting Rev 0 4 Jul 2010 24 hynix Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and VOHdiff AC for differential signals as shown in table and Figure below Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VoLaiff AC Vondit ac Vonaitt ac VoLaitt ac DeltaTRdiff Differential output slew rate for falling edge Vouditt AC Votaitt ac Vouditt AC Mota acy DeltaTFdiff Notes 1 Output slew rate is verified by design and characterization and may not be subject to production test Differential Output Voltage i e DQS DQS P M vOHdiff AC o E EE B vOLdiff AC Differential Output Slew Rate Definition Differential Output slew Rate Definition Differential Output Slew Rate DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 Unit nits Parameter Symbol Min Max Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 TBD 10 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Rev 0 4 Jul 2010 25 hynix Reference Load for AC Timing and Ou
48. ionships are maintained as shown EVENT __ gt Temp Sensor Rank 1 RESET gt 00 015 Rev 0 4 Jul 2010 12 hynix Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss 0 4 V 1 975 V V 1 VDDQ Voltage on VDDQ pin relative to Vss 0 4 V 1 975 V V 1 Vin Vout Voltage on any pin relative to Vss 0 4 V 1 975 V V 1 Tstg Storage Temperature 55 to 100 oC 1 2 Notes l Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may affect reliability Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to J ESD51 2 standard VDD and VDDQ must be within 300mV of each other at all times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mvV DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Rating Units Notes T Normal Operating Temperat
49. les 2 DQS 7 0 Data strobes 8 RAS Row Address Strobe 1 DQS 7 0 Data strobes negative line 8 CAS Column Address Strobe 1 EVENT Temperature event pin 1 WE Write Enable ZEE Eo UE S 1 0 Chip Selects 2 RESET Reset Pin 1 EU Address Inputs 14 Vpp Core and 1 0 Power 18 A10 AP Address Input Autoprecharge 1 Vss Ground 52 A12 BC Address Input Burst chop 1 BA 2 0 SDRAM Bank Addresses 3 VnEFDQ 1 Input Output Reference ODT 1 0 On Die Termination Inputs 2 VREFCA 1 SCL Geier SE SESCH 1 Ver Termination Voltage 2 SDA SPD Data Input Output 1 Vppspp SPD Power 1 SA 1 0 SPD Address Inputs 2 NC Reserved for future use 2 Total 204 Rev 0 4 Jul 2010 5 hynix I nput Output Functional Descriptions Symbol Type Polarity Function um The system clock inputs All address and command lines are sampled on the cross point CKO0 CKO IN Cross Point of the rising edge of CK and falling edge of CK A Delay Locked Loop DLL circuit is CK1 CK1 driven from the clock inputs and output timing for read operations is synchronized to the input clock Active Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when CKE 1 0 IN High low By deactivating the clocks CKE low initiates the Power Down mode or the Self g Refresh mode Active Enables the associated DDR3 SDRAM command decoder when low and disables the S 1 0 IN L command decoder when high When the command decoder is disabled new
50. level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 27 Differential I nput Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in the table below The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS Rev 0 4 Jul 2010 Vix Definition VDD VSS r CK DQS CK DQS 20 hynix Cross point voltage for differential input signals CK DQS DDR3 800 1066 1333 amp 1600 Symbol Parameter Unit Notes Min Max V Differential Input Cross Point Voltage 150 150 mV od relative to VDD 2 for CK CK 175 175 mV 1 Differential Input Cross Point Voltage Vix relative to VDD 2 for DS DOS Ge Ge my Notes 1 Extended range for Vix is only allowed for clock and if single ended clock input signals CK and CK are monotonic with a single ended swing VSEL VSEH of at least VDD 2 250 mV and when the differential sl
51. o Overshoot and Undershoot Specifications on page 27 Allowed time before ringback tDVAC for CK CK and DQS DOS tDVAC ps tDVAC ps Slew Rate V ns VIH Ldiff ac 350mV VIH Ldiff ac 300mV min max min max gt 4 0 75 175 4 0 57 E 170 8 3 0 50 E 167 2 0 38 163 1 8 34 162 e 1 6 29 161 1 4 22 159 1 2 13 155 1 0 0 150 lt 1 0 0 150 i Rev 0 4 Jul 2010 18 hynix Single ended requirements for differential signals Each individual component of a differential signal CK DQS DQSL DQSU CK DOS DQSL of DQSU has also to comply with certain requirements for single ended signals CK and CK have to approximately reach VSEHmin VSELmax approximately equal to the ac levels VIH ac VIL ac for ADD CMD signals in every half cycle DQS DQSL DQSU DQS DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac MIL ac for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if VIH CA AC150 VIL CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK VDD or VDDQ VSEHmin 7 7 7 fy T VDD Zor VDDQ 2 2 Lz 2 2l 2 X 2 22 CK or DQS
52. than Sub Loops 0 9 Q L o s 8 og S u e 2 d5 RMS 5 zl SE E ele ee B8 S 8 3 g SS ren 0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 i repeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 1 nRRD 1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 ai repeat above D Command until 2 nRRD 1 2 2 nRRD repeat Sub Loop 0 but BA 2 0 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 T 5 9 nFAW 4 nRRD D 1 0 0 0 0 7 00 0 0 F 0 X Assert and repeat above D Command until 2 nFAW 1 if necessary S 2 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 e a 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 EE Repeat above D Command until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 11 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0
53. the fly will be performed HIGH no burst chop LOW burst chopped DQ 63 0 1 0 Data Input Output pins Rete The data write masks associated with one data byte In Write mode DM operates as a DM 7 0 IN High byte mask by allowing input data to be written if it is low but blocks the write operation g if it is high In Read mode DM lines have no effect Vow apen Suppl lies fi O Serial d d for the modul Vss upply Power supplies for core UO Serial Presence Detect and ground for the module The data strobes associated with one data byte sourced with data transfers In Write DQS 7 0 mode the data strobe is sourced by the controller and is centered in the data window DOS 7 0 1 0 Cross Point n Read mode the data strobe is sourced by the DDR3 SDRAMs and is sent at the lead i ing edge of the data window DQS signals are complements and timing is relative to the crosspoint of respective DQS and DQS SA 1 0 IN 8 These signals are tied at the system planar to either Vss or Vppspp to configure the i serial SPD EEPROM address range Rev 0 4 Jul 2010 hynix Symbol Type Polarity Function This bidirectional pin is used to transfer data into or out of the SPD EEPROM A resistor SDA 1 0 must be connected from the SDA bus line to Vppspp on the system planar to act as a pullup SCL IN This signal is used to clock data into and out of the SPD EEPROM A resistor may be con B nected from the
54. their associated deratings Rev 0 4 Jul 2010 16 hynix AC and DC Logic I nput Levels for Differential Signals Differential signal definition EET UE E EEN Tt EE EE WEE SE half cycle TEE Differential Input Voltage i e DQS DQS CK CK VILDIFRACMAX em menge Definition of differential ac swing and time above ac level tpyac Rev 0 4 Jul 2010 17 hynix Differential swing requirements for clock CK CK and strobe DQS DQS Differential AC and DC I nput Levels DDR3 800 1066 1333 amp 1600 Symbol Parameter Unit Notes Min Max VIHdiff Differential input high 0 200 Note 3 V 1 VILdiff Differential input logic low Note 3 0 200 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 VILdiff ac Differential input low ac Note 3 2 x VIL ac Vref V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK use VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DOS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer t
55. tput Slew Rate Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ VTT VDDQ 2 Reference Load for AC Timing and Output Slew Rate Rev 0 4 Jul 2010 26 hynix Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 V ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 V ns A0 A15 BAO BA3 CS RAS CAS WE CKE ODT See figure below for each parameter definition Maximum Amplitude Overshoot Ar
56. ure Range 0 to 85 C 1 2 OPER Extended Temperature Range 85 to 95 C 1 3 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea surement conditions please refer to the J EDEC document J ESD51 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must be maintained between 0 85 C under all operating conditions Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to the DIMM SPD for option availability b If Self Refresh operation is required in the Extended Temperature Range then it is mandatory to either use the Manual Self Refresh mode with Extended Temperature Range capability MR2 A6 0b and MR2 A7 1b or enable the optional Auto Self Refresh mode MR2 A6 1b and MR2 A7 Ob Hynix DDR3 SDRAMs sup port Auto Self Refresh and Extended Temperature Range and please refer to Hynix component datasheet and or the DIMM SPD for tREFI requirements in the Extended Temperature Range
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