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Intel Xeon 7041

1. Table 4 1 Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Cont d Pin Name Pin No Pa Direction Pin Name Pin No B m Direction A3 A22 Source Sync Input Output A28 E13 Source Sync Input Output A4 A20 Source Sync Input Output A29 D12 Source Sync Input Output A5 B18 Source Sync Input Output A30 C11 Source Sync Input Output A6 C18 Source Sync Input Output A31 B7 Source Sync Input Output A7 A19 Source Sync Input Output A32 A6 Source Sync Input Output A8 C17 Source Sync Input Output A33 A7 Source Sync Input Output A9 D17 Source Sync Input Output A34 C9 Source Sync Input Output A10 A13 Source Sync Input Output A35 C8 Source Sync Source Sync Adis B16 Source Sync Input Output A36 F16 Source Sync Source Sync A124 B14 Source Sync Input Output A37 F22 Source Sync Source Sync A13 B13 Source Sync Input Output A38 B6 Source Sync Source Sync A14 A12 Source Sync Input Output A39 C16 Source Sync Source Sync A15 C15 Source Sync Input Output A20M4 F27 AsyncGTL Input A16 C14 Source Sync Input Output ADS D19 Common Clk Input Output A178 D16 Source Sync Input Output ADSTBO F17 Source Sync Input Output A18 D15 Source Sync Input Output ADSTB1 F14 Source Sync Input Output A19 F15 Source Sync Input Outp
2. Register Command R W Reset State RESERVED 00h N A RESERVED Ch 1 Temp Value 01h R 0000 0000 Status Register 1 02h R Undefined Configuration Register 03h R 0000 0000 Conversion Rate Register 04h R 0000 0111 RESERVED2 05h 06h N A RESERVED Ch 1 Temp High Limit 07h R 0101 0101 Ch 1 Temp Low Limit 08h R 0000 0000 Configuration Register 1 09h W 0000 0000 Conversion Rate Register OAh W 0000 0111 RESERVED OBh OCh N A RESERVED Ch 1 Temp High Limit 0Dh W 0101 0101 Ch 1 Temp Low Limit OEh W 0000 0000 One shot OFh w N A RESERVED2 10h N A RESERVED Ch 1 Temp Offset 11h R W 0000 0000 RESERVED 12h 22h N A RESERVED Status Register 2 23h R 0000 0000 RESERVED 24h 29h N A RESERVED Ch 2 Temp Value 30h R 0000 0000 Ch 2 Temp High Limit 31h R W 0101 01010 Ch 2 Temp Low Limit 32h R W 0000 0000 RESERVED 33h R 0000 0000 Ch 2 Temp Offset 34h R W 0000 0000 RESERVED 35h FEh N A RESERVED Die Revision Code FFh R 1001 XXXX NOTES 1 Bit 3 of Configuration register 1 must be set to 0 default value is 0 2 Writing to RESERVED bits may cause unexpected results RESERVED bits that must be correctly programmed are identified in the register definitions in the following section Reading from RESERVED bits will return unknown values 3 The 4 least significant bits of the thermal sensor die revision code may change and should not be used
3. Offset Section Bits Function Notes Cache Data 25 26h 16 Reserved Reserved for future use 27 28h 16 L2 Cache Size per core 16 bit hexadecimal number in KB 29 2Ah 16 L3 Cache Size 16 bit hexadecimal number in KB 2B 2Ch 16 Processor Cache VID 16 bit hexadecimal Vcache value requested by CVID output in mV 2D 2Eh 16 Cache Voltage Minimum 16 bit hexadecimal Vcache value Minimum Processor DC Cache Voltage in in mV 2F 30h 16 Reserved Reserved 31h 8 Checksum 1 byte checksum Package Data 32 35h 32 Package Revision Four 8 bit ASCII characters 36h 8 Reserved Reserved for future use 37h 8 Checksum 1 byte checksum Part Number Data 38 3Eh 56 Processor Part Number Seven 8 bit ASCII characters 3F 4Ch 112 Reserved Reserved 4D 54h 64 Processor Electronic 64 bit identification number Signature 55 GEN 208 Reserved Reserved 6Fh 8 Checksum 1 byte checksum Thermal Ref Data 70h 8 Reserved Reserved 71 72h 16 Reserved Reserved 73h 8 Checksum 1 byte checksum Feature Data 32 Processor Core Feature From CPUID function 1 EDX contents 74 77h Flags 8 Processor Feature Flags 7 Multi Core 6 Serial Signature 5 Electronic Signature Present 78h 4 Thermal Sense Device Present 3 Thermal Reference Byte Present 2 OEM EEPROM Present 1 Core VID Present 0 L3 Cache Present 8 Processor Thread and Core 7 4 Reserved 79h Information 8
4. Dual Core Intel Xeon Processor 7000 Series Datasheet 34 Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 2 2 40 2 133Hs SuiAVHO 31Y28 LON OG 1 2 31V2S A38 HIER 38M0N N IMYYA 2 3003 aevo Jus 1N3NLBYd30 REV 2 SHT C91394 DWG NO 006 Lgi MALA 01108 6S0 LH913H IN3NOdMNOO 318VMO11V XVN E 00 291 EEN SE Ze P 3ovwovd WII 3018 IA dOl ery Gell Xe rer 96 6 6 eG d V3uv 3H91VH SSOWUD 110431 IN3NOdNO 610 1H913H LN3NOdNOD 318VM011Y IN c X 90 L 19 Xe 35 Dual Core Intel Xeon Processor 7000 Series Datasheet Mechanical Specifications n 3 2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements A thermal and mechanical solution design must not intrude into the required keepout zones Decoupling capacitors are typically mounted to either the topside or pin side of the package substrate See Figure 3 2 and Figure 3 3 for keepout zones 3 3 Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package T
5. 100 Bottom Side Board Keepout Zones 101 Board Mounting Hole Keepout Zones 102 Thermal Solution Volumetric men nn nana Ak KA kk 103 Recommended Processor Layout and Pitch mmm eee 104 Features of the Dual Core Intel Xeon Processor 7000 Series 12 Core Frequency to Front Side Bus Multiplier Configuration 16 BSEL 1 0 Frequency Table for BCLK 1 0 nenea eee 16 Voltage Identification VID Definition eese 19 Front Side Bus Pin Groupe 21 Signal Description Table 22 Signal Reference Voltages sse nnns 22 Processor Absolute Maximum Ratings mmm nenea enma 23 Voltage and Current Specifications mm eee nenea anna 24 VCC Static and Transient Tolerance nenea nenea ana 27 Voce Overshoot Specifications nenea nenea ae aaa ea a eee aaa aaa 28 Front Side Bus Differential BCLK Specifications 29 BSEL 1 0 VID 5 0 and DC Specifications nene nenea nea 30 VIDPWRGD DC Specifications mmm nn nea mean na 30 AGTL Signal Group DC Specifications mm eee 30 PWRGOOD Input and TAP Signal Group DC Specificatione 30 7 1 7 3 7 4 7 5 7 6 7 7 7 8 7 9 7 10 7 11 7 12 7 13 7 14 7 15 7 16 7 17 7 18 7 19 7 20 7 21 7 22 GTL Asynchronous and AGTL Asynchronous Signal Group DG Specificat
6. 0 e0000000K 8 Lle e e e e e e e e ee ee e ee e l lt gt Ml e e e Processor e e e e e e e e M o S Noeoeoeoeo 9 0000000N gt Peoeoceoceoe e e e e e e e e e P o Rle e e e e e e e o Bottom View e e e e R Tle e e e e e e e e e e e e T ul e e e e e e e e U vle e e e e e e e e e e e eV We e e e e o 00oOlo eo olw Yeo 9 O O 0 0 0 0 0 6 000000000000 ole o e Y AA e 0 0 0 0 00000000000000 0 0 e e o e e AA ABleeooeocoeooeooeoooeocoeooeooje e o e e AB AC O 6 0 0 0 0 6 0 O0 0 0 0 0 0 0 0 0 0j0 9 e e AC ADeeoooeooeooeooeoeooeooeoo j0 0 e O Ap AE 000606000006000600006000600000 00909 AE 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 DATA CLOCKS O Signal GTLREF Power Reserved No Connect Ground V 40 Dual Core Intel Xeon Processor 7000 Series Datasheet 4 Pin Listing 4 1 Dual Core Intel Xeon Processor 7000 Series Pin Assignments Section 2 5 contains the front side bus signal groups for the Dual Core Intel Xeon processor 7000 series see Table 2 4 This section provides a sorted pin list in Table 4 1 and Table 4 2 Table 4 1 is a listing of all processor pins ordered alphabetically by pin name Table 4 2 is a listing of all processor pins ordered by pin number 4 1 1 Pin Listing by Pin Name
7. Dual Core Intel Xeon Processor 7000 Series Datasheet Revision 2 1 September 2006 Document Number 309626 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Dual Core Intel Xeon Processor 7000 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request 64 bit computing on Intel architecture requires a co
8. BPM5 Common Clk Input Output C26 IGNNE Async GTL Input E5 IERR Async GTL Output C27 SMI Async GTL Input E6 Voc Power Other C28 Don t Care E7 BPM2 Common Clk Input Output C29 Vgg Power Other E8 BPM4 Common Clk Input Output C30 Vcc Power Other E9 Vss Power Other C31 Don t Care E10 APO Common Clk Input Output D1 Don t Care E11 BR2 Common Clk Input Output D2 Vss Power Other E12 Mer Power Other D3 VID2 Power Other Output E13 A28 Source Sync Input Output D4 STPCLK Async GTL Input E14 A24 Source Sync Input Output D5 Vss Power Other E15 Vsg Power Other D6 INIT Async GTL Input E16 Reserved D7 MCERR Common Clk Input Output E17 Vgs Power Other D8 Mee Power Other E18 DRDY Common Clk Input Output D9 AP1 Common CIk Input Output E19 TRDY Common CIk Input D10 BR34 Common Clk Input Output E20 Mee Power Other D11 Vss Power Other E21 RSO Common Clk Input D12 A29 Source Sync Input Output E22 HIT Common CIk Input Output D13 A254 Source Sync Input Output E23 Vgs Power Other Di4 Voc Power Other E24 TCK TAP Input D15 A18 Source Sync Input Output E25 TDO TAP Output D16 A17 Source Sync Input Output E26 Vcc Power Other D17 A9 Source Sync Input Output E27 FERR PBE Async GTL Output D18 Voc Power Other E28 Vcc Power Other D19 ADS Common Clk Input Output E29 Vss Power Other D20 BRO Common Clk Input Output E30 Mee Power Other D21 Vss Power Other E31 Vss
9. Power Other Vss P9 Power Other Vss V25 Power Other Vss P23 Power Other Vss V27 Power Other Vss P25 Power Other Vss V29 Power Other Vss P27 Power Other Vss V31 Power Other Vss P29 Power Other Vss we Power Other Vss P31 Power Other Vss W4 Power Other Vss R2 Power Other Vss W24 Power Other Vss R4 Power Other Vss W26 Power Other Vss R6 Power Other Vss W28 Power Other Vss R8 Power Other Vss W30 Power Other Vss R24 Power Other Vss Y1 Power Other Vss R26 Power Other Vss Y3 Power Other Vss R28 Power Other Vss Y5 Power Other Vss R30 Power Other Vss Y7 Power Other Vss T1 Power Other Vss Y13 Power Other Vss T3 Power Other Vss Y19 Power Other Vss T5 Power Other Vss Y25 Power Other Vss T7 Power Other Vss AA2 Power Other Vss T9 Power Other Vss AA9 Power Other Vss T23 Power Other Vss AA15 Power Other Vss T25 Power Other Vss AA17 Power Other Vss T27 Power Other Vss AA23 Power Other Vss T29 Power Other Vss AA30 Power Other Vss T31 Power Other Vss AB1 Power Other Vss U2 Power Other Vss AB5 Power Other Vss U4 Power Other Vss AB11 Power Other Vss U6 Power Other Vss AB21 Power Other Vss U8 Power Other Vss AB27 Power Other Vss U24 Power Other Vss AB31 Power Other Vss U26 Power Other Vss AC2 Power Other Vss U28 Power Other Vss AC7 Power Other Vss U30 Power Other Vss AC13 Power Other Vss V1 Power Other Vss AC19 Power Other Vss V3 Power Other Vss AC25 Power Other Vss V5 Power Other Vss AD3 Power Other Vs
10. S Slave Address Write A Command Code A Data A P 1 7 bits 1 1 8 bits 1 8 bits 1 1 SMBus Thermal Sensor The processor s SMBus thermal sensor provides a means of acquiring thermal data from the processor The thermal sensor is composed of control logic SMBus interface logic precision analog to digital converters and precision current sources The sensor drives a small current through the p n junction of a thermal diode located on each processor core The forward bias voltage generated across the thermal diode is sensed and the precision A D converter derives a single byte of thermal reference data or a thermal byte reading The nominal precision of the least significant bit of a thermal byte is 1 Celsius The processor incorporates the SMBus thermal sensor onto the processor package consistent with past members of the Intel Xeon processor family Upper and lower thermal reference thresholds for each core can be individually programmed for the SMBus thermal sensor Comparator circuits sample the register where the single byte of thermal data for each core thermal byte reading is stored These circuits compare the single byte result against programmable threshold bytes If enabled the alert signal on the processor SMBus SM_ALERT will be asserted when the sensor detects that either core s threshold is reached or crossed Analysis of SMBus thermal sensor data may be useful in detecting changes in the system
11. as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the Dual Core Intel Xeon processor 7000 series heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide Dual Core Intel Xeon Processor 7000 Series Datasheet 107 Debug Tools Specifications Ntel T 108 Dual Core Intel Xeon Processor 7000 Series Datasheet
12. 025 VID 0 045 VID 0 065 1 2 3 25 VID 0 031 VID 0 051 VID 0 071 1 2 3 30 VID 0 038 VID 0 058 VID 0 077 1 2 3 35 VID 0 044 VID 0 064 VID 0 084 1 2 3 40 VID 0 050 VID 0 070 VID 0 090 1 2 3 45 VID 0 056 VID 0 076 VID 0 096 1 2 3 50 VID 0 063 VID 0 083 VID 0 103 1 2 3 55 VID 0 069 VID 0 089 VID 0 109 1 2 3 60 VID 0 075 VID 0 095 VID 0 115 1 2 3 65 VID 0 081 VID 0 101 VID 0 121 1 2 3 70 VID 0 087 VID 0 108 VID 0 128 1 2 3 75 VID 0 094 VID 0 114 VID 0 134 1 2 3 80 VID 0 100 VID 0 120 VID 0 140 1 2 3 85 VID 0 106 VID 0 126 VID 0 147 1 2 3 90 VID 0 112 VID 0 133 VID 0 153 1 2 3 95 VID 0 119 VID 0 139 VID 0 159 1 2 3 100 VID 0 125 VID 0 145 VID 0 165 1 2 3 105 VID 0 131 VID 0 151 VID 0 172 1 2 3 110 VID 0 137 VID 0 158 VID 0 178 1 2 3 115 VID 0 144 VID 0 164 VID 0 184 1 2 3 120 VID 0 150 VID 0 170 VID 0 190 1 2 3 125 VID 0 156 VID 0 177 VID 0 197 1 2 3 130 VID 0 162 VID 0 183 VID 0 203 1 2 3 135 VID 0 169 VID 0 189 VID 0 209 1 2 3 140 VID 0 175 VID 0 195 VID 0 216 1 2 3 145 VID 0 181 VID 0 202 VID 0 222 1 2 3 150 VID 0 187 VID 0 208 VID 0 228 1 2 3 NOTES 1 The Vcc min and Vcc max loadlines represent static and transient limits 2 This table is intended to aid in reading discrete points on Figure 2 4 3 The loadlines specify voltage limits at the die measured at the VCCSENSE and VSSSENCE pins Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc and Vss pins Refer to the Voltage R
13. BIOS Writer s Guide BWG for specific information to enable and configure Enhanced Intel SpeedStep technology in BIOS System Management Bus SMBus Interface The Dual Core Intel Xeon processor 7000 series package includes an SMBus interface which allows access to a memory component with two sections referred to as the Processor Information ROM and the Scratch EEPROM and a thermal sensor on the substrate The SMBus thermal sensor may be used to read the thermal diode mentioned in Section 6 2 7 These devices and their features are described below The SMBus thermal sensor and its associated thermal diode are not related to and are completely independent of the precision on die temperature sensor and TCC of the Thermal Monitor feature discussed in Section 6 2 1 Dual Core Intel Xeon Processor 7000 Series Datasheet Features The processor SMBus implementation uses the clock and data signals of the System Management Bus SMBus Specification It does not implement the SMBSUS signal Layout and routing guidelines are available in the appropriate platform design guide document For platforms which do not implement any of the SMBus features found on the processor all of the SMBus connections except SM VCC to the socket pins may be left unconnected SM_ALERT SM CLK SM DAT SM EP A 2 0 SM TS A 1 0 SM WP Figure 7 2 Logical Schematic of SMBus Circuitry 7 4 1 Dual Core Intel Xeon Processor 7000 Series Datasheet SM
14. GTL Input TESTHI2 W8 Power Other Input REQO B19 Source Sync Input Output TESTHIS Y6 Power Other Input REQ1 B21 Source Sync Input Output TESTHI4 AA7 Power Other Input REQ2 C21 Source Sync Input Output TESTHI5 AD5 Power Other Input REQ3 C20 Source Sync Input Output TESTHI6 AE5 Power Other Input REQ4 B22 Source Sync Input Output THERMTRIP F26 Async GTL Output Reserved C1 TMS A25 TAP Input Reserved E16 TRDY E19 Common Clk Input Reserved W3 TRST F24 TAP Input Reserved Y27 Voc A8 Power Other Reserved Y28 Voc A14 Power Other Reserved AC1 Voc A18 Power Other Reserved AE30 Vcc A24 Power Other RESET Y8 Common CIk Input Vcc B20 Power Other RSO E21 Common Clk Input Vcc C4 Power Other RS1 D22 Common Clk Input Vcc C22 Power Other RS2 F21 Common Clk Input Voc C30 Power Other RSP C6 Common Clk Input Voc D8 Power Other SKTOCC A3 Power Other Output Vec D14 Power Other 44 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Pin Listing Table 4 1 Pin Listing by Pin Name Cont d Table 4 1 Pin Listing by Pin Name Cont d Pin Name Pin No ns Direction Pin Name Pin No o ae Direction Voc D18 Power Other Voc L2 Power Other Voc D24 Power Other Voc L4 Power Other Voc D31 Power Other Voc L6 Power Other Voc E6 Power Other
15. Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the A 32 Intel Architecture Software Developer s Manual Volume III System Programmer s Guide for more information The system can generate a STPCLK while the processor is in the HALT Power Down state When the system deasserts the STPCLK interrupt the processor returns execution to the HALT state While in HALT Power Down state the processor processes bus snoops and interrupts Figure 7 1 Stop Clock State Machine 7 2 3 74 HALT or MWAIT Instruction and HALT Bus Cycle Generated N Stat y gt Enhanced HALT or HALT State urs j e i INIT BINIT INTR NMI SMI BCLK running 9rmarcexecuuon RESET FSB interrupts Snoops and interrupts allowed A Snoop Snoop Event Event Occurs Serviced STPCLK STPCLK Asserted De asserted Y Enhanced HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Y Stop Grant State Snoop Event Occurs Stop Grant Snoop State BCLK running BCLK running Snoops and interrupts allowed Snoop Event Serviced Service snoops to caches Stop Grant State When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle For the Dual Core Intel Xeon processor 7000 series both logica
16. LA Nu3llVd 310H 40 331N32 MO Nuillvd 3108 40D 00821 091 geo y 90 61 dO 1N3SNO2 NIL qaon00td34 03 Q 38 LON AVN 2N301 1N02 NI 03 I0du09 131NI SNI 9N1MVQ SIHL Dual Core Intel Xeon Processor 7000 Series Datasheet FIR CIE ea n 9 1 9 Figure 8 5 Board Mounting Hole Keepout Zones Boxed Processor Specifications 102 Figure 8 6 Thermal Solution Volumetric Boxed Processor Specifications ask 750 Tx 39 4 u TIP REGION Hm HEAT FIN REC PARTS LIST Dual Core Intel Xeon Processor 7000 Series Datasheet 103 Boxed Processor Specifications Ntel Figure 8 7 Recommended Processor Layout and Pitch 8 2 2 8 2 3 104 MIN 82 6MM 3 25 UIDI Boxed Processor Heatsink Weight The boxed processor heatsink weight is approximately 530 grams See Section 3 of this document for details on the processor weight Boxed Processor Retention Mechanism and Heatsink Supports Baseboards and chassis s designed for use by system integrators should include holes that are in proper alignment with each other to support the boxed processor See Figure 8 7 for example of processor pitch and layout Figure 8 1 illustrates the new retention solution This is designed to extend air cooling capability through the use of larger h
17. Please refer to the ITP700 Debug Port Design Guide eXtended Debug Port Debug Port Design Guide for Twin Castle Chipset Platforms eXtended Debug Port Debug Port Design Guide for MP Platforms and the appropriate platform design guide for more detailed information regarding debug tools specifications Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Dual Core Intel Xeon processor 7000 series systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Dual Core Intel Xeon processor 7000 series based multiprocessor systems the LAT is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a Dual Core Intel Xeon processor 7000 series based system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI pins plug into the socket while the processor pins plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume
18. Power Other AA3 BSELO Power Other J Output W25 Mee Power Other AAA Don t Care W26 Vss Power Other AAR VssA Power Other Input W27 Vcc Power Other AA6 Voc Power Other W28 Vss Power Other AA7 TESTHI4 Power Other Input W29 Vcc Power Other AA8 D61 Source Sync Input Output W30 Vss Power Other AA9 Vss Power Other W31 Mee Power Other AA10 D544 Source Sync Input Output Y1 Vss Power Other AA11 D53 Source Sync Input Output Y2 Voc Power Other AA12 IV Power Other Y3 Vss Power Other AA13 D48 Source Sync Input Output Y4 BCLKO FSB CIk Input AA14 D49 Source Sync Input Output Y5 Vss Power Other AA15 Vss Power Other Y6 TESTHI3 Power Other Input AA16 D334 Source Sync Input Output Y7 Vss Power Other AA17 Vas Power Other Y8 RESET Common Clk Input AA18 D24 Source Sync Input Output Y9 D624 Source Sync Input Output AA19 D15 Source Sync Input Output Y10 Vrr Power Other AA20 Nee Power Other Y11 DSTBP3 Source Sync Input Output AA21 D11 Source Sync Input Output Y12 DSTBN3 Source Sync Input Output AA22 D10 Source Sync Input Output Y13 Vss Power Other AA23 Vas Power Other Y14 DSTBP2 Source Sync Input Output AA24 D6 Source Sync Input Output Y15 DSTBN2 Source Sync Input Output AA25 D3 Source Sync Input Output Y16 Voc Power Other AA26 Voc Power Other Y17 DSTBP1 4 Source Sync Input Output AA27 Dis Source Sync Input Output Y18 DSTBN1 Source Sync Input Output AA28 SM TS1 AO SMBus Input Y19
19. Type Description BNR yo BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wire OR signal which must connect the appropriate pins of all processor system bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges BOOT_ SELECT The BOOT_SELECT input informs the processor whether the platform supports the Dual Core Intel Xeon processor 7000 series Incompatible platform designs will have this input connected to Vss Thus this pin is essentially an electrical key to prevent the Dual Core Intel Xeon processor 7000 series from running in a system that is not designed for it For platforms that are designed to support the Dual Core Intel Xeon processor 7000 series this pin should be changed to a no connect BPM 5 0 yo BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins of all Dual Core Intel Xeon processor 7000 series FSB agents BPM4 provides
20. VCC SM TS A0 SM TS AI Processor SM EP A Information pATA Ai ROM SM_EP_A BE and Thermal EB Sensor SM WP Scratch STDBY EEPROM ALERT 1 Kbit each SM_CLK SM_DAT SM_ALERT NOTE Actual implementation may vary This figure is provided to offer a general understanding of the architecture All SMBus pull up and pull down resistors are 10 kQ and located on the processor Processor Information ROM PIROM The lower half 128 bytes of the SMBus memory component is an electrically programmed read only memory with information about the processor This information is permanently write protected Table 7 2 shows the data fields and formats provided in the Processor Information ROM PIROM This is PIROM data format revision 2 Offset 00 Fields which have changed for this revision are marked in italics in Table 7 2 77 Features 78 Table 7 2 Processor Information ROM Format Sheet 1 of 3 of Offset Section Bits Function Notes Header 00h 8 Data Format Revision Two 4 bit hex digits 01 02h 16 EEPROM Size Size in bytes MSB first 03h 8 Processor Data Address Byte pointer 00h if not present 04h 8 Processor Core Data Byte pointer OOh if not present Address 05h 8 L3 Cache Data Address Byte pointer OOh if n
21. Xeon processor 7000 series does not have an L3 cache this field is set to Oh This field is in mV and is reflected in hex Some systems read this offset to determine if all processors support the same default CVID setting Minimum L3 cache voltage specifications are reflected in offset 2D 2Eh This field is in mV and reflected in hex For processors that follow a load line DC specification the minimum VcAcHE reflected in this field should reflect the minimum allowable voltage at maximum current Example Since the Dual Core Intel Xeon processor 7000 series does not have an L3 cache offset 2B 2Ch would contain Oh and offset 2D 2Eh would contain Oh Package Data This section describes the package revision location at offset 32 35h This field tracks the highest level revision It is provided in ASCII format of four characters 8 bits x 4 characters 32 bits The package is documented as 1 0 2 0 etc Because this only consumes three ASCII characters a leading space is provided in the data field Example The C 1 stepping of the Intel Xeon processor with 512 KB L2 cache is packaged in the 603 pin micro PGA interposer with 31 mm OLGA package and utilizes the second revision of this package Thus at offset 32 35h the data is a space followed by 2 0 In hex this would be 20 32 2E 30 Part Number Data This section provides traceability There are 208 available bytes in this section for future use Dual Core Intel Xeon Proc
22. attempts to ensure the Thermal Control Circuit is not activated below maximum T casg when dissipating TDP power There is no defined or fixed correlation between the PROCHOT trip temperature the case temperature or the thermal diode temperature Thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of TcAsg PROCHOT or Tdiode on random processor samples Dual Core Intel Xeon Processor 7000 Series Datasheet 71 LU Thermal Specifications Ntel e 6 2 4 6 2 5 6 2 6 6 2 7 72 FORCEPR Signal Pin The FORCEPR force power reduction input can be used by the platform to force the Dual Core Intel Xeon processor 7000 series processor to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal The TCC will remain active until the system deasserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system components To use the voltage regulator VR as an example when the FORCEPR pin is asserted the TCC in the processor will activate reducing the current consumption of the processor and the corresponding temperature of the VR It should be noted that assertion of FORCEPR does not automatically assert PROCHOT As mentioned previously the PROCHOT signal is asserted when a high temperature situation is detected A minimum pulse width of 500 microseconds is
23. environment that may require attention Note that sensor readings from different cores can vary significantly and must all be monitored The SMBus thermal sensor feature in the processor cannot be used to measure Tease The Tease specification in Section 6 must be met regardless of the reading of the processor s thermal sensor in order to ensure adequate cooling for the entire processor The SMBus thermal sensor feature is only available while Vcc and SM_VCC are at valid levels and the processor is not in a low power state Thermal Sensor Supported SMBus Transactions The thermal sensor responds to five of the SMBus packet types Write Byte Read Byte Send Byte Receive Byte and Alert Response Address ARA The Send Byte packet can be used for sending one shot commands The Receive Byte packet accesses the register commanded by the last Read Byte packet and can be used to continuously read from a register If a Receive Byte packet was preceded by a Write Byte or send Byte packet more recently than a Read Byte packet then the behavior is undefined Table 7 5 through Table 7 9 diagram the five packet types In these figures S represents the SMBus start bit P represents a stop bit Ack represents an acknowledge and I P represents a negative acknowledge NACK The shaded bits are transmitted by the thermal sensor and the bits that aren t shaded are transmitted by the SMBus host controller Table 7 10 shows the encoding of the c
24. for identification 4 Ch 1 limit registers have a separate 7 bit read and write address while channel 2 limit registers have the same 7 bit address for read and write All of the commands in Table 7 10 are for reading or writing registers in the SMBus thermal sensor except the one shot register OFh The one shot command forces the start of a new conversion cycle If a conversion is in progress when the one shot command is received then the command is ignored If the thermal sensor is in stand by mode when the one shot command is received a conversion is performed and the sensor returns to stand by mode The one shot command is not supported when the thermal sensor is in auto convert mode Dual Core Intel Xeon Processor 7000 Series Datasheet 83 Features Note 7 4 6 7 4 6 1 intel Writing to a read command register or reading from a write command register will produce invalid results The default command after reset is to a reserved value 00h After reset Receive Byte SMBus packets will return invalid data until another command is sent to the thermal sensor SMBus Thermal Sensor Registers Temperature Value Registers Once the SMBus thermal sensor reads a processor thermal diode it performs an analog to digital conversion and stores the data in a temperature value register The supported range is O to 127 decimal and is expressed as an eight bit number representing temperature in degrees Celsius This eight bit val
25. is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET IGNNE IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid a 6 clks before the I O write s response INIT INIT Initialization when asserted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor FSB agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in S
26. sample their BR 3 0 pins on the active to inactive transition of RESET The pin which the agent samples asserted determines its agent ID BSEL 1 0 These output signals are used to select the FSB frequency The frequency is determined by the processor s chipset and frequency synthesizer capabilities All FSB agents must operate at the same frequency Individual processors will only operate at their specified FSB frequency See the appropriate platform design guide for implementation examples See Table 2 2 for output values Refer to the appropriate platform design guide for termination recommendations COMPO COMPO must be terminated to Vss on the baseboard using precision resistors This input configures the AGTL drivers of the processor Refer to the appropriate platform design guide for implementation details 60 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Signal Definitions Table 5 1 Signal Definitions Sheet 3 of 7 Name Type Description D 63 0 UO D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each g
27. two SMBus packet types Read Byte and Write Byte However since the PIROM is write protected it will acknowledge a Write Byte command but ignore the data The Scratch EEPROM responds to Read Byte and Write Byte commands Table 7 3 diagrams the Read Byte command Table 7 4 diagrams the Write Byte command Following a write cycle to the scratch ROM software must allow a minimum of 10 ms before accessing either ROM of the processor In the tables S represents the SMBus start bit P represents a stop bit R represents a read bit W represents a write bit A represents an acknowledge ACK and represents a negative acknowledge NACK The shaded bits are transmitted by the Processor Information ROM or Scratch EEPROM and the bits that aren t shaded are transmitted by the SMBus host controller In the tables the data addresses indicate 8 bits The SMBus host controller should transmit 8 bits with the most significant bit indicating which section of the EEPROM is to be addressed the Processor Information ROM MSB 0 or the Scratch EEPROM MSB 1 Table 7 3 Read Byte SMBus Packet 80 Slave S Command Slave S Address Write A Code A S Address Read A Data III P 1 7 bits 1 1 8 bits 1 1 7 bits 1 1 8 bits 1 1 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Table 7 4 7 4 4 7 4 5 Table 7 5 Features Write Byte SMBus Packet
28. up to 8 processors on a single SMBus 7 4 9 Managing Data in the PIROM The PIROM consists of the following sections Header Processor Data Processor Core Data Cache Data Package Data Part Number Data Thermal Reference Data Feature Data Other Data Details on each of these sections are described below Note Reserved fields or bits SHOULD be programmed to zeros However OEMs should not rely on this model 7 4 9 1 Header To maintain backward compatibility the Header defines the starting address for each subsequent section of the PIROM Software should check for the offset before reading data from a particular section of the ROM Example Code looking for the cache data of a processor would read offset 05h to find a value of 25h 25h is the first address within the Cache Data section of the PIROM Dual Core Intel Xeon Processor 7000 Series Datasheet 89 Features 7 4 9 2 7 4 9 3 7 4 9 3 1 90 Note Note intel The Header also includes the data format revision at offset Oh and the EEPROM size formatted in hex bytes at offset 01 02h The data format revision is used whenever fields within the PIROM are redefined Normally the revision would begin at a value of 1 If a field or bit assignment within a field is changed such that software needs to discern between the old and new definition then the data format revision field should be incremented The EEPROM size provides the size of the PIROM in h
29. 00 V 5 Vus Undershoot 0 300 N A N A V 6 VRBM Ringback Margin 0 200 N A N A V 7 VTM Threshold Margin Vcnoss 0 100 Vcrosst0 100 V 8 NOTES 1 N 9 m o N Dual Core Intel Xeon Processor 7000 Series Datasheet Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLKO is equal to the falling edge of BCLK1 The crossing point must meet the absolute and relative crossing point specifications simultaneously VHayg is the statistical average of the Vu measured by the oscilloscope VHavg can be measured directly using Vtop on Agilent scopes and High on Tektronix scopes Overshoot is defined as the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches It includes input threshold hysteresis 29 Electrical Specifications Table 2 12 BSEL 1 0 VID 5 0 and DC Specifications Symbol Parameter Max Unit Notes RoN Buffer On Resistance 60 Q 1 lo Max Pin Current 8 mA lio Output Leakage Current 200 HA 2 VIOL Voltage Tolerance 3 3 5 V 3 NOTES 1 These para
30. 000 series supports 40 bit addressing The Dual Core Intel Xeon processor 7000 series uses a scalable system bus protocol referred to as the front side bus in this document The FSB utilizes a split transaction deferred reply protocol The FSB uses Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus clock 4X data transfer rate Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked double pumped or the 2X address bus In addition the Request Phase completes in one clock cycle Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 5 3 GB 677 MHz per second Finally the FSB is also used to deliver interrupts Terminology A symbol after a signal name refers to an active low signal indicating that a signal is in the asserted state when driven to a low level For example when RESET is low i e when RESET is asserted a reset has been requested Conversely when NMI is high that is when NMI is asserted a nonmaskable interrupt request has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHU refers to a hex A and D 3 0 LHLH also refers to a hex A H Hig
31. 001 32 1010 Continuous Measurements 7 4 7 SMBus Thermal Sensor Alert Interrupt The SMBus thermal sensor located on the processor includes the ability to interrupt the SMBus when a fault condition exists The fault conditions consist of 1 A processor thermal diode value measurement that exceeds a user defined high or low threshold programmed into the Command Register or 2 Disconnection of the processor thermal diode from the thermal sensor The interrupt can be enabled and disabled via the thermal sensor Configuration Register and is delivered to the system board via the SM_ALERT open drain output Once latched the SM_ALERT should only be cleared by reading the Alert Response byte from the Alert Response Address of the thermal sensor The Alert Response Address is a special slave address shown in Table 7 9 The SM ALERT will be cleared once the SMBus master device reads the slave ARA unless the fault condition persists Reading the Status Register or setting the mask bit within the Configuration Register does not clear the interrupt Dual Core Intel Xeon Processor 7000 Series Datasheet 87 Features 7 4 8 88 intel Of the addresses broadcast across the SMBus the memory component claims those of the form 1010XXXZb The XXX bits are defined by pull up and pull down resistors on the system baseboard These address pins are pulled down weakly 10 kQ on the processor substrate to ensure tha
32. 1375 0 0 1 1 0 1 1 5375 1 1 1 1 0 0 1 1500 1 0 1 1 0 0 1 5500 0 1 1 1 0 0 1 1625 0 0 1 1 0 0 1 5625 1 1 1 0 1 1 1 1750 1 0 1 0 1 1 1 5750 0 1 1 0 1 1 1 1875 0 0 1 0 1 1 1 5875 1 1 1 0 1 0 1 2000 1 0 1 0 1 0 1 6000 Dual Core Intel Xeon Processor 7000 Series Datasheet 19 Electrical Specifications Ntel 2 3 2 4 20 Reserved Unused and TESTHI Pins All RESERVED pins must be left unconnected Connection of these pins to Vcc Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 5 for a pin listing for the processor and the location of all RESERVED pins For reliable operation always terminate unused inputs or bidirectional signals to their respective deasserted states On die termination has been included on the Dual Core Intel Xeon processor 77000 series to allow signals to be terminated within the processor silicon Most unused AGTL inputs may be left as no connects since AGTL termination is provided on the processor silicon See Table 2 5 for details on AGTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground V ss Unused outputs may be left unconnected However this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any si
33. 13N02 NI 038019810 SI 11 NOIIYWUOJNI Y 1N3014NO3 Wei ge T31NI SNIYINOO NINVAG SIMI 2 ug 26281V on onal D 9 L 8 S Dual Core Intel Xeon Processor 7000 Series Datasheet 100 Boxed Processor Specifications v S 9 L 9 ERC sI 262SL i Au mm zum 3000 aovoh SWYOILV 1d NI J04 NId33N 1H913H IN3NOJWOO XVW WW FS 2 4001 SWYOSLV 1d JAQAY NV Ne HOS NId339 1H913H IN3NOdWOO XVW NN 980 S 002 Q34OT1V 1N3432V1d IN3NOdWOO QHuVOGN3HION ON FLV1d ONIUdS e 7 LOOL E 86 6 1000721 n C 8 00 cose er H 1009 21 zi daia 808 000 0 H 1 j 06271 J 7 RR Ines E I6 9 1 NOISUIA CISS NOLLV2141234S AVG 21N0312313 NIHL JHL NO Q35Y8 3uv SNOISNINIG 393Hl 308383438 J04 NMOHS QNVOG 1531 SNNOilYld NI WO LHOl3H LN3NOdNOD XY NN PS 2 001 SNYO4LVTd 3AOBV QNY NZ 304 NId33y 149134 IN3NOdNOD XYN WW 80 S 002 a 20 AMVONOO3S HEW fa Il y S 9 I 8 Figure 8 4 Bottom Side Board Keepout Zones 101 Dual Core Intel Xeon Processor 7000 Series Datasheet Y S 9 L 8 HI iNs4iuvd3d v3UuV SIHL NI 3JO0QNVIS SISSVHO YO S310H ONILNNOW GYVOE ON 32N343434 404 NMOHS 310H ONILNNOW J0 3208d JINO 32383438 803 NMOHS 31100 QVO FAY 109 SU E 4 79 0p L As T T T
34. 15 AA19 Source Sync Input Output D53 AA11 Source Sync Input Output D16 AE26 Source Sync Input Output D54 AA10 Source Sync Input Output D17 AC26 Source Sync Input Output D55 AB10 Source Sync Input Output D18 AD25 Source Sync Input Output D56 AC8 Source Sync Input Output D19 AE25 Source Sync Input Output D57 AD7 Source Sync Input Output D20 AC24 Source Sync Input Output D58 AE7 Source Sync Input Output D21 AD24 Source Sync Input Output D59 AC6 Source Sync Input Output D22 AE23 Source Sync Input Output D60 AC5 Source Sync Input Output D23 AC23 Source Sync Input Output D61 AA8 Source Sync Input Output D24 AA18 Source Sync Input Output D62 Y9 Source Sync Input Output D25 AC20 Source Sync Input Output D63 AB6 Source Sync Input Output D26 AC21 Source Sync Input Output DBI0 AC27 Source Sync Input Output 42 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Pin Listing Table 4 1 Pin Listing by Pin Name Cont d Table 4 1 Pin Listing by Pin Name Cont d Pin Name Pin No Signal Direction Pin Name Pin No Signal Direction Buffer Type Buffer Type DBI1 AD22 Source Sync Input Output Don t Care N1 DBI2 AE12 Source Sync Input Output Don t Care N3 DBI3 AB9 Source Sync Inp
35. 2 Number of cores 1 0 Number of threads per core Dual Core Intel Xeon Processor 7000 Series Datasheet 79 Features intel Table 7 2 Processor Information ROM Format Sheet 3 of 3 7 4 2 7 4 3 Offset Section ES Function Notes its 8 Aaditional Processor 7 Reserved Feature Flags 6 Reserved 5 Enhanced Halt State 4 Intel Virtualization Technology 7Ah 3 Execute Disable 2 Intel 64 architecture 1 Thermal Monitor 2 0 Enhanced Intel SpeedStep Technology 7B 7Ch 16 Thermal Adjustment Factors 15 8 Measurement Correction Factor Pending 7 0 Temperature Target 7D 7Eh 16 Reserved Reserved 7Fh 8 Checksum 1 byte checksum Scratch EEPROM Also available in the memory component on the processor SMBus is an EEPROM which may be used for other data at the system or processor vendor s discretion The data in this EEPROM once programmed can be write protected by asserting the active high SM_WP signal This signal has a weak pull down 10 kQ to allow the EEPROM to be programmed in systems with no implementation of this signal The Scratch EEPROM resides in the upper half of the memory component addresses 80 FFh The lower half comprises the Processor Information ROM addresses 00 7Fh which is permanently write protected by Intel PIROM and Scratch EEPROM Supported SMBus Transactions The Processor Information ROM PIROM responds to
36. 3 4 3 5 3 6 3 7 6 1 6 2 7 2 8 1 8 2 8 4 8 5 8 6 8 7 Tables 1 1 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 Dual Core Intel Xeon Processor 7000 Series Datasheet On Die Front Side Bus Termination nana nea kk aaa 15 Phase Lock Loop PLL Filter Requirements AA 17 Dual Core Intel Xeon Processor 7000 SeriesLoad Current vs TIME u u uu mna ua Foe reas und de ds iu a aa KR RE a lt 26 VCC Static and Transient Tolerance nenea nenea ana 28 Voc Overshoot Example Waveform air da Add Hi dudit 29 Processor Package Assembly Sketch sss 33 Processor Package Drawing Sheet 1 of 2 34 Processor Package Drawing Sheet 2 of 2 35 Processor Topside Markimgs eee een nennen 38 Processor Bottom Side Markings sss 38 Processor Pin Out Coordinates Top View 39 Processor Pin Out Coordinates Bottom View E keke 40 Dual Core Intel Xeon Processor 7000 Series Thermal Profile A 69 Case Temperature TCASE Measurement Location 70 Stop Clock State Machine enne 74 Logical Schematic of SMBUS Circuitry sess 77 Passive Dual Core Intel Xeon Processor 7000 Series Thermal Solution 3U and Lager 97 Top Side Board Keepout Zones Part 1 sse 99 Top Side Board Keepout Zones Part 2
37. 7 18 7000 series with multiple VIDs lr Front Side Bus end agent V77 current 4 A 4 lr Front Side Bus mid agent V r current 1 3 A 2 lsv_vcc Icc for SMBus supply 100 122 5 mA f Joe VCCA Icc for PLL power pins 60 mA 5 Iec_veciopL ec for I O PLL power pins 60 mA 5 lcc_GTLREF loc for GTLREF pins 200 uA 16 ISGNT Icc Stop Grant for Dual Core 63 A 7 17 18 Intel Xeon processor 7000 series 2 8 GHz FMB lec loc TCC Active loc A 19 Dual Core Intel Xeon Processor 7000 Series Datasheet n Ntel 6 Electrical Specifications R Table 2 8 Voltage and Current Specifications Sheet 2 of 2 Symbol Parameter Min Typ Max Unit Notes1 Joe me Icc for Dual Core Intel Xeon processor 130 A 7 20 13 7000 series Thermal Design Current 2 8 FMB GHz NOTES 1 2 3 8 9 10 11 12 13 14 15 16 17 18 19 20 Unless otherwise noted all specifications in this table apply to all processors These specifications are based on silicon characterization however they may be updated as further data becomes available Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have different VID settings These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 2 for more information The voltage specification requiremen
38. 7 4 6 5 Bit Name Reset State Function 6 RUN STOP 0 Stand by mode control bit If set the device immediately Stops converting and enters stand by mode It will perform new temperature measurements when a one shot is performed If cleared the device automatically updates on a timed basis AL TH This bit selects the function of pin 13 Default 0 ALERT Always set this bit to 0 RESERVED RESERVED Reserved for future use Remote 1 2 0 Setting this bit to 1 enables the user to read the remote 2 values from the remote 1 registers Default 0 Read remote 1 values from the remote 1 registers Always set this bit to O Temp Range Setting this bit to 1 enables the extended temperature measurement range 50 C to 150 C Default 0 0 C to 127 C Always set this bit to 0 Mask R1 Setting this bitto 1 masks ALERTS due to the processor core 1 temperature exceeding a programmed limit Default 0 Always set this bit to 0 Mask R2 Setting this bitto 1 masks ALERTS due to the processor core 2 temperature exceeding a programmed limit Default 0 Always set this bit to 0 Conversion Rate Register The contents of the Conversion Rate Registers determine the nominal rate at which analog to digital conversions happen when the SMBus thermal sensor is in auto convert mode There are two Conversion Rate Registers address 04h for reading the conversion
39. 7000 series Dual Core Intel Xeon Processor 7000 Series Datasheet intel Signal Definitions Table 5 1 Signal Definitions Sheet 7 of 7 Name Type Description Voca l Vcca provides isolated power for the analog portion of the internal PLL s Use a discrete RLC filter to provide clean power Refer to the appropriate platform design guide for complete implementation details VccIoPLL VeciopL provides isolated power for digital portion of the internal PLL s Follow the guidelines for Vcca and refer to the appropriate platform design guide for complete implementation details VCCSENSE O VccsENSE and Vsssense provide isolated low impedance connections to the processor core voltage VSSSENSE Vcc and ground Vss They can be used to sense or measure voltage or ground near the silicon with little noise VID 5 0 O VID 5 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc These are open drain signals that are driven by the processor and must be pulled through a resistor Conversely the VR output must be disabled prior to the voltage supply for these pins becoming invalid The VID pins are needed to support processor voltage specification variations See Table 2 3 for definitions of these pins The Vcc VR must supply the voltage that is requested by these pins or disable itself VIDPWRGD l The processor requires this input to determine that the supply voltage fo
40. AP0 REQ 4 0 AP1 APO BCLK 1 0 The differential bus clock pair BCLK 1 0 determines the bus frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing the falling edge of BCLK1 BINIT UO BINIT Bus Initialization may be observed and driven by all processor FSB agents If used BINIT must connect the appropriate pins of all such agents If the BINIT driver is enabled BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration see Section 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their UO Queue IOQ and transaction tracking state machines upon observation of BINIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the FSB and attempt completion of their bus queue and IOQ entries If BINIT observation is enabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system Dual Core Intel Xeon Processor 7000 Series Datasheet 59 Signal Definitions Intel Table 5 1 Signal Definitions Sheet 2 of 7 Name
41. C26 D17 Source Sync Input Output AB17 D314 Source Sync Input Output AC27 DBl Source Sync Input Output AB18 Voc Power Other AC28 SM CLK SMBus Input AB19 D14 Source Sync Input Output AC29 SM DAT SMBus Output ABO D124 Source Sync Input Output AC30 DontCare AB21 Vss Power Other AC31 Mee Power Other AB22 D13 Source Sync Input Output AD1 Reserved AB23 D9 Source Sync Input Output AD2 Mee Power Other AB24 Vcc Power Other AD3 Vss Power Other AB25 D8 Source Sync Input Output AD4 VccioPLL Power Other Input AB26 D7 Source Sync Input Output AD5 TESTHI5 Power Other Input AB27 Vss Power Other AD6 Don tCare AB28 SM EP A2 SMBus Input AD7 D57 Source Sync Input Output AB29 SM EP A1 SMBus Input AD8 D464 Source Sync Input Output AB30 Vcc Power Other AD9 Vss Power Other AB31 Vss Power Other AD10 D45 Source Sync Input Output AC Reserved ADM D40 Source Sync InputOutput AC2 Vss Power Other AD12 V Power Other AC3 Nee Power Other AD13 D38 Source Sync Input Output ACA Don t Care AD14 D39 Source Sync Input Output AC5 D60 Source Sync Input Output AD15 Nee Power Other AC6 D59 Source Sync Input Output AD16 COMPO Power Other Input AC7 Vss Power Other AD17 Vsg Power Other AC8 D564 Source Sync Input Output AD18 D36 Source Sync Input Output AC9 D47 Source Sync Input Output AD19 D30 Source Sync Input Output AC10 Ver Power Other AD20 Vcc Power Oth
42. Clock Input Clock BCLK 1 0 SMBus Synchronous to SM CLK SM_ALERT SM CLK SM DAT SM EP A 2 0 SM TS A 1 0 SM WP Power Other Power Other BOOT SELECT BSEL 1 0 COMPO TESTHI 6 0 GTLREF 3 0 ODTEN PWRGOOD RESERVED SKTOCC SLEW CTRL SM VCC TEST BUS Vcc Voca VccioPLL Vecsense VID S 0 VIDPWRGD Vss Vssa VsssENsE VTT VTTEN PROCTYPE NOTES 1 Refer to Section 5 1 for signal descriptions Dual Core Intel Xeon Processor 7000 Series Datasheet 21 Electrical Specifications Ntel Table 2 5 Table 2 6 2 6 22 Signal Description Table Signals with Ry A 39 3 ADS ADSTB 1 0 AP 1 0 BINIT BNR BOOT SELECT BPRI D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM LOCK MCERR ODTENS REQ 4 0 RS 2 0 TEST BUS RSP TCK4 TDI4 TMS4 TRDY TRST 4 Signals with RL BINIT BNR HIT HITM MCERR NOTES 1 Signals not included in the Signals with R77 list require termination on the baseboard Please refer to Table 2 4 for the signal type and Table 2 12 to Table 2 17 for the corresponding DC specifications 2 The BOOT_SELECT pin is not terminated with RT It has a 250 5000 Q internal pullup 3 THe ODTEN pin is not terminated with Rrr It has a 2 KO 10 KQ internal pullup 4 TCK TDI TMS and TRST are not terminated with Dr They have a 4 KO 20 KO internal pullup The ODTEN signals enables
43. D RESERVED Reserved for future use 6 RESERVED RESERVED Reserved for future use 5 RESERVED RESERVED Reserved for future use 4 R2HIGH 0 If set indicates the processor core 2 thermal diode high temperature alarm has activated 3 R2LOW 0 If set indicates the processor core 2 thermal diode low temperature alarm has activated 2 R2OPEN 0 If set indicates an open fault in the connection to the processor core 2 diode 1 RESERVED RESERVED Reserved for future use 0 LSB ALERT 0 If set indicates the ALERT pin has been asserted low This bit gets reset when the ALERT output gets reset Configuration Register The Configuration Register controls several functions of the temperature sensor such as ALERT masking stand by mode and others Table 7 14 and Table 7 11 shows the bit definitions of the Configuration Registers Table 7 14 SMBus Thermal Sensor Configuration Register Sheet 1 of 2 Bit Name Reset State Function 7 MSB MASK 0 Mask SM_ALERT bit Clear the bit to allow interrupts via SM_ALERT and allow the thermal sensor to respond to the ARA command when an alarm is active Set the bit to disable interrupt mode The bit is not used to clear the state of the SM ALERT output An ARA command may not be recognized if the mask is enabled Dual Core Intel Xeon Processor 7000 Series Datasheet 85 Features Intel Table 7 14 SMBus Thermal Sensor Configuration Register Sheet 2 of 2
44. M etc The second set is for the source synchronous signals that are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asynchronous signals are present A20M IGNNE etc and can become active at any time during the clock cycle Table 2 4 identifies signals as common clock source synchronous and asynchronous Table 2 4 Front Side Bus Pin Groups Signal Group Type Signals AGTL Common Clock Input Synchronous to BCLK 1 0 BPRI DEFER RESET RS 2 0 RSP TRDY AGTL Common Clock I O Synchronous to BCLK 1 0 ADS AP 1 0 BINIT BNR BPM 5 0 BR 3 0 DBSY DP 3 0 DRDY HIT HITM LOCK MCERR AGTL Source Synchronous I O Synchronous to associated strobe Signals Associated Strobe REQ 4 0 ADSTBO A 37 36 16 3 t A 39 38 35 1 7 ADSTB1 D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBIS DSTBP3 DSTBN3 AGTL Strobe Input Output Synchronous to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 AGTL Asynchronous Output Asynchronous FERR PBE IERR PROCHOT GTL Asynchronous Input Asynchronous A20M FORCEPR IGNNE INIT LINTO INTR LINT1 NMI SMI STPCLK GTL Asynchronous Output Asynchronous THERMTRIP TAP Input Synchronous to TCK TCK TDI TMS TAP Input Asynchronous TRST TAP Output Synchronous to TCK TDO Front Side Bus
45. M DIDOM nenea nana 77 1 42 Scrate EEPROM ue iet ftit data a aaa ka v s z 80 7 4 3 PIROM and Scratch EEPROM Supported SMBus Transactions 80 7 4 A SMBus Thermal Sensor nn nana aa ana 81 7 4 5 Thermal Sensor Supported SMBus Transactions 81 7 4 6 SMBus Thermal Sensor Registers 84 7 4 7 SMBus Thermal Sensor Alert Interrupt E 87 7 4 8 SMBus Device Addressing Eke k ana 88 7 4 9 Managing Data in the PIROM sss 89 Boxed Processor Gpeclflcations sse nana nana na 97 8 1 II GO DO HOL ee oe t u Ree ott ene tere 97 8 2 Mechanical Specifications esses eene 98 8 2 1 Boxed Processor Heatsink Dimensions aa 98 8 2 2 Boxed Processor Heatsink Weobt A 104 8 2 3 Boxed Processor Retention Mechanism and Heatsink Supports 104 8 3 Thermal Specifications esses enne 105 8 3 4 Boxed Processor Cooling Requirements 105 8 3 2 Boxed Processor Contents sss 105 Debug Tools Specifications nnne nau KAK KA KAR na 107 9 1 Logic Analyzer Interface LAI ilu y eku ae kak ana a 107 9 1 1 Mechanical Considerations kek kk kk k 107 9 1 2 Electrical Considerations Eke kk kek 107 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Figures 2 1 2 2 2 3 2 4 2 5 3 1 3 2
46. P states P states are power consumption and capability states within the Normal state Enhanced Intel SpeedStep technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system Note that the FSB is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology Two voltage frequency operating points provide optimal performance at reduced power consumption Voltage Frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency If the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals Refer to the Prescott Nocona and Potomac Processor
47. PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents Please refer to the appropriate platform design guide for more detailed information BPRI BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connect the appropriate pins of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until its requests are issued then releases the bus by deasserting BPRI BR 3 0 yo BR 3 0 Bus Request drive the BREQ 3 0 signals in the system The BREQ 3 0 signals are interconnected in a rotating manner to individual processor pins The tables below give the rotating interconnect between the processor and bus signals for 3 load configurations BR 3 0 Signals Rotating Interconnect 3 Load Configuration Bus Signal Agent 0 Pins Agent 1 Pins BREQO BRO BR1 BREQ1 BR1 BRO BREQ2 BR2 BR3 BREQ3 BR3 BR2 During power on configuration the central agent must assert the BREQO bus signal All symmetric agents
48. Power Other D22 RS1 Common CIk Input F1 Vec Power Other D23 BPRI Common Clk Input F2 Vss Power Other D24 Nee Power Other F3 VIDO Power Other J Output D25 Don t Care F4 Vec Power Other D26 VsssENsE Power Other Output F5 BPM3 Common Clk Input Output Dual Core Intel Xeon Processor 7000 Series Datasheet 51 Pin Listing intel Table 4 2 Pin Listing by Pin Number Cont d Table 4 2 Pin Listing by Pin Number Cont d Pin No Pin Name jos d Direction Pin No Pin Name bui Eu Direction F6 BPMO Common Clk Input Output G29 Vgs Power Other F7 Vss Power Other G30 Vcc Power Other F8 BPM1 Common Clk Input Output G31 Vss Power Other F9 GTLREF3 Power Other Input H1 Don t Care F10 Mr Power Other H2 Vss F11 BINIT Common CIk Input Output H3 Don t Care F12 BR1 Common Clk Input Output H4 Vss F13 Vss Power Other H5 Don Care F14 ADSTB1 Source Sync Input Output H6 Vss F15 A194 Source Sync Input Output H7 Don t Care F16 A36 Source Sync Input Output H8 Vss F17 ADSTBO Source Sync Input Output H9 Don t Care F18 DBSY Common Clk Input Output H23 Vcc Power Other F19 Vss Power Other H24 Vss Power Other F20 BNR Common Clk Input Output H25 Voc Power Other F21 RS2 Common Clk Input H26 Vss Power Other F22 A37 Source Sync Input Output H27 Vcc Power Other F23 GTLREF2 P
49. S 51186 x08 04 on ome a0 2 noissin ooz e d 3009 aovolaz i002 S310H NAHL ONIINNOW Y0SSIJOYd TI on 20074 20 0 91 01g xv BOIS AHVWid aa 910 1 99 s2 1000 1 WH o 000000000000000000000000 6000000000000000000 0000000000000000000000000 00871 L 2971 KEN 000 0 ISIE H Sz EM 00S LU 000000000 Q3W011V SIN3NOdWO2 QHVOBH3HION ON 1n0d33 39N14 QuvOG ONIYdS 32 NOI12181S3U 1H9 3H LNINOdNOD QuVOGH3HION DN WAPI ISS Q3M011V 1N3N32V1d 1N3NOdHOO GYVORYIHLOW ON VAN J18H35SVS 10 XNISLV3H NOI12181S38 18913H LN3NOdWOD XVW WW 9278 SZE NOI12131S3H 1H913H LNANOdNOD XVW NN 9279 ze V3uV XNISIV3H NOT 12181838 1H913H IN3NOdWOO XYW WWIG OGI S0090 2 z eo ui 329N343434 403 NMOHS QuVOH 1S31 c 9 H 0 9 DKCH SL 06 062 Hi eie 20571 86671 IEN y ZL IEN 88 vL 60 s8 0SE LOSP E 9 18 NOILYMOdHOO 131N 4O INISNOJ NLLIUN HOlNd JHL LDONLIM 038012810 38 LON AYN SIN21NOD SLI ANY 32N30
50. Sheet 1 of 2 2 40 1334S ONIAvuG 3WOS LON OG 1 2 31V2S HSINI4 I GR 2 A3 yagwnn oNimyya 3002 39vo Jus 0v 193191 pe 31va 48 03n0udav NOIL93rOWd 319NV QUIHL 9NIMVHO SIWZ 31111 3 vq A8 030382 1N3HLUV430 TU7IU7CT UL ERR D mu aly 1 POT EP MEK 3iva Ag NMVO 3 vg A8 03N9is30 REV SHT C97394 DWG NO Lei Cio EE O 82 0 lt 0 0 rez 0d 090 HERE 0S0 DISVA L271 LOSS 21Sv8 16 l 3 9 g v tet071 app og OSL 21SV8 SO 6 0021 21908 Sp 0 0091 9ISV8 9 6917 Cyr lei 99 0901 3ISYS Le 3 viteeo 1 1 02911 ZIS I 9 8 Y 8 8 v teeo 1 1 02911 IEN 9 8 Y 9 1 I 01721 960 d les LEE vol Z 960 Mag a es 1 I SLN3WNOD XVA NIW S3HONI SY3LIWI TIIN WII 01108 MILA 3015 2007 1007 0690 0 r620 0U 00 080 80 0TE0 2 e 1 01 JIS V TYL 920 XYW 99 05 T XV 920 XVW 60970 lt 800 02 0 v0 N 260 1 ALVYLSENS 39VJ2Vd 00 1 210 Z7 011 SH MALA 1NO34 MAIA dOL
51. TE Refer to the Dual Core Intel Xeon Processor 7000 Sequence Thermal Mechanical Design Guidelines for system and environmental implementation details Table 6 2 Dual Core Intel Xeon Processor 7000 Series Thermal Profile A Thermal Profile A Y4 0 184 C W Ta 45 C Power Temperature C 27 50 30 51 40 52 50 54 60 56 70 58 80 60 90 62 100 64 110 65 120 67 130 69 140 71 150 73 160 75 165 76 Dual Core Intel Xeon Processor 7000 Series Datasheet 69 LU Thermal Specifications Ntel e 6 1 2 Thermal Metrology The maximum and minimum case temperatures Tcasp specified in Table 6 1 are measured at the geometric top center of the processor IHS Figure 6 2 illustrates the location where TcASE temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the Dual Core Intel Xeon Processor 7000 Sequence Thermal Mechanical Design Guidelines Figure 6 2 Case Temperature TcAsg Measurement Location 6 2 6 2 1 70 Measure from edge of IHS 15 5 mm 0 610 in Measure T oase atthis point geometric center of IHS 15 5 mm 0 610 in 53 34 mm FC mPGA4 Package Thermal grease should cover entire area of IHS Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the TCC when the processor silicon reaches
52. THI 6 5 TESTHI4 cannot be grouped with other TESTHI signals Mixing Processors Intel supports and validates multi processor configurations in which all processors operate with the same FSB frequency and internal cache sizes Intel does not support or validate operation of processors with different cache sizes or mixed processor models Mixing different processor steppings but the same model is supported Details on this process are provided in the Dual Core Intel Xeon Processor 7000 Sequence Specification Update Prescott Nocona and Potomac Processor BIOS Writer s Guide BWG document and the AP 485 Intel Processor Identification and the CPUID Instruction application note Dual Core Intel Xeon Processor 7000 Series Datasheet Electrical Specifications Front Side Bus Signal Groups The FSB signals are grouped by buffer type as listed in Table 2 4 The buffer type indicates which AC and DC specifications apply to the signals AGTL input signals have differential input buffers that use GTLREF as a reference level In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving Implementing a source synchronous data bus requires specifying two sets of timing parameters One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HIT
53. The Dual Core Intel Xeon processor 7000 series is packaged in a FC mPGA4 package that interfaces with the motherboard via a mPGA604 socket The package consists of a processor core mounted on a substrate pin carrier An IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the mPGA604 Socket Design Guidelines for complete details on the mPGA604 socket The package components shown in Figure 3 1 include the following 1 IHS 2 Processor die 3 FC mPGAA package 4 Pin side capacitors 5 Package pin Figure 3 1 Processor Package Assembly Sketch 3 1 Note LA Figure 3 1 is not to scale and is for reference only The mPGA604 socket is not shown Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 3 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include Package reference with tolerances total height length width etc IHS parallelism and tilt Pin dimensions Top side and back side component keepout dimensions QA La N Reference datums All drawing dimension are in mm in Dual Core Intel Xeon Processor 7000 Series Datasheet 33 Mechanical Specifications Figure 3 2 Processor Package Drawing
54. Vcc Power Other T2 IVe Power 0ther V7 Vss Power Other T3 Vgs Power Other V8 Mee Power Other T4 Vcc Power Other V9 Vss Power Other T5 Vss Power Other V23 Vss Power Other T6 Mee Power Other V24 Voco Power Other T7 Vgs Power Other V25 Vgs Power Other T8 Mee Power Other V26 Voc Power Other T9 Vss Power Other V27 Vos Power Other T23 Vss Power Other V28 Nee Power Other T24 Mee Power Other V29 Vss Power Other T25 Vsg Power Other V30 Mee Power Other T26 Mee Power Other V31 Vss Power Other 127 Vss PowerOther Wi Vcc Power Other T28 Voc Power Other W2 Vss Power Other T29 Vss Power Other W3 Reserved Tab Vcc CC Power 9ther W4 Vss Power Other 54 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Table 4 2 Pin Listing by Pin Number Cont d Pin Listing Table 4 2 Pin Listing by Pin Number Cont d Signal Buffer Signal Buffer Pin No Pin Name Type Direction Pin No Pin Name Type Direction W5 BCLK1 FSB CIk Input Y28 Reserved W6 TESTHIO Power Other Input Y29 SM TS1 A1 SMBus Input W7 TESTHI Power Other Input Y30 Nee Power Other W8 TESTHI2 Power Other Input Y31 PROCTYPE Power Other O W9 GTLREF1 Power Other Input AAT Vcc Power Other W23 GTLREFO Power Other Input AA2 Vss Power Other W24 Vss
55. Voc AA20 Power Other Vss B23 Power Other Vcc AA26 Power Other Vss B28 Power Other Vcc AA31 Power Other Vss C7 Power Other Voc AB2 Power Other Vss C13 Power Other Voc AB8 Power Other Vss C19 Power Other Vcc AB14 Power Other Vss C25 Power Other Vcc AB18 Power Other Vss C29 Power Other Vcc AB24 Power Other Vss D2 Power Other Vcc AB30 Power Other Vss D5 Power Other Vcc AC3 Power Other Vss D11 Power Other Vcc AC16 Power Other Vss D21 Power Other Voc AC22 Power Other Vss D28 Power Other Voc AC31 Power Other Vss D30 Power Other 46 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Pin Listing Table 4 1 Pin Listing by Pin Name Cont d Table 4 1 Pin Listing by Pin Name Cont d Pin Name Pin No i Direction Pin Name Pin No ku dm Direction Vss E9 Power Other Vss J31 Power Other Vss E15 Power Other Vss K2 Power Other Vss E17 Power Other Vss K4 Power Other Vss E23 Power Other Vss K6 Power Other Vss E29 Power Other Vss K8 Power Other Vss E31 Power Other Vss K24 Power Other Vss F2 Power Other Vss K26 Power Other Vss F7 Power Other Vss K28 Power Other Vss F13 Power Other Vss K30 Power Other Vss F19 Power Other Vss L1 Power Other Vss F25 Power Other Vss L3 Power Other Vss F28 Power Other Vss L5 Pow
56. Voc L8 Power Other Voc E20 Power Other Voc L24 Power Other Voc E26 Power Other Voc L26 Power Other Voc E28 Power Other Vcc L28 Power Other Voc E30 Power Other Voc L30 Power Other Voc FA Power Other Voc M23 Power Other Voc F4 Power Other Voc M25 Power Other Voc F29 Power Other Voc M27 Power Other Voc F31 Power Other Voc M29 Power Other Voc G2 Power Other Voc M31 Power Other Voc G4 Power Other Voc N23 Power Other Voc G6 Power Other Voc N25 Power Other Voc G8 Power Other Voc N27 Power Other Voc G24 Power Other Voc N29 Power Other Voc G26 Power Other Voc N31 Power Other Voc G28 Power Other Voc P2 Power Other Voc G30 Power Other Voc P4 Power Other Voc H23 Power Other Voc P6 Power Other Voc H25 Power Other Vec P8 Power Other Voc H27 Power Other Voc P24 Power Other Voc H29 Power Other Voc P26 Power Other Voc H31 Power Other Voc P28 Power Other Voc J2 Power Other Voc P30 Power Other Voc J4 Power Other Voc R23 Power Other Vec J6 Power Other Voc R25 Power Other Voc J8 Power Other Voc R27 Power Other Voc J24 Power Other Voc R29 Power Other Voc J26 Power Other Voc R31 Power Other Voc J28 Power Other Voc T2 Power Other Voc J30 Power Other Voc T4 Power Other Voc K23 Power Other Voc T6 Power Other Voc K25 Power Other Voc T8 Power Other Voc K27 Power Other Voc T24 Power Other Voc K29 Power Other Voc T26 Power Other Voc K31 Power Other Voc T28 Power Other Dual Core Intel Xeon Processor 7000 Seri
57. Vss Power Other AA29 SM EP AO SMBus Input Y20 DSTBPO Source Sync Input Output AA30 Vss Power Other Y21 DSTBNO4 Source Sync Input Output AA31 Nee Power Other Y22 Mee Power Other AB1 Vss Power Other Y23 D5 Source Sync Input Output AB2 Vcc Power Other Y24 D2 Source Sync Input Output AB3 BSEL1 Power Other J Output Y25 Vss Power Other AB4 VccA Power Other Input Y26 D0 Source Sync Input Output AB5 Vss Power Other Y27 Reserved AB6 D63s Source Sync Input Output Dual Core Intel Xeon Processor 7000 Series Datasheet 55 Pin Listing ntel S Table 4 2 Pin Listing by Pin Number Cont d Table 4 2 Pin Listing by Pin Number Cont d Pin No Pin Name Direction Pin No Pin Name Kur d Direction AB7 PWRGOOD Async GTL Input AC17 D34 Source Sync Input Output AB8 Vcc Power Other AC18 DPO Common Clk Input Output AB9 DBI3 Source Sync Input Output AC19 Vss Power Other AB10 D55 Source Sync Input Output AC20 D25 Source Sync Input Output AB11 Vss Power Other AC21 D26 Source Sync Input Output AB12 D51 Source Sync Input Output AC22 Vcc Power Other AB13 D52 Source Sync Input Output AC23 D23 Source Sync Input Output AB14 Vcc Power Other AC24 D20 Source Sync Input Output AB15 D37 Source Sync Input Output AC25 Vss Power Other AB16 D32 Source Sync Input Output A
58. a i Pa erue i a ERR S 38 3 9 Processor Pin Out Coordinates nene nea ana nana na 39 Pin Be TE 41 4 1 Dual Core Intel Xeon Processor 7000 Series Pin Assignments 41 4 1 1 Pin Listing by Pin Name semen nnn 41 4 1 2 Pin Listing by Pin Number 50 Signal RR Ur 59 5 1 Signal Definitions u eaae iens t etd ettet ing n ced endian rd da di ea a 59 Thermal Specifications U L L nene Akla kake deka ki daren ba duan diana a k d rennes 67 6 1 Package Thermal Specifications Ek nana aaa ana 67 6 1 1 Thermal Specifications L 67 6 12 Thermal Metrology uu u ya dareka eki raala ke yaka daa kk ahaa d aa a 70 6 2 Processor Thermal Features 70 6 2 1 Thermal Ne ul LEE 70 6 2 2 On Demand Mode A 71 6 2 3 PROCHOT Signal Pm 71 6 2 4 FORCEPR Signal Pin 72 6 2 5 THERMTRIP Signal Pin 72 6 2 6 Tcontrol and Fan Speed Reduction iui keke 72 6 2 Thermal Diode etae a a a T er a a Sq 72 Wap d LH S 73 7 1 Power On Configuration Options sse 73 7 2 Clock Control and Low Power Giates EEE kk ana ana 73 ZS Normal State cO d et a a ETE RR da tina 73 7 2 2 HALT Power Down State enne 74 7 2 8 Stop Grant State E 74 7 2 4 HALT Grant Snoop State sse 75 7 2 5 Enhanced HALT Powerdown Gtate kk kk kk 75 7 3 Enhanced Intel SpeedStep Technology 76 7 4 System Management Bus SMBus Interface sse 76 7 4 1 Processor Information RO
59. age Offset 1F 20h would contain 585h 1413 decimal and offset 21 22h would contain 4BOh 1200 decimal Tcase Maximum The last field within Processor Core Data is the Teasg Maximum field The field reflects temperature in degrees Celsius in hex format This data can be found in the Table 6 1 In the case of the Dual Core Intel Xeon processor 7000 series the thermal specifications are specified at the case IHS Dual Core Intel Xeon Processor 7000 Series Datasheet 91 Features 7 4 9 4 7 4 9 4 1 7 4 9 4 2 7 4 9 4 3 7 4 9 5 7 4 9 6 92 intel Cache Data This section contains cache related data L2 Cache Size Offset 27 28h is the L2 cache size field The field reflects the size of the level two cache for each core in kilobytes Example The Dual Core Intel Xeon processor 7000 series may have a 2 MB 2048 KB L2 cache per core Thus offset 27 28h will contain 800h L3 Cache Size Offset 29 2Ah is the L3 cache size field The field reflects the size of the level three cache in kilobytes Example The Dual Core Intel Xeon processor 7000 series does not have an L3 cache per core Thus offset 29 2Ah will contain Oh Cache Voltage There are two areas defined in the PIROM for the L3 cache voltages associated with the processor Offset 2B 2Ch is the Processor Cache VID Cache Voltage Identification or CVID field and contains the voltage requested via the CVID pins Because the Dual Core Intel
60. ation on the pending break event functionality including the identification of support of the feature and enable disable information refer to Vol 3 of the A 32 Intel Architecture Software Developer s Manual and the AP 485 Intel Processor Identification and the CPUID Instruction application note FORCEPR This input can be used to force activation of the Thermal Control Circuit GTLREF 3 0 GTLREF determines the signal reference level for AGTL input pins GTLREF is used by the AGTL receivers to determine if a signal is an electrical O or an electrical 1 Dual Core Intel Xeon Processor 7000 Series Datasheet 61 Signal Definitions Intel Table 5 1 Signal Definitions Sheet 4 of 7 Name Type Description HIT HITM y o y o HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together every other common clock Since multiple agents may deliver snoop results at the same time HIT and HITM are wire OR signals which must connect the appropriate pins of all processor FSB agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers HIT and HITM are activated on specific clock edges and sampled on specific clock edges IERR IERR Internal Error
61. c Asp must be at or below TcAsE_MAx as defined by the thermal profile see Figure 6 1 and Table 6 2 Otherwise the processor temperature can be maintained at Tcontrol Thermal Diode The processor incorporates an thermal diode on each processor core A thermal sensor located on the processor package monitors the die temperature of each core for thermal management long term die temperature change purposes The thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor Dual Core Intel Xeon Processor 7000 Series Datasheet T Features 7 1 Power On Configuration Options Several configuration options can be set by hardware The Dual Core Intel Xeon processor 7000 series samples its hardware configuration at reset on the active to inactive transition of RESET For specifications on these options refer to Table 7 1 The sampled information configures the processor for subsequent operation These configuration options can only be changed by another reset All resets configure the processor For most reset purposes the processor does not distinguish between a warm reset and a power on reset Table 7 1 Power On Configuration Option Pins Configuration Option Pin Notes Output tri state SMI 1 2 Execute BIST Built In Self Test INIT 1 2 In Order Queue de pipelining set IOQ depth to 1 A7 1 2 Disable MCERR obse
62. ch to the lower bus ratio and then transition to the lower VID While in the Enhanced HALT state the processor will process bus snoops The processor exits the Enhanced HALT state when a break event occurs When the processor exists the Enhanced HALT state it will first transition the VID to the original value and then change the bus ratio back to the original value Dual Core Intel Xeon Processor 7000 Series Datasheet 75 Features 7 3 7 4 76 Note Note intel Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology enables the processor to switch between multiple frequency and voltage points which may result in platform power savings In order to support this technology the system must support dynamic VID transitions Switching between voltage frequency states is software controlled For more configuration details also refer to the Prescott Nocona and Potomac Processor BIOS Writer s Guide BWG Not all processors are capable of supporting Enhanced Intel SpeedStep technology More details on which processor frequencies will support this feature will be provided in future releases of the NDA Specification Update Dynamic VID transitions will only occur if both cores request a lower operating frequency However only one core has to request a higher frequency for the VID to transition to a higher value Enhanced Intel SpeedStep Technology is a technology that creates processor performance states
63. cks when combined with a supporting operating system Execute Disable Bit allows the processor to classify areas in memory by where application code can execute and where it cannot When a malicious worm attempts to insert code in the buffer the processor disables code execution preventing damage or worm propagation Other features within the Intel NetBurst microarchitecture include Advanced Dynamic Execution Advanced Transfer Cache enhanced floating point and multi media unit Streaming SIMD Extensions 2 SSE2 and Streaming SIMD Extensions 3 SSE3 Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The Advanced Transfer Cache is a 2 MB or 1 MB per core on die level 2 L2 cache with increased bandwidth The floating point and multi media units include 128 bit wide registers and a separate register for data movement Streaming SIMD2 SSE2 instructions provide highly efficient double precision floating point SIMD integer and memory management operations In addition SSE3 instructions have been added to further extend the capabilities of Intel processor technology Other processor enhancements include core frequency improvements and microarchitectural improvements Dual Core Intel Xeon processor 7000 series are intended for high performance multi processor server systems with support for up to two processors on a 667 MHz FSB All versions of the Dual Core Intel Xeon processor 7000 series
64. d e E n I 3NI11N0 A18W3SSVSId Gel 393993 E 00 9399389 H Ern 29 9 EN E CH L T H O S310H DHL ONILNNOW 80 3208d 100 00y i 2004097 t 2010 4 01d Xr S0 0 2 1 Nid 139208 00661 I 3NI1400 XNISIV3H 6 88 4 1N3W0200 31V8v43S a NO NHOHS 38 1114 100433 NOILYT1n938 39V110A 031V3931N 30N343434 04 NMOHS GYVOE 1931 1180388510 XNISLV3H 1n0AV1 AVM ONY E eB anid y II EI 03132V88 SU3L3AIT1IN NI Q31VIS SNOISNINIG AUVHI d 86 6 Fels ISNY Ydd S39NV83101 ANY NOISN3WIQ Tv d 3114 Q311dd0S 3A0O 32N30303Ud 201 ONIMYUG STHL NO S39NYVY310L NV SNOISN3WIO 11V F114 3Sv8V1V0 Q311dd0S HLIM NOII1VI3UNOO NI 03SN 38 Ol 190 STHL I _ JAIS AYYNI Yd SN DEE EH et E Kau 3N0Z NOI1VHOdNOO 131N JO LN3SNOO NILLIYM NOlNd JHL LNOHLIM 03141004 YO 031Y14S10 0320008438 035012810 38 ION AVN ABOISH NOISIASH S1N31N02 SLI NV 32N30 iNO2 NI 0385019810 SI LI NOIIVWHOJNI 1VI1N30 3NO NOI1VHOdNOD 131NI SNIVINOO ONIMVHO SIHL l 262SL al as 8T n 9 L 9 Figure 8 2 Top Side Board Keepout Zones Part 1 99 Dual Core Intel Xeon Processor 7000 Series Datasheet Boxed Processor Specifications Figure 8 3 Top Side Board Keepout Zones Part 2 2 v 9 L 8 3 30 2 1335 OMENESC SI A38 g6261V om ONIAVA WONT WOS 6118 2506 V3 EVIS VINY
65. d by the EFLAGS IF bit being clear still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state HALT Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in Stop Grant state or in HALT Power Down state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor stays in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or HALT Power Down state as appropriate Enhanced HALT Powerdown State Enhanced HALT state is a low power state entered when all logical processors have executed the HALT or MWAIT instruction and Enhanced HALT state has been enabled via the BIOS When one of the logical processors executes the HALT instruction that logical processor is halted however the other processor continues normal operation The Enhanced HALT state is generally a lower power state than the Stop Grant state The processor will automatically transition to a lower core frequency and voltage operating point before entering the Enhanced HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first swit
66. d on the temperature reported by the processor s Thermal Diode If the diode temperature is greater than or equal to Tcontrol see Section 6 2 6 then the processor case temperature must remain at or below the temperature as specified by the thermal profile see Figure 6 1 If the diode temperature is less than Tcontrol then the case temperature is permitted to exceed the thermal profile but the diode temperature must remain at or below Tcontrol Systems that implement fan speed control must be designed to take these conditions into account Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications The Dual Core Intel Xeon processor 7000 series thermal profile ensures adherence to Intel reliability requirements The thermal profile is representative of a volumetrically unconstrained thermal solution i e industry enabled 2U heatsink In this scenario it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Refer to the Dual Core Intel Xeon9 Processor 7000 Sequence Thermal Mechanical Design Guidelines for details on system thermal solution design thermal profiles and environmental considerations Dual Core Intel Xeon Processor 7000 Series Datasheet 67 LU Thermal Specifications Ntel e 68 Table 6 1 The upper point of the thermal profile consists of the Thermal De
67. d that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable A thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Dual Core Intel Xeon Processor 7000 Sequence Thermal Mechanical Design Guidelines for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems utilizing the Dual Core Intel Xeon processor 7000 series must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the IA32 CLOCK MODULATION MSR is written to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processo
68. e Roeoeoeoeo Top View e e e e Tle e e e e e e e e e e e e Uoeoeoeoeo 00000060090 ve e e e e e e e e e e e e wle e e olo oo o 0 e e e vYeeeoceloeooeooeooeooeooeooeoo0looee A eeoooleooceooeooeoceooeooecoeclooee DOLL O O Set 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 e AC o e 0 Oj O 0 0 0 0 0 0 0 0 0 0 0 0 0 Oj0 0 0 AD e O O0 O 0 0 0 0 0 0 0 0 0 0 0 0 Oj0 0 AE OO Ol O O0 O0 0 O0 0 0 0 0 0 0 0 0 O0 6 O O 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 CLOCKS DATA O Signal VTT VCC O Reserved No Connect e Ground gt pS Ss CH 24 ZS st OT mp O U gt SSA 99A Dual Core Intel Xeon Processor 7000 Series Datasheet 39 Mechanical Specifications n Figure 3 7 Processor Pin Out Coordinates Bottom View Async COMMON ADDRESS COMMON JTAG CLOCK CLOCK 31 29 27 25 23 21 19 17 15 13 11 9 7 5 8 1 AeoeoeooelooeooleocooeocoeooeooQgee0o00 A Beeeeoceocleooeocloeoeooeooeoc eoeoeo B coeoeocoeocloeooelooeocoeooeoog oeeooeoc Deeeeecoejopoceooleoooceooeoogeooeocoee D Eeeeocooojeooeooeoeooeoc ooeooooe E Fo e e e co felt o o ejo o eo o eo 9 o o OOO CH Gle e e e e O e O e OG Heeoeoeoceo e e e H le e e e e e e e e e e 0 e e e e J Kl e e e
69. e have been exceeded It also indicates whether a conversion is in progress or an open circuit has been detected in either processor core thermal diode connection Once set alarm bits stay set until they are cleared by a Status Register read A successful read to the Status Register will clear any alarm bits that may have been set unless the Dual Core Intel Xeon Processor 7000 Series Datasheet n B Features alarm condition persists If the SM ALERT signal is enabled via the Thermal Sensor Configuration Register and a thermal diode threshold is exceeded an alert will be sent to the platform via the SM ALERT signal Table 7 12 SMBus Thermal Sensor Status Register 1 Bit Name Reset State Function 7 MSB BUSY N A If set indicates that the device s analog to digital converter is busy RESERVED RESERVED Reserved for future use 5 RESERVED RESERVED Reserved for future use 4 R1HIGH 0 If set indicates the processor core 1 thermal diode high temperature alarm has activated 3 R1LOW 0 If set indicates the processor core 1 thermal diode low temperature alarm has activated 2 R1OPEN 0 If set indicates an open fault in the connection to the processor core 1 diode 1 RESERVED RESERVED Reserved for future use 0 LSB RESERVED RESERVED Reserved for future use Table 7 13 SMBus Thermal Sensor Status Register 2 7 4 6 4 Bit Name Reset State Function 7 MSB RESERVE
70. eatsinks with minimal airflow blockage and minimal bypass These retention mechanisms can allow the use of much heavier heatsink masses compared to legacy Dual Core Intel Xeon Processor 7000 Series Datasheet 8 3 8 3 1 8 3 2 Boxed Processor Specifications solution limitations by using a load path attached to the chassis pan The hat spring on the under side of the baseboard provides the necessary compressive load for the thermal interface material The baseboard is intended to be isolated such that the dynamic loads from the heatsink are transferred to the chassis pan via the heatsink screws and heatsink standoffs This reduces the risk of package pullout and solder joint failures in a shock and vibe situation The assembly requires larger diameter holes to compensate for the CEK spring embosses See Figure 8 2 and Figure 8 3 for processor mounting thorough holes Thermal Specifications This section describes the cooling requirements of the heatsink solution utilized by the boxed processor Boxed Processor Cooling Requirements The boxed processor will be cooled by forcing ducted chassis fan airflow through the passive heatsink solution Meeting the processor s temperature specifications is a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Section 6 of this document For the boxed processor passive heatsink to opera
71. ecifications in this table apply to all processor frequencies DLO Qu duco I Table 2 17 SMBus Signal Group DC Specifications The V 7 represented in these specifications refers to instantaneous Vr Vu is defined as the voltage range at a receiving agent that will be interpreted as a logical low value Viu is defined as the voltage range at a receiving agent that will be interpreted as a logical high value Refer to Table 2 5 to determine which signals include additional on die termination resistance R Leakage to Vgg with pin held at Vr Leakage to Vyr with pin held at 300 mV Symbol Parameter Min Max Unit Notes 1 2 Vu Input Low Voltage 0 30 0 30 SM VCC V Vin Input High Voltage 0 70 SM_VCC 3 465 V VoL Output Low Voltage 0 0 400 V lov Output Low Current N A 3 0 mA lui Input Leakage Current N A 10 HA lio Output Leakage Current N A 10 HA Coup SMBus Pin Capacitance 15 0 pF 3 NOTES 1 These parameters are based on design characterization and are not tested 2 All DC specifications for the SMBus signal group are measured at the processor pins 3 Platform designers may need this value to calculate the maximum loading of the SMBus and to determine maximum rise and fall times for SMBus signals Dual Core Intel Xeon Processor 7000 Series Datasheet 31 Electrical Specifications 32 Dual Core Intel Xeon Processor 7000 Series Datasheet Mechanical Specifications
72. egulator Module VRM and Enterprise Voltage Regulator Down ERVD 10 2 Design Guidelines for socket loadline guidelines and VR implementation Dual Core Intel Xeon Processor 7000 Series Datasheet 27 Electrical Specifications Figure 2 4 Vcc Static and Transient Tolerance Vcc V VID VID VID VID VID VID VID VID VID VID VID VID VID 0 000 0 020 4 0 040 4 0 060 4 0 080 4 0 100 4 0 120 4 0 140 4 0 160 4 0 180 4 0 200 4 0 220 4 0 240 Icc A 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 V cc Maximum Typical V cc Minimum 2 9 2 NOTES The Voc min and Vcc max loadlines represent static and transient limits The Voc min and Voc max loadlines are plots of the discrete point found in Table 2 9 Refer to Table 2 8 for processor VID information The loadlines specify voltage limits at the die measured at the VOCSENSE and VSSSENSE pins Voltage regulation feedback for voltage regulator circuits must be taken from processor Vcc and Vss pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 2 Design Guidelines for socket loadline guidelines and VR implementation AON Vcc Overshoot Specification The Dual Core Intel Xeon processor 7000 series processor can tolerate short transient overshoot events whe
73. elf Test BIST LINTO INTR LINT1 NMI LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all FSB agents When the APIC functionality is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK yo LOCK indicates to the system that a set of transactions must occur atomically This signal must connect the appropriate pins of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MCERR yo MCERR Machine Check Error is asserted to indicate an unrecoverable error or a bus protocol violation It may be driven by all processor FSB agents MCERR assertion conditions are confi
74. ent should be less than 0 05 MHz 4 fcore represents the maximum care frequency supported by the platform Voltage Identification VID The VID 5 0 pins supply the encodings that determine the voltage to be supplied by the Vcc the core voltage for the Dual Core Intel Xeon processor 7000 series voltage regulator The VID specification for the Dual Core Intel Xeon processor 7000 series is defined by the Vcc Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 2 Design Guidelines The voltage set by the VID pins is the maximum Vcc voltage allowed by the Dual Core Intel Xeon Processor 7000 Series Datasheet 17 Electrical Specifications Ntel processor A minimum Vcc voltage is provided in Table 2 7 and changes with frequency This allows processors running at a higher frequency to have a relaxed minimum Vcc voltage specification The specifications have been set such that one voltage regulator can work with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings Furthermore any Dual Core Intel Xeon processor 7000 series even those on the same processor FSB can drive different VID settings during normal operation The Dual Core Intel Xeon processor 7000 series uses six voltage identification pins VID 5 0 to support automatic selection of power supply voltages Table 2 3 specifi
75. er ACHT D43 Source Sync Input Output AD21 D29 Source Sync Input Output AC12 D41 Source Sync Input Output AD22 DBI1 Source Sync Input Output AC13 vss jPowe Ohe AD23 Mes Power otner AC14 D50 Source Sync Input Output AD24 D21 Source Sync Input Output AC15 DP2 Common CIk Input Output AD25 D18 Source Sync Input Output AC16 vec Powrthr AD26 Voc Power otner 56 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Table 4 2 Pin Listing by Pin Number Cont d Pin Listing Table 4 2 Pin Listing by Pin Number Cont d Pin No Pin Name t a Direction Pin No Pin Name T Direction AD27 D4 Source Sync Input Output AE14 Voc Power Other AD28 SM ALERT SMBus Output AE15 Don t Care AD29 SM WP SMBus Input AE16 Don t Care AD30 Dont Care AE17 DP3 Common Clk Input Output AD31 Don t Care AE18 Nee Power Other AE2 Don t Care AE19 DP1 Common Clk Input Output AE3 Don t Care AE20 D28 Source Sync Input Output AE4 Vr Power Other AE21 Vss Power Other AER TESTHI6 Power Other Input AE22 D27 Source Sync Input Output AE6 Vss Power Other Input AE23 D22 Source Sync Input Output AE7 D58 Source Sync Input Output AE24 Vcc Power Other AE8 Don tCare AE25 D19 Source Sync Input Output AE9 D444 Source Sync Input Output AE26 D164 Source Sync Input Ou
76. er K4 Vss Power Other M9 Dont Care K5 Don t Care M23 Vcc Power Other K6 Vss Power Other M24 Vgg Power Other K7 Don t Care M25 Voc Power Other K Vss Power Other M26 Vss Power Other K9 Dont Care M27 Vcc Power Other K23 Mee Power Other M28 Vss Power Other K24 Vss Power Other M29 Mee Power Other K25 Nee Power Other M30 Vss Power Other K26 Vss Power Other M31 Vcc Power Other K27 Nee Power Other N1 Don t Care K28 Vss Power Other N2 Vss Power Other K29 Nee Power Other N3 Don t Care K30 Vss Power Other N4 Vss Power Other K31 Vcc Power Other N5 Don t Care L1 Vss Power Other N6 Vss Power Other L2 Nee Power Other N7 Don Care L3 Vss Power Other N8 Vss Power Other L4 Voc Power Other N9 Don t Care L5 Vss Power Other N23 Voc Power Other L6 Voc Power Other N24 Vss Power Other L7 Vss Power Other N25 Voc Power Other L8 Nee Power Other N26 Vos Power Other L9 Vss Power Other N27 Nee Power Other L23 Vss Power Other N28 Vss Power Other L24 Mee Power Other N29 Mee Power Other L25 Vss Power Other N30 Vss Power Other L26 Nee Power Other N31 Voc Power Other L27 Vss Power Other P1 Vss Power Other L28 Nee Power Other P2 Vcc Power Other L29 Vss Power Other P3 Vss Power Other L30 Nee Power Other P4 Voc Power Other L31 Vss Power Other P5 Vss Power Other M1 Don t Care P6 Voc Power Other M2 Vgg Power Other P7 Vss Power Other M3 Don t Care P8 Vcc Power Other MA Vss Power Other P9 Vss Power Ot
77. er Other Vss F30 Power Other Vss L7 Power Other Vss G1 Power Other Vss L9 Power Other Vss G3 Power Other Vss L23 Power Other Vss G5 Power Other Vss L25 Power Other Vss G9 Power Other Vss L27 Power Other Vss G25 Power Other Vss L29 Power Other Vss G27 Power Other Vss L31 Power Other Vss G29 Power Other Vss M2 Power Other Vss G31 Power Other Vss M4 Power Other Vss H2 Power Other Vss M6 Power Other Vss H4 Power Other Vss M8 Power Other Vss H6 Power Other Vss M24 Power Other Vss H8 Power Other Vss M26 Power Other Vss H24 Power Other Vss M28 Power Other Vss H26 Power Other Vss M30 Power Other Vss H28 Power Other Vss N2 Power Other Vss H30 Power Other Vss N4 Power Other Vss J1 Power Other Vss N6 Power Other Vss J3 Power Other Vss N8 Power Other Vss J5 Power Other Vss N24 Power Other Vss J7 Power Other Vss N26 Power Other Vss J9 Power Other Vss N28 Power Other Vss J23 Power Other Vss N30 Power Other Vss J25 Power Other Vss P1 Power Other Vss J27 Power Other Vss P3 Power Other Vss J29 Power Other Vss P5 Power Other Dual Core Intel Xeon Processor 7000 Series Datasheet 47 intel Pin Listing Table 4 1 Pin Listing by Pin Name Cont d Table 4 1 Pin Listing by Pin Name Cont d Pin Name Pin No Die Direction Pin Name Pin No Pa Direction Vss P7 Power Other Vss V23
78. ers and workstations Integrated Heat Spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface mPGA604 The Dual Core Intel Xeon processor 7000 series mates with the system board through this surface mount 604 pin zero insertion force ZIF socket OEM Original Equipment Manufacturer Dual Core Intel Xeon Processor 7000 Series The entire product including processor core substrate and integrated heat spreader IHS Processor core The processor s execution engine All AC timing and signal integrity specifications are to the pads of the processor core Processor Information ROM PIROM A memory device located on the processor and accessible via the System Management Bus SMBus which contains information regarding the processor s features This device is shared with the Scratch EEPROM is programmed during manufacturing and is write protected Scratch EEPROM Electrically Erasable Programmable Read Only Memory A memory device located on the processor and addressable via the SMBus which can be used by the OEM to store information useful for system management SMBus System Management Bus A two wire interface through which simple system and power management related devices can communicate with the rest of the system It is based on the principals of the operation of the I2C two w
79. es Datasheet 45 intel Pin Listing Table 4 1 Pin Listing by Pin Name Cont d Table 4 1 Pin Listing by Pin Name Cont d Pin Name Pin No Die Direction Pin Name Pin No Pa Direction Vcc T30 Power Other Vec AD2 Power Other Vcc U23 Power Other Vcc AD20 Power Other Voc U25 Power Other Voc AD26 Power Other Voc U27 Power Other Voc AE14 Power Other Voc U29 Power Other Voc AE18 Power Other Vcc U31 Power Other Vcc AE24 Power Other Vcc v2 Power Other Voca AB4 Power Other Input Voc V4 Power Other Vcc oPLL AD4 Power Other Input Vec V6 Power Other VCCSENSE B27 Power Other Output Vec V8 Power Other VIDO F3 Power Other Output Voc V24 Power Other VID1 E3 Power Other Output Voc V26 Power Other VID2 D3 Power Other Output Voc V28 Power Other VID3 C3 Power Other Output Vec V30 Power Other VID4 B3 Power Other Output Voc Wi Power Other VID5 A1 Power Other Output Voc W25 Power Other VIDPWRGD B1 Power Other Input Voc W27 Power Other Vss A5 Power Other Voc W29 Power Other Vss A11 Power Other Vcc W31 Power Other Vss A21 Power Other Voc Y2 Power Other Vss A27 Power Other Voc Y16 Power Other Vss A29 Power Other Voc Y22 Power Other Vss B2 Power Other Voc Y30 J Power Other Vss B9 Power Other Voc AA1 Power Other Vss B15 Power Other Vec AA6 Power Other Vss B17 Power Other
80. es the voltage level corresponding to the state of VID 5 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty i e when the voltage regulator sees VID 5 0 2 111111 or VID 5 0 2 011111 or the voltage regulation circuit cannot supply the voltage that is requested the processor s voltage regulator must disable itself See the Vcc Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 2 Design Guidelines for more details The Dual Core Intel Xeon processor 7000 series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 2 8 includes VID step sizes and DC shift ranges The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for VID transitions are included in Table 2 8 and Table 2 9 Please refer to the Vcc Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 2 Design Guidelines for more details Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable Further detail
81. essor 7000 Series Datasheet Intel 7 4 9 6 1 7 4 9 6 2 7 4 9 7 7 4 9 7 1 7 4 9 7 2 Features Processor Part Number Offset 38 3Eh contains seven ASCII characters reflecting the Intel part number for the processor This information is typically marked on the outside of the processor If the part number is less than 7 characters a leading space is inserted into the value The part number should match the information found in the marking specification found in Section 3 Example The Intel Xeon processor with 512 KB L2 cache 533 MHz FSB has a part number of 80532KE Thus the data found at offset 38 3Eh is 38 30 35 33 32 4B 45 Processor Electronic Signature Offset 4D 54h contains a 64 bit identification number Intel does not guarantee that each processor will have a unique value in this field Feature Data This section provides information on key features that the platform may need to understand without powering on the processor Processor Core Feature Flags Offset 74 77h contains a copy of results in EDX 31 0 from Function 1 of the CPUID instruction These details provide instruction and feature support by product family A decode of these bits is found in the Prescott Nocona and Potomac Processor BIOS Writer s Guide BWG or the AP 485 Intel Processor Identification and CPUID Instruction application note Processor Feature Flags Offset 78h provides feature information for the processor This fie
82. et 6 of 7 Name Type Description SM EP A 2 0 The SM EP A EEPROM Select Address pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors To set an SM EP A line high a pull up resistor should be used that is no larger than 1 KQ The processor includes a 10 KQ pull down resistor to Vss for each of these signals For more information on the usage of these pins see Section 7 4 8 SM TS A 1 0 The SM TS A Thermal Sensor Select Address pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors The device s addressing as implemented includes a Hi Z state for both address pins The use of the Hi Z state is achieved by leaving the input floating unconnected For more information on the usage of these pins see Section 7 4 8 SM VCC SM VCC provides power to the SMBus components on the Dual Core Intel Xeon processor 7000 series package SM WP WP Write Protect can be used to write protect the Scratch EEPROM The Scratch EEPROM is write protected when this input is pulled high to SM VCC The processor includes a 10 KQ pull down resistor to Vgg for this signal SMI SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt processors
83. ex bytes The PIROM is 128 bytes thus offset 01 02h would be programmed to 80h Processor Data This section contains two pieces of data The S spec QDF of the part in ASCII format 1 2 bit field to declare if the part is a pre production sample or a production unit The S spec QDF field is six ASCII characters wide and is programmed with the same S spec QDF value as marked on the processor If the value is less than six characters in length leading spaces 20h are programmed in this field Example A processor with a QDF mark of QEUS contains the following in field OE 13h 20 20 51 45 55 35h This data consists of two blanks at OEh and OFh followed by the ASCII codes for QEUS in locations 10 13h Offset 14h contains the sample production field which is a two bit field and is LSB aligned All Q spec material will use a value of 00b All S spec material will use a value of 01b All other values are reserved Example A processor with a Qxxx mark engineering sample will have offset 14h set to 00b A processor with an Sxxxx mark production unit will use 01b at offset 14h Processor Core Data This section contains core silicon related data CPUID The CPUID field is a copy of the results in EAX 13 0 from Function 1 of the CPUID instruction The field is not aligned on a byte boundary since the first two bits of the offset are reserved Thus the data must be shifted right by two in order to obtain the same resu
84. frequency selected by a 166 MHz BCLK 1 0 frequency respectively Individual processors operate at the FSB frequency specified by BSEL 1 0 For more information about these pins refer to Section 5 1 and the appropriate platform design guide BSEL 1 0 Frequency Table for BCLK 1 0 BSEL1 BSELO Function 0 0 RESERVED 0 1 RESERVED 1 0 RESERVED 1 1 166 MHz Dual Core Intel Xeon Processor 7000 Series Datasheet Electrical Specifications Phase Lock Loop PLL Power and Filter VccA VCCIOPLL are power sources required by the PLL clock generators on the Dual Core Intel Xeon processor 7000 series These are analog PLLs and they require low noise power supplies for minimum jitter These supplies must be low pass filtered from Vyr The AC low pass requirements with input at Vpr are as follows lt 0 2 dB gain in pass band lt 0 5 dB attenuation in pass band lt 1 Hz gt 34 dB attenuation from 1 MHz to 66 MHz 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 2 2 For recommendations on implementing the filter refer to the appropriate platform design guide Figure 2 2 Phase Lock Loop PLL Filter Requirements 2 2 28dB lt DC 1 Hz fpeak 1 MHz 66 MHz fcore dk passband high frequency band NOTES 1 Diagram not to scale 2 No specification for frequencies beyond f ore core frequency 3 foeak if exist
85. gnal to power or ground a resistor will also allow for system testability For unused AGTL input or I O signals use pull up resistors of the same value as the on die termination resistors Rp See Table 2 15 TAP Asynchronous GTL inputs and Asynchronous GTL outputs do not include on die termination Inputs and utilized outputs must be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the appropriate platform design guidelines Don t Care pins are pins on the processor package that are not connected to the processor die These pins can be connected on the motherboard in any way necessary for compatible motherboard designs to support other processor versions The TESTHI pins should be tied to Vyr using a matched resistor where a matched resistor has a resistance value within 20 of the impedance of the board transmission line traces For example if the trace impedance is 50 Q then a value between 40 Q and 60 Q is required The TESTHI pins may use individual pull up resistors or be grouped together as detailed below Please note that utilization of boundary scan test will not be functional if pins are connected together A matched resistor should be used for each group TESTHI 3 0 TES
86. gurable at a system level Assertion options are defined as follows Enabled or disabled Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the A 32 Intel Software Developer s Manual Volume 3 System Programming Guide or the BIOS Writer s Guide which includes the Dual Core Intel Xeon processor 7000 series Since multiple agents may drive this signal at the same time MCERR is a wired OR signal which must connect the appropriate pins of all processor FSB agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers MCERR is activated on specific clock edges and sampled on specific clock edges 62 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Signal Definitions Table 5 1 Signal Definitions Sheet 5 of 7 Name Type Description ODTEN ODTEN On die termination enable should be connected to Ver through a resistor to enable on die termination for end bus agents For middle bus agents pull this signal down via a resistor to ground to disable on die termination Whenever ODTEN is high on die termination will be active regardless of other states of the bus PROCHOT The assertion
87. gure 3 4 Processor Topside Markings 2D Matrix EOM E Includes ATPO and Serial Number front end mark i m 05 Pin 1 Indicator NOTES 1 All characters will be in upper case Figure 3 5 Processor Bottom Side Markings Pin 1 Indicator N Speed Cache Bus Voltage Pin Field 3000MP 2MB 667 1 425V SL6NY COSTA RICA lt S Spec C0096109 0021 Country of Assy FPO Serial 13 Characters 38 Dual Core Intel Xeon Processor 7000 Series Datasheet Intel 3 9 Processor Pin Out Coordinates Mechanical Specifications Figure 3 6 shows the top view of the processor pin coordinates The coordinates are referred to throughout the document to identify processor pins Figure 3 6 Processor Pin Out Coordinates Top View COMMON ADDRESS COMMON Async CLOCK CLOCK JTAG 1 3 5 7 9 11 18 15 17 19 21 23 25 27 29 31 loeoee eogoeocoeooeoooelooeocleooeoeoo Boeooooocoeooeooeoeolooeooelooooeooo cleoooeoo opooeooeoooocleooeocloeoooeco Doeooeooepoeooeoooelooeooleoooeoee Eeooooeooe ooeooeoeojoeooeocoeoceeee Fee o e o o e 000006000006 0000000000600 Gle e e e e e O e O 0 e e Hoeoeoeoeo e e e e lle e e e e e e e e e e e e Koeoeoeoeo 00000060090 8 LJe e e e e e e e e e e e e e gt Moeoeoeoeo 060000060090 8 Noeoeoeoeo Rrocessof e e e gt ple ee e e e e e e e e
88. h 0 5 Vtr Vuvs MIN 0 5 Vrr Vuvs max V 3 Threshold Voltage Vu Input High to Low 0 5 Vrr Vuvs Max 0 5 Vrr Vuvs MIN V 3 Threshold Voltage Von Output High Voltage N A Vr V 1 2 4 loL Output Low Current 45 mA 4 liL Input Leakage Current N A 200 HA 30 Dual Core Intel Xeon Processor 7000 Series Datasheet Electrical Specifications Table 2 15 PWRGOOD Input and TAP Signal Group DC Specifications Sheet 2 of 2 Symbol Parameter Min Max Unit Notes lot Output Leakage Current N A 200 HA RoN Buffer On Resistance 4 8 Q NOTES 1 All outputs are open drain 2 The VI represented in these specifications refers to instantaneous Vrr 3 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load 4 Vpys represents the amount of hysteresis nominally centered about 0 5 Ver for all PWRGOOD and TAP inputs Table 2 16 GTL Asynchronous and AGTL Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vit Input Low Voltage 0 0 GTLREF 0 10 Mad V 2 3 Vu Input High Voltage GTLREF 0 10 Vr Vr V 2 4 Vou Output High Voltage 0 90 Vr Vr V 2 loL Output Low Current N A 50 mA 2 5 lu Input Leakage Current N A 200 HA 6 7 lio Output Leakage Current N A 200 HA 6 7 Ron Buffer On Resistance 4 8 Q NOTES 1 Unless otherwise noted all sp
89. h Definitions Bit Definition 6 Reserved Enhanced Halt State Intel Virtualization Technology Execute Disable Intel 64 N Gol O N 1 Thermal Monitor 2 0 Enhanced Intel Speed Step Technology Bits are set when a feature is present and cleared when they are not 7 4 9 7 5 Thermal Adjustment Factors Offsets 7B 7Ch provides information on thermal adjustment factors for the processor This field and it s details are pending and will be updated in a future revision The field is defined as follows Table 7 21 Offset 7Bh Definitions Bit Definition 15 8 Measurement Correction Factor 7 0 Temperature Target 7 4 9 8 Other Data Addresses 7D 7E are listed as reserved 7 4 9 9 Checksums The PIROM includes multiple checksums Table 7 22 includes the checksum values for each section defined in the 128 byte ROM except Other Data 94 Dual Core Intel Xeon Processor 7000 Series Datasheet j ntel B Features Table 7 22 128 Byte ROM Checksum Values Section Checksum Address Header ODh Processor Data 15h Processor Core Data 24h Cache Data 3th Package Data 37h Part Number Data 6Fh Thermal Reference Data 73h Feature Data 7Fh Other Data None Defined Checksums are automatically calculated and programmed by Intel The first step in calculating the checksum is to add each byte from the field to the next subseque
90. h logic level L Low logic level Front side bus refers to the interface between the processor system core logic i e the chipset components and other bus agents The FSB supports multiprocessing and cache coherency For this document front side bus is used as the generic term for the Dual Core Intel Xeon processor 7000 series system bus Commonly used terms are explained here for clarification FC mPGA4 The Dual Core Intel Xeon processor 7000 series is available in a Flip Chip Micro Pin Grid Array 4 package consisting of a processor core mounted on a pinned substrate with an integrated heat spreader IHS This packaging technology employs a 1 27 mm 0 05 in pitch for the substrate pins Front Side Bus FSB The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O Dual Core Intel Xeon Processor 7000 Series Datasheet Note Introduction transactions as well as interrupt messages pass between the processor and chipset over the FSB Functional Operation Refers to the normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology is the next generation implementation of Geyserville technology which extends power management capabilities of serv
91. h provides the maximum core frequency for the processor The frequency should equate to the markings on the processor and or the QDF S spec speed even if the parts are not limited or locked to the intended speed Format of this field is in MHz rounded to a whole number and encoded in hex format Example A 2 8 GHz processor will have a value of OAFOh which equates to 2800 decimal Core Voltage There are two areas defined in the PIROM for the core voltages associated with the processor Offset 1F 20h is the Processor Core VID Voltage Identification field and contains the voltage requested via the VID pins In the case of the Dual Core Intel Xeon processor 7000 series this is 1 3875 V This field rounded to the next thousandth is in mV and is reflected in hex This data 1s also in Table 2 8 Some systems read this offset to determine if all processors support the same default VID setting Minimum core voltage is reflected in offset 21 22h This field is in mV and reflected in hex The minimum VCC reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw The minimum core voltage value in offset 21 22h is a single value that assumes the FMB maximum current draw Refer to Table 2 8 for the actual minimum core voltage specifications based on actual real time current draw Example The specifications for a Dual Core Intel Xeon processor 7000 series at FMB are 1 4125 V VID and 1 200 V minimum volt
92. hanical and thermal specifications must be satisfied 2 Overshoot and undershoot voltage guidelines for input output and I O signals are outlined in Table 2 11 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no pins can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any packaging or trays Dual Core Intel Xeon Processor 7000 Series Datasheet 23 Electrical Specifications 2 9 2 9 1 Processor DC Specifications The following notes apply The processor DC specifications in this section are defined at the processor core silicon and not at the package pins unless noted otherwise The notes associated with each parameter are part of the specification for that parameter Unless otherwise noted all specifications in the tables apply to all frequencies and cache sizes See Section 5 for the pin signal definitions Most of the signals on the processor FSB are in the AGTL signal group The DC specifications for these signals are listed in Table 2 14 Table 2 8 lists the DC specifications for the Dual Core Intel Xeon processor 7000
93. he current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the AP 1 0 signal description for details on parity checking of these signals RESET Asserting the RESET signal resets all processors to known states and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least 1 ms after Vcc and BCLK have reached their specified levels On observing active RESET all FSB agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms after PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in Section 7 1 RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor FSB agents RSP RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor FSB agents A correct parity signal is electrically high if an even number of covered signals are electrically low and electrically low if an odd number of co
94. her M5 Don t Care P23 Vsg Power Other M6 Vss Power Other P24 Vcc Power Other M7 Don t Care P25 Vsg Power Other Dual Core Intel Xeon Processor 7000 Series Datasheet 53 Pin Listing ntel S Table 4 2 Pin Listing by Pin Number Cont d Table 4 2 Pin Listing by Pin Number Cont d Pin No Pin Name em Direction Pin No Pin Name iii Ea Direction P26 Vcc Power Other T31 Vas Power Other P27 Vsg Power Other U1 Don t Care P28 Vcc Power Other U2 Vss Power Other P29 Vss Power Other US Don t Care P30 Mee Power Other U4 Vss Power Other P31 Vss Power Other U5 Don t Care R1 Don t Care U6 Vss Power Other R2 Vss Power Other U7 Don Care R3 Don t Care U8 Vss Power Other R4 Vss Power Other U9 Don Care R5 DontCae U23 Voc Power Other R6 Vss Power Other U24 Vss Power Other R7 Don Care U25 Vcc Power Other R8 Vss Power 9ther U26 Vss Power Other R9 Don t Care U27 Vcc Power Other R23 Vcc Power Other U28 Vss Power Other Re4 Vss Power Other U29 Vcc Power Other R25 Vcc Power Other U30 Vss Power Other R26 Vsg Power Other U31 Mee Power Other R27 Vcc Power Other V1 Vss Power Other R28 Vss Power Other V2 Vcc Power Other R29 Vcc Power Other V3 Vss Power Other R30 Vss Power Other V4 Voc Power Other R31 Vcc Power Other V5 Vss Power Other T1 Vss Power Other V6
95. hese mechanical load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solutions The minimum loading specification must be maintained by any thermal and mechanical solution Table 3 1 Processor Loading Specifications Parameter Minimum Maximum Unit Notes Static Compressive 44 222 N 1 2 3 4 Load 10 50 Ibf 44 288 N 1 2 3 5 10 65 Ibf Dynamic 222 N 0 45 kg 100 G N 1 3 4 6 7 Compressive Load 50 Ibf static 1 Ibm 100 G lbf 288 N 0 45 kg 100 G N 1 3 5 6 7 65 Ibf static 1 Ibm 100 G Ibf Transient 445 N 1 3 8 100 Ibf ed NOTES 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These parameters are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 This specification applies for thermal retention solutions that allow baseboard deflection 5 This specification applies either for thermal retention solutio
96. imits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes 2 Voc Processor core supply voltage with 0 3 1 55 V respect to Vss Vr Front side bus termination voltage with 0 3 1 55 V respect to Vss TcAsE Processor case temperature See Section 6 See Section 6 C TsTORAGE Processor storage temperature 40 85 C 3 4 NOTES 1 For functional operation all processor electrical signal quality mec
97. ines are based on limited testing for design characterization 3 A tensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface 4 Atorque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface Package Insertion Specifications The Dual Core Intel Xeon processor 7000 series can be inserted into and removed from a mPGA604 socket 15 times The socket should meet the mPGA604 requirements detailed in the mPGA604 Socket Design Guidelines Processor Mass Specifications The typical mass of the Dual Core Intel Xeon processor 7000 series is 0 0784 Ib 1 2544 oz 35 5616 g to 0 0788 Ib 1 2608 oz 35 743 g This mass weight includes all the components that are included in the package Processor Materials Table 3 3 lists some of the package components and associated materials Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Pins Gold Plated Copper Dual Core Intel Xeon Processor 7000 Series Datasheet 37 Mechanical Specifications Ntel 6 3 8 Processor Markings Figure 3 4 shows the topside markings and Figure 3 5 shows the bottom side markings on the processor These diagrams are to aid in the identification of the Dual Core Intel Xeon processor 7000 series Please note that the figures in this section are not to scale Fi
98. ions N DD a aaa necati Kn 31 SMBus Signal Group DC Specifications nenea nana 31 Processor Loading Specifications nana kk kk na 36 Package Handling Guidelines nenea ana nana 37 Processor Materlals sited eet i cce O K xa qaa a KA e oboe ideas 37 Pin Listing by Pin Name ua sa be ki k l n nennen nnne nter ek e 41 Pin Listing by Pin Number 50 Signal Definitions ae kila eret RR RR REV ERR ai aaa En de d xan aa 0 59 Dual Core Intel Xeon Processor 7000 Series Thermal Specifications 68 Dual Core Intel Xeon Processor 7000 Series Thermal Profile A 69 Power On Configuration Option Pins 73 Processor Information ROM Format 78 Read Byte SMBu s Packet 5 i ite td Peer ident arg 80 Write Byte SMBus Packet EEE kek kk k k A KAKA KAK nens 81 Write Byte SMBus Packet T kek nana nens 81 Read Byte SMBus Packet kk kk kk ke kek kk kk kk KAK ana na 82 Send Byte SMBus Packet nennen nens 82 Receive Byte SMBus Packet eene nennen 82 ARA SMBus Packet anite e title t iaa W Zad ka 82 SMBus Thermal Sensor Command Byte Assignments 83 Temperature Value Register Encoding ui nana nana ana 84 SMBus Thermal Sensor Status Register 1 anna 85 SMBus Thermal Sensor Status Register 2 sss 85 SMBus The
99. ire serial bus from Phillips Semiconductor DC is a two wire communications bus protocol developed by Philips SMBus is a subset of the DC bus protocol and was developed by Intel Implementations of the DC bus protocol or the SMBus bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor pins should not be connected to any supply voltages have any I Os biased or receive any clocks Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are known as Symmetric MultiProcessing SMP systems Dual Core Intel Xeon processor 7000 series should only be used in SMP systems which have two or fewer symmetric agents per FSB Dual Core Intel Xeon Processor 7000 Series Datasheet 13 Introduction N 1 2 Reference Documents Material and concepts available in the following documents may be beneficial when reading this document Document Intel Order Number AP 485 Intel Processor Identification and the CPUID Instruction 241618 IA 32 Intel Architecture S
100. its maximum operating temperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The Thermal Monitor must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor is enabled and a high temperature situation exists 1 e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 5096 Clocks will not be off for more than 3 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum Dual Core Intel Xeon Processor 7000 Series Datasheet 6 2 2 6 2 3 Thermal Specifications operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a thermal solution designed to meet the thermal profile it is anticipate
101. l processors must be in the Stop Grant state before the deassertion of STPCLK Since the AGTL signal pins receive power from the FSB these pins should not be driven allowing the level to return to V rr for minimum power drawn by the termination resistors in this state In addition all other input pins on the FSB should be driven to the inactive state Dual Core Intel Xeon Processor 7000 Series Datasheet 7 2 4 7 2 5 Features BINIT is not serviced while the processor is in Stop Grant state The event is latched and can be serviced by software upon exit from the Stop Grant state RESET causes the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state occurs with the deassertion of the STPCLK signal A transition to the HALT Grant Snoop state occurs when the processor detects a snoop on the FSB see Section 7 2 4 While in the Stop Grant state SMI INIT BINIT and LINT 1 0 are latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event is recognized upon return to the Normal state While in Stop Grant state the processor processes snoops on the FSB and latches interrupts delivered on the FSB The PBE signal can be driven when the processor is in Stop Grant state PBE is asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocke
102. ld is defined as follows Table 7 18 Offset 78h Definitions 7 4 9 7 3 Bit Definition Multi Core set if the processor is a dual core processor Serial signature set if there is a serial signature at offset 4D 54h Electronic signature present set if there is a electronic signature at 4D 54h Thermal Sense Device present set if an SMBus thermal sensor on package Reserved OEM EEPROM present set if there is a scratch ROM at offset 80 FFh N wo BR Q O N Core VID present set if there is a VID provided by the processor 0 Reserved Bits are set when a feature is present and cleared when they are not Processor Thread and Core Information Offset 79h provides information regarding the number of cores and threads on the processor Table 7 19 Offset 79h Definitions Sheet 1 of 2 Bits Definition 7 4 Reserved Dual Core Intel Xeon Processor 7000 Series Datasheet 93 Features i ntel iB Table 7 19 Offset 79h Definitions Sheet 2 of 2 Bits Definition 3 2 Number of cores 1 0 Number of threads per core Example The Dual Core Intel Xeon processor 7000 series has two cores and two threads per core Therefore this register will have a value of OAh 7 4 9 7 4 Additional Processor Feature Flags Offset 7Ah provides additional feature information for the processor This field is defined as follows Table 7 20 Offset 7A
103. ll processor FSB agents DP 3 0 DRDY UO y o DP 3 0 Data Parity provide optional parity protection for the data bus They are driven by the agent responsible for driving D 63 0 and if parity is implemented must connect the appropriate pins of all bus agents which use them DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor FSB agents DSTBN 3 0 UO Data strobe used to latch in D 63 0 and DBI 3 0 DSTBP 3 0 y o Data strobe used to latch in D 63 0 and DBI 3 0 FERR PBE FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional inform
104. lts Example The CPUID of a C 1 stepping Intel Xeon processor with 512 KB L2 cache is 0F27h The value programmed into offset 16 17h of the PIROM is 3C9Ch The first two bits of the PIROM are reserved as highlighted in the example below CPUID instruction results 0000 1111 0010 0111 0F27h PIROM content 0011 1100 1001 1100 3COCh Dual Core Intel Xeon Processor 7000 Series Datasheet Intel 7 4 9 3 2 7 4 9 3 3 7 4 9 3 4 7 4 9 3 5 Note 7 4 9 3 6 Features Front Side Bus Frequency Offset 1A 1Bh provides FSB frequency information Systems may need to read this offset to decide if all installed processors support the same FSB speed Because the Intel NetBurst microarchitecture bus is described as a 4x data bus the frequency given in this field is currently 667 MHz The data provided is the speed rounded to a whole number and reflected in hex Example The Dual Core Intel Xeon processor 7000 series supports a 667 MHz FSB Therefore offset 1A IBh has a value of 029Bh Multi Processor Support Offset 1Ch has 2 bits defined for representing the supported number of physical processors on the bus These two bits are MSB aligned where 00b equates to single processor operation 01b is a dual processor operation and 11b represents multi processor operation Normally only values of 01 and 11b are used The remaining six bits in this field are reserved for the future use Maximum Core Frequency Offset 1D 1E
105. meters are not tested and are based on design simulations 2 Leakage to Vgg with pin held at 2 5 V 3 Represents the maximum allowable termination voltage Table 2 13 VIDPWRGD DC Specifications Symbol Parameter Min Max Unit Figure Notes Vu Input Low Voltage 0 0 0 30 V Vu Input High Voltage 0 90 Vr V Table 2 14 AGTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes ViL Input Low Voltage 0 0 GTLREF 0 10 V 1 3 Vr ViH Input High Voltage GTLREF Vr V 2 3 0 10 V Von Output High Voltage 0 90 Ver Ver V 3 loL Output Low Current N A Vrr mA 5 0 50 Rtt_min RoN min RI Iu Input Leakage Current N A 200 HA 4 6 ILO Output Leakage Current N A 200 HA 4 6 RON Buffer On Resistance 4 8 Q NOTES Q Q N specified into the test load 6 Leakage to Vrr with pin held at 300 mV Table 2 15 PWRGOOD Input and TAP Signal Group DC Specifications Sheet 1 of 2 Mi is defined as the voltage range at a receiving agent that will be interpreted as a logical low value Viu is defined as the voltage range at a receiving agent that will be interpreted as a logical high value The V71 represented in these specifications refers to instantaneous VT Leakage to Vgg with pin held at Vr The maximum output current is based on maximum current handling capability of the buffer and is not Symbol Parameter Min Max Unit Notes Vuvs Input Hysteresis 200 350 mV 5 Vu Input Low to Hig
106. mputer system with a processor chipset BIOS operating system device drivers and applications enabled for Inte 64 architecture Processors will not operate including 32 bit operation without an Intel 64 architecture enabled BIOS Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order l2C is a two wire communications bus protocol developed by Philips SMBus is a subset of the 12C bus protocol and was developed by Intel Implementations of the I2C bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation Intel Intel Xeon Intel NetBurst and Intel SpeedStep are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2005 2006 Intel Corporation 2 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Contents Dual Core Intel Xeon Processor 7000 Series Datasheet ug tele Lee 11 1 1 Terminology rrr ie ME 12 1 2 Reference DOCUMENTS essiensa nnii t aa a tenen a Reese a 14 1 3 State of Data umu uu x 14 Electrical Specifications UU nenea anemia akla aaa ana 15 2 1 Fr
107. n advanced operating systems such as Microsoft Windows 2003 server and Linux operating systems The Intel Xeon processor 7000 series delivers compute power at unparalleled value and flexibility for internet infrastructure and departmental server applications including application servers databases and business intelligence The Inter NetBurst microarchitecture with Hyper Threading Technology and Intel 64 architecture delivers outstanding performance and headroom from peak internet server workloads resulting in faster response times support for more users and improved scalability Dual Core Intel Xeon Processor 7000 Series Datasheet 9 10 Dual Core Intel Xeon Processor 7000 Series Datasheet Introduction The Dual Core Intel Xeon processor 7000 series is Intel s first dual core product for multi processor servers utilizing two physical Intel NetBurst microarchitecture cores in one package It maintains the tradition of compatibility with IA 32 software and includes features found in the Intel Xeon processor such as hyper pipelined technology a Rapid Execution Engine and an Execution Trace Cache Hyper pipelined technology includes a multi stage pipeline allowing the processor to reach much higher core frequencies The processor features a choice of two system bus speeds The 667 MHz front side bus FSB is a quad pumped bus running off a 166 MHz system clock making 5 3 GB per second data transfer rates possible The Executi
108. nned Thermal Monitor must be enabled for the processor to remain within specification Dual Core Intel Xeon Processor 7000 Series Thermal Specifications Core Maximum Thermal Minimum Maximum Frequency Power Design Power TCASE TCASE Notes GHz W W C C 2 66 GHz FMB 173 165 5 See Figure 6 1 Table 6 2 1 2 3 4 NOTES 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and Icc combination wherein Vcc exceeds Voc max at specified Icc Please refer to the Voc static and transient tolerance specifications in Section 2 H 2 Maximum Power is the maximum thermal power that can be dissipated by the processor through the integrated heat spreader IHS Maximum Power is measured at maximum Tcase 3 Thermal Design Power TDP should be used for processor chipset thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum TcAsE 4 These specifications are based on final silicon characterization Dual Core Intel Xeon Processor 7000 Series Datasheet n Thermal Specifications Figure 6 1 Dual Core Intel Xeon Processor 7000 Series Thermal Profile A Thermal Profile 80 75 70 Thermal Profile Teasemax 0 184 x Power 45 Temperature C 8 I Ge 55 50 45 80 100 120 140 160 180 Power W NO
109. nput Output B23 Vsg Power Other B24 LINTO INTR Async GTL Input B25 PROCHOT Async GTL Output B26 Don tCare B27 VccsENsE Power Other Output B28 Vss Power Other B29 Don t Care B30 Don t Care B31 Don t Care C1 Reserved C2 Don t Care C3 VID3 Power Other Output C4 Voc Power Other C5 Vr Power Other C6 RSP Common Clk Input C7 Vss Power Other C8 A35 Source Sync Input Output C9 A34 Source Sync Input Output C10 Vrt Power Other C11 A30 Source Sync Input Output C12 A234 Source Sync Input Output C13 Vss Power Other C14 A164 Source Sync Input Output C15 A15 Source Sync Input Output C16 A39 Source Sync Input Output intel Table 4 2 Pin Listing by Pin Number Cont d Pin Listing Table 4 2 Pin Listing by Pin Number Cont d Signal Buffer Signal Buffer Pin No Pin Name Type Direction Pin No Pin Name Type Direction C17 A8 Source Sync Input Output D27 Don tCare C18 A6 Source Sync Input Output D28 Vss Power Other C19 Vss Power Other D29 Don t Care C20 REQ3 Common Clk Input Output D30 Vss Power Other C21 REQ24 Common Clk Input Output D31 Mee Power Other C22 Voc Power Other E1 VTTEN Power Other Output C23 DEFER Common CIk Input E2 Don t Care C24 TDI TAP Input E3 VID1 Power Other J Output C25 Vss Power Other Input E4
110. nput Output D33 AA16 Source Sync Input Output BR3 D10 Common Clk Input Output D34 AC17 Source Sync Input Output BSELO AA3 Power Other Output D35 AE13 Source Sync Input Output BSEL1 AB3 Power Other Output D36 AD18 Source Sync Input Output COMPO AD16 Power Other Input D37 AB15 Source Sync Input Output DO Y26 Source Sync Input Output D38 AD13 Source Sync Input Output D1 AA27 Source Sync Input Output D39 AD14 Source Sync Input Output D2 Y24 Source Sync Input Output D40 AD11 Source Sync Input Output D3 AA25 Source Sync Input Output D41 AC12 Source Sync Input Output D4 AD27 Source Sync Input Output D42 AE10 Source Sync Input Output D5 Y23 Source Sync Input Output D43 AC11 Source Sync Input Output D6 AA24 Source Sync Input Output D44 AE9 Source Sync Input Output D7 AB26 Source Sync Input Output D45 AD10 Source Sync Input Output D8 AB25 Source Sync Input Output D46 AD8 Source Sync Input Output D9 AB23 Source Sync Input Output D47 AC9 Source Sync Input Output D10 AA22 Source Sync Input Output D48 AA13 Source Sync Input Output D11 AA21 Source Sync Input Output D49 AA14 Source Sync Input Output D12 AB20 Source Sync Input Output D50 AC14 Source Sync Input Output D13 AB22 Source Sync Input Output D51 AB12 Source Sync Input Output D14 AB19 Source Sync Input Output D52 AB13 Source Sync Input Output D
111. ns that prevent baseboard deflection or for the Intel enabled reference solution CEK 6 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 7 Experimentally validated test condition used a heatsink mass of 1 Ibm 0 45 kg with 100 G acceleration measured at heatsink mass The dynamic portion of this specification in the product application can have flexibility in specific values but the ultimate product of mass times acceleration should not exceed this validated dynamic load 1 Ibm x 100 G 100 Ib 8 Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement representative of loads experienced by the package during heatsink installation 36 Dual Core Intel Xeon Processor 7000 Series Datasheet intel 3 4 Table 3 2 3 5 3 6 3 7 Table 3 3 Mechanical Specifications Package Handling Guidelines Table 3 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N 80 Ibf 1 2 Tensile 156 N 35 Ibf 3 2 Torque 8 N m 70 Ibf in 4 2 NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 These guidel
112. nt byte This result is then negated to provide the checksum Example For a byte string of AA445Ch the resulting checksum will be Boh AA 10101010 44 01000100 5C 0101100 AA 44 SC 01001010 Negate the sum 10110101 1 101101 B6h Dual Core Intel Xeon Processor 7000 Series Datasheet 95 Features 96 Dual Core Intel Xeon Processor 7000 Series Datasheet 8 1 Boxed Processor Specifications Introduction The Dual Core Intel Xeon processor 7000 series will be offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from components available through distribution channels The boxed thermal solution is under development and is subject to change This section is meant to provide some insight into the current direction of the thermal solution Future revisions may have solutions that differ from those discussed here The current thermal solution plan for the boxed Dual Core Intel Xeon processor 7000 series is to include an unattached passive heatsink This solution is currently targeted at chassis which are 3U and above in height This section documents baseboard and platform requirements for the thermal solution supplied with the boxed Dual Core Intel Xeon processor 7000 series This section is particularly important to companies that design and manufacture baseboards chassis and complete systems Figure 8 1 shows the conceptual drawing of the boxed processor thermal
113. ntation does not add excessive capacitance to the address inputs Excess capacitance at the address inputs may cause address recognition problems Refer to the appropriate platform design guide document Figure 7 2 shows a logical diagram of the pin connections Table 7 16 and Table 7 17 describe the address pin connections and how they affect the addressing of the devices Table 7 16 Thermal Sensor SMBus Addressing Note Device Select SES IM 2 Address Hex SM TS A1 SM TS A0 b 7 0 0 0 3Xh 0011000Xb 0 Z2 0011001Xb 0 1 0011010Xb Z2 0 5Xh 0101001Xb Z2 Z2 0101010Xb Z2 1 0101011Xb 1 0 9Xh 1001100Xb 1 Z2 1001101Xb 1 1 1001110Xb NOTES 1 Upper address bits are decoded in conjunction with the device select pins 2 A tri state or Z state on this pin is achieved by leaving this pin unconnected System management software must be aware of the processor dependent addresses for the thermal sensor Dual Core Intel Xeon Processor 7000 Series Datasheet n Ntel Features 8 Table 7 17 Memory Device SMBus Addressing Upper Device Select R W Address Address Hex SM_EP_A2 SM_EP_A1 SM_EP_A0 bits 74 bit 3 bit 2 bit 1 bit 0 AOh A1h 1010 0 0 0 X A2h A3h 1010 0 0 1 X A4h A5h 1010 0 1 0 x A6h A7h 1010 0 1 1 x A8h A9h 1010 1 0 0 x AAh ABh 1010 1 0 1 X ACh ADh 1010 1 1 0 x AEh AFh 1010 1 1 1 x NOTE 1 This addressing scheme will support
114. of PROCHOT processor hot indicates that the processor die temperature has reached its thermal limit See Section 6 2 3 for more details PROCTYPE PROCTYPE is used to identify when the Dual Core Intel Xeon processor 7000 series is installed This pin should be used to toggle logic needed for the Dual Core Intel Xeon processor 7000 series 64 bit Intel Xeon Processor MP with up to 8MB L3 Cache or 64 bit Intel Xeon Processor MP with 1MB L2 Cache The pin is left floating on the Dual Core Intel Xeon Processor 7000 Series package while on the 64 bit Intel Xeon9 Processor MP with up to 8MB L3 Cache packages this pin connects to Vss PWRGOOD PWRGOOD Power Good is an input The processor requires this signal to be a clean indication that all Dual Core Intel Xeon processor 7000 series clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state The PWRGOOD signal must be supplied to the processor This signal is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 I O REQ 4 0 Request Command must connect the appropriate pins of all processor FSB agents They are asserted by t
115. of physical m Intel NetBurst microarchitecture e ne W 144 Streaming SIMD Extensions 2 SSE2 m Hyper Threading Technology instrnettans W Hardware support for multithreaded applications m 13 Streaming SIMD Extensions 3 SSE3 W Fast 667 MHz system bus instructions W Rapid Execution Engine Arithmetic Logic Units W Enhanced floating point and multimedia unit for ALUs run at twice the processor core frequency enhanced video audio encryption and 3D performance Hyper Pipelined Technology j System Management mode Advanced Dynamic Execution Thermal monitor Machine Check Architecture MCA Demand Based Switching DBS with Enhanced Execute Disable Bit Intel SpeedStep Technology Includes 16 KB Level 1data cache Very deep out of order execution Enhanced branch prediction The Dual Core Intel Xeon processor 7000 series is designed for high performance multi processor server applications for mid tier enterprise serving and server consolidation Based on the Intel NetBurst microarchitecture and the new Hyper Threading Technology it is binary compatible with pervious Intel Architecture LA 32 processors The addition of Intel 64 architecture provides 64 bit computing and 40 bit addressing provides up to 1 Terabyte of direct memory addressability The Dual Core Intel Xeon processor 7000 series is scalable to four processors and beyond in a multiprocessor system providing exceptional performance for applications running o
116. oftware Developer s Manual 253665 Volume 1 Basic Architecture 253666 Volume 24A Instruction Set Reference A M 253667 Volume 2B Instruction Set Reference N Z 253668 Volume 3 System Programming Guide IA 32 Intel Architecture and Intel Extended Memory 64 Software 252046 Developer s Manual Documentation Changes mPGA604 Socket Design Guidelines 254239 MPS Power Supply A Server System Infrastructure SSI Specification Note 3 For Midrange Chassis Power Supplies Dual Core Intel Xeon Processor 7000 Sequence Core Boundary Scan Note 2 Descriptive Language BSDL Model 64 bit Intel Xeon Processor MP with up to 8MB L3 Cache Cooling Note 2 Solution Mechanical Models 64 bit Inte amp Xeon Processor MP with up to 8MB L3 Cache Thermal Note 2 Test Vehicle and Cooling Solution Thermal Modelss 64 bit Intel Xeon Processor MP with up to 8MB L3 Cache Mechanical Note 2 Models Dual Core Intel Xeon Processor 7000 Sequence Specification Update 309627 Dual Core Intel Xeon Processor 7000 Sequence Thermal Mechanical 309625 Design Guidelines Vcc Voltage Regulator Module VRM and Enterprise Voltage Regulator Note 2 Down EVRD 10 2 Design Guidelines ITP700 Debug Port Design Guide 249679 Prescott Nocona and Potomac Processor BIOS Writer s Guide BWG Note 1 NOTES 1 Contact your Intel representative for the latest revision of documents 2 This collateral is available publicly at http developer intel com 3 This document is available at ht
117. ommand byte Write Byte SMBus Packet S Slave Address Write Ack Command Code Ack Data Ack P 1 7 bits 0 1 8 bits 1 8 bits 1 1 Dual Core Intel Xeon Processor 7000 Series Datasheet 81 Features N Table 7 6 Read Byte SMBus Packet Slave Command Slave S J Address Write Ack Code Ack S Address Read Ack Data P 1 7 bits 0 1 8 bits 1 1 7 bits 1 1 8 bits 1 1 Table 7 7 Send Byte SMBus Packet S Slave Address Write Ack Command Code Ack P 1 7 bits 0 1 8 bits 1 1 Table 7 8 Receive Byte SMBus Packet S Slave Address Read Ack Data II P 1 T bits 1 1 8 bits 1 1 Table 7 9 ARA SMBus Packet S ARA Read Ack Address Ill P 1 0001 100 1 1 Device Address 1 1 NOTES 1 This is an 8 bit field The device which sent the alert will respond to the ARA Packet with its address in the seven most significant bits The least significant bit is undefined and may return as a 1 or 0 See Section 7 4 8 for details on the Thermal Sensor Device addressing 2 The shaded bits are transmitted by the thermal sensor and the bits that aren t shaded are transmitted by the SMBus host controller 82 Dual Core Intel Xeon Processor 7000 Series Datasheet n B Features Table 7 10 SMBus Thermal Sensor Command Byte Assignments
118. on Trace Cache is a level 1 L1 cache that stores decoded micro operations which removes the decoder from the main execution path thereby increasing performance In addition the Dual Core Intel Xeon processor 7000 series includes Intel 64 architecture providing additional addressing capability Enhanced thermal and power management capabilities are implemented including Thermal Monitor and Enhanced Intel SpeedStep Technology Thermal Monitor provides efficient and effective cooling in high temperature situations Enhanced Intel SpeedStep Technology allows trade offs to be made between performance and power consumption This may lower average power consumption in conjunction with OS support The Dual Core Intel Xeon processor 7000 series supports Hyper Threading Technology HT Technology This feature allows a single physical processor to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers control registers to provide increased system responsiveness in multitasking environments and headroom for next generation multi threaded applications More information on HT Technology can be found at http www intel com technology hyperthread Support for Intel s Execute Disable Bit functionality has been added which can prevent certain classes of malicious buffer overflow atta
119. onment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the Dual Core Intel Xeon Processor 7000 Sequence Thermal Mechanical Design Guidelines The boxed processor will ship with a component thermal solution Refer to Section 8 for details on the boxed processor Thermal Specifications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature TcAsg specifications as defined by the applicable thermal profile see Table 6 1 and Figure 6 1 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the appropriate processor thermal mechanical design guideline The Dual Core Intel Xeon processor 7000 series introduces a new methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and assure processor reliability Selection of the appropriate fan speed will be base
120. ons for the BCLK 1 0 inputs are provided in Table 2 11 The Dual Core Intel Xeon processor 7000 series utilizes differential clocks Details regarding BCLK 1 0 driver specifications are provided in the CK409 Clock Synthesizer Driver Design Guidelines or CK409B Clock Synthesizer Driver Design Guidelines Table 2 1 contains core frequency to FSB multipliers and their corresponding core frequencies Core Frequency to Front Side Bus Multiplier Configuration Core Frequency to Core Frequency with 166 MHz Notes Front Side Bus Multiplier Front Side Bus Clock 1114 RESERVED 1 2 3 1 15 RESERVED 2 3 1 16 2 66 GHz 2 3 1117 RESERVED 2 3 1 18 3 GHz 2 3 NOTES 1 Individual processors operate only at or below the frequency marked on the package 2 Listed frequencies are not necessarily committed production frequencies 3 For valid core frequencies of the processor refer to the Dual Core Intel Xeon Processor 7000 Sequence Specification Update Front Side Bus Clock Select BSEL 1 0 The BSEL 1 0 signals are hardwired outputs used to select the frequency of the processor input clock BCLK 1 0 Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All processors must operate at the same FSB frequency The Dual Core Intel Xeon processor 7000 series operates at 667 MHz FSB
121. ont Side Bus and GTLREP L atu ar a n p a i a au 15 2 1 1 Front Side Bus Clock and Processor Clocking 15 2 1 2 Front Side Bus Clock Select BSEL 1 o 16 2 1 3 Phase Lock Loop PLL Power and Elter 17 2 2 Voltage Identification VID nenea nnn 17 2 3 Reserved Unused and TESTHI Pins 20 24 Mixing Processors c nmxx qmrggmmoomxx 20 2 5 Front Side Bus Signal Groups 21 2 6 GTL Asynchronous Signals and AGTL Asynchronous Signals 22 2 7 Test Access Port TAP Connection 23 2 8 Absolute Maximum and Minimum Ratings eee 23 2 9 Processor DC Specifications enne 24 2 9 1 Flexible Motherboard FMB Guidelines 24 2 9 2 Vcc Overshoot Specification sse 28 Mechanical Specifications ta aa aaa Pa o Dita ta ii 33 3 1 Package Mechanical Drawing nenea enma enm a kwa dada kak 33 3 2 Processor Component Keepout Zones ceea nana na 36 3 3 Package Loading Specifications mmm nenea nn kk kk kk kk RA 36 3 4 Package Handling Guidelines nenea nenea nenea nn 37 3 5 Package Insertion Specifications nea Ek kk kk kk 37 3 6 Processor Mass Specifications nn ana aaa ana na 37 3 7 ProcessorMalerial S_ cat ct aaa a la aa ab i 37 3 8 Processor Markings u L cea a a a
122. or disables Rp Those signals affected by ODTEN still present RpyT termination to the signal s pin when the processor is placed in tri state mode Furthermore the following signals are not affected when the processor is placed in tri state mode BSEL 1 0 SKTOCC SM ALERT SM CLK SM DAT SM EP A 2 0 SM TS A I1 0 SM WP TEST BUS TESTHI 6 0 VID 5 0 TDO and VTTEN Signal Reference Voltages GTLREF Vir 2 A20M A 39 3 ADS ADSTB 1 0 AP 1 0 BOOT SELECT PWRGOOD1 TCK TDI TMS1 BINIT BNR BPM 5 0 BPRI BR 3 0 TRST 1 VIDPWRGD D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM IGNNE INIT LINTO INTR LINT1 NMI LOCK MCERR ODTEN REQ 4 0 RESET RS 2 0 RSP SMI STPCLK TRDY NOTES 1 These signals also have hysteresis added to the reference voltage See Table 2 15 for more information GTL Asynchronous Signals and AGTL Asynchronous Signals The Dual Core Intel Xeon processor 7000 series does not utilize CMOS voltage levels on any signals that connect to the processor silicon As a result input signals such as A20M FORCEPR IGNNE INIT LINTO INTR LINTI NMI SMI SLP and STPCLK utilize GTL input buffers Legacy output THERMTRIP utilizes a GTL output buffers All of these Asynchronous GTL signals follow the same DC requirements as GTL signals however the outputs are not driven high during the logical 0
123. ot present 06h 8 Package Data Address Byte pointer OOh if not present 07h 8 Part Number Data Address Byte pointer OOh if not present 08h 8 Thermal Reference Data Byte pointer OOh if not present Address 09h 8 Feature Data Address Byte pointer OOh if not present OAh 8 Other Data Address Byte pointer 00h if not present OBh 16 Reserved Reserved 0Dh 8 Checksum 1 byte checksum Processor Data OE 13h 48 S spec QDF Number Six 8 bit ASCII characters 14h 6 Reserved Reserved most significant bits 2 Sample Production 00b Sample only 01 11b Production 15h 8 Checksum 1 byte checksum Processor Core Data 16 17h 2 Processor Core Type From CPUID 4 Processor Core Family From CPUID 4 Processor Core Model From CPUID 4 Processor Core Stepping From CPUID 2 Reserved Reserved for future use 18 19h 16 Reserved Reserved for future use 1A 1Bh 16 Front Side Bus Speed 16 bit hexadecimal number in MHz 1Ch 2 Multiprocessor Support 00b UP 01b DP 10b RSVD 11b MP 6 Reserved Reserved 1D 1Eh 16 Maximum Core Frequency 16 bit hexadecimal number in MHz 1F 20h 16 Max Processor Core VID Max Vcc requested by VID outputs in mV 21 22h 16 Core Voltage Minimum Minimum processor DC Vcc spec in mV 23h 8 TcAse Maximum Maximum case temperature spec in C 24h 8 Checksum 1 byte checksum Dual Core Intel Xeon Processor 7000 Series Datasheet Table 7 2 Processor Information ROM Format Sheet 2 of 3 Features of
124. ower Other Input H28 Vss Power Other F24 TRST TAP Input H29 Nee Power Other F25 Vss Power Other H30 Vss Power Other F26 THERMTRIP Async GTL Output H31 Nee Power Other F27 A20M4 Async GTL Input J1 Vss Power Other F28 Vss Power Other J2 Vcc Power Other F29 Mee Power Other J3 Vss Power Other F30 Vss Power Other J4 Voc Power Other F31 Mee Power Other J5 Vss Power Other G1 Vss Power Other J6 Mee Power Other G2 Voc Power Other J7 Vss Power Other G3 Vss Power Other J8 Voc Power Other G4 Voc Power Other J9 Vss Power Other G5 Nee Power Other J23 Vss Power Other G6 Voc Power Other J24 Mee Power Other G7 BOOT SELECT Power Other Input J25 Vss Power Other G8 Voc Power Other J26 Mee Power Other G9 Vss Power Other J27 Mes Power Other G23 LINT1 NMI Async GTL Input J28 Vcoc Power Other G24 Voc Power Other J29 Vss Power Other G25 Vss Power Other J30 Voc Power Other G26 Vcc Power Other J31 Vss Power Other G27 Vss Power Other K1 Don t Care G28 Voc Power Other K2 Vss Power Other 52 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Table 4 2 Pin Listing by Pin Number Cont d Pin Listing Table 4 2 Pin Listing by Pin Number Cont d Pin No Pin Name b e Direction Pin No Pin Name T Direction K3 Don t Care M8 Vss Power Oth
125. per processor operation See Section 2 3 for more details THERMTRIP The processor protects itself from catastrophic overheating by use of an internal thermal sensor To ensure that there are no false trips THERMTRIP Thermal Trip will activate at a temperature that is about 20 C above the maximum case temperature Tc Once activated the processor will stop all execution and the signal remains latched until RESET goes active There is no hysteresis built into the thermal sensor itself as long as the die temperature drops below the trip level a RESET pulse will reset the processor and execution will continue If the temperature has not dropped below the trip level the processor will continue to drive THERMTRIP and remain stopped TMS TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY TRDY Target Ready is asserted by the target chipset to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all FSB agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven electrically low during power on Reset Please refer to the eXtended Debug Port Debug Port Design Guide for Twin Castle Chipset Platforms or the eXtended Debug Port Debug Port Design Guide for MP Platforms for details 64 Voc provides power to the core logic of the Dual Core Intel Xeon processor
126. r A12 A14 Source Sync Input Output A13 A104 Source Sync Input Output A14 Nee Power Other A15 FORCEPR Async GTL Input A16 TEST BUS Power Other Input A17 LOCK Common Clk Input Output A18 Nee Power Other A19 A7 Source Sync Input Output A20 A4 Source Sync Input Output A21 Vss Power Other A22 A3 Source Sync Input Output A23 HITM Common Clk Input Output A24 Nee Power Other A25 TMS TAP Input A26 Don t Care A27 Vss Power Other A28 Don t Care A29 Vss Power Other A30 Don t Care A31 Don t Care B1 VIDPWRGD Power Other Input B2 Vss Power Other B3 VIDA Power Other J Output B4 Don t Care B5 ODTEN Power Other Input B6 A38 Source Sync Input Output B7 A31 Source Sync Input Output B8 A27 Source Sync Input Output 50 In Table 4 2 Pin Listing by Pin Number Cont d Dual Core Intel Xeon Processor 7000 Series Datasheet Pin No Pin Name p Direction B9 Vss Power Other B10 A21 Source Sync Input Output B11 A22 Source Sync Input Output B12 Mr Power Other B13 A13 Source Sync Input Output B14 A124 Source Sync Input Output B15 Vss Power Other B16 A11 Source Sync Input Output B17 Vss Power Other B18 A5 Source Sync Input Output B19 REQO Common Clk Input Output B20 Vcc Power Other B21 REQ14 Common Clk Input Output B22 REQ4 Common Clk I
127. r BSEL 1 0 and VID 5 0 is stable and within specification Vss l Vss is the ground plane for the Dual Core Intel Xeon processor 7000 series VssA l Vssa provides an isolated internal ground for internal PLL s Do not connect directly to ground This pin is to be connected to Veca and Vccjop through a discrete filter circuit VIT Vrr is the FSB termination voltage VTTEN O VTTEN can be used as an output enable for the Vr regulator VTTEN is used as an electrical key to prevent processors with mechanically equivalent pinouts from accidentally booting in a Dual Core Intel Xeon processor 7000 series platform Since VTTEN is an open circuit on the processor package VTTEN must be pulled up on the motherboard Refer to the appropriate platform design guide for implementation details Dual Core Intel Xeon Processor 7000 Series Datasheet 65 Signal Definitions 66 Dual Core Intel Xeon Processor 7000 Series Datasheet 6 1 6 1 1 Note Thermal Specifications Package Thermal Specifications The Dual Core Intel Xeon processor 7000 series requires a thermal solution to maintain temperatures within operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal envir
128. r temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the ITA32 CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 596 off to 87 5 on 12 5 off in 12 596 increments On Demand mode may be used in conjunction with the Thermal Monitor If the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its factory configured trip point If the Thermal Monitor is enabled note that the Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT Refer to the IA 32 Intel Architecture Software Developer s Manual and the Prescott Nocona and Potomac Processor BIOS Writer s Guide BWG for specific register and programming details PROCHOT is designed to assert at or a few degrees higher than maximum Tagg as specified by the thermal profile when dissipating TDP power and cannot be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and
129. rate value and address OAh for writing the value Table 7 15 shows the mapping between Conversion Rate Register values and the conversion rate As indicated in Table 7 10 the Conversion Rate Register is set to its default state of 1000b 16 Hz nominally when the thermal sensor is powered up There is a 30 error tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate Table 7 15 SMBus Thermal Sensor Conversion Rate Register Sheet 1 of 2 86 Bit Name Reset State Function 7 MSB Averaging 0 Setting this bit to 1 disables averaging of the temperature measurements at the slower conversion rates Default 0 Averaging enabled 6 RESERVED RESERVED Reserved for future use Dual Core Intel Xeon Processor 7000 Series Datasheet n B Features Table 7 15 SMBus Thermal Sensor Conversion Rate Register Sheet 2 of 2 Bit Name Reset State Function 5 4 Channel Selector 00 These bits are used to select the temperature measurement channels 00 Round robin 01 Local Temperature 10 Remote 1 Temperature 11 Remote 2 Temperature Default 00 Always set these bits to 00 3 0 Conversion Rates 1000 These bits determine how often the temperature sensor measures each temperature channel Bit encoding Conversions sec 0000 0 0625 0001 0 125 0010 0 25 0011 0 5 0100 1 0101 2 011024 011128 1000 16 default 1
130. re V cc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos MAX Vos max is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCCSENSE and VSSSENSE pins Table 2 10 Vcc Overshoot Specifications 28 Symbol Parameter Min Max Units Figure Notes Vos MAX Magnitude of Vec 0 050 V 2 5 overshoot above VID Tos MAX Time duration of Voc 25 us 2 5 E overshoot above VID Dual Core Intel Xeon Processor 7000 Series Datasheet Electrical Specifications Figure 2 5 Vcc Overshoot Example Waveform Example Overshoot Waveform VID 0 050 Vos o o gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID NOTES 1 Vos is measured overshoot voltage 2 Tos is measured time duration above VID Table 2 11 Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes VL Input Low Voltage 0 150 0 000 N A V VH Input High Voltage 0 660 0 700 0 850 V VcROSS abs Absolute Crossing 0 250 N A 0 550 V 1 2 Point VcROSS re Relative Crossing 0 250 0 5 N A 0 550 0 5 V 3 2 4 Point Viavg 0 700 VHavg 0 700 A VCROSS Range of Crossing N A N A 0 140 V Point Vov Overshoot N A N A Vu 0 3
131. recommended when FORCEPR is asserted by the system Sustained activation of the FORCEPR pin may cause noticeable platform performance degradation Refer to the appropriate platform design guide for details on implementing the FORCEPR signal feature THERMTRIP Signal Pin Regardless of whether or not Thermal Monitor is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 5 1 At this point the system bus signal THERMTRIP will go active and stay active as described in Table 5 1 THERMTRIP activation is independent of processor activity and does not generate any bus cycles Intel also recommends removal of Vyr Tcontrol and Fan Speed Reduction Tcontrol is a temperature specification based on a temperature reading from the thermal diode The value for Tcontrol will be calibrated in manufacturing and configured for each processor The Tcontrol temperature for a given processor can be obtained by reading the IA32 TEMPERATURE TARGET MSR in the processor The Tcontrol value that is read from the IA32 TEMPERATURE TARGET MSR must be converted from Hexadecimal to Decimal and added to a base value of 50 C The value of Tcontrol may vary from 0x00h to Ox 1Eh Refer to the Prescott Nocona and Potomac Processor BIOS Writer s Guide BWG for specific register details When Tdiode is above Tcontrol then T
132. rmal Sensor Configuration Register 85 SMBus Thermal Sensor Conversion Rate Register 86 Thermal Sensor SMBus Addressing sse 88 Memory Device SMBus Addressing 89 Offset 78h Definitions seen enne trennt nennen 93 Offset 79h Definitions mn nenea amana ana ana aaa 93 Offset 7Ah Definitions cea ca ae eee ata da d a a a 94 Offset Bh Definitiohs s ac ct cote ca eg ba a d um ce n a 94 128 Byte ROM Checksum Values mmm nenea kk ana aaa nana na 95 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Revision History Series Updated Section 1 2 Reference Documents Document Revision Number Number Description Date 309626 001 Initial release of this document November 2005 309626 002 Changed product name to Dual Core Intel Xeon Processor 7000 September 2006 Dual Core Intel Xeon Processor 7000 Series Datasheet Dual Core Intel Xeon Processor 7000 Series Datasheet intel Features E Available at 2 66 or 3 0 GHz E Intel 64 architecture E 90 nm process technology W Up to2 MB Advanced Transfer Cache On die full m Bi ible with application runni speed Level 2 L2 Cache with 8 way associativity inary compatible with application running on and Error Correcting Code ECC previous members of Intel s IA 32 microprocessor line E Enables system support of up to 64 GB
133. roup of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to strobes and DBI Furthermore the DBI pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 I O DBI 3 0 are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electronically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBIO DBI1 DBI2 DBI3 D 15 0 D 31 16 D 47 32 D 63 48 DBSY DEFER y o DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor FSB agents DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or UO agent This signal must connect the appropriate pins of a
134. rvation AQ 1 2 Disable BINIT observation A10 1 2 Disable bus parking A15 1 2 APIC Cluster ID A 12 11 4 1 2 Symmetric agent arbitration ID BR 3 0 1 2 Disable Hyper Threading Technology A31 1 2 3 NOTES 1 Asserting this signal during RESET will select the corresponding option 2 Address pins not identified in this table as configuration options should not be asserted during RESET 3 This mode is not tested 7 2 Clock Control and Low Power States The processor allows the use of HALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state The Dual Core Intel Xeon processor 7000 series also adds support for the Enhanced HALT state For more configuration details also refer to the Prescott Nocona and Potomac Processor BIOS Writer s Guide See Figure 7 1 for a visual representation of the processor low power states 7 2 1 Normal State This is the normal operating state for the processor Dual Core Intel Xeon Processor 7000 Series Datasheet 73 Features 7 2 2 Intel HALT Power Down State HALT is a low power state entered when the processor executes the HALT instruction The processor transitions to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the FSB RESET causes the processor to immediately initialize itself The return from a System Management
135. s V7 Power Other Vss AD9 Power Other Vss v9 Power Other Vss AD15 Power Other 48 Dual Core Intel Xeon Processor 7000 Series Datasheet intel Pin Listing Table 4 1 Pin Listing by Pin Name Cont d Table 4 1 Pin Listing by Pin Name Cont d Pin Name Pin No ns Direction Pin Name Pin No o Ae Direction Vss AD17 Power Other Vr C5 Power Other Vss AD23 Power Other Vr C10 Power Other Vss AE6 Power Other VIT E12 Power Other Vss AE11 Power Other Vr F10 Power Other Vss AE21 Power Other Vr Y10 Power Other Vss AE27 Power Other Vr AA12 Power Other VssA AA5 Power Other Input Vr AC10 Power Other VsssENSE D26 Power Other Output Vr AD12 Power Other VIT A4 Power Other VIT AE4 Power Other Vr B12 Power Other VTTEN E1 Power Other Output Dual Core Intel Xeon Processor 7000 Series Datasheet 49 Pin Listing 4 1 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Signal Buffer Pin No Pin Name Type Direction A1 VID5 Power Other J Output A2 Don t Care A3 SKTOCC Power Other J Output A4 Vr Power Other A5 Vss Power Other A6 A32 Source Sync Input Output A7 A33 Source Sync Input Output A8 Vcc Power Other A9 A26 Source Sync Input Output A10 A20 Source Sync Input Output A11 Vgg Power Othe
136. s and specifications will be included in future revisions of this document Dual Core Intel Xeon Processor 7000 Series Datasheet n Table 2 3 Voltage Identification VID Definition Electrical Specifications VID5 VIDA VID3 VID2 VID1 VIDO VID V VID5 VIDA VID3 VID2 VID1 VIDO VID V 0 0 1 0 1 0 0 8375 0 1 1 0 1 0 1 2125 1 0 1 0 0 1 0 8500 1 1 1 0 0 1 1 2250 0 0 1 0 0 1 0 8625 0 1 1 0 0 1 1 2375 1 0 1 0 0 0 0 8750 1 1 1 0 0 0 1 2500 0 0 1 0 0 0 0 8875 0 1 1 0 0 0 1 2625 1 0 0 1 1 1 0 9000 1 1 0 1 1 1 1 2750 0 0 0 1 1 1 0 9125 0 1 0 1 1 1 1 2875 1 0 0 1 1 0 0 9250 1 1 0 1 1 0 1 3000 0 0 0 1 1 0 0 9375 0 1 0 1 1 0 1 3125 1 0 0 1 0 1 0 9500 1 1 0 1 0 1 1 3250 0 0 0 1 0 1 0 9625 0 1 0 1 0 1 1 3375 1 0 0 1 0 0 0 9750 1 1 0 1 0 0 1 3500 0 0 0 1 0 0 0 9875 0 1 0 1 0 0 1 3625 1 0 0 0 1 1 1 0000 1 1 0 0 1 1 1 3750 0 0 0 0 1 1 1 0125 0 1 0 0 1 1 1 3875 1 0 0 0 1 0 1 0250 1 1 0 0 1 0 1 4000 0 0 0 0 1 0 1 0375 0 1 0 0 1 0 1 4125 1 0 0 0 0 1 1 0500 1 1 0 0 0 1 1 4250 0 0 0 0 0 1 1 0625 0 1 0 0 0 1 1 4375 1 0 0 0 0 0 1 0750 1 1 0 0 0 0 1 4500 0 0 0 0 0 0 1 0875 0 1 0 0 0 0 1 4625 1 1 1 1 1 1 VRM off 1 0 1 1 1 1 1 4750 0 1 1 1 1 1 VRM off 0 0 1 1 1 1 1 4875 1 1 1 1 1 0 1 1000 1 0 1 1 1 0 1 5000 0 1 1 1 1 0 1 1125 0 0 1 1 1 0 1 5125 1 1 1 1 0 1 1 1250 1 0 1 1 0 1 1 5250 0 1 1 1 0 1 1
137. s specification is measured at the pin Baseboard bandwidth is limited to 20 MHz This specification refers to a single processor with R77 disabled Please note the end agent and middle agent may not require Irr max simultaneously Details will be provided in future revisions of this document This specification refers to platforms implementing a power delivery system that complies with VR 10 2 guidelines Please see the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 10 2 Design Guidelines for further details This specification refers to a single processor with Rr enabled Please note the end agent and middle agent may not require Irr max simultaneously This parameter is based on design characterization and not tested These specifications apply to the PLL power pins VCCA VCCIOPLL and VSSA See Section 2 1 3 for details These parameters are based on design characterization and are not tested This specification represents a total current for all GTLREF pins The current specified is also for HALT State This specification applies to both the HALT and Enhanced HALT States The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of the PROCHOT signal is the maximum lec for the processor loc Toc Thermal Design Current is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the vol
138. save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tri state its outputs STPCLK STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK TCK Test Clock provides the clock input for the processor Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TEST_BUS Must be connected to all other processor TEST_BUS signals in the system See the appropriate platform design guideline for termination details TESTHI 6 0 TESTHI 6 0 must be connected to a Vyr power source through a resistor for pro
139. series and are valid only while meeting specifications for case temperature clock frequency and input voltages Flexible Motherboard FMB Guidelines The FMB guidelines are estimates of the maximum values that the Dual Core Intel Xeon processor 7000 series will reach over the product lifetime The values are only estimates as actual specifications for future processors may differ The Dual Core Intel Xeon processor 7000 series may or may not have specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure that their systems will be compatible with future releases of the Dual Core Intel Xeon processor 7000 series Table 2 8 Voltage and Current Specifications Sheet 1 of 2 24 Symbol Parameter Min Typ Max Unit Notes VID range VID range for Dual Core Intel Xeon 1 2625 1 4125 V 2 3 processor 7000 series Voc Vcc for Dual Core Intel Xeon See Table 2 9 and VID lee max V 3 4 5 6 7 processor 7000 series Figure 2 4 1 25 mQ VID VID step size during a transition 12 5 mv J Transition z i 7 Total allowable DC load line shift from 450 mV VID steps VIT Front side bus termination voltage 1 176 1 20 1 224 V 10 DC specification Front side bus termination voltage 1 140 1 20 1 260 V 0 11 AC amp DC specification SM_VCC SMBus supply voltage 3 135 3 300 3 465 V 2 loc Icc for Dual Core Intel Xeon processor 150 FMB A 6
140. sertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid 6 clks before the I O write s response ADS y o ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 39 3 and transaction request type on REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must connect the appropriate pins on all Dual Core Intel Xeon processor 7000 series FSB agents ADSTB 1 0 y o Address strobes are used to latch A 39 3 and REQ 4 0 on their rising and falling edge AP 1 0 y o AP 1 0 Address Parity are driven by the requestor one common clock after ADS A 39 3 REQ 4 0 are driven A correct parity signal is electrically high if an even number of covered signals are electrically low and electrically low if an odd number of covered signals are electrically low This allows parity to be electrically high when all the covered signals are electrically high AP 1 0 should connect the appropriate pins of all Dual Core Intel Xeon processor 7000 series FSB agents The following table defines the coverage for these signals Request Signals Subphase 1 Subphase 2 A 39 24 APO AP1 A 23 3 AP1
141. sign Power TDP defined in Table 6 1 and the associated Tc Asp value The lower point of the thermal profile consists of x PcowrROL BASE nd y Tease Max PcoNTROL BASE Pcontrol is defined as the processor power at which Tcagg calculated from the thermal profile corresponds to the lowest possible value of Tcontrol This point is associated with the Tcontrol value see Section 6 2 6 However because Tcontrol represents a diode temperature it is necessary to define the associated case temperature This is Tease max PcoNTROL BASE Please see Section 6 2 6 and the Dual Core Intel Xeon Processor 7000 Sequence Thermal Mechanical Design Guidelines for proper usage of the Tcontrol specification The case temperature is defined at the geometric top center of the processor IHS Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the TDP indicated in Table 6 1 instead of the maximum processor power consumption The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature refer to Section 6 2 To ensure maximum flexibility for future requirements systems should be designed to the FMB guidelines even if a processor with a lower thermal dissipation is currently pla
142. solution Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keepout zone for all cooling solutions It is the system designer s responsibility to consider their proprietary cooling solution when designing to the required keepout zone on their system platform and chassis Figure 8 1 Passive Dual Core Intel Xeon Processor 7000 Series Thermal Solution 3U and Larger 4X HEAT SINK SCREW 7j _ HEAT SINK 4X HEATSINK a SCREW SPRING __ PROCESSOR MAIN BOARD AND SOCKET gt Dual Core Intel Xeon Processor 7000 Series Datasheet 97 Boxed Processor Specifications Ntel NOTE 1 The heatsink in this image is for reference only 2 This drawing shows the retention scheme for the boxed processor 8 2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor passive heatsink 8 2 1 Boxed Processor Heatsink Dimensions The boxed processor is shipped with an unattached passive heatsink Clearance is required around the heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor and assembled heatsink are shown in the following figures 98 Dual Core Intel Xeon Processor 7000 Series Datasheet 20 20 01 zu 20720701 DUSSIER di
143. t the memory components are in a known state in systems which do not support the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction SMBus Device Addressing The thermal sensor internally decodes one of three upper address patterns from the bus of the form 0011XXXZb 1001 XXXZb or 0101XXXZb The device s addressing as implemented uses the SM TS A 1 0 pins in either the HI LO or Hi Z state Therefore the thermal sensor supports nine unique addresses To set either pin for the Hi Z state the pin must be left floating As before the Z bit is the read write bit for the serial transaction Note that addresses of the form 0000XXXXb are Reserved and should not be generated by an SMBus master The thermal sensor samples and latches the SM TS A 1 0 signals at power up and at the starting point of every conversion System designers should ensure that these signals are at valid Vu Vu or floating input levels prior to or while the thermal sensor s SM VCC supply powers up This should be done by pulling the pins to SM VCC or Vgg via a 1 KQ or smaller resistor or leaving the pins floating to achieve the Hi Z state If the system designer wants to drive the SM TS A 1 0 pins with logic the designer must still ensure that the pins are at valid input levels prior to or while the SM VCC supply ramps up The system designer must also ensure that their particular impleme
144. tage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guidelines for further details The processor is capable of drawing Icc tpc indefinitely Refer to Figure 2 3 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested Dual Core Intel Xeon Processor 7000 Series Datasheet 25 Electrical Specifications n 26 Figure 2 3 Dual Core Intel Xeon Processor 7000 SeriesLoad Current vs Time Sustained Current A NOTES 155 150 145 140 135 130 125 T T T 0 01 0 1 1 10 100 1000 Time Duration s 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than lcc_Tpc 2 Not 100 tested Specified by design characterization Dual Core Intel Xeon Processor 7000 Series Datasheet n Electrical Specifications Table 2 9 Vcc Static and Transient Tolerance Icc Vcc_max Vcc_typical Vcc_min Notes 0 VID 0 000 VID 0 020 VID 0 040 1 2 3 5 VID 0 006 VID 0 026 VID 0 046 1 2 3 10 VID 0 013 VID 0 033 VID 0 052 1 2 3 15 VID 0 019 VID 0 039 VID 0 059 1 2 3 20 VID 0
145. te properly chassis air movement devices are required Necessary airflow and associated flow impedance is 29 cfm at 0 10 H50 In addition the processor pitch should be 3 25 inches or slightly more when placed in side by side orientation Figure 8 7 illustrates the side by side orientation and pitch Note that the heatsinks are interleaved to reduce air bypass It is also recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The air passing directly over the processor heatsink should not be preheated by other system components such as another processor and should be kept at or below 40 C Again meeting the processor s temperature specification is the responsibility of the system integrator Boxed Processor Contents The boxed processor will include the following items Dual Core Intel Xeon Processor 7000 Series Unattached passive heatsink with captive screws Thermal interface material pre attached Warranty installation manual with Intel Inside logo The other items required with this thermal solution should be shipped with either the chassis or the mainboard They include CEK spring typically included with mainboard Chassis standoffs System fans Dual Core Intel Xeon Processor 7000 Series Datasheet 105 Boxed Processor Specifications Ntel T 106 Dual Core Intel Xeon Processor 7000 Series Datasheet 9 1 9 1 1 9 1 2 Debug Tools Specifications
146. tel Pin Listing Table 4 1 Pin Listing by Pin Name Cont d Table 4 1 Pin Listing by Pin Name Cont d Pin Name Pin No Signal Direction Pin Name Pin No Signal Direction Buffer Type Buffer Type DSTBP3 Y11 Source Sync Input Output SM_ALERT AD28 SMBus Output FERR PBE E27 Async GTL Output SM_CLK AC28 SMBus Input FORCEPR A15 Async GTL Input SM_DAT AC29 SMBus Input Output GTLREFO W23 Power Other Input SM EP AO AA29 SMBus Input GTLREF1 Wa Power Other Input SM EP A1 AB29 SMBus Input GTLREF2 F23 Power Other Input SM EP A2 AB28 SMBus Input GTLREF3 F9 Power Other Input SM TS1 A0 AA28 SMBus Input HIT E22 Common Clk Input Output SM_TS1_A1 Y29 SMBus Input HITM A23 Common Clk Input Output SM_VCC AE28 Power Other IERR E5 Async GTL Output SM VCC AE29 Power Other IGNNE C26 Async GTL Input SM WP AD29 SMBus Input INIT D6 Async GTL Input SMI C27 Async GTL Input LINTO INTR B24 Async GTL Input STPCLK D4 Async GTL Input LINT1 NMI G23 Async GTL Input TCK E24 TAP Input LOCK A17 Common Clk Input Output TDI C24 TAP Input MCERR D7 Common Clk Input Output TDO E25 TAP Output ODTEN B5 Power Other Input TEST BUS A16 Power Other Input PROCHOT B25 Async GTL Output TESTHIO W6 Power Other Input PROCTYPE Y31 Power Other O TESTHI1 W7 Power Other Input PWRGOOD AB7 Async
147. tive on die termination Signal listings are included in Table 2 5 and Table 2 6 Figure 2 1 On Die Front Side Bus Termination 2 1 1 End Agent Middle Agent Signal Signal R44 On die termination resistors for AGTL signals R Additional on die resistance implemented for proper noise margin and signal integrity Front Side Bus Clock and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous processor generations the Dual Core Intel Xeon processor 7000 series core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set during manufacturing Dual Core Intel Xeon Processor 7000 Series Datasheet 15 Electrical Specifications Ntel Table 2 1 Table 2 2 The BCLK 1 0 inputs directly control the operating speed for the FSB interface The processor core frequency is configured during reset by using values stored internally during manufacturing The stored value sets the highest bus fraction at which the particular processor can operate If lower speeds are desired the appropriate ratio can be configured by setting bits 15 8 of the IA32 FLEX BRVID SEL MSR Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 1 0 input with exceptions for spread spectrum clocking Processor DC and AC specificati
148. to 1 transition by the processor FERR PBE TERR and IGNNE have now been defined as AGTL asynchrnous signals as they include an active p MOS device GTL asynchronous and AGTL asynchronous signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the GTL asynchronous and AGTL asynchronous signals are required to be asserted deasserted for at least six BCLKs in order for the processor to recognize them See Table 2 16 for the DC specifications for the asynchronous GTL signal groups Dual Core Intel Xeon Processor 7000 Series Datasheet 2 8 Table 2 7 Electrical Specifications Test Access Port TAP Connection Due to the voltage levels supported by other components in the TAP logic Intel recommends that the Dual Core Intel Xeon processor 7000 series be first in the TAP chain followed by any other components within the system Use of a translation buffer to connect to the rest of the chain is recommended unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TCK TMS TRST TDI and TDO Two copies of each signal may be required each driving a different voltage level Absolute Maximum and Minimum Ratings Table 2 7 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition l
149. tp www ssiforum org 1 3 State of Data The data contained within this document is subject to change It is the most accurate information available by the publication date of this document For processor stepping info refer to the Dual Core Intel Xeon Processor 7000 Sequence Specification Update 14 Dual Core Intel Xeon Processor 7000 Series Datasheet 2 1 Electrical Specifications Front Side Bus and GTLREF Most Dual Core Intel Xeon processor 7000 series FSB signals use Assisted Gunning Transceiver Logic AGTL signaling technology The termination voltage level for the Dual Core Intel Xeon processor 7000 series AGTL signals is Vr Termination resistors are provided on the processor silicon and are terminated to Vpr Intel chipsets also provide on die termination thus eliminating the need to terminate the bus on the system board for most AGTL signals Some AGTL signals do not include on die termination and must be terminated on the system board When designing a system Intel strongly recommends that design teams perform analog simulations of the FSB Design guidelines for the Dual Core Intel Xeon processor 7000 series FSB are detailed in the appropriate platform design guide Some Dual Core Intel Xeon processor 7000 series signals include additional on die resistors RL to ensure proper noise margin and signal integrity specifications are met see Table 2 5 for a list of these signals Figure 2 1 illustrates the ac
150. tput AE10 D42 Source Sync Input Output AE27 Vss Power Other AE11 Vss Power Other AE28 SM_VCC Power Other AE12 DBI2 Source Sync Input Output AE29 SM VCC Power Other AE13 D35 Source Sync Input Output AE30 Reserved Dual Core Intel Xeon Processor 7000 Series Datasheet 57 Pin Listing 58 Dual Core Intel Xeon Processor 7000 Series Datasheet 5 5 1 Signal Definitions Signal Definitions Table 5 1 Signal Definitions Sheet 1 of 7 Name Type Description A 39 3 y o A 39 3 Address define a 240 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the Dual Core Intel Xeon processor 7000 series FSB A 39 3 are protected by parity signals AP 1 0 A 39 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 39 3 pins to determine their power on configuration See Section 7 1 A20M If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 Mbyte boundary As
151. ts are measured across vias on the platform for the VCCSENSE and VSSSENSE pins close to the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Refer to Table 2 9 and corresponding Figure 2 4 The processor should not be subjected to any static Voc level that exceeds the Voc max associated with any particular current Failure to adhere to this specification can shorten processor lifetime Minimum Vcc and maximum Icc are specified at the maximum processor case temperature Tcasg shown in Table 6 1 loc max is specified at the relative Vcc max point on the Vcc load line The processor is capable of drawing Icc max for up to 10 ms Refer to Figure 2 3 for further details on the average processor current draw over various time durations FMBis the flexible motherboard guideline These guidelines are for estimation purposes only See Section 2 9 1 for further details on FMB guidelines This specification represents the Vcc reduction due to each VID transition See Section 2 2 AC timing requirements will be included in future revisions of this document This specification refers to the potential total reduction of the load line due to VID transitions below the specified VID V r must be provided via a separate voltage source and must not be connected to Vcc Thi
152. ue consists of seven bits of data and a sign bit MSB where the sign is always positive sign 0 and is shown in Table 7 7 The values shown are also used to program the Thermal Limit Registers The values of these registers should be treated as saturating values Values above 127 are represented at 127 decimal and values of zero and below may be represented as 0 to 127 decimal If the device returns a value where the sign bit is set 1 and the data is 000 0000 through 111 1110 the temperature should be interpreted as 0 Celsius Table 7 11 Temperature Value Register Encoding 7 4 6 2 7 4 6 3 84 Temperature Register Value binary 127 01111111 126 01111110 100 0 110 0100 50 0 011 0010 25 0 001 1001 1 0 000 0001 0 0 000 0000 Thermal Limit Registers The SMBus thermal sensor has high and low Thermal Limit Registers for each channel These registers allow the user to define high and low limits for the processor core thermal diode readings The encoding for these registers is the same as for the thermal reference registers shown in Table 7 7 If either processor thermal diode reading equals or exceeds one of these limits then the alarm bit RIHIGH R1LOW R2HIGH or R2LOW in the Thermal Sensor Status Register is triggered Status Registers The Status Registers shown in Table 7 12 and Table 7 13 indicates which if any thermal value thresholds for the processor core thermal diod
153. ut APO E10 Common Clk Input Output A20 A10 Source Sync Input Output AP1 D9 Common Clk Input Output A21 B10 Source Sync Input Output BCLKO Y4 FSB Clk Input A22 B11 Source Sync Input Output BCLK1 W5 FSB Clk Input A234 C12 Source Sync Input Output BINIT F11 Common CIk Input Output A248 E14 Source Sync Input Output BNR F20 Common Clk Input Output A25 D13 Source Sync Input Output BOOT SELECT G7 Power Other Input A26 A9 Source Sync Input Output BPMO F6 Common CIk Input Output A271 B8 Source Sync Input Output BPM1 F8 Common CIk Input Output BPM2 E7 Common Clk Input Output Dual Core Intel Xeon Processor 7000 Series Datasheet 41 intel Pin Listing Table 4 1 Pin Listing by Pin Name Cont d Table 4 1 Pin Listing by Pin Name Cont d Pin Name Pin No Die Direction Pin Name Pin No MER Direction BPM3 F5 Common CIk Input Output D274 AE22 Source Sync Input Output BPM4 E8 Common Clik Input Output D28 AE20 Source Sync Input Output BPM5 E4 Common CIk Input Output D29 AD21 Source Sync Input Output BPRI D23 Common Clk Input D30 AD19 Source Sync Input Output BRO D20 Common Clk Input Output D31 AB17 Source Sync Input Output BR1 F12 Common CIk Input Output D324 AB16 Source Sync Input Output BR2 E11 Common Clk I
154. ut Output Don t Care N5 DBSY F18 Common CIk Input Output Don t Care N7 DEFER C23 Common CIk Input Don t Care N9 Don t Care A2 Don t Care R1 Don t Care A26 Don t Care R3 Don t Care A28 Don t Care R5 Don t Care A30 Don t Care R7 Don t Care A31 Don t Care R9 Don t Care B4 Don t Care U1 Don t Care B26 Don t Care U3 Don t Care B29 Don t Care U5 Don t Care B30 Don t Care U7 Don t Care B31 Don t Care U9 Don t Care C2 Don t Care AA4 Don t Care C28 Don t Care AC4 Don t Care C31 Don t Care AC30 Don t Care D1 Don t Care AD6 Don t Care D25 Don t Care AD30 Don t Care D27 Don t Care AD31 Don t Care D29 Don t Care AE2 Don t Care E2 Don t Care AE3 Don t Care H1 Don t Care AE8 Don t Care H3 Don t Care AE15 Don t Care H5 Don t Care AE16 Don t Care H7 DPO AC18 Common Clk Input Output Don t Care H9 DP1 AE19 Common Clk Input Output Don t Care K1 DP2 AC15 Common Clk Input Output Don t Care K3 DP3 AE17 Common Clk Input Output Don t Care K5 DRDY E18 Common Clk Input Output Don t Care K7 DSTBNO Y21 Source Sync Input Output Don t Care K9 DSTBN1 Y18 Source Sync Input Output Don t Care M1 DSTBN2 Y15 Source Sync Input Output Don t Care M3 DSTBN3 Y12 Source Sync Input Output Don t Care M5 DSTBPO Y20 Source Sync Input Output Don t Care M7 DSTBP1 Y17 Source Sync Input Output Don t Care M9 DSTBP2 Y14 Source Sync Input Output Dual Core Intel Xeon Processor 7000 Series Datasheet 43 in
155. va Sana semi Ms i o ke 20729791 a IN o ol T Anne 31vo e gano 3ivo 18 0332382 48 navaa 1830 ATO 39N383438 04 0027 92118 AYVANNOG 133208 09v9du Boxed Processor Specifications NO112181S3U 1H913H 196 j S 9 L 8 30 T I33S 9WIAY8Q AWIS LOW OOT NOW 3735 T Zem em SI 26261V x qd 7 Q3WO11V SIN3NOdNO3 QHYOBHHLON ON 100433 YIONI4 GYVO 9NINJS 3D Ei jew ontavua 3002 ovo laris mum T 1 1nod33y zea Suel aa mag NOI12141938 1H913H 1N3NOdNOO QUYOGU3HION XVN WPI ISS NOI12181S38 1H913H LNINOdWOD XVH WW 92 8 GZC V3uV A18N3SSVSIQ XNISIV3H NOLLOIYLS3Y 1H913H 1N3NOdHOO XVW WW 9278 S2t V3uV JNISIV3H NOI12181938 1H913H 1N3NOdWOD XVN NN BTE OGI Q3MO11V 1N3W32V1d LNINOdNOD QNVOGH3HLON ON l D NO 11213815833 ma 7 N H EIERE M H A H 3NI1L00 WNISLV3H 0017 000000 O00000 h YL 9L 000000 00000 HE HEH 995999 399399 339389 333383 9087 pu p a hor i
156. vered signals are electrically low If RS 2 0 are all electrically high RSP is also electrically high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present There is no connection to the processor silicon for this signal SM_ALERT SM_ALERT SMBus Alert is an asynchronous interrupt line associated with the SMBus Thermal Sensor device It is an open drain output and the processor includes a 10 kQ pull up resistor to SM_VCC for this signal For more information on the usage of the SM_ALERT pin see Section 7 4 7 SM_CLK y o The SM CLK SMBus Clock signal is an input clock to the system management logic which is required for operation of the system management features of the Dual Core Intel Xeon processor 7000 series This clock is driven by the SMBus controller and is asynchronous to other clocks in the processor The processor includes a 10 KQ pull up resistor to SM VCC for this signal SM DAT y o The SM DAT SMBus Data signal is the data signal for the SMBus This signal provides the single bit mechanism for transferring data between SMBus devices The processor includes a 10 kQ pull up resistor to SM VCOC for this signal Dual Core Intel Xeon Processor 7000 Series Datasheet 63 Signal Definitions Intel Table 5 1 Signal Definitions She
157. will include manageability features Components of the manageability features include an OEM writable EEPROM and Processor Information ROM Dual Core Intel Xeon Processor 7000 Series Datasheet 11 Introduction Table 1 1 1 1 intel which are accessed through an SMBus interface and contain information relevant to the particular processor and system in which it is installed Thermal management and further thermal redundancy can be achieved with the use of the Thermal Monitor feature Features of the Dual Core Intel Xeon Processor 7000 Series of Supported L2 Advanced Front Side Bus Processor Symmetric Transfer Package Agents per Bus Cache Frequency Dual Core Intel Xeon 1 2 1 2 MB per core 667 MHz 604 pin FC mPGA4 processor 7000 series The Dual Core Intel Xeon processor 7000 series supports Intel 64 as an enhancement to Intel s IA 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details on Intel 64 and its programming model can be found in the 64 bit Extension Technology Software Developer s Guide at http developer intel com technology 64bitextensions The Dual Core Intel Xeon processor 7000 series is packaged in a 604 pin Flip Chip Micro Pin Grid Array FC mPGA4 package and utilizes a surface mount Zero Insertion Force ZIF mPGA604 socket The Dual Core Intel Xeon processor 7

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