Intel Pentium SL22T processor
Contents
1. 0 0 3 1 10 M MSR Model Specific Register 1 2 3 7 P Physical xAPICID liliis 3 1 10 R FA so el oe Eyed ees 3 6 Index 1 S SELF IPI register ee EE Ee Ee ee ee 4 7 SVR Spurious Interrupt Vector Register 16 T TMR Trigger Mode Register 5 15 16 18 TPR Task Priority Register 4 7 18 X XOAPIE EE SE e enum 2 1 2 15 23 x2APICID 3 10 11 12 14 18 20 23 x2APIC Mode2 1 2 3 6 7 9 10 11 13 14 15 17 23 XAPIC camo 1 2 1 3 7 9 14 17 23 xAPIC Mode 2 3 7 10 12 13 15 16 17 23 Index 2 This page intentionally left blank Index 32. The high half of the Interrupt Command Register is not preserved 2 8 CPUID EXTENSIONS AND TOPOLOGY ENUMERATION For Intel 64 and 1A 32 processors that support x2APIC the CPUID instruction provides additional mechanism for identifying processor topology information Specifically a value of 1 reported by CPUI D O1H ECX 21 indicates that the processor supports x2APIC and the extended topology enumeration leaf CPUID OBH The extended topology enumeration leaf can be accessed by executing CPUID with EAX OBH Software can detect the availability of the extended topology enumera tion leaf OBH by performing two steps Check maximum input value for basic CPUID information by executing CPUID with EAX 0 If CPUID OH EAX is greater than or equal or 11 OBH then proceed to next step e Check CPUID EAX 0BH ECX 0H EBX is non zero If both of the above conditions are true extended topology enumeration leaf is avail able The presence of CPUID leaf OBH in a processor does not guarantee support for X2APIC If CPUI D EAX OBH ECX 0H EBX returns zero and maximum input value for basic CPUID information is greater than OBH then CPUI D OBH leaf is not supported on that processor The extended topology enumeration leaf is intended to assist software with enumer ating processor topology on systems that requires 32 bit x2APIC IDs to address indi vidual logical processors The basic concept of processor topology enumeration using 8 bit
3. IPI register x2APIC mode only with an illegal vector vector lt OFH will set the Send Illegal Vector bit On receiving an IPI with an illegal vector vector lt OFH the Receive Illegal Vector bit will be set On receiving an interrupt with illegal vector in the range OH OFH the interrupt will not be delivered to the processor nor will an IRR bit be set in that range Only the ESR Receive Illegal Vector bit will be set If the ICR is programmed with lowest priority delivery mode then the Re directible I PI bit will be set in X2APIC modes same as legacy xAPIC behavior and the inter rupt will not be processed 31 87654 3210 Reserved Illegal Register Address Received Illegal Vector Send Illegal Vector Redirectible IPI Reserved MSR Address 828H Figure 2 2 Error Status Register ESR 2 3 6 X2APIC Register Availability The local APIC registers can be accessed via the MSR interface only when the local X2APIC has been switched to the x2API C mode as described in Section 2 2 Accessing any APIC register in the MSR address range 0800H through OBFFH via RDMSR or WRMSR when the local APIC is not in x2APIC mode will cause the instructions to raise a GP fault In x2APIC mode the memory mapped interface is not available and any access to the MMIO interface will behave similar to that of a legacy xAPIC in globally disabled state Table 2 3 provides the intera
4. intel Intel 64 Architecture x2APIC Specification Reference Number 318148 004 March 2010 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANT ED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTI ES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL LIFE SAVING OR LIFE SUSTAINING APPLICATIONS Intel may make changes to specifications and product descriptions at any time without notice Developers must not rely on the absence or characteristics of any features or instructions marked re served or undefined Improper use of reserved or undefined features or instructions may cause unpre dictable behavior or failure in developer s software code when running on an Intel processor Intel reserves these features or instructions for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from their unauthorized use The Intel 64 architecture processors may contain design defects or errors known as errata Current c
5. specified in the Intel Virtualization Technology for Directed I O Rev 1 1 specification Modifications to ACPI interfaces to support x2APIC are described in the ACPI 4 0 specification 1 3 GLOSSARY This document uses the terms listed in the following table Term Table 1 1 Description of terminology Description APIC The set of advanced programmable interrupt controller features which may be implemented in a stand alone controller part of a system chipset or in a microprocessor local APIC The processor component that implements the APIC functionalities The underlying APIC registers their functionalities are documented in Chapter 8 of Intel 64 and IA 32 Architectures Software Developer s Manual Vol 3B Historically this may refer narrowly to early generations of processor component in the Pentium and P6 processors In this document we also use this term generically across multiple generations of processor components VO APIC The system chipset component that implements APIC functionalities to communicate with a local APIC xAPIC The extension of the APIC architecture that includes messaged APIC interface over the system bus and expanding processor physical addressability from 4 bits to 8 bits local xAPIC The processor component that implements the associated xAPIC functionalities This is supported by Intel Pentium 4 processors Pentium M processors Intel Core M Duo processors
6. to report correct topology up to the maximum values supported by the fields and 8 bit initial APIC ID For future processors with topology that exceeds the limits of CPUID O1H EBX 23 16 CPUI D OLH EBX 31 24 CPUID EAX 04H ECX 0H EAX 31 26 these legacy fields will report the respective modulo maximum values If CPUID OBH returns EBX 0 when input ECX 0 then assume that CPUI D OBH leaf data for extended processor topology enumeration is not supported on this processor Use CPUID 01H and CPUI D 04H leaves for topology information 2 22 LOCAL x2APIC ARCHITECTURE 2 8 1 Consistency of APIC IDs and CPUID The consistency of physical x2APIC ID in MSR 802H in x2APIC mode and the 32 bit value returned in CPUI D OBH EDX is facilitated by processor hardware CPUI D OBH EDX will report the full 32 bit ID in xAPIC and x2APIC mode This allows BIOS to determine if a system has processors with IDs exceeding the 8 bit initial APIC ID limit CPUID O1H EBX 31 24 Initial APIC ID CPUID O1H EBX 31 24 is always equal to CPUI D OBH EDX 7 0 If the values of CPUI D OBH EDX reported by all logical processors in a system are less than 255 BIOS can transfer control to OS in xAPIC mode If the values of CPUI D OBH EDX reported by some logical processors in a system are greater or equal than 255 BIOS must support two options to hand off to OS e f BIOS enables logical processors with x2APIC IDs greater than 255 then it should ena
7. zero value to EOI register is enforced Writes of a non zero value to the EOI register in x2APIC mode will raise a GP fault System soft ware continues to have to perform the EOI write to indicate interrupt service comple tion But in x2APIC mode the EOI write is with a value of zero 2 3 5 4 Error Status Register Semantics The Error Status register ESR records all errors detected by the local APIC In xAPI C mode software can read write to the ESR A write of any value to the ESR must be done to update the register before attempting to read it This write clears any previously logged errors and updates the ESR with any errors detected since the 2 8 LOCAL x2APIC ARCHITECTURE last write to the ESR Errors are collected regardless of LVT Error mask bit but the APIC will only issue an interrupt due to the error if the LVT Error mask bit is cleared In the x2APIC mode the write of a zero value is enforced Software writes zero s to the ESR to clear the error status Writes of a non zero value to the Error Status Register in x2APIC mode will raise a GP fault The layout of ESR is shown in Figure 2 2 In x2API C mode a RDMSR or WRMSR to an illegal register address raises a GP fault In xAPIC mode the equivalent MMIO accesses would have generated an APIC error So in the x2APIC mode the Illegal Register Address field in the Error Status register will not have any errors logged Write to the ICR in xAPIC and x2API C modes or to SELF
8. 9 Read Only 0150H 015H ISR bits 160 191 Read Only 0160H 016H ISR bits 192 223 Read Only 0170H 017H ISR bits 224 255 Read Only 0180H 018H Trigger Mode Register Read Only TMR bits 0 31 0190H 019H TMR bits 32 63 Read Only 01A0H 01AH TMR bits 64 95 Read Only 01BOH 01BH TMR bits 96 127 Read Only 01COH 01CH TMR bits 128 159 Read Only O1DOH 01DH TMR bits 160 191 Read Only 01 0H O1EH TMR bits 192 223 Read Only 01F0H O1FH TMR bits 224 255 Read Only 0200H 020H Interrupt Request Read Only Register IRR bits 0 31 0210H 021H IRR bits32 63 Read Only 0220H 022H IRR bits 64 95 Read Only 0230H 023H IRR bits 96 127 Read Only 0240H 024H IRR bits 128 159 Read Only 0250H 025H IRR bits 160 191 Read Only 0260H 026H IRR bits 192 223 Read Only 0270H 027H IRR bits 224 255 Read Only 0280H 028H Error Status Register Read Write GP fault on non zero writes 0290H 029H 02 EH Reserved 02 0H 02FO0H 02FH Reserved 0300H 030H Interrupt Command Read Write 0310H Register ICR bits 0 63 2 5 LOCAL x2APIC ARCHITECTURE Table 2 2 Local APIC Register Address Map Supported by x2APIC Contd MSR Offset MMIO Offset x2APIC R W XAPIC mode mode Register Name Semantics Comments 0320H 032H LVT Timer Register Read Write 0330H 033H LVT Thermal Sensor Read Write Register 0340H 034H LVT Performance Read Write Monitoring Register 0350H 035H LVT LINTO Regis
9. D register in the system are reserved and cannot be assigned to any logical processor In x2APIC mode the local APIC ID register is a read only register to system software and will be initialized by hardware It is accessed via the RDMSR instruction reading the MSR at address 0802H Figure 2 3 provides the layout of the Local x2APIC ID register MSR Address 802H 31 0 x2APIC ID Figure 2 3 Local APIC ID Register in x2APIC Mode Each logical processor in the system including clusters with a communication fabric must be configured with an unique x2APIC ID to avoid collisions of x2APIC IDs On DP and high end MP processors targeted to specific market segments and depending on the system configuration it is possible that logical processors in different and un connected clusters power up initialized with overlapping x2APIC IDs In these configurations a model specific means may be provided in those product segments to enable BIOS and or platform firmware to re configure the x2APIC IDs in some clusters to provide for unique and non overlapping system wide IDs before config uring the disconnected components into a single system 2 4 2 Logical Destination Register In x2APIC mode the Logical Destination Register LDR is increased to 32 bits wide It is a read only register to system software This 32 bit value is referred to as logical x2APIC ID System software accesses this register via the RDMSR instruc tion rea
10. ICR Destina tion Shorthand ICR 19 18 01 Self Trigger Mode ICR 15 0 Edge Delivery Mode ICR 10 8 000 Fixed Vector ICR 7 0 Vector 2 14 LOCAL x2APIC ARCHITECTURE MSR Address 083FH 31 87 0 Reserved Vector Figure 2 6 SELF IPI register The SELF IPI register is a write only register A RDMSR instruction with address of the SELF IPI register will raise a GP fault The handling and prioritization of a self IPI sent via the SELF IPI register is architec turally identical to that for an IPI sent via the ICR from a legacy xAPIC unit Specifi cally the state of the interrupt would be tracked via the Interrupt Request Register IRR and In Service Register ISR and Trigger Mode Register TMR as if it were received from the system bus Also sending the IPI via the Self Interrupt Register ensures that interrupt is delivered to the processor core Specifically completion of the WRMSR instruction to the SELF IPI register implies that the interrupt has been logged into the IRR As expected for edge triggered interrupts depending on the processor priority and readiness to accept interrupts it is possible that interrupts sent via the SELF IPI register or via the ICR with identical vectors can be combined 2 5 X2APIC ENHANCEMENTS TO LEGACY XAPIC ARCHITECTURE The x2APIC architecture also provides enhanced features for a local x2APIC unit operating in xAPI C mode This section describes x2APIC enhancem
11. PIC ID 3 0 The rest of the bits of the x2APIC ID then form the cluster ID portion of the logical x2APIC ID Logical x2APIC ID X2APIC ID 31 4 lt lt 16 1 lt lt X2APIC ID 3 0 The use of lowest 4 bits in x2APIC ID implies that at least 16 APIC IDs are reserved for logical processors within a socket in multi socket configurations If more than 16 APIC IDS are reserved for logical processors in a socket package then multiple cluster Ds can exist within the package The LDR initialization occurs whenever the x2APIC mode is enabled This is described in Section 2 7 2 4 5 SELF IPI register SELF IPIs are used extensively by some system software The xAPIC architecture provided a mechanism for sending an IPI to the current local APIC using the self PI short hand in the interrupt command register see Figure 2 5 The x2APIC architec ture introduces a new register interface This new register is dedicated to the purpose of sending self IPls with the intent of enabling a highly optimized path for sending self IPl s Figure 2 6 provides the layout of the SELF IPI register System software only speci fies the vector associated with the interrupt to be sent The semantics of sending a self IPI via the SELF IPI register are identical to sending a self targeted edge trig gered fixed interrupt with the specified vector Specifically the semantics are identical to the following settings for an inter processor interrupt sent via the
12. Status Register The details on Error Status Register are in Section 2 3 5 4 2 3 5 MSR Access Semantics To allow for efficient access to the APIC registers in X2APIC mode the serializing semantics of WRMSR are relaxed when writing to the APIC registers Thus system software should not use WRMSR to APIC registers in x2API C mode as a serializing instruction Read and write accesses to the APIC registers will occur in program order Additional semantics for the WRMSR instruction expected by system software for specific registers EOI TPR SELF IPI are described in Section 2 3 5 3 Section 2 3 5 2 and Section 2 4 5 The RDMSR instruction is not serializing and this behavior is unchanged when reading APIC registers in x2APIC mode System software accessing the APIC regis ters using the RDMSR instruction should not expect a serializing behavior Note The MMI O based xAPIC interface is mapped by system software as an un cached region Consequently read writes to the xAPI C MMIO interface have serializing semantics in the xAPIC mode There are some simplifications to the means used by system software for accessing the Interrupt Control Register via the register interface in the x2API C mode These changes are described in Section 2 3 5 1 2 3 5 1 Interrupt Command Register Semantics A processor generates an inter processor interrupt IPI by writing to the Interrupt Command Register ICR in the local xAPIC unit In xAPIC mode ICR
13. al xAPIC ID Logical xAPIC ID is not initialized by hardware The value reported by CPUID 01H EBX 31 24 Initial APIC ID is initialized initial APIC ID by hardware The 32 bit value in the local APIC ID register defined by the x2APIC architecture The value is initialized by hardware and can be accessed via RDMSR in x2APIC mode It is also reported by CPUID OBH EDX Application x2APIC ID can query CPUID OBH EDX in user mode without RDMSR logical x2APIC ID The APIC ID value that specifies a target processor to receive interrupt delivered in logical destination mode in a local x2APIC This is a 32 bit value initialized by hardware RsvdZ Reads of reserved bits return zero 1 4 REFERENCES http developer intel com products processor manuals index htm Intel Virtualization Technology for Directed O Rev 1 1 specification Intel 64 and 1A 32 Architectures Software Developer s Manual in five volumes http download intel com technology computing vptech Intel r VT for Direc t 1O pdf Detecting Multi Core Processor Topology in an 1 A 32 Platform http www3 intel com cd ids developer asmo na eng recent 275339 htm The ACPI 4 0 specification http www acpi info spec htm INTRODUCTION This page intentionally left blank 2 1 LOCAL x2APIC ARCHITECTURE CHAPTER 2 LOCAL x2APIC ARCHITECTURE X2APIC ENHANCEMENTS The key enhancements provided by the x2APIC architecture over xAPIC are the following Sup
14. and Intel Xeon processors based on Intel NetBurst microarchitecture and Intel Core microarchitecture x2APIC The extension of xAPIC architecture to support 32 bit addressability of processors and associated enhancements local x2APIC The processor component that implements the associated x2APIC functionalities XAPIC mode The operating mode of a local xAPIC unit when it is enabled or that of a local x2APIC unit when it is enabled but not in extended mode X2APIC mode The operating mode of a local x2APIC unit when it is enabled and in extended mode INTRODUCTION Table 1 1 Description of terminology Term Description APIC ID A unique ID that can identify individual agent in a platform or clustered configuration The maximum bit width supported is 8 bit versus 32 bits in X2APIC local xAPIC ID The value configured in the local APIC ID register in xAPIC mode This is an 8 bit value for xAPIC and x2APIC in xAPIC mode Because this is used to specify a target destination in physical delivery mode it is also referred to as physical xAPIC ID The processor initializes local xAPIC ID physical xAPIC ID See local xAPIC ID The APIC ID value that specifies a target processor to receive interrupt delivered in logical destination mode in a local xAPIC See documentation on logical destination register LDR in Section 2 4 2 This is an 8 bit value logic
15. bits of the APIC register for access in xAPIC mode e The following APIC registers are reset to all zeros for those fields that are defined in the xAPI C mode IRR ISR TMR ICR LDR TPR Divide Configuration Register See Chapter 8 of Intel 64 and 1A 32 Architectures Software Developer s Manual Vol 3B for details of individual APIC registers Timer initial count and timer current count registers The LVT registers are reset to Os except for the mask bits these are set to 1s The local APIC version register is not affected The Spurious Interrupt Vector Register is initialized to 000000FFH e The DFR available only in xAPI C mode is reset to all 1s SELF IPI register is reset to zero Disabled EN 1 ni EN 0 Illegal Extd 0 Transition A M Extd 1 7A cbe E E oie EN 1 Extd 0 _ ie invalid MELLE Extd 1 die w Illegal Te ea eee N Transition EN 0 x Extd 0 A llegal 2 B Transition Extended EN 0 Mode EN 1 Extd 1 Reset Init Figure 2 9 Local x2APIC State Transitions with IA32 APIC BASE INIT and RESET 2 18 LOCAL x2APIC ARCHITECTURE 2 7 1 1 X2APIC After RESET The valid transitions from the xAPI C mode state are e to the x2APIC mode by setting EXT to 1 resulting EN 1 EXTD 1 The physical X2APIC ID see Figure 2 3 is preserved across this transition and the logical x2APIC ID see Figure 2 4 is initialized by hardware
16. ble X2APIC in Boot Strap Processor BSP and all Application Processors AP before passing control to the OS Application requiring processor topology information must use OS provided services based on x2APIC I Ds or CPUI D OBH leaf e faBIlOS transfers control to OS in xAPIC mode then the BIOS must ensure that only logical processors with CPUI D OBH EDX value less than 255 are enabled BIOS initialization on all logical processors with CPUI D OB EDX values greater than or equal to 255 must a disable APIC and execute CLI in each logical processor and b leave these logical processor in the lowest power state so that these processors do not respond to INIT IPI during OS boot The BSP and all the enabled logical processor operate in xAPIC mode after BIOS passed control to OS Application requiring processor topology information can use OS provided legacy services based on 8 bit initial APIC IDs or legacy topology information from CPUI D O1H and CPUID 04H leaves 29 SYSTEM TRANSITIONS This section describes implications for the x2APIC across system state transitions specifically initialization and booting The default will be for the BIOS to pass the control to the OS with the local x2API Cs in xAPI C mode if all x2APIC IDs reported by CPUI D OBH EDX are less than 255 and in X2APIC mode if there are any logical processor reporting its X2APIC ID at 255 or greater 2 10 LEGACY xAPIC CLARIFICATIONS The x2APIC architecture eliminates
17. contains a delivery status bit bit 12 that indicates the status of the delivery of this interrupt The field has software read only semantics A value of 0 implies that there is currently no activity while a value of 1 implies that the transmission is pending The delivery status bit gets cleared when the interrupt has been transmitted With the legacy xAPIC interface system software would poll the delivery status bit until it is clear prior to sending an IPI Similarly if the semantics of the send operation required that the interrupt be sent from the local xAPIC unit then system software would busy wait for the delivery status bit to be cleared In the x2APIC mode the semantics of programming Interrupt Command Register to dispatch an interrupt is simplified A single MSR write to the 64 bit ICR see Figure 2 5 is required for dispatching an interrupt 2 7 LOCAL x2APIC ARCHITECTURE Other semantics change related to reading writing the I CR in x2APIC mode vs xAPIC mode are Completion of the WRMSR instruction to the ICR does not guarantee that the interrupt to be dispatched has been received by the targeted processors If the system software usage requires this guarantee then the system software should explicitly confirm the delivery of the interrupt to the specified targets using an alternate software mechanisms For example one possible mechanism would be having the interrupt service routine associated with the target interrupt de
18. ctions between the legacy amp extended modes and the legacy and register interfaces 2 9 LOCAL x2APIC ARCHITECTURE Table 2 3 MSR MMIO Interface of a Local x2APIC in Different Modes of Operation MMIO Interface MSR Interface xAPIC mode Available GP Fault X2APIC mode Behavior identical to xAPIC in globally Available disabled state 2 3 7 VM exit Controls for MSRs and x2APIC Registers The VMX architecture allows a VMM to specify lists of MSRs to be loaded or stored on VMX transitions using the VMX transition MSR areas see VM exit MSR store address field VM exit MSR load address filed and VM entry MSR load address field in Intel 64 and A 32 Architectures Software Developer s Manual Volume 3B The X2API C MSRs cannot to be loaded and stored on VMX transitions A VMX transi tion fails if the VMM has specified that the transition should access any MSRs in the address range from 0000 0800H to 0000 08FFH the range used for accessing the X2APIC registers Specifically processing of an 128 bit entry in any of the VMX transition MSR areas fails if bits 31 0 of that entry represented as ENTRY LOW DW satisfies the expression ENTRY LOW DW amp FFFFF800H 00000800H Such a failure causes an associated VM entry to fail by reloading host state and causes an associated VM exit to lead to VMX abort 2 4 EXTENDED PROCESSOR ADDRESSABILITY This section provides details on extensions to the physical xAPIC ID a
19. deprecates some of the features provided by the legacy xAPIC and some of the legacy xAPIC features that were not used by prevailing commercial system software This section provides a list of the features capabilities that are not supported in the x2APIC architecture 2 23 LOCAL x2APIC ARCHITECTURE Re directible Lowest Priority inter processor interrupts are not supported in the X2APIC architecture 2 24 LOCAL x2APIC ARCHITECTURE This page intentionally left blank LOCAL x2APIC ARCHITECTURE 2 26 A APIE si ed Ser RR n bea 1 2 1 6 7 9 17 nid Rr 3 11 14 23 C CPUID instruction deterministic cache parameters leaf 21 D DFR Destination Format Register 3 12 18 E EOI End Of Interrupt register 1 4 7 15 ESR Error Status Register liis 5 7 ICR Interrupt Command Register 3 13 14 15 18 Initial APIC ID ser te e 3 20 Interrupt Command Register 3 IRR Interrupt Request Register 5 15 18 ISR In Service Register 1 4 15 18 l Q APIC RES ee EE xr bs ane rts Cees ees 2 L LDR Logical Destination Register 3 10 11 14 18 Local APIE ic 2408 ord fret 2 4 register address map iii Ee Ee de 4 Local x2APIC 2 1 12 15 16 17 23 Local xAPIC EE iE aa nd oe Have EE E Di 1 2 15 Local APIE ID ie EE NE RA teas eee 3 18 Logical x2APICID 3 1 10 12 14 Logical xAPICID
20. ding the MSR at address 80DH Figure 2 4 provides the layout of the Logical Destination Register in x2API C mode 2 11 LOCAL x2APIC ARCHITECTURE MSR Address 80DH 31 0 Logical x2APIC ID Figure 2 4 Logical Destination Register in x2APIC Mode In the xAPIC mode the Destination Format Register DFR through MMIO interface determines the choice of a flat logical mode or a clustered logical mode Flat logical mode is not supported in the x2APIC mode Hence the Destination Format Register DFR is eliminated in x2APIC mode The 32 bit logical x2APIC ID field of LDR is partitioned into two sub fields Cluster ID LDR 31 16 is the address of the destination cluster Logical ID LDR 15 0 defines a logical ID of the individual local x2APIC within the cluster specified by LDR 31 16 This layout enables 2 16 1 clusters each with up to 16 unique logical IDs effec tively providing an addressability of 2 20 16 processors in logical destination mode Itis likely that processor implementations may choose to support less than 16 bits of the cluster I D or less than 16 bits of the Logical ID in the Logical Destination Register However system software should be agnostic to the number of bits implemented in the cluster I D and logical ID sub fields The x2APIC hardware initialization will ensure that the appropriately initialized logical x2APIC IDs are available to system software and reads of non impleme
21. during this transition as documented in Section 2 4 4 The state of the extended fields in other APIC registers which was not initialized at RESET is not architecturally defined across this transition and system software should explicitly initialize those program mable APIC registers e to the disabled state by setting EN to 0 resulting EN 0 EXTD 0 The result of an INIT in the xAPIC state places the x2APIC in the state with EN 1 EXTD 0 The state of the local APIC ID register is preserved the 8 bit xAPIC ID is in the upper 8 bits of the APIC ID register All the other APIC registers are initialized as a result of INIT A RESET in this state places the x2APIC in the state with EN 1 EXTD 0 The state of the local APIC ID register is initialized as described in Section 2 7 1 All the other APIC registers are initialized described in Section 2 7 1 2 7 1 2 X2APIC Transitions From x2APIC Mode From the x2API C mode the only valid x2APIC transition using 1A32 APIC BASE is to the state where the x2APIC is disabled by setting EN to 0 and EXTD to 0 The x2APIC ID 32 bits and the legacy local xAPIC ID 8 bits are preserved across this transi tion A transition from the x2APIC mode to xAPI C mode is not valid and the corre sponding WRMSR to the A32 APIC BASE MSR will raise a GP fault A RESET in this state places the x2APIC in xAPIC mode All APIC registers including the local APIC ID register are initialized as described in Secti
22. e accessed only through MSR based interfaces in the x2API C mode The Memory Mapped IO MMI O interface used by xAPIC is not supported in the x2APIC mode The semantics for accessing API C registers have been revised to simplify the programming of frequently used APIC registers by system software Specifically the software semantics for using the I nterrupt Command Register ICR and End Of Interrupt EOI registers have been modified to allow for more efficient delivery and dispatching of interrupts The x2APIC extensions are made available to system software by enabling the local X2APIC unit in the x2APIC mode The rest of this chapter provides details for detecting enabling and programming features of x2APIC 2 1 LOCAL x2APIC ARCHITECTURE P DETECTING AND ENABLING x2APIC A processor s support to operate its local APIC in the x2APIC mode can be detected by querying the extended feature flag information reported by CPUID When CPUID is executed with EAX 1 the returned value in ECX Bit 21 indicates processor s support for the x2API C mode If CPUID EAX 01H ECX Bit 21 is set then the local APIC in the processor supports the x2APIC capability and can be placed into the X2API C mode This bit is set only when the x2APIC hardware is present e System software can place the local APIC in the x2APIC mode by setting the X2APIC mode enable bit bit 10 in the 1A32 APIC BASE MSR at MSR address O1BH The layout for the A32 APIC BASE MSR i
23. ents that are common to xAPI C mode and x2APIC mode 2 5 1 Directed EOI To support level triggered interrupts the legacy xAPIC architecture broadcasts EOI messages for level triggered interrupts over the system interconnect to all the OxAPICs in the system indicating that the interrupt has been serviced Broadcasting the EOIs can lead to system inefficiencies on a link based system interconnect Also in systems with multiple IOxAPICs where different IOxAPI Cs have been programmed with the same vector but different processor destinations the broad casting of the EOI message can lead to duplicate interrupts being delivered to the local xAPIC for the same event on an IO device 2 15 LOCAL x2APIC ARCHITECTURE Directed EOI capability is intended to enable system software to perform directed EOIs to specific IOxAPICs in the system System software desiring to perform a directed EOI would do the following inhibit the broadcast of EOI message by setting bit 12 of the Spurious Interrupt Vector Register and following the EOI to the local x2APIC unit for a level triggered interrupt perform a directed EOI to the IOxAPIC generating the interrupt by writing to its EOI register Supporting directed EOI capability would require system software to retain a mapping associating level triggered interrupts with IOxAPICs in the system Bit 12 of the Spurious Interrupt Vector Register SVR in the local x2APIC unit controls the generation of
24. gy of the system This value in this field EBX 15 0 is only intended for display diagnostic purposes The actual number of logical processors available to BIOS OS Applications may be different from the value of EBX 15 0 depending on software and platform hardware configura tions The value of Level Type field is not related to level numbers in any way higher level type values do not mean higher levels Level Type field has the following encoding 0 Invalid 1 SMT 2 Core 3 255 Reserved The lowest level number is zero Level number 0 is reserved to specify SMT related topology information see Hyper Threading Technology in Section 7 8 of Intel amp 64 and 1A 32 Architectures Software Developer s Manual Vol 3A If SMT is not present in a processor implementation but CPUID leaf OBH is supported CPUI D EAX OBH ECX 0 will return EAX 0 EBX 1 and level type 1 Number of logical processors at the core level is reported at level type 2 CPUI D OBH leaf can report level type and level number in any order Each level type defines a specific topology configuration within the physical package Thus there is no level type corresponding to package for CPUI D OBH leaf The Level Type encodings indicate the topology level and need not correspond to any Level number except level number 0 is reserved for level type SMT The legacy processor topology enumeration fields in CPUI D O1H and CPUID O4H will continue
25. har acterized errata are available on request Hyper Threading Technology requires a computer system with an Intel processor supporting Hyper Threading Technology and an HT Technology enabled chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information see http www in tel com technology hyperthread index htm including details on which processors support HT Technology Intel virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality perfor mance or other benefits will vary depending on hardware and software configurations Intel virtualization Technology enabled BIOS and VMM applications are currently in development 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS oper ating system device drivers and applications enabled for Intel 64 architecture Processors will not operate including 32 bit operation without an Intel 64 architecture enabled BIOS Performance will vary de pending on your hardware and software configurations Consult with your system vendor for more infor mation Intel Pentium Intel Xeon Intel NetBurst Intel Core Solo Intel Core Duo Intel Core 2 Duo Intel Core 2 Extreme Intel Pentium D Itanium Intel SpeedStep MMX and VTune are trademarks or regis
26. initial APIC ID CPUID O1H EBX 31 24 on legacy systems is similar to using 32 bit X2APIC ID reported by CPUID leaf OBH apply appropriate bit masks on unique IDs to sort out levels of topology in a system Legacy processor enumeration algorithm is based on examining the initial APIC IDs and additional information from CPUI D leaves 01H and 04H to infer system wide 2 20 LOCAL x2APIC ARCHITECTURE processor topology The relevant information in CPUID leaves 01H and 04H do not directly map to individual levels of the topology but merely relate to the sharing characteristics below different levels The extended topology enumeration leaf of CPUID provides topology information and data that simplify the algorithm to sort out the processor topology within a physical package from a 32 bit x2APIC ID Each level of the processor topology is enumerated by specifying a level number in ECX as input when executing CPUI D EAX OBH This enumeration by level number allows the CPUI D OBH leaf to support more sophisti cated topology than the limitation of legacy topology definitions SMT core package The bit fields reported by CPUI D EAX OBH include the x2APIC ID of the current logical processor in EDX an encoded value of hierarchy referred to as level type in ECX 15 8 the number of enabled logical processors at each queried level type below its immediate parent level type and a bit vector length field to simplify the parsing of 32 bit
27. ister that is implemented as a 64 bit MSR The semantics of handling reserved bits are defined in Section 2 3 3 Reserved Bit Checking 2 3 2 APIC Register Address Space The MSR address range between 0000 0800H through 0000 OBFFH is architectur ally reserved and dedicated for accessing APIC registers in x2APIC mode Figure 2 2 provides the detailed list of the APIC registers in xAPIC mode and x2APIC mode The MSR address offset specified in the table is relative to the base MSR address of 800H The MMI O offset specified in the table is relative to the default base address of FEEQOOOOH There is a one to one mapping between the legacy xAPIC register MMIO offset and the MSR address offset with the following exceptions e The Interrupt Command Register ICR The two 32 bit ICR registers in xAPIC mode are merged into a single 64 bit MSR in x2API C mode The Destination Format Register DFR is not supported in x2APIC mode 2 3 LOCAL x2APIC ARCHITECTURE The SELF IPI register is available only if x2API C mode is enabled The MSR address space is compressed to allow for future growth Every 32 bit register on a 128 bit boundary in the legacy MMIO space is mapped to a single MSR in the local x2APIC MSR address space The upper 32 bits of all x2API C MSRs except for the ICR are reserved Table 2 2 Local APIC Register Address Map Supported by x2APIC MSR Offset MMIO Offset
28. isters defined in the x2APIC architec ture are accessible in the following operating modes of the processor Protected Mode Virtual 8086 Mode Real Mode and IA 32e mode both 64 bit and compati bility sub modes 2 7 X2APIC STATE TRANSITIONS This section provides a detailed description of the x2APIC states of a local x2APIC unit transitions between these states as well as interactions of these states with I NIT and RESET esl x2APIC States The valid states for a local x2APIC unit is listed in Table 2 1 e APIC disabled 1A32 APIC BASE EN 0 and 1A32 APIC BASE EXTD 0O e XAPIC mode 1A32 APIC BASEIEN1 1 and 1A32 APIC BASE EXTD O e x2APIC mode 1A32 APIC BASE EN 1 and 1A32 APIC BASE EXTD 1 e Invalid A32 APIC BASE EN 0 and 1A32_APIC_BASE EXTD 1 The state corresponding to EXTD 1 and EN 0 is not valid and it is not possible to get into this state Values written to the1A32 APIC BASE MSR that attempt a transition from a valid state to this invalid state will cause a GP fault Figure 2 9 shows the comprehensive state transition diagram for a local x2APIC unit On coming out of RESET the local x2APIC unit is enabled and is in the xAPI C mode 1A32_APIC_BASE EN 1 and 1A32_APIC_BASE EXTD 0 The APIC registers are initialized as 2 17 LOCAL x2APIC ARCHITECTURE e The local APIC ID is initialized by hardware with a 32 bit ID X2APIC ID The lowest 8 bits of the x2APIC ID is the legacy local xAPIC ID and is stored in the upper 8
29. livery to update a memory location thereby allowing the dispatching software to verify the memory location has been updated Adestination ID value of FFFF FFFFH is used for broadcast of interrupts in both logical destination and physical destination modes The Delivery Status bit of the ICR has been removed Software need not poll on the Delivery Status bit before writing the I CR e ICR reads are still allowed to aid debugging However software should not assume the value returned by reading the ICR is the last written value 2 3 5 2 Task Priority Register Semantics In x2APIC mode the layout of the Task Priority Register has the same layout as in the xAPI C mode The semantics for reading and writing to the TPR register via the MSR interface are identical to those used for TPR access via the CR8 register Specifically the write to the TPR register ensures that the result of any re prioritization action due to the change in processor priority is reflected to the processor prior to the next instruction following the TPR write Any deliverable interrupts resulting from the TPR write would be taken at the instruction boundary following the TPR write 2 3 5 3 End Of Interrupt Register Semantics In xAPIC mode the EOI register is written by an interrupt service routine to indicate that the current interrupt service has completed System software performs a write to the EOI register to signal an EOI In the x2API C mode the write of a
30. llowed for the local APIC 2 3 X2APIC MODE REGISTER INTERFACE In xAPIC mode the software model for accessing the APIC registers is through a memory mapped interface Specifically the APIC registers are mapped to a 4K Byte region in the processor s memory address space the physical address base of the 4K Byte region is specified in the 1A32 APIC BASE MSR Default value of FEEO 0000H In x2APIC mode a block of MSR address range is reserved for accessing APIC regis ters through the processor s MSR address space This section provides details of this MSR based interface 2 3 1 Instructions to Access APIC Registers In x2API C mode system software uses RDMSR and WRMSR to access the APIC regis ters The MSR addresses for accessing the x2APIC registers are architecturally defined and specified in Section 2 3 2 APIC Register Address Space Executing the RDMSR instruction with APIC register address specified in ECX returns the content of bits 0 through 31 of the APIC registers in EAX Bits 32 through 63 are returned in register EDX these bits are reserved if the APIC register being read is a 32 bit register Similarly executing the WRMSR instruction with the APIC register address in ECX writes bits O to 31 of register EAX to bits O to 31 of the specified APIC register If the register is a 64 bit register then bits 0 to 31 of register EDX are written to bits 32 to 63 of the APIC register The Interrupt Command Register is the only APIC reg
31. nd the logical xAPIC ID to support extended processor addressability The x2APIC architecture also provides two destination modes physical destination mode and logical destination mode Each logical processor in the system has a unique physical xAPIC ID which is used for targeting interrupts to that processor in physical destination mode The local APIC ID register provides the physical destina tion mode 8 bit or 32 bit ID for the processor depending on xAPIC mode or x2APIC mode Section 2 4 1 describes the 32 bit X2APIC ID in x2APIC mode Each logical processor in the system also can have a unique logical xAPIC ID which is used for targeting interrupts to that processor in logical destination mode The Logical Destination Register specified in Section 2 4 2 It contains the logical x2APIC ID for the processor in X2APIC mode 2 4 1 Local APIC ID Register In x2API C mode the local APIC ID register is increased to 32 bits wide This enables 2 32 1 processors to be addressable in physical destination mode This 32 bit value is referred to as X2APIC ID A processor implementation may choose to support less 2 10 LOCAL x2APIC ARCHITECTURE than 32 bits in its hardware System software should be agnostic to the actual number of bits that are implemented All non implemented bits will return zeros on reads by software The APIC ID value of FFFF_FFFFH and the highest value corresponding to the imple mented bit width of the local APIC I
32. nted bits return zero This is a read only register that soft ware must read to determine the logical x2APIC ID of the processor Specifically software can apply a 16 bit mask to the lowest 16 bits of the logical x2APIC ID to identify the logical address of a processor within a cluster without needing to know the number of implemented bits in cluster ID and Logical ID sub fields Similarly software can create a message destination address for cluster model by bit Oring the Logical X2APIC ID 31 0 of processors that have matching Cluster ID 31 16 To enable cluster ID assignment in a fashion that matches the system topology char acteristics and to enable efficient routing of logical mode lowest priority device inter rupts in link based platform interconnects the LDR are initialized by hardware based on the value of x2APIC ID upon x2APIC state transitions Details of this initialization are provided in Section 2 4 4 2 12 LOCAL x2APIC ARCHITECTURE 2 4 3 Interrupt Command Register In x2APIC mode the layout of the Interrupt Command Register is shown in Figure 2 5 The lower 32 bits of ICR in x2APIC mode is identical to the lower half of the ICR in xAPIC mode except bit 12 Delivery Status is not used since it is not needed in X2API C mode The destination ID field is expanded to 32 bits in X2APIC mode 63 32 Destination Field 31 2019181716 1514 1312 1110 87 0 Reserved Destination Shor
33. on 2 7 1 An INIT in this state keeps the x2APIC in the x2APIC mode The state of the local APIC ID register is preserved all 32 bits However all the other APIC registers are initialized as a result of the INIT transition 2 7 1 3 X2APIC Transitions From Disabled Mode From the disabled state the only valid x2APIC transition using A32_APIC_BASE is to the xAPIC mode EN 1 EXTD 0 Thus the only means to transition from x2APIC mode to xAPIC mode is a two step process e first transition from x2APIC mode to local APIC disabled mode EN 0 EXTD 0 followed by another transition from disabled mode to xAPIC mode EN 1 EXTD 0 Consequently all the APIC register states in the x2APIC except for the x2APIC ID 32 bits are not preserved across mode transitions 2 19 LOCAL x2APIC ARCHITECTURE A RESET in the disabled state places the x2APIC in the xAPIC mode All APIC registers including the local APIC ID register are initialized as described in Section 2 7 1 An INIT in the disabled state keeps the x2APIC in the disabled state 2 7 1 4 State Changes From xAPIC Mode to x2APIC Mode After APIC register states have been initialized by software in xAPIC mode a transi tion from xAPIC mode to x2APIC mode does not affect most of the APIC register states except the following The Logical Destination Register is not preserved Any APICID value written to the memory mapped local APIC ID register is not preserved
34. port for two modes of operation to provide backward compatibility and exten sibility for future platform innovations n xAPIC compatibility mode APIC registers are accessed through memory mapped interface to a 4K Byte page identical to the xAPIC architecture n x2APIC mode APIC registers are accessed through Model Specific Register MSR interfaces In this mode the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery Increased range of processor addressability in x2API C mode Physical xAPIC ID field increases from 8 bits to 32 bits allowing for interrupt processor addressability up to 4G 1 processors in physical destination mode A processor implementation of x2APIC architecture can support fewer than 32 bits in a software transparent fashion Logical xAPIC ID field increases from 8 bits to 32 bits The 32 bit logical x2APIC ID is partitioned into two sub fields a 16 bit cluster ID and a 16 bit logical ID within the cluster Consequently 2 20 16 processors can be addressed in logical destination mode Processor implementations can support fewer than 16 bits in the cluster ID sub field and logical ID sub field in a software agnostic fashion More efficient MSR interface to access APIC registers To enhance inter processor and self directed interrupt delivery as well as the ability to virtualize the local APIC the APIC register set can b
35. priorities interrupt sources interrupt destination types Provides extensions to scale processor addressability for both the logical and physical destination modes Adds new features to enhance performance of interrupt delivery Reduces complexity of logical destination mode interrupt delivery on link based architectures 1 2 IMPACTED PLATFORM COMPONENTS X2APIC is architected to extend from the xAPIC architecture while minimizing the impact on platform components Specifically support for the x2APIC architecture can be implemented in the local APIC unit All existing PCI MSI capable devices and VOXAPIC unit should work with the x2API C extensions defined in this document The X2APIC architecture also provides flexibility to cope with the underlying fabrics that connect the PCI devices IOxAPICs and Local APIC units The extensions provided in this specification translate into modifications to e the local APIC unit the underlying fabrics connecting Message Signaled Interrupts MSI capable PCI devices to local xAPI Cs e the underlying fabrics connecting the I OxAPICs to the local APIC units INTRODUCTION However no modifications are required to PCI or PCle devices that support direct interrupt delivery to the processors via Message Signaled Interrupts Similarly no modifications are required to the IOxAPIC The routing of interrupts from these devices in X2APIC mode leverages the interrupt remapping architecture
36. s shown in Figure 2 1 63 36 35 121110987 0 Reserved APIC Base APIC Base Base physical address EN xAPIC global enable disable EXTD Enable x2APIC mode BSP Processor is BSP Reserved Figure 2 1 1A32 APIC BASE MSR Supporting x2APIC Table 2 1 x2APIC operating mode configurations describe the possible combina tions of the enable bit EN bit 11 and the extended mode bit EXTD bit 10 in the IA32 APIC BASE MSR Table 2 1 x2APIC Operating Mode Configurations XAPIC global enable X2APIC enable IA32 APIC BASE 11 IA32 APIC BASE 10 Description local APIC is disabled Invalid local APIC is enabled in xAPIC mode 2 2 o0 o Oo o I local APIC is enabled in x2APIC mode Once the local APIC has been switched to x2APIC mode EN 1 EXTD 1 switching back to xAPI C mode would require system software to disable the local APIC unit Specifically attempting to write a value to the1A32 APIC BASE MSR that has EN 1 EXTD 0 when the local APIC is enabled and in x2API C mode will raise a GP exception Once bit 10 in1A32 APIC BASE MSR is set the only way to leave X2API C mode using 1A32 APIC BASE would require a WRMSR to set both bit 11 and 2 2 LOCAL x2APIC ARCHITECTURE bit 10 to zero Section 2 7 X2APIC STATE TRANSITIONS provides a detailed state diagram for the state transitions a
37. ter Read Write 0360H 036H LVT LINT1 Register Read Write 0370H 037H LVT Error Register Read Write 0380H 038H Initial Count Register Read Write for Timer 0390H 039H Current Count Register Read Only for Timer 03AO0H 03AH 03DH Reserved 03D0H 03E0H O3EH Divide Configuration Read Write Register for Timer Not supported 03FH SELF IPI Write only Only in x2APIC mode 040H 3FFH Reserved NOTES 1 Destination format register DFR is supported in xAPIC mode at MMIO offset OOEOH 2 APIC register at MMIO offset 0310H is accessible in xAPIC mode only 3 MSR 831H offset 31H is reserved read write operations will result in a GP fault 4 SELF IPI register is supported only if x2APIC mode is enabled 2 3 3 Reserved Bit Checking Section 2 3 2 and Table 2 2 specifies the reserved bit definitions for the APIC regis ters in X2APIC mode Non zero writes by WRMSR instruction to reserved bits to these registers will raise a general protection fault exception while reads return zeros RsvdZ semantics 2 6 LOCAL x2APIC ARCHITECTURE 2 3 4 Error Handling RDMSR and WRMSR operations to reserved addresses in the x2APIC mode will raise a GP fault Note In xAPIC mode an APIC error is indicated in the Error Status Register on an illegal register access Additionally reserved bit violations cause GP faults as detailed in Section 2 3 3 Beyond illegal register access and reserved bit violations other APIC errors are logged in Error
38. tered trade marks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation P O Box 5937 Denver CO 80217 9808 or call 1 800 548 4725 or visit Intel s website at http www intel com Copyright 2006 2010 Intel Corporation INTRODUCTION CHAPTER 1 INTRODUCTION 1 1 INTRODUCTION The xAPIC architecture provided a key mechanism for interrupt delivery in many generations of Intel processors and platforms across different market segments This document describes the x2APIC architecture which is extended from the xAPIC archi tecture the latter was first implemented on Intel Pentium 4 Processors and extended the APIC architecture implemented on Pentium and P6 processors Exten sions to the xAPIC architecture are intended primarily to increase processor addres sability The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendability for future Intel platform innovations Specifi cally x2API C Retains all key elements of compatibility to the xAPIC architecture delivery modes interrupt and processor
39. thand Delivery Mode 00 No Shorthand 000 Fixed 01 Self 001 Reserved 10 All Including Self 010 SMI 11 All Excluding Self 011 Reserved 100 NMI 101 INIT 110 Start Up Reserved 111 Reserved Unused Destination Mode 0 Physical 1 Logical Level Address 830H 63 0 0 De assert 1 Assert Value after Reset 0H Trigger Mode 0 Edge 1 Level Figure 2 5 Interrupt Command Register ICR in x2APIC Mode A single MSR write to the Interrupt Command Register is required for dispatching an interrupt in x2APIC mode With the removal of the Delivery Status bit system soft ware no longer has a reason to read the ICR It remains readable only to aid in 1 WRMSR to the ICR MSR ignores bit 12 of its source operand The value returned by RDMSR from the ICR MSR into bit 12 of its destination is undefined 2 13 LOCAL x2APIC ARCHITECTURE debugging however software should not assume the value returned by reading the ICR is the last written value A destination ID value of FFFF FFFFH is used for broadcast of interrupts in both logical destination and physical destination modes 2 4 4 Deriving Logical x2APIC ID from the Local x2APIC ID In X2APIC mode the 32 bit logical X2APIC ID which can be read from LDR is derived from the 32 bit local x2APIC ID Specifically the 16 bit logical ID sub field is derived by shifting 1 by the lowest 4 bits of the x2APIC ID i e Logical ID 1 lt lt x2A
40. the EOI broadcast if the Directed EOI capability is supported This bit is reserved to 0 if the processor doesn t support Directed EOI If SVR bit 12 is set a broadcast EOI is not generated on an EOI cycle even if the asso ciated TMR bit is indicating the current interrupt is a level triggered interrupt Layout of the Spurious Interrupt Vector Register is shown in Figure 2 7 31 12 11 987 0 Reserved EOI Broadcast Disable APIC Software Enable Disable 0 APIC Disabled 1 APIC Enabled Spurious Vector MMIO Address FEEO OOFOH MSR Address 080FH Figure 2 7 Spurious Interrupt Vector Register SVR of x2APIC The default value for SVR bit 12 is clear indicating that an EOI broadcast will be performed The support for Directed EOI capability can be detected by means of bit 24 in the Local APIC Version Register This feature is supported in both the xAPIC mode and 2 16 LOCAL x2APIC ARCHITECTURE X2APIC modes of a local x2APIC unit Layout of the Local APIC Version register is as shown in Figure 2 8 The Directed EOI feature is supported if bit 24 is set to 1 31 2524 23 16 15 8 7 0 Reserved Max LVT Entry Reserved Vector Directed EOI Support MMIO Address FEEO 0030H MSR Address 0803H Figure 2 8 Local APIC Version Register of x2APIC 2 6 INTERACTION WITH PROCESSOR CORE OPERATING MODES Similar to the xAPIC architecture the APIC reg
41. x2APIC ID into hierarchical components The detailed bit field defi nitions for CPUI D OBH leaf are shown in Table 2 4 Table 2 4 CPUID Leaf OBH Information Initial EAX Value Information Provided about the Processor CPUID leaves 3 80000000 are visible only when 1A32 MISC ENABLES BOOT NT4 bit 22 O default Extended Topology Enumeration Leaf OBH NOTE Most fields of leaf OBH output depends on the initial value in ECX EDX output do not vary with initial value in ECX ECX 7 0 output always reflect initial value in ECX All other output value for an invalid initial value in ECX are O EAX Bits 4 0 Number of bits to shift x2APIC ID right to get unique topology ID of next level type All logical processors with same next level ID share current level Bits 31 5 Reserved EBX Bits 15 00 Number of enabled logical processors at this level type The number reflects configuration as shipped by Intel Bits 31 16 Reserved ECX Bits 07 00 Level number Same value as input Bits 15 08 Level Type Bits 31 16 Reserved EDX Bits 31 0 x2APIC ID of the current logical processor 2 21 LOCAL x2APIC ARCHITECTURE Table 2 4 CPUID Leaf OBH Information Contd Initial EAX Value Information Provided about the Processor NOTES Software should use this field EAX 4 0 to enumerate processor topology of the system Software must not use EBX 15 0 to enumerate processor topolo
42. x2APIC R W XAPIC mode mode Register Name Semantics Comments 0000H 000H 001H Reserved 0010H 0020H 002H Local APIC ID Register Read only See Section 2 7 1 for initial values 0030H 003H Local APIC Version Read only Same version between Register extended and legacy modes Bit 24 is available only to an x2APIC unit in xAPIC mode and x2APIC modes See Section 2 5 1 0040H 004H 007H Reserved 0070H 0080H 008H Task Priority Register Read Write Bits 7 0 are RW Bits 31 8 TPR are Reserved 0090H OOSH Reserved OOAOH OOAH Processor Priority Read only Register PPR OOBOH OOBH EOI Register Write only O is the only valid value to write GP fault on non zero write OOCOH OOCH Reserved OODOH OODH Logical Destination Read only Read Write in xAPIC Register mode OOEOH OOEH Reserved GP fault on Read Write in x2APIC mode OOFOH OOFH Spurious Interrupt Read Write Bits 0 8 12 Read Write Vector Register other bits reserved 0100H 010H In Service Register Read Only ISR bits 0 31 0110H 011H ISR bits 32 63 Read Only 2 4 LOCAL x2APIC ARCHITECTURE Table 2 2 Local APIC Register Address Map Supported by x2APIC Contd MSR Offset MMIO Offset x2APIC R W xAPIC mode mode Register Name Semantics Comments 0120H 012H ISR bits 64 95 Read Only 0130H 013H ISR bits 96 127 Read Only 0140H 014H ISR bits 128 15
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