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Supermicro H8DCI motherboard

1. 12 Header Pin Definitions J24 Pin Definition 1 Clock 2 Data 3 PWR Fail 4 Gnd 5 Header Pin Definitions J22 Pin Definition cx Data Ground Clock No Connection H8DC8 H8DCi User s Manual CD1 Header The 4 pin CD1 header allows you to use the onboard sound for audio CD playback Connect the audio cable from your CD drive to this header See the table on the right for pin definitions AUX1 Header AUX1 is an additional different stan dard header allows you to use the on board sound for audio CD playback Connect the audio cable from your CD drive to this header See the table on the right for pin definitions 3rd Power Supply Alarm Header Connect a cable from your power supply to JP10 to provide you with warning of a power supply failure The warning signal is passed through the PWR_LED pin to indicate a power failure See the table on the right for pin definitions Alarm Reset Header Connect JAR to the alarm reset but ton on your chassis if available or to a microswitch to allow you to turn off the alarm that sounds when a power supply module fails See the table on the right for pin definitions 2 14 CD1 Pin Definitions Pin Definition Right Signal Ground Ground Left Signal Pin Definition Right Signal Ground Ground Left Signal 3rd Power Supply Alarm Header Pin Definitions
2. Chapter 2 Installation 3rd Power Supply Fail Signal Jumper Settings J3P Jumper Setting Definition Open Disabled Closed Enabled to PCI Enable Disable Jumper Settings 1 2 Jumper Setting Definition Closed Enabled Open Disabled Audio Enable Disable Jumper Settings JPAC Jumper Setting Definition Pins 1 2 Enabled Pins 2 3 Disabled H8DC8 H8DCi User s Manual Watch Dog JWD controls Watch Dog a system monitor that takes action when a soft ware application freezes the system Jumping pins 1 2 will cause WD to reset the system if an application is hung up Jumping pins 2 3 will gen erate a non maskable interrupt signal for the application that is hung up See the table on the right for jumper settings Watch Dog can also be enabled via BIOS Onboard Speaker Enable Disable The JD1 header allows you to use either an external speaker or the in ternal onboard speaker To use the internal onboard speaker close pins 6 and 7 with a jumper To use an external speaker remove the jumper and connect the speaker wires to pins 4 5V and 7 control signal See the table on the right for settings and the table associated with the Power LED Keylock Speaker connection previ ous section for pin definitions PCI X Slot Speed Jumpers JPX1B and JPX1A on the H8DC8 H8DCi can be used to change the speed of PCI X slots 2 and 3 and PCI X slot 1
3. 48h Patterns written in base memory Determining the amount of memory below 1 MB next 49h The amount of memory below 1 MB has been found and verified 4Bh The amount of memory above 1 MB has been found and verified Checking for a soft reset and clearing the memory below 1 MB for the soft reset next If this is a power on situation going to checkpoint 4Eh next B 4 Appendix B BIOS POST Checkpoint Codes Checkpoint Code Description 4Ch The memory below 1 MB has been cleared via a soft reset Clearing the memory above 1 MB next 4Dh The memory above 1 MB has been cleared via a soft reset Saving the memory size next Going to checkpoint 52h next 4Eh The memory test started but not as the result of a soft reset Displaying the first 64 KB memory size next 4Fh The memory size display has started The display is updated during the memory test Performing the sequential and random memory test next memory size for relocation and shadowing next 50h The memory below 1 MB has been tested and initialized Adjusting the displayed 51h The memory size display was adjusted for relocation and shadowing 52h The memory above 1 MB has been tested and initialized Saving the memory size information next 53h The memory size information and the CPU registers are saved Entering real mode next 54h Shutdown was successful The CPU is in real mode Disabling the Gate A20 line parity and the NMI next 57h The A20 addres
4. AC97 IDE ATA133 USB Ports 8 Parallel Port Figure 1 3 nVidia nForce Pro 2200 2050 Chipset System Block Diagram Note This is a general block diagram and may not exactly represent the features on your serverboard See the previous pages for the actual specifications of your serverboard Chapter 1 Introduction 1 2 Chipset Overview The H8DC8 H8DCi serverboard is based on the nVidia nForce Pro 2200 2050 and AMD 8132 chipset The nVidia nForce Pro 2200 2050 functions as Media and Com munications Processors MCPs and the AMD 8132 as a PCI X Tunnel Controllers for the system memory are integrated directly into the AMD Opteron processors 2200 Media and Communications Processor This MCP is a single chip high performance HyperTransport peripheral controller The 2200 includes a 20 lane PCI Express interface an AMD Opteron 16 bit Hyper Transport interface link a four port Serial ATA interface a dual ATA133 bus master interface a USB 2 0 interface and support for 32 bit PCI slots This hub connects directly to CPU 1 and the 2050 MCP The GLAN 1 port connects directly to the 2200 MCP 2050 Media and Communications Processor The 2050 is pin to pin compatible with the 2200 It includes a PCI Express inter face with 20 lanes and an AMD Opteron 16 bit Hyper Transport interface link The GLAN 2 connects directly to
5. Chapter 2 Installation Line In blue port Surround L R Line Out green port Front L R MIC pink port Center Subwoofer Audio Output Jumper Header Pin Definitions J26 Pin Definition E MIC Ground Reference voltage 5V audio Line Out right channel from board Line Out right channel to port NC Key o Oi A C Line Out left channel from board o Line Out left channel to port Notes NC indicates no connection Pins 6 and 10 are not active when a header is used for front side audio access H8DC8 H8DCi User s Manual 2 7 Jumper Settings Explanation of Jumpers To modify the operation of the 3 2 1 serverboard jumperscanbeusedto 52 between optional settings mz Jumpers create shorts between two pins to change the function of the connector Pin 1 is identified with a sguare solder pad on the printed circuit board See the diagram at rightforan example ofjumping pins 1 and 2 Refer to the serverboard layout page for jumper locations Jumper N Note Ontwo pinjumpers Closed means the jumperis on and Open means the jumper is off the pins CMOS Clear JBT1 is used to clear CMOS and will also clear any passwords Instead of pins this jumper consists of contact pads to prevent accidentally clearing the contents of CMOS To clear CMOS 1 First power down the system and unplug the power cord
6. FAN1 8 Pin Definition Ground Black 12V Red Tachometer PWM Control Notes JLAN1 is the top port and JLAN2 is the bottom port Wake On LAN from S3 S4 and S5 are supported by JLAN1 JLAN2 supports WOL from S1 only H8DC8 H8DCi User s Manual Power LED Speaker On JD1 pins 1 2 and 3 are for the power LED and pins 4 through 7 are for the speaker See the tables on the right for pin definitions Note The speaker connector pins are for use with an external speaker If you wish to use the onboard speaker you should close pins 6 and 7 with a jumper ATX PS 2 Keyboard and PS 2 Mouse Ports The ATX PS 2 keyboard and the PS 2 mouse ports are located at J101 The mouse is the top green port See the table on the right for pin definitions Chassis Intrusion A Chassis Intrusion header is located at JL1 Attach the appropriate cable to inform you of a chassis intrusion See the table on the right for pin definitions Overheat LED Connect an LED to the JOH1 header to provide warning of chassis over heating See the table on the right for pin definitions 2 12 PWR LED Connector Pin Definitions JD1 Pin Definition 1 Vcc 2 Control S Control Speaker Connector Pin Definitions JD1 Pin Definition 4 Red wire 5V No connection 5 6 Buzzer signal 7 Speaker data PS 2 Keyboard and Mouse Port Pin Definitions J101 Pin Definition
7. Uncompressing the POST code next The CMOS checksum calculation is done next OAh The CMOS checksum calculation is done Initializing the CMOS status register for date and time next OBh The CMOS status register is initialized Next performing any required initialization before the keyboard BAT command is issued OCh The keyboard controller input buffer is free Next issuing the BAT command to the keyboard controller OEh The keyboard controller BAT command result has been verified Next performing any necessary initialization after the keyboard controller BAT command test OFh The initialization after the keyboard controller BAT command test is done The key board command byte is written next 10h The keyboard controller command byte is written Next issuing the Pin 23 and 24 blocking and unblocking command 11h Next checking if lt End or lt Ins gt keys were pressed during power on Initializing CMOS RAM if the Initialize CMOS RAM in every boot AMIBIOS POST option was set in AMIBCP or the lt End gt key was pressed Next disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2 The video display has been disabled Port B has been initialized Next initializing the chipset The 8254 timer test will begin next Next programming the flash ROM The memory refresh line is toggling Checking the 15 second on off time next Passing control to the video ROM to perform any required configuration before th
8. JP10 Pin Definition P S 1 Fail Signal P S 2 Fail Signal P S 3 Fail Signal Reset from MB Note This feature is only available when using redundant power supplies Alarm Reset Header Pin Definitions JAR Pin Definition 1 Ground Reset Signal AC97 AC97 provides high quality onboard audio The H8DC8 H8DCi features 6 channel 5 1 sound for front L amp R rear L amp R center and subwoofer speakers This feature is activated with software included on the CD ROM that came with the serverboard Sound is output through the Line In Line Out and MIC jacks see at right Activate AC97 with the JPAC jumper see next section for details and the BIOS setting for the Audio Codec under South Bridge Configuration In addition there are also CD1 and AUX1 connectors on the board that can be used for audio output Audio Output Jumper Header The J26 header is used both as a jump er and a cable header Jump pins 5 6 and 9 10 to use the backpanel jacks for AC97 audio output see Figure 2 3 J26 also gives you the option of direct ing the audio output to Line In Line Out Mic jacks that may be added to the front of the chassis requires additional hardware not included See the table on the right for pin definitions Keylock Header The keyboard lock header is designat ed JK1 Utilizing this header allows you to inhibit any actions made on the keyboard effectively locking it 2 15
9. 5 Serverboard Features 2 si yasasin salar l inle 1 6 nVidia nForce Pro 2200 2050 Chipset System Block Diagram 1 8 1 2 Chipset OVOIVIOW os 1 9 1 9 PC Health MonttOrlhg iken seramik 1 10 1 4 Power Configuration Settings 1 11 1 5 MR Huyay ses 1 12 1 6 Super tee 1 13 Chapter 2 Installation 2 1 Static Sensitive Devices MAMA 2 1 2 2 Processor and Heatsink Installation 2 2 2 3 Mounting the Serverboard into a Chassis 2 4 2 4 Installing Memory i i n eer ener 2 4 2 5 I O Port and Control Panel Connections 2 7 2 6 Connecting Cables laa sala 2 8 Power Connector i alemleri 2 8 Processor Power Connector pp 2 8 AwiliaryPowerConnector A MI 2 8 Power cet ne RII ELI 2 8 Ni PEE 2 9 NICT LED DELE 2 9 2 E 2 9 Overheat Fan Fail LED 2 9 Power LED 2 10 Reset BURLON e 2 10 Power BUG 2 10 Universal Serial Bus Ports USBO 1 2 3 2 10 iv Table of Contents Extra USB Headers EE er xe Te ue Ede E 2 11 Serial uere 2 11 Br me 2 11 JEANT1 2 Ethernet Pons visi oorr rg n rhe ee ize 2 11 Power LED Speaker erred kno to hastings RR RR Sakall akla 2 12 ATX PS 2 Keyboa
10. IRQ4 and 2E8 IRQ3 Serial Port 2 Mode Tells BIOS which mode to select for serial port 2 The options are Normal IrDA and ASKIR Parallel Port Address This option specifies the I O address used by the parallel port Select Disabled to prevent the parallel port from accessing any system resources When the value of this option is set to Disabled the printer port becomes unavailable Select 378 to allow the parallel port to use 378 as its I O port address The majority of parallel ports on computer systems use and I O Port 378H as the standard setting Select 278 to allow the parallel port to use 278 as its I O port address Select 3BC to allow the parallel port to use 3BC as its I O port address Parallel Port Mode Specify the parallel port mode The options are Normal Bi directional EPP and ECP Parallel Port IRQ Select the IRQ interrupt request for the parallel port The options are IRQ5 and IRQ7 4 7 H8DC8 H8DCi User s Manual gt Advanced Chipset Control gt North Bridge Configuration gt Memory Configuration Memclock Mode This setting determines how the memory clock is set Auto has the memory clock by code and Limit allows the user to set a standard value MCT Timing Mode Sets the timing mode for memory Options are Auto and Manual User Configuration Mode Options are Auto and Manual Bank Interleaving Select Auto to automatically enable interleaving memory scheme when this function i
11. dual single channel DIMM slots supporting up to 32 GB of registered ECC DDR333 266 or up to 16 GB of registered ECC DDR400 SDRAM Note Refer to Section 2 4 before installing Chipset nVidia nForce Pro 2200 2050 AMD 8132 Expansion Slots Two 2 PCI Express x16 slots One 1 PCI Express x4 slot can support x8 cards 2 PCI X 133 100 MHz slots PCI X 100 MHz slot ZCR slot 32 bit 33 MHz PCI slot Two One 1 One 1 BIOS e 8 Mb AMIBIOS LPC Flash ROM DMI 2 3 PCI 2 2 ACPI 1 0 ACPI 2 0 is BIOS supported SMBIOS 2 3 Plug and Play PnP PC Health Monitoring Onboard voltage monitors for two CPU cores Hyper Transport 1 2V two memory banks 2 5V nVidia 2200 2050 chipset 1 5V Fan status monitor with firmware software on off and speed control Watch Dog Environmental temperature monitoring via BIOS Power up mode control for recovery from AC power loss System resource alert via included utility program Pulse Width Modulated PWM fan connectors Auto switching voltage regulator for the CPU core Thermal Monitor 2 TM2 support A single processor configuration is not recommended see notes on page 1 4 1 6 Chapter 1 Introduction ACPI Features Microsoft OnNow Slow blinking LED for suspend state indicator BIOS support for USB keyboard Main switch override mechanism Internal external modem ring on Su
12. for the resolution of any such disputes The manufacturer s total liability for all claims will not exceed the price paid for the hardware product Manual Revision 1 0b Release Date November 17 2006 Unless you request and receive written permission from the Manufacturer you may not copy any part of this document Information in this document is subject to change without notice Other products and companies referred to herein are trademarks or registered trademarks of their respective companies or mark holders Copyright 2006 All rights reserved Printed in the United States of America Preface Preface About This Manual This manual is written for system integrators PC technicians and knowledgeable PC users It provides information for the installation and use of the H8DC8 H8DCi serverboard The H8DC8 H8DCi is based on the nVidia nForce Pro 2200 2050 chipset and supports dual AMD Opteron 200 series type processors in 940 pin microPGA ZIF sockets and up to 32 GB of DDR333 or DDR266 or up to 16 GB of DDR400 registered ECC SDRAM Please refer to the serverboard specifications pages on our web site for updates on supported processors http www supermicro com aplus This product is intended to be professionally installed Manual Organization Chapter 1 includes a checklist of what should be included in your serverboard box describes the features specifications and performance of the serverboard and provides detailed
13. information about the chipset Chapter 2 begins with instructions on handling static sensitive devices Read this chapter when installing the processor s and memory modules and when installing the serverboard in a chassis Also refer to this chapter to connect the floppy and hard disk drives the parallel and serial ports the mouse and keyboard and the twisted wires for the power and reset buttons and the system LEDs If you encounter any problems see Chapter 3 which describes troubleshooting procedures for the video the memory and the setup configuration stored in CMOS For quick reference a general FAQ Frequently Asked Questions section is pro vided Instructions are also included for contacting technical support In addition you can visit our web site for more detailed information Chapter 4 includes an introduction to BIOS and provides detailed information on running the CMOS Setup utility Appendix A provides BIOS Error Beep Code Messages Appendix B lists BIOS POST Checkpoint Codes H8DC8 H8DCi User s Manual Table of Contents Preface About This Manual nase iii Manual iii Chapter 1 Introduction 1 12 TP ap 1 1 CheckllSste EN 1 1 HSDCS H8DCi Image cr tr retreat nere ge as sagas 1 3 H8DC8 H8DCi Layout 1 4 1
14. memory size check is done Displaying a soft error and checking for a password or bypassing WINBIOS Setup next B 5 H8DC8 H8DCi Users Manual Checkpoint 86h 87h Code Description The password was checked Performing any required programming before WIN BIOS Setup next The programming before WINBIOS Setup has completed Uncompressing the WINBIOS Setup code and executing the AMIBIOS Setup or WINBIOS Setup utility next Returned from WINBIOS Setup and cleared the screen Performing any necessary programming after WINBIOS Setup next The programming after WINBIOS Setup has completed Displaying the power on screen message next Programming the WINBIOS Setup options next The WINBIOS Setup options are programmed Resetting the hard disk controller next The hard disk controller has been reset Configuring the floppy drive controller next The floppy drive controller has been configured Configuring the hard disk drive controller next Initializing the bus option ROMs from C800 next See the last page of this chapter for additional information Initializing before passing control to the adaptor ROM at C800 Initialization before the C800 adaptor ROM gains control has completed The adap tor ROM check is next The adaptor ROM had control and has now returned control to BIOS POST Perform ing any required processing after the option ROM returned control Any initialization required after the option ROM test h
15. place the CPU into the socket Do not drop the CPU on the socket move the CPU horizontally or vertically or rub the CPU against the socket or against any pins of the socket which may damage the CPU and or the socket 2 2 Chapter 2 Installation 4 With the CPU inserted into the socket inspect the four corners of the CPU to make sure that it is properly installed and flush with the socket 5 Gently press the CPU socket le ver down until it locks in the plastic tab Repeat these steps to install another CPU into the CPU 2 socket Note the use of single processor only is not recommended see notes on page 1 4 Installing the Heatsink Retention Modules Two heatsink retention modules BKT 0005 and four screws are included in the retail box Once installed these are used to help attach the heatsinks to the CPUs To install position the module so that the CPU backplate standoffs insert through the holes on the heatsink retention module and the four feet on the module contact the serverboard Secure the retention module to the backplate with two of the screws provided See Figure 2 1 Repeat for the second CPU socket Note BKT 0005 is included for use with non proprietary heatsinks only When installing Supermicro heatsinks only BKT 0004 CPU backplate is needed The BKT 0005 retention module was designed to provide compatibility with clip and cam type heatsinks from third parties Figure 2 1 CPU Backplate Heatsink
16. the CPU will wake up and the LED will automatically stop blinking and remain on BIOS Support for USB Keyboard If a USB keyboard is the only keyboard in the system it will function like a normal keyboard during system boot up Main Switch Override Mechanism When an ATX power supply is used the power button can function as a system suspend button When the user depresses the power button the system will enter a SoftOff state The monitor will be suspended and the hard drive will spin down Depressing the power button again will cause the whole system to wake up Dur ing the SoftOff state the ATX power supply provides power to keep the required circuitry in the system alive In case the system malfunctions and you want to turn off the power just depress and hold the power button for 4 seconds The power will turn off and no power will be provided to the serverboard Wake On LAN JWOL Wake On LAN is defined as the ability of a management application to remotely power up a computer that is powered off Remote PC setup up dates and access tracking can occur after hours and on weekends so that daily LAN traffic is kept to a minimum and users are not interrupted The serverboard has a 3 pin header JWOL to connect to the 3 pin header on a Network Interface Card NIC that has WOL capability Wake On LAN must be enabled in BIOS Note that Wake On LAN can only be used with an ATX 2 01 or above compliant power supply 1 11 H8DC8 H8DCi
17. tray by aligning the serverboard mounting holes with the raised metal standoffs in the tray Insert screws into all the mounting holes in the serverboard that line up with the standoffs Then use a screwdriver to secure the serverboard to the mainboard tray tighten until just snug if too tight you might strip the threads Metal screws provide an electrical contact to the serverboard ground to provide a continuous ground for the system 2 4 Installing Memory CAUTION Exercise extreme care when installing or removing memory modules to prevent any possible damage 1 Insert each memory module vertically into its slot paying attention to the notch along the bottom of the module to prevent inserting the module incorrectly see Figure 2 2 See support information below 2 Gently press down on the memory module until it snaps into place Note each processor has its own built in memory controller 128 MB 256 MB 512 MB 1 GB 2 GB and 4 GB memory modules are supported It is highly rec ommended that you remove the power cord from the system before installing or changing any memory modules Chapter 2 Installation Support The H8DC8 H8DCi supports single or dual channel registered ECC DDR400 333 266 SDRAM Both interleaved and non interleaved memory are supported so you may populate any number of DIMM slots see note on previous page and charts on following page Populating two adjacent slots at a time with memory modules
18. upside down No Power 1 Make sure that no short circuits exist between the serverboard and the chas sis 2 Verify that all jumpers are set to their default positions 3 Check that the 115V 230V switch on the power supply is properly set 4 Turn the power switch on and off to test the system 5 The battery on your serverboard may be old Check to verify that it still supplies 3VDC If it does not replace it with a new one No Video 1 If the power is on but you have no video remove all the add on cards and cables 2 Use the speaker to determine if any beep codes exist Refer to Appendix A for details on beep codes 3 1 H8DC8 H8DCi User s Manual NOTE If you are a system integrator VAR or OEM a POST diagnostics card is recommended For I O port 80h codes refer to App Memory Errors 1 Make sure that the DIMM modules are properly and fully installed 2 You should be using registered ECC DDR memory see next page Also it is recommended that you use the same memory type and speed for all DIMMs in the system See Section 2 4 for memory details and limitations 3 Check for bad DIMM modules or slots by swapping modules between slots and noting the results 4 Check the power supply voltage 115V 230V switch Losing the System s Setup Configuration 1 Make sure that you are using a high quality power supply A poor quality power supply may cause the system to lose the CMOS setup information Ref
19. 1 Data NC Ground 2 9 4 VCC 5 Clock 6 Chassis Intrusion Pin Definitions JL1 Pin Definition 1 Battery voltage Intrusion signal Overheat LED Pin Definitions JOH1 Pin Definition 1 3 3V 2 OH Active Wake On LAN The Wake On LAN header is desig nated JWOL See the table on the right for pin definitions You must have a LAN card with a Wake On LAN connector and cable to use the Wake On LAN feature Note Wake On LAN from S3 S4 S5 are supported by LAN1 LAN2 sup ports Wake On LAN from S1 only Wake On Ring The Wake On Ring header is desig nated JWOR This function allows your computer to receive and wake up by an incoming call to the modem when in suspend state See the table on the right for pin definitions You must have a Wake On Ring card and cable to use this feature Header The header at J24 is for which may be used to monitor the status of the power supply fans and system temperature See the table on the right for pin definitions SMBus Header The header at J22 is for the System Management Bus Connect the ap propriate cable here to utilize SMB on the system See the table on the right for pin definitions 2 13 Chapter 2 Installation Wake On LAN Pin Definitions JWOL Pin o Definition 1 5V Standby 2 Ground Wake up Wake On Ring Pin Definitions JWOR Pin Definition 1 Ground Black Wake up
20. 3 3V primary power supply con nector J1B4 meets the SSI Super Set ATX 24 pin specification Refer to the table on the right for the pin defini tions of the ATX 24 pin power connec tor This connection supplies power to the chipset fans and memory 12V 3 3V COM COM PS ON 5V COM COM COM Res NC Note You must also connect the 8 pin JPW2 and 4 pin J32 power connectors to your power supply see below EN 5V 5V 5V Processor Power Connector Processor Power Connector In addition to the primary ATX power connector above the 12v 8 pin processor power connector at JPW2 must also be connected to your power supply This connection supplies power to the CPUs See the table on the right for pin definitions Auxiliary Power Connector The 4 pin auxiliary power connector at 432 must also be connected to your power supply This connection sup plies extra power that may be needed for high loads See the table on the right for pin definitions Power LED The Power LED connection is located on pins 15 and 16 of JF1 Refer to the table on the right for pin definitions 2 8 Pin Definitions JPW2 Pins Definition 1 through 4 Ground 5 through 8 12V Required Connection Auxiliary Power Connector Pin Definitions J32 Pins Definition 1 amp 2 Ground 3 amp 4 12V Pin Definitions JF1
21. ACK 25 RST 59 RST 26 MSG 60 MSG 27 SEL 61 SEL 28 C D 62 C D 29 REQ 63 REQ 30 64 31 DB 8 65 DB 8 32 DB 9 66 DB 9 33 DB 10 67 DB 10 34 DB 11 68 DB 11 2 24 Chapter 3 Troubleshooting Chapter 3 Troubleshooting 3 1 Troubleshooting Procedures Use the following procedures to troubleshoot your system If you have followed all of the procedures below and still need assistance refer to the Technical Support Procedures and or Returning Merchandise for Service section s in this chapter Always disconnect the AC power cord before adding changing or installing any hardware components Before Power On 1 Check that the 3 3V standby power LED is lit DP1 on the serverboard 2 Make sure that the main ATX power connector at J1B4 the 8 pin connector at JPW2 and the 4 pin connecor at J32 are all connected to your power supply 3 Make sure that no short circuits exist between the serverboard and chassis 4 Disconnect all ribbon wire cables from the serverboard including those for the keyboard and mouse 5 Remove all add on cards 6 Install a CPU and heatsink making sure it is fully seated and connect the in ternal chassis speaker and the power LED to the serverboard Check all jumper settings as well 7 Use the correct type of onboard CMOS battery as recommended by the manufac turer To avoid possible explosion do not install the CMOS battery
22. BIOS POST Checkpoint Codes pp B 1 vi Chapter 1 Introduction 1 1 Chapter 1 Introduction Overview Checklist Congratulations on purchasing your computer serverboard from an acknowledged leader in the industry Our boards are designed with the utmost attention to detail to provide you with the highest standards in quality and performance Please check that the following items have all been included with your serverboard If anything listed here is damaged or missing contact your retailer Included with retail box only One 1 H8DC8 H8DCi serverboard One 1 IDE cable CBL 036 One 1 floppy cable CBL 022 One 1 USB 2 0 port cable CBL 083 Two 2 SATA cables CBL 044 One 1 SCSI cable H8DC8 only CBL 034 U320 Two 2 CPU backplates BKT 0004 Two 2 heatsink retention modules with four 4 screws BKT 0005 One 1 I O shield for chassis CSE PT53 One 1 CD containing drivers and utilities 1 1 H8DC8 H8DCi User s Manual Contacting Supermicro Headquarters Address SuperMicro Computer Inc 980 Rock Ave San Jose CA 95131 U S A Tel 1 408 503 8000 Fax 1 408 503 8008 Email marketing supermicro com General Information support supermicro com Technical Support Web Site www supermicro com Europe Address SuperMicro Computer B V Het Sterrenbeeld 28 5215 ML s Hertogenbosch The Netherlands Tel 31 0 73 6400390 Fax 31 0 73 6416525 Email sale
23. CPU2 DIMM 2A JC2 CPU2 DIMM 2B FAN2 Line In Out CPU2 DIMM 1A JC1 Mic CPU2 DIMM 1B FAN7 CPU1 Fan FANS x4 PCI Express 7 J26 Slot 6 x16 PCI Express nForce Pro 2200 eu nForce Pro 2050 1 CK8 04 Slot 5 PCI 33 MHz 10 4 u Slot 4 x16 PCI Express c JPA3 Slot 3 PCI X 133 100 MHz 1 7 1 2C2 C 2662 8132 Adaptec ee Slot 2 PCI X 133 100 MHz AIC 7902 x lt J13 __ speaker Slot 1 PCI X 100 MHz 2 DA1 JPA2 J22 JPX1A Bios WD USB6 7 USB4 5 JPA1 AUX 601 SATAO SATA1 SATA2 SATA3 JB2 JWOL JK1 JWOR JOH1 JL1 JD1 PwrLED Spkr Notes 1 Jumpers not indicated are for test purposes only 2 The H8DCi has the same layout as the H8DC8 but with no SCSI components con nectors or jumpers 3 Dual processors are required for the nForce 2050 104 to function properly otherwise PCI Express slots 4 and 7 and onboard LAN2 will not work 4 Wake On LAN from S3 S4 and S5 are supported by JLAN1 JLAN2 supports Wake On LAN from S1 only 1 4 Jumpers J13 J26 J3P JBT1 JI2C1 2 JPA1 JPA2 JPA3 JPAC JPX1A JPX1B JWD Connectors AUX1 CD1 COM1 COM2 FAN 1 8 JIDE 1 JIDE 2 J1B4 J4 J22 J24 J32 JA1 JAR JB2 JC1 JC2 JD1 JF1 JFDD1 JK1 JL1 JLAN1 2 JOH1 JPW2 JWOL JWOR SATAO 3 05 0 1 2 3 USB4 5 05 6 7 De
24. EL key to enter the setup utility The options are Enabled and Disabled Onboard SCSI RAID Enable to activate the onboard SCSI RAID The options are Enabled and Dis abled 4 16 Chapter 4 BIOS Interrupt 19 Capture Enable to allow ROMs to trap Interrupt 19 The options are Enabled and Dis abled gt Boot Device Priority This feature allows the user to prioritize the sequence for the Boot Device The devices to set are 1st Boot Device 2nd Boot Device 3rd Boot Device 4th Boot Device gt Hard Disk Drives This feature allows the user to specify the boot sequence from available hard disk drives 1st Drive Specifies the boot sequence for the 1st Hard Drive gt Removable Drives This feature allows the user to specify the Boot sequence from available remov able drives 1st Drive Specifies the boot sequence for the 1st Removable Drive The options are 1st Floppy Drive and Disabled gt CD DVD Drives This feature allows the user to specify the Boot sequence from available CD DVD drives OS Installation Change this setting if using a 64 bit Linux operating system The available options are Other and 64 bit Linux 2 6 9 H8DC8 H8DCi User s Manual 4 5 Security Menu AMI BIOS provides a Supervisor and a User password If you use both passwords the Supervisor password must be set first Change Supervisor Password Select this option and press lt Enter gt to access the sub menu and t
25. H8DC8 USER S MANUAL Revision 1 0b The information in this Users Manual has been carefully reviewed and is believed to be accurate The vendor assumes no responsibility for any inaccuracies that may be contained in this document makes no commitment to update or to keep current the information in this manual or to notify any person or organization of the updates Please Note For the most up to date version of this manual please see our web site We reserve the right to make changes to the product described in this manual at any time and without notice This product including software if any and documentation may not in whole or in part be copied photocopied reproduced translated or reduced to any medium or machine without prior written consent IN NO EVENT WILL THE MANUFACTURER BE LIABLE FOR DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES PARTICULAR THE VENDOR SHALL NOT HAVE LIABILITY FOR ANY HARDWARE SOFTWARE OR DATA STORED OR USED WITH THE PRODUCT INCLUDING THE COSTS OF REPAIRING REPLACING INTEGRATING INSTALLING OR RECOVERING SUCH HARDWARE SOFTWARE OR DATA Any disputes arising between manufacturer and customer shall be governed by the laws of Santa Clara County in the State of California USA The State of California County of Santa Clara shall be the exclusive venue
26. Power Fail LED The Power Fail LED connection is Pin Definitions JF1 located on pins 5 and 6 of JF1 Refer to the table on the right for pin defini Pin Definition 5 Vcc tions This feature is only available 6 Control for systems with redundant power supplies Reset Button Reset Button The Reset Button connection is lo Pin Definitions JF1 cated on pins 3 and 4 of JF1 Attach Pin Definition it to the hardware reset switch on the 3 Reset computer case Refer to the table on 4 Ground the right for pin definitions Power Button The Power Button connection is located on pins 1 and 2 of JF1 Mo mentarily contacting both pins will Power Button power on off the system This button Pin Definitions JF1 can also be configured to function Pin Definition as a suspend button see the Power 1 PW ON Button Mode setting in BIOS To turn 2 Ground off the power when set to suspend mode depress the button for at least 4 seconds Refer to the table on the right for pin definitions Universal Serial Bus Ports Pin Definitions USB0 1 2 3 Universal Serial Bus Ports 05 0 1 2 3 05 0 05 1 Pin Definition Pin Definition Four Universal Serial Bus ports 1 5V 1 5V USB2 0 are located beside the key 2 2 board mouse ports See the table on 3 PO 3 PO the right for pin definitions 4 4 Gund 2 10 Extra USB Headers Four additional
27. ROM control has completed Displaying the system configuration next Uncompressing the DMI data and executing DMI POST initialization next Copying any code to specific areas The system configuration is displayed Code copying to specific areas is done Passing control to INT 19h boot loader next B 7 H8DC8 H8DCi User s Manual Notes B 8
28. Required Connection Power LED Pin Definition 15 Vcc 16 Control HDD LED The HDD IDE Hard Disk Drive LED connection is located on pins 13 and 14 of JF1 Attach the IDE hard drive LED cable to display disk activity Refer to the table on the right for pin definitions NIC1 LED The NIC1 Network Interface Control ler LED connection is located on pins 11 and 12 of JF1 Attach the NIC1 LED cable to display network activity Refer to the table on the right for pin definitions NIC2 LED The NIC2 Network Interface Control ler LED connection is located on pins 9 and 10 of JF1 Attach the NIC2 LED cable to display network activity Refer to the table on the right for pin definitions Overheat Fan Fail LED Connect an LED to the OH connection on pins 7 and 8 of JF1 to provide ad vanced warning of chassis overheat ing Refer to the table on the right for pin definitions and status indicators Chapter 2 Installation HDD LED Pin Definitions JF1 Pin Definition 14 HD Active NIC1 LED Pin Definitions JF1 Pin Definition 11 veo 12 NIC1 Active NIC2 LED Pin Definitions JF1 Pin Definition 9 Vcc 10 NIC2 Active OH Fan Fail LED OH Fan Fail Pin Definitions JF1 LED Status JF1 Pin Definition State Indication 7 Vcc Solid Overheat 8 Control Blinking Fan fail 2 9 H8DC8 H8DCi User s Manual Power Fail LED
29. Retention Module Installation Mounting screw Mounting screw 1 Heatsink retention module Serverboard 1 Peel off release paper CPU backplate Installing the Heatsink We recommend the use of active type heatsinks except for 1U systems Use the Fan7 header for the CPU1 fan and the Fan8 header for the CPU2 fan due to fan monitoring and wiring considerations To install the heatsinks please follow the installation instructions included with your heatsink package not included 2 3 H8DC8 H8DCi User s Manual 2 3 Mounting the Serverboard into a Chassis All serverboards and motherboards have standard mounting holes to fit different types of chassis Make sure that the locations of all the mounting holes for both the serverboard and the chassis match Although a chassis may have both plastic and metal mounting fasteners metal ones are highly recommended because they ground the serverboard to the chassis Make sure that the metal standoffs click in or are screwed in tightly 1 Check the compatibility of the serverboard ports and the I O shield The H8DC8 H8DCi serverboard requires a chassis that can support extended ATX boards of 12 x 13 05 in size Make sure that the I O ports on the serverboard align with their respective holes in the I O shield at the rear of the chassis 2 Mounting the serverboard onto the mainboard tray in the chassis Carefully mount the serverboard onto the mainboard
30. USB2 0 headers USB4 5 and USB6 7 are included on the serverboard These may be con nected to provide front side access A USB cable not included is needed for the connection See the table on the right for pin definitions Serial Ports The COM1 and 2 serial ports are located under the parallel port Refer to Figure 2 3 for locations and the table on the right for pin definitions Fan Headers The H8DC8 H8DCi has eight fan headers which are designated FAN1 through FANS Fans are Pulse Width Modulated PWM and their speed is controlled via Thermal Management with a BIOS setting See the table on the right for pin definitions Note when using active heatsinks those with fans connect the heatsink fan for CPU1 to the FAN7 header and the heatsink fan for CPU2 to the FAN8 header JLAN1 2 Ethernet Ports Two Gigabit Ethernet ports desig nated JLAN1 and JLAN2 are located beside the COM2 port These Ether net ports accept RJ45 type cables 2 11 Chapter 2 Installation Extra Universal Serial Bus Headers Pin Definitions USB4 5 6 7 USB2 USB3 4 Pin Definition Pin Definition 1 5V 1 5V 2 PO 2 PO 3 PO 3 PO 4 Ground 4 Ground 5 5 No connection Serial Port Pin Definitions COM1 COM2 Pin Definition Pin Definition 1 DCD 6 DSR 2 RXD 7 RTS S TXD 8 CTS 4 DTR 9 RI 5 Ground 10 NC Note NC indicates no connection Fan Header Pin Definitions
31. User s Manual Wake On Ring Header JWOR Wake up events can be triggered by a device such as the external modem ringing when the system is in the SoftOff state Note that external modem ring on can only be used with an ATX 2 01 or above compliant power supply 1 5 Power Supply As with all computer products a stable power source is necessary for proper and reliable operation It is even more important for processors that have high CPU clock rates of 1 GHz and faster The H8DC8 H8DCi accommodates 12V ATX power supplies Although most power supplies generally meet the specifications required by the CPU some are inad equate A 2 amp current supply on a 5V Standby rail is strongly recommended It is strongly recommended that you use a high quality power supply that meets 12V ATX power supply Specification 1 1 or above Additionally in areas where noisy power transmission is present you may choose to install a line filter to shield the computer from noise It is recommended that you also install a power surge protector to help avoid problems caused by power surges Warning To prevent the possibility of explosion do not use the wrong type of onboard CMOS battery or install it upside down Chapter 1 Introduction 1 6 Super I O The disk drive adapter functions of the Super I O chip include a floppy disk drive controller that is compatible with industry standard 82077 765 a data separator write pre compensation circuitry de
32. as completed Configuring the timer data area and printer base address next Set the timer and printer base addresses Setting the RS 232 base address next Returned after setting the RS 232 base address Performing any required initializa tion before the Coprocessor test next Required initialization before the Coprocessor test is over Initializing the Coproces sor next Coprocessor initialized Performing any required initialization after the Coproces sor test next Initialization after the Coprocessor testis complete Checking the extended keyboard keyboard ID and Num Lock key next Issuing the keyboard ID command next Displaying any soft errors next The soft error display has completed Setting the keyboard typematic rate next The keyboard typematic rate is set Programming the memory wait states next Memory wait state programming is over Clearing the screen and enabling parity and the NMI next NMl and parity enabled Performing any initialization required before passing control to the adaptor ROM at E000 next Initialization before passing control to the adaptor ROM at E000h completed Passing control to the adaptor ROM at E000h next B 6 Checkpoint A9h Aah Abh BOh Bih 00h Appendix B BIOS POST Checkpoint Codes Code Description Returned from adaptor ROM at E000h control Performing any initialization required after the E000 option ROM had control next Initialization after E000 option
33. by a Legacy ISA device The options are Available and Reserved DMA Channel 0 Channel 1 Channel 3 Channel 5 Channel 6 Channel 7 Select Available to indicate that a specific DMA channel is available to be used by a PCI PnP device Select Reserved if the DMA channel specified is reserved for a Legacy ISA device The options are Available and Reserved Reserved Memory Size This feature specifies the size of memory block to be reserved for Legacy ISA devices The options are Disabled 16K 32K and 64K 4 6 Chapter 4 BIOS gt Super IO Configuration Serial Port1 Address This option specifies the base I O port address and Interrupt Request address of serial port 1 Select Disabled to prevent the serial port from accessing any system resources When this option is set to Disabled the serial port physically becomes unavailable Select 3F8 IRQ4 to allow the serial port to use 3F8 as its I O port address and IRQ 4 for the interrupt address The options are Disabled 3F8 IRQ4 3E8 IRQ4 and 2E8 IRQ3 Serial Port2 Address This option specifies the base I O port address and Interrupt Request address of serial port 2 Select Disabled to prevent the serial port from accessing any system resources When this option is set to Disabled the serial port physically becomes unavailable Select 2F8 IRQ3 to allow the serial port to use 2F8 as its I O port address and IRQ 3 for the interrupt address The options are Disabled 2F8 IRQ3 3E8
34. code logic data rate selection a clock genera tor drive interface control logic and interrupt and DMA logic The wide range of functions integrated onto the Super I O greatly reduces the number of components required for interfacing with floppy disk drives The Super I O supports two 360 K 720 K 1 2 M 1 44 M or 2 88 M disk drives and data transfer rates of 250 Kb s 500 Kb s or 1 Mb s It also provides two high speed 16550 compatible serial communication ports UARTs one of which supports serial infrared communication Each UART in cludes a 16 byte send receive FIFO a programmable baud rate generator complete modem control capability and a processor interrupt system Both UARTs provide legacy speed with baud rate of up to 115 2 Kbps as well as an advanced speed with baud rates of 250 K 500 K or 1 Mb s which support higher speed modems The Super I O supports one PC compatible printer port SPP Bi directional Printer Port BPP Enhanced Parallel Port EPP or Extended Capabilities Port ECP The Super I O provides functions that comply with ACPI Advanced Configuration and Power Interface which includes support of legacy and ACPI power manage ment through a SMI or SCI function pin It also features auto power management to reduce power consumption The IRQs DMAs and I O space resources of the Super I O can be flexibly adjusted to meet ISA PnP requirements which support ACPI and APM Advanced Power Management H8DC8 H8DC
35. data transfer rate of 8 3 MBs Select 3 to allow AMI BIOS to use PIO mode 3 It has a data transfer rate of 11 1 MBs Select 4 to allow AMI BIOS to use PIO mode 4 It has a data transfer rate of 16 6 MBs This setting generally works with all hard disk drives manufactured after 1999 For other disk drives such as IDE CD ROM drives check the specifications of the drive 4 3 H8DC8 H8DCi User s Manual DMA Mode Selects the DAM Mode Options are SWDMAO SWDMA1 SWDMA2 MWDMAO MDWDMA1 MWDMA2 UDMAO UDMA1 UDMA2 UDMAS UDMA4 and UDMAS SWDMA Single Word DMA MWDMA Multi Word DMA UDMA UltraDMA S M A R T Self Monitoring Analysis and Reporting Technology SMART can help predict impending drive failures Select Auto to allow BIOS to auto detect hard disk drive support Select Disabled to prevent AMI BIOS from using the S M A R T Select Enabled to allow AMI BIOS to use the S M A R T to support hard drive disk The options are Disabled Enabled and Auto 32 Bit Data Transfer Select Enabled to activate the function of 32 Bit data transfer Select Disabled to deactivate the function The options are Enabled and Disabled Hard Disk Write Protect Select Enabled to enable the function of Hard Disk Write Protect to prevent data from being written to HDD The options are Enabled or Disabled IDE Detect Time Out Sec This feature allows the user to set the time out value for detecting ATA ATA PI devices installed in
36. de and 5 Super Quiet Mode FAN1 Speed through FAN8 Speed The speeds of the onboard fans in rpm are displayed here FAN7 is intended to be used for the CPU1 heatsink fan and FAN8 is intended to be used for the CPU2 heatsink fan 4 15 H8DC8 H8DCi User s Manual 4 4 Boot Menu This feature allows the user to configure the following items gt Boot Settings Configuration Quick Boot If Enabled this option will skip certain tests during POST to reduce the time needed for the system to boot up The options are Enabled and Disabled Quiet Boot If Disabled normal POST messages will be displayed on boot up If Enabled this display the OEM logo instead of POST messages Add On ROM Display Mode This setting controls the display of add on ROM read only memory messages Select Force BIOS to allow the computer system to force a third party BIOS to display during system boot Select Keep Current to allow the computer system to display the BIOS information during system boot Boot up Num Lock Set this to On to allow the Number Lock setting to be modified during boot up The options are On and Off PS 2 Mouse Support This setting is to specify PS 2 mouse support The options are Auto Enabled and Disabled Wait for F1 If Error Enable to activate the Wait for F1 if Error function The options are Enabled and Disabled Hit DEL Message Display Enable to display the message telling the user to hit the D
37. e video ROM test All necessary processing before passing control to the video ROM is done Look ing for the video ROM next and passing control to it The video ROM has returned control to BIOS POST Performing any required pro cessing after the video ROM had control Reading the 8042 input port and disabling the MEGAKEY Green PC feature next Making the BIOS code segment writable and performing any necessary configura tion before initializing the interrupt vectors The configuration required before interrupt vector initialization has completed In terrupt vector initialization is about to begin B 3 H8DC8 H8DCi User s Manual Checkpoint Code Description 25h Interrupt vector initialization is done Clearing the password if the POST DIAG switch is on 27h Any initialization before setting video mode will be done next 28h Initialization before setting the video mode is complete Configuring the mono chrome mode and color mode settings next 2Ah Bus initialization system static output devices will be done next if present See the last page for additional information 2Eh Completed post video ROM test processing If the EGA VGA controller is not found performing the display memory read write test next 2Fh The EGA VGA controller was not found The display memory read write test is about to begin 30h The display memory read write test passed Look for retrace checking next 31h The display memory read write
38. ed 2 20 13 dg e 2 20 SCSlI Activity LEDS kesisi aaa kl rel ARR anana 2 20 2 9 Floppy IDE Parallel Port SCSI and SATA Drive Connections 2 21 ener creer rer E e 2 21 2 22 H8DC8 H8DCi User s Manual Parallel Port Connector 2 23 SATA CONNE CIOS ne 2 23 SCSI E 2 24 Chapter 3 Troubleshooting 3 1 Troubleshooting 3 1 Before Power OT PE 3 1 T sala ay 3 1 VIGGO Mc ee re ede 3 1 Memory inco i e E 3 2 Losing the System s Setup Configuration 3 2 3 2 Technical Support Procedures 3 2 3 3 Frequently Asked Questions pp 3 3 3 4 Returning Merchandise for Service pp 3 4 Chapter 4 BIOS e 1 ERE 4 1 4 2 Menu ea 4 2 4 3 Advanced Settings Menu RN 4 2 4 4 Boot 4 16 4 5 SBCUrity Mu IER 4 18 4 6 2 1 2 0 002000000000000000000000000 4 19 Appendices Appendix A BIOS Error Beep Codes RN A 1 Appendix B
39. efinitions of the parallel printer port SATA Ports There are no jumpers to con figure the SATA ports which are designated SATAO through SATA3 See the table on the right for pin definitions 2 23 Parallel Port Connector Definition Strobe Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 ACK BUSY PE Pin Definitions SATAO SATA3 Pin Definitions Definition Auto Feed Error Init SLCT IN GND GND GND GND GND GND Write Data Write Gate NC SATA Ports Pin 1 Nm Definition Ground TXP TXN Ground RXN RXP Ground H8DC8 H8DCi Users Manual SCSI Connectors Ultra320 SCSI Connectors H8DC8 only Pin Definitions JA1 JB2 Pin Definition Pin Definition Refer to the table at right for 1 DB 12 35 DB 12 definitions for the Ultra320 2 DB 13 36 DB 13 SCSI connectors located at 3 DB 14 37 DB 14 JA1 and JB2 4 DB 15 38 DB 15 5 DB P1 39 DB P1 6 DB 0 40 DB 0 7 DB 1 41 DB 1 8 DB 2 42 DB 2 9 DB 3 43 DB 3 10 DB 4 44 DB 4 11 DB 5 45 DB 5 12 DB 6 46 DB 6 13 DB 7 47 DB 7 14 DB P 48 DB P 15 Ground 49 Ground 16 DIFFSENS 50 Ground 17 TERMPWR 51 TERMPWR 18 TERMPWR 52 TERMPWR 19 Reserved 53 Reserved 20 Ground 54 Ground 21 ATN 55 ATN 22 Ground 56 Ground 23 BSY 57 BSY 24 ACK 58
40. er PCI Express 4 10 Chapter 4 BIOS gt Configuration gt General APCI Configuration Suspend Mode Select the mode used for the system suspend state Options are S1 POS S3 STR and Auto POS Power Off Standby STR Suspend to RAM gt Advanced ACPI Configuration ACPI 2 0 Features Yes enables RSDP pointers to 64 bit fixed system description pages Op tions are Yes and No ACPI APIC Support Select Enabled to allow the ACPI APIC table pointer to be included in the RSDP pointer list The options are Enabled and Disabled ACPI SRAT Table Use this setting the Enable or Disable the building of an SRAT Table AMI OEMB Table When Enabled tells BIOS to include the OEMB table pointer to R X SDT pointer lists Options are Enabled and Disabled Headless Mode Enable this setting to activate the Headless Operation Mode through ACPI The options are Enabled and Disabled 4 11 H8DC8 H8DCi User s Manual gt Power Menu Power Button Mode Allows the user to change the function of the power button Options are On Off and Suspend Restore on AC Power Loss This setting allows you to choose how the system will react when power returns after an unexpected loss of power The options are Power Off Power On and Last State Watch Dog Timer This setting is used to Enable or Disable the Watch Dog Timer function It must be used in conjunction with the Watch Dog jumper see Chapter 2 fo
41. er to Sec tion 1 6 for details on recommended power supplies 2 The battery on your serverboard may be old Check to verify that it still supplies 3VDC If it does not replace it with a new one 3 If the above steps do not fix the setup configuration problem contact your vendor for repairs 3 2 Technical Support Procedures Before contacting Technical Support please take the following steps Also note that as a serverboard manufacturer we do not sell directly to end users so it is best to first check with your distributor or reseller for troubleshooting services They should know of any possible problem s with the specific system configuration that was sold to you 1 Please review the Troubleshooting Procedures and Frequently Asked Questions FAQs sections in this chapter or see the FAQs on our web site before contacting Technical Support 2 BIOS upgrades can be downloaded from our web site Note Not all BIOS can be flashed depending on the modifications to the boot block code Chapter 3 Troubleshooting 3 If you still cannot resolve the problem include the following information when contacting us for technical support e X Serverboard model and PCB revision number e BIOS release date version this can be seen on the initial display when your system first boots up e System configuration An example of a Technical Support form is posted on our web site 4 Distributors For immediate assistance plea
42. hen type in the password Change User Password Select this option and press lt Enter gt to access the sub menu and then type in the password Boot Sector Virus Protection This option is near the bottom of the Security Setup screen Select Disabled to deactivate the Boot Sector Virus Protection Select Enabled to enable boot sector protection When Enabled AMI BIOS displays a warning when any program or virus issues a Disk Format command or attempts to write to the boot sector of the hard disk drive The options are Enabled and Disabled 4 18 Chapter 4 BIOS 4 6 Exit Menu Select the Exit tab from AMI BIOS Setup Utility screen to enter the Exit BIOS Setup screen Save Changes and Exit When you have completed the system configuration changes select this option to leave BIOS Setup and reboot the computer so the new system configuration parameters can take effect Select Save Changes and Exit from the Exit menu and press lt Enter gt Discard Changes and Exit Select this option to quit BIOS Setup without making any permanent changes to the system configuration and reboot the computer Select Discard Changes and Exit from the Exit menu and press lt Enter gt Discard Changes Select this option and press lt Enter gt to discard all the changes and return to AMI BIOS Utility Program Load Optimal Defaults To set this feature select Load Optimal Defaults from the Exit menu and press lt Enter gt Then Selec
43. hird Fouth Fifth Sixth IDE Master Slave Highlight one of the items above and press lt Enter gt to access the submenu for that item Type Select the type of device connected to the system The options are Not Installed Auto CDROM and ARMD LBA Large Mode LBA Logical Block Addressing is a method of addressing data on a disk drive The options are Disabled and Auto Block Multi Sector Transfer Block mode boosts IDE drive performance by increasing the amount of data transferred Only 512 bytes of data can be transferred per interrupt if block mode is not used Block mode allows transfers of up to 64 KB per interrupt Select Disabled to allow the data to be transferred from and to the device one sec tor at a time Select Auto to allows the data transfer from and to the device occur multiple sectors at a time if the device supports it The options are Auto and Disabled PIO Mode PIO Programmable mode programs timing cycles between the IDE drive and the programmable IDE controller As the PIO mode increases the cycle time decreases The options are Auto 0 1 2 3 and 4 Select Auto to allow AMI BIOS to auto detect the PIO mode Use this value if the IDE disk drive support cannot be determined Select 0 to allow AMI BIOS to use PIO mode 0 It has a data transfer rate of 3 3 MBs Select 1 to allow AMI BIOS to use PIO mode 1 It has a data transfer rate of 5 2 MBs Select 2 to allow AMI BIOS to use PIO mode 2 It has a
44. i Users Manual Notes Chapter 2 Installation Chapter 2 Installation 2 1 Static Sensitive Devices Electrostatic Discharge ESD can damage electronic components To prevent dam age to your system board it is important to handle it very carefully The following measures are generally sufficient to protect your equipment from ESD Precautions Use a grounded wrist strap designed to prevent static discharge Touch a grounded metal object before removing the board from the antistatic bag Handle the board by its edges only do not touch its components peripheral chips memory modules or gold contacts When handling chips or modules avoid touching their pins e Put the serverboard and peripherals back into their antistatic bags when not in use For grounding purposes make sure your computer chassis provides excellent conductivity between the power supply the case the mounting fasteners and the serverboard Use only the correct type of CMOS onboard battery as specified by the manufac turer Do not install the CMOS onboard battery upside down which may result in a possible explosion Unpacking The serverboard is shipped in antistatic packaging to avoid static damage When unpacking the board make sure the person handling it is static protected Installation Procedures Follow the procedures as listed below to install the serverboard into a chassis 1 Install the processor s and the hea
45. ial port to use for console redirection Options are COM1 and COM2 Serial Port Mode Selects the serial port settings to use Options are 115200 8 n 1 57600 8 n 1 38400 8 n 1 19200 8 n 1 and 09600 8 n 1 Flow Control Selects the flow control to be used for console redirection Options are None Hardware and Software 4 13 H8DC8 H8DCi User s Manual Redirection After BIOS POST Options are Disable no redirection after BIOS POST Boot Loader redirection during POST and during boot loader and Always redirection always active Note that some OS s may not work with this set to Always Terminal Type Selects the type of the target terminal Options are ANSI VT100 and VT UTF8 VT UTF8 Combo Key Support Allows you to Enable or Disable VT UTF8 combination key support for ANSI VT100 terminals Sredir Memory Display Delay Use this setting to set the delay in seconds to display memory information Op tions are No Delay 1 sec 2 secs and 4 secs gt USB Configuration This screen will display the module version and all USB enabled devices USB Controller Support Enable the controller for your USB ports Options are Disabled USB 1 1 only and USB 1 1 USB 2 0 Legacy USB Support Select Enabled to enable the support for USB Legacy Disable Legacy support if there are no USB devices installed in the system The options are Disabled Enabled and Auto USB 2 0 Controller Mode Selec
46. ings JPA1 Jumper Setting Definition Jumper is used to enable or dis 3 able the onboard SCSI controller The default setting is on pins 1 2 to enable SCSI See the table on right for jumper settings Pins 1 2 Enabled Pins 2 3 Disabled USB Standby Power Enable Disable USB Standby Power Enable Disable Jumper Settings J13 Jumper J13 is used to enable or dis Jumper Setting Definition able the presence of standby power for Pins 1 2 Disabled all onboard USB ports and headers Pins 2 3 Enabled Enabling this jumper allows the user to wake up the system from standby mode with a USB keyboard or mouse The default setting is on pins 1 2 to dis able See the table on right for jumper settings 2 19 H8DC8 H8DCi User s Manual 2 8 Onboard Indicators JLAN1 JLAN2 LEDs The Ethernet ports located beside Connection Speed Indicator the VGA port have two LEDs On mii each Gb LAN port one LED indicates gi omuz activity when blinking while the other Green 100 MHz LED may be green amber or off to Amber 1 GHz indicate the speed of the connection See the table on the right for the func tions associated with the connection speed LED 3 3V Standby LED When illuminated the DP1 LED indi 3 3V yn LED cates that 3 3V standby power from the power supply is being supplied to the serverboard DP1 should normally FA EE be illuminated when the system is Off No powe
47. le Options are Disabled and various times in nanoseconds and microseconds gt IOMMU Option Menu IOMMU Mode IOMMU is supported on Linux based systems to convert 32 bit MO addresses to 64 bit Options are AGP Present Disabled 32MB 64MB 128MB 256MB 512MB and 1GB Selecting the Best Fit or Absolute settings allows the user to select aperture size 4 9 H8DC8 H8DCi User s Manual Memory Timing Parameters Allows the user to select which CPU Node s timing parameters memory clock etc to display Options are CPU Node 0 and CPU Node1 gt South Bridge Configuration Audio CODEC Interface Use this setting to Enable or Disable the internal ACI MAC Interface Use this setting to Enable or Disable the internal 802 3 MAC 104 MAC Interface Use this setting to Enable or Disable the 104 internal 802 3 MAC CPU Spread Spectrum This setting is used to enable spread spectrum for the CPU Options are Dis abled and Center Spread SATA Spread Spectrum This setting is used to enable spread spectrum for the SATA Options are Dis abled and Down Spread PCI Express Spread Spectrum This setting is used to enable spread spectrum for the PCI Express Options are Disabled and Down Spread Primary Video This setting is used to switch the PCI bus scanning order while searching for the video card It allows the user to select the type of primary VGA in case of multiple video controllers Options are Slave PCI Express and Mast
48. lect Yes to allow the OS to configure Plug amp Play devices This is not required for system boot if your system has an OS that supports Plug amp Play Select No to allow AMIBIOS to configure all devices in the system PCI Latency Timer This option sets the latency of all PCI devices on the PCI bus Select a value to set the PCI latency in PCI clock cycles Options are 32 64 96 128 160 192 224 and 248 4 5 H8DC8 H8DCi User s Manual Allocate IRQ to PCI VGA Set this value to allow or restrict the system from giving the VGA adapter card an interrupt address The options are Yes and No Palette Snooping Select Enabled to inform the PCI devices that an ISA graphics device is installed in the system in order for the graphics card to function properly The options are Enabled and Disabled PCI IDE BusMaster Set this value to allow or prevent the use of PCI IDE busmastering Select Enabled to allow AMI BIOS to use PCI busmaster for reading and writing to IDE drives The options are Disabled and Enabled Offboard PCI ISA IDE Card This option allows the user to assign a PCI slot number to an Off board PCI ISA IDE card in order for it to function properly The options are Auto PCI Slot1 PCI Slot2 PCI Slot3 PCI Slot4 PCI Slot5 and Slot6 IRQ3 IRQ4 IRQ5 IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 This feature specifies the availability of an IRQ to be used by a PCI PnP device Select Reserved for the IRQ to be used
49. moni tor Real time readings of these voltage levels are all displayed in BIOS Fan Status Monitor with Firmware Software Speed Control The PC health monitor can check the RPM status of the cooling fans The onboard fans are controlled by thermal management via BIOS CPU Overheat Fan Fail LED and Control This feature is available when the user enables the CPU overheat Fan Fail warning function in the BIOS This allows the user to define an overheat temperature When this temperature is exceeded or when a fan failure occurs then the Overheat Fan Fail warning LED is triggered Auto Switching Voltage Regulator for the CPU Core The 3 phase switching voltage regulator for the CPU core can support up to 80A and auto sense voltage IDs ranging from 0 8 V to 1 55V This will allow the regulator to run cooler and thus make the system more stable Chapter 1 Introduction 1 4 Power Configuration Settings This section describes the features of your serverboard that deal with power and power settings Microsoft OnNow The OnNow design initiative is a comprehensive system wide approach to system and device power control OnNow is a term for a PC that is always on but appears to be off and responds immediately to user or other requests Slow Blinking LED for Suspend State Indicator When the CPU goes into a suspend state the chassis power LED will start blinking to indicate that the CPU is in suspend mode When the user presses any key
50. most cases the lt Delete gt key is used to invoke the BIOS setup screen There are a few cases when other keys are used such as lt F1 gt lt F2 gt etc Each main BIOS menu option is described in this manual The Main BIOS screen has two main frames The left frame displays all the options that can be configured Grayed out options cannot be configured The right frame displays the key legend Above the key legend is an area reserved for a text mes sage When an option is selected in the left frame it is highlighted in white Often a text message will accompany it Note that BIOS has default text messages built in We retain the option to include omit or change any of these text messages Set tings printed in Bold are the default values M indicates a submenu Highlighting such an item and pressing the Enter key will open the list of settings within that submenu The BIOS setup utility uses a key based navigation system called hot keys Most of these hot keys lt F1 gt lt F10 gt lt Enter gt lt ESC gt lt Arrow gt keys etc can be used at any time during the setup navigation process 4 1 H8DC8 H8DCi User s Manual 4 2 Main Menu When you first enter AMI BIOS Setup Utility you will see the Main Menu screen You can always return to the Main Menu by selecting the Main tab on the top of the screen with the arrow keys The Main Menu screen provides you with a system overview which includes the
51. ng the interrupt vector table next E2h Initializing the DMA and Interrupt controllers next E6h Enabling the floppy drive controller and Timer IRQs Enabling internal cache mem ory Edh Initializing the floppy drive Eeh Looking for a floppy diskette in drive A Reading the first sector of the diskette Efh read error occurred while reading the floppy drive in drive A FOh Next searching for the AMIBOOT ROM file in the root directory F1h The AMIBOOT ROM file is not in the root directory F2h Next reading and analyzing the floppy diskette FAT to find the clusters occupied by the AMIBOOT ROM file F3h Next reading the AMIBOOT ROM file cluster by cluster F4h The AMIBOOT ROM file is not the correct size F5h Next disabling internal cache memory FBh Next detecting the type of flash ROM FCh Next erasing the flash ROM FDh Next programming the flash ROM FFh Flash ROM programming was successful Next restarting the system BIOS B 2 Appendix B BIOS POST Checkpoint Codes B 3 Uncompressed Initialization Codes The following runtime checkpoint codes are listed in order of execution These codes are uncompressed in F0000h shadow RAM Checkpoint Code Description 03h 05h The NMI is disabled Next checking for a soft reset or a power on condition The BIOS stack has been built Next disabling cache memory 07h 08h Next initializing the CPU and the CPU data area 06h
52. nnector s to your hard drive s Consult the documentation that came with your disk drive for details on actual jumper locations and settings for the hard disk drive Floppy Connector Floppy Drive Connector The floppy connector is located eee beside the IDE 2 connector See the table on the right for pin definitions Definition i Definition GND FDHDIN GND Reserved Key FDEDIN Index Motor Enable Drive Select B Drive Select A Motor Enable DIR STEP Write Data Write Gate Track 00 Write Protect Read Data Side 1 Select Diskette 2 21 H8DC8 H8DCi User s Manual IDE Connectors IDE Drive Connectors Pin Definitions JIDE 1 JIDE 2 There are no jumpers to config Pin Definition Pin Definition ure the onboard IDE 1 and 2 1 Reset IDE 2 Ground connectors See the table on 3 Host Data 7 4 Host Data 8 the right for pin definitions 5 Host Data 6 6 Host Data 9 7 Host Data 5 8 Host Data 10 9 Host Data 4 10 Host Data 11 11 Host Data 3 12 Host Data 12 13 Host Data 2 14 Host Data 13 15 Host Data 1 16 Host Data 14 Alf Host Data 0 18 Host Data 15 19 Ground 20 Key 21 DRQ3 22 Ground 23 VO Write 24 Ground 25 Read 26 Ground 27 IOCHRDY 28 BALE 29 DACK3 30 Ground 31 IRQ14 32 IOCS16 33 Addr1 34 Ground 35 Addr0 36 Addr2 37 Select 0 38 Chip Select 1 39 Activity 40 Ground 2 22 Chapter 2 Installation Parallel Port Connector See the table on the right for pin d
53. of the same size and type will result in interleaved 128 bit memory which is faster than non interleaved 64 bit memory See charts on following page Optimizing memory performance It is better to stagger pairs of DIMMs across both sets of CPU DIMM slots first popu late CPU1 slots 1A and 1B then CPU2 slots 1A and 1B then the next two CPU1 slots etc This balances the load over both CPUs to optimize performance Maximum memory two CPUs 32 GB for DDR266 and 16 GB for DDR400 333 Figure 2 2 Side and Top Views of DDR Installation To Install Insert module vertically and press down until it snaps into place The release tabs should close if they do not you should close them yourself To Remove Use your thumbs to gently push each re lease tab outward to release the DIMM from the slot Notch pisa Note Notch eet should align with the receptive point on the slot Note the notch in the slot and on the bottom of the DIMM These prevent the DIMM from being installed incorrectly Top View of DDR Slot Release Tab Il IL Release Tab 2 5 H8DC8 H8DCi Users Manual Populating Memory Banks for 128 bit Operation CPU1 CPU1 CPU1 CPU1 CPU2 CPU2 CPU2 CPU2 DIMM1A DIMM1B DIMM2A DIMM2B DIMM1A DIMM1B DIMM2A DIMM2B X X EXE gt Notes X indicates a populated DIMM slot If adding at least four DIMMs with two CPUs installed the configu
54. r connected nected to AC power whether turned or not will flash on and off when the system is in an S1 S3 Suspend to RAM or S4 Suspend to Disk state See the table on the right for DP1 LED states State System Status Flashing System in standby state SCSI Activity LEDs H8DC8 When illuminated the DA1 and DA2 ADAN LEDS indicate activity on SCSI chan nels A and B respectively These LEDs are located near the SCSI con troller chip See the table on the right for LED states State System Status On SCSI channel active Off SCSI channel inactive 2 20 Chapter 2 Installation 2 9 Floppy IDE Parallel Port SCSI and SATA Drive Connections Use the following information to connect the floppy and hard disk drive cables e The floppy disk drive cable has seven twisted wires e Ared mark on a wire typically designates the location of pin 1 e Asingle floppy disk drive ribbon cable has 34 wires and two connectors to provide for two floppy disk drives The connector with twisted wires always connects to drive A and the connector that does not have twisted wires always connects to drive B e The 80 wire ATA133 IDE hard disk drive cable that came with your system has two connectors to support two drives This special cable should be used to take advantage of the speed this new technology offers The blue connector connects to the onboard IDE connector interface and the other co
55. r details gt Hyper Transport Configuration CPU0 CPU1 HT Link Speed The HT link will run at the speed specified in this setting if it is slower than or equal to the system clock and if the board is capable Options are Auto 200 MHz 400 MHz 600 MHz 800 MHz and 1 GHz CPU0 CPU1 HT Link Width The HT link will run at the width specified in this setting Options are Auto 2 bit 4 bit 8 bit and 16 bit CPU0 0 HT Link Speed The HT link will run at the speed specified in this setting if it is slower than or equal to the system clock and if the board is capable Options are Auto 200 MHz 400 MHz 600 MHz 800 MHz and 1 GHz CPU0 HT Link Width The HT link will run at the width specified in this setting Options are Auto 2 bit 4 bit 8 bit and 16 bit 4 12 Chapter 4 BIOS gt MPS Configuration MPS Revision This setting allows the user to select the MPS revision level The options are 1 1 and 1 4 gt PCI Express Configuration Active State Power Management Use this setting to Enable or Disable PCI Express LOs and L1 link power states gt AMD PowerNow Configuration This setting is used to Enable or Disable the AMD PowerNow feature gt SMBIOS Configuration SMBIOS SMI Support Enable or Disable SMBIOS wrapper support for PnP function 50h 54h gt Remote Access Configuration Remote Access Allows you to Enable or Disable Remote Access Serial Port Number Selects the ser
56. rations with DIMMs spread over both CPUs and not like the con figuration in row 5 will result in optimized performance Note that the first two DIMMs must be installed in the CPU1 memory slots Populating Memory Banks for 64 bit Operation CPU1 CPU1 CPU1 CPU1 CPU2 CPU2 CPU2 CPU2 DIMM1A DIMM1B DIMM2A DIMM2B DIMM1A DIMM1B DIMM2A DIMM2B 2 6 Chapter 2 Installation 2 5 Port and Control Panel Connections The I O ports are color coded in conformance with the PC99 specification to make setting up your system easier See Figure 2 3 below for the colors and locations of the various ports Figure 2 3 Port Locations and Definitions Mouse Parallel Port Green USB0 1 2 3 Burgundy que Line Out 40977 Hill E 4 Pink Nool Keyboard COM1 Port COM2 Port JLAN2 Line In Purple Turquoise Turquoise Blue Front Control Panel JF1 contains header pins for various front control panel connectors See Figure 2 4 for the pin definitions of the various connectors Refer to Section 2 6 for details Figure 2 4 JF1 Front Control Panel Header JF1 Ground Reset Button Ground Power Button 2 1 2 7 H8DC8 H8DCi User s Manual 2 6 Connecting Cables ATX Power 24 pin Connector Pin Definitions J1B4 ATX Power Connector Definition Pin Definition 3 3V
57. rd Mouse Ports pp 2 12 2 2 12 Overheat LED pe VES m 2 12 M 2 13 5 leman e in dilsel 2 13 ie 2 13 iso 2 13 CD1 IG ACN be M MM ce 2 14 x To E TERTII 2 14 3rd Power Supply Alarm Header pp 2 14 Alarm Reset Header nee ere teer eee E hades 2 14 Gone ne era eet eer ee eee ene ee e eee eee ee ee 2 15 Audio Output Jumper Header 2 15 Keylock Fleader 2 15 2 7 Settings e UEM 2 16 Explanation of J mpers REB e yaa 2 16 GMOS 2 16 3rd Power Supply Fail Signal Enable Disable 2 17 FC to ey a db pl as bears 2 17 Audio Enable Disable sss e C e EY 2 17 Watch Dog Enable Disable pp 2 18 PCI X Slot Speed ise sasi dele 2 18 Onboard Speaker 2 18 SCSI Termination Enable Disable 2 19 SCSI Controller Enable Disable pp 2 19 USB Standby Power Enable Disable 2 19 2 8 Onboard 2 20 JLANT ILAN2 Se sesini cin sauna de rere noe pala
58. respectively See the tables on the right for jumper settings Note JPX1B controls the speed for PCI X slots 2 and 3 and JPX1A controls the speed for PCI X slot 1 The default setting for both is Auto 2 18 Watch Dog Jumper Settings JWD Jumper Setting Definition Pins 1 2 Reset Pins 2 3 NMI Open Disabled Note When enabled the user needs to write their own application software in or der to disable the Watch Dog timer Onboard Speaker Enable Disable Pin Definitions JD1 Pins Definition 6 7 Jump for onboard speaker 4 7 Attach external speaker wires Note Pins 4 7 are used only for the on board speaker PCI X Slot Speed Jumper Settings JPX1A JPX1B Jumper Setting Definition Open Auto Pins 1 2 PCI X 66 MHz Pins 2 3 PCI 66 MHz Chapter 2 Installation SCSI Termination Enable Disable H8DC8 only SCSI Term Enable Disable Jumper Settings JPA2 JPA3 Jumper Setting Definition Jumpers JPA2 and JPA3 are used to enable or disable termination for the SCSI Channel A and B connector re spectively The default setting is open to enable termination See the table on right for jumper settings Note In order for the SCSI drives to function properly please do not change the default setting enabled set by the Open Enabled Closed Disabled manufacturer SCSI Controller Enable Jumper Sett
59. rked with the date of purchase is required be fore any warranty service will be rendered You can obtain service by calling your vendor for a Returned Merchandise Authorization RMA number When returning to the manufacturer the RMA number should be prominently displayed on the outside of the shipping carton and mailed prepaid or hand carried Shipping and handling charges will be applied for all orders that must be mailed when service is complete For faster service RMA authorizations may be requested online http www supermicro com support rma This warranty only covers normal consumer use and does not cover damages in curred in shipping or from failure due to the alteration misuse abuse or improper maintenance of products During the warranty period contact your distributor first for any product problems 3 4 Chapter 4 BIOS Chapter 4 BIOS 4 1 Introduction This chapter describes the AMIBIOS Setup utility for the H8DC8 H8DCi The AMI ROM BIOS is stored in a flash chip and can be easily upgraded using a floppy disk based program Note Due to periodic changes to the BIOS some settings may have been added or deleted and might not yet be recorded in this manual Please refer to the Manual Download area of our web site for any changes to BIOS that may not be reflected in this manual Starting the Setup Utility To enter the BIOS Setup Utility hit the lt Delete gt key while the system is booting up In
60. s 2 With the power disconnected short the CMOS pads with a metal object such as a small screwdriver for at least four seconds 3 Remove the screwdriver or shorting device 4 Reconnect the power cord s and power on the system Notes Do not use the PW ON connector to clear CMOS The onboard battery does not need to be removed when clearing CMOS however you must short JBT1 for at least four seconds JBT1 contact pads 2 16 3rd Power Supply Fail Signal Enable Disable The system can notify you in the event of a power supply failure This feature assumes that three redundant power supply units are installed in the chas sis If you only have one or two power supplies installed you should disable the function with the J3P header to pre vent false alarms See the table on the right for jumper settings to PCI Enable Disable The JI2C1 2 pair of jumpers allows you to connect the System Management Bus to any one of the PCI expansion slots The default setting is closed on for both jumpers to enable the connec tion Both connectors must be set the same JI C1 is for data and JI2C2 is for the clock See the table on right for jumper settings Audio Enable Disable Jumper JPAC is used to enable or dis able the audio Onboard audio is pro vided by AC97 audio CODEC for high quality 6 channel 5 1 sound The de fault setting is on pins 1 2 to enable the audio See the table on right for jumper settings
61. s line parity and the NMI are disabled Adjusting the memory size depending on relocation and shadowing next 58h The memory size was adjusted for relocation and shadowing Clearing the Hit lt DEL gt message next 59h The Hit lt DEL gt message is cleared The lt WAIT gt message is displayed Starting the DMA and interrupt controller test next 60h The DMA page register test passed Performing the DMA Controller 1 base register test next 62h The DMA controller 1 base register test passed Performing the DMA controller 2 base register test next 65h The DMA controller 2 base register test passed Programming DMA controllers 1 and 2 next 66h Completed programming DMA controllers 1 and 2 Initializing the 8259 interrupt controller next 67h Completed 8259 interrupt controller initialization 7Fh 80h The keyboard test has started Clearing the output buffer and checking for stuck keys Issuing the keyboard reset command next Extended NMI source enabling is in progress 81h A keyboard reset error or stuck key was found Issuing the keyboard controller interface test command next 82h The keyboard controller interface test completed Writing the command byte and initializing the circular buffer next 83h The command byte was written and global data initialization has completed Check ing for a locked key next 84h Locked key checking is over Checking for a memory size mismatch with CMOS RAM data next 85h The
62. s supermicro nl General Information support supermicro nl Technical Support rma supermicro nl Customer Support Asia Pacific Address SuperMicro Taiwan No 232 1 Liancheng Rd Chung Ho 235 Taipei Taiwan R O C Tel 886 2 8226 3990 Fax 886 2 8226 3991 Web Site www supermicro com tw Technical Support Email support supermicro com tw Tel 886 2 8228 1366 ext 132 or 139 1 2 Chapter 1 Introduction Figure 1 1 H8DC8 H8DCi Image Note H8DC8 is pictured The H8DCi shares the same layout but with no SCSI compo nents connectors or jumpers 1 3 H8DC8 H8DCi User s Manual Figure 1 2 H8DC8 H8DCi Serverboard Layout not drawn to scale a Kybd ATX Power J32 J24 JPw2 SX J101 Mouse 5 6 FANS CPU2 Fan J1B4 CPU1 DIMM 1B J5 USB0 1 2 3 CPU1 DIMM 1A e COM1 CPU1 DIMM 2B amp CPU1 DIMM 2A 3 J4 C P U2 S x FAN1 E CPU1 Ld JLAN1 2
63. s supported by the processor The options are Auto and Disabled Burst Length Use this setting to set the memory burst length 64 bit Dq must use 4 beats Options are 8 beats 4 beats and 2 beats Hardware Memory Hole When Enabled this feature enables hardware memory remapping around the memory hole Options are Enabled and Disabled Note this is only supported by Rev processors and above BNode Interleaving Use this setting to Enable or Disable node memory interleaving Bank Swizzle Mode Use this setting to Enable or Disable the Bank Swizzle Mode 4 8 Chapter 4 BIOS gt ECC Configuration DRAM ECC Enable DRAM ECC allows hardware to report and correct memory errors automati cally Options are Enabled and Disabled MCA DRAM ECC Logging When Enabled MCA DRAM ECC logging and reporting is enabled Options are Enabled and Disabled ECC Chipkill Allows the user to enabled ECC Chipkill Options are Enabled and Disabled DRAM Scrub Redirect Allows system to correct DRAM ECC errors immediately even with background scrubbing on Options are Enabled and Disabled DRAM BG Scrub Corrects memory errors so later reads are correct Options are Dis abled and various times in nanoseconds and microseconds L2 Cache BG Scrub Allows L2 cache RAM to be corrected when idle Options are Disabled and various times in nanoseconds and microseconds Data Cache BG Scrub Allows L1 cache RAM to be corrected when id
64. scription USB Standby Power En Dis Audio Output 3rd Power Fail Detect En Dis CMOS Clear to PCI Enable Disable SCSI Enable Disable SCSI Channel Term Audio Enable Disable Chapter 1 Introduction H8DC8 H8DCi Quick Reference Default Setting Pins 1 2 Disabled Pins 5 6 9 10 Closed Closed Enabled See Section 2 7 Closed Enabled Pins 1 2 Enabled Open Enabled Pins 1 2 Enabled PCI X Slot 1 Freq Select Open Auto PCI X Slots 2 3 Freq Select Open Auto Watch Dog Pins 1 2 Reset Description Auxiliary Connection for Audio Audio Out for CD COM1 COM2 Serial Ports System Fan Headers IDE Drive Connectors 24 Pin ATX Power Connector Parallel Printer Port System Management Bus Header Power Supply Header 4 pin Auxiliary Power Connector U320 SCSI Channel A Connector 3rd Power Supply Alarm Reset Header U320 SCSI Channel B Connector JC1 MIC Port JC2 Lineln LineOut Ports Onboard Speaker Keylock Power LED Front Panel Connector Floppy Disk Drive Connector Keylock Header Chassis Intrusion Header Gigabit Ethernet RJ45 Ports Overheat Warning Header 8 Pin Processor Power Connector Wake On LAN Header Wake On Ring Header Serial ATA Connectors Universal Serial Bus USB Ports 0 1 2 3 Additional USB Headers 1 5 H8DC8 H8DCi User s Manual Serverboard Features CPU Dual AMD Opteron 200 series 64 bit processors in 940 pin microPGA ZIF sock ets Memory Eight
65. se have your account number ready when contacting our technical support department by e mail 3 3 Frequently Asked Questions Question What type of memory does my serverboard support Answer The H8DC8 H8DCi supports up to 32 GB of registered ECC DDR333 266 or up to 16 GB of registered ECC DDR400 interleaved or non interleaved SDRAM with two CPUs installed See Section 2 4 for details on installing memory Question How do update my BIOS Answer It is recommended that you not upgrade your BIOS if you are not experi encing problems with your system Updated BIOS files are located on our web site Please check our BIOS warning message and the information on how to update your BIOS on our web site Also check the current BIOS revision and make sure it is newer than your current BIOS before downloading Select your mainboard model on the web page and download the corresponding BIOS file to your computer Unzip the BIOS update file in which you will find the readme txt flash instructions the afudos exe BIOS flash utility and the BIOS image xxx rom files Copy these files to a bootable floppy disk insert the disk into drive A and reboot the system At the DOS prompt after rebooting enter the command flash without quotation marks then type in the BIOS file that you want to update with xxxx rom Question What s on the CD that came with my serverboard Answer The supplied compact disc has quite a few drivers and programs tha
66. spend to RAM STR Onboard On chip SATA controller supporting four 4 SATA ports RAID 0 1 and 0 1 Adaptec AIC 7902W U320 SCSI controller RAID 0 1 and 10 Two 2 UltraDMA ATA 133 100 IDE ports One 1 floppy port interface up to 2 88 MB Two 2 Fast UART 16550 compatible serial ports On chip nVidia 2200 2050 Ethernet controller supports two Gigabit LAN ports PS 2 mouse and PS 2 keyboard ports Eight 8 USB Universal Serial Bus 2 0 ports headers Other Wake on Ring JWOR Wake on LAN JWOL AC97 Audio CODEC Onboard 3 3V standby power LED DP1 SCSI channel activity LEDs H8DC8 only Chassis intrusion detection CD Utilities BIOS flash upgrade utility Dimensions Extended ATX form factor 12 x 13 05 305 x 332 mm 1 7 H8DC8 H8DCi Users Manual DDR400 333266 DIMM A1 DIMM A2 128bit data 16 bit ECC 16 x 16 HT link 1 GHz 428 bit data 16 bit ECC DIMM A3 DDR400 339266 DIMM A4 DIMM Bi DIMM B2 AMD Opteron AMD Opteron Y gt 7902W SCSI Ports 2 DIMM B3 Processor CPU2 Processor CPU1 PCEX 100 Slot 1 CHA DIMM B4 x 16 16 HT link 1 GHz gt PCI X 133 100 Slots 2 amp 3 PCI E x16 Slot 6 PCIE x16 Slot 4 PCI Slot 5 LAN 1 PCI E x4 Slot 7 nVidia 10 4 nVidia CK8 04 2050 2200 SATA Ports 4
67. t OK to allow BIOS to automatically load the Optimal Defaults as the BIOS Settings The Optimal settings are designed for maximum system performance but may not work best for all computer applications Load Fail Safe Defaults To set this feature select Load Fail Safe Defaults from the Exit menu and press lt Enter gt The Fail Safe settings are designed for maximum system stability but not maximum performance 4 19 H8DC8 H8DCi Users Manual Notes 4 20 Appendix A BIOS Error Beep Codes Appendix A BIOS Error Beep Codes During the POST Power On Self Test routines which are performed each time the system is powered on errors may occur Non fatal errors are those which in most cases allow the system to continue the boot up process The error messages normally appear on the screen Fatal errors are those which will not allow the system to continue the boot up pro cedure If a fatal error occurs you should consult with your system manufacturer for possible repairs These fatal errors are usually communicated through a series of audible beeps The numbers on the fatal error list on the following page correspond to the number of beeps for the corresponding error All errors listed with the exception of Beep Code 8 are fatal errors 1 AMIBIOS Error Beep Codes Beep Code Error Message Description 1 beep Refresh Circuits have been reset Ready to power up 5 short 1 long Memory error No memory detec
68. t the controller mode for your USB ports Options are HiSpeed and FullSpeed HiSpeed 480 Mbps FullSpeed 12 Mbps BIOS EHCI Hand Off Enable or Disable a workaround for OS s without EHCI hand off support 4 14 Chapter 4 BIOS gt System Health Monitor CPU Overheat Temperature Use the and keys to set the CPU temperature threshold to between 65 and 90 C When this threshold is exceeded the overheat LED on the chas sis will light up and an alarm will sound The LED and alarm will turn off once the CPU temperature has dropped to 5 degrees below the threshold set The default setting is 78 C Other items in the submenu are all systems monitor displays for the following information CPU1 Temperature CPU2 Temperature for 2U systems System Temperature CPU1 Vcore CPU2 Vcore for 2U systems CPU1 DIMM voltage CPU2 DIMM voltage 1 5V 2 5V 3 3V Vcc V 3 3VSB 5Vin 5VSB 12Vin 12Vcc 1 2V for Hyper Transport and battery voltage gt System Fan Monitor Fan Speed Control Modules This feature allows the user to determine how the system will control the speed of the onboard fans Select Workstation if your system is used as a Workstation Select Server if your system is used as a Server Select Disable to disable the fan speed control function to allow the onboard fans to continuously run at full speed 12V The options are 1 Disable Full Speed 2 Server Mode 3 Workstation Mode 4 Quiet Mo
69. t will greatly enhance your system We recommend that you review the CD and install the applications you need Applications on the CD include chipset drivers for Windows and security and audio drivers 3 3 H8DC8 H8DCi User s Manual Question Why can t I turn off the power using the momentary power on off switch Answer The instant power off function is controlled in BIOS by the Power But ton Mode setting When the On Off feature is enabled the serverboard will have instant off capabilities as long as the BIOS has control of the system When the Standby or Suspend feature is enabled or when the BIOS is not in control such as during memory count the first screen that appears when the system is turned on the momentary on off switch must be held for more than four seconds to shut down the system This feature is required to implement the ACPI features on the serverboard Question How do connect the ATA133 cable to my IDE device s Answer The 80 wire 40 pin high density ATA133 IDE cable that came with your system has two connectors to support two drives This special cable must be used to take advantage of the speed the ATA133 technology offers Connect the blue connector to the onboard IDE header and the other connector s to your hard drive s Consult the documentation that came with your disk drive for details on actual jumper locations and settings 3 4 Returning Merchandise for Service A receipt or copy of your invoice ma
70. ted in system 8 beeps Display memory read write error Video adapter missing or with faulty memory A 1 H8DC8 H8DCi User s Manual Notes A 2 Appendix B BIOS POST Checkpoint Codes Appendix B BIOS POST Checkpoint Codes When AMIBIOS performs the Power On Self Test it writes checkpoint codes to I O port 0080h Ifthe computer cannot complete the boot process diagnostic equipment can be attached to the computer to read port 0080h B 1 Uncompressed Initialization Codes The uncompressed initialization checkpoint codes are listed in order of execution Checkpoint Code Description DOh The NMI is disabled Power on delay is starting Next the initialization code check sum will be verified Dih Initializing the DMA controller performing the keyboard controller BAT test starting memory refresh and entering 4 GB flat mode next D3h Starting memory sizing next D4h Returning to real mode Executing any OEM patches and setting the Stack next D5h Passing control to the uncompressed code in shadow RAM at E000 0000h The initialization code is copied to segment 0 and control will be transferred to segment 0 H8DC8 H8DCi User s Manual B 2 Bootblock Recovery Codes The bootblock recovery checkpoint codes are listed in order of execution Checkpoint Code Description EOh The onboard floppy controller if available is initialized Next beginning the base 512 KB memory test E1h Initializi
71. test or retrace checking failed Performing the alter nate display memory read write test next 32h The alternate display memory read write test passed Looking for alternate display retrace checking next 37h 38h Initializing the bus input IPL general devices next if present See the last page of this chapter for additional information The display mode is set Displaying the power on message next 34h Video display checking is over Setting the display mode next 39h Displaying bus initialization error messages See the last page of this chapter for additional information 3Ah The new cursor position has been read and saved Displaying the Hit lt DEL gt mes sage next 3Bh The Hit lt DEL gt message is displayed The protected mode memory test is about to start 40h Preparing the descriptor tables next 42h The descriptor tables are prepared Entering protected mode for the memory test next 43h Entered protected mode Enabling interrupts for diagnostics mode next 44h Interrupts enabled if the diagnostics switch is on Initializing data to check memory wraparound at 0 0 next 45h Data initialized Checking for memory wraparound at 0 0 and finding the total sys tem memory size next 46h The memory wraparound test is done Memory size calculation has been done Writing patterns to test memory next 47h The memory pattern has been written to extended memory Writing patterns to the base 640 KB memory next
72. the 2050 MCP 8132 HyperTransport PCI X Tunnel This hub includes AMD specific technology that provides two PCI X bridges with each bridge supporting a 64 bit data bus as well as separate PCI X operational modes and independent transfer rates Each bridge supports up to five PCI masters that include clock request and grant signals This hub connects to the processors and through them to system memory HyperTransport Technology HyperTransport technology is a high speed low latency point to point link that was designed to increase the communication speed by a factor of up to 48x between integrated circuits This is done partly by reducing the number of buses in the chipset to reduce bottlenecks and by enabling a more efficient use of memory in multi processor systems The end result is a significant increase in bandwidth within the chipset 1 9 H8DC8 H8DCi User s Manual 1 3 Health Monitoring This section describes the PC health monitoring features of the H8DC8 H8DCi The serverboard has an onboard System Hardware Monitor chip that supports PC health monitoring Onboard Voltage Monitors for two CPU cores Hyper Transport 1 2V two memory banks 2 5V nVidia 2200 2050 chipset 1 5V The onboard voltage monitor will scan these voltages continuously Once a voltage becomes unstable it will give a warning or send an error message to the screen Users can adjust the voltage thresholds to define the sensitivity of the voltage
73. the system The options are 0 sec 5 10 15 20 25 30 and 35 ATA PI 80Pin Cable Detection This setting allows AMI BIOS to auto detect the 80 Pin ATA PI cable The options are Host Device and Host amp Device SATAO IDE Interface This setting is used to Enable or Disable the serial controller for SATAO SATA1 IDE Interface This setting is used to Enable or Disable the serial controller for SATA1 First Boot Device From Use this setting to select the first boot device as being P ATA or S ATA 4 4 Chapter 4 BIOS gt Configuration nVidia RAID ROM RAID Option ROM This setting is used to Enable or Disable the nVidia ROM If Enabled the setting below will appear Master SATA as RAID This setting is used to Enable or Disable the 3rd Master as RAID gt Floppy Configuration Floppy A Move the cursor to these fields via up and down lt arrow gt keys to select the floppy type The options are Disabled 360 KB 5 1 4 1 2 MB 5 1 4 720 3 1 44 MB 3 and 2 88 374 Floppy B Move the cursor to these fields via up and down lt arrow gt keys to select the floppy type The options are Disabled 360 KB 5 1 4 1 2 MB 5 1 4 720 KB 3 1 44 3 and 2 88 MB 377 Onboard Floppy Controller Use this setting to Enable or Disable the onboard floppy controller gt PCI PnP Menu Clear NVRAM Select Yes to clear NVRAM during boot up The options are Yes and No Plug amp Play OS Se
74. tsink s 2 Install the serverboard in the chassis 3 Install the memory and add on cards 4 Finally connect the cables and install the drivers 2 1 H8DC8 H8DCi User s Manual 2 2 Processor and Heatsink Installation sor Always connect the power cord last and always remove it be Exercise extreme caution when handling and installing the proces fore adding removing or changing any hardware components Installing the CPU Backplates Two CPU backplates BKT 0004 are included in the retail box The backplates prevent the CPU area of the serverboard from bending and provide a base for at taching the heatsink retention modules To install begin by peeling off the release paper to expose the adhesive On the underside of the serverboard locate the two holes on either side of the CPU socket Attach the adhesive side of the backplate to the board by inserting the standoffs into the two holes and applying light pressure so that the backplate sticks to the underside of the board Repeat for the second CPU socket See Figure 2 1 Note that two CPUs are required for nForce 2050 104 to function properly Installing the Processor 1 Lift the lever on CPU socket 1 until it points straight up 2 Use your thumb and your index fin ger to hold the CPU Locate pin 1 on the CPU socket and pin 1 on the CPU Both are marked with a triangle Triangles 3 Align pin 1 of the CPU with pin 1 of the socket Once aligned carefully
75. version built date and ID of the AMIBIOS the type speed and number of the processors in the system and the amount of memory installed in the system System Time System Date You can edit this field to change the system time and date Highlight System Time or System Date using the lt Arrow gt keys Enter new values through the keyboard Press the lt Tab gt key or the lt Arrow gt keys to move between fields The date must be entered in DAY MM DD YYYY format The time is entered in HH MM SS format Please note that time is in a 24 hour format For example 5 30 A M appears as 05 30 00 and 5 30 P M as 17 30 00 4 3 Advanced Settings Menu gt CPU Configuration Sub Menu GART Error Reporting This setting is used for testing only MTRR Mapping This determines the method used for programming CPU MTRRs when 4 GB or more memory is present The options are Continuous which makes the PCI hole non cacheable and Discrete which places the PCI hole below the 4 GB boundary gt IDE Configuration Onboard PCI IDE Controller The following options are available to set the IDE controller status Disabled will dis able the controller Primary will enable the primary IDE controller only Secondary will enable the secondary IDE controller only Both will enable both the primary and the secondary IDE controllers The six controllers listed are for two dual channel IDE and eight SATA devices 4 2 Chapter 4 BIOS Primary Secondary T

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