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Lenovo Intel Xeon Processor L7445

1. Symbol Parameter Min Max Units Figure Notes Vos MAX Magnitude of Vcc overshoot above VID 50 mV 2 5 Tos Max Time duration of Vcc overshoot above VID 25 us 2 5 Vcc Overshoot Example Waveform Example Overshoot Waveform VID 0 050 Vos z o 9 s gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID Notes 1 VOS is the measured overshoot voltage 2 TOS is the measured time duration above VID Die Voltage Validation Core voltage VCC overshoot events at the processor must meet the specifications in Table 2 15 when measured across the VCC SENSE and VSS SENSE pins and across the VCC SENSE2 and VSS SENSE2 pins Overshoot events that are lt 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope Intel Xeon Processor 7400 Series Datasheet 33 2 11 4 2 11 4 1 intel Electrical Specifications Platform Environmental Control Interface PECI DC Specifications PECI is an Intel proprietary one wire bus interface that provides a communication channel between Intel processor and external thermal monitoring devices The Intel Xeon Processor 7400 Series contains Digital Thermal Sensors DTS distributed throughout the die These sensors are implemented as analog to digital converters calibrated at the factory for reasonable accuracy to provide a di
2. T Parameter Min Max Unit Figure i a T35 Asynchronous GTL input pulse width 8 BCLKs 5 T36 PWRGOOD assertion to RESET de assertion 1 10 ms 2 20 T37 BCLK stable to PWRGOOD assertion 10 BCLKs 2 20 6 12 T38 PROCHOT pulse width 500 us 2 16 7 T39 THERMTRIP assertion until Vcc removed 500 ms 2 17 8 T40 FERR valid delay from STPCLK deassertion 0 5 BCLKs 2 21 T41 Vcc stable to PWRGOOD assertion 0 05 500 ms 2 20 10 T42 PWRGOOD rise time 20 ns 11 T44 VID BSEL valid to Vcc stable 100 us 2 20 10 T48 Vy stable to VID BSEL valid 10 us 2 20 10 T49 Vccp stable to PWRGOOD assertion 1 ms 2 20 10 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All AC timings for the Asynchronous GTL signals are referenced to the BCLKO rising edge at Crossing Seg od so co 10 11 12 Voltage Vcnoss PWRGOOD is referenced to BCLKO rising edge at 0 5 Vy These signals may be driven asynchronously Refer to Section 7 2 for additional timing requirements for entering and leaving low power states A minimum pulse width of 500 us is recommended when FORCEPR is asserted by the system Refer to the PWRGOOD signal definition in Section 5 for more details information on behavior of the signal Length of assertion for PROCHOT does not equal TCC activation time Time is required after the assertion and before the deassertion of PROCHOT for the processor to enable o
3. Vcc Vss lt mo aul monu l O E u SSES gt lt d d lt lt roooee 4 4 60 O e e e e e o oo Des e O o 60000000000 o o o Ol fq 9000 e e e _ o o e o amp SEN eoooo 6060600000000 o ooooe e e e e e e e e N o o o 0 O 606000000000 E 0060 e e e e e e A N 60000000000 22 COMMON CLOCK 21 o N 2ej jooeo0 6 2 o a o o to 2 T a E o o c x A o 2 o 9 e e e e e e e e e e e e e e eo N e e e e e e e e e e e e e e e 9 9 e o o o e d e e e e 0 e 5v e e e e e e e e 0 e e e e zo e e e e e e 0 0 ee zo e e e e e e eeeoo 90 eeoe e e e e o o monodultgugrox zzuemrto z mononu lt lt lt lt lt SSA 99A Figure 3 11 Processor Pin Out Coordinates Top View Mechanical Specifications 3 9 63 Reserved No Connect VTT Ki o DATA Signal VCC e Ground O e CLOCKS Intel Xeon Processor 7400 Series Datasheet 64 Mechanical Specifications Intel Xeon Processor 7400 Series Datasheet Pin Listing 4 4 1 4 1 1 Pin Listing Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 1 of 16 Processor Pin Assignments Section 2 6 contains the front side bus signal groups for th
4. VTT P The FSB termination voltage input pins Refer to Table 2 9 for further details VTT_SEL O The VTT_SEL signal is used to select the correct V voltage level for the processor VTT_SEL is connected to ground on the Intel Xeon Processor 7400 Series package 88 Intel Xeon Processor 7400 Series Datasheet n Thermal Specifications n tel 6 6 1 6 1 1 Thermal Specifications Package Thermal Specifications The Intel Xeon Processor 7400 Series require a thermal solution to maintain temperatures within its operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting This section provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution refer to the Intel Xeon Proce
5. 70 Intel Xeon Processor 7400 Series Datasheet Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 13 of 16 Table 4 1 Pin Listing by Pin Name intel Sheet 14 of 16 Pin Name Ne od Direction Pin Name n RN Direction Vss J29 Power Other Vss P9 Power Other Vss 31 Power Other Vss P23 Power Other Vss K2 Power Other Vss P25 Power Other Vss K4 PPower Other Vss P27 Power Other Vss K6 Power Other Vss P29 Power Other Vss K8 Power Other Vss P31 Power Other Vss K24 Power Other Vss R2 Power Other Vss K26 Power Other Vss R4 Power Other Vss K28 Power Other Vss R6 Power Other Vss K30 Power Other Vss R8 Power Other Vss L1 Power Other Vss R24 Power Other Vss L3 Power Other Vss R26 Power Other Vss L5 Power Other Vss R28 Power Other Vss L7 Power Other Vss R30 Power Other Vss L9 Power Other Vss T1 Power Other Vss L23 Power Other Vss T3 Power Other Vss L25 Power Other Vss T5 Power Other Vss L27 Power Other Vss T7 Power Other Vss L29 Power Other Vss T9 Power Other Vss L31 Power Other Vss T23 Power Other Vss M2 Power Other Vss T25 Power Other Vss MA Power Other Vss T27 JPower Other Vss M6 Power Other Vss T29 Power Other Vss M8 Power Other Vss T31 Power Other Vss M24 Power Other Vss U2 Power Other Vss M26 Power Other Vss U4 Power Oth
6. Tg LUNII be Vcc poor Ta pa Tb 1 Te gt Td TTT OODUA DEEN EEN EN Ta T43 Vcc poor stable to VID 6 1 BSEL 2 0 valid Tb T44 VID 6 1 BSEL 2 0 valid to Vcc stable Tc T48 Vr stable to VID 6 1 BSEL 2 0 valid Td T36 PWRGOOD assertion to RESET de assertion Te T41 Vcc stable to PWRGOOD assertion Tf T37 BCLK stable to PWRGOOD assertion Tg T49 Vcce stable to PWRGOOD assertion Th T45 Reset Configuration Signals A 35 3 BR 1 0 INIT SMI Setup Time Ti T46 Reset Configuration Signals A 35 3 INIT SMI Hold Time Tj T47 Reset Configuration Signals BR 1 0 Hold Time FERR PBE Valid Delay Timing BCLK System bus STPCLK FERR PBE Ta FERR Intel Xeon Processor 7400 Series Datasheet Electrical Specifications Notes 1 Ta T40 FERR Valid Delay from STPCLK Deassertion 2 FERR PBE is undefined from STPCLK assertion until the Stop Grant acknowledge is driven on the FSB FERR PBE is also undefined for a period of Ta from STPCLK deassertion Inside these undefined regions the PBE signal Figure 2 22 VID Step Timings is driven FERR is driven at all other times intel VID n Vue max Ta T84 Tb T82 Tc T85 Td T83 Ta Tb Vc min jz VID Down to Valid V max VID Down
7. A 39 3 ADS ADSTB 1 0 AP 1 0 BINIT BPM 5 0 BPMb 3 0 RESET BR 1 0 BNR BPRI D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 HIT HITM LOCK MCERR REQ 4 0 RS 2 0 RSP TRDY Note 1 Signals that have RTT in the package with 50 Q pullup to V Non AGTL Signal Description Table Signals with R t Signals with no R r A20M BCLK 1 0 BSEL 2 0 COMP 3 0 FERR PBE FORCEPR GTLREF ADD MID GTLREF ADD END GTLREF DATA MID GTLREF DATA END IERR IGNNE INIT LINTO INTR LiNT1 NMI LL ID 1 0 PROC ID 1 0 PECI PROCHOT PWRGOOD SKTOCC SMI STPCLK TCK TDI TDO TESTHI 1 0 TESTIN1 TESTIN2 THERMTRIP TMS TRST VCC SENSE VCC_SENSE2 VID 6 1 VSS_ SENSE VSS_SENSE2 VIT SEL Signal Reference Voltages GTLREF CMOS A 39 3 ADS ADSTB 1 0 AP 1 0 BINIT A20M FORCEPR LINTO INTR LINT1 NMI IGNNEZ BNR BPM 5 0 BPMb 3 0 BPRI BR 1 0 INITZ PWRGOOD SMI STPCLK TCK TDI TMS D 63 0 DBI 3 0 DBSY DEFER DP 3 0 TRST DRDY DSTBN 3 0 DSTBP 3 0 HIT HITM LOCK MCERR RESET REQ 4 0 RS 2 0 RSP TRDY CMOS Asynchronous and Open Drain Asynchronous Signals Legacy input signals such as A20M IGNNEZ INIT SMI and STPCLK utilize CMOS input buffers Legacy output signals such as FERR PBE IERR PROCHOT THERMTRIP and TDO utilize
8. TCK V Valid Signal Tx T58 TDO Clock to Output Delay Ts T56 TDI TMS Setup Time Th T57 TDI TMS Hold Time V 0 5 VL Note Please refer to Table 2 12 for TAP Signal Group DC specifications and Table 2 24 for TAP Signal Group AC specifications Figure 2 16 Test Reset TRST Async GTL Input and PROCHOT Timing Waveform T 159 TRST Pulse Width V 0 5 V r q Tas PROCHOT Pulse Width V GTLREF Figure 2 17 THERMTRIP Power Down Sequence THERMTRIP Vcc Vor T T39 THERMTRIP to removal of power 46 Intel Xeon Processor 7400 Series Datasheet Electrical Specifications n tel Figure 2 18 SMBus Timing Waveform Figure 2 19 HD STA Ch ke t H SU DAT Data Low T93 t HD STA T100 t gu sta T101 t HIGH T92 t HD DAT T98 SU STD T102 R T94 t BUF T99 te mme supar T97 SMBus Valid Delay Timing Waveform SM CLK TAA gt DATA VALID SM DAT J XS JV sa kw zm a DATA OUTPUT TAA T96 Intel Xeon Processor 7400 Series Datasheet 47 Electrical Specifications Figure 2 20 Voltage Sequence Timing Requirements Figure 2 21 48 VID 6 1 BSEL 2 0 Vit VecrLt Vcc PWRGOOD BCLK Reset Configuration Signals A 35 3 INIT SMI Reset Configuration Signals BR 1 0 RESET IIT X
9. sse eene enn 60 3 2 Package Handling Guidelines ccc eee eee kk kala kak aa memes 61 3 3 Processor Materials E DRE X RA FER be aa a ab w d wiy MATE EE D COE 61 45L2 Pin Listing by Pin NAME EE 65 4 2 Pin Listing by Pin Number 73 5 1 Signal DejllllklOh Siy eo exter ax reser Ed int Ee EEN Ae eg 81 6 1 Processor Thermal Specifications sse kk kk nnns 91 6 2 Intel Xeon X7460 Processor Thermal Profile Table 92 6 3 6 Core Intel Xeon Processor E7400 Series Thermal Profile Table 93 6 4 4 Core Intel Xeon Processor E7400 Series Thermal Profile Table 94 6 5 6 Core Intel Xeon Processor L7400 Series Thermal Profile Table 95 6 6 4 Core Intel Xeon Processor L7400 Series Thermal Profile Table 96 6 7 GetTempO and GetTemp1 Error Codes mmn nn 104 7 1 Power On Configuration Option Pins 105 7 2 Extended HALT Maximum Power ssssssen Hmmm se memem esee eser 107 7 3 Memory Device SMBus Addressing hk kk kkkk kk kk kk meme nemen 112 7 4 Read Byte SMBUS Packet cece cece eee een mese seems sess 112 725 Write Byte SMBUS PaCket aisen test egeeeegeg eg n tee dE SEN ee 112 7 6 Processor Information ROM Data Sections ccecee eee e kk kk e mmn 113 7 7 128 Byte ROM Checksum values 0 ce cece eee eee ener ee nemen memes senes 132 6 Intel Xeon Processor 74
10. 9 Eee eu een z 9 9 9 000000000 lt 000000000 000000000 1 000000000 000000000 000000000 000000000 PERA RE BR z 088048000000009 f gt aovwovd oe x 0000 0000000000 0000 9 9 9 9 x DFEEEEEEEEFCFEFRERE FT 9 99 0 9 99 0 9 9 9 9 9 9 Y St 9re 19 1 X2 k r zi 2 ins 50580 Am c 9 g 53 Intel Xeon Processor 7400 Series Datasheet 54 3 2 Mechanical Specifications Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements A thermal and mechanical solution design must not intrude into the required keepout zones Decoupling capacitors are typically mounted to either the topside or pin side of the package substrate All drawing dimension are in mm in Intel Xeon Processor 7400 Series Datasheet intel Mechanical Specifications Top Side Board Keepout Zones Part 1 Figure 3 4 AINO 32N34313U Y 0J AYYONNOG 134208 r09v9gU N0I12181S38 1H913H 1N3NOdWOO XVW WW 9279 G2 V3uV YNISLYJH y l 9 L 8 9 40 133HS 9NIMYYA 178 LON 00 3NON 31v28 x asina LI 46261V X d 73 E 03NO11V S1N3NOdHO2 QNYOGHHION ON 100d33 YIONI4 QNVOG ONIYdS 439 o A Zem oniavaa 3005 a9v3 fanis mum 34 Mn Y Nod ivo se ganodev 1nodx za zue onon CT WI
11. Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor FSB agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present There is no connection to the processor silicon for this signal SM_CLK 1 0 The SM_CLK SMBus Clock signal is an input clock to the system management logic which is required for operation of the system management features of the processor This clock is driven by the SMBus controller and is asynchronous to other clocks in the processor The processor includes a 10 kQ pull up resistor to SM_VCC for this signal SM_DAT 1 0 The SM_DAT SMBus Data signal is the data signal for the SMBus This signal provides the single bit mechanism for transferring data between SMBus devices The processor includes a 10 kQ pull up resistor to SM_VCC for this signal SM_EP_A 2 0 The SM_EP_A EEPROM Select Address pins are decoded on the SMBus in conjunction with the upper address bits in order to m
12. activation and may incur measurable performance loss See Section 6 2 for details on TCC activation Refer to the Intel amp Xeon Processor 7400 Series Thermal Mechanical Design Guide for system and environmental implementation details Intel Xeon Processor 7400 Series Datasheet 95 E e n tel Thermal Specifications Figure 6 5 4 Core Intel Xeon Processor L7400 Series Thermal Profile Tease 0 400 x Power 45 C 0 10 20 30 40 50 Power W Notes 1 Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 6 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide for system and environmental implementation details Table 6 6 4 Core Intel Xeon Processor L7400 Series Thermal Profile Table Power W Tcase Max C 0 45 10 49 20 53 30 57 40 61 50 65 Notes 1 Thermal Profile is representative of a volumetrically unconstrained platform 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermor
13. 0000h FFFFh Reserved CDCKS Cache Data Checksum This location provides the checksum of the Cache Data Section Writes to this register have no effect Offset 31h Bit Description 7 0 Cache Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Package Data This section provides package revision information PREV Package Revision This location tracks the highest level package revision It is provided in ASCII format of four characters 8 bits x 4 characters 32 bits The package is documented as 1 0 2 0 etc If this only consumes three ASCII characters a leading space is provided in the data field Example The Intel Xeon Processor 7400 Series utilizes the first revision of the FC mPGA8 package Thus at offset 32 35h the data is a space followed by 1 0 In hex this would be 20h 31h 2Eh 30h Offset 32h 35h Bit Description 31 24 Character 4 ASCII character or 20h OOh OFFh ASCII character 23 16 Character 3 ASCII character OOh OFFh ASCII character 15 8 Character 2 ASCII character OOh OFFh ASCII character 7 0 Character 1 ASCII character OOh OFFh ASCII character Intel Xeon Processor 7400 Series Datasheet Features 7 4 3 5 2 7 4 3 5 3 7 4 3 6 7 4 3 6 1 RES5 Reserved 5 This location is reserved Writes to this register have no effect
14. L PACKAGE 4 PIN 7 0 15 0 203 A 0 65 max F t L 0 0650 P RO 0254 4 JL SCALE 10 1 0 65 MAX nm A I 4 SIDE VIEW 50 31 MAX 52 E E pte 3 m E I be I E Io Dr o o ES E pi 3 gt lt 2 SES 2 rev be xa E n zSx e o ez kel S be Li 1 o p SOR EI UN 228 ooa d acm E TP 5u a e ote E z 2 2x 85 o ees Eo i T e Fu oo E ZG E is a 2 2 j 3 2 E a al 2 S RW UN 2 E gt s co Intel Xeon Processor 7400 Series Datasheet intel Mechanical Specifications Intel Xeon Processor 7400 Series Package Drawing Sheet 2 of 2 Figure 3 3 9 9 EES ETT Ki det ll e Gi 1 MILA WOLLOG MAIA dOl EN M3 A 3q IS V3uY GIHDLVHSSOYD 1H913H 1N3NOdNO2 Y 100 4339 LNINOdNOD 318VM011V XVW Z N i i ji H Seege gege ge 00000 O 00000000000 00000 6666990 eee 90 0 9660 06 e 0 66060006090 00 00000 kas 000QQ0OOQQOHO 00000 E HILL 22909 EE 000000000 0000 ed 000000000 0000 lt 000000000 00009 4 n 4 eeeeeeeee I 993 9
15. Other B18 A5 Source Sync Input Output B19 REQO Common Clk Input Output B20 Vcc Power Other B21 REQ1 Common Clk Input Output B22 REQ4 Common Clk Input Output B23 Vss Power Other B24 LI NTO Async GTL Input B25 PROCHOT Async GTL Output B26 Vss_SENSE2 Power Other Output B27 Vcc_SENSE Power Other J Output B28 LL_ID1 Power Other Output B29 PROC ID1 Power Other Output B30 Reserved B31 LL IDO Power Other J Output C VI D6 Power Other Output C2 TESTIN2 Power Other Input C3 VID3 Power Other Output C4 Vcc Power Other C5 Ver Power Other C6 RSP Common Clk Input C7 Vss Power Other C8 A35 Source Sync Input Output C9 A34 Source Sync Input Output C10 Ver Power Other C11 A30 Source Sync Input Output C12 A23 Source Sync Input Output C13 Vss Power Other C14 Al6 Source Sync Input Output C15 A154 Source Sync Input Output C16 A39 Source Sync Input Output C17 A8 Source Sync Input Output C18 A6 Source Sync Input Output C19 Vss Power Other C20 REQ3 Common Clk Input Output C21 REQ2 Common Clk Input Output C22 Mee Power Other 73 intel Pin Listing Table 4 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Sheet 3 of 14 Sheet 4 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type C23
16. Power Other Vss F2 Power Other Vcc AE18 Power Other Vss F3 Power Other Vcc AE24 Power Other Vss F7 Power Other VccPLL AD1 Power Other Input Vss F13 Power Other Vcc sENSE B27 Power Other Output Vss F19 Power Other Vcc_SENSE2 A26 Power Other Output Vss F25 Power Other VID1 E3 Power Other Output Vss F28 Power Other VID2 D3 Power Other Output Vss F30 Power Other VID3 C3 Power Other Output Vss G1 Power Other VID4 B3 Power Other Output Vss G3 Power Other VID5 A1 Power Other Output Vss G5 Power Other VID6 C1 Power Other Output Vss G7 Power Other Vss A5 Power Other Vss G9 Power Other Vss A11 Power Other Vss G25 Power Other Vss A21 Power Other Vss G27 Power Other Vss A27 Power Other Vss G29 Power Other Vss A29 Power Other Vss G31 Power Other Vss B2 Power Other Vss H2 Power Other Vss B9 Power Other Vss H4 Power Other Vss B15 Power Other Vss H6 Power Other Vss B17 Power Other Vss H8 Power Other Vss B23 Power Other Vss H24 Power Other Vss C7 Power Other Vss H26 Power Other Vss C13 Power Other Vss H28 Power Other Vss C19 Power Other Vss H30 Power Other Vss C25 Power Other Vss J Power Other Vss C29 Power Other Vss J3 Power Other Vss D2 Power Other Vss J5 Power Other Vss D5 Power Other Vss J7 Power Other Vss D11 Power Other Vss J9 Power Other Vss D21 Power Other Vss J23 Power Other Vss D28 Power Other Vss J25 Power Other Vss D30 Power Other Vss J27 Power Other
17. T4 Vcc Power Other v25 Vss Power Other T5 Vss Power Other V26 Vcc Power Other T6 Vcc Power Other V27 Vss Power Other T7 Vss Power Other V28 Vcc Power Other T8 Vcc Power Other V29 Vss Power Other T9 Vss Power Other v30 Vcc Power Other T23 Vss Power Other V31 Vss Power Other T24 Vcc Power Other WI Vcc Power Other T25 Vss Power Other w2 Vss Power Other T26 Vcc Power Other w3 TESTHI1 Power Other Input T27 Vss Power Other WA Vss Power Other T28 Vec Power Other w5 BCLK1 FSB Clk Input T29 Vss Power Other W V Power Other T30 Vcc Power Other WI V Power Other T31 Vss Power Other W V Power Other U1 Vcc Power Other w9 GTLREF_DATA_END Power Other Input U2 Vss Power Other W23 GTLREF DATA MID Power Other Input U3 Vcc Power Other W24 Vss Power Other UA Vss Power Other W25 Vcc Power Other U5 Vcc Power Other W26 Vss Power Other U6 Vss Power Other W27 Vcc Power Other U7 Vcc Power Other W28 Vss Power Other U8 Vss Power Other W29 Vec Power Other U9 Vcc Power Other W30 Vss Power Other U23 Vec Power Other W31 Mee Power Other U24 Vss Power Other Y1 Vss Power Other U25 Vcc Power Other Y2 Vcc Power Other U26 Vss Power Other Y3 Vss Power Other U27 Vcc Power Other Y4 BCLKO FSB Clk Input U28 Vss Power Other Y5 Vss Power Other U29 Vcc Power Other Y6 Ver Power Other U30 Vss Power Other Y7 Vss Power Other U31 Vcc Power Other Y8 RESET Common Clk Input V1 Vss Power Other Y9 D62 Source Sync Input Output V2 Vcc Power Other Y10 Ver Power
18. These specifications must be met while also meeting signal integrity requirements as outlined in Table 2 18 The processor utilizes differential clocks Details regarding BCLK 1 0 driver specifications are provided in the CK410B Clock Synthesizer Driver Design Guidelines Table 2 1 contains processor core frequency to FSB multipliers and their corresponding core frequencies Core Frequency to Multiplier Configuration Core Frequency to FSB Core Frequency with Notes Multiplier 266 MHz FSB Clock 1 8 2 13 GHz 1 9 2 40 GHz 1 10 2 66 GHz Notes 1 Individual processors operate only at or below the frequency marked on the package 2 For valid processor core frequencies refer to the Intel Xeon Processor 7400 Series Specification Update Front Side Bus Frequency Select Signals BSEL 2 0 Upon power up the FSB frequency is set to the maximum supported by the individual processor BSEL 2 0 are CMOS outputs and are used to select the FSB frequency Please refer to Table 2 12 for DC specifications Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer All FSB agents must operate at the same core and FSB frequency See the appropriate platform design guidelines for further details BSEL 2 0 Frequency Table BSEL2 BSEL1 BSELO Bus Clock Frequency 0 0 0
19. Xeon Processor 7400 Series 01 Intel Xeon Processor 7300 and 7200 Series 10 Reserved 11 Reserved Intel Xeon Processor 7400 Series Datasheet 85 intel Table 5 1 Signal Definitions Signal Definitions Sheet 6 of 8 Name PROCHOT Type O Description PROCHOT Processor Hot will go active when the processor s temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the Thermal Control Circuit TCC has been activated if enabled The TCC will remain active until shortly after the processor deasserts PROCHOT See Section 6 2 5 for more details Notes PWRGOOD PWRGOOD Power Good is an input The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state Figure 2 20 illustrates the relationship of PWRGOOD to the RESET signal PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 2 15 and be followed by a 1 10 ms RESET pulse The PWRGOOD
20. n tel 3 4 Table 3 2 3 5 3 6 3 7 Table 3 3 Package Handling Guidelines Table 3 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N 80 Ibf 1 2 Tensile 156 N 35 Ibf 3 2 Torque 8 N m 70 Ibf in 4 2 Notes 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 These guidelines are based on limited testing for design characterization 3 A tensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface 4 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface Package Insertion Specifications The Intel Xeon Processor 7400 Series can be inserted into and removed from a mPGA604 socket 15 times The socket should meet the mPGA604 requirements detailed in the mPGA604 Socket Design Guidelines Processor Mass Specifications The typical mass of the Intel Xeon Processor 7400 Series is 37 6 g 1 50z This mass weight includes all the components that are included in the package Processor Materials Table 3 3 lists some of the package components and associated materials Processor Mate
21. 11b Reserved Intel Xeon Processor 7400 Series Datasheet Features 7 4 3 2 3 7 4 3 3 7 4 3 3 1 Note intel This location provides the checksum of the Processor Data Section Writes to this register have no effect PDCKS Processor Data Checksum Offset 15h Bit Description 7 0 Processor Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Processor Core Data This section contains core silicon related data CPUI D Processor CPUI D Signature This location contains the CPUID Processor Type Family Model and Stepping The CPUID field is a copy of the results in EAX 27 0 from Function 1 of the CPUID instruction The MSB is at location 16h the LSB is at location 19h Writes to this register have no effect Example If the CPUID of a processor is 000106D0h A 0 stepping then the value programmed into offset 16 19h of the PIROM is 00041980h The field is not aligned on a byte boundary since the first two bits of the offset are reserved Thus the data must be shifted right by two in order to obtain the same results as the CPUID instruction Offset 16h 19h Bit Description 31 30 Reserved 00b 11b Reserved 29 21 Extended Family 00h 0Fh Extended Family 21 18 Extended Model Oh Fh Extended Model 17 16 Reserved 00b 11b Reserved 15 14 Processor Type 00b 11b
22. 2 8 Processor Absolute Maximum Rat ngS kh h k k kk kk kk memes 23 2 9 Voltage and Current Specifications 0 ccc kk nner kak kk ka 24 2 10 VCC Static and Transient Tolerance icc ce eee eee kk kk kaka ka 30 2 11 AGTL Signal Group DC Gpeclcations ccc meme 31 2 12 CMOS Signal Input Output Group DC Specifications sse 32 2 13 Open Drain Signal Group DC Specifications cece ee eee kaka 32 2 14 SMBus Signal Group DC Gpecflcations cece eee eee mene 32 2 15 VCC Overshoot Specifications cc semen memes memes nnn 33 2 16 BECH DC Electrical Limits ss Hasen k Sakan don te la an nola ed Za n na a ana d waa n n n d en 34 2 17 AGTL Bus Voltage Definitions kk kk kk kk een 36 2 18 FSB Differential BCLK Specifications 2 0 0 kk kk ka 36 2 19 Front Side Bus Differential Clock AC Specifications cccecece eee eee ee eee kk 37 2 20 Front Side Bus Common Clock AC Specifications c cece eee eee eee ka 37 2 21 FSB Source Synchronous AC Gpechfications cece teeter eee 38 2 22 Miscellaneous GTL AC Gpechfications cece eee memes 39 2 23 Front Side Bus AC Specifications Reset Conditions 39 2 24 TAP Signal Group AC Specifications cece eee een enne 40 2 25 VID Signal Group AC Specifications sssssssrsssrrerit ttrt tintin kk memes ene 40 2 26 SMBus Signal Group AC Specifications cece eee nmm 40 3 1 Processor Loading Specifications
23. 4 94 700 650 8 o g o Toge 0222 x Power A 45 C Temperature C BOB E o 350 Notes 1 Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 4 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide for system and environmental implementation details 4 Core Intel Xeon Processor E7400 Series Thermal Profile Table Power W TcasE MAX C 0 45 0 10 47 2 20 49 4 30 51 7 40 53 9 50 56 1 60 58 3 70 60 6 80 62 8 90 65 0 Notes 1 Thermal Profile is representative of a volumetrically constrained platform 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide f
24. 4 2 Input Device Hysteresis ccc eee mmm 35 2 12 AGTL FSB Specifications cco ERR eret ee beni aa ni INR REED ee ENER CEA 35 2 13 Front Side Bus AC Specifications s i a dla kalak yaya nne kall kan keli kala awa kla aa bal alal aa a nea ala 37 2 14 Processor AC Timing Waveforms M L L hL k k kk kk kk kk kk kak ka kak kk kk ke 41 3 Mechanical Specifications L L LLL LL kk kk kk kaka kak 51 3 1 Package Mechanical Drawing kk kk kk kk k y een 51 3 2 Processor Component Keepout Zones 54 3 3 Package Loading Specifications sssssssssssssesee mme kk ees 60 3 4 Package Handling Guidelines nemen memes 61 3 5 Package Insertion Gpechflcations mmn nemen eren 61 3 6 Processor Mass Specifications s alal lkaala kanala kabra aa mme nee waya a a war ees 61 3 7 Processor Materials ep sta dll k lana d k na d eR xx n nad d xERR HAE EEEE EE EE 61 3 8 Processor Maliki 05 35 eite Da Wik Erro biased Eed ab E Ee 62 3 9 Processor Pin Out Coordinates hL h h kWk KL lkkkk kk kk kk kak kk y k aka ke 63 4 NIR E e cerr r bbn 65 4 1 Processor Pin Assignments 0 cece kk kk kk kk kaka kk enne kaka 65 41 1 PinListing by Pin Name xng ege EES AE nie nab at beda b Wan de D n ebe nali 65 4 1 2 Pin Listing by Pin Number 73 5 Signal Definitions oe AER SE ER REES EE 81 5 4 Signal DeflinitlOris i cte caxeteis E b a n nina dana ET MEE ec 81 6
25. 4 Core Intel Xeon Processor L7400 Series Launch FMB 65 15 lec Toc Thermal Design Current TDC for a Intel Xeon X7460 Processor Launch FMB 5 13 lec toc Thermal Design Current TDC for a 6 core Intel Xeon Processor E7400 Series Launch FMB 95 5 13 lec mme Thermal Design Current TDC for a 4 core I ntel amp Xeon Processor E7400 Series Launch FMB 95 5 13 lec mme Thermal Design Current TDC for a 6 Core Intel Xeon Processor L7400 Series Launch FMB 70 5 13 Icc Toc Thermal Design Current TDC for a 4 Core Intel Xeon Processor L7400 Series Launch FMB 55 5 13 IsM vcc Icc for SMBus supply 100 122 5 mA lr lec for Vr supply before Vcc stable Icc for Vr supply after Vcc stable 8 0 7 0 14 Icc GTLREF ICC vccPLL lec for GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END Icc for PLL supply 200 520 HA mA 11 Intel Xeon Processor 7400 Series Datasheet 25 E e n tel Electrical Specifications Table 2 9 Voltage and Current Specifications Sheet 2 of 3 Symbol Parameter Min Typ Max Unit Notes 1 lec Icc for an 6 Core Intel 85 A 3 4 5 8 Xeon Processor L7400 Series Launch FMB lec Icc for an 4 Core Intel 65 A 3 4 5 8 Xeon Processor L7400 Series Launch FMB cc_RESET cc_RESET f
26. APO AP1 A 23 3 AP1 APO REQ 4 0 AP1 APO BCLK 1 0 The differential bus clock pair BCLK 1 0 Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss Intel Xeon Processor 7400 Series Datasheet 81 n intel DEE Table 5 1 Signal Definitions Sheet 2 of 8 Name Type Description Notes BINIT 1 0 BINIT Bus Initialization may be observed and driven by all processor FSB agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration see Section 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their I O Queue OO and transaction tracking state machines upon observation of BINIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the FSB and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a priority agent may handle an assertion of BINIT as appropr
27. BPMb3 Common Clk Input Output AC24 D20 Source Sync Input Output AE4 V Power Other AC25 Vss Power Other AE5 V Power Other AC26 D17 Source Sync Input Output AE6 Vss Power Other Input AC27 DBIO Source Sync Input Output AE7 D58 Source Sync Input Output AC28 SM_CLK SMBus Input AE8 Reserved AC29 GM DAT SMBus Output AE9 D44 Source Sync Input Output AC30 Reserved AE10 D42 Source Sync Input Output AC31 Mee Power Other AE11 Vss Power Other AD1 Vccpii Power Other Input AE12 DBI2 Source Sync Input Output AD2 Vcc Power Other AE13 D35 Source Sync Input Output AD3 Vss Power Other AE14 Vcc Power Other AD4 Reserved AE15 COMP2 Power Other Input AD5 Vr Power Other AE16 COMP3 Power Other Input AD6 Reserved AE17 DP3 Common Clk Input Output AD7 D57 Source Sync Input Output AE18 Vcc Power Other AD8 D46 Source Sync Input Output AE19 DP1 Common Clk Input Output AD9 Vss Power Other AE20 D28 Source Sync Input Output AD10 D45 Source Sync Input Output AE21 Vss Power Other AD11 D40 Source Sync Input Output AE22 D27 Source Sync Input Output AD12 Vir Power Other AE23 D22 Source Sync Input Output AD13 D38 Source Sync Input Output AE24 Vcc Power Other AD14 D39 Source Sync Input Output AE25 D19 Source Sync Input Output AD15 Vss Power Other AE26 D16 Source Sync Input Output AD16 J Reserved AE27 Vss Power Other AD17 Vss Power Other AE28 SM_VCC Power Other AD18 D36 Source Sync Input O
28. Data section not present O1h 31h Reserved 32h Package Data section pointer value 33h FFh Reserved Intel Xeon Processor 7400 Series Datasheet 117 intel 7 4 3 1 7 7 4 3 1 8 7 4 3 1 9 118 PNDA Part Number Data Address Features This location provides the offset to the Part Number Data Section Writes to this register have no effect Offset 07h Bit Description 7 0 Part Number Data Address Byte pointer to the Part Number Data section 00h Part Number Data section not present O1h 37h Reserved 38h Part Number Data section pointer value 39h FFh Reserved TRDA Thermal Reference Data Address This location provides the offset to the Thermal Reference Data Section Writes to this register have no effect Offset 08h Bit Description 7 0 Thermal Reference Data Address Byte pointer to the Thermal Reference Data section 00h Thermal Reference Data section not present Olh 6Fh Reserved 70h Thermal Reference Data section pointer value 71h FFh Reserved FDA Feature Data Address This location provides the offset to the Feature Data Section Writes to this register have no effect Offset 09h Bit Description 7 0 Feature Data Address Byte pointer to the Feature Data section 00h Feature Data section not present Olh 73h Reserved 74h Feature Data section pointer value 75h FFh Reserved Intel Xeon Proces
29. GetTemp1 Error Code Support 104 Featl res use emendet bia en BIN ne End P PEU Pn FOL DE ben b ada Ded HE nanan af d 105 7 1 Power On Configuration Options s sssssssssssssssrrstinsrr kk kk kaka eats 105 7 2 Clock Control and Low Power Gtates IH aka kk enne nnne nnn 105 72 1 Moral States EE 106 7 2 2 HALT or Extended HALT State 106 KE EC He DN e E WEE 106 7 2 2 2 Extended HALT State 106 T23 Stop Grarit State iis oed ana banll aba E AEA dak Hel AD MERI RENE aetna 108 7 2 4 Extended HALT Snoop or HALT Snoop State Stop Grant SNOOP State EECH 109 7 2 4 1 HALT Snoop State Stop Grant Snoop State 109 7 2 4 2 Extended HALT Snoop State 109 7 3 Enhanced Intel SpeedStep Technology 109 7 4 System Management Bus SMBus Interface ccceccecece ese ee eee kk kk kk K 110 7 4 1 SMBus Device Addressing ccc cece ee een kk kak kaka 111 7 4 2 PIROM and Scratch EEPROM Supported SMBus Transachons 112 7 4 3 Processor Information ROM PIROM hw kk kk kk kk kya kak 113 FASA TE TEE 115 7 4 3 2 Processor Data iss ban n diya ni saa akan a an n Wa NENNEN NENNEN NEEN 119 7 4 3 3 Processor Core Data 121 FAZA Gache RE 124 7 4 3 5 Package Data kan neainan cech he he RR Lade ER RN ek denen RE 126 7 4 3 6 Part Number Data 127 7 4 3 7 Thermal Reference Data 129 7 4 3 8 Feature Data 130 7 4 3 9 OD Other Data 131 quA OhecksulTiS aana aa eeu dotem Ee ra ratios ni
30. MB or 2000h for 8 MB Offset 29h 2Ah Bit Description 15 0 L3 Cache Size 0000h FFFFh KB MAXCVI D Maximum Cache VID This location contains the maximum Cache VID Voltage Identification voltage that may be requested via the CVID pins This field rounded to the next thousandth is in mV and is reflected in hex Writes to this register have no effect Example The Intel Xeon Processor 7400 Series does not utilize a Cache VID Offset 2B 2Ch will contain 0000h 0 decimal Offset 2Bh 2Ch Bit Description 15 0 Maximum Cache VID 0000h FFFFh mV MI NCV Minimum Cache Voltage This location contains the minimum Cache voltage This field rounded to the next thousandth is in mV and is reflected in hex The minimum Veacu_e reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw for two processors Writes to this register have no effect Example The Intel Xeon Processor 7400 Series does not utilize a Cache VID Offset 2D 2Eh will contain 0000h 0 decimal Offset 2Dh 2bh Bit Description 15 0 Minimum Cache Voltage 0000h FFFFh mV Intel Xeon Processor 7400 Series Datasheet 125 7 4 3 4 6 7 4 3 4 7 7 4 3 5 7 4 3 5 1 126 intel RES4 Reserved 4 These locations are reserved Writes to this register have no effect Offset 2Fh 30h Bit Description 15 0 RESERVED 4
31. Min Typ Max Unit Notes X7460 Processor during active thermal control circuit TCC Itcc Icc for a Intel Xeon 130 A Processor E7400 Series during active thermal control circuit TCC Ircc Icc for an 6 core Intel 85 A Xeon Processor L7400 Series during active thermal control circuit TCC Itcc Icc for an 4 core Intel 65 A Xeon Processor L7400 Series during active thermal control circuit TCC Notes 1 Unless otherwise noted all specifications in this table apply to all processors 2 The voltage specification requirements are measured across the VCC SENSE and VSS SENSE pins and with an oscilloscope set to 100 MHz bandwidth 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 3 The processor must not be subjected to any static Vcc level that exceeds the Vcc max associated with any particular current Failure to adhere to this specification can shorten processor lifetime 4 lec max Specification is based on maximum V c loadline Refer to Figure 2 4 for details The processor is capable of drawing Icc max for up to 10 ms Refer to Figure 2 1 Figure 2 2 or Figure 2 3for further details on the average processor current draw over various time durations 5 FMB is the flexible motherboard guideline These guidelines are for estimati
32. Offset 36h Bit Description 7 0 RESERVED 5 OOh FFh Reserved PDCKS Package Data Checksum This location provides the checksum of the Package Data Section Writes to this register have no effect Offset 37h Bit Description 7 0 Package Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Part Number Data This section provides traceability There are 208 available bytes in this section for future use PPN Processor Part Number This location contains seven ASCII characters reflecting the Intel part number for the processor This information is typically marked on the outside of the processor If the part number is less than 7 characters a leading space is inserted into the value The part number should match the information found in the marking specification found in Section 3 Writes to this register have no effect Example A processor with a part number of 80546KF will have data found at offset 38 3Eh is 38h 30h 35h 34h 36h 4Bh 46h Offset 38h 3Eh Bit Description 4F 48 Character 7 ASCII character or 20h OOh OFFh ASCII character 47 40 Character 6 ASCII character or 20h OOh OFFh ASCII character 39 32 Character 5 ASCII character or 20h OOh OFFh ASCII character 31 24 Character 4 ASCII character OOh OFFh ASCII character Intel Xeon Processor 740
33. Other V3 Vss Power Other Y11 DSTBP3 Source Sync Input Output VA Vcc Power Other Y12 DSTBN3 Source Sync Input Output V5 Vss Power Other Y13 Vss Power Other V6 Vcc Power Other Y14 DSTBP2 Source Sync Input Output V7 Vss Power Other Y15 DSTBN2 Source Sync Input Output V8 Vcc Power Other Y16 Vcc Power Other Intel Xeon Processor 7400 Series Datasheet 77 intel Pin Listing Table 4 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Sheet 11 of 14 Sheet 12 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type Y17 DSTBP1 Source Sync Input Output AA30 Vss Power Other Y18 DSTBN1 Source Sync Input Output AA31 Mee Power Other Y19 Vss Power Other AB1 Vss Power Other Y20 DSTBPO Source Sync Input Output AB2 Vcc Power Other Y21 DSTBNO Source Sync Input Output AB3 BSEL1 Power Other Output Y22 Vcc Power Other AB4 Reserved Y23 D5 Source Sync Input Output AB5 Vss Power Other Y24 D2 Source Sync Input Output AB6 D63 Source Sync Input Output Y25 Vss Power Other AB7 PWRGOOD Async GTL Input Y26 DO Source Sync Input Output AB8 Vcc Power Other Y27 Reserved AB9 D I 3 Source Sync Input Output Y28 Reserved AB10 D55 Source Sync Input Output Y29 Reserved AB11 Vss Power Other Y30 Vcc
34. Other Vcc P30 Power Other Vcc W29 Power Other Vcc R1 Power Other Vcc W31 Power Other Vcc R3 Power Other Vcc Y2 Power Other Vcc R5 Power Other Vcc Y16 Power Other Vcc R7 Power Other Vcc Y22 Power Other Vcc R9 Power Other Vcc Y30 Power Other Vcc R23 Power Other Vcc AAT Power Other Vcc R25 Power Other Vcc AA6 Power Other Vcc R27 Power Other Vcc AA20 Power Other Vcc R29 Power Other Vcc AA26 Power Other Vcc R31 Power Other Vcc AA31 Power Other Vcc T2 Power Other Vcc AB2 Power Other Vcc T4 Power Other Vcc AB8 Power Other Vcc T6 Power Other Vcc AB14 Power Other Vcc T8 Power Other Vcc AB18 Power Other Vcc T24 Power Other Vcc AB24 Power Other Vcc T26 Power Other Vcc AB30 Power Other Intel Xeon Processor 7400 Series Datasheet 69 intel Table 4 1 Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 11 of 16 Sheet 12 of 16 Pin Name he a Direction Pin Name N N Direction We Tac Power Other Vss El Power Other Vcc AC16 Power Other Vss E9 Power Other Vcc AC22 Power Other Vss E15 Power Other Vcc AC31 Power Other Vss E17 Power Other Vcc AD2 Power Other Vss E23 Power Other Vcc AD20 Power Other Vss E29 Power Other Vcc AD26 Power Other Vss E31 Power Other Vcc AE14
35. Power Other AB12 D51 Source Sync Input Output Y31 BSEL2 Power Other Output AB13 D52 Source Sync Input Output AAL Mee Power Other AB14 Mee Power Other AA2 Vss Power Other AB15 D37 Source Sync Input Output AA3 BSELO Power Other Output AB16 D32 Source Sync Input Output AAA BPMbO Common Clk Input Output AB17 D31 Source Sync Input Output AA5 Reserved AB18 Mee Power Other AA6 Vcc Power Other AB19 D14 Source Sync Input Output AAT Vit Power Other AB20 D12 Source Sync Input Output AA8 D61 Source Sync Input Output AB21 Vss Power Other AA9 Vss Power Other AB22 D13 Source Sync Input Output AA10 D54 Source Sync Input Output AB23 D9 Source Sync Input Output AA11 D53 Source Sync Input Output AB24 Mee Power Other AA12 vr Power Other AB25 D8 Source Sync Input Output AA13 D48 Source Sync Input Output AB26 D7 Source Sync Input Output AA14 D49 Source Sync Input Output AB27 Mes Power Other AA15 Vss Power Other AB28 SM_EP_A2 SMBus Input AA16 D33 Source Sync Input Output AB29 SM EP Al SMBus Input AA17 Vss Power Other AB30 Mee Power Other AA18 D24 Source Sync Input Output AB31 Vss Power Other AA19 D15 Source Sync Input Output AC1 BPMb1 Common Clk J Output AA20 Vcc Power Other AC2 Vss Power Other AA21 D11 Source Sync Input Output AC3 Vcc Power Other AA22 D10 Source Sync Input Output ACA Ver Power Other AA23 Vss Power Other AC5 D60 Source Sync Input Output AA24 D6 Source Syn
36. Processor 7400 Series will include manageability features Components of the manageability features include an OEM EEPROM and Processor Information ROM which are accessed through an SMBus interface and contain information relevant to the particular processor and system in which it is installed The Intel Xeon Processor 7400 Series is packaged in a 604 pin Flip Chip Micro Pin Grid Array FC mPGA8 package and utilizes a surface mount Zero Insertion Force ZIF mPGA604 socket The Intel Xeon Processor 7400 Series supports 40 bit addressing 10 Processor Features of Processor L1 Cache per Total L2 Advanced Total L3 Shared Front Side Bus Pack Cores Core Transfer Cache Cache 1 Transfer Rate aexage 4or6 32 KB 6M or 9M 12M or 16M 1066 MTS FC mPGA8 instruction Shared L2 Cache 32 KB data Notes 1 Total accessible size of the L3 cache may vary by up to thirty two 32 cache lines 64 bytes per line depending on usage and operating environment 2 Total accessible size of L2 caches may vary by one cache line pair 128 bytes per core depending on usage and operating environment Intel Xeon Processor 7400 Series based platforms implement independent core voltage Vcc power planes for each processor FSB termination voltage Vr is shared and must connect to all FSB agents The processor core voltage utilizes power delivery guidelines specified by VRM EVRD 11 0 and its associated load line see Voltage
37. SMBus Signal Group AC Specifications T Parameter Min Max Unit Figure Notes 1 2 T90 SM_CLK Frequency 10 100 KHz T91 SM_CLK Period 10 100 us T92 SM CLK High Time 4 0 N A us 2 18 T93 SM CLK Low Time 4 7 N A us 2 18 T94 SMBus Rise Time 0 02 1 0 us 2 18 3 T95 SMBus Fall Time 0 02 0 3 us 2 18 3 T96 SMBus Output Valid Delay 0 1 4 5 us 2 19 T97 SMBus Input Setup Time 250 N A ns 2 18 T98 SMBus Input Hold Time 300 N A ns 2 18 T99 Bus Free Time 4 7 N A us 2 18 4 5 T100 Hold Time after Repeated Start Condition 4 0 N A us 2 18 T101 Repeated Start Condition Setup Time 4 7 N A us 2 18 T102 Stop Condition Setup Time 4 0 N A us 2 18 Notes 1 These parameters are based on design characterization and are not tested 2 All AC timings for the SMBus signals are referenced at Vu max Or Vi_ min and measured at the processor pins Refer to Figure 2 19 i i 40 Intel Xeon Processor 7400 Series Datasheet n Electrical Specifications n tel 2 14 Note Figure 2 7 Rise time is measured from Vi max 0 15V to Vi M n 0 15V Fall time is measured from 0 9 SM VCC to Vi max 0 15V DC parameters are specified in Table 2 26 Minimum time allowed between request cycles Following a write transaction an internal write cycle time of 10ms must be allowed before starting the next transaction Processor AC Timing Waveforms The following figures are used i
38. SM_EP_A2 SM EP A1 SM EP AO bits 7 4 bit 3 bit 2 bit 1 bit 0 AOh A1h 1010 0 0 0 X A2h A3h 1010 0 0 1 X A4h A5h 1010 0 1 0 X A6h A7h 1010 0 1 1 X A8h A9h 1010 1 0 0 X AAh ABh 1010 1 0 1 X ACh ADh 1010 1 1 0 X AEh AFh 1010 1 1 1 X Note 1 This addressing scheme will support up to 8 processors on a single SMBus 7 4 2 PI ROM and Scratch EEPROM Supported SMBus Transactions The Processor Information ROM PIROM responds to two SMBus packet types Read Byte and Write Byte However since the PIROM is write protected it will acknowledge a Write Byte command but ignore the data The Scratch EEPROM responds to Read Byte and Write Byte commands Table 7 4 diagrams the Read Byte command Table 7 5 diagrams the Write Byte command Following a write cycle to the scratch ROM software must allow a minimum of 10 ms before accessing either ROM of the processor In the tables S represents the SMBus start bit P represents a stop bit R represents a read bit W represents a write bit A represents an acknowledge ACK and represents a negative acknowledge NACK The shaded bits are transmitted by the Processor Information ROM or Scratch EEPROM and the bits that aren t shaded are transmitted by the SMBus host controller In the tables the data addresses indicate 8 bits The SMBus host controller should transmit 8 bits with the most significant bit indicating which section of the EEPROM is to be addressed the Proce
39. Series Datasheet
40. Vcc Power Other P28 Vcc Power Other M8 Vss Power Other P29 Vss Power Other M9 Vcc Power Other P30 Vcc Power Other M23 vce jPower Oter P31 Vss Power Other M24 Vss Power Other R1 Vcc Power Other M25 Vcc Power Other R2 Vss Power Other M26 Vss Power Other R3 Vcc Power Other M27 Vcc Power Other R4 Vss Power Other M28 Vss Power Other R5 Vcc Power Other M29 Vcc Power Other R6 Vss Power Other M30 Vss Power Other R7 Vcc Power Other M31 Vcc Power Other R8 Vss Power Other N1 Vcc Power Other R9 Vcc Power Other N2 Vss Power Other R23 Vcc Power Other N3 Vcc Power Other R24 Vss Power Other NA Vss Power Other R25 Vcc Power Other N5 Vcc Power Other R26 Vss Power Other N6 Vss Power Other R27 Vcc Power Other N7 Vcc Power Other R28 Vss Power Other N8 Vss Power Other R29 Vcc Power Other N9 v amp Powr the R30 Vss Power Other N23 ve jPowe yOter R31 Vcc Power Other 76 Intel amp Xeon Processor 7400 Series Datasheet intel Pin Listing Table 4 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Sheet 9 of 14 Sheet 10 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type T1 Vss Power Other v9 Vss Power Other T2 Vcc Power Other V23 Vss Power Other T3 Vss Power Other V24 Vcc Power Other
41. breakpoint and performance BPMb 2 1 O monitor signals They are additional outputs from the processor which indicate the BPMb0 1 0 status of breakpoints and programmable counters used for monitoring processor performance BPMb 3 0 should connect the appropriate pins of all FSB agents BPRI I BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connect the appropriate pins of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BR 1 0 1 0 The BR 1 0 signals are sampled on the active to inactive transition of RESET The signal which the agent samples asserted determines its agent ID BRO drives the BREQO signal in the system and is used by the processor to request the bus These signals do not have on die termination and must be terminated BSEL 2 0 O The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processors chipset and clock synthesizer All FSB agents must operate at the same frequency For more info
42. constraints on the debug port that must be followed The mechanical constraint requires the debug port connector to be installed in the system with adequate physical clearance Electrical constraints exist due to the mixed high and low speed signals of the debug port for the processor While the J TAG signals operate at a maximum of 75 MHz the execution signals operate at the common clock FSB frequency The functional constraint requires the debug port to use the J TAG system via a handshake and multiplexing scheme In general the information in this chapter may be used as a basis for including all run control tools in Intel Xeon Processor 7400 Series based systems designs including tools from vendors other than Intel The debug port and J TAG signal chain must be designed into the processor board to utilize the XDP for debug purposes except for interposer solutions Logic Analyzer I nterface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Intel Xeon Processor 7400 Series systems Tektronix and Agilent should be contacted to obtain specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Intel Xeon Processor 7400 Series based multiprocessor systems the LAI is critical in providing the ability to probe and capture FSB
43. continued by reasserting HIT and HITM together IERR O IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep ERR asserted until the assertion of RESET This signal does not have on die termination 84 Intel Xeon Processor 7400 Series Datasheet Signal Definitions Table 5 1 Signal Definitions Sheet 5 of 8 intel Name IGNNE Z Type l Description IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNEZ is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNEZ has no effect when the NE bit in control register 0 CRO is set IGNNEZ is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction Notes INIT LINT 1 0 INIT Initialization when asserted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then be
44. event will be recognized upon return to the Normal state While in Stop Grant state the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus The PBE signal can be driven when the processor is in Stop Grant state PBE will be asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state Extended HALT Snoop or HALT Snoop State Stop Grant Snoop State The Extended HALT Snoop state is used in conjunction with the Extended HALT state If the Extended HALT state is not enabled in the BIOS the default Snoop state entered will be the HALT Snoop state Refer to the sections below for details on HALT Snoop state Stop Grant Snoop state and Extended HALT Snoop state HALT Snoop State Stop Grant Snoop State The processor will respond to snoop or interrupt transactions on the front side bus while in Stop Grant state or in HALT state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the proce
45. how often the PECI host will poll the processor for temperature data and the rate at which fan speed is changed Depending on the designer s specific requirements the DTS sample rate and alpha beta filter may have no effect on the fan control algorithm Intel Xeon Processor 7400 Series Datasheet m Thermal Specifications n tel 6 3 2 6 3 2 1 6 3 2 2 6 3 2 3 PECI Specifications PECI Device Address The Intel Xeon Processor 7400 Series obtains its PECI address based on the processors APIC ID 4 3 at power on APIC ID 4 3 is also known as the Cluster ID 1 0 The Cluster ID 1 0 is set by the chipset by asserting the power on configuration POC signals A 12 11 at the deassertion of RESET The PECI address for the Intel Xeon Processor 7400 Series 0x30 Cluster ID 0 1 1 The initial Cluster ID assigned to each socket must be unique to ensure a unique PECI address is assigned to each socket The Cluster ID may be changed via the XAPIC ID register The default PECI device address for the Intel 7300 chipset FSBO is 0x30 The default PECI device address for the Intel 7300 chipset FSB1 is 0x32 The default PECI device address for the Intel 7300 chipset FSB2 is 0x31 The default PECI device address for the Intel 7300 chipset FSB3 is 0x33 The power on configuration POC settings of third party chipsets may produce different PECI addresses than those shown above Thermal designers should consult their th
46. is not activated below maximum Tcase when dissipating TDP power There is no defined or fixed correlation between the PROCHOT trip temperature or the case temperature Thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of TcASE or PROCHOT FORCEPR Signal The FORCEPRZ force power reduction input can be used by the platform to cause the Intel Xeon Processor 7400 Series to activate the TCC If the Intel Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal Assertion of the FORCEPR signal will activate TCC for all processor cores The TCC will remain active until the system deasserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system components To use the VR as an example when FORCEPR is asserted the TCC circuit in the processor will activate reducing the current consumption of the processor and the corresponding temperature of the VR It should be noted that assertion of FORCEPR does not automatically assert PROCHOT As mentioned previously the PROCHOT signal is asserted when a high temperature situation is detected A minimum pulse width of 500 us is recommended when FORCEPR is asserted by the system Sustained activation of the FORCEPR signal may cause noticeable platform performance degradation Refer to the Caneland Platform Design Guide for details on implement
47. output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 9 and Table 2 10 while AC specifications are included in Table 2 25 Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable Intel Xeon Processor 7400 Series Datasheet n Electrical Specifications n tel Table 2 3 Voltage Identification Definition VI D6 VI D5 VI D4 VI D3 VID2 VID1 VID6 VID5 VID4 VID3 VID2 VID1 HEX 400 200 100 50 25 12 5 Vcc Max HEX 400 200 100 50 25 12 5 Nee wax mV mV mV mV mV mV mV mV mV mV mV mV 7A 1 1 1 1 0 1 0 8500 3C 0 1 1 1 di 0 1 2375 78 1 1 1 1 0 0 0 8625 3A 0 1 1 1 0 al 1 2500 76 1 1 1 0 1 1 0 8750 38 0 1 1 1 0 0 1 2625 74 1 1 1 0 1 0 0 8875 36 0 1 1 0 1 1 1 2750 72 1 1 1 0 0 1 0 9000 34 0 1 1 0 1 0 1 2875 70 1 1 1 0 0 0 0 9125 32 0 1 1 0 0 1 1 3000 6E 1 1 0 1 1 1 0 9250 30 0 al 1 0 0 0 1 3125 6C 1 1 0 1 1 0 0 9375 2E 0 1 0 1 1 1 1 3250 6A 1 1 0 1 0 1 0 9500 2C 0 1 0 1 1 0 1 3375 68 1 1 0 d 0 0 0 9625 2A 0 1 0 1 0 1 1 3500 66 1 1 0 0 1 1 0 9750 28 0 1 0 1 0 0 1 3625 64 1 1 0 0 1 0 0 9875 26 0 1 0 0 1 il 1 3750 62
48. receiver Te T 4 T 2 3T 4 H ji i i H 1 T 1 i i valid Tp T1 BCLK 1 0 Period valid Ty T23 Source Sync Address Output Valid Before Address Strobe Ty T24 Source Sync Address Output Valid After Address Strobe Tk T27 Source Sync Address Strobe Setup Time to BCLK Tm T25 Source Sync Input Setup Time Tn T26 Source Sync Input Hold Time Ts T20 Source Sync Output Valid Delay Tr 131 Address Strobe Output Valid Delay Intel Xeon Processor 7400 Series Datasheet Electrical Specifications Figure 2 14 FSB Source Synchronous 4X Data Timing Waveform TO BCLK1 T4 Ty 3T 4 Ti BCLKO DSTBp driver DSTBn driver D driver gt DSTBp receiver DSTBn receiver D receiver Te T1 BCLK 1 0 Period Ta T21 Source Sync Data Output Valid Delay Before Data Strobe Tg T22 Source Sync Data Output Valid Delay After Data Strobe Tc T28 Source Sync Data Strobe Setup Time to BCLK Tp T30 Data Strobe n DSTBN Output Valid Delay Te T25 Source Sync Input Setup Time Tg T26 Source Sync Input Hold Time Ty T20 Source Sync Data Output Valid Delay Intel Xeon Processor 7400 Series Datasheet 45 E e n tel Electrical Specifications Figure 2 15 TAP Valid Delay Timing Waveform
49. see e Pra se lete ben b be beben Ee ege 13 1 3 References EE 13 2 Electrical Specifications oss e bsp ud e efe WA ed XR NEEN ANNER EN 15 2 1 Front Side Bus and GTLREF sssssssssssese mem k y ka yaka kaka aka 15 2 2 Decoupling G ldelines iioi ee Petite oem b ba ENEE camas ban e Feed E 16 22 1 VCCIDECOUDIING DEET 16 2 2 2 WIT Decoupling 5 5 xu 5y aba e een nn EEN EES 16 2 2 3 Front Side Bus AGTL Decoupling cece eee eee mme 16 2 3 Front Side Bus Clock BCLK 1 0 and Processor Cocking esses 16 2 3 1 Front Side Bus Frequency Select Signals BSEL 2 0 EE 17 2 3 2 PLL Power SUpply creo trie Rer mne etl rex Sie Ee pucr exu inte binas 18 2 4 Voltage Identification ID 18 2 5 Reserved Unused or Test Gionals nmm memes 20 2 6 Front Side Bus Signal Groups 20 2 7 CMOS Asynchronous and Open Drain Asynchronous Gionals este ee ea ee 22 2 8 Test Access Port TAP Connection 22 2 9 Mgr Oe DES Ae Sege Eege EE geleed SES 23 2 10 Absolute Maximum and Minimum Rating 23 2 11 Processor DC Specifications cee emen nns 24 2 11 1 Flexible Motherboard Guidelines FMB semen 24 2 11 2 Vee Ov rshoot Specification eim dala a cen o a ene n I RC nea 33 2 11 3 Die Voltage Validation eene n sil ya xime kan kd SEENEN ced e w k Wad wed pe ei 33 2 11 4 Platform Environmental Control Interface PECI DC Specifications 34 2 11 4 T DC CharactenStiCS EE 34 2 11
50. signals There are two sets of considerations to keep in mind when designing a Intel Xeon Processor 7400 Series based system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI plugs into the socket while the processor plugs into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system In some cases it is known that some of the electrolytic capacitors fall inside of the keepout volume for the LAI In this case it is necessary to move these capacitors to the backside of the board before using the LAI Additionally note that it is possible that the keepout volume reserved for the LAI may include Intel Xeon Processor 7400 Series Datasheet 133 e n tel Debug Tools Specifications different requirements from the space normally occupied by the heatsink If this is the case the logic analyzer vendor will provide either a cooling solution as part of the LAI or additional hardware to mount the existing cooling solution 8 2 2 Electrical Considerations The LAI will also affect the ele
51. the lowest supported bus ratio 1 8 for the Intel Xeon Processor 7400 Series When the TCC is activated the processor automatically transitions to the new frequency This transition occurs rapidly on the Intel Xeon Processor 7400 Series Datasheet m Thermal Specifications n tel Figure 6 7 6 2 4 order of 5 us During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps in order to support Intel Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will be one VID table entry see Table 2 3 The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has exp
52. the pin Intel Xeon Processor 7400 Series Datasheet 31 intel Table 2 12 CMOS Signal I nput Output Group DC Specifications Table 2 13 Table 2 14 32 Electrical Specifications Symbol Parameter Min Typ Max Units Notes Vu Input Low Voltage 0 10 0 00 0 3 V V 2 Vin Input High Voltage 0 7 Vir Ver Vrrt l V 2 VoL Output Low Voltage 0 10 0 0 1 V V 2 Vou Output High Voltage 0 9 Vir Ver Vrr 0 1 V 2 lot Output Low Current 1 70 N A 4 70 mA 3 lou Output High Current 1 70 N A 4 70 mA 4 lu Input Leakage Current N A N A 100 HA 5 6 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vr referred to in these specifications refers to instantaneous Vtr 3 Measured at 0 1 Vy 4 Measured at 0 9 Vr 5 For Vin between 0 V and Ver Measured when the driver is tristated 6 This is the measurement at the pin Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes VoL Output Low Voltage N A 0 20 V Vou Output High Voltage Vr 5 Vr Vr 5 V 3 lot Output Low Current 16 N A 50 mA 2 lio Leakage Current N A N A x 200 H 4 5 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at 0 2 V m 3 Voy is determined by value of the external pullup resistor to Vy Please ref
53. this register have no effect Example A processor with a S Spec mark of SLA67 contains the following in field OE 13h 20h 53h 4Ch 41h 36h 37h This data consists of one blank at OEh followed by the ASCII codes for SLA67 in locations 10 13h Intel Xeon Processor 7400 Series Datasheet 119 7 4 3 2 2 120 Features Offset OEh 13h Bit Description 47 40 Character 6 S SPEC character or 20h OOh OFFh ASCII character 39 32 Character 5 S SPEC character or 20h OOh OFFh ASCII character 31 24 Character 4 S SPEC character OOh OFFh ASCII character 23 16 Character 3 S SPEC character OOh OFFh ASCII character 15 8 Character 2 S SPEC character OOh OFFh ASCII character 7 0 Character 1 S SPEC character OOh OFFh ASCII character SAMPROD Sample Production This location contains the sample production field which is a two bit field and is LSB aligned All Q spec material will use a value of 00b All S spec material will use a value of O1b All other values are reserved Writes to this register have no effect Example A processor with a Qxxx mark engineering sample will have offset 14h set to 00h A processor with an Sxxxx mark production unit will use O1h at offset 14h Offset 14h Bit Description 7 2 RESERVED 000000b 111111b Reserved 1 0 Sample Production Sample or Production indictor 00b Sample 01b Production 10b
54. 0 Series Datasheet 127 7 4 3 6 2 7 4 3 6 3 7 4 3 6 4 128 Offset 38h 3Eh Bit Description 23 16 Character 3 ASCII character OOh OFFh ASCII character 15 8 Character 2 ASCII character OOh OFFh ASCII character 7 0 Character 1 ASCII character OOh OFFh ASCII character RES6 Reserved 6 This location is reserved Writes to this register have no effect Offset 3Fh 4Ch Bit Description 111 0 RESERVED 6 PS ESIG Processor Serial Electronic Signature Features This location contains a 64 bit identification number The value in this field is either a serial signature or an electronic signature Bits 5 amp 6 of the Processor Feature Flags Offset 78h indicates which signature is present Intel does not guarantee that each processor will have a unique value in this field Writes to this register have no effect Offset 4Dh 54h Bit Description 63 0 Processor Serial Electronic Signature 00000000h FFFFFFFFh Electronic Signature RES7 Reserved 7 This location is reserved Writes to this register have no effect Offset 55h 6Eh Bit Description 207 0 RESERVED 7 Intel amp Xeon Processor 7400 Series Datasheet Features 7 4 3 6 5 7 4 3 7 7 4 3 7 1 7 4 3 7 2 7 4 3 7 3 intel PNDCKS Part Number Data Checksum This location provides the checksum of the Part Number Data Section Writ
55. 00 350 2 300 250 200 T T T T T T T T T T T T T T T T T T 1 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg mV Intel Xeon Processor 7400 Series Datasheet Electrical Specifications Figure 2 11 BCLK Waveform at Processor Pad and Pin 08 Black is the simulated waveform at the bottom side of the via near CPU SKT Blue is the simulated waveform at the CPU PAD e 0 6 04 DER fall at PAD Ba DER rise atPAD PP P XD em 2 5967g slew 2 6719g S x 0 0 02 D ue axp DER rise at PIN DER fall at PN slew 892 16 slew 906 3meg 04 0 6 lt gt lt gt 08 Notes 1 Waveform at pin is non monotonic Waveform at pad is monotonic 2 Differential Edge Rate DER measured zero 200mv 3 g indicates Vins units and meg indicates mv ns units 4 Waveform at pad has faster edge rate than at pin Figure 2 12 FSB Common Clock Valid Delay Timing Waveform TO T1 BCLK1 BCLKO T2 Common Clock Signal driver Common Clock Signal receiver T T10 Common Clock Output Valid Delay Tg T11 Common Clock Input Setup Tp T12 Common Clock Input Hold Time Intel Xeon Processor 7400 Series Datasheet 43 intel Electrical Specifications Figure 2 13 FSB Source Synchronous 2X Address Timing Waveform 44 BCLK1 BCLKO ADSTB driver A driver ADSTB receiver At
56. 00 Series Datasheet Revision History Document Revision Description Date Number 320335 001 Initial Release September 2008 320335 002 Updated Power Information September 2008 320335 003 Add Boxed Processor Information October 2008 Intel Xeon Processor 7400 Series Datasheet Intel Xeon Processor 7400 Series Datasheet intel l Introduction ALL INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE The Intel Xeon Processor 7400 Series is a four or six core product for multi processor servers The processor is a single die based on Intel s 45 nanometer process technology combining high performance with the power efficiencies of a low power microarchitecture The processor maintains the tradition of compatibility with A 32 software Some key features include on die 32 KB Level 1 instruction data cache per core and 3 MB of shared Level 2 cache per two processor cores with Advanced Transfer Cache Architecture The Intel Xeon Processor 7400 Series will be available with 12 MB or 16 MB of on die level 3 L3 cache The processor s Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs resulting in reduced bus cycle penalties and improved performance The 1066 MTS Front Side Bus FSB is a quad pumped bus running off a 266 MHz system clock making 8 5 GBytes per second data transfer rates possible Enhanced thermal and power management capabilities ar
57. 000000 O 00 339899 H Zeen 000000 KA Sg E i w O 310H NYHL ONILNMOW YOSSIJOYd In 400r i NERT en 9 DI Xv aJ 6010 9 1 Nid 1394208 006 j _________jj r INI 1100 XNISIV3H 6 88 e 1N3AQ20Q 31vuvdiS NO NMOHS 38 11IM 1n0d339 NOI1V10938 39V110A Q31V8931NI 3oN38343U 404 NMOHS QYYOG IS3L beten ier LMOAWT AVM Z ONY v09 139208 NO Q3SV8 SNOISN3WIQ H 001 S3HONI NI Q31VIS SNOISN3NIQ 9666 031342VU8 SU313WNI T1IW NI Q31VIS SNOISNIWIG ANVWIUd E q v661 S VIA ISNV 1d SJ NYYJIOL ONY NOISN3NIQ 11 Z F114 03114405 YIAO 32N30303ud IVVL ONIMVYG SIHL NO S32Nv83101 ONY SNOISN3WIQ TV F114 3Sv8vivd QE Gil TddN HLIM NOI1VI3UH0D NI Q3S 38 OL ONIMVEG SIHI I L sou as 262811 on 55 Intel Xeon Processor 7400 Series Datasheet Mechanical Specifications Top Side Board Keepout Zones Part 2 Intel Xeon Processor 7400 Series Datasheet c v S 9 d 8 EES m Tree YE TEYE YINE are 3037705 e
58. 00h if not present Address 05h 8 L3 Cache Data Address Byte pointer 00h if not present 06h 8 Package Data Address Byte pointer 00h if not present 07h 8 Part Number Data Address Byte pointer 00h if not present 08h 8 Thermal Reference Data Byte pointer 00h if not present Address 09h 8 Feature Data Address Byte pointer 00h if not present OAh 8 Other Data Address Byte pointer 00h if not present OB OCh 16 Reserved Reserved ODh 8 Checksum 1 byte checksum Processor Data OE 13h 48 S spec Number Six 8 bit ASCII characters 14h 6 Reserved Reserved most significant bits 2 Sample Production 00b Sample 01b Production 15h 8 Checksum 1 byte checksum Processor Core Data 16 19h 2 Reserved Reserved for future use 8 Extended Family From CPUID 4 Extended Model From CPUID Intel Xeon Processor 7400 Series Datasheet 113 intel Table 7 6 114 Features Processor Information ROM Data Sections Sheet 2 of 3 Offset Section edid Function Notes 2 Reserved Reserved for future use 2 Processor Core Type From CPUID 4 Processor Core Family From CPUID 4 Processor Core Model From CPUID 4 Processor Core Stepping From CPUID 2 Reserved Reserved for future use 1A 1Bh 16 Front Side Bus Speed 16 bit binary number in MTS 1Ch 2 Multiprocessor Support 00b UP 01b DP 10b RSVD 11b MP 6 Reserved Reserved 1D 1Eh 16 Maximum Co
59. 075 VID 0 090 VID 0 105 1 2 65 VID 0 081 VID 0 096 VID 0 111 1 2 3 70 VID 0 088 VID 0 103 VID 0 118 1 2 75 VID 0 094 VID 0 109 VID 0 124 1 2 3 80 VID 0 100 VID 0 115 VID 0 130 1 2 3 85 VID 0 106 VID 0 121 VID 0 136 1 2 3 90 VID 0 113 VID 0 128 VID 0 143 1 2 3 95 VID 0 119 VID 0 134 VID 0 149 1 2 100 VID 0 125 VID 0 140 VID 0 155 1 2 3 4 105 VID 0 131 VID 0 146 VID 0 161 1 2 3 4 110 VID 0 138 VID 0 153 VID 0 168 1 2 3 4 115 VID 0 144 VID 0 159 VID 0 174 1 2 3 4 120 VID 0 150 VID 0 165 VID 0 180 1 2 3 4 125 VID 0 156 VID 0 171 VID 0 186 1 2 3 4 130 VID 0 163 VID 0 178 VID 0 193 1 2 3 4 135 VID 0 169 VID 0 184 VID 0 199 1 2 3 4 5 140 VID 0 175 VID 0 190 VID 0 205 1 2 3 4 5 145 VID 0 181 VID 0 201 VID 0 221 1 2 3 4 5 150 VID 0 188 VID 0 208 VID 0 228 1 2 3 4 5 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 11 2 for Vcc overshoot specifications 2 This table is intended to aid in reading discrete points on Figure 2 4 for Intel Xeon Processor 7400 Series 3 The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE pins and across the VCC_SENSE2 and VSS SENSE2 pins Voltage regulation feedback for voltage regulator circuits must also be taken from the processor VCC SENSE2 and VSS SENSE2 pins Refer to the Voltage Regulator Module VRM and
60. 1 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation 5 Icc values greater than 95 A are not applicable for the Ultra Dense Intel Xeon Processor 7400 Series 6 Icc values greater than 130 A are not applicable for the Rack Optimized Intel Xeon Processor 7400 Series Table 2 11 AGTL Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes VIL Input Low Voltage 0 10 0 GTLREF 0 10 V 2 4 6 Vin Input High Voltage GTLREF 0 10 Vit V r 0 10 V Vou Output High Voltage Ver 0 10 N A Vr V 4 6 RoN Buffer On Resistance 7 9 11 Q 5 lu Input Leakage Current N A N A 100 uA 7 8 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vu is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 Viu is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 This is the pull down driver resistance Measured at 0 33 V7 Refer to processor I O Buffer Models for I V characteristics 5 GTLREF should be generated from V7 with a 196 tolerance resistor divider The V r referred to in these specifications is the instantaneous Vr 6 Specified when on die Ry and Roy are turned off Viy between 0 and Var 7 This is the measurement at
61. 1 1 0 0 0 1 1 0000 24 0 1 0 0 1 0 1 3875 60 1 1 0 0 0 0 1 0125 22 0 al 0 0 0 al 1 4000 5E 1 0 1 1 di 1 1 0250 20 0 1l 0 0 0 0 1 4125 5C il 0 1 1 1 0 1 0375 1E 0 0 1 1 1 1 1 4250 5A 1 0 1 1 0 1 1 0500 LC 0 0 1 1 1 0 1 4375 58 1 0 1 1 0 0 1 0625 1A 0 0 1 il 0 1 1 4500 56 1 0 1 0 1 1 1 0750 18 0 0 1 1 0 0 1 4625 54 1 0 1 0 di 0 1 0875 16 0 0 1 0 1 1 1 4750 52 1 0 1 0 0 1 1 1000 14 0 0 1 0 1 0 1 4875 50 1 0 1 0 0 0 1 1125 12 0 0 1 0 0 1 1 5000 4E 1 0 0 1 1 1 1 1250 10 0 0 1 0 0 0 1 5125 4C 1 0 0 1 1 0 1 1375 OE 0 0 0 1 1 1 1 5250 4A 1 0 0 1 0 1 1 1500 0C 0 0 0 1 1 0 1 5375 48 1 0 0 1 0 0 1 1625 0A 0 0 0 1 0 1 1 5500 46 1 0 0 0 di di 1 1750 08 0 0 0 1 0 0 1 5625 44 1 0 0 0 1 0 1 1875 06 0 0 0 0 1 1 1 5750 42 1 0 0 0 0 1 1 2000 04 0 0 0 0 1 0 1 5875 40 1 0 0 0 0 0 1 2125 02 0 0 0 0 0 1 1 6000 3E 0 1 1 1 1 1 1 2250 00 0 0 0 0 0 0 OFF1 Notes 1 When this VID pattern is observed the voltage regulator output should be disabled 2 Shading denotes the expected VID range of the Intel Xeon Processor 7400 Series 3 The VID range includes VID transitions that may be initiated by thermal events assertion of the FORCEPR signal see Section 6 2 3 Extended HALT state transitions see Section 7 2 2 or Enhanced Intel SpeedStep Technology transitions see Section 7 3 The Extended HALT state must be enabled for the processor to remain within its specifications 4 Once the VRM EVRD is operating after power up if either the Output Enable signal is d
62. 2 VTT_SEL Power Other Output A3 SKTOCC Power Other Output A4 Vit Power Other A5 Vss Power Other A6 A32 Source Sync Input Output A7 A33 Source Sync Input Output A8 Vcc Power Other A9 A26 Source Sync Input Output A10 A20 Source Sync Input Output A11 Vss Power Other A12 Al4 Source Sync Input Output A13 A10 Source Sync Input Output A14 Vcc Power Other A15 FORCEPR Async GTL Input A16 TESTHIO Power Other Input A17 LOCK Common Clk Input Output A18 Vcc Power Other A19 AIX Source Sync Input Output A20 A4 Source Sync Input Output A21 Vss Power Other A22 A33 Source Sync Input Output A23 HITM Common Clk Input Output A24 Vcc Power Other A25 TMS TAP Input A26 Vcc sENSE2 Power Other Output A27 Vss Power Other A28 Reserved A29 Vss Power Other A30 PROC IDO Power Other J Output A31 Reserved B1 Reserved B2 Vss Power Other B3 VIDA Power Other Output B4 Reserved B5 Vr Power Other B6 A38 Source Sync Input Output B7 A313 Source Sync Input Output B8 A27 Source Sync Input Output B9 Vss Power Other B10 A215 Source Sync Input Output B11 A22 Source Sync Input Output Intel Xeon Processor 7400 Series Datasheet Table 4 2 Pin Listing by Pin Number Sheet 2 of 14 Pin No Pin Name Signal Direction Buffer Type B12 Ver Power Other B13 A13 Source Sync Input Output B14 A124 Source Sync Input Output B15 Vss Power Other B16 A114 Source Sync Input Output B17 Vss Power
63. 266 666 MHz 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Intel Xeon Processor 7400 Series Datasheet 17 e n tel Electrical Specifications 2 3 2 18 PLL Power Supply An on die PLL filter solution is implemented on the processor The Vecp input is used to provide power to the on chip PLL of the processor Please refer to Table 2 9 for DC specifications Refer to the appropriate platform design guidelines for decoupling and routing guidelines Voltage Identification VI D The Voltage Identification VID specification for the processor is defined by the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins VID signals are CMOS outputs Please refer to Table 2 11 for the DC specifications for these signals A voltage range is provided in Table 2 9 and changes with frequency The specifications have been set such that one voltage regulator can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings This is reflected by the VID range values provided in Table 2 3 The processor uses six voltage identification signals VID 6 1 to support automatic se
64. 6 DFR Data Format Revision Features This location identifies the data format revision of the PIROM data structure Writes to this register have no effect Offset 00h Bit Description 7 0 Data Format Revision incremented 00h Reserved O1h Initial definition 02h Second revision 03h Third revision 04h Fourth revision Defined by this EMTS O5h FFh Reserved The data format revision is used whenever fields within the PIROM are redefined The initial definition will begin at a value of 1 If a field or bit assignment within a field is changed such that software needs to discern between the old and new definition then the data format revision field will be Example The Intel amp Xeon Processor 7400 Series will use 04h at offset 00h Changes from Third Revision 1 The Number of cores field in PTCI Processor Thread and Core Information at offset 79h was extended to six bits It now defined as Number of Core Bits 7 2 It previously was defined as Bits 3 2 PISIZE PI ROM Size This location identifies the PI ROM size Writes to this register have no effect Offset O1h 02h Bit Description 15 0 PIROM Size location O1h the LSB is at location 02h 0000h 007Fh Reserved 0080h 128 byte PIROM size 0081 FFFFh Reserved The PI ROM size provides the size of the device in hex bytes The MSB is at PDA Processor Data Address This location provides t
65. BN1 DSTBP2 DSTBN2 DSTBP3 DSTBN3 AGTL Strobes I O Open Drain Output Synchronous to BCLK 1 0 Asynchronous ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 FERR PBE IERR PROCHOT THERMTRIP TDO CMOS Asynchronous Input Asynchronous A20M FORCEPR IGNNEZ INIT LINTO INTR LINT1 NMI PWRGOOD SMI STPCLK TCK TDI TMS TRST CMOS Asynchronous Output FSB Clock Asynchronous Clock BSEL 2 0 VID 6 1 BCLK 1 0 SMBus Synchronous to SM_CLK SM_CLK SM DAT SM EP A 2 0 SM WP Power Other Power Other COMP 3 0 GTLREF_ADD_MID GTLREF_ADD_END GTLREF_DATA_MID GTLREF DAT END LL ID 1 0 PROC ID 1 0 PECI RESERVED SKTOCC SM_VCC TESTHI 1 0 TESTI N1 TESTIN2 VCC VCC SENSE VCC_SENSE2 VCCPLL VID 0 VSS_SENSE VSS SENSE2 VSS VTT VIT SEL Notes 1 Refer to Section 4 for signal descriptions 2 These signals may be driven simultaneously by multiple agents Wired OR Intel Xeon Processor 7400 Series Datasheet 21 E e n tel Electrical Specifications Table 2 5 Table 2 6 Table 2 7 2 7 2 8 22 Table 2 6 outlines AGTL signals which include on die termination RTT and those that require external termination Table 2 6 outlines non AGTL signals including open drain signals Table 2 7 provides signal reference voltages AGTL Signal Description Table AGTL signals with R77 AGTL signals with no RyT
66. C SENSE VCC SENSE2 VCC SENSE and VCC SENSE2 provides an isolated low impedance connection to the processor core power and ground This signal should be connected to the voltage regulator feedback signal which insures the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details Intel Xeon Processor 7400 Series Datasheet 87 n n tel Signal Definitions Table 5 1 Signal Definitions Sheet 8 of 8 Name Type Description Notes VID 6 1 O VID 6 1 Voltage ID pins are used to support automatic selection of power supply voltages Vcc These are CMOS signals that are driven by the processor and must be pulled up through a resistor Conversely the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are needed to support processor voltage specification variations See Table 2 3 for definitions of these pins The VR must supply the voltage that is requested by these pins or disable itself VSS_SENSE O VSS SENSE and VSS SENSE2 provides an isolated low impedance connection to VSS SENSE2 the processor core power and ground This signal should be connected to the z voltage regulator feedback signal which insures the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details
67. CLK e SM DAT e Note Actual implementation may vary This figure is provided to offer a general understanding of the architecture All SMBus pull up and pull down resistors are 10 kQ and located on the processor SMBus Device Addressing Of the addresses broadcast across the SMBus the memory component claims those of the form 1010XXXZb The XXX bits are defined by pull up and pull down resistors on the system baseboard These address pins are pulled down weakly 10 kQ on the processor substrate to ensure that the memory components are in a known state in systems which do not support the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction Note that addresses of the form 0000XXXXb are Reserved and should not be generated by an SMBus master The system designer must also ensure that their particular implementation does not add excessive capacitance to the address inputs Excess capacitance at the address inputs may cause address recognition problems Refer to the appropriate platform design guide document Figure 7 2 shows a logical diagram of the pin connections Table 7 3 describe the address pin connections and how they affect the addressing of the devices Intel Xeon Processor 7400 Series Datasheet 111 intel Table 7 3 Memory Device SMBus Addressing yog ul Device Select R W
68. Clk Input Output D31 AB17 Source Sync Input Output BR1 F12 Common Clk Input Output D32 AB16 Source Sync Input Output BSELO AA3 Power Other Output D33 AA16 Source Sync Input Output BSEL1 AB3 Power Other Output D34 AC17 Source Sync Input Output BSEL2 Y31 Power Other Output D35 AE13 Source Sync Input Output COMPO D25 Power Other Input D36 AD18 Source Sync Input Output COMP1 E16 Power Other Input D37 AB15 Source Sync Input Output COMP2 AE15 Power Other Input D38 AD13 Source Sync Input Output COMP3 AE16 Power Other Input D39 AD14 Source Sync Input Output DO Y26 Source Sync Input Output D40 AD11 Source Sync Input Output D1 AA27 Source Sync Input Output D41 AC12 Source Sync Input Output D2 Y24 Source Sync Input Output D42 AE10 Source Sync Input Output D3 AA25 Source Sync Input Output D43 AC11 Source Sync Input Output D4 AD27 Source Sync Input Output D44 AE9 Source Sync Input Output D5 Y23 Source Sync Input Output D45 AD10 Source Sync Input Output D6 AA24 Source Sync Input Output D46 AD8 Source Sync Input Output D7 AB26 Source Sync Input Output D47 AC9 Source Sync Input Output D8 AB25 Source Sync Input Output D48 AA13 Source Sync Input Output D9 AB23 Source Sync Input Output D49 AA14 Source Sync Input Output D10 AA22 Source Sync Input Output D50 AC14 Source Sync Input Output D11 AA21 Source Sync Input Output D51 AB12 Source Sync Input Output D12 AB20 Source Sync Inp
69. DATA END are the reference voltage for the FSB 4X data signals GTLREF ADD MID and GTLREF ADD END are the reference voltage for the FSB 2X address signals and common clock signals Table 2 17 lists the GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END specifications The AGTL reference voltages GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END must be generated on the baseboard using high precision voltage divider circuits Refer to the appropriate platform design guidelines for implementation details Intel Xeon Processor 7400 Series Datasheet 35 intel Table 2 17 AGTL Bus Voltage Definitions Electrical Specifications Symbol Parameter Min Typ Max Units Notes GTLREF_DATA_MID Data Bus Reference 0 98 0 67 V r 0 67 Vz 1 02 0 67 Vr V 2 3 GTLREF DATA END Voltage GTLREF ADD MID Address Bus 0 98 0 67 Var 0 67 Vr 1 02 0 67 Vir V 2 3 GTLREF ADD END Reference Voltage Ry Termination 45 50 55 Q 4 Resistance pull up COMP COMP Resistance 49 4 49 9 50 4 Q 5 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of Vj 3 GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END is generated from V on the baseboard by a voltage di
70. DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END for both 0 and 1 logic levels unless otherwise specified The timings specified in this section should be used in conjunction with the processor signal integrity models provided by Intel AGTL layout guidelines are also available in the appropriate platform design guidelines Care should be taken to read all notes associated with a particular timing parameter Front Side Bus Differential Clock AC Specifications T Parameter Min Typ Max Unit Figure Notes FSB Clock Frequency 265 247 266 666 266 745 MHz 2 T1 BCLK 1 0 Period 3 7489 3 7500 3 7700 ns 2 9 3 T2 BCLK 1 0 Period Stability 150 ps 4 5 T3 BCLK 1 0 Rise Time 700 ps 6 T4 BCLK 1 0 Fall Time 700 ps 6 Differential Rising and Falling Edge 0 6 4 V ns 7 Rates Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The processor core clock frequency is derived from BCLK The bus clock to processor core clock ratio is determined during initialization as described in Section 2 3 Table 2 1 includes core frequency to FSB multipliers 3 The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 4 Forthe clock jitter specification refer to the CK410B Clock Synthesize Driver Design Guidelines 5 In this context period sta
71. DEFER Common Clk Input E5 IERR Async GTL Output C24 TDI TAP Input E6 Vcc Power Other C25 Vss Power Other Input E7 BPM2 Common Clk Input Output C26 IGNNE Async GTL Input E8 BPM4 Common Clk Input Output C27 SMI Async GTL Input E9 Vss Power Other C28 PECI Power Other Input Output E10 APO Common Clk Input Output C29 Vss Power Other E11 Ver Power Other C30 Vcc Power Other E12 Ver Power Other C31 Reserved E13 A28 Source Sync Input Output D1 TESTIN1 Power Other Input E14 A24 Source Sync Input Output D2 Vss Power Other E15 Vss Power Other D3 VID2 Power Other Output E16 COMP1 Power Other Input D4 STPCLK Async GTL Input E17 Vss Power Other D5 Vss Power Other E18 DRDY Common Clk Input Output D6 INIT Async GTL Input E19 TRDY Common Clk Input D7 MCERR Common Clk Input Output E20 Vcc Power Other D8 Vcc Power Other E21 RSO Common Clk Input D9 AP1 Common Clk Input Output E22 HIT Common Clk Input Output D10 Ver Power Other E23 Vss Power Other D11 Vss Power Other E24 TCK TAP Input D12 A29 Source Sync Input Output E25 TDO TAP Output D13 A25 Source Sync Input Output E26 Vcc Power Other D14 Vcc Power Other E27 FERR PBE Async GTL Output D15 A18 Source Sync Input Output E28 Vcc Power Other D16 A174 Source Sync Input Output E29 Vss Power Other D17 A9 Source Sync Input Output E30 Vcc Power Other D18 Vcc Power Other E31 Vss Power Other D19 ADS Common Clk Input Output F1 Vcc Power Other D20 BRO Common Cl
72. ECK Clock VWauetortt er 42 Differential Clock Wawvefotrm si xun ikna kikan REENEN ed REENEN EE xira a sal khan ar 42 Differential Clock Crosspoint Gpechfication kk ne 42 BCLK Waveform at Processor Pad and Pin 43 FSB Common Clock Valid Delay Timing Waveform cc cece cent eee eee eee HH 43 FSB Source Synchronous 2X Address Timing Waveform eens 44 FSB Source Synchronous 4X Data Timing Wavetorm sss 45 TAP Valid Delay Timing Waveform csssssssssss meme kk e emen 46 Test Reset TRST Async GTL Input and PROCHOT Timing Waveform 46 THERMTRIP Power Down Sequence cece cette ee ee mmm enne nenne 46 SMBus TIMING NEE td ETA 47 SMBus Valid Delay Timing Waveform sssssssssssese ne meme enn 47 Voltage Sequence Timing Requirements cc cceee cetera meer 48 FERR PBE Valid Delay Timing 48 VID Step TI mln EE 49 VID Step Times and Vcc Waveforms cece nee kaka nnn 49 Processor Package Assembly Sketch 51 Intel Xeon Processor 7400 Series Package Drawing Sheet 1 of 2 52 Intel Xeon Processor 7400 Series Package Drawing Sheet 2 of 2 53 Top Side Board Keepout Zones Part II 55 Top Side Board Keepout Zones Part 2 emen 56 Bottom Side Board Keepout Zones 57 Board Mounting Hole Keepout Zones sss emen memes 58 Volumetric Height Keep Ins cs si an si ENNER ete nee na kan n k ma mi n a ka an Win mune z
73. EN mg GUTHI NOIL91YLS3Y 1H913H LN3NOdNOO ONYOGHJHION XYM WAPI ISS Q ive i9 000300 iiv aun SH Ja at ZERE Y2 YET YI yr 3m iv Y om sell SUE gy Al xwana Tal u ET Q34071V 1N3M32V14 LN3NOdNOD GYVOBYIHLON ON oS 002 92118 NOILIIYLSIY 1H9 3H LNINOdWOD XVW WW 928 G2t v3uv ATGWISSVSIG WNISLVIH 318V1 AJY YOI 9 39Vd 33S ETT EY WI ole ANOLSM _NOISIATE w013 1Y JAIS AYYNIYd NO 12181518 EM 1H913H lt NOILOIYLSIY 1H913H LNINOdNOD XVW WNI8 OSI T 0N3931 o g E 900000000000000000000000 SE H EE X 1H913H e NM 99999999999999999989999999 LA 9000000000000000000000000 GE 201 1100 WU SLY3H 0000000000000000000000000 001 1900000 9009009 n 006006 KG F C FL 0L 288999 922869 000000 9909009 B 000000 000000 9 6 ci 000000 600600 d 0061 f 6606000 000000 19 l 1 9 000000 9909009 310H BW HLIM 3NIT NI 399999 399999 MOY Nid 139208 000000 e 50000 999999 H INI 1100 ATgN3SSVSIQ 10070
74. Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for Socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation 4 Icc values greater than 95 A are not applicable for the Ultra Dense Intel Xeon Processor 7400 Series 5 Icc values greater than 130 A are not applicable for the Rack Optimized Intel Xeon Processor 7400 Series 30 Intel Xeon Processor 7400 Series Datasheet Electrical Specifications intel Figure 2 4 Vcc Static and Transient Tolerance Load Lines Icc A 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 VID 0 000 4 Voc Maximum VID 0 050 4 VID 0 100 4 E VID 0 150 4 Voc Typical VID 0 200 4 Voc Minimum VID 0 250 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 11 2 for VCC overshoot specifications 2 Refer to Table 2 9 for processor VID information 3 Refer to Table 2 10 for VccStatic and Transient Tolerance 4 The load lines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE pins and the VCC SENSE2 and VSS SENSE2 pins Voltage regulation feedback for voltage regulator circuits must also be taken from the processor VCC_SENSE2 and VSS SENSE2 pins Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 1
75. Intel Xeon Processor 7400 Series Datasheet October 2008 Order Number 320335 Revision 003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Xeon Processor 7400 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the late
76. M3 Power Other Vcc G28 Power Other Vcc M5 Power Other IVcc Lean Power Other Ve M7 Power Other 68 Intel Xeon Processor 7400 Series Datasheet Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 9 of 16 Table 4 1 Pin Listing by Pin Name intel Sheet 10 of 16 Pin Name Me Ran Direction Pin Name og E Direction Vcc M9 Power Other Vcc T28 Power Other Vcc M23 Power Other Vcc T30 Power Other Vcc M25 Power Other Vcc U1 _ Power Other Vcc M27 Power Other Vcc U3 Power Other Vcc M29 Power Other Vcc U5 Power Other Vcc M31 Power Other Vcc U7 j Power Other Vcc N1 jPower Other Vcc U9 jPower Other Vcc N3 Power Other Vcc U23 Power Other Vcc N5 jPower Other Vcc U25 Power Other Vcc N7 Power Other Vcc U27 Power Other Vcc N9 Power Other Vcc U29 Power Other Vcc N23 Power Other Vcc U31 Power Other Vcc N25 Power Other Vcc V2 Power Other Vcc N27 Power Other Vcc V4 Power Other Vcc N29 Power Other Vcc V6 Power Other Vcc N31 Power Other Vcc V8 Power Other Vcc P2 Power Other Vcc V24 Power Other Vcc P4 Power Other Vcc V26 Power Other Vcc P6 Power Other Vcc V28 Power Other Vcc P8 Power Other Vcc V30 Power Other Vcc P24 Power Other Vcc WI Power Other Vcc P26 Power Other Vcc W25 Power Other Vcc P28 Power Other Vcc W27 Power
77. Processor Type 13 10 Processor Family Oh Fh Processor Family 9 6 Processor Model Oh Fh Processor Model 5 2 Processor Stepping Oh Fh Processor Stepping 1 0 Reserved 00b 11b Reserved Intel Xeon Processor 7400 Series Datasheet 121 intel 7 4 3 3 2 7 4 3 3 3 7 4 3 3 4 122 FSB Front Side Bus Speed This location contains the front side bus transaction rate information Systems may need to read this offset to decide if all installed processors support the same front side bus speed Because FSB is described as a 4X data bus the transaction rate given in this field is currently 1066 MTS The data provided is the speed rounded to a whole number and reflected in hex Writes to this register have no effect Example The Intel Xeon Processor 7400 Series supports a 1066 MTS front side bus Therefore offset 1A 1Bh has a value of 042Ah Offset 1Ah 1Bh Bit Description 15 0 Front Side Bus Speed 0000h FFFFh MTS MPSUP Multiprocessor Support This location contains 2 bits for representing the supported number of physical processors on the bus These two bits are MSB aligned where 00b equates to single processor operation 01b is a dual processor operation and 11b represents multi processor operation The Intel Xeon Processor 7400 Series is an MP processor The remaining six bits in this field are reserved for the future use Writes to this re
78. Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details VRM EVRD 11 0 will support the power requirements of all frequencies of the processors including Flexible Motherboard Guidelines FMB see Section 2 11 1 Refer to the appropriate platform design guidelines for implementation details The Intel Xeon Processor 7400 Series supports 1066 MTS Mega Transfers per Second Front Side Bus operation The FSB utilizes a split transaction deferred reply protocol and Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus clock 4X data transfer rate Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or a 2X address bus In addition the Request Phase completes in one clock cycle Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 8 5 GBytes per second The FSB is also used to deliver interrupts Signals on the FSB use Assisted Gunning Transceiver Logic AGTL level voltages Section 2 1 contains the electrical specifications of the FSB while implementation details are fully described in the appropriate platform design guidelines refer to Section 1 3 The Intel Xeon Processor 7400 Series supports Intel Cache Safe Technology on the L3 cache This provides a threshold based mechanism for cache error
79. T state or Stop Grant state The Extended HALT state must be enabled for the processor to remain within its specifications The processor will automatically transition to a lower core frequency and voltage operating point before entering the Extended HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus to core frequency ratio and then transition to the lower voltage VID While in the Extended HALT state the processor will process bus snoops Intel Xeon Processor 7400 Series Datasheet Se intel Table 7 2 Extended HALT Maximum Power Symbol Parameter Min Max Unit Notes PEXTENDED HALT Extended HALT State Power 42 Ww 1 2 Intel Xeon X7460 Processor PEXTENDED HALT Extended HALT State Power 32 Ww 1 2 6 Core Intel Xeon Processor E7400 Series PEXTENDED HALT Extended HALT State Power 36 W 1 2 3 4 Core Intel Xeon Processor E7400 Series P watt C1 Idle Power 42 W 1 2 3 4 core Intel Xeon E7420 E7430 Processor P naLT C1 Idle Power 20 Ww 1 2 3 6 Core Intel amp Xeon Processor L7455 Series P ua C1 Idle Power 15 W 1 2 3 4 Core Intel Xeon Processor L7445 Series Notes 1 The specification is at Tease 50 C and nominal Vcc The VID setting represents the maximum expected VID while running in HALT sta
80. Thermal Specifications oec dE NEE lates es aio ee aka kaka kk 89 6 1 Package Thermal Gpechfications cece eee eee eee ee eee kk memes 89 6 1 1 Thermal Specifications cereri kanl kalen ma ka ika WW ee xwal v na memes 89 6 1 2 Thermal Metrology s s x si sucanaa xin ka ka a h n Eu deg SE zab la na Da ne W Dua a sn wa xain ban n 97 Intel Xeon Processor 7400 Series Datasheet 3 6 2 Processor Thermal Features ireccio E RE RAE 97 6 2 1 Intel Thermal Monitor Features 97 6 2 2 lintel Thermal Mohlk0r si si s da nak sun e nnn a ay nab ka wara an n ya wan kra h na Wa n WAR W 97 6 2 3 Intel Thermal Monitor 2 98 6 2 4 On Demand Mode 99 6 2 5 PROCHOT SiGNal 5 3 c i key n n k kaka layek ec Pd NN de E E De eh EEN NEEN 100 6 2 0 FORCEPR SIQNAl ioci efiam darl i evo e e ORC Pan ca C o e da need kan 100 6 2 7 THERMTRIP Gional nmm nenne nnn 100 6 3 Platform Environment Control Interface PECI ccccccccsecccee sees menn 101 6 3 1 introduction cse se rne oc HA eco v dn c ie Dei e FR FCR OK A EORR ERE eR 101 6 3 1 5 TCONTROL and Tcc Activation on PECI Based Gvstems 102 6 3 1 Processor Thermal Data Sample Rate and Filtering 102 6 3 2 PECI Eis Aaaa a ra EE A ET A A T 103 6 3 2 1 PECI Device Address 103 6 3 2 2 PECI Command Support 103 6 3 2 3 PECI Fault Handling Requirements sssssesseese 103 6 3 2 4 PECI GetTempO and
81. V supplies the PECI interface PECI behavior does not affect V min max specifications 2 The leakage specification applies to powered devices on the PECI bus 3 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes Intel Xeon Processor 7400 Series Datasheet m Electrical Specifications n tel 2 11 4 2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 2 6 as a guide for input buffer design Figure 2 6 Input Device Hysteresis gn Maximum Vpg J Minimum Vp Minimum Valid Input Hysteresis Signal Range Maximum Vw Minimum Vy PECI Ground 2 12 AGTL FSB Specifications Routing topologies are dependent on the processors supported and the chipset used in the design Please refer to the appropriate platform design guidelines for specific implementation details In most cases termination resistors are not required as these are integrated into the processor silicon See Table 2 6 for details on which signals do not include on die termination Please refer to Table 2 17 for Ry values Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END GTLREF DATA MID and GTLREF
82. XYN WW PS T2 001 SWYOILVTd 3AO8Y ONY NZ YOd NId33 LHOIGH INJNOdWO XYH WW 80 S 002 Q3NO11V 1N3H3OY1d LN3NOdNOO QUVOGNJHLON ON 31V1d ONIYdS e Y S8 99 16 000 21 r g 06 T 69 1 1 90 r g 8t6 e DH reem 20 9r 000 0 H S61 96 7 2 611 H 92 8l FI NOISU3A ISS NOIIV2I3I234S AVG S21NOJU12313 NIHL JHL NO Q3SV8 3UV SNOISN3NIO 3S3Hl 39N343434 04 NMOHS GUVOE 1511 SWYOILV 1d NI JO3 1H913H IN3NOdNOO XVW WW PS 2 001 SWHO4LV1d JAQAY ONY NZ NO4 NId339 1H9I3H LNINOdWOD XVN WW 80 6 u q Jais AHVGNO93S UA 26261V ON oma 57 Intel Xeon Processor 7400 Series Datasheet Mechanical Specifications intel Board Mounting Hole Keepout Zones Figure 3 7 t 3 30 v 133MS 9NIAYEO 31V9S 10N 00 KEIER LI A9 262G LV U3ONNN_ONIMVYG DI 1N3n18v430 KINO 310H ONIINQON YOSSIJOYd e v3uv SIHI NI S4400NVLS SISSVHO YO S310H ONILNNOW QuvOG ON 39N381438 401 NMOHS S310H 9NIINDON 3J0SS3208d NuillVd 3108 40 AINO 38383438 404 NNOHS 3NI1100 GUYO 190911 v9 0r om LU g Nu3llVd 310H 40 HU31N32 MO NY3L1Yd 310H 40D 006 2 061 geo u am 90 61 n Lb alt as itm y G 9 Intel Xeon Processor 7400 Series Datasheet 58 Mechanical Specific
83. aintain unique addresses on the SMBus in a system with multiple processors To set an SM_EP_A line high a pull up resistor should be used that is no larger than 1 KQ The processor includes a 10 KQ pull down resistor to Vss for each of these signals SM VCC 86 SM VCC provides power to the SMBus components on the processor package Intel Xeon Processor 7400 Series Datasheet Signal Definitions Table 5 1 intel Signal Definitions Sheet 7 of 8 Name SM WP Type l Description WP Write Protect can be used to write protect the Scratch EEPROM The Scratch EEPROM is write protected when this input is pulled high to SM VCC The processor includes a 10 kQ pull down resistor to Vss for this signal Notes SMI SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tri state its outputs See Section 7 1 STPCLK STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units Th
84. ases Speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with previous processor families Design guidelines for the processor FSB are detailed in the appropriate platform design guidelines refer to Section 1 3 The AGTL inputs require reference voltages GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END which are used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF_DATA_MID and GTLREF_DATA_END are used for the 4X front side bus signaling group and GTLREF_ADD_MID and GTLREF_ADD_END are used for the 2X and common clock front side bus signaling groups GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END must be generated on the baseboard See Table 2 17 for GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END specifications Refer to the applicable platform design guidelines for details Termination resistors Ry for AGTL signals are provided on the processor silicon and are terminated to Vr The on die termination resistors are always enabled on the processor to control reflections on the transmission line Intel chipsets also provide on die termination thus eliminating the need to terminate the bus on the baseboard for most AGTL signals Some FSB signals do not include on die termination Rrr and must be terminated on the baseboard See Table 2 4 Table 2 5 and Table 2 6 for d
85. ata Checksum This location provides the checksum of the Processor Core Data Section Writes to this register have no effect Offset 24h Bit Description 7 0 Processor Core Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Cache Data This section contains cache related data RES3 Reserved 3 These locations are reserved Writes to this register have no effect Offset 25h 26h Bit Description 15 0 RESERVED 3 0000h FFFFh Reserved L2SI ZE L2 Cache Size This location contains the size of the level two cache in kilobytes Writes to this register have no effect Example The Intel Xeon Processor 7400 Series processor has a 6 MB 6144 KB or a 9 MB 9216 KB L2 cache total 3 MB L2 cache per two processor cores Thus offset 27 28h will contain 1800h for 6 MB or 2400h for 9 MB Offset 27h 28h Bit Description 15 0 L2 Cache Size 0000h FFFFh KB Intel Xeon Processor 7400 Series Datasheet Features 7 4 3 4 3 7 4 3 4 4 7 4 3 4 5 intel This location contains the size of the level three cache in kilobytes Writes to this register have no effect L3SI ZE L3 Cache Size Example The Intel Xeon Processor 7400 Series has either a 12 MB 12288 KB 16 MB 16384 KB or 8 MB 8192 KB L3 cache Thus offset 29 2Ah will contain 3000h for 12 MB 4000h for 16
86. ations Figure 3 8 Volumetric Height Keep I ns Kg aa s ig a e e lt lt E j ES amp Wei wo e a Ko tel o Lu E eo Ld eo ez E L a gt i o Ka oo a Intel Xeon Processor 7400 Series Datasheet 59 Table 3 1 60 Mechanical Specifications Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solutions The minimum loading specification must be maintained by any thermal and mechanical solution Processor Loading Specifications Parameter Minimum Maximum Unit Notes Static Compressive 44 222 N 1 2 3 4 Load 10 50 bf 44 288 N 1 2 3 5 10 65 bf Dynamic 222 N 0 45 kg 100 G N 1 3 4 6 7 Compressive Load 50 Ibf static 1 Ibm 100 G bf 288 N 0 45 kg 100 G N 1 3 5 6 7 65 Ibf static 1 Ibm 100 G bf Tra
87. aximum Core VID 0000h FFFFh mV MI NV Minimum Core Voltage This location contains the minimum Processor Core voltage This field rounded to the next thousandth is in mV and is reflected in hex The minimum Vcc reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw Writes to this register have no effect The minimum core voltage value in offset 21 22h is a single value that assumes the FMB maximum current draw Refer to Table 2 9and Table 2 10 for the minimum core voltage specifications based on actual real time current draw Example For an Intel Xeon Processor 7400 Series the minimum voltage is 0 695 V 0 900 V Min VID 0 205 V Voltage Offset at maximum current Offset 21 22h would contain 0267Fh 0695 decimal Offset 21h 22h Bit Description 15 0 Minimum Core Voltage 0000h FFFFh mV TCASE Tcase Maximum This location provides the maximum Tease for the processor The field reflects temperature in degrees Celsius in hex format This data can be found in the Table 6 1 The thermal specifications are specified at the case Integrated Heat Spreader IHS Writes to this register have no effect Intel Xeon Processor 7400 Series Datasheet 123 intel 7 4 3 3 8 7 4 3 4 7 4 3 4 1 7 4 3 4 2 124 Offset 23h Bit Description 7 0 Tcase Maximum OOh FFh Degrees Celsius PCDCKS Processor Core D
88. bility is defined as the worst case timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability Rise and fall times are measured single ended between 245 mV and 455 mV of the clock swing Measured from 200 mV to 200 mV The signal must be monotonic through the measurement region for rise and fall time The 400 mV measurement window is centered on the differential zero See Figure 2 11 Bo Front Side Bus Common Clock AC Specifications T Parameter Min Max Unit Figure Notes 2 3 T10 Common Clock Output Valid Delay 0 22 1 10 ns 2 12 4 T11 Common Clock Input Setup Time 0 650 N A ns 2 12 5 T12 Common Clock Input Hold Time 0 150 N A ns 2 12 5 T13 RESET Pulse Width 1 10 ms 2 20 6 7 8 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Not 100 tested Specified by design characterization 3 All common clock AC timings for AGTL signals are referenced to the Crossing Voltage Vcross of the BCLK 1 0 at rising edge of BCLKO All common clock AGTL signal timings are referenced at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END at the processor pads Intel Xeon Processor 7400 Series Datasheet 37 Table 2 21 38 8 go SI e Electrical Specifications Valid delay timings for these sig
89. by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor FSB agents Intel Xeon Processor 7400 Series Datasheet 83 n n tel Signal Definitions Table 5 1 Signal Definitions Sheet 4 of 8 Name Type Description Notes DSTBN 3 0 1 0 Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 D 63 48 DBI3 DSTBN3 DSTBP 3 0 1 0 Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 FERR PBE O FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The asse
90. c Input Output AC6 D59 Source Sync Input Output AA25 D3 Source Sync Input Output AC7 Vss Power Other AA26 Vcc Power Other AC8 D56 Source Sync Input Output AA27 D1 Source Sync Input Output AC9 D47 Source Sync Input Output AA28 Reserved AC10 Mer Power Other AA29 SM_EP_AO SMBus Input AC11 D43 Source Sync Input Output 78 Intel Xeon Processor 7400 Series Datasheet intel Pin Listing Table 4 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Sheet 13 of 14 Sheet 14 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type AC12 D41 Source Sync Input Output AD22 DBI1 Source Sync Input Output AC13 Maes Power Other AD23 Vss Power Other AC14 D50 Source Sync Input Output AD24 D21 Source Sync Input Output AC15 DP2 Common Clk Input Output AD25 D18 Source Sync Input Output AC16 Vcc Power Other AD26 Vcc Power Other AC17 D34 Source Sync Input Output AD27 D4 Source Sync Input Output AC18 DPO Common Clk Input Output AD28 Reserved AC19 Vss Power Other AD29 SM WP SMBus Input AC20 D25 Source Sync Input Output AD30 Reserved AC21 D26 Source Sync Input Output AD31 Reserved AC22 Mee Power Other AE2 BPMb2 Common Clk Output AC23 D23 Source Sync Input Output AE3
91. cations Processor DC Specifications The following notes apply The processor DC specifications in this section are defined at the processor die and not at the package pins unless noted otherwise The notes associated with each parameter are part of the specification for that parameter Unless otherwise noted all specifications in the tables apply to all frequencies and cache sizes See Section 5 for the pin signal definitions Most of the signals on the processor FSB are in the AGTL signal group The DC specifications for these signals are listed in Table 2 11 Table 2 9 through Table 2 17 list the DC specifications and are valid only while meeting specifications for case temperature Tcase as specified in Section 6 clock frequency and input voltages Flexible Motherboard Guidelines FMB The Flexible Motherboard FMB guidelines are estimates of the maximum values the Intel Xeon Processor 7400 Series will have over certain time periods The values are only estimates and actual specifications for future processors may differ Processors may or may not have specifications equal to the FMB value in the foreseeable future System designers should meet the FMB values to ensure their systems will be compatible with future processors Voltage and Current Specifications Sheet 1 of 3 Symbol Parameter Min Typ Max Unit Notes 1 VID VID range 0 9000 1 4500 V 10 Vcc Vcc for All proces
92. ceptual Fan Control Diagram For a PECI Based Platform TcowrRoL TCC Activation Setting Temperature PECI 0 Fan Speed n RPM PECI 10 I l PECI 20 Temperature not intended to depict actual implementation Processor Thermal Data Sample Rate and Filtering The DTS Digital Thermal Sensors provide an improved capability to monitor device hot spots which inherently leads to more varying temperature readings over short time intervals The DTS sample interval range can be modified and a data filtering algorithm can be activated to help moderate this The DTS sample interval range is 82 us default to 20 ms max This value can be set in BIOS To reduce the sample rate requirements on PECI and improve thermal data stability vs time the processor DTS also implements an averaging algorithm that filters the incoming data This is an alpha beta filter with coefficients of 0 5 and is expressed mathematically as Current filtered temp Previous filtered temp 2 new sensor temp 2 This filtering algorithm is fixed and cannot be changed It is on by default and can be turned off in BIOS Host controllers should utilize the min max sample times to determine the appropriate sample rate based on the controller s fan control algorithm and targeted response rate The key items to take into account when settling on a fan control algorithm are the DTS sample rate whether the temperature filter is enabled
93. ctrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide 134 Intel Xeon Processor 7400 Series Datasheet n Boxed Processor Specifications n te 9 Boxed Processor Specifications 9 1 Introduction The Intel Xeon Processor 7400 Series is also offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from baseboards and standard components The boxed processor will not be supplied with a cooling solution Future revisions may have solutions that differ from those discussed here 9 2 Thermal Specifications Please see Chapter 6 for the the cooling requirements of the boxed processor 9 2 1 Boxed Processor Cooling Requirements A suitable heatsink is required to properly cool the boxed processor However meeting the processor s temperature specifications is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Section 6 2 1 of this document Intel Xeon Processor 7400 Series Datasheet 135 n tel Boxed Processor Specifications 136 Intel Xeon Processor 7400
94. cus eat p Dro Da om E ns 132 7 4 5 Scratch EEDRON HH e hehe mese enean nean enean nnn 132 Debug Tools Specifications ssssssssssssssseee emen 133 8 1 Debug Port System Requirements nee eene 133 8 2 Logic Analyzer Interface LA 133 8 2 1 Mechanical Considerations cesses ee eene nena 133 8 2 2 Electrical Considerations cesses ene nennen kaka aka 134 Boxed Processor Spechiflcations nemen nnn 135 9 1 lin FOU Vie EE 135 9 2 Thermal Specifications ene h Wa Ee RD EE b salada kara 135 9 2 1 Boxed Processor Cooling Requirements cence eee e eee e ee ee na eae nents 135 Intel Xeon Processor 7400 Series Datasheet a e c bes M 100 0 00 0 0 0 01 0 rrr 1 LA M OO OO N 6 QI PS DI M OH UJ UJ UJ UJ UJ QJ UJ GJ UU UJ CJ NJ NJ NJ NJ NJ NJ NJ NJ NJ NJ fJ NJ NJ SJ NJ SJ SJ NJ fJ NJ NJ IN N e O ooo qo um B UN 6 6 6 7 6 8 6 9 7 1 7 2 u Intel Xeon X7460 Processor Load Current versus Time 28 Intel Xeon Processor E7400 Series Load Current versus Time ssse 28 Intel Xeon Processor L7400 Series Load Current versus Time 29 VCC Static and Transient Tolerance Load LINES e 31 VCC Overshoot Example Waveform sss nmm kk kk nnn 33 Input Device Hysteresis sii rent YE bi akla Daka b da Ye lata ald EN ERE na M EE XE Y E YA WA r 35 Electrical Test CIEGUIE ecce sEege krna an Taka ka AW Ra SE ENEE Erud 2a kar n Wi 41 T
95. e utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Intel amp Xeon Processor 7400 Series Thermal Mechanical Design Guide for system and environmental implementation details 96 Intel Xeon Processor 7400 Series Datasheet m Thermal Specifications n tel 6 1 2 Figure 6 6 6 2 6 2 1 6 2 2 Thermal Metrology The minimum and maximum case temperatures TcAsg are specified in Table 6 2 through Table 6 5 and are measured at the geometric top center of the processor integrated heat spreader IHS Figure 6 6 illustrates the location where Tease temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the Intel amp Xeon Processor 7400 Series Thermal Mechanical Design Guide Case Temperature TcAsg Measurement Location Measure from edge of IHS 19 25 mm 0 76 in Measure T case at this point geometric center of IHS 19 25 mm 0 76 in 53 34 mm FC mPGA8 Package Thermal grease should cover entire area of IHS Note Figure is not to scale and is for reference only Processor Thermal Features Intel Thermal Monitor Features Intel Xeon Processor 7400 Series provide two thermal monitor features Intel Thermal Monitor TM1 and Enhanced Thermal Monit
96. e Intel Xeon Processor 7400 Series see Table 2 4 This section provides a sorted pin list in Table 4 1 and Table 4 2 Table 4 1 is a listing of all processor pins ordered alphabetically by pin name Table 4 2 is a listing of all processor pins ordered by pin number Table 4 1 Pin Listing by Pin Name Sheet 2 of 16 Pin Name ri EE Direction A3 A22 Source Sync Input Output A4 A20 Source Sync Input Output A5 B18 Source Sync Input Output A6 C18 Source Sync Input Output A7T A19 Source Sync Input Output A8 C17 Source Sync Input Output A9 D17 Source Sync Input Output A10s A13 Source Sync Input Output All B16 Source Sync Input Output Al2 B14 Source Sync Input Output A13 B13 Source Sync Input Output Al4 A12 Source Sync Input Output A15 C15 Source Sync Input Output Al6 C14 _ Source Sync Input Output Al7 D16 Source Sync Input Output A18 D15 Source Sync Input Output A19 F15 Source Sync Input Output A20 A10 Source Sync Input Output A21 B10 Source Sync Input Output A22 B11 Source Sync Input Output A23 C12 Source Sync Input Output A24 E14 Source Sync Input Output A25 D13 Source Sync Input Output A26 A9 Source Sync Input Output A27 B8 Source Sync Input Output A28 E13 Source Sync Input Output A29 D12 Source Sync Input Output A30 C11 _ Source Sync I
97. e asserted or a specific VID off code is received the VRM EVRD must turn off its output the output should go to high impedance within 500 ms and latch off until power is cycled Refer to Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines Intel Xeon Processor 7400 Series Datasheet 19 E e n tel Electrical Specifications 2 6 20 Reserved Unused or Test Signals All Reserved signals must remain unconnected Connection of these signals to Vcc Ver Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 4 for a pin listing of the processor and the location of all Reserved signals For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the baseboard trace for FSB signals unless otherwise noticed in the appropriate platform design guidelines For unused AGTL input or I O signals use pull up r
98. e falling edge of BCLK1 3 Vhawg is the statistical average of the Vu measured by the oscilloscope 4 Overshoot is defined as the absolute value of the maximum voltage 5 Undershoot is defined as the absolute value of the minimum voltage 6 Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback 7 Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches It includes input threshold hysteresis 8 The crossing point must meet the absolute and relative crossing point specifications simultaneously 9 Vuavg Can be measured directly using Vtop on Agilent and High on Tektronix oscilloscopes 10 For VIN between 0 V and VH 11 VCROSS is defined as the total variation of all crossing voltages as defined in note 3 36 Intel Xeon Processor 7400 Series Datasheet m Electrical Specifications n tel 2 13 Note Table 2 19 Table 2 20 Front Side Bus AC Specifications The processor FSB timings specified in this section are defined at the processor core pads Therefore proper simulation of the FSB is the only means to verify proper timing and signal quality See Table 4 1 for the pin listing and Table 5 1 for signal definitions Table 2 19 through Table 2 24 list the AC specifications associated with the processor FSB All AGTL timings are referenced to GTLREF
99. e implemented including Intel Thermal Monitor TM1 Intel Thermal Monitor 2 TM2 and Enhanced Intel SpeedStep Technology TM1 and TM2 provide efficient and effective cooling in high temperature situations Enhanced Intel SpeedStep Technology allows trade offs to be made between performance and power consumption This may lower average power consumption in conjunction with OS support Processor features include Advanced Dynamic Execution enhanced floating point and multi media units Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Streaming SIMD Extensions 4 SSE4 SSE4 extends the Intel 64 instruction set to accelerate applications that involve graphics video 3D imaging and Web services Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The floating point and multi media units include 128 bit wide registers and a separate register for data movement SSE3 instructions provide highly efficient double precision floating point SIMD integer and memory management operations The Intel Xeon Processor 7400 Series supports Intel 64 as an enhancement to Intel s IA 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details on Intel 64 and its programming model can be found in the Intel 64 and IA 32 Intel Architectures Software Develop
100. e processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDO TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support TESTHI 1 0 TESTHI 1 0 must be connected to a V power source through a resistor for proper processor operation Refer to Section 2 5 for TESTHI grouping restrictions TESTIN1 TESTIN2 TESTIN1 must be connected to a VIT power source through a resistor as well as to the TESTIN2 pin of the same socket for proper processor operation TESTI N2 must be connected to a VTT power source through a resistor as well as to the TESTIN1 pin of the same socket for proper processor operation Refer to Section 2 5 for TESTIN restrictions THERMTRIP Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur Measurement of the temperature is accomplish
101. e setup time to each respective strobe 8 This specification represents the minimum time the data or address will be valid before its strobe Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications 9 This specification represents the minimum time the data or address will be valid after its strobe Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications 10 The rising edge of ADSTB must come approximately 1 2 BCLK period after the falling edge of ADSTB 11 For this timing parameter n 1 2 and 3 for the second third and last data strobes respectively 12 The address strobe setup time is measured with respect to T2 Calculation of the setup time is as follows a If T27 gt BCLK period then the setup time calculated is positive The value calculated indicates setup time before T1 b f T27 lt BCLK period then the setup time calculated is positive The value calculated indicates setup time after T1 Intel amp Xeon Processor 7400 Series Datasheet m Electrical Specifications n tel 13 14 15 Table 2 22 Mis This specification applies only to DSTBN 3 0 and is measured to the second falling edge of the strobe This specification reflects a typical value not a minimum or maximum For this timing parameter n 0 to 1 cellaneous GTL AC Specifications
102. e then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes 2 Vcc Core voltage with respect to Vss 0 30 1 45 V Ver FSB termination voltage with respect to 0 30 1 45 V Vss TCASE Processor case temperature See See C Section 6 Section 6 TsTORAGE Storage temperature 40 85 C 3 4 5 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no pins can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 3 This rating applies to the processor and does not include any tray or packaging 4 Failure to adhere to this specification can affect the long term reliability of the processor Intel Xeon Processor 7400 Series Datasheet 23 intel 2 11 2 11 1 Table 2 9 24 Electrical Specifi
103. ed through an internal thermal sensor Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP See Figure 2 17 and Table 2 22 for the appropriate power down sequence and timing requirements Intel is currently evaluating whether Vor must also be removed Driving of the THERMTRIP signals is enabled within 10 ms of the assertion of PWRGOOD and is disabled on de assertion of PWRGOOD Once activated THERMTRIP remains latched until PWRGOOD is de asserted While the de assertion of the PWRGOOD signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 ms of the assertion of PWRGOOD TMS TMS Test Mode Select is a J TAG specification support signal used by debug tools TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all FSB agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VccPLL The Intel Xeon Processor 7400 Series implement an on die PLL filter solution The Vccp input is used as a PLL supply voltage VC
104. ementations of the 12C bus protocol or the SMBus bus protocol may require licenses from various entities including Phillips Electronics N V and North American Phillips Corporation State of Data The data contained within this document is subject to change The specifications are subject to change without notice Verify with your local Intel sales office that you have the latest datasheet before finalizing a design References Material and concepts available in the following documents may be beneficial when reading this document Document Document Number Notes AP 485 Intel Processor Identification and the CPUID Instruction 241618 1 Intel 64 and IA 32 Architectures Software Developer s Manual 253665 Ti Volume 1 Basic Architecture 253666 Volume 2A Instruction Set Reference A M 253667 Volume 2B Instruction Set Reference N Z 253668 Volume 3A System Programming Guide 253669 Volume 3B System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Documentation 1 252046 Changes Intel 64 and IA 32 Architectures Optimization Reference Manual 248966 1 64 bit Extension Technology Software Developer s Guide 1 Volume 1 300834 Volume 2 300835 Intel Virtualization Technology for A 32 Processors VT x Preliminary C97063 1 Specification Intel Xeon Processor 7400 Series Specification Update 32033501 1 Voltage Regulator Module VRM and Enterpr
105. er F22 A37 Source Sync Input Output H30 Vss Power Other F23 GTLREF ADD MID Power Other Input H31 Vcc Power Other F24 TRST TAP Input J Vss Power Other F25 Vss Power Other J2 Vcc Power Other F26 THERMTRI P Async GTL Output J3 Vss Power Other F27 A20M Async GTL Input J4 Vcc Power Other F28 Vss Power Other J5 Vss Power Other F29 Vcc Power Other J6 Vcc Power Other F30 Vss Power Other J7 Vss Power Other F31 Vcc Power Other J8 Vcc Power Other G1 Vss Power Other J9 Vss Power Other G2 Vcc Power Other J23 Vss Power Other G3 Vss Power Other J24 Vcc Power Other G4 Vcc Power Other J25 Vss Power Other G5 Vss Power Other J26 Vcc Power Other G6 Vcc Power Other J27 Vss Power Other G7 Vss Power Other J28 Vcc Power Other G8 Vcc Power Other J29 Vss Power Other G9 Vss Power Other J30 Vcc Power Other G23 LINT1 Async GTL Input J31 Vss Power Other G24 Vcc Power Other K1 Vcc Power Other G25 Vss Power Other K2 Vss Power Other G26 Vcc Power Other K3 Vcc Power Other G27 Vss Power Other K4 Vss Power Other G28 Vcc Power Other K5 Vcc Power Other G29 Vss Power Other K6 Vss Power Other G30 Vcc Power Other K7 Vcc Power Other G31 Vss Power Other K8 Vss Power Other H1 Vcc Power Other K9 Vcc Power Other H2 Vss Power Other K23 Vcc Power Other H3 Vcc Power Other K24 Vss Power Other HA Vss Power Other K25 Vcc Power Other H5 Vcc Power Other K26 Vss Power Other H6 Vss Power Other K27 Vcc Power Other H7 Vcc Power Other K28 Vss Power Other H8 Vss P
106. er Vss M28 Power Other Vss U6 Power Other Vss M30 Power Other Vss U8 Power Other Vss N2 Power Other Vss U24 Power Other Vss NA Power Other Vss U26 Power Other Vss N6 Power Other Vss U28 Power Other Vss N8 Power Other Vss U30 Power Other Vss N24 Power Other Vss V1 j Power Other Vss N26 Power Other Vss V3 Power Other Vss N28 Power Other Vss V5 Power Other Vss N30 Power Other Vss V7 Power Other Vss P1 Power Other Vss V9 Power Other Vss P3 Power Other Vss V23 Power Other Vss P5 Power Other Vss V25 Power Other Vss P7 Power Other Vss V27 Power Other Intel Xeon Processor 7400 Series Datasheet 71 intel Pin Listing Table 4 1 Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 15 of 16 Sheet 16 of 16 Pin Name he Ed d Direction Pin Name N o Direction Vss V29 Power Other Vss AD3 Power Other Vss V31 Power Other Vss AD9 Power Other Vss W2 Power Other Vss AD15 Power Other Vss WA Power Other Vss AD17 Power Other Vss W24 Power Other Vss AD23 Power Other Vss W26 Power Other Vss AE6 Power Other Vss W28 Power Other Vss AE11 Power Other Vss W30 Power Other Vss AE21 Power Other Vss Y1 Power Other Vss AE27 Power Other Vss Y3 Power Other Vss sENSE D26 Power Other Output Vss Y5 Power Other Vss sENSE2 B26 Power Other Output Vss Y7 Power Other Vr A4 Power Othe
107. er s Manual In addition the Intel Xeon Processor 7400 Series supports the Execute Disable Bit functionality When used in conjunction with a supporting operating system Execute Disable allows memory to be marked as executable or non executable This feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system Further details on Execute Disable can be found at http www intel com cd ids developer asmo na eng 149308 htm The Intel Xeon Processor 7400 Series supports Intel Virtualization Technology for hardware assisted virtualization within the processor Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling multiple independent software environments inside a single platform Further details on Intel Virtualization Technology can be found at http developer intel com technology vt Intel Xeon Processor 7400 Series Datasheet 9 intel maces Table 1 1 Intel Xeon Processor 7400 Series are intended for high performance multi processor server systems The processors support a Multiple Independent Bus MIB architecture with one processor on each bus The MIB architecture provides improved performance by allowing increased FSB speeds and bandwidth All versions of the Intel Xeon
108. er to platform design guide for details 4 For Viu between 0 V and Von 5 This is the measurement at the pin SMBus Signal Group DC Specifications Symbol Parameter Min Max Unit Notes 1 2 VIL Input Low Voltage 0 30 0 30 SM_VCC V Vin Input High Voltage 0 70 SM_VCC 3 465 V VoL Output Low Voltage 0 0 400 V lot Output Low Current N A 3 0 mA lu Input Leakage Current N A 10 HA lio Output Leakage Current N A 10 HA CsMB SMBus Pin Capacitance 15 0 pF 3 Notes 1 These parameters are based on design characterization and are not tested 2 All DC specifications for the SMBus signal group are measured at the processor pins 3 Platform designers may need this value to calculate the maximum loading of the SMBus and to determine maximum rise and fall times for SMBus signals Intel Xeon Processor 7400 Series Datasheet e Electrical Specifications n tel 2 11 2 Table 2 15 Figure 2 5 2 11 3 Vcc Overshoot Specification Processors can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC SENSE and VSS SENSE pins and across the VCC_SENSE2 and VSS SENSE2 pins Vcc Overshoot Specifications
109. es to this register have no effect Offset 6F Bit Description 7 0 Part Number Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Thermal Reference Data This section is reserved for future use RES8 Reserved 8 This location is reserved Writes to this register have no effect Offset 70h Bit Description 7 0 RESERVED 8 RES9 Reserved 9 This location is reserved Writes to this register have no effect Offset 71h 72h Bit Description 15 0 RESERVED 9 TRDCKS Thermal Reference Data Checksum This location provides the checksum of the Thermal Reference Data Section Writes to this register have no effect Offset 73h Bit Description 7 0 Thermal Reference Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Intel Xeon Processor 7400 Series Datasheet 129 7 4 3 8 7 4 3 8 1 7 4 3 8 2 Note 7 4 3 8 3 130 intel Features Feature Data This section provides information on key features that the platform may need to understand without powering on the processor PCFF Processor Core Feature Flags This location contains a copy of results in EDX 31 0 from Function 1 of the CPUID instruction These details provide instruction and feature support by product family A decode of these b
110. esistors of the same value as the on die termination resistors R77 For details see Table 2 20 TAP Asynchronous GTL inputs and Asynchronous GTL outputs do not include on die termination Inputs and utilized outputs must be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the appropriate platform design guidelines For each processor socket connect the TESTIN1 and TESTIN2 signals together then terminate the net with a 51 Q resistor to Vy The TESTHI signals may use individual pull up resistors or be grouped together as detailed below e TESTHI 1 0 can be grouped together with a single pull up to V Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END as reference levels In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving AGTL asynchronous outputs can become active anytime and include an active PMOS pull up transistor to assist during the fi
111. esulting checksum will be B6h AA 10101010 44 01000100 5C 0101100 AA 44 5C 01001010 Negate the sum 10110101 1 101101 B6h Scratch EEPROM Also available in the memory component on the processor SMBus is an EEPROM which may be used for other data at the system or processor vendor s discretion The data in this EEPROM once programmed can be write protected by asserting the active high SM WP signal This signal has a weak pull down 10 kQ to allow the EEPROM to be programmed in systems with no implementation of this signal The Scratch EEPROM resides in the upper half of the memory component addresses 80 FFh The lower half comprises the Processor Information ROM addresses 00 7Fh which is permanently write protected by Intel Intel Xeon Processor 7400 Series Datasheet n Debug Tools Specifications n te 8 8 1 Note 8 2 8 2 1 Debug Tools Specifications Please refer to the appropriate platform design guidelines for information regarding debug tool specifications Section 1 3 provides collateral details Debug Port System Requirements The Intel Xeon Processor 7400 Series debug port is the command and control interface for the In Target Probe ITP debugger The ITP enables run time control of the processors for system debug The debug port which is connected to the FSB is a combination of the system J TAG and execution signals There are several mechanical electrical and functional
112. etails regarding these signals The AGTL bus depends on incident wave switching Therefore timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the FSB including trace lengths is highly recommended when designing a system Contact your Intel Field Representative to obtain the processor signal integrity models which includes buffer and package models Intel Xeon Processor 7400 Series Datasheet 15 E e n tel Electrical Specifications 2 2 1 2 2 2 2 2 3 2 3 16 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cgu k such as electrolytic capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 9 Failure to do so can result in timing violations or reduced lifetime of the component For further information and guidelines refer to the appropriate platfor
113. f Ai mu en Kee BEN al G3MOTIV SIN3NOdHOD GUVOGYIHLON ON 100d334 YIONI4 GVO 9NINdS 332 e NOLLOIBIS3U LHOI3H IN3NONOD GYVOBYSHLON XYN HMI ISS Q v 038011Y INJHJOWTd IN3NOGHOD GYVOGYIHLON ON Q S310H NYHL ONTINNON YOSSIIONd N0 1131381838 14913 LNINONOD XVH HH 3278 wS2E VJUY ATGNISSVSIG WNISLYIH e 100 100 an Jas 19 2010 4 NO 119131838 LHO13H ININOJNOD XVW MH 9278 G2 VIUY NNISLVIH O 19 91 01D XP G0 0 4 NOLLOIYLSIY 1H913H LNINOdNOD XWA WWIB E OSI D 0072 0N3931 96 09 Io 2 rng 100021 90 g 6281 WEI 61871 o 1 9p H ETTI J R 9909990999909999909999999 9950099900999000990099900 EE 328383438 803 NMOHS QNVOG ISIL 1810711 EE RAA EE to00 13 EE E 900000 h EI 000000 33339 208999 99999 900009 23339 228999 00g 38989 398988 pl 38986 999398 39329 398989 ter 39989 388888 V bi 59598 0990098 39339 9999989 00000 19900000 33389 9990090 888 HIS 0000 12000000 3339 9990099 3 H 3933 9999938 H 0000 1000000 h Of q 2 2 ne rno ce z8 SS SEGS oS Z5 25 Pe wmm Bin Rid SH i BS REGS SR SS V 37 2 27S laa Be ge gf Ser E ge ae TET BEY EI a il v 2 S 9 L 8 intel Figure 3 5 56 intel Mechanical Specifications Bottom Side Board Keepout Zones Figure 3 6 y ap S 9 L g ie rs rival ita ine SWYOILV NI 201 NId339 1H913H LNINOMNOD
114. gins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor FSB agents LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all FSB agents When the APIC functionality is disabled the LINTO INTR signal becomes INTR a maskable interrupt request signal and LINT1 NMI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LL ID 1 0 The LL ID 1 0 signals are used to select the correct loadline slope for the processor These signals are not connected to the processor die A logic 0 is pulled to ground and a logic 1 is a no connect on the Intel Xeon Processor 7400 Series package 00 Reserved 01 1 25 mQ Load Line 10 Reserved 11 Reserved LOCK 1 0 LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning
115. gister have no effect Example The Intel Xeon Processor 7400 Series will use COh at offset 1Ch Offset 1Ch Bit Description 7 6 Multiprocessor Support UP DP or MP indictor 00b UP 01b DP 10b Reserved 11b MP 5 0 RESERVED 000000b 111111b Reserved MCF Maximum Core Frequency This location contains the maximum core frequency for the processor The frequency should equate to the markings on the processor and or the S spec speed even if the parts are not limited or locked to the intended speed Format of this field is in MHz rounded to a whole number and encoded in hex format Writes to this register have no effect Example A 2 93 GHz processor will have a value of 0675h which equates to 2933 decimal Therefore offset 1D 1Eh has a value of 0765h Intel Xeon Processor 7400 Series Datasheet Features 7 4 3 3 5 7 4 3 3 6 Note 7 4 3 3 7 Offset 1Dh 1Eh Bit Description 15 0 Maximum Core Frequency 0000h FFFFh MHz MAXVI D Maximum Core VID This location contains the maximum Core VID Voltage Identification voltage that may be requested via the VID pins This field rounded to the next thousandth is in mV and is reflected in hex Writes to this register have no effect Example From Table 2 9the maximum VID is 1 450 V maximum voltage Offset 1F 20h would contain 05AAh 1450 decimal Offset 1Fh 20h Bit Description 15 0 M
116. gital representation of relative processor temperature PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal fan speed control More detailed information may be found in Section 6 3 Platform Environment Control Interface PECI and the RS Platform Environment Control Interface PECI Specification DC Characteristics A PECI device interface operates at a nominal voltage set by Vor The set of DC electrical specifications shown in Table 2 16 is used with devices normally operating from a Vy interface supply Ver nominal levels will vary between processor families All PECI devices will operate at the V level determined by the processor installed in the system For specific nominal Vr levels refer to Table 2 11 Table 2 16 PECI DC Electrical Limits 34 Symbol Da Min Max Units Notes1 Vin Input Voltage Range 0 150 Ver V Vhysteresis Hysteresis 0 1 Vir N A V Negative edge Vn ire Held voltage Iro Var eee Va Y Vp e cs 0 550 Vr 0 725 Vyr V High level output I source source 6 0 N A mA Vou 0 75 Vr Low level output sink lsi 0 5 1 0 mA ank VoL 0 25 Vir High impedance state leak leakage to Vy N A 50 HA 2 Vieak Vol High impedance leak leakage to GND N A 10 HA 2 Vieak Vou Cpus Bus capacitance N A 10 pF 3 Signal noise immunity Vnoise above 300 MHz OUT Var N A Vp p Note 1
117. gs 78h 8 Processor Feature Flags 7 Multi Core 6 Serial Signature 5 Electronic Signature Present 4 Thermal Sense Device Present 3 Reserved 2 OEM EEPROM Present 1 Core VID Present 0 L3 Cache Present 79h 8 Processor Thread and Core 7 2 Number of cores Information 1 0 Number of threads per core 7Ah 8 Additional Processor Feature 7 Reserved Flags 6 Intel Cache Safe Technology 5 Extended Halt State C1E 4 Intel Virtualization Technology 3 Execute Disable 2 Intel 64 1 Thermal Monitor TM2 0 Enhanced Intel SpeedStep Technology 7B 7Ch 16 Thermal Adjustment Factors 15 8 Measurement Correction Factor Pending 7 0 Temperature Target 7D 7Eh 16 Reserved Reserved 7Fh 8 Checksum 1 byte checksum Details on each of these sections are described below Note Reserved fields or bits SHOULD be programmed to zeros However OEMs should not rely on this model 7 4 3 1 Header To maintain backward compatibility the Header defines the starting address for each subsequent section of the PIROM Software should check for the offset before reading data from a particular section of the ROM Example Code looking for the cache data of a processor would read offset 05h to find a value of 25h 25h is the first address within the Cache Data section of the PIROM Intel Xeon Processor 7400 Series Datasheet 115 intel 7 4 3 1 1 Note 7 4 3 1 2 7 4 3 1 3 11
118. h h mana bawa naa z 59 Processor Topside Markings kh l ll kk kk kk kk kaka y k aka ka 62 Processor Bottom Side Markings khk h klll kk kk kk kaka kak kaka k 62 Processor Pin Out Coordinates Top View 63 Intel Xeon X7460 Processor Thermal Profile 91 6 Core Intel Xeon Processor E7400 Series Thermal Profile 93 4 Core Intel Xeon Processor E7400 Series Thermal Profile E E 94 6 Core Intel Xeon Processor L7400 Series Thermal Profile 95 4 Core Intel Xeon Processor L7400 Series Thermal Profile 96 Case Temperature TCASE Measurement Location 97 Intel Thermal Monitor 2 Frequency and Voltage Ordering ee ee eee eee tees 99 PECI T pol VE 101 Conceptual Fan Control Diagram For a PECI Based battomm sse 102 Stop Glock State Machine ctio ce EE XR B ERR RERO a A RR ERAN ERR E EE ERE 108 Logical Schematic of SMBus Circuitry ssssssssssssee memes 111 Intel Xeon Processor 7400 Series Datasheet 5 Tables 1 41 Processor Feat 8 yk ail kelan nk mr oc ege ee Pres WA na haa Ze hel el wort ena Re EE RE 10 2 1 Core Frequency to Multiplier Configuration sssssssssssenem nne 17 2 2 BSEL 2 0 Frequency Table 17 2 3 Voltage Identification Definition cette kk ak kaka ke 19 2 4 FSB SIlgnal Ee e UE 21 2 5 AGTL Signal Description Table 22 2 6 Non AGTL Signal Description Table 22 2 7 Signal Reference Voltages ee eee se nee eese 22
119. he offset to the Processor Data Section Writes to this register have no effect Offset 03h Bit Description 7 0 Processor Data Address Byte pointer to the Processor Data section 00h Processor Data section not present O1h ODh Reserved OEh Processor Data section pointer value OFh FFh Reserved Intel amp Xeon Processor 7400 Series Datasheet ae intel 7 4 3 1 4 PCDA Processor Core Data Address This location provides the offset to the Processor Core Data Section Writes to this register have no effect Offset 04h Bit Description 7 0 Processor Core Data Address Byte pointer to the Processor Data section 00h Processor Core Data section not present O1h 15h Reserved 16h Processor Core Data section pointer value 17h FFh Reserved 7 4 3 1 5 L3CDA L3 Cache Data Address This location provides the offset to the L3 Cache Data Section Writes to this register have no effect Offset 05h Bit Description 7 0 L3 Cache Data Address Byte pointer to the L3 Cache Data section 00h L3 Cache Data section not present O1h 24h Reserved 25h L3 Cache Data section pointer value 26h FFh Reserved 7 4 3 1 6 PDA Package Data Address This location provides the offset to the Package Data Section Writes to this register have no effect Offset 06h Bit Description 7 0 Package Data Address Byte pointer to the Package Data section 00h Package
120. hould not trip for load currents greater than TDC 100 tested Specified by design characterization Intel Xeon Processor 7400 Series Datasheet Electrical Specifications Figure 2 3 Intel Xeon Processor L7400 Series Load Current versus Time 100 95 90 85 80 75 70 Sustained Current A 65 60 1 10 Time Duration s 100 1000 Notes 1 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than lc C TDC 2 Not 10096 tested Specified by design characterization Intel Xeon Processor 7400 Series Datasheet 29 E e n tel Electrical Specifications Table 2 10 Vcc Static and Transient Tolerance Icc A Vcc Max V Vcc ren V Vcc we V Notes 0 VID 0 000 VID 0 015 VID 0 030 1 2 3 5 VID 0 006 VID 0 021 VID 0 036 1 2 10 VID 0 013 VID 0 028 VID 0 043 1 2 3 15 VID 0 019 VID 0 034 VID 0 049 1 2 20 VID 0 025 VID 0 040 VID 0 055 1 2 3 25 VID 0 031 VID 0 046 VID 0 061 1 2 30 VID 0 038 VID 0 053 VID 0 068 1 2 3 35 VID 0 044 VID 0 059 VID 0 074 1 2 3 40 VID 0 050 VID 0 065 VID 0 080 1 2 3 45 VID 0 056 VID 0 071 VID 0 086 1 2 3 50 VID 0 063 VID 0 078 VID 0 093 1 2 55 VID 0 069 VID 0 084 VID 0 099 1 2 3 60 VID 0
121. hread and Core Information This location contains information regarding the number of cores and threads on the processor Writes to this register have no effect Example The Intel Xeon Processor 7400 Series has two four or six cores and one thread per core Therefore this register will have a value of 9h 11h or 19h Intel Xeon Processor 7400 Series Datasheet Se intel Offset 79h Bit Description 7 2 Number of cores 1 0 Number of threads per cores 7 4 3 8 4 AFF Additional Processor Feature Flags This location contains additional feature information for the processor This field is defined as follows Writes to this register have no effect Offset 7Ah Bit Description Reserved Intel Cache Safe Technology Extended Halt State CIE Intel9 Virtualization Technology Execute Disable Intel 64 Thermal Monitor 2 O FINI AJ O a Ji Enhanced Intel SpeedStep Technology Bits are set when a feature is present and cleared when they are not Example The Intel Xeon Processor 7400 Series may or may not have Enhanced Intel SpeedStep Technology present and supports all the other available features Offset 7Ah will contain 7Eh or 7Fh 126 or 127 decimal 7 4 3 8 5 TAF Thermal Adjustment Factors This location contains information on thermal adjustment factors for the processor This field and it s details are pending a
122. hrough BIOS PECI Topology 0 DomainO C28 0 Socket 0 0 Cluster ID 1 0 0 x 3 Domain1 0 0 3 DomainO C28 2 Socket 1 0 Cluster ID 1 0 1 x 3 Domain1 2 PECI Host Controller 0 3 DomainO c28 j Socket 2 0 Cluster ID 1 0 2 x 3 Domain1 1 0 A DomainO C28 3 Socket 3 0 Cluster ID 1 0 3 x 3 Domain1 3 Note 1 Note The power on configuration POC settings of third party chipsets may produce different PECI addresses than those shown in Figure 6 8 Thermal designers should consult their third party chipset designers for the configured PECI addresses Intel Xeon Processor 7400 Series Datasheet 101 E e n tel Thermal Specifications 6 3 1 1 Figure 6 9 6 3 1 2 102 TcoNTROL and Tcc Activation on PECI Based Systems Fan speed control solutions based on PECI utilize a TcontroL Temperature Control Offset value stored in the processor 1A32 TEMPERATURE TARGET MSR This MSR uses the same offset temperature format as PECI though it contains no sign bit Thermal management devices should infer the Tcontro value as negative Thermal management algorithms should utilize the relative temperature value delivered over PECI in conjunction with the MSR value to control or optimize fan speeds Figure 7 8 shows a conceptual fan control diagram using PECI temperatures Con
123. ia bits 3 1 of the same Intel Xeon Processor 7400 Series Datasheet 99 E e n tel Thermal Specifications 6 2 5 6 2 6 6 2 7 100 1A32_CLOCK_MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Intel Thermal Monitor however if the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal An external signal PROCHOT processor hot is asserted when the temperature of either processor die has reached its factory configured trip point If the Intel Thermal Monitor is enabled note that the Intel Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel 64 and IA 32 Architectures Software Developer s Manual PROCHOT is designed to assert at or a few degrees higher than maximum Tease as specified by Thermal Profile when dissipating TDP power and cannot be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and attempts to ensure the Thermal Control Circuit
124. iate to the error handling architecture of the system BNR 1 0 BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wired OR signal which must connect the appropriate pins of all processor FSB agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges BPM5 1 0 BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals BPM4 They are outputs from the processor which indicate the status of breakpoints and O GE BPM3 programmable counters used for monitoring processor performance BPM 5 0 g 1 0 should connect the appropriate pins of all FSB agents BPM 2 11 O BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a BPMO I O processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents Please refer to the appropriate platform design guidelines for more detailed information BPMb3 1 0 BPMb 3 0 Breakpoint Monitor are a second set of
125. ifications including DC AC FSB signal quality mechanical and thermal are satisfied Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor pins should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Priority Agent The priority agent is the host bridge to the processor and is typically known as the chipset Intel Xeon Processor 7400 Series Datasheet 11 12 ntel Introduction Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are known as Symmetric Multiprocessing SMP systems Integrated Heat Spreader I HS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Thermal Design Power Processor thermal solutions should be designed to meet this target It is the highest expected sustainable power while running known power intensive real app
126. ing the FORCEPR signal feature THERMTRI P Signal Regardless of whether or not the Intel Thermal Monitor or Intel Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when either die has reached an elevated temperature refer to the THERMTRIP definition in Table 5 1 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 5 1 THERMTRIP activation is independent Intel Xeon Processor 7400 Series Datasheet m Thermal Specifications n tel 6 3 6 3 1 Figure 6 8 of processor activity and does not generate any bus cycles If THERMTRIP is asserted processor core voltage Vcc must be removed within the time frame defined in Table 2 22 and Figure 2 17 Intel also recommends the removal of V Platform Environment Control I nterface PECI I ntroduction PECI offers an interface for thermal monitoring of Intel processor and chipset components It uses a single wire thus alleviating routing congestion issues Figure 6 8 shows an example of the PECI topology in a system with Intel Xeon Processor 7400 Series PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2 Kbps to 2 Mbps The PECI interface on Intel Xeon Processor 7400 Series is disabled by default and must be enabled t
127. ird party chipset designers for the default configured PECI addresses or power on configuration method Please note that each address also supports two domains Domain 0 and Domain 1 For more information on PECI domains please refer to the Platform Environment Control Interface Specification Note 1 The Cluster ID bit order is reversed 0 1 for the PECI address calculation PECI Command Support PECI command support is covered in detail in RS Platform Environment Control Interface PECI Specification Please refer to this document for details on supported PECI command function and codes PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios where the PECI is known to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not guaranteed to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational
128. ired the operating frequency and voltage transition back to the normal system operating point Transition of the VID code will occur first in order to ensure proper operation once the processor reaches its normal operating frequency Refer to Figure 6 7 for an illustration of this ordering Intel Thermal Monitor 2 Frequency and Voltage Ordering Ton Temperature Frequency Vcc Time lt T hysterisis gt The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Intel Thermal Monitor or Intel Thermal Monitor 2 is enabled On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Intel Thermal Monitor and Intel Thermal Monitor 2 features On Demand mode is intended as a means to reduce system level power consumption Systems utilizing the Intel Xeon Processor 7400 Series must not rely on software usage of this mechanism to limit the processor temperature If bit 4 of the 1A32 CLOCK MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable v
129. ires support for dynamic VID transitions in the platform HALT State HALT is a low power state entered when the processor has executed the HALT or MWAIT instruction When one of the processor cores executes the HALT or MWAIT instruction that processor core is halted however the other processor cores continue normal operation The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the front side bus RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT state See the Intel 64 and IA 32 Architectures Software Developer s Manual Volume IIl System Programming Guide for more information The system can generate a STPCLK while the processor is in the HALT state When the system deasserts STPCLK the processor will return execution to the HALT state While in HALT state the processor will process front side bus snoops and interrupts Extended HALT State Extended HALT state is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT state has been enabled via the BIOS When one of the processor cores executes the HALT instruction that processor core is halted however the other processor cores continue normal operation The Extended HALT state is a lower power state than the HAL
130. ise Voltage Regulator Down DC DC converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the processor VID bits Vcc The processor core power supply VccpiL The processor Phase Lock Loop PLL power supply Vss The processor ground Ver FSB termination voltage Note In some Intel processor EMTS documents Vr is instead called Vccp Processor I nformation ROM PIROM A memory device located on the processor and accessible via the System Management Bus SMBus which contains information regarding the processor s features This device is shared with the Scratch EEPROM is programmed during manufacturing and is write protected Scratch EEPROM Electrically Erasable Programmable Read Only Memory A memory device located on the processor and addressable via the SMBus which can be used by the OEM to store information useful for system management SMBus System Management Bus A two wire interface through which simple system and power management related devices can communicate with the rest of the system It is based on the principals of the operation of the I2C two wire serial bus from Phillips Semiconductor Intel Xeon Processor 7400 Series Datasheet Introduction Note 1 2 1 3 intel 12C is a two wire communications bus protocol developed by Phillips SMBus is a subset of the I2C bus protocol and was developed by Intel Impl
131. ise Voltage Regulator Down EVRD 315889 1 11 0 Design Guidelines EPS12V Power Supply Design Guide A Server system Infrastructure SSI 2 Specification for Entry Chassis Power Supplies Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide 32033701 1 Notes 1 Document is available publicly at http developer intel com 2 Document available on www ssiforum org 13 Intel Xeon Processor 7400 Series Datasheet 14 Introduction Intel Xeon Processor 7400 Series Datasheet n Electrical Specifications n tel 2 2 1 Electrical Specifications Front Side Bus and GTLREF Most Intel Xeon Processor 7400 Series FSB signals use Assisted Gunning Transceiver Logic AGTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates AGTL buffers are open drain and require pull up resistors to provide the high logic level and termination AGTL output buffers differ from GTL buffers with the addition of an active PMOS pull up transistor to assist the pull up resistors during the first clock of a low to high voltage transition Platforms implement a termination voltage level for AGTL signals defined as V m Because platforms implement separate power planes for each processor and chipset Vcc and Vy are supplied separately to the processor This configuration allows for improved noise tolerance as processor frequency incre
132. its is found in the AP 485 Intel9 Processor Identification and CPUID Instruction application note Writes to this register have no effect Offset 74h 77h Bit Description 31 0 Processor Core Feature Flags 0000h FFFFF Feature Flags PFF Processor Feature Flags This location contains additional feature information from the processor Writes to this register have no effect Bit 5 and Bit 6 are mutually exclusive only one bit will be set Offset 78h Bit Description Multi Core set if the processor is a multi core processor Serial signature set if there is a serial signature at offset 4D 54h Electronic signature present set if there is a electronic signature at 4D 54h Thermal Sense Device present set if an SMBus thermal sensor on package Reserved OEM EEPROM present set if there is a scratch ROM at offset 80 FFh Core VID present set if there is a VID provided by the processor O FIN Di Pi oO JI L3 Cache present set if there is a level 3 cache on the processor Bits are set when a feature is present and cleared when they are not Example The Intel Xeon Processor 7400 Series does not support a SMBus Thermal Sense Device supports either a Serial Signature or Electronic signature supports an OEM EEPROM supports Core VID and supports an L3 Cache Offset 78h will contain A7h or C7h 167 or 199 decimal PTCI Processor T
133. k Input Output F2 Vss Power Other D21 Vss Power Other F3 Vss Power Other D22 RS1 Common Clk Input F4 Vcc Power Other D23 BPRI Common Clk Input F5 BPM3 Common Clk Input Output D24 Vcc Power Other F6 BPMO Common Clk Input Output D25 COMPO Power Other Input F7 Vss Power Other D26 Vss SENSE Power Other Output F8 BPM1 Common Clk Input Output D27 Reserved F9 GTLREF ADD END Power Other Input D28 Vss Power Other F10 Ver Power Other D29 Reserved F11 BINIT Common Clk Input Output D30 Vss Power Other F12 BR1 Common Clk Input Output D31 Mee Power Other F13 Vss Power Other EL Vss Power Other F14 ADSTB1 Source Sync Input Output E2 Reserved F15 A195 Source Sync Input Output E3 VID1 Power Other Output F16 A36 Source Sync Input Output EA BPM5 Common Clk Input Output F17 ADSTBO Source Sync Input Output 74 Intel Xeon Processor 7400 Series Datasheet intel Pin Listing Table 4 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Sheet 5 of 14 Sheet 6 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type F18 DBSY Common Clk Input Output H26 Vss Power Other F19 Vss Power Other H27 Vcc Power Other F20 BNR Common Clk Input Output H28 Vss Power Other F21 RS2 Common Clk Input H29 Mee Power Oth
134. l result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation Refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide for system and environmental implementation details Intel Xeon X7460 Processor Thermal Profile Table Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation Power W Tcase_max C 0 45 10 46 5 20 47 9 30 49 4 40 50 8 50 52 3 60 53 8 70 55 2 80 56 7 90 58 2 100 59 6 110 61 1 120 62 5 130 64 Notes Thermal Profile is representative of a volumetrically unconstrained platform ER Refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide for system and environmental implementation details Intel Xeon Processor 7400 Series Datasheet Thermal Specifications n tel Figure 6 2 6 Core Intel Xeon Processor E7400 Series Thermal Profile 750 700 50 g o Temperature C 8 400 350 300 Notes 1 Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 3 fo
135. le 4 1 Pin Listing by Pin Name Sheet 6 of 16 Pin Name o orc id Direction Pin Name Ne Mi XA Direction DP1 AE19 Common Clk Input Output Reserved A31 DP2 AC15 Common Clk Input Output Reserved Bl DP3 AE17 Common Clk Input Output Reserved B4 DRDY E18 Common Clk Input Output Reserved B30 DSTBNO Y21 Source Sync Input Output Reserved C31 DSTBN1 Y18 Source Sync Input Output Reserved D27 DSTBN2 Y15 Source Sync Input Output Reserved D29 DSTBN3 Y12 Source Sync Input Output Reserved E2 DSTBPO Y20 Source Sync Input Output Reserved Y27 DSTBP1 Y17 Source Sync Input Output Reserved Y28 DSTBP2 Y14 Source Sync Input Output Reserved Y29 DSTBP3 Y11 Source Sync Input Output Reserved AA5 FERR PBE E27 Async GTL Output Reserved AA28 FORCEPR A15 Async GTL Input Reserved ABA GTLREF ADD END F9 Power Other Input Reserved AC30 GTLREF_ADD_MID F23 Power Other Input Reserved AD4 GTLREF_DATA_END W9 Power Other Input Reserved AD6 GTLREF DATA MID W23 Power Other Input Reserved AD16 HIT E22 Common Clk Input Output Reserved AD28 HITM A23 Common Clk Input Output Reserved AD30 ERR E5 Async GTL Output Reserved AD31 IGNNE Z C26 Async GTL Input Reserved AE8 INIT D6 Async GTL Input Reserved AE30 LINTO B24 Async GTL Input RESET Y8 Common Clik Input LINT1 G23 Async GTL In
136. lection of power supply voltages Table 2 3 specifies the voltage level corresponding to the state of VID 6 1 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level The definition provided in Table 2 3 is not related in any way to previous Intel Xeon processors or voltage regulator designs If the processor socket is empty VID 6 1 111111 or the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself See the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details Although the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines defines VID 7 0 VID 7 and VID 0 are not used on the Intel Xeon Processor 7400 Series The Intel Xeon Processor 7400 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 2 9 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 10 and Table 2 2 The VRM or EVRD utilized must be capable of regulating its
137. lications TDP is not the maximum power that the processor can dissipate Platform Environment Control Interface PECI A proprietary one wire bus interface that provides a communication channel between Intel processor and controller components to external thermal monitoring devices for use in fan speed control PECI communicates readings from the processor s Digital Thermal Sensors DTS The DTS replaces the thermal diode available in previous processors Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology is the next generation implementation of the Geyserville technology which extends power management capabilities of servers Intel 64 An enhancement to Intel s A 32 architecture that allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details on can be found in the 64 bit Extension Technology Software Developer s Guide at http developer intel com technology 64bitextensions Intel Virtualization Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform VRM Voltage Regulator Module DC DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits EVRD Enterpr
138. ltage frequency operating points P states are lower power capability states within the Normal state as shown in Figure 7 1 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system The Intel Xeon Processor 7400 Series have hardware logic that coordinates the requested voltage VID between the processor cores The highest voltage requested from the four processor cores is selected for that processor package Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology Multiple voltage frequency operating points provide optimal performance at reduced power consumption Voltage frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency f the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the proce
139. m design guidelines Vcc Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR Bulk decoupling must be provided on the baseboard to handle large current swings The power delivery solution must insure the voltage and current specifications are met as defined in Table 2 9 For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines V Decoupling Bulk decoupling must be provided on the baseboard Decoupling solutions must be sized to meet the expected load To insure optimal performance various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution consists of a combination of low ESR bulk capacitors and high frequency ceramic capacitors For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines Front Side Bus AGTL Decoupling The processor integrates signal termination on the die as well as a portion of the required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB Bulk decoupling must also be provided by the baseboard for proper AGTL bus operation Deco
140. mal Mechanical Design Guide for details on system thermal solution design thermal profiles and environmental considerations The Intel Xeon Processor E7400 Series see Figure 6 2 Table 6 3 and Intel Xeon Processor L7400 Series see Figure 6 4 Table 6 5 supports a single Thermal Profile The Thermal Profiles are indicative of a constrained thermal environment Ex 1U form factor Because of the reduced cooling capability represented by this solution the probability of TCC activation and performance loss is increased Additionally utilization of a thermal solution that does not meet the Thermal Profile will violate the thermal specifications and may result in permanent damage to the processor Refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide for details on system thermal solution design thermal profiles and environmental considerations The upper point of the thermal profile consists of the Thermal Design Power TDP and the associated Tcase value It should be noted that the upper point associated with Intel Xeon X7460 Processor Thermal Profile x TDP and y Tcase max P TDP represents a thermal solution design point In actuality the processor case temperature will not reach this value due to TCC activation see Figure 6 1 for the Intel Xeon X7460 Processor Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained ti
141. me periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP instead of the maximum processor power consumption The Intel Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature refer to Section 6 2 To ensure maximum flexibility for future requirements systems should be designed to the Flexible Motherboard FMB guidelines even if a processor with lower power dissipation is currently planned Intel Thermal Monitor or I ntel Thermal Monitor 2 feature must be enabled for the processor to remain within its specifications Intel Xeon Processor 7400 Series Datasheet Thermal Specifications n tel Table 6 1 Figure 6 1 Processor Thermal Specifications Core Daw Design Minimum Maximum Not Frequency Ww TCASE C TCASE C ores Intel Xeon X7460 130 5 See Figure 6 1 Figure 6 3 1 2 3 4 5 Processor Launch to FMB Table 6 2 Table 6 4 Intel Xeon Processor 90 5 See Figure 6 2 Table 6 3 1 2 3 4 5 E7400 Series Launch to FMB 6 core Intel Xeon 65 5 See Figure 6 4 Table 6 5 1 2 3 4 5 Processor L7400 Series Launch to FMB 4 core Intel Xeon 50 5 See Figure 6 5 Table 6 6 1 2 3 4 5 Processor L7400 Series Launch to FMB Notes 1 These values are specified at Vcc max for all processor frequencies Syste
142. ms must be designed to ensure the processor is not to be subjected to any static Vcc and Lee combination wherein Vcc exceeds Vcc max at specified Icc Please refer to the loadline specifications in Section 2 11 i 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Teaser 3 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 4 Power specifications are defined at all VIDs found in Table 2 3 The Intel Xeon Processor 7400 Series may be shipped under multiple VIDs for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Intel Xeon X7460 Processor Thermal Profile a Tore 0 146x Power 45 C Temperature C 8 Notes 1 Thermal Profile is representative of a volumetrically unconstrained platform Please refer to Table 6 2 for discrete points that constitute the thermal profile Intel Xeon Processor 7400 Series Datasheet 91 Table 6 2 92 Thermal Specifications Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile wil
143. n conjunction with the AC timing tables Table 2 19 through Table 2 25 For Figure 2 8 through Figure 2 21 the following apply 1 All common clock AC timings for AGTL signals are referenced to the Crossing Voltage Vcnoss of the BCLK 1 0 at rising edge of BCLKO All common clock AGTL signal timings are referenced at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END at the processor pads All source synchronous AC timings for AGTL signals are referenced to their associated strobe address or data at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END Source synchronous data signals are referenced to the falling edge of their associated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END at the processor pads All AC timings for AGTL strobe signals are referenced to BCLK 1 0 at Vcnoss All AGTL strobe signal timings are referenced at nominal GTLREF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END at the processor pads All AC timings for the TAP signals are referenced to the TCK at 0 5 V m at the processor pins All TAP signal timings TMS TDI etc are referenced at 0 5 Vy at the processor pads 5 All CMOS signal timings are refe
144. nals are specified into the test circuit described in Figure 2 7 and with GTLREF DATA MID GTLREF_DATA_END GTLREF ADD MID and GTLREF ADD END at 0 67 Ver Specification is for a minimum swing is specified into the test circuit described in Figure 2 7 and defined between AGTL Vi max to Vin M N This assumes an edge rate of 2 0 V ns to 3 0 Vins RESET can be asserted active asynchronously but must be deasserted synchronously This should be measured after Vr and BCLK 1 0 become stable Maximum specification applies only while PWRGOOD is asserted FSB Source Synchronous AC Specifications T Parameter Min Max Unit Figure Notes 1 2 3 4 T20 Source Sync Output Valid Delay 0 00 1 10 ns 2 13 5 first data address only 2 14 T21 Tygp Source Sync Data Output Valid 0 27 ns 2 14 5 8 Before Data Strobe T22 Tyap Source Sync Data Output Valid 0 27 ns 2 14 5 9 After Data Strobe T23 Tyga Source Sync Address Output 0 66 ns 2 13 5 8 Valid Before Address Strobe T24 TyaA Source Sync Address Output 0 66 ns 2 13 5 9 Valid After Address Strobe T25 Tsyss Data Input Setup Time 0 19 ns 2 13 6 2 14 T25 Tsyss Address Input Setup Time 0 3 ns 2 13 6 2 14 T26 Tysg Data Input Hold Time 0 19 ns 2 13 6 2 14 T26 Tuse Address Input Hold Time 0 300 ns 2 13 6 2 14 T27 Source Synchronous Address Strobe 3 5 1 875 n ns 2 13 12 14 15 10 Setup Time to BCLK 1 0 2 14 T28 Sou
145. ncy per bits 12 8 of the CLOCK FLEX MAX MSR however this does not apply to frequency transitions initiated due to thermal events Extended HALT Enhanced Intel SpeedStep technology transitions or assertion of the FORCEPR signal See Section 6 Mixing processors of different steppings but the same model as per CPUID instruction is supported Details regarding the CPUID instruction are provided in the AP 485 Intel Processor Identification and the CPUID Instruction application note Absolute Maximum and Minimum Ratings Table 2 8 specifies absolute maximum and minimum ratings only which lie outside the functional limits of the processor Only within specified operation limits can functionality and long term reliability be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of tim
146. nd will be updated in a future revision Writes to this register have no effect Offset 7Bh 7Ch Bit Description 15 8 Measurement Correction Factor 7 0 Temperature Target 7 4 3 9 OD Other Data These locations are reserved Writes to this register have no effect Offset 7Dh 7Eh Bit Description 15 0 RESERVED Intel Xeon Processor 7400 Series Datasheet 131 intel 7 4 3 9 1 7 4 4 Table 7 7 7 4 5 132 FDCKS Feature Data Checksum This location provides the checksum of the Feature Data Section Writes to this register have no effect Offset 7Fh Bit Description 7 0 Feature Data Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Checksums The PIROM includes multiple checksums Table 7 7 includes the checksum values for each section defined in the 128 byte ROM 128 Byte ROM Checksum Values Section Checksum Address Header ODh Processor Data 15h Processor Core Data 24h Cache Data 31h Package Data 37h Part Number Data 6Fh Thermal Ref Data 73h Feature Data 7Fh Checksums are automatically calculated and programmed by Intel The first step in calculating the checksum is to add each byte from the field to the next subsequent byte This result is then negated to provide the checksum Example For a byte string of AA445Ch the r
147. nput Output A31 B7 Source Sync Input Output Intel Xeon Processor 7400 Series Datasheet Pin Name N u Direction A32 A6 Source Sync Input Output A33 A7 Source Sync Input Output A34 C9 Source Sync Input Output A35 C8 Source Sync Input Output A36 F16 Source Sync Input Output A37 F22 Source Sync Input Output A38 B6 Source Sync Input Output A39 C16 Source Sync Input Output A20M F27 Async GTL Input ADS D19 Common Clk Input Output ADSTBO F17 Source Sync Input Output ADSTB1 F14 Source Sync Input Output APO E10 Common Clik nput Output AP1 D9 Common Clk Input Output BCLKO YA FSB Clk Input BCLK1 w5 FSB Clk Input BINIT F11 Common Clk Input Output BNR F20 Common Clk Input Output BPMO F6 Common Clik Input Output BPM1 F8 Common Clk Output BPM2 E7 Common Clk J Output BPM3 F5 Common Clk Input Output BPM4 E8 Common Clk Output BPM5 E4 Common Clk Input Output BPMbO AAA Common Clk Input Output BPMb1 AC1 Common Clk Output BPMb2 AE2 CommonClk Output BPMb3 AE3 Common Ik Input Output BPRI D23 Common CIk Input 65 intel Pin Listing Table 4 1 Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 3 of 16 Sheet 4 of 16 Pin Name Re ww Direction Pin Name u Ic um Direction BRO D20 Common
148. ns 2 15 4 7 T57 TDI TMS Hold Time 7 5 ns 2 15 4 7 T58 TDO Clock to Output Delay 0 7 5 ns 2 15 5 T59 TRST Assert Time 2 Trck 2 16 6 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Not 100 tested Specified by design characterization 3 This specification is based on the capabilities of the ITP debug port not on processor silicon 4 Referenced to the rising edge of TCK 5 Referenced to the falling edge of TCK 6 TRST must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor 7 Specification for a minimum swing defined between TAP V to Viz This assumes a minimum edge rate of 0 5 V ns It is recommended that TMS be asserted while TRST is being deasserted e Table 2 25 VID Signal Group AC Specifications T Parameter Min Max Unit Figure Notes1 2 T80 VID Step Time 5 HS 2 23 T81 VID Dwell Time 50 HS 2 23 T82 VID Down Transition to Valid Vcc min 0 HS 2 22 2 23 T83 VID Up Transition to Valid Vcc min 50 HS 2 22 2 23 T84 VID Down Transition to Valid Vcc max 50 HS 2 22 2 23 T85 VID Up Transition to Valid Vcc max 0 HS 2 22 2 23 Notes 1 See Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for addition information 2 Platform support for VID transitions is required for the processor to operate within specifications Table 2 26
149. nsient 445 N 1 3 8 100 bf Notes 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These parameters are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 This specification applies for thermal retention solutions that allow baseboard deflection 5 This specification applies either for thermal retention solutions that prevent baseboard deflection or for the Intel enabled reference solution CEK 6 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 7 Experimentally validated test condition used a heatsink mass of 1 Ibm 0 45 kg with 100 G acceleration measured at heatsink mass The dynamic portion of this specification in the product application can have flexibility in specific values but the ultimate product of mass times acceleration should not exceed this validated dynamic load 1 Ibm x 100 G 100 Ib 8 Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement representative of loads experienced by the package during heatsink installation Intel Xeon Processor 7400 Series Datasheet m Mechanical Specifications
150. of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MCERR 1 0 MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor FSB agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled e Asserted if configured for internal errors along with ERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the Intel 64 and 1A 32 Architectures Software Developer s Manual Volume 3 System Programming Guide PECI 1 0 PECI is a proprietary one wire bus interface that provides a communication channel between Intel processor and chipset components to external thermal monitoring devices See Section 6 3 Platform Environment Control Interface PECI for more on the PECI interface PROC ID 1 0 PROC ID signals are used to identify which processor is installed 00 Intel
151. on purposes only See Section 2 11 1 for further details on FMB guidelines 6 This specification represents the total current for GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END 7 Vm must be provided via a separate voltage source and must not be connected to Vcc This specification is measured at the pin 8 Minimum VCC and maximum ICC are specified at the maximum processor case temperature TCASE shown in Figure 6 1 9 This specification refers to the total reduction of the load line due to VID transitions below the specified VID 10 Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings 11 This specification applies to the VCCPLL pin 12 Baseboard bandwidth is limited to 20 MHz 13 Icc tpc is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guidelines for further details The processor is capable of drawing Icc tpc indefinitely Refer to Figure 2 6 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested 14 This is the maximum total cu
152. open drain output buffers All of the CMOS and Open Drain signals are required to be asserted deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state See Section 2 11 and Section 2 13 for the DC and AC specifications See Section 7 2 for additional timing requirements for entering and leaving the low power states Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor s be first in the TAP chain and followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Similar considerations must be made for TCK TMS and TRST Two copies of each signal may be required with each driving a different voltage level Intel Xeon Processor 7400 Series Datasheet Electrical Specifications 2 9 Note 2 10 Table 2 8 intel Mixing Processors Intel supports and validates multi processor configurations only in which all processors operate with the same FSB frequency core frequency number of cores and have the same internal cache sizes Mixing components operating at different internal clock frequencies or number of cores is not supported and will not be validated by Intel Processors within a system must operate at the same freque
153. or TM2 The TM1 and TM2 must both be enabled in BIOS for the processor to be operating within specifications When both are enabled TM2 will be activated first and TM1 will be added if TM2 is not effective Intel Thermal Monitor The Intel Thermal Monitor TM1 feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The Intel Thermal Monitor or Enhanced Thermal Monitor Thermal Monitor 2 must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and Intel Xeon Processor 7400 Series Datasheet 97 e n tel Thermal Specifications 6 2 3 Note 98 is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Intel Thermal Monitor is enabled and a high temperature situation exists that is TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amoun
154. or a Intel 150 A 15 Xeon X7460 Processor Launch FMB lcc REsET Icc RESET for a Intel 130 A 15 Xeon Processor E7400 Series Launch FMB Icc RESET Icc neser for a 6 Core 85 A 15 Intel Xeon Processor L7400 Series Launch FMB cc_RESET cc_RESET for a 4 Core 65 A 15 Intel Xeon Processor L7400 Series Launch FMB lec Toc Thermal Design Current 125 A 5 13 TDC for a Intel Xeon X7460 Processor Launch FMB lec toc Thermal Design Current 95 A 5 13 T TDC for a 6 core Intel Xeon Processor E7400 Series Launch FMB lec Toc Thermal Design Current 95 A CES TDC for a 4 core Intel Xeon Processor E7400 Series Launch FMB lec mme Thermal Design Current 70 A 5 13 TDC for a 6 Core Intel Xeon Processor L7400 Series Launch FMB lec Toc Thermal Design Current 55 A 5 43 TDC for a 4 Core Intel Xeon Processor L7400 Series Launch FMB Ism_vcc Icc for SMBus supply 100 122 5 mA I lec for Vr supply before Vcc 8 0 A 14 stable Icc for Vr supply after Vcc 7 0 stable Icc GTLREF lcc for 200 HA 6 GTLREF_DATA_MID GTLREF_DATA_END GTLREF ADD MID and GTLREF ADD END Icc vcceLL Icc for PLL supply 520 mA 11 26 Intel Xeon Processor 7400 Series Datasheet Electrical Specifications n tel Table 2 9 Voltage and Current Specifications Sheet 3 of 3 Itcc Icc for a Intel Xeon 150 A Symbol Parameter
155. or safety issues due to an abnormal condition on PECI the Host controller should take action to protect the system from possible damaging states If the Host controller cannot complete a valid PECI transactions of GetTempO with a given PECI device over 3 consecutive failed transactions or a one second max specified interval then it should take appropriate Intel Xeon Processor 7400 Series Datasheet 103 6 3 2 4 Table 6 7 104 Thermal Specifications actions to protect the corresponding device and or other system components from overheating The host controller may also implement an alert to software in the event of a critical or continuous fault condition PECI GetTempO and GetTemp1 Error Code Support The error codes supported for the processor GetTempO and GetTemp1 commands are listed inTable 6 7 below GetTempO and GetTemp1 Error Codes Error Code Description 0x8000 General sensor error 0x8002 Sensor is operational but has detected a temperature below its operational range underflow currently 309C absolute temperature 8 Intel Xeon Processor 7400 Series Datasheet Features 7 7 1 Table 7 1 7 2 intel Features Power On Configuration Options Several configuration options can be configured by hardware The Intel Xeon Processor 7400 Series samples its hardware configuration at reset on the active to inactive transition of RESET For specific
156. or system and environmental implementation details Intel Xeon Processor 7400 Series Datasheet Thermal Specifications n tel Figure 6 4 6 Core Intel Xeon Processor L7400 Series Thermal Profile 600 Toge 0481 x Power 45 C Temperature C 400 380 0 10 20 d 4 5 Eu Poner W Notes 1 Thermal Profile is representative of a volumetrically constrained platform Please refer to Table 6 5 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide for system and environmental implementation details Table 6 5 6 Core Intel Xeon Processor L7400 Series Thermal Profile Table Power W TcasE MAX C 0 45 10 49 3 20 53 6 30 57 9 40 62 2 50 66 5 60 70 8 65 73 Notes 1 Thermal Profile is representative of a volumetrically unconstrained platform 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC
157. ower Other K29 Vcc Power Other H9 Vcc Power Other K30 Vss Power Other H23 Vcc Power Other K31 Vcc Power Other H24 Vss Power Other L1 Vss Power Other H25 Vcc Power Other L2 Vcc Power Other Intel Xeon Processor 7400 Series Datasheet 75 n tel j Pin Listing Table 4 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Sheet 7 of 14 Sheet 8 of 14 Pin No Pin Name Signal Direction Pin No Pin Name Signal Direction Buffer Type Buffer Type L3 Vss Power Other N24 Vss Power Other L4 Vcc Power Other N25 Vcc Power Other L5 Vss Power Other N26 Vss Power Other L6 Vcc Power Other N27 Vcc Power Other L7 Vss Power Other N28 Vss Power Other L8 Vcc Power Other N29 Vcc Power Other L9 Vss Power Other N30 Vss Power Other L23 Vss Power Other N31 Vcc Power Other L24 Vcc Power Other P1 Vss Power Other L25 Vss Power Other P2 Vcc Power Other L26 Vcc Power Other P3 Vss Power Other L27 Vss Power Other P4 Vcc Power Other L28 Vcc Power Other P5 Vss Power Other 0129 vs Power 0ther P6 Vcc Power Other L30 Vcc Power Other P7 Vss Power Other L31 Vss Power Other P8 Vcc Power Other M1 Vcc Power Other P9 Vss Power Other M2 Vss Power Other P23 Vss Power Other M3 Vcc Power Other P24 Vcc Power Other M4 Vss Power Other P25 Vss Power Other M5 Vcc Power Other P26 Vcc Power Other M6 Vss Power Other P27 Vss Power Other M7
158. pending on each particular state See Figure 7 1 for a visual representation of the processor low power states The Extended HALT state is a lower power state than the HALT state or Stop Grant state The Extended HALT state must be enabled via the BI OS for the processor to remain within its specifications For processors that are already running at the lowest bus to core frequency ratio for its nominal operating point the processor will transition to the HALT state instead of the Extended HALT state The Stop Grant state requires chipset and BIOS support on multiprocessor systems In a multiprocessor system all the STPCLK signals are bussed together thus all processors are affected in unison When the STPCLK signal is asserted the processor enters the Stop Grant state issuing a Stop Grant Special Bus Cycle SBC for each processor The chipset needs to account for a variable number of processors asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states Refer to the applicable chipset specification Intel Xeon Processor 7400 Series Datasheet 105 intel 7 2 2 1 7 2 2 2 106 Normal State This is the normal operating state for the processor HALT or Extended HALT State The Extended HALT state CIE is enabled via the BIOS The Extended HALT state must be enabled for the processor to remain within its specifications The Extended HALT state requ
159. put RSO E21 Common Clk Input LL IDO B31 Power Other J Output RS1 D22 Common Clk Input LL ID1 B28 Power Other Output RS2 F21 Common Clk Input LOCK A17 Common Clk Input Output RSP C6 Common Clik Input MCERR D7 Common Clk Input Output SKTOCC A3 Power Other Output PECI C28 Power Other Input Output SM_CLK AC28 SMBus Input PROC IDO A30 Power Other Output SM DAT AC29 SMBus Input Output PROC ID1 B29 Power Other Output SM_EP_AO AA29 SMBus Input PROCHOT B25 Async GTL Output SM EP A1 AB29 SMBus Input PWRGOOD AB7 Async GTL Input SM_EP_A2 AB28 SMBus Input REQO B19 Source Sync Input Output SM_VCC AE28 Power Other REQ1 B21 Source Sync Input Output SM VCC AE29 Power Other REQ2 C21 Source Sync Input Output SM_WP AD29 SMBus Input REQ3 C20 Source Sync Input Output SMI C27 Async GTL Input REQ4 B22 Source Sync Input Output STPCLK D4 Async GTL Input Reserved A28 TCK E24 TAP Input Intel Xeon Processor 7400 Series Datasheet 67 n tel j Pin Listing Table 4 1 Pin Listing by Pin Name Table 4 1 Pin Listing by Pin Name Sheet 7 of 16 Sheet 8 of 16 Pin Name E Rid cd Direction Pin Name Wie E Direction ri ceu me nu Io Hl Power Other TDO E25 TAP Output Vcc H3 Power Other TESTHIO A16 Power Other Input Vcc H5 Power Other TESTHI1 W3 Power Other Input Vcc H7 Power Othe
160. r TESTIN1 D1 Power Other Input Vcc H9 Power Other TESTIN2 C2 Power Other Input Vcc H23 Power Other THERMTRIP F26 Async GTL Output Vcc H25 Power Other TMS A25 TAP Input Vec H27 Power Other TRDY E19 Common Clk Input Vcc H29 Power Other r Fae4 TP linwe Io H31 Power Other Vcc A8 Power Other Vcc J2 Power Other Vcc A14 Power Other Vcc J4 Power Other Ve f am Poweyother Wo J6 Power Other Vcc A24 Power Other Vec J8 Power Other Vcc B20 Power Other Vcc J24 Power Other Vcc C4 Power Other Vcc J26 Power Other Vcc C22 Power Other Vcc J28 Power Other Vcc C30 Power Other Vcc J30 j Power Other Vcc D8 Power Other Vcc K1 Power Other Vcc D14 Power Other Vcc K3 Power Other Vcc D18 Power Other Vcc K5 Power Other Vcc D24 Power Other Vcc K7 Power Other Vcc D31 Power Other Vcc K9 Power Other Vcc E6 Power Other Vcc K23 Power Other vec Leon Powe oter V K25 Power Other Vec E26 Power Other Vec K27 Power Other Vcc E28 Power Other Vcc K29 Power Other Vcc E30 Power Other Vcc K31 Power Other Vcc F1 Power Other Vcc L2 Power Other Vcc F4 Power Other Vcc L4 Power Other Vcc F29 Power Other Vcc L6 Power Other Vcc F31 Power Other Vcc L8 Power Other Vcc G2 j Power Other Vcc L24 Power Other Vcc G4 J Power Other Vcc L26 Power Other Vcc G6 J Power Other Vcc L28 Power Other Vcc G8 Power Other Vcc L30 Power Other Vcc G24 Power Other Vcc M1 Power Other Vcc G26 Power Other Vcc
161. r Vss Y13 Power Other Vr B5 J Power Other Vss Y19 Power Other Vir B12 Power Other Vss Y25 Power Other Vr C5 Power Other Vss AA2 Power Other Vr C10 Power Other Vss AA9 Power Other Vit D10 Power Other Vss AA15 Power Other Vit E11 Power Other Vss AA17 Power Other Vit E12 Power Other Vss AA23 Power Other Vit F10 Power Other Vss AA30 Power Other Vit W6 Power Other Vss AB1 Power Other Vr WI Power Other Vss AB5 Power Other Vr W8 Power Other Vss AB11 Power Other Vr Y6 Power Other Vss AB21 Power Other Vit Y10 Power Other Vss AB27 Power Other Vir AAT Power Other Vss AB31 Power Other Vr AA12 Power Other Vss AC2 Power Other Vit AC4 Power Other Vss AC7 Power Other Vit AC10 Power Other Vss AC13 Power Other Vir AD5 Power Other Vss AC19 Power Other Vr AD12 Power Other Vss AC25 Power Other Vr AE4 Power Other Vr AER Power Other VIT SEL A2 Power Other Output 72 Intel Xeon Processor 7400 Series Datasheet intel Pin Listing 4 1 2 Pin Listing by Pin Number Table 4 2 Pin Listing by Pin Number Sheet 1 of 14 Pin No Pin Name Signal Direction Buffer Type A1 VID5 Power Other Output A
162. r discrete points that constitute the thermal profile 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide for system and environmental implementation details Table 6 3 6 Core Intel Xeon Processor E7400 Series Thermal Profile Table Power W TcasE MAX C 0 45 0 10 47 6 20 50 1 30 52 7 40 55 2 50 57 8 60 60 3 70 62 9 80 65 4 90 68 0 Notes 1 Thermal Profile is representative of a volumetrically unconstrained platform 2 Implementation of Thermal Profile should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide for system and environmental implementation details Intel Xeon Processor 7400 Series Datasheet 93 intel Thermal Specifications Figure 6 3 4 Core Intel Xeon Processor E7400 Series Thermal Profile Table 6
163. r disable the TCC Intel recommends the Vr power supply also be removed upon assertion of THERMTRIP This specification requires that the VID and BSEL signals be sampled no earlier than 10 us after Vcc at Vcc Boot voltage and V are stable Parameter must be measured after applicable voltage level is stable Stable means that the power supply is in regulation as defined by the minimum and maximum DC AC specifications for all components being powered by it The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor Measured between 0 3 Vr and 0 7 Vr See Table 2 19 for BCLK specifications Table 2 23 Front Side Bus AC Specifications Reset Conditions T Parameter Min Max Unit Figure Notes T45 A 39 3 BR 1 0 INIT SMI Setup Time Reset Configuration Signals 480 us 2 20 1 T46 A 39 3 INIT SMI Hold Time Reset Configuration Signals 2 20 BCLKs 2 20 2 T47 BR 1 0 Hold Time Reset Configuration Signals 2 2 BCLKs 2 20 2 Notes 1 2 Intel Xeon Processo Before the clock that de asserts RESET After the clock that de asserts RESET r 7400 Series Datasheet 39 E e n tel Electrical Specifications Table 2 24 TAP Signal Group AC Specifications T Parameter Min Max Unit Figure Notes 1 2 8 T55 TCK Period 30 ns 2 8 3 T56 TDI TMS Setup Time 7 5
164. r issued Stop Grant Acknowledge special bus cycle Once the STPCLK pin has been asserted it may only be deasserted once the processor is in the Stop Grant state All processor cores will enter the Stop Grant state once the STPCLK pin is asserted Additionally all processor cores must be in the Stop Grant state before the deassertion of STPCLK Since the AGTL signal pins receive power from the front side bus these pins should not be driven allowing the level to return to Vrr for minimum power drawn by the termination resistors in this state In addition all other input pins on the front side bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus see Section 7 2 4 1 Intel Xeon Processor 7400 Series Datasheet Features 7 2 4 7 2 4 1 7 2 4 2 7 3 Note intel While in the Stop Grant state SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each
165. rce Synchronous Data Strobe 4 15 0 9375 n ns 2 14 11 14 Setup Time to BCLK 1 0 T30 Data Strobe n DSTBN Output 3 28 4 38 ns 2 14 13 Valid Delay T31 Address Strobe Output Valid Delay 2 81 3 91 ns 2 13 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Not 100 tested Specified by design characterization 3 All source synchronous AC timings are referenced to their associated strobe at nominal GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END Source synchronous data signals are referenced to the falling edge of their associated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at nominal GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END at the processor pads 4 Unless otherwise noted these specifications apply to both data and address timings 5 Valid delay timings for these signals are specified into the test circuit described in Figure 2 7 and with GTLREF DATA MID GTLREF DATA END GTLREF ADD MID and GTLREF ADD END at 0 67 V 6 Specification is for a minimum swing into the test circuit described in Figure 2 7 and defined between AGTL Vi max tO Vin M N This assumes an edge rate of 3 0 V ns to 5 5 V ns 7 All source synchronous signals must meet the specified setup time to BCLK as well as th
166. re Frequency 16 bit binary number in MHz 1F 20h 16 Maximum Core VID Maximum Vcc requested by VID outputs in m 21 22h 16 Minimum Core Voltage Minimum processor DC Vcc in mV 23h 8 Tcase Maximum Maximum case temperature spec in C 24h 8 Checksum 1 byte checksum Cache Data 25 26h 16 Reserved Reserved for future use 27 28h 16 L2 Cache Size 16 bit binary number in KB 29 2Ah 16 L3 Cache Size 16 bit binary number in KB 2B 2Ch 16 Maximum Cache CVID Maximum VcAcyg requested by CVID outputs in mV 2D 2Eh 16 Minimum Cache Voltage Minimum processor DC VcAcug in mV 2F 30h 16 Reserved Reserved 31h 8 Checksum 1 byte checksum Package Data 32 35h 32 Package Revision Four 8 bit ASCII characters 36h 8 Reserved Reserved for future use 37h 8 Checksum 1 byte checksum Part Number Data 38 3Eh 56 Processor Part Number Seven 8 bit ASCII characters 3F 4Ch 112 Reserved Reserved 4D 54h 64 Processor Electronic 64 bit identification number Signature 55 6Eh 208 Reserved Reserved 6Fh 8 Checksum 1 byte checksum Intel Xeon Processor 7400 Series Datasheet m Features n tel Table 7 6 Processor Information ROM Data Sections Sheet 3 of 3 Offset Section SE Function Notes Bits Thermal Ref Data 70h 8 Reserved Reserved 71 72h 16 Reserved Reserved 73h 8 Checksum 1 byte checksum Feature Data 74 77h 32 Processor Core Feature From CPUID function 1 EDX contents Fla
167. renced at 0 5 V at the processor pins 6 All AC timings for the SMBus signals are referenced to the SM_CLK at 0 5 SM_VCC at the processor pins All SMBus signal timings SM_DAT SM_CLK etc are referenced at The circuit used to test the AC specification is shown in Figure 2 7 Electrical Test Circuit Vit Vir Buffer RLoAD 48 ohms 169 ps in 1200 mils Ee AC Timings specified at this point Intel Xeon Processor 7400 Series Datasheet 41 intel Figure 2 8 Figure 2 9 Figure 2 10 42 TCK Clock Waveform Electrical Specifications T k fo XK GE Nee tette ice To T T55 Period V1 V2 For rise and fall times TCK is measured between 20 and 80 points on the waveform V3 TCK is referenced to 0 5 V Differential Clock Waveform I uem ee cc mp eee Pay ror Overshoot BCLK1 vu Rising Edge BE NN NEE N dE E NA GE Ringback aay eee ee Crossing VI Crossing Ringback Threshold j Voltage Voltage Margin Region Ba TAT RRE D GER Falling Edge E E ales U E ree ee e ET EE Ringback BCLKO LL VL mv aya A ala ka Undershoot S gt Tp T1 BCLK 1 0 period Differential Clock Crosspoint Specification 650 0 M Eege SE gt Le 550 mV E 500 550 0 5 VHavg 700 o 450 a 2 400 o 250 0 5 VHavg 7
168. reporting Intel recommends that fault prediction handlers rely on this mechanism to assess processor cache health Please refer to the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A for more detailed information Intel Xeon Processor 7400 Series Datasheet Introduction intel 1 1 Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Commonly used terms are explained here for clarification Intel Xeon Processor 7400 Series Intel 64 bit microprocessor intended for multi processor servers The Intel Xeon Processor 7400 Series is a single die implementation based on Intel s 45 nanometer process in the FC mPGA8 package with four or six processor cores and L3 cache Processor core Processor core with integrated L1 cache The L2 cache is shared between two cores on the die and interfaces to other processor pairs and the L3 cache through a simplified direc
169. rials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Pins Gold Plated Copper Intel Xeon Processor 7400 Series Datasheet 61 m e n tel Mechanical Specifications Figure 3 9 Processor Markings Figure 3 9 shows the topside markings and Figure 3 10 shows the bottom side markings on the processor These diagrams are to aid in the identification of the Intel amp Xeon Processor 7400 Series Please note that the figures in this section are not to scale Processor Topside Markings 2D Matrix Includes ATPO and Serial Number front end mark Processor Name i m 05 TS Pin 1 Indicator Notes 1 Character size for laser markings is 17 Point height 1 27 mm 50 mils width 0 81 mm 32 mils 2 All characters will be in upper case Figure 3 10 Processor Bottom Side Markings 62 Pin 1 Indicator 2D Matrix Includes ATPO and Serial Number front end mark Processor Speed Cache Bus cM MF 7xxx 2933 16M 1066 SL9HA COSTA RICA S Spec C0096109 0021 Country of Assy FPO Serial 8 13 Characters Intel amp Xeon Processor 7400 Series Datasheet intel Figure 3 11 shows the top view of the processor pin coordinates The coordinates are referred to throughout the document to identify processor pins Processor Pin Out Coordinates
170. rmation about these signals including termination recommendations refer to the appropriate platform design guideline COMP 3 0 l COMP 3 0 must be terminated to VSS on the baseboard using precision resistors These inputs configure the AGTL drivers of the processor Refer to the appropriate platform design guidelines for implementation details 82 Intel Xeon Processor 7400 Series Datasheet Signal Definitions Table 5 1 Signal Definitions Sheet 3 of 8 intel Name D 63 0 Type 1 0 Description D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to strobes and DBI DSTBN DSTBP BBIE Data Group D 15 0 0 D 31 16 w N ej oO 1 D 47 32 2 D 63 48 3 Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inve
171. rrent drawn from the Vor plane by the processor with R77 enabled This specification does not include the current coming from on board termination Rrr through the signal line Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine the total I drawn by the system This parameter is based on design characterization and is not tested 15 Icc reset is specified while PWRGOOD and RESET are asserted Refer to Table 2 22 for the PWRGOOD to RESET de assertion time specification and Table 2 23 for the RESET Pulse Width specification Intel Xeon Processor 7400 Series Datasheet 27 intel Figure 2 1 Figure 2 2 28 Electrical Specifications Intel Xeon X7460 Processor Load Current versus Time 155 150 145 140 135 130 Sustained Current A 125 120 0 1 1 10 100 1000 Time Duration s Notes 1 Icc Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than TDC 2 Not 10096 tested Specified by design characterization Intel Xeon Processor E7400 Series Load Current versus Time Sustained Current A 135 125 120 115 110 105 100 95 90 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 2 lice Not Processor or Voltage Regulator thermal protection circuitry s
172. rst clock of a low to high voltage transition With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLKO ADS HIT HITMZ etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as rising edge of BCLKO Asynchronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 2 4 identifies which signals are common clock source synchronous and asynchronous Intel Xeon Processor 7400 Series Datasheet Electrical Specifications Table 2 4 FSB Signal Groups intel Signal Group AGTL Common Clock Input Type Synchronous to BCLK 1 0 Signals BPRI DEFER RESET RS 2 0 RSP TRDY AGTL Common Clock Output Synchronous to BCLK 1 0 BPM4 BPM 2 1 BPMb 2 1 AGTL Common Clock I O Synchronous to BCLK 1 0 ADS AP 1 0 BINIT 2 BNR 2 BPM5 BPM3 BPMO BPMb3 BPMbOZ BR 1 0 DBSY DP 3 0 DRDY HIT 2 HITM 2 LOCK MCERR 2 AGTL Source Synchronous I O Synchronous to assoc strobe Signals Associated Strobe REQ 4 0 ADSTBO A 37 36 16 3 A 39 38 35 17 ADSTB1 D 15 0 DBIO D 31 16 DBI1 D 47 32 DBI2 D 63 48 DBI3 DSTBPO DSTBNO DSTBP1 DST
173. rted and therefore sampled active high Notes DBI 3 0 1 0 DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within within a 16 bit group would have been asserted electronically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment to Data Bus Bus Signal Data Bus Signals DBIO D 15 0 DBI1 D 31 16 DBI2 D 47 32 DBI3 D 63 48 DBSY DEFER 1 0 DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor FSB agents DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all processor FSB agents DP 3 0 1 0 DP 3 0 Data Parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all processor FSB agents DRDY 1 0 DRDY Data Ready is asserted
174. rtion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to Vol 3 of the Intel 64 and IA 32 Architectures Software Developer s Manual and the AP 485 Intel Processor Identification and the CPUID Instruction application note FORCEPR I The FORCEPR force power reduction input can be used by the platform to cause the Intel Xeon Processor 7400 Series to activate the Thermal Control Circuit TCC GTLREF_ADD_MID l GTLREF_ADD determines the signal reference level for AGTL address and GTLREF ADD END common clock input pins GTLREF_ADD is used by the AGTL receivers to determine if a signal is a logical 0 or a logical 1 Please refer to Table 2 17 and the appropriate platform design guidelines for additional details GTLREF_DATA_MID l GTLREF_DATA determines the signal reference level for AGTL data input pins GTLREF DATA END GTLREF_DATA is used by the AGTL receivers to determine if a signal is a logical 0 g AA or a logical 1 Please refer to Table 2 17 and the appropriate platform design guidelines for additional details HIT 1 0 HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation HITM 1 0 results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be
175. s on these options please refer to Table 7 1 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset PWRGOOD signal remains asserted and a power on reset Power On Configuration Option Pins Configuration Option Pin Name Notes Output tri state SMI 1 2 3 Execute BIST Built In Self Test A3 1 2 Disable MCERR observation AQ 1 2 Disable BINIT observation A103 1 2 Cluster ID A 12 11 1 2 Disable bus parking A15 1 2 Notes 1 Asserting this signal during RESET will select the corresponding option 2 Address pins not identified in this table as configuration options should not be asserted during RESET 3 Requires de assertion of PWRGOOD Disabling of any of the cores within the Intel Xeon Processor 7400 Series must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR will allow for the disabling of a single core per core pair within the Intel Xeon Processor 7400 Series package Clock Control and Low Power States The Intel Xeon Processor 7400 Series supports the Extended HALT state also referred to as C1E in addition to the HALT state and Stop Grant state to reduce power consumption by stopping the clock to internal sections of the processor de
176. signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 1 0 REQ 4 0 Request Command must connect the appropriate pins of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the AP 1 0 signal description for details on parity checking of these signals RESET Asserting the RESET signal resets all processors to known states and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least 1 ms after VCC and BCLK have reached their proper specifications On observing active RESET all FSB agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 7 1 This signal does not have on die termination and must be terminated on the system board RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor FSB agents RSP RSP
177. sor 7400 Series Datasheet Features 7 4 3 1 10 7 4 3 1 11 7 4 3 1 12 7 4 3 2 7 4 3 2 1 intel This location provides the offset to the Other Data Section Writes to this register have no effect ODA Other Data Address Offset OAh Bit Description 7 0 Other Data Address Byte pointer to the Other Data section 00h Other Data section not present O1h 7Dh Reserved 7Eh Other Data section pointer value 7Fh FFh Reserved RES1 Reserved 1 This locations are reserved Writes to this register have no effect Offset OBh OCh Bit Description 15 0 RESERVED 0000h FFFFh Reserved HCKS Header Checksum This location provides the checksum of the Header Section Writes to this register have no effect Offset ODh Bit Description 7 0 Header Checksum One Byte Checksum of the Header Section 00h FFh See Section 7 4 4 for calculation of the value Processor Data This section contains two pieces of data The S spec of the part in ASCII format 1 2 bit field to declare if the part is a pre production sample or a production unit SQNUM S Spec Number This location provides the S SPec number of the processor The S spec field is six ASCII characters wide and is programmed with the same S spec value as marked on the processor If the value is less than six characters in length leading spaces 20h are programmed in this field Writes to
178. sors See Table 2 10 and Figure 2 4 V 2 3 5 8 Launch FMB Vcc Boot Default Vcc Voltage for initial 1 1 V E power up Vvip STEP VID step size during a 12 5 mV i transition VVID SHIFT Total allowable DC load line 450 mV 9 i shift from VID steps Ver FSB termination voltage 1 045 1 100 1 155 V 7 12 DC AC specification VccPLL PLL supply voltage DC AC 1 425 1 50 1 605 V specification SM Vcc SMBus supply voltage 3 135 3 300 3 465 lec Icc for a 6 Core Intel 150 A 3 4 5 8 Xeon X7460 Processor Launch FMB lec Icc for a Intel Xeon 130 A 3 4 5 8 Processor E7400 Series Launch FMB lec Icc for a 4 Core Intel 130 A 3 4 5 8 Xeon Processor E7400 Series Launch FMB Intel Xeon Processor 7400 Series Datasheet Electrical Specifications n tel Table 2 9 Voltage and Current Specifications Sheet 2 of 3 Symbol lec Parameter Icc for an 6 Core Intel Xeon Processor L7400 Series Launch FMB Min Typ Max 85 Unit Notes 1 3 4 5 8 lec Icc for an 4 Core Intel Xeon Processor L7400 Series Launch FMB 65 3 4 5 8 cc_RESET lec RESET for a Intel Xeon X7460 Processor Launch FMB 150 15 lcc REsET Icc RESET lec RESET for a Intel Xeon Processor E7400 Series Launch FMB Icc reset for a 6 Core Intel Xeon Processor L7400 Series Launch FMB 130 85 v5 15 lcc REsET lec RESET for a
179. ssor 7400 Series Thermal Mechanical Design Guide Thermal Specifications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature Tease specifications as defined by the applicable thermal profile see Table 6 2 and Figure 6 1 for the Intel Xeon X7460 Processor Table 6 3 and Figure 6 2 for the 6 core Intel Xeon Processor E7400 Series Figure 6 3 and Table 6 4 for the 4 core Intel amp Xeon Processor E7400 Series and Table 6 5 and Figure 6 4 for the 6 core Intel Xeon Processor L7400 Series and Table 6 6 and Figure 6 5 for the 4 core Intel Xeon Processor L7400 Series Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide The Intel Xeon Processor 7400 Series implement a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI bus as described in Section 6 3 If the value reported via PECI is less than TCONTROL then the case temperature is permit
180. ssor Information ROM MSB 0 or the Scratch EEPROM MSB 1 Table 7 4 Read Byte SMBus Packet Slave Comman Slave S Adares Write A d Code AJS Address Read A Data 1 P 1 7 bits I 1 8 bits 1 1 7 bits 1 1 8 bits 1 1 Table 7 5 Write Byte SMBus Packet S Slave Address Write A Command Code A Data A P 1 7 bits 1 1 8 bits 1 8 bits 1 I 112 Intel Xeon Processor 7400 Series Datasheet Features 7 4 3 Processor Information ROM PI ROM intel The lower half 128 bytes of the SMBus memory component is an electrically programmed read only memory with information about the processor This information is permanently write protected Table 7 6 shows the data fields and Section 7 4 3 provides the formats of the data fields included in the Processor Information ROM PIROM The PIROM consists of the following sections Table 7 6 Header Processor Data Processor Core Data Cache Data Package Data Part Number Data Thermal Reference Data Feature Data Other Data Processor I nformation ROM Data Sections Sheet 1 of 3 of Offset Section Bits Function Notes Header 00h 8 Data Format Revision Two 4 bit hex digits 01 02h 16 PIROM Size Size in bytes MSB first 03h 8 Processor Data Address Byte pointer 00h if not present 04h 8 Processor Core Data Byte pointer
181. ssor can not be exceeded If the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals System Management Bus SMBus I nterface The Intel Xeon Processor 7400 Series package includes an SMBus interface which allows access to a memory component with two sections referred to as the Processor Information ROM and the Scratch EEPROM These devices and their features are described below The SMBus on package thermal sensor has been removed and is no longer used Refer to Section 6 3 for details about the new digital thermometer and PECI interface The processor SMBus implementation uses the clock and data signals of the System Management Bus SMBus Specification It does not implement the SMBSUS signal Layout and routing guidelines are available in the Caneland Platform Design Guide document For platforms which do not implement any of the SMBus features found on the processor all of the SMBus connections except SM VCC to the socket pins may be left unconnected SM CLK SM DAT SM EP A 2 0 SM WP Intel Xeon Processor 7400 Series Datasheet Features Figure 7 2 7 4 1 Logical Schematic of SMBus Circuitry SM_VCC VCC SM_EP_AO DATA SM EP A1 Processor 07 Information CLK SM EP A2 ROM and Scratch SM WP EEPROM 1Kbit each vss SM_
182. ssor will return to the Stop Grant state or HALT state as appropriate Extended HALT Snoop State The Extended HALT Snoop state is the default Snoop state when the Extended HALT state is enabled via the BIOS The processor will remain in the lower bus to core frequency ratio and VID operating point of the Extended HALT state While in the Extended HALT Snoop state snoops and interrupt transactions are handled the same way as in the HALT Snoop state After the snoop is serviced or the interrupt is latched the processor will return to the Extended HALT state Enhanced Intel SpeedStep Technology Intel Xeon Processor 7400 Series support Enhanced Intel SpeedStep Technology This technology enables the processor to switch between multiple frequency and voltage points which results in platform power savings Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform Switching between voltage frequency states is software controlled Not all Intel Xeon Processor 7400 Series may be capable of supporting Enhanced Intel SpeedStep Technology More details on which processor frequencies will support this feature will be provided in future releases of the Intel Xeon Processor 7400 Series Specification Update when available Intel Xeon Processor 7400 Series Datasheet 109 intel 7 4 Note 110 Enhanced Intel SpeedStep Technology creates processor performance states P states or vo
183. st specifications and before placing your product order 12C is a two wire communications bus protocol developed by Philips SMBus is a subset of the ZC bus protocol and was developed by Intel Implementations of the 12C bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Intel Pentium Intel Xeon Enhanced Intel SpeedStep Technology and Intel NetBurst are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Intel 64 Formerly called Intel EM64T requires a computer system with a processor chipset BIOS OS device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations Intel 64 enabled OS BIOS device drivers and applications may not be available Check with your vendor for more information Other names and brands may be claimed as the property of others Copyright O 2008 Intel Corporation 2 Intel Xeon Processor 7400 Series Datasheet Contents 1 Bi de TT d LEE 9 fu Een ge lu te e Le KEE 11 1 2 State of Data coeno Sg e
184. t interface All AC timing and signal integrity specifications are at the pads of the processor die FC mPGAS8 The Intel Xeon Processor 7400 Series is available in a Flip Chip Micro Pin Grid Array 8 package consisting of a single processor die mounted on a pinned substrate with an integrated heat spreader IHS This packaging technology employs a 1 27 mm 0 05 in pitch for the substrate pins mPGA604 The Intel Xeon Processor 7400 Series processor mates with the system board through this surface mount 604 pin zero insertion force ZIF socket FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Multi I ndependent Bus MI B A front side bus architecture with one processor on each bus rather than a FSB shared between multiple processor agents The MIB architecture provides improved performance by allowing increased FSB speeds and bandwidth MTS Mega Transfers per Second Flexible Motherboard Guidelines FMB Are estimates of the maximum values the Intel Xeon Processor 7400 Series will have over certain time periods The values are only estimates and actual specifications for future processors may differ Functional Operation Refers to the normal operating conditions in which all processor spec
185. t of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a thermal solution designed to meet the Intel Xeon Processor 7400 Series Thermal Profiles it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Intel Xeon Processor 7400 Series Thermal Mechanical Design Guide or information on designing a thermal solution The duty cycle for the TCC when activated by the Intel Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Intel Thermal Monitor 2 The Intel Xeon Processor 7400 Series adds supports for an Enhanced Thermal Monitor capability known as Intel Thermal Monitor 2 TM2 This mechanism provides an efficient means for limiting the processor temperature by reducing
186. te 2 This specification is characterized by design 3 Processors running in the lowest bus ratio will enter the HALT state when the processor has executed the HALT and MWAIT instruction since the processor is already in the lowest core frequency and voltage operating point The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will first transition the VID to the original value and then change the bus to core frequency ratio back to the original value Intel Xeon Processor 7400 Series Datasheet 107 intel Figure 7 1 7 2 3 108 Stop Clock State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Normal State gt Extended HALT or HALT State N j INIT BINIT INTR NMI SMI BCLK running DESCH RESET FSB interrupts Snoops and interrupts allowed A A x P Snoop Snoop STPCLK STPCLK amp Event Event Asserted De asserted ed Occurs Serviced os SF lt Extended HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Y Stop Grant State EE Stop Grant Snoop State BCLK running j BCLK running Snoops and interrupts allowed 4 Snoop Event Serviced Service snoops to caches Stop Grant State When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processo
187. ted to exceed the Thermal Profile If the value reported via PECI is greater than or equal to TCONTROL then the processor case temperature must remain at or below the temperature as specified by the thermal profile The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 6 2 Processor Thermal Features Systems that implement fan speed control must be designed to use this data Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications Intel has developed a thermal profile of which can be implemented with the Intel Xeon X7460 Processor to ensure adherence to Intel reliability requirements The Intel Xeon X7460 Processor Thermal Profile see Figure 6 1 Table 6 2 is representative of a volumetrically unconstrained thermal solution that is industry Intel Xeon Processor 7400 Series Datasheet 89 e n tel Thermal Specifications enabled 2U heatsink In this scenario it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Intel has developed the thermal profile to allow customers to choose the thermal solution and environmental parameters that best suit their platform implementation Refer to the Intel Xeon Processor 7400 Series Ther
188. the power consumption within the processor The Intel Thermal Monitor or Enhanced Thermal Monitor must be enabled for the processor to be operating within specifications TM2 requires support for dynamic VID transitions in the platform Not all Intel Xeon Processor 7400 Series are capable of supporting TM2 More detail on which processor frequencies will support TM2 will be provided in future releases of the Intel Xeon Processor 7400 Series Specification Update when available When Intel Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated for all processor cores The TCC causes the processor to adjust its operating frequency via the bus multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption A processor enabled for Intel Thermal Monitor 2 includes two operating points each consisting of a specific operating frequency and voltage which is identical for both processor dies The first operating point represents the normal operating condition for the processor Under this condition the core frequency to system bus multiplier utilized by the processor is that contained in the CLOCK_FLEX_MAX MSR and the VID that is specified in Table 2 3 The second operating point consists of both a lower operating frequency and voltage The lowest operating frequency is determined by
189. tion of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction ADS 1 0 ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 39 3 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must be connected to the appropriate pins on all Intel Xeon Processor 7400 Series FSB agents ADSTB 1 0 1 0 Address strobes are used to latch A 39 3 and REQ 4 0 on their rising and falling edge Strobes are associated with signals as shown below Signals Associated Strobes REQ 4 0 ADSTBO A 37 36 16 3 A 39 38 35 17 ADSTB1 AP 1 0 1 0 AP 1 0 Address Parity are driven by the requestor one common clock after ADS A 39 3 REQ 4 0 are driven A correct parity signal is electrically high if an even number of covered signals are electrically low and electrically low if an odd number of covered signals are electrically low This allows parity to be electrically high when all the covered signals are electrically high AP 1 0 should connect the appropriate pins of all processor FSB agents The following table defines the coverage for these signals Request Signals Subphase 1 Subphase 2 A 39 24
190. to Valid Vcec min VID Up to Valid Vcc max VID Up to Valid Vcc min m m 1 Tc gt lt _ Td Figure 2 23 VI D Step Times and Vcc Waveforms Ta Tb VID n EXE n 6 VID yp n 4 n 3 n 2 Voc max Ta T80 Tb T81 Tc T84 Td T82 Te T85 Tf T83 Voc min mE Td Voc max n 3 Te Tc LI 2H S GE Tf VID Step Time Thermal Monitor 2 Dwell Time VID Down to Valid Voc max VID Down to Valid Voc min VID Up to Valid Vcc max VID Up to Valid Vcc min Note This waveform illustrates an example of an Intel Thermal Monitor 2 transition or an Intel Enhanced SpeedStep Technology transition that is six VID steps down from the current state and six steps back up Any arbitrary up or down transition can be generalized from this waveform Voc min n 4 Intel Xeon Processor 7400 Series Datasheet 49 50 Electrical Specifications Intel Xeon Processor 7400 Series Datasheet 5 Mechanical Specifications n tel 3 Figure 3 1 Note 3 1 Mechanical Specifications The Intel Xeon Processor 7400 Series is packaged in a lead free FC mPGA8 package that interfaces with the motherboard via a mPGA604 socket The package consists of the processor die mounted on a substrate pin carrier An IHS is attached to the package subs
191. trate and die and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together The package components shown in Figure 3 1 include the following 1 IHS Processor die FC mPGA8 package Pin side capacitors u PS WN Package pin Processor Package Assembly Sketch Figure 3 1 is not to scale and is for reference only The mPGA604 socket is not shown Package Mechanical Drawing The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include 1 Package reference with tolerances total height length width etc 2 IHS parallelism and tilt 3 Pin dimensions 4 Top side and back side component keepout dimensions 5 Reference datums All drawing dimensions are in mm in Intel Xeon Processor 7400 Series Datasheet 51 Mechanical Specifications intel Figure 3 2 Intel Xeon Processor 7400 Series Package Drawing Sheet 1 of 2 e i w a o a lt gene o 3 2 3 S 8 a a a Se o B m E 5 S z aja wi El lej l sts 9 e co gt E 8 2 l L i c xd 5 o ME a s 2 i i e I e EH S
192. upling guidelines are described in the appropriate platform design guidelines Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 inputs directly controls the FSB interface speed as well as the core frequency of the processor As in previous processor generations the processor core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier is set during manufacturing The default setting is for the maximum speed of the processor It is possible to override this setting using software This permits operation at lower frequencies than the processor s tested frequency Intel Xeon Processor 7400 Series Datasheet m Electrical Specifications n tel Table 2 1 2 3 1 Table 2 2 The processor core frequency is configured during reset by using values stored internally during manufacturing The stored value sets the highest bus fraction at which the particular processor can operate If lower speeds are desired the appropriate ratio can be configured via the CLOCK_FLEX_MAX Model Specific Register MSR For details of operation at core frequencies lower than the maximum rated processor speed Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 1 0 input with exceptions for spread spectrum clocking Processor DC and AC specifications for the BCLK 1 0 inputs are provided in Table 2 18 and Table 2 19 respectively
193. ut Output D52 AB13 Source Sync Input Output D13 AB22 Source Sync Input Output D53 AA11 Source Sync Input Output D14 AB19 Source Sync Input Output D543 AA10 Source Sync Input Output D15 AA19 Source Sync Input Output D55 AB10 Source Sync Input Output D16 AE26 Source Sync Input Output D56 ACH Source Sync Input Output D17 AC26 Source Sync Input Output D57 AD7 Source Sync Input Output D18 AD25 Source Sync Input Output D58 AE7 Source Sync Input Output D19 AE25 Source Sync Input Output D59 AC6 Source Sync Input Output D20 AC24 Source Sync Input Output D60 AC5 Source Sync Input Output D21 AD24 Source Sync Input Output D61 AA8 Source Sync Input Output D22 AE23 Source Sync Input Output D62 Y9 Source Sync Input Output D23 AC23 Source Sync Input Output D63 AB6 Source Sync Input Output D24 AA18 Source Sync Input Output DBIO AC27 Source Sync Input Output D25 AC20 Source Sync Input Output DBI1 AD22 Source Sync Input Output D26 AC21 Source Sync Input Output DBI2 AE12 Source Sync Input Output D27 AE22 Source Sync Input Output DBI3 AB9 Source Sync Input Output D28 AE20 Source Sync Input Output DBSY F18 Common Clk Input Output D29 AD21 Source Sync Input Output DEFER C23 Common Clk Input D30 AD19 Source Sync Input Output DPO AC18 Common Clk Input Output 66 Intel Xeon Processor 7400 Series Datasheet Pin Listing Table 4 1 Pin Listing by Pin Name Sheet 5 of 16 intel Tab
194. utput AE29 SM_VCC Power Other AD19 D30 Source Sync Input Output AE30 Reserved AD20 Vcc Power Other AD21 D29 Source Sync Input Output Intel Xeon Processor 7400 Series Datasheet 79 80 Pin Listing Intel Xeon Processor 7400 Series Datasheet Signal Definitions 5 Signal Definitions 5 1 Signal Definitions Table 5 1 Signal Definitions Sheet 1 of 8 Name Type Description Notes A 39 3 1 0 A 39 3 Address define a 240 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In Sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the processor FSB A 39 3 are protected by parity signals AP 1 0 A 39 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 39 3 pins to determine their power on configuration See Section 7 1 A20M If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting AZOM emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recogni
195. vider of 196 resistors The minimum and maximum specifications account for this resistor tolerance Refer to the appropriate platform design guidelines for implementation details The Vor referred to in these specifications is the instantaneous Vr 4 SUE EE termination resistance measured at Vo of the AGTL output driver Measured at 0 33 Vr Rrr is connected to on die 5 COMP resistance must be provided on the system board with 1 resistors See the applicable platform design guide for implementation details Table 2 18 FSB Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 Vu Input Low Voltage 0 150 0 0 15 V 2 9 Vu Input High Voltage 0 660 0 710 0 850 V 2 9 VcRoss abs Absolute Crossing 0 250 0 350 0 550 V 2 9 2 10 2 8 Point VcRossi rel Relative Crossing 0 250 N A 0 550 V 2 9 2 10 3 8 9 11 Point 0 5 VHavg 0 700 0 5 VHavg 0 700 Vcnoss Range of Crossing N A N A 0 140 V 2 9 2 10 Points Vos Overshoot N A N A Vy 0 300 V 2 9 4 Vus Undershoot 0 300 N A N A V 2 9 5 VnBM Ringback Margin 0 200 N A N A V 2 9 6 VTR Threshold Region Vcnoss 0 100 N A VcRoss 0 100 V 2 9 7 lu Input Leakage N A N A 100 uA 10 Current Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLKO is equal to th

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