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VisualDSP++ 3.5 Loader Manual for 16-Bit

1. VisualD SP 3 5 Loader M anual for 16 Bit Processors ADSP 218x DSP Loader Guide EPROM Booting BDMA To generate a PROM image for EPROM booting invoke the elfspl21 exe loader from the command line or change the V isualD SP project type to Splitter file and specify options on the Project O ptions dialog box s Load page T he command line syntax is discussed on page 5 7 For information on how to set up the loader options from within the VisualD SP see online H elp After reset the AD SP 218x D SP loads the 96 bytes from PROM address 0x0000 into the first 32 locations of on chip PM memory Assuming these 96 bytes consist of 32 valid instructions the D SP executes this piece of program preloader afterwards U sually 32 instructions are not sufficient to load the complete project data therefore bootstrapping continues and the preloader loads a set of so called page loaders beginning at PM address 0x0020 After the preloader terminates the D SP executes the page loaders which load the project data page by page T he loader uses a default preloader You can force the loader with the uload switch to use a customized preloader to reduce wait states or to implement a boot management scenario discussed in detail in the Appli cation N ote EE 146 Example T he following example lists the default preloader together with its opcode N ote that the Bwcount value is generated dynamically standar
2. LDR Loader output file KNL Loader output files containing kernel code only when two output files are selected Command Line Switc hes A summary of the loader command line switches appear in T able 2 9 Table 2 9 Blackfin Loader Command Line Switches Switch D escription b prom Specifies the boot mode T he b switch directs the loader to prepare a b flash boot loadable file for the specified boot mode Valid boot modes b spi include PROM Flash and SPI If b does not appear on the command line the default is b prom baudrate Accepts a baud rate for SPI booting only N ote Currently supported only for AD SP BF535 processors Valid baud rates and corresponding values are 500K 500 kH z the default M 1MHz e 2M 2MHz Boot kernel loading supports an SPI baud rate up to 2 MHz enc di filename Encrypts the data stream from the application DXEt files If the file name parameter does not appear on the command line the encryp tion algorithm from the default AD I s file is used kenc d11 filename Specifies the user encryption file for the data stream from the kernel file If the filename parameter does not appear on the command line the encryption algorithm from the default AD I s file is used f hex f ASCII f binary Specifies the boot file s format T he f switch prepares a boot load able file in the specified format Intel hex 32 ASCII bi
3. Last Block Indicates that the block is the last block to be booted into memory After the last block the processor jumps to the start of L1 memory for application code execution W hen it jumps to L1 memory for code execution the processor is still in Supervisor M ode and in the lowest priority interrupt IV G 15 Initialization Blocks The init filename option directs the loader to produce an initialization block from the code of the initialization section of the named file T he ini tialization block is placed at the top of aloader file It is executed before the rest of the code in the loader file is booted into the memory see Figure 2 11 Following execution of the initialization block the booting process con tinues with the rest of data blocks until it encounters a final block see Figure 2 12 The initialization code example follows in Listing 2 1 VisualD SP Loader M anual 2 21 for 16 Bit Processors Blackfin Processor Booting ADSP BF531 BF532 BF533 Processor PROM Flash or SPI Device App Code Data Figure 2 11 ADSP BF531 BF532 BF533 Initialization Block Execution ADSP BF531 BF532 BF533 Processor PROM Flash or SPI Device Figure 2 12 AD SP BF531 BF532 BF533 Booting Application Code 2 22 VisualD SP Loader M anual for 16 Bit Processors Blac kfin Processor Loader Splitter Listing 2 1 Initialization Block Code Example This file contains 3 sections 1
4. Figure 2 16 ROM Splitter Pane T he M ask Address field masks all EPROM address bits above or equal to the number specified For example M ask Address 29 default masks all the bits above and including 429 AN D ed by oxirrr rrrr T hus 2 52 VisualD SP Loader M anual for 16 Bit Processors Blac kfin Processor Loader Splitter 0x2000 0000 becomes 0x0000 0000 T he valid numbers are integers o through 32 but based on your specific input file the value can be within a subset of 0 32 No boot Mode T he hardware settings of BMopE 000 for AD SP BF535 processors or BMODE 00 for ADSP BF531 AD SP BF532 and AD SP BF533 proces sors select the no boot option In this mode of operation the on chip boot kernel is bypassed after reset and the processor starts fetching and executing instructions from address 0x2000 0000 in the Asynchronous M emory Bank 0 The processor assumes 16 bit memory with valid instructions at that location To create a proper LDR file that can be burned into either a parallel Flash or EPROM device you must modify the standard LDF file in order the reset vector isto be located accordingly T he following code fragments illustrate the required modifications in case of an AD SP BF533 processor Listing 2 3 Section Assignment LDF File MEMORY Off chip Instruction ROM in Async Bank 0 MEM PROGRAM ROM TYPE ROM START 0Ox20000000 END Ox2009FFFF WIDTH 8 Off chip cons
5. In this mode project data is stored in an 8 bit wide PROM After reset the D SP follows a special bootstrapping scenario T he D SP readsthe PROM scontents through the BDMA interface and initializes on chip and off chip memories The e1fsp121 loader utility generates a PRO M image that contains all project data and loader code Refer to EPROM Booting BD M A on page 5 6 for a detailed discus sion of this mode H ost Booting IDMA M ode In this mode the D SP does not start program execution immediately but Waits passively until a host D SP such as a microcontroller or another AD SP 218x part writes project data into the D SP s on chip memory through the ID M A interface The e1fsp121 loader processes the project data but the data may require post processing because each type of host processor requires its individual data format Refer to H ost Booting ID M A on page 5 11 for a detailed discussion of this mode N o Boot In this mode the D SP does not perform booting After a reset the D SP starts program execution directly from the off chip 24 bit PROM mem ory T he splitter capabilities of the e1fsp121 generate a proper PROM hex file T his option is not often used You must run elfsp121 exe from a command line VisualD SP 3 5 Loader M anual 5 3 for 16 Bit Processors ADSP 218x DSP Loader Guide Refer to N o Booting on page 5 13 for a detailed discussion of this mode Determining Boot Modes
6. Bit Field Description Zero Fill Block Indicates that the block is a buffer filled with zeros Zero Block is not included within loader file W hen the loader parses through the DxE file and encounters a large buffer with zeros it creates a zero fill block to reduce LDR file size and boot time If this bit is set there is no data in the block Ignore Block Indicates that the block is not to be booted into memory skips the block and move on to thenext one Currently is not implemented for application code Initialization Block Indicates that the block isto be executed before booting T heinitialization block indicator allows the on chip boot ROM to execute a number of instruc tions before booting the actual application code W hen the on chip boot ROM detects an Init Block it boots the block into internal memory and makes a CALL to it Initialization code must have a RTS at the end T his option allows the user to run initialization code such as SD RAM initial ization before the full boot sequence proceeds Figure 2 11 and Figure 2 12 illustrate the process Initialization code can be included within the LDR file by using the init switch see init filename on page 2 43 Processor Type Indicates the processor either AD SP BF531 BF532 or AD SP BF533 After booting is complete the cn chip boot ROM jumpsto oxFFAO 0000 fora AD SP BF533 processor and to oxFFAO 8000 for a ADSP BF531 BF532 pro cessor
7. File Extension D escription DXE Executable files and boot kernel files 0VL O verlay memory files T he loader recognizes overlay memory files but does not expect these files on the command line Place ovL filesin the same directory as the DXE file that refers to them the loader can locate them when processing the BNM file BNM Loader output file for EPROM s IDM Loader output file for ID M A Loader Switches T able 5 5 lists and describes the loader switches used in BD M A mode VisualD SP 3 5 Loader M anual 5 9 for 16 Bit Processors ADSP 218x DSP Loader Guide Table 5 5 AD SP 218x DSP BD MA Mode Command Line Switches Switch Description sourcefile Specifies the executable file DXE to be processed for a single proces sor boot loadable file outputfile Specifies the loader s output file BNM h O utputs the list of command line switches to standard output and exits 23 Produces Intel hex format b Produces M otorola S2 format byte Produces byte stream output format 218 x 1 218 4 5 6 8 9 Specifies the target processor e 2181 ADSP 2181 or AD SP 2183 D SP 218x one of the AD SP 2184 through AD SP 2189 DSP W hen used with 1oader keeps the image Use in place of 218x Specifies the AD SP 2184 AD SP 2185 AD SP 2186 AD SP 2187 AD SP 2188 or AD SP 2189 D SP asatarget processor Supports P
8. W SUN DSP 7 3 5 Analog D evices Inc One Technology Way Norwood M ass 02062 9106 Loader Manual for 16 Bit Processors Revision 1 0 O ctober 2003 Part N umber 82 000035 04 ANALOG DEVICES Copynght Information 2003 Analog Devices Inc ALL RIGHTS RESERVED This docu ment may not be reproduced in any form without prior express written consent from Analog D evices Inc Printed in the USA Disclaimer Analog D evices Inc reserves the right to change this product without prior notice Information furnished by Analog D evices is believed to be accurate and reliable H owever no responsibility is assumed by Analog D evices for its use nor for any infringement of patents or other rights of third parties which may result from its use N o license is granted by impli cation or otherwise under the patent rights of Analog D evices Inc Trademark and Service Mark Notice The Analog D eviceslogo VisualD SP the VisualD SP logo Blackfin the Blackfin logo CRO SSCORE the CRO SSCORE logo and EZ KIT Lite are registered trademarks of Analog D evices Inc VisualD SP and the VisualD SP logo are trademarks of Analog D evices Inc All other brand and product names are trademarks or service marks of their respective owners CONTENTS PREFACE Purposeor This Mangal UTE Xi IBID Ne ainsi dabei onde de Pia d Rd qd diris i pao ui ERR Xi UE IE EN Ir c RETE T TO xii Technical ar Customer SODDB
9. acy support only Creates a non bootable image and non boot stream image in the same output file together with the boot loadable image Boot mode must be set to PROM b PROM and format must be set to hex f hex romsplitter Creates a non bootable image only T his switch overwrites b and any other switch bounded by boot types An ASCII file is produced when f ASCII and romsplitter are spec ified regardless of the b 7e type setting split 4 The split 8 8 switch generates two output files for the 16 bit wide EMI data bus the LDU file contains the upper eight data bits and the LDL file contains the lower eight data bits The split 16 switch produces one 16 bit wide file Note Valid only when width is 16 bit O utputs status information as the loader processes files VisualD SP Loader M anual 3 23 for 16 Bit Processors ADSP 219x DSP Loader Guide Table 3 6 Loader Command Line Switches Cont d Switch Description waits Determines the number of wait states for external accesses Valid inputs are 0 to 7 inclusive D efault is 7 Note For EPROM and H ost boot modes only width Specifies the bus width in bits for EPROM Flash or H ost booting Valid numbers are 8 default and 16 Width must correspond to the EMICTL register s E BWS bit For multi DXE processing if the width changes from one pd group to the next anew LDR file
10. A Pre Init Section this section saves off all the DSP registers onto the stack 2 An Init Code Section this section is the initialization code which can be modified by the customer As an example an SDRAM initialization code is supplied The example setups the SDRAM controller as required by certain SDRAM types Different SDRAMs may require different initialization procedure or values 3 A Post Init Section this section restores all the register from the stack Customers should not modify the Pre Init and Post Init Sections The Init Code Section can be modified for a particular application d Finclude lt defBF532 h gt SECTION program f kk ek ke e KG A SPpre Init SOCEION KKK RK RK KAKA KK KK ek ek ee KK SP ASTAT Stack Pointer SP is set to the end of SP RETS scratchpad memory OxFFBOOFFC SP r7 0 by the on chip boot ROM eeSpl Gp5s0335 eaS PIS IOZDe sSPR Sollee SP 8OI2TD SR 135 Per SR l BORL SPS Bk SPS B2ebs SP 3 B34 SEE oMOsie SP SMIE ASPR M25 b eSP IS M33 ee SP EOS ESSE Lis le SP ay ike bass Pl E33 fe e e e A S Indt Code SACL TON KKK AKA KAKKK KKK KKK KK KK KK KKK Please insert Initialization code in this section ERKKKKKKKKKKKKKKKKKEKEKS DRAM Sei Up AEA AAA AAAKERARE KARKKEKKARKRA Ke Setup_SDRAM PO L EBIU_SDRRC amp OxFFFF SDRAM Refresh Rate Control Register VisualD SP Lo
11. An initialization block or a second stage loader must be used to initialize the SDRAM memory of the AD SP BF561 processor before any instruc tions or data are loaded into it Theinitialization block is identified by a bit in theflag word of the 10 byte block header When the boot ROM encounters an initialization block in the boot stream it loads the block and executes it immediately T he initialization block must save and restore registers and return to the boot ROM so the boot ROM can load the rest of the blocks For more details see Flags of Block H eader on page 2 20 Both the initialization block and second stage loader can be used to force the boot ROM to load a specific pxe from the external memory device if the boot ROM stores multiple executable files T he initialization block can manipulate the no or R3 register which the boot ROM uses as external memory pointers for Flash PROM or SPI memory boot respectively After the processor returns from the initialization block the boot ROM continues to load blocks from the location specified in the no or n3 regis ter which can be any DxeE in the boot stream T his option requires the starting locations of specific executables within external memory T he no or R3 register must point to the 10 byte count header as illustrated in AD SP BF531 BF532 BF533 and AD SP BF561 M ultiple D XE Boot ing on page 2 37 VisualD SP Loader M anual 2 35 for 16 Bit Processors Blackf
12. Extended linear address records specify bits 31 16 for the data records that follow T able A 2 shows an example of an extended linear address record T able A 3 shows the organization of an example data record T able A 4 shows an end of file record VisualD SP Loader M anual A 7 for 16 Bit Processors Build Files Table A 2 Extended Linear Address Record Example Field Purpose 020000040000FA Example record Start character 02 Byte count always 02 0000 Address always 0000 04 Record type 0000 O ffset address FA Checksum Table A 3 D ata Record Example Field Purpose 0402100000FE03FO0F9 Example record Start character 04 Byte count of this record 0210 Address 00 Record type 00 First data byte FO Last data byte F9 Checksum Table A 4 End of File Record Example Field Purpose 00000001FF End of file record Start character 00 Byte count zero for this record 0000 Address of first byte A 8 VisualD SP Loader M anual for 16 Bit Processors File Formats Table A 4 End of File Record Example Cont d Field Purpose 01 Record type FF Checksum Splitter Output Files in ASCII Format W hen the loader is invoked as a splitter its output can be an ASCII for mat file with the LDR extension ASC
13. amp wopt pins T hese pins can be read through bits in the System Reset Configuration Register syscr T he BMopE pins are dedicated mode control pins that is no other functions are shared with these pins 2 2 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter Refer to the processor s data sheet and H ardwareReference for more information on system configuration peripherals registers and Operating modes ADSP BF535 Processor Booting U pon reset an AD SP BF535 processor jumps to an external 16 bit mem ory for execution if BMopE 000 or to the on chip boot ROM if BMODE 001 010 011 Table 2 1 summarizes booting modes and code execution start addresses for AD SP BF535 processors Table 2 1 AD SP BF535 Processor Boot M ode Selections Boot Source BMODE 2 0 Execution Start Address Execute from 16 bit external memory Async Bank 0 000 0x2000 0000 no boot mode bypass on chip boot RO M Boot from 8 bit 16 bit Flash memory 001 0xF000 0000 Boot from 8 bit address SP10 serial EEPROM 010 0xF000 0000 Boot from 16 bit address SPIO serial EEPROM 011 0xF000 0000 Reserved 111 100 A 1 The processor jumps to this location after the booting is complete A description of each boot mode is as follows e ADSP BF535 Processor On Chip Boot ROM on page 2 4 e ADSP BF535 Processor Second Stage Loader on page 2 6 e ADSP BF535 Processo
14. 19 AD SP 219x Loader Command Line Reference 3 19 Pesene mariana dst Mae que op inbnb beni ipe 3 20 Fe 0 100011 sates PR EE PR SURPRIS 3 20 Wee EEEE e A E RO aras abd eria goi 3 21 vi VisualD SP 3 5 Loader M anual for 16 Bit Processors Contents AD SP 2192 12 DSP LOADER ADSP 2192 DSP ENG cinta tet ccerceatnxalaailathucaidannas danrin 4 2 AD SP 2192 DSP Reset Types sisctiieniderieeavsarssanianrdaanaisannaainss 4 2 ADP USP RTEL dtelxhnediciciakh eene dpt tka dbeusar tus 4 4 Bunding OAE FIG E 4 5 Creating a EAE FUE prekni R MD 4 6 Rote BL sionsnraiini n EN 4 7 ADSP 2192 DSP RBT L and Overlays iae iani deitas 4 8 Usipo Overlay SS sities niccinnapusees 4 9 ADSP 2197 DSP Loader Guide susscebiexvikel ak iseuT I TERH ia Uie ERUR RSS 4 10 Single Processsr Command LH sciieciiciiasainnaninss Ttva canada 4 10 Two Precesor Command LING iisccissarsssiensbicaniantehsidiasinaceninans 4 11 lleno Peg NE E 4 12 idR YT pi 5 PPM E 4 13 Loader Command Line Switches sissiserva eh vai aa iei e ttbi 4 13 AD SP 218X DSP LOADER SPLITTER BOS Perl es DSP Loader GUE se nsaniaccnaiiardeasivaniuiiwareenivanias 5 1 Boo MNONO eariad eae 5 2 Determining Baot MOES dss Er aa EM ETE Da dt 5 4 EPROM Booting SD M A iesasideoioxiaeiickb dbi tae hi9 lel ep dida 5 6 AD SP 218x BDM A Loader Command Line Reference 5 7 FI Sees rennandi patet p npe LSU C RR d LR EIS 5 9 HIBERUM E A A sadi M UM Cid i ARI d 5 9 VisualD SP 3 5 Loader
15. 1st data block in 1st DXE 200 207 M SB of the byte count of the 1st data block in 1st DXE 208 215 LSB of theflag word of the 1st block in 1st DXE 216 223 M SB of the flag word of the 1st block in 1st DXE 224 231 Byte 3 of the 1st block of 1st DXE 232 239 Byte 2 of the 1st block of 1st DXE 240 247 Byte 1 of the 1st block of 1st DXE 248 255 Byte 0 of the 1st block of 1st DXE 256 263 Byte 7 of the 1st block of 1st DXE And so on LSB of the address field of the nth data block of 1st DXE 8 15 of the address field of the nth data block of 1st DxE 16 23 of the address field of the nth data block of 1st DXE M SB of the address field of the nth data block of 1st DxE LSB of the byte count field of the nth block of 1st DXE 2 32 VisualD SP Loader M anual for 16 Bit Processors Blac kfin Processor Loader Splitter Table 2 7 AD SP BF561 Processor Boot Stream Structure Cont d Bit Field D escription 8 15 of the byte count field of the nth block of 1st DXE 16 23 of the byte count field of the nth block of 1st DXE M SB of the byte count field of the nth block of 1st DXE LSB of the flag word of the nth block of 1st DXE M SB of theflag word of the nth block of 1st DXE Byte 1 of the nth block of 1st DXE Byte 0 of the nth block of 1st DXE LSB of the address field of 2nd DXE count block no care 8 15 of the address field of 2nd DXE count block no care And
16. 3 23 4 14 INDEX VisualD SP Load page 5 2 5 6 Load page Boot kernd options 2 49 Load page ROM splitter options2 52 W wait states 2 46 2 48 5 6 waits loader switch 2 46 3 24 width loader switch 2 46 3 5 3 24 W indows drivers AD SP 2192 12 loader 4 7 Z zero fill blocks 2 21 VisualD SP Loader M anual for 16 Bit Processors l 11 INDEX 12 VisualD SP Loader M anual for 16 Bit Processors
17. B SRAM 0xFF90 4000 0xFF90 7FFF v Instruction SRAM OxFFAO 8000 FFA1 3FFF e ADSP BF533 processor v DataBank A SRAM oxFF80 0000 0xFF80 7FFF v DataBank B SRAM oxrr90 000 0xFF90 7FFF v Instruction SRAM 0xFFAO 0000 FFA1 3FFF SDRAM memory v Bank 0 0x0000 0000 0x07FF FFFF Booting to scratchpad memory oxrr amp o 0000 is not supported SDRAM must beinitialized by user code before any instructions or data are loaded into it VisualD SP Loader M anual 2 25 for 16 Bit Processors Blac kfin Processor Booting ADSP BF531 BF532 BF533 Processor SPI Memory Boot Se quence The AD SP BF531 BF532 BF533 processors support booting from 8 16 or 24 bit addressable SPI memories BMODE 11 T o determine the memory type connected to the processor 8 16 or 24 bit the processor sends signals to the SPI memory until it responds back The SPI memory does not respond back until it is properly addressed The on chip boot ROM does the following 1 2 3 Sends a READ command 0x03 then does a dummy READ Sends an address byte 0x00 then does a dummy READ Sends another byte 0x00 and verifies if the incoming byte is a zero If the byte is a zero an 8 bit addressable SPI memory device is connected If the incoming byte is not a zero the on chip boot ROM sends another byte 0x00 and verifies if the incoming byte is a zero If the byte is a zero a 16 bit addressable SPI memory device is connected If t
18. Bit Processors 3 ADSP 219X DSP LOADER SPLITTER This chapter explains how the loader splitter program e1floader exe is used to convert executable files 0x into boot loadable no bootable or combined output files for AD SP 219x D SPs AD SP 219x loader splitter refers to the loader splitter program designed for AD SP 2191 AD SP 2195 AD SP 2196 AD SP 21990 AD SP 21991 and AD SP 21992 D SPs The AD SP 2192 12 loader is described in Chapter 4 AD SP 2192 12 D SP Loader on page 4 1 Refer to Introduction on page 1 1 for the loader overview the introduc tory material appliesto all processor families Loader operations specific to the listed above processors are detailed in the following sections e ADSP 219x DSP Booting on page 3 2 Provides general information on boot sequences kernels and Streams ADSP 219x DSP Loader Guide on page 3 19 Provides reference information on the command line interface VisualD SP Loader M anual 3 1 for 16 Bit Processors ADSP 219x DSP Booting ADSP 219x DSP Booting T he AD SP 219x loader splitter creates a boot stream non boot stream or combinational output T he program accepts one executable file xt as input and generates one file LDR as output U pon powerup a AD SP 219x D SP can be booted from the EPROM UART SPI or H ost port Booting can also be initiated in software after RESET Refer to the Application N oteEE 131 and your D SP s data sheet
19. Loader To create an cxt file from VisualD SP 1 From the Load page of the Project O ptions dialog box specify the input Dxe files under Core 0 and Corel 2 From the Post Build page configure one or more command lines to execute the RT BL 3 Run the project T his generates the file and creates the Exe file The cxe file which is executed on the end user system traverses the data structures H created by the loader and subsequently compiled by the RT BL The content of these data structures are downloaded to the AD SP 2192 12 D SP through a user provided W indows driver A program running in virtual memory space as do all Windows applications cannot access the PCI mapped memory of the AD SP 2192 D SP directly A driver is mandatory Reference RTBL Creating the RT BL and driver can be a complex task especially the first time T o facilitate the process V isualD SP includes a reference RT BL in the form of a M icrosoft V isualC 6 0 project named reference rtb1 dsp This project is located in the 1ar subdirectory of your VisualD SP installation directory Refer to the files in the project for information on the operation of the RTBL and the provided driver interface TheRTBL downloads the code via the PCI busto the AD SP 2192 12 EZ KIT Lite evaluation system through the EZ KIT Lite s PCI driver T his reference can serve as an example for traversing and using the data structures emitted by the loader T
20. Loader Splitter T he two reasons for this restriction are e Core writes into L1 instruction memory are not allowed DMA from an 8 bit external memory is not possible since the minimum width of the External Bus Interface U nit EBIU is 16 bits Load bytes into L1 instruction memory by using the instruction test com mand and data registers as described in the M emory chapter of the appropriate H ardware Reference manual T hese registers transfer 8 byte sections of data from external memory to internal L1 instruction memory VisualD SP Loader M anual 2 15 for 16 Bit Processors Blackfin Proc essor Booting ADSP BF531 BF532 BF533 Processor Booting U pon reset an AD SP BF531 BF532 BF533 processor jumps to the on chip boot ROM if BMobdE 01 11 or jumps to 16 bit external mem ory for execution if BMoDE 00 located at oxEF00 0000 T able 2 2 shows booting modes and execution start addresses for AD SP BF531 AD SP BF532 and AD SP BF 533 processors Table 2 2 AD SP BF531 BF532 BF533 Processor Boot M ode Selections Execution Start Address Boot Source BM OD E 1 0 AD SP BF531 AD SP BF532 Processors AD SP BF533 Processor Execute from 16 bit External ASYN C BankO memory no boot mode or bypass on chip boot ROM 0x2000 0000 0x2000 0000 Boot from 8 or 16 bit Prom Flash OxFFAO 8000 OxFFAO 0000 Reserved 10 OxFFAO 8000 OxFFAO 0000 Boot from a 8 16 or 24 bit a
21. M anual vii for 16 Bit Processors Loader Switches iosssseidexipekid epa pes bea xke rel diede Hp etin 5 9 nox boonno UDMA sca dlexitechatibuMa Mekiea Qulio adan 5 11 AD SP 218x IDM A Loader Command Line Reference 5 13 B HODIN ED adsdaraiidaeliicnanibe ab Gnd AGERE A EDUC Nd pO NM MER Ed dE 5 13 AD SP 218x D3P Splitter GUJE Ls beside RE DEBA A M P Ue 5 15 Usmo See MPO n 5 15 AD SP 218x Splitter Command Line Reference 5 16 FILE FORMATS SENTO EE Loss me udi ae naar T N EA N A A 2 LIC M SOOS PIS cennar anaa aded oia oai A 2 AGB Sorea FIDA ausis dsord tation Ser pe bills eli uid a A 3 Assembly Initialization D ata Files a e A 3 Hoa FIG Prec PT m A 4 Linker DESC pan PIS aioaxdedddabode eH REMO FPE EE DERE ODIK A 4 Linka Command Line FUSS uasisuuincdecitee decimae qe aplitas iaa A 5 ENR il AMNEM UNI E tie E T IN ONT NUNT US A 5 A Sembla O Deet FES Re ner einna A 5 crai Tt T UT A 6 Liter Output FUES uaedan dad Qa e NAM E A 6 Memory M ap TEMOR crpe niet re ibn ae RORRUe SR bx eids A 7 Loader Output Files in Intel H ex 32 Format ssse A 7 Splitter Qutput Files in ASC I Format iusso rtr aas A 9 OCS TIE us euxabtasdixto to leue A sated EA burn est A 9 atit A I qiie cM T A 10 viii VisualD SP 3 5 Loader M anual for 16 Bit Processors Contents INDEX VisualD SP 3 5 Loader M anual ix for 16 Bit Processors VisualD SP 3 5 Loader M anual for 16 Bit Processors
22. PREFACE Thank you for purchasing Analog D evices development software for digital signal processor D SP applications Purpose of This Manual T he VisualD SP 3 5 Loader M anual for 16 Bit Processors contains infor mation on how to use the loader splitter to convert executable files into boot loadable or non bootable files for 16 bit fixed point AD SP 21xx D SPs and Blackfin processors T hese files are then programmed burned into an external memory device within your target system Intended Audience T he primary audience for this manual is D SP programmers who are familiar with Analog D evices D SPs T his manual assumes that the audi ence has a working knowledge of the appropriate D SP architecture and instruction set Programmers who are unfamiliar with Analog D evices D SPscan use this manual but should supplement it with other texts such as H ardware Reference and Instruction Set Reference manuals that describe your target architecture VisualD SP Loader M anual xi for 16 Bit Processors Manual Contents Manual Contents T he manual contains Chapter 1 Introduction Chapter 2 Blackfin Processor Loader Splitter Chapter 3 AD SP 219x D SP Loader Splitter Chapter 4 AD SP 2192 12 D SP Loader Chapter 4 AD SP 218x D SP Loader Splitter Appendix A File Formats Technical or Customer Support You can reach D SP T ools Support in the following ways Visit the D SP D evelopment T ools website
23. SP BF561 M ultiple D XE Booting 2 36 AD SP BF531 BF532 BF533 and AD SP BF561 M ultiple D XE Booting 2 37 Blackfin Processor Loader Guide 2oiniiben Erie p REFER BER FERAIS 2 40 Using Loader Command LIBE uos E DEM DIES HRIQ SEHE LDE EA 2 40 BEC 15 RR 2 41 Pile Geile OUD crete idt it Mb EMribeM AE 2 41 Command Line SEEDS uos decode sia ie Crude ibis Ho Egal 2 42 Uang Bare LOI NTC NT TU RUP TRIER US 2 47 VisualD SP 3 5 Loader M anual V for 16 Bit Processors Using Second Stage Loader isoneudaeisekrresikeskck dante erar 2 49 Ung RON SES Golese dientes oer Rex dE bab fon ber Ne Dor testi ws 2 51 oes o e ER 2 53 AD SP 219X DSP LOADER SPLITTER AD SP 219x DSP DOOR osisaeiigobublukbnR p ER DEEP Ra te bbiU qus Se Na DEUS 3 2 ADZPAISEDSE Boot M OUES 2 uus ala rio ad EK GA M aera az RE 3 3 ADSPGUISEDSP Boot KETE aie aixied dub aic Qd Didi kni 3 4 Pr ae DSP Boot SU BONS sorrisa mnia 3 4 Parallel EPROM Boot Streams 1s ieri iiis nda iaa 3 4 BIB HORE iia iie ibee adi c Rb Hebe ERICH LIRE lE Em 3 5 bf eielo a emer 3 6 AD SP 219x DSP M ultiple D XE Support 1 2 ane 3 7 BUS BOND aussen psp naa Mas ad di MR DOMO amma 3 10 UART BOOMO Goneditebedadededtebidei Med GhbHb o NM Mead 3 11 GNIS EPROM ND uisnsaitehiciuidovapikapinz Uu alidt Minds 3 12 lea C ENERO IO dain QEOR IR DEEST TRO MONT 3 12 Enriching Boot EPROM s with No boot Data 3 16 ADSP 219x DSP Logger G HEB uus reap asiick tico unb AM dE pK id 3
24. Several dialects of C code are supported pure portable AN SI C and at least two subtypes of ANSI C with ADI extensions T hese extensions include memory type designations for certain data objects and segment directives used by the linker to structure and place executable files The C C 4 compiler run time library as well as a definition of ADI extensions to AN SI C are detailed in your target processor s VisualD SP 3 5 C C Compiler and Library M anual 1 With and without built in function support a minimal differentiator T here are others A 2 VisualD SP Loader M anual for 16 Bit Processors File Formats Assembly Source Files Assembly source files asm are text files containing assembly instructions assembler directives and optionally preprocessor commands For infor mation on assembly instructions see your processor s Programming Reference T he processor s instruction set is supplemented with assembly directives Preprocessor commands control macro processing and conditional assem bly or compilation For information on the assembler and preprocessor see the VisualD SP 3 5 Assembler and Preprocessor M anual Assembly Initialization Data Files Assembly initialization data files DAT are text files that contain fixed or floating point data T hese files provide initialization data for an assembler VAR directive or serve in other tool operations W hen a var directive uses a DAT file fo
25. T he default second stage loader uses the last 1024 bytes of L2 memory T he area must be reserved during booting but can be reallocated at runtime 2 36 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter ADSP BF531 BF532 BF533 and ADSP BF561 Multiple DXE Booting T his section describes how to boot more than one oxt file into a AD SP BF531 BF532 BF533 and AD SP BF561 processor T he informa tion presented in this section applies to all of the named processors For additional information on the AD SP BF561 processor refer to AD SP BF561 M ultiple D XE Booting on page 2 36 The ADSP BF531 BF532 BF533 and AD SP BF561 loader file structure and the silicon revision of 0 1 and higher allow to boot multiple oxe files into a single processor from external memory Each executable file is pre ceded by a 4 byte count header which is the number of bytes within the executable including headers T his information can be used to boot a spe cific DxE into the processor T he 4 byte oxe count block is encapsulated within a 10 byte header to be compatible with the silicon revision 0 0 For more information see Blocks and Block H eaders on page 2 19 Booting multiple executables can be accomplished by one of thefollowing methods 1 U se the second stage loader switch userkernel T his option allows to use your own second stage loader or kernel After the second stage loader gets boote
26. T o determine the boot mode an AD SP 218x D SP samples its mode pins input flag pins after reset T able 5 1 and T able 5 2 explain how to con figure various D SPs by pulling the proper pins up or down Table 5 1 Boot M odes AD SP 2181 and AD SP 2183 D SPs MMAP Pin BMODE Pin D escription 0 0 BD MA is used in default mode to load the first 32 program memory words from byte memory space Program execution is held off until all 32 words have been loaded IDMA is used to load any internal memory as desired Program execution is held off until internal program memory location 0 is written to Bootstrap is disabled Program execution immediately starts from location 0 Table 5 2 Boot M odes AD SP 2184 to AD SP 2189 D SPs ModeD ModeC ModeB ModeA Description X 0 0 0 BDMA is used to load the first 32 program memory words from byte memory space Program execution is held off until all 32 words have been loaded T he chip is configured in Full Memory Mode X 0 1 0 No automatic boot operations occur Program execu tion starts at external memory location 0 Thechip is configured in Full M emory M ode BDMA can still be used but the processor does not automatically use or wait for these operations 5 4 VisualD SP 3 5 Loader M anual for 16 Bit Processors ADSP 218x DSP Loader Splitter Table 5 2 Boot M odes AD SP 2184 to AD SP 2189 D SPs Cont
27. WIDTH 16 The sTARTO ENDO and LENGTHC commands expect logical addresses Since the example segment stores 24 bit wide instructions the rYPECPM command defines the logical width of the segment to be 24 bits The example assumes no boot mode 000 and runs from external memory starting at address 0x010000 T hisis why the WIDTH 16 command sets the physical width to 16 bits Dueto AD SP 219x EMI packing rules the first instruction is stored in the physical 16 bit EPROM location 0x020000 The 16 bit EPROM address locations between 0x010000 and 0x01FFFF can be used by an additional read only data segment as shown below MEMORY seg ext code TYPECPM ROM START 0x010000 END OxOI7FFF WIDTH 16 j seg ext data TYPECDM ROM START 0x010000 END OxOIFFFF WIDTH 16 j VisualD SP Loader M anual 3 13 for 16 Bit Processors ADSP 219x DSP Booting T he data segment seg ext data is defined by the TyPE DM command which sets the logical width to 16 bits SincethewrprH 16 command also sets the physical width to 16 bit no data packing and no address multiply is required Logical addresses are equal to physical EPROM addresses in this special case The 16 bit EPROM image generated by the loader is described in T able 3 2 Table 3 2 EPROM Image D escription Address range Purpose 0x000000 0x00FFFF N ot used 0x010000 0x01FFFF seg ext data 0x020000 0x02FFFF seg ext code The D SP
28. also generate ASCII files DM Example ext data TYPE DM ROM START 0x010000 END 0x010003 WIDTH 8 The above DM segment results in the following code 00010000 32 bit logical address field 00000004 32 bit logical length field 00020201 32 bit control word 2x address multiply 02 bytes logical width 01 byte physical width 00000000 reserved 1234 1st data word DM data is 16 bits 5678 9ABC DEFO Ath last data word CRC16 optional controlled by the checksum switch PM Example ext code TYPE PM ROM START 0x040000 END 0x040007 WIDTH 16 The above PM segment results in the following code 00040000 32 bit logical address field 00000008 32 bit logical length field 00020302 32 bit control word 2x address multiply 03 bytes logical width 02 bytes physical width 00000000 reserved 123456 lst data word PM data is 16 bits VisualD SP Loader M anual 3 15 for 16 Bit Processors ADSP 219x DSP Booting 789ABC DEF012 345678 9ABCDE F01234 56789A BCDEFO 8th last data word optional controlled by the checksum switch Enriching Boot EPROMs with No boot Data T he loader s splitter functionality refer to N o booting on page 3 12 enables powerful memory utilization in combination with the parallel EPROM boot mode T hesame EPROM used for booting can also be used at runtime for read only data and overlay storage Furthermore the D SP can execute non speed c
29. any debugging tools connected After power up proces sor memories need to be initialized to be booted T herefore the linker output must be transformed to a format readable by the processor T his process is handled by the loader splitter utility T he loader splitter uses the debugged and tested executable as well as shared memory and overlay files as inputsto yield a processor loadable file 1 2 VisualD SP 3 5 Loader M anual for 16 Bit Processors Introduction VisualD SP includes two loader splitter programs e elfloader exe for AD SP BF5xx and AD SP 219x processors e elfspl21 exe for AD SP 218x processors You can run the loader splitter from the ID D E In order to do so change you project s type from D SP Executable to D SP Loader File f preferred the command line interface is also available Loader operations depend on loader options which control how the loader processes executable files letting you select features such as kernels boot modes and output file formats T hese options are set on the Load page of the Project O ptions dialog box in the VisualD SP environment or on theloader s command line O ption settings on the Load page corre spond to switches typed on the command line T he loader splitter output is either a boot loadable or non bootable file described in thefollowing Boot loadable Files V ersus N on bootable Files The output is meant to be loaded onto the target T here are sev eral ways to
30. at www analog com technology dsp developmentTools index html Email questions to dsptools supportGanalog com Phone questions to 1 800 AN ALO GD Contact your ADI local sales office or authorized distributor Send questions by mail to Analog Devices Inc One Technology Way P O Box 9106 Norwood MA 02062 9106 USA xii VisualD SP Loader M anual for 16 Bit Processors Preface Supported Processors T he name AD SP 21xx refers to two families of Analog D evices 16 bit fixed point processors V isualD SP H for AD SP 21xx D SPs currently supports the following processors e ADSP 218x family D SPs AD SP 2181 AD SP 2183 AD SP 2184 84L 84N AD SP 2185 85L 85M 85N AD SP 2186 86L 86M 86N ADSP 2187L 87N AD SP 2188L 88N and AD SP 2189M 89N e ADSP 219x family D SPs ADSP 2191 AD SP 2192 12 AD SP 2195 AD SP 2196 AD SP 21990 AD SP 21991 and AD SP 21992 T he name Blackfin refersto a family of Analog D evices 16 bit embed ded processors V isualD SP currently supports the following Blackfin processors Blackfin Processors AD SP BF531 AD SP BF532 formerly AD SP 21532 AD SP BF533 AD SP BF535 formerly AD SP 21535 AD SP BF561 and AD 6532 Product Information You can obtain product information from the Analog D evices W eb site from the product CD RO M or from the printed publications manuals Analog D evices is online at www analog com O ur W eb site provides infor mation about a
31. beginning of L2 memory 0xF000 0000 A second stage loader must be used in applications in which multiple seg ments reside in L2 memory or in L1 memory and or SDRAM In addition a second stage loader must be used to change the wait states or hold time cycles for a Flash PROM booting or to change the baud rate for a SPI boot see Command Line Switches on page 2 42 for more infor mation on these features W hen a second stage loader is used for booting the following sequence takes place 1 Upon reset the on chip boot ROM downloads n bytes the second stage loader from external memory to address oxF000 0000 in L2 memory Figure 2 4 ADSP BF535 Processor L J PROM Flash or SPI Device Figure 2 4 AD SP BF535 Processors Booting W ith Second Stage Loader 2 6 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter 2 The second stage loader copies itself to the bottom of L2 memory ADSP BF535 Processor PROM Flash or SPI Device 0x0 Figure 2 5 AD SP BF535 Processors C opying Second Stage Loader 3 The second stage loader boots in the application code data into the various memories of the Blackfin processor ADSP BF535 Processor PROMFlash or SPI Device D Application Code Data Figure 2 6 AD SP BF535 Processors Booting Application Code VisualD SP Loader M anual 2 7 for 16 Bit Processors Blackfin Proc essor Booting 4 Finally after booting th
32. block header an a block body if it isa non zero block A block does not have a block body if it isa zero block A block header is illustrated below Output LDR File 4 Bytes r 4 Bytes N Bytes 4Bytes Block Block Header 4 Bytes 2 Bytes 4 Bytes 4 Bytes N1 Bytes Global H eaders A global header for 8 and 16 bit PRO M Flash booting LEE EFC es EC RR ECT EE EIER DOR L1 LC Number of hold time cycles 3 default 4 Number of wait states 15 default 1 16 bit PROM Flash 0 8 bit PROM Flash 0 default A global header for 8 and 16 bit addressable SPI booting a Fs i EGGS 9 UR a ER S TT Ld Baud rate 0 500 kHz default 1 1 MHz 2 2 MHz 2 12 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter Block H eaders A block header has three words 4 byte clock start address 4 byte block byte count and 2 byte flag word Flags The AD SP BF535 block flag word s bits are illustrated below te es es Bit 15 1 Last Block 0 Not Last Block Bit 0 1 Zero Fill 0 No Zero Fill ADSP BF535 Processor Memory Ranges Second stage loaders are available for AD SP BF535 processors in V isu alD SP 3 0 and higher T hey allow booting to e L2 memory 0xF000 0000 e L1 memory v DataBank A SRAM oxrra0 0000 v DataBank B SRAM oxFF90 0000 v Instruction SRAM oxrrAo 0000 v Scratchpad SRAM oxFFBO 0000 SDRAM v Bank 0 0x
33. broad range of products analog integrated circuits amplifiers converters and digital signal processors VisualD SP Loader M anual xiii for 16 Bit Processors Product Information MyAnalog com M yAnalog com is a free feature of the Analog D evices website that allows customization of a webpage to display only the latest information on products you are interested in You can also chooseto receive weekly email notification containing updates to the webpages that meet your interests M yAnalog com provides access to books application notes data sheets code examples and more Registration Visit www myanalog com to sign up Click Register to use M yAnalog com Registration takes about five minutes and serves as means for you to select the information you want to receive If you are already a registered user just log on Your user name is your email address Embedded Processor and DSP Product Information For information on digital signal processors visit our website at www analog com processors which provides access to technical publica tions datasheets application notes product overviews and product announcements You may also obtain additional information about Analog D evices and its products in any of the following ways Email questions or requests for information to dsp support analog com e Fax questions or requests for information to 1 781 461 3010 N orth America 49 0 089 76 903 557 Europe e
34. file SM Shared memory files T he loader recognizes shared memory files but does not expect these files on the command line Place sm filesin the same directory as the DXE filethat refers to them the loader can locate them when processing the DXE file Loader output files C language header files Loader Command Line Switc hes T able 4 4 lists and describes the loader switches Table 4 4 AD SP 2192 D SP Loader Command Line Switches Switch D escription f format Specifies the boot file format Prepares an output file in the specified format Currently the loader utility supports the C style header file H only This is the default h Invokes the command line help outputs a list of command line or switchesto standard output and exits By default the n switch alone help provides help for the loader driver To obtain a help screen for the ADSP 2192 processor type loader proc ADSP 2192 h M Generates make dependencies only MM Shows dependencies while processing the files VisualD SP Loader M anual 4 13 for 16 Bit Processors ADSP 2192 DSP Loader Guide Table 4 4 AD SP 2192 D SP Loader Command Line Switches Cont d Switch Description Mo filename Writes make dependencies to the named file The Mo option is for use with either the or MM option If Mo is not present the default is a stdout display Mt targetname S
35. for user application code Valid values are 80r16for PROM or Flash boot kernel e 8 for SPI boot kernel If this switch is absent from the command line the default file width is e the width parameter when booting from PRO M Flash 8 when booting from SPI T his switch should be used in conjunction with the o2 switch userkernel Specifies the user s boot kernel T he loader utilizes the user specified kernel and ignores the default boot kernel if there is one Note Currently only AD SP BF535 processors have default kernels M Generates make dependencies only no output file will be generated maskaddr M asks all EPROM address bits above or equal to For example maskaddr 29 default masks all the bits above and including A29 AN Ded by Oox1FFF FFFF For example 0x2000 0000 becomes 0x0000 0000 The valid fs are integers 0 through 32 but based on your specific input file the value can be within a subset of 0 32 T his switch requires romsplitter and affectstheROM section address only MaxBlockSize Specifies the maximum block byte count which must bea multiply of 16 MM Generates make dependencies while producing the output files Mo filename Writes make dependencies to the named file The Mo option is for use with either the M or MM option If Mo is not present the default isa lt stdout gt display 2 44 VisualD SP Loader M anual for
36. ghc loader switch 2 43 global headers 2 11 2 12 2 30 3 4 INDEX H headers 2 37 block headers 2 13 hap loader switch 2 43 3 21 4 13 5 10 hex format files LDR A 7 H oldT ime loader switch 2 43 host booting AD SP 218x D SPs 5 5 5 11 host booting mode overview 1 6 host processors 1 4 5 3 5 11 host3bytes loader switch 3 21 I i hex splitter switch 5 18 IDMA 5 11 control register 5 11 creating boot file 5 13 interface 5 3 5 4 5 5 5 11 overlay register 5 11 idma loader switch 5 13 ignore blocks 2 21 init filename loader switch 2 38 2 43 initialization block code example 2 23 blocks 2 21 2 35 2 38 code 2 21 2 43 2 49 sections 2 21 input files 2 41 5 8 5 10 5 16 input flag pins 5 4 Intel hex format 5 10 5 19 interrupt vectors 2 28 VisualD SP Loader M anual for 16 Bit Processors INDEX K k kernel width loader switch 2 44 kb boot mode loader switch 2 43 kenc dll filename loader switch 2 42 kernel file option 2 49 kernels 1 6 see also boot kernel kf kernel format loader switch 2 43 kp kernel hex address loader switch 2 44 L userkernel loader switch 2 37 2 44 L1 memory 2 6 2 13 2 14 2 17 2 25 2 29 2 34 L2 memory 2 4 2 5 2 6 2 13 2 14 last blocks 2 21 library files A 6 linker command line files T XT A 5 description file LD F see LDF files executable files A 6 memory map files M AP A 7 settings 1 2 linking 1 2 little endian 3 10 lo
37. header files 4 6 JDM loader output files 5 9 5 12 KNL kernel only loader output files 2 42 LDF Linker D escription Format files A 4 LDR files 2 8 2 42 5 1 ASCII format A 9 hex format A 7 splitter output A 9 M AP memory map files A 7 OVL overlay memory files 5 9 A 6 SM shared memory files 4 10 4 11 A 6 TXT ASCII text files A 5 N umerics 16 bit addressable SPI memory 2 27 2184 5 6 8 9 loader switch 5 10 5 13 218x 1 loader switch 5 10 5 13 24 bit addressable SPI memory 2 27 8 bit addressable SPI memory 2 27 A AD SP 218x D SPs EPROM BDM A booting 5 6 host ID M A booting 5 11 start addresses 5 10 using loader 5 1 using splitter 5 15 AD SP 218x loader switches 2184 5 6 8 9 5 10 5 13 218x 1 5 10 5 13 bdma inputfile start address 5 10 bdmaload start address 5 10 byte 5 10 help 5 10 i Intel hex format 5 10 idma 5 13 loader 5 10 noloader 5 10 VisualD SP Loader M anual for 16 Bit Processors INDEX offsetaddr 5 11 offsetpage 5 11 S S2 format 5 10 uload file 5 11 AD SP 218x loader splitter 1 4 AD SP 218x processors loader 5 1 AD SP 218x splitter 5 15 command line switches 5 18 extracting segments from dm memory 5 18 extracting segments from pm memory 5 18 AD SP 218x splitter switches byte 5 18 dm 5 18 i hex format 5 18 pm 5 18 readall 5 18 S sl format 5 19 ui 5 19 us 5 19 us2 5 19 AD SP 2191 loader switches help 3 21 AD SP 2191 processors load
38. include the drive and directory For multiprocessor or multiin put systems specify multiple input oxes Put the input filenames in the order in which you want the loader to process the files Enclose long file names within straight quotes 1ong file name proc processor Part number of the processor for example ADSP BF531 for which the loadable file is to be built Provide a processor part number for every input DxE if designing multipro cessor systems If the processor is not specified the default is ADSP BF535 switch O neor more optional switches to process Switches select operations and modes for the loader Command line switches may be placed on the command line in any order except the order of input files for a multiinput system For amultiinput system the loader processes the input files in the order presented on the command line File Searches File searches are important in the loader processing T he loader supports relative and absolute directory names default directories File searches occur as described on page 1 9 File Extensions Some loader switches take a file name as an optional parameter T able 2 8 lists the expected file types names and extensions VisualD SP Loader M anual 2 41 for 16 Bit Processors Blackfin Processor Loader Guide Table 2 8 File Extensions Extension File Description DXE Loader input files boot kernel files and initialization files
39. must be created by specifying o in the pd group where width has changed See o filename and pd address inputfile for details 3 24 VisualD SP Loader M anual for 16 Bit Processors 4 ADSP 2192 12 DSP LOADER T his chapter explains how the loader program e1floader exe is used to convert executable files 0xe into boot loadable files H for AD SP 2192 12 DSPs You cannot produce a non bootable PROM image file that is splitting is not supported for an AD SP 2192 12 D SP Refer to Introduction on page 1 1 for the loader overview the introduc tory material appliesto all processor families Loader operations specific to AD SP 2192 12 D SPs AD SP 2192 for short are detailed in the follow ing sections ADSP 2192 DSP Booting on page 4 2 Provides general information on the loader commands and operations e ADSP 2192 DSP Loader Guide on page 4 10 Provides reference information on the loader s command line syn tax and switches VisualD SP Loader M anual 4 1 for 16 Bit Processors ADSP 2192 DSP Booting ADSP 2192 DSP Booting An AD SP 2192 12 DSP can be boot loaded through its PCI or USB interface For PCI loading the loadable executable x must reside in the PC host s memory space before it is loaded into the D SP The AD SP 2192 12 loader repackages pxe files and associated ovi and SM files produced by the linker into an u file for use with a run time loader RTBL T
40. on how to improve our manuals and online H elp You can contact us at dsp techpubs analog com xviii VisualD SP Loader M anual for 16 Bit Processors Preface Notation Conventions T he following table identifies and describes text conventions used in this manual Additional conventions which apply only to specific chapters may appear throughout this document Example Description Close command Text in bold style indicates the location of an item within the File menu VisualD SP environment s menu system For example the Close command appears on the File menu this that Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars read the example as this or that this that O ptional items in syntax descriptions appear within brackets and sepa rated by vertical bars read the example as an optional this or that this O ptional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipsis read the example as an optional comma separated list of this SECTION Commands directives keywords and feature names are in text with letter gothic font filename N on keyword placeholders appear in text with italic style format D A note providing information of special interest or identifying a related topic In the online version of this book the word N ote appears instead of
41. page 2 16 D ifferences occur because the AD SP BF561 processor has two cores core A and core B After reset core B remains idle but coreA executes the on chip boot ROM located at address oxEroo 0000 Please refer to Chapter 3 of the AD SP BF561 H ardware Reference M anual for information about the processor s operating modes and states Please refer to System Reset and Power up Configuration for background information on reset and booting The boot ROM loads an application program from an external memory device and starts executing that program by jumping to the start of core A sL1 instruction SRAM at address oxFFAO 0000 T able 2 5 summarizes the boot modes and execution start addresses for AD SP BF561 processors Table 2 5 AD SP BF561 Processor Boot M ode Selections Boot Source BMODE 2 0 Execution Start Address Reserved 000 N ot applicable Boot from 8 bit 16 bit PRO M Flash memory 001 OxFFAO 0000 Boot from 8 bit addressable SPIO serial EEPROM 010 OxFFAO 0000 Boot from 16 bit addressable SPIO serial EEPROM 011 OxFFAO 0000 Reserved 111 100 N ot applicable Just likethe AD SP BF531 BF532 BF533 processor the AD SP BF561 boot ROM usestheinterrupt vectors to stay in supervisor mode T he boot ROM code transitions from the reset interrupt service routine into the lowest priority user interrupt service routine Int 15 and remains in the 2 28 VisualD SP Loader M anual for 16 Bit Proce
42. process has completed D epending on hardware capa bilities there are two different methods of host booting In the first case the host system has full control over all target memories It halts the target while it is initializing all memories as required In the second case the host communicates by a certain handshake with the loader kernel running on the target processor T his kernel may execute from on chip ROM or may be pre loaded by the host devices into thetarget s SRAM by any boot strapping scheme T he loader splitter utility generates a file that can be consumed by the host device It depends on the intelligence of the host device and on the target architecture whether the host expects raw application data or a for matted boot stream 1 6 VisualD SP 3 5 Loader M anual for 16 Bit Processors Introduction In this context a boot loadable file is a file that stores instruction code in a formatted manner in order to be processed by a boot kernel A non bootable file stores raw instruction code N otethat in some case a single file may contain both types of data Boot Kemels A loader boot kernel refers to the resident program in the boot ROM Space responsible for booting the processor Alternatively or in absence of the boot ROM the boot kernel can be preloaded from the boot source by a boot strapping scheme W hen a reset signal is sent to the processor the processor starts booting from a PROM host device or th
43. processors Refer to Introduction on page 1 1 for the loader overview the introduc tory material applies to all processor families Loader operations specific to AD SP BF 5xx Blackfin processors are detailed in the following sections e Blackfin Processor Booting on page 2 2 Provides general information on various booting modes including information on second stage kernels e AD SP BF535 Processor Booting on page 2 3 e AD SP BF531 BF532 BF533 Processor Booting on page 2 16 e AD SP BF561 Processor Booting on page 2 28 e Blackfin Processor Loader Guide on page 2 40 Provides reference information on the loader s command line syn tax and switches VisualD SP Loader M anual 2 1 for 16 Bit Processors Blackfin Proc essor Booting Blackfin Processor Booting Figure 2 1 is a simplified view of the Blackfin processor s booting sequence ASM C CPP External Memory ADSP BF53x Processor Figure 2 1 Blackfin Processors Booting Sequence A Blackfin processor can be booted from an 8 or 16 bit Flash PROM memory or an 8 16 or 24 bit addressable SPI memory 24 bit address able SPI memory booting supported only on AD SP BF531 BF532 BF533 processors T here is also a no boot option bypass mode in which execu tion occurs from a 16 bit external memory At powerup after the reset the processor transitions into a boot mode sequence configured by the
44. so on VisualD SP Loader M anual 2 33 for 16 Bit Processors Blac kfin Processor Booting ADSP BF561 Processor Memory Ranges The on chip boot ROM of the AD SP BF561 processor can load a full application to the various memories of both cores Booting is allowed to the following memory ranges The boot ROM clears these memory ranges before booting in anew application CoreA v Li Instruction SRAM 0xFFA0 0000 0xFFAO 3FFF v L1 Instruction Cache SRAM 0xFFA1 0000 0xFFA1 3FFF v L1DataBank A SRAM 0xFF80 0000 0xFF80 3FFF v L1DataBank A Cache SRAM oxFF80 4000 0xFF80 7FFF v L1DataBank B SRAM oxrr90 0000 0xrr90 3FFF v L1DataBankB Cache SRAM oxrr90 4000 0xFF90 7FFF v Li Instruction SRAM oxFF60 0000 0xFF6 O3FFF v L1 Instruction Cache SRAM oxrrei 0000 0xrr61 3FFF v L1DataBank A SRAM 0xFF40 0000 0xFF40 3FFF v L1DataBank A Cache SRAM oxrr40 4000 0xFF40 7FFF v L1DataBank B SRAM oxrrso 0000 0xrr50 3FFF v L1DataBankB Cache SRAM oxrrso 4000 0xFF50 7FFF Four Banks of Configurable Synchronous DRAM 0x0000 0000 up to oxirrr FFFF 2 34 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter The boot ROM does not support booting to core A scratch mem ory oxFFB0 0000 0xFFBO OFFF and to core B scratch memory OxFF70 0000 0xFF70 OFFF Datathat needs to be initialized prior to runtime should not be placed in scratch memory ADSP BF561 Processor Initialization Bloc ks
45. usethe output e Download the loadable file into the processor s PROM spaceon an EZ KIT Lite board viathe Flash Programmer plug in Refer to VisualD SP H elp or the EZ KIT Lite Evaluation System M anual for information on the Flash Programmer UseVisualD SP to simulate booting in a simulator session where supported Load the loader file and then reset the processor to debug the booting routines N o hardware is required just point to VisualD SP 3 5 Loader M anual 1 3 for 16 Bit Processors Program Development How the location of the loader file letting the simulator to do the rest You can step through the boot kernel code as it brings the rest of the code into memory Storethe loader file in an array on a multiprocessor system A mas ter host processor has the array in its memory allowing a full control to reset and load the file into the memory of a slave processor Boot loadable Files Versus Non bootable Files A boot loadablefile is transported into and run from a processor s internal memory on chip boot ROM N ote T his is different for AD SP 218x processors T hefileisthen programmed burned into an external mem ory device within your target system T he loader outputs files in industry standard file formats such as Intel hex 32 and M otorola S which are readable by most EPROM burners For advanced usage other file formats are supported A non bootable EPRO M image file executes from the processo
46. 0000 0000 v Bank 1 0x0800 0000 VisualD SP Loader M anual 2 13 for 16 Bit Processors Blackfin Proc essor Booting v Bank 2 0x1000 0000 v Bank 3 0x1800 0000 SDRAM must be initialized by user code before any instructions or data are loaded into it For more information see U sing Second Stage Loader on page 2 49 Second Stage Loader Restrictions W hen using the second stage loader e Thebottom of L2 memory must be reserved during booting T hese locations can be reallocated during runtime T he following loca tions pertain to the current second stage loaders v For 8 and 16 bit PROM Flash booting reserve 0xF003 FEO0 0xF003 FFFF last 512 bytes v For 8 and 16 bit addressable SPI booting reserve 0xF003 FDOO OxF003 FFFF last 768 bytes If segments residein SDRAM memory configure the SDRAM reg isters accordingly in the second stage loader kernels before booting v Modify section of code called SDRAM setup in the second stage loader and rebuild the second stage loader Any segments residing in L1 instruction memory OxFFAO 0000 0xFFAO 3FFF must be 8 byte aligned v Declare segments within the Lor file that residein L1 instruction memory at starting locations that are 8 byte aligned for example 0xFFAO 0000 OxFFAO 0008 OxFFAO 0010 and so on v Orusethe ALIGN 8 directivesin the application code 2 14 VisualD SP Loader M anual for 16 Bit Processors Blac kfin Processor
47. 16 Bit Processors Blac kfin Processor Loader Splitter Table 2 9 Blackfin Loader Command Line Switches Cont d Switch Description Mt filename Specifies the make dependencies target output filename The Mt option is for use with either the M or MM option If Mt is not present the default is the name of the input file with the LDR extension no2kernel Produces the output file without the boot kernel but uses the boot strap code from the internal boot ROM The boot stream gener ated by the loader is different from the one generated by the boot ker nel Note Currently supported only for AD SP BF535 processors o filename Directs the loader to use the specified f77ename as the name for the loader s output file If the fi 7ename is absent the default name is the name of the input file with an LDR extension 02 p 4 Produces two output files one for the Init block if present and boot kernel and another for the user application code To havea different format from the application code output file use the kb kf kwidth switches to specify the boot mode the boot format and the boot width for the output kernel file If you intent to use the 02 switch do not combine it with e nokernel on AD SP BF535 processors filename and or init filename on AD SP BF531 BF532 BF535 BF561 processors Specifies a hex PRO M Flash output start address for the application code A valid va
48. 16 Bit Processors ADSP 219x DSP Booting controlled by the mode pins T he width information configures the EM interface and remains valid during the entire boot process If you want to boot off chip memories be awarethat the width of the memory you want to boot must be identical to the width of the interface from which you are booting Data Blocks T he header is followed by the data block also called payload data T he 16 bit block is sent in a 16 bit field and the 24 bit block is sent in a 32 bit field 24 bit data block is represented differently in the boot stream from 24 bit addresses 32 bit data block istransmitted the following way a byte of zeros inserted by the loader bits 0 7 followed by bits 8 15 and finally bits 16 24 W hen booting from an 8 or 16 bit EPROM direct D SP core accesses and M emory DM A under the control of an EPROM boot routine located in the ROM space are used to load a boot stream formatted program located in the boot space Appropriate packing modes are selected based on the requirements of the boot stream Each page of boot space is 64K words long and 16 bits can address the EPROM per page T he upper 8 address bits specify the boot page U pon hardware reset booting is from address 0x0000 of logical page 0x80 which mirrors physical address 0x000000 because the upper address lines are not available off chip T he External Port Interface EPI uses its default configuration divide b
49. 5 1 for 16 Bit Processors ADSP 218x DSP Loader Guide Loader operations depend on loader options which control how the loader processes executable files letting you select features such as loader kernel boot type and output file format T hese options appear on the loader s command line or the Load page of the Project O ptions dialog box in the VisualD SP environment O ption setting on the Load page correspond to switches displayed on the command line T o generate a boot loadable file you can specify the loader options from within the VisualD SP environment V isualD SP invokes the elfsp121 and builds the output file To generate a non bootable PROM file you must run the e1fsp121 utility from a command line T o ensure correct operation of the loader familiarize yourself with Boot M odes on page 5 2 e Determining Boot M odes on page 5 4 EPROM Booting BD M A on page 5 6 Host Booting IDM A on page 5 11 No Booting on page 5 13 Boot Modes A fully debugged program can be automatically downloaded to the proces sor after power up or after a software reset T he way the loader creates a boot loadable file depends upon how your program is booted into the D SP booting mode 5 2 VisualD SP 3 5 Loader M anual for 16 Bit Processors ADSP 218x DSP Loader Splitter AD SP 218x D SPs support the following boot modes EPROM booting BDM A Host booting IDM A No boot EPROM Booting BDMA
50. 7 dual core application 2 36 DWARF format references A 10 E E BWS bit 3 24 E STAT register 3 18 EEPROM memory 2 28 2 29 ELF file dumper references A 10 EMICTL register 3 24 emulator 1 2 enc dll filename loader switch 2 42 EPROM 5 7 output 2 8 2 42 with no boot data 3 16 excluding AD SP 218x loader 5 10 Executable and Linkable Format ELF 1 2 executable files 1 4 A 6 External Bus Interface U nit EBIU 2 15 external memory 1 4 2 5 2 6 2 15 2 37 EZ KIT Lite boards 1 3 F f file format loader switch 2 42 3 21 4 13 file extensions AD SP 218x 5 17 AD SP 2192 12 loader 4 10 4 13 AD SP 219x loader 3 20 fileformats 1 3 ASCII file5 12 Blackfin loader 2 8 2 48 Intel hex 32 5 7 M otorola 5 7 5 19 see also boot streams selecting for output 2 43 file searches 1 9 files ASM assembly A 3 H header 4 6 l 6 VisualD SP Loader M anual for 16 Bit Processors LDR ASCII format A 9 LDR hex format A 7 build A 5 C C A 2 data files A 3 debugger A 9 executable A 6 format references A 10 formats A 1 input A 2 library A 6 library files A 6 memory map A 7 overlay memory O VL A 6 shared memory SM A 6 text files A 5 final blocks 2 30 see last blocks flags 2 30 2 35 bits of 2 20 structure of 2 21 Flash memory 2 29 booting 2 3 2 6 2 9 2 14 2 16 hold time cycle selection 2 43 Flash Programmer plug in 1 3 forcefirstbyte loader switch 3 21 full memory mode AD SP 218x D SPs 5 4 G
51. 9 for 16 Bit Processors ADSP 219x DSP Booting elfloader proc ADSP 2191 b PROM width 16 appl dxe app2 dxe pdAddrNext 0x20000 elfloader proc ADSP 2191 b PROM width 8 o flash ldr pd 0x20000 p 0x20000 app3 dxe pd 0x30000 app4 dxe In cases where the pa and p values are expected to be the same you may specify pEqua1PD elfloader proc ADSP 2191 b PROM width 16 appl dxe app2 dxe pd 0x20000 pEqualPD width8 o flash ldr app3 dxe pd 0x30000 app4 dxe With the NoDxeAddrHdr switch this artificial block is not inserted T hen the user loader can still parse the complete boot stream block by block until it detects a final init block Since the default p value is reset to a zero whenever an o is specified the addresses in the Intel hex record has to be explicitly set to 0x20000 for f1ash 1dr It is very likely that second stage loaders and similar type of programs exe cute directly from the EPROM Thus this multiple ox amp scenarios are often combined with the features discussed in Enriching Boot EPROM s with N o boot D ata on page 3 16 Host Booting H ost booting is performed in either an 8 bit or 16 bit scenario By default little endian format is used If configured in H ost boot mode the D SP does not support the boot process actively It is the host s responsi bility to initialize the D SP memories properly T he D SP passively waits until the host writes a 1 to the Semaphore A register IO address Ox1
52. Access the Digital Signal Processor D ivision s FT P website at ftp ftp analog com Or ftp 137 71 23 21 ftp ftp analog com xiv VisualD SP Loader M anual for 16 Bit Processors Preface Related Documents For information on product related development software see the follow ing publications isualD SP 3 5 Getting Started Guide for 16 Bit Processors sualD SP 3 5 User s Guide for 16 Bit Processors sualD SP 3 5 Product Release Bulletin for 16 Bit Processors sualD SP 3 5 C C Compiler and Library M anual for Blackfin Processors isualD SP 3 5 C C Compiler and Library M anual for AD SP 219x DSPs sualD SP 3 5 C Compiler and Library M anual for AD SP 218x DSPs sualD SP 3 5 Linker and Utilities M anual for 16 Bit Processors sualD SP 3 5 Assembler and Preprocessor M anual for Blackfin Processors isualD SP 3 5 Assembler and Preprocessor M anual for AD SP 218x and AD SP 219x D SPs sualD SP 3 5 Kernel VDK User s Guide for 16 Bit Processors sualD SP 3 5 Component Software Engineering U ser s Guide for 16 Bit Processors CE I E ee B 2 4 uick Installation Reference Card For hardware information refer to your D SP sH ardwareReference manual and datasheet Online Technical Documentation Online documentation comprises the V isualD SP H elp system and tools manuals D inkum Abridged C library and FlexLM network license manager software documentation Y ou can easily search acrossth
53. D SP 2192 DSP are power on reset forced reset via PCI U SB and software reset T he reset type is specified by bits 8 and 9 cRsT 1 0 of the Chip M ode Status Register CM SR as follows in T able 4 1 Table 4 1 AD SP 2192 12 DSP CM SR Settings CMSR Setting RESET Type CRST lt 1 0 gt 00 Power on reset CRST lt 1 0 gt 10 PCI U SB hard reset CRST lt 1 0 gt 10 PCI U SB hard reset CRST lt 1 0 gt 11 Soft reset from CM SR RST bit If the reset source is a power on reset the processors s BUSMODE pins are read to determine whether boot is via PCI U SB Sub ISA or CardBUS interface T able 4 2 Table 4 2 AD SP 2192 12 D SP Bus M odes Bus Type BUS Mode BUS Mode SCFG BUS 1 0 Pin 0 Pin 1 Register Field Bits 1 10 PCI or Mini PCI GND GND 00 CardBUS PC Card GND Open 01 Sub ISA O pen GND 10 U SB Serial Bus O pen O pen 11 VisualD SP Loader M anual 4 3 for 16 Bit Processors ADSP 2192 DSP Booting Once the bus configurations have been determined assuming that a serial EEPROM exists the boot kernel calls a function to commence reading data from the serial EEPROM Data format of serial EEPROM boot stream is described in the AD SP 2192 DSP RT BL on page 4 4 Oncethe kernel has finished reading data from the serial EEPROM it proceeds to set up and commit bus configurations for the rest of booting viathe PCI or USB interfaces For PCI the configuration regis
54. D SP Loader file Under Name type a name for the D SP s core pxe file From the Link page configure linker options for the core 0 file Run the project T his generates the DxE ovL and sw files oO Ui A UJ From the Project page under N ame type a name for the D SP s core 1 pxt file 8 From the Link page configure linker options for the core 1 file 9 Run the project T his generates the DxE ovL and sM files For more information about the VisualD SP ID DE seethe VisualD SP 3 5 U ser s Guide for 16 bit Processors or online H ep If aDSP executable file changes rerun the loader T he rerun creates a new H file from the bxe ovL and sw input files Then run theRTBL as described in Creating a EXE File on page 4 6 to build an cxt file from the u file Automate these tasks from the V isualD SP environment by specifying the target type as D SP Loader file on the Project page of the Project O ptions dialog box and running the RT BL with a post build command Post Build page of the Project O ptions dialog box this invokes a makefile that builds the RT BL Creating a EXE File T he loader generates a single output file with an H extension As described in Building D XE Files on page 4 5 a host compiler inputs the loader output H and other user written code c or cpP to create a host executable Ext 4 6 VisualD SP Loader M anual for 16 Bit Processors ADSP 2192 12 DSP
55. IN PROCESSOR LOADER SPLITTER Blackin Ue BODUIB reisimas dia debat sciri tabula ud i 2 2 ADSP BF539 Processor BOONG iuasdcnickei aic odh dta ad iata aab sania 2 3 AD SP BF535 Processor On Chip Boot ROM 2 4 AD SP BF535 Processor Second Stage Loader 2 6 AD SP BF535 Processor Boot Streams 2 8 Output Loader FIRES Lai spine tete pen FL Rb del AER Peicida 2 9 Global Headers and BLOCKS iusserit ntn 2 11 iv VisualD SP 3 5 Loader M anual for 16 Bit Processors Contents d s BRUM Preparar 2 13 AD SP BF535 Processor M emory Ranges 2 13 Second Stage Loader Restrictions seessss 2 14 AD SP BF531 BF532 BF533 Processor Booting 2 16 AD SP BF531 BF532 BF533 Processor On Chip Boot ROM 2 17 AD SP BF531 BF532 BF533 Processor Boot Streams 2 19 Blocks and Block H eaders aissasiscki peniia arci Fabi taba ed 2 19 FE Black HOUSE auizepesiisebiartieexeie Ya pe M a 2 20 initialization BIOK conis vnda na 2 21 AD SP BF531 BF532 BF533 Processor M emory Ranges 2 25 AD SP BF531 BF532 BF533 Processor SPI M emory Boot Sequence 2 26 AD SP BF561 Processor Booting uus ener rn nnm rens 2 28 AD SP BF561 Processor Boot Streams 2 29 AD SP BF561 Processor M emory Ranges ssse 2 34 AD SP BF561 Processor Initialization Blocks 2 35 AD
56. IT intents cutie erie s Ped id xii SUDDUITeU POCEO S rania UHR FUR ADEM DM ap Moa hdd xiii Product ON SOND anossa Ul ba La e va rb det xiii Ligstrt sre dur qp NR RR US XIV Embedded Processor and D SP Product Information Xiv Paata DOCUMEN dacuext etusiikqs tpud rut tioin daddi ea existen XV Online Technical Documentation eeeennnnnne XV Prom v raU SR aa xvi do dg ETSI xvi do db ill RUN xvii Printed M ND at catechins vad tsa Decoration si eei xvii VisualD SP Documentation Set eere xvii af puo is ap T T xviii DEOS snosibnibasatedbebibads rir enviar en tnay Hu Fas dU idi cios xviii Contacting DSP Publications Lecta barsii Re tiob Desde RP Pd xviii VisualD SP 3 5 Loader M anual for 16 Bit Processors Notation C ODVERn DIOS aiusosassdikiek pedea haa geli a arde el abd ab aede xx INTRODUCTION Program Development PLOW 1212senpeeteiqedto bvarvibetuka yiri hearty denn 1 1 Compiling ang Assembling iocis dad pa ai abide tb n oda d 1 2 LIBE ob ode MEER E ET E QUIE pb ODE IE ERE 1 2 Lacing amd c TM 1 2 Boot loadable Files Versus N on bootableFiles 1 4 Booting ED mosina dada suia ea 1 5 fene M OUE PN 1 5 PROM Booting ModE uedisseeiueebq eq la ERE ub lC i 1 6 Box PONIO DE ORB iepa Mer uide aa 1 6 2S T di Ne MR RR ines acriaaidaolablaiadinbientautanbes 1 7 Eu MES TT 1 8 Lode FS T S 1 8 FT GENER EI EE id inc ess dM rdg ip Hed baia Uto 1 9 BLACKF
57. Il format files are text representations of ROM memory images that can be post processed by users For more information refer to the chapter in this manual that is appropriate for your target processor Debugger Files D ebugger files provide input to the debugger to define support for simula tion or emulation of your program T he debugger supports all the executable file types produced by the linker DxE sM ovL To simulate 1 0 the debugger also supports the assembler s data file format DAT and the loader s loadable file formats LDR T he standard hexadecimal format for a SPORT data file is oneinteger value per line H exadecimal numbers do not require an 0x prefix A value can have any number of digits but is read into the SPORT register as follows Thehexadecimal number is converted to binary Thenumber of binary bits read in matchesthe word size set for the SPORT register which starts reading from the LSB The SPORT register then fills with zero values shorter than the word size or conversely truncates bits beyond the word size on the M SB end VisualD SP Loader M anual A 9 for 16 Bit Processors Format References In the following example T able A 5 a SPORT register is set for 20 bit words and the data file contains hexadecimal numbers T he simulator con verts the hex numbers to binary and then fills truncates to match the SPORT word size T he 4545 is filled and 123456 is truncated Table A 5 SPOR
58. MOVLAY DMOVLAY loader Includes the AD SP 218x default loader noloader Excludes the AD SP 218x loader When used with 2181 loader or 218x 1oader generates a byte memory image without a loader T his suppresses the preloader and page loaders bdma inputfile start address Use with 2181 loader Specifies placement of an additional DXE file input fi7e in byte memory starting at the specified address T he loader returns an error if the specified address is in use by the loader or by another additional bdma specified file Files specified this way may be BD M A loaded at runtime but the individual start addresses length and target informa tion must be predefined bdmaload inputfile start address Specifies an additional DXE file input fi7e to be placed in byte memory starting at the specified address T he address must be a multi ple of 0x4000 Unlike the bdma switch this option generates a pre loader and page loaders for the specified DxE file This way two or more applications can be stored in the same EPROM and may replace the default application at runtime VisualD SP 3 5 Loader M anual for 16 Bit Processors ADSP 218x DSP Loader Splitter Table 5 5 AD SP 218x DSP BD M A M ode Command Line Switches Switch Description uload filename Reads the BD M A preloader from filename doj T he preloader must consist of exactly 32 instructions Preloaders gene
59. RT BL for an example of how thisis done D ue to the D SP s inability to access W indows virtual memory space the RTBL and driver must be coordinated to make overlays available in PCI memory space T ypically the overlay s image and size information is sent to the driver The driver ma11oc s a memory buffer equal in size to the overlay and then copies the overlay to this space thus making the overlay available in the PCI memory space 4 8 VisualD SP Loader M anual for 16 Bit Processors ADSP 2192 12 DSP Loader Using Overlay Symbols The loader utility when running searches for the 0viPciAdrtb1 and OvlMgrTb1 symbols If the loader cannot resolve the two symbols it sets both values to zero You must declare one or both symbols in the assembly source file to make the run time loader handle the overlay properly The 0viPciAdrtb1 symbol holds the start address of the overlay live address table T he loader gets this symbol s value from the input pxe file and places it in the offset of the first retocation type array The value of the offset of the second retocation type array is then the value of the first relocation type offset plus 2 Consequently each subsequent offset gets a value equal to the previous offset plus 2 The run time loader determines the exact the overlay live address of each overlay according to the provided offset value Instead of defining oviPciAdrTb1 define oviMgrTb1 in the assembly sour
60. SP see Table 5 5 on page 5 10 The sourcefile and outputfi1e names must be placed first on the command line Command line switches may occur in any order except for the 2181 or 218x and 1oader switches When required the 2181 or 218x and 1oader switches follow the outputfile name the 2181 or 218x switch always precedes the loader switch Example elfspl21 p0 dxe output bnm 218x loader i uload test doj In the above example the AD SP 218x BD MA loader runs with p0 dxe the name of the executable file to process into a boot loadable file output bnm the name of the loader output file 218x the target processor one of the AD SP 2184 through AD SP 2189 D SPs 5 8 VisualD SP 3 5 Loader M anual for 16 Bit Processors ADSP 218x DSP Loader Splitter e loader EPROM booting asthe boot mode for the boot loadable file e i Intel hex 32 format for the boot loadable file e uload test doj asthe boot kernel for the boot loadable file File Searches M any loader switches take a file name as an optional parameter T able 5 4 on page 5 9 lists the expected file types File searches are important in the loader operation T he loader supports relative and absolute directory names default directories File searches occur as described on page 1 9 File Extensions T able 5 4 lists and describes file types input and output by the loader Table 5 4 AD SP 218x Loader File Extensions
61. T Data File Example Hex Number Binary Number Truncated Filled A5A5A 1010 0101 1010 0101 1010 1010 0101 1010 0101 1010 FFFF1 1111 1111 1111 1111 000 1111 1111 1111 1111 0001 A5A5 1010 0101 1010 010 0000 1010 0101 1010 0101 5A5A5 0101 1010 0101 1010 010 0101 1010 0101 1010 0101 11111 0001 0001 0001 0001 000 0001 0001 0001 0001 0001 123456 0001 0010 0011 0100 0101 0110 0010 0011 0100 0101 0110 Format References T he following texts define industry standard file formats supported by VisualD SP Gircys G R 1988 U ndersandingand U sing COFF by O Reilly amp Associates N ewton MA 1993 Executable and Linkable Format ELF V1 1 from the Portable Formats Specification V 1 1 T ools Interface Standards TIS Committee Go to http developer intel com vtune tis htm 1993 D ebugging Information Format DWARF V1 1 from the Portable Formats Specification V1 1 UN IX International Inc Go to http developer intel com vtune tis htm VisualD SP Loader M anual for 16 Bit Processors INDEX Symbols ALIGN directive 2 14 ASM assembly files A 3 BNL splitter output files 5 1 5 18 BNM loader output files 5 7 5 9 BNM splitter output files 5 1 5 18 BNU loader output files 5 1 BN U splitter output files 5 18 DAT data initialization files A 3 DLB library files A 6 D XE executable files A 6 D XE loader input files 2 42 5 1 5 9 5 18 H
62. The digits to the left of the point specify the chip tapeout number the digits to the right of the point identify the metal mask revision number The number to the right of the point can not exceed decimal 255 A none version value is also supported indicating that the VDSP tool should ignore silicon errata T hisswitch either generates a warning about any potential anomalous conditions or generates an error if any anomalous conditions occur Note In the absence of the silicon revision switch the loader selects the greatest silicon revision it is aware of if any Note In the absence of the version parameter a valid version value si revision aloneor with an invalid value the loader generates an error O utputs verbose loader messages and status information as the loader processes files waits width Specifies the number of the wait states for external access Valid inputs are 0 through 15 D efault is 15 Wait states apply to the Flash PROM boot mode only Note Currently supported only for AD SP BF535 processors Specifies the loader output file s width in bits Valid values are 8 and 16 depending on the boot mode T he default is 8 T he switch has no effect on boot kernel code processing on AD SP BF535 processors T he loader processes the kernel in 8 bit widths regardless of selection of the output data width For Flash PROM booting the size of the output file depends on the widt
63. U se boot kernel By default this option is selected for AD SP BF535 and grayed out for AD SP BF531 BF532 BF533 and AD SP BF561 processors 4 f you want to produce two output files boot kernel file and appli cation code file select the O utput kernel in separate file check box This option boots the second stage loader from one source and the application code from another source If the O utput kernel in separate file box is selected you can specify the kernel output file options such as the Boot mode source Boot format and O utput width VisualD SP Loader M anual for 16 Bit Processors 2 50 Blac kfin Processor Loader Splitter 5 Enter the Kernel file oxe You must either use the default kernel in case of a AD SP BF535 processor or enter a kernel filename if Use boot kernel in step 3 is selected T he following second stage loaders are currently available for the AD SP BF535 processor Boot Source Second Stage Loader File or Boot Kernel File 8 bit Flash PRO M 535_prom8 dxe 16 bit Flash PRO M 535_proml6 dxe SPI 535_spi dxe For ADSP BF531 AD SP BF532 AD SP BF533 and AD SP BF561 processors no second stage loaders are required hence no default kernel files are provided U sers can supply their own second stage loader file if so desired 6 Specify the Start address FLash PROM output address in hexa decimal format for the kernel code T his option allows you to place the
64. able 5 6 lists and describes each switch used in ID M A mode Table 5 6 AD SP 218x DSP IDM A Command Line Switches Switch Description sourcefile Specifies the executable file DXE to be processed for a single processor boot loadable file outputfile Specifies the output file 1DM 218 x 1 Specifies the target processor e 2181 ADSP 2181 or ADSP 2183 D SP 218x one of the AD SP 2184 through AD SP 2189 D SP W hen used with 1oader keeps the image 218 4 5 6 8 9 Usein place of 218x Specifies the AD SP 2184 AD SP 2185 ADSP 2186 AD SP 2187 AD SP 2188 or AD SP 2189 D SP asa target processor Supports PMOVLAY DMOVLAY idma Forces the loader to create an ID M A boot file It overwrites most of the BDMA boot specific options No Booting In very rare cases applications require that the D SP not be booted after reset or that the D SP is booted with aROM connected to the D SP s off chip DM PM address space Preparing a non bootable PROM image is called splitting n most cases developers working with AD SP 218x D SPs usethe loader instead of the splitter For AD SP 218x D SPs splitter and loader features are handled by VisualD SP 3 5 Loader M anual 5 13 for 16 Bit Processors ADSP 218x DSP Loader Guide the e1fsp121 exe T he splitter must be invoked by a completely different set of command line switches Refer to the following AD SP 218x D SP Splitter Guide for more inf
65. adable files 1 2 loader AD SP 218x D SPs 1 4 3 1 5 1 5 2 AD SP 2191 processors 3 19 AD SP 2192 12 D SP 4 1 AD SP 219x D SPs 3 2 boot kernel 1 7 3 4 build options 4 6 for AD SP 218x processors 5 1 hex format files A 7 settings selection 3 21 4 13 5 9 loader loader switch 5 10 M M loader switch 2 44 3 21 4 13 maskaddr loader switch 2 44 3 22 masking EPROM address bits 2 44 M axBlockSize loader switch 2 44 memory ranges 2 34 MM loader switch 2 44 3 21 4 13 MM AP pin 5 4 M o loader switch 2 44 3 22 4 14 M ode D pin settings AD SP 218x D SPs 5 5 modes see boot modes M otorola S2 format 5 10 53 format 5 17 Mt loader switch 2 45 3 22 4 14 multi D XE booting 2 37 multiprocessor systems 1 4 N no2kernel loader switch 2 45 no boot data in EPROM image 3 16 no boot mode 2 45 AD SP 218x D SPs 5 3 5 13 5 15 AD SP 219x D SPs 3 5 3 12 AD SP BF531 32 33 2 16 VisualD SP Loader M anual for 16 Bit Processors AD SP BF535 processors 2 3 Blackfin processors 2 53 overview 1 5 Selecting 2 48 2 53 N oD xeAddrH dr loader switch 3 22 noloader loader switch 5 10 non bootable files 1 4 2 45 5 1 0 0 loader switch 2 45 3 22 4 14 02 two output files loader switch 2 45 offsetaddr loader switch 5 11 offsetpage loader switch 5 11 on chip boot ROM 2 25 2 26 2 34 AD SP BF531 32 33 processors 2 16 AD SP BF535 processors 2 4 opmode z loader switch 3 22 OPMODE pin AD SP 219x D SPs 3 3
66. ader M anual 2 23 for 16 Bit Processors Blac kfin Processor Booting PO H EBIU_SDRRC gt gt 16 amp OxFFFF RO 0x074A 2 WEPO RO SSYNC PO L EBIU SDBCTL amp OxFFFF SDRAM Memory Bank Control Register PO H EBIU_SDBCTL gt gt 16 amp OxFFFF RO 0x0001 2 WCPO RO SSYNC PO L EBIU_SDGCTL amp OxFFFF SDRAM Memory Global Control Register PO H EBIU_SDGCTL gt gt 16 amp OXFFFF RO L 0x998D RO H 0x0091 PO RO SSYNC RRKKKKKKKKKKKKKKKKKEKDOSHK Init Section X X Xx KKK KK KK KKK KK KKK L3 SP L2 SP L1 SP LO SP M3 SP M2 SP MI SP MO SP B3 SP B2 SP Bl SP BO SP 13 SP 12 SP I1 SP 10 SP p5 0 SP r7 0 SP RETS SP ASTAT SP RE RKRR KKK KK KKK KKK KK KK KKK KK KK KK KK KKK KKK KKK KKK KKK KK KKK KKK KKK KK KK RTS 2 24 VisualD SP Loader M anual for 16 Bit Processors Blac kfin Processor Loader Splitter ADSP BF531 BF532 BF533 Processor Memory Ranges The on chip boot ROM on AD SP BF531 AD SP BF532 and AD SP BF533 Blackfin processors allows booting to the following memory ranges e L1 memory e ADSP BF531 processor v DataBank A SRAM oxFF80 4000 0xFF80 7FFF v Instruction SRAM oxFFAO 8000 FFAO BFFF ADSP BF532 processor v DataBank A SRAM oxFF80 4000 0xFF80 7FFF v DataBank
67. ader switch 5 10 S splitter switch 5 19 scratch memory 2 35 SD RAM memory 2 6 2 13 2 25 2 35 configuring 2 14 init code example 2 23 initializing 2 14 2 21 2 25 second stage loader 2 6 2 35 2 36 2 49 2 51 default settings 2 49 restrictions 2 14 selecting 2 48 setting options 2 49 shared memory 2 36 silicon revision setting 2 46 4 14 simulating booting process 5 7 simulator 1 2 1 3 S revision loader switch 4 14 S revision loader switch 2 46 slave processors 1 4 5 11 software resets 1 5 source files 1 2 assembly instructions A 3 C C A 2 fixed point data A 3 specifying format bytestream 5 10 Intel hex 5 10 M otorola 5 10 specifying kernel amp app files 2 50 specifying M otorola formats 5 19 SPI booting 2 3 2 9 2 12 2 14 2 16 2 26 baudrate 2 42 SPI memory 2 26 2 28 8 16 24 bit addressable 2 27 split loader switch 3 23 splitter AD SP 218x D SPs 5 1 5 15 AD SP 219x D SPs 3 13 ASCII format files LD R A 9 splitting 1 4 SPORT data files A 9 SRAM memory 2 25 2 28 2 34 2 13 start addresses 2 16 5 10 status information 2 46 2 48 streams l 10 VisualD SP Loader M anual for 16 Bit Processors see boot streams supervisor mode 2 28 SYSCR register 2 5 2 29 AD SP BF531 32 33 processors 2 17 AD SP BF535 processors 2 2 2 4 U uload file loader switch 5 11 us splitter switch 5 19 user interrupts 2 28 utilities elfloader exe AD SP 219x 3 1 V V verbose loader switch 2 46
68. age 4 13 Single Proc essor Command Line U se the following syntax for the loader s command line when there is only one input executable Dx elfloader coreO0 sourcefile o outputfile proc ADSP 2192 switch or elfloader corel sourcefile o outputfile proc ADSP 2192 switch where coreQ corel Specify that the sourcefile is for coreo Or corel respectively T he loader makes up the array and structure names according to the supplied core number e sourcefile Identifies the input executable file 0xe to process A file name can include the drive and directory enclose long file name within straight quotes long file name Before running the loader ensure that all ovi and sm filesresidein the same working directory as the executable T he loader automatically opensthe overlay and shared memory files to read in the data while process ing the executables 4 10 VisualD SP Loader M anual for 16 Bit Processors ADSP 2192 12 DSP Loader e o outputfile Optional name of the loader s output a C lan guage header file e proc ADSP 2192 T he mandatory switch directs the loader to produce an output filefor the AD SP 2192 processor e switch Oneor more optional switches to pass to the loader Command line switches may be placed in any order Two Proc essor Command Line U se the following syntax for the loader s command line when there are two input executables xt elfl
69. am Development How Compiling and Assembling Input source files are compiled and assembled to yield object files Source files are text files containing C C code compiler directives possibly a mixture of assembly code and directives and typically preprocessor com mands Refer to the VisualD SP 3 5 Assembler and Preprocessor M anual or the VisualD SP 3 5 C C Compiler and Library M anual for informa tion about the assembler and compiler source files Linking U nder the direction of the Linker D escription File LDF and linker set tings the linker consumes separately assembled object and library files to yield an executable file If specified shared memory and overlay files are also produced The linker output conforms to the Executable and Link able Format ELF an industry standard format for executable files T he linker also produces map files and other embedded information used by the debugger DW ARF 2 T hese executable files oxe are not readable by the processor hardware directly T hey areneither supposed to be burned onto a EPROM or Flash memory device Executable files are consumed by V isualD SP debugging targets such as the simulator or emulator Refer to the VisualD SP 3 5 Linker and Utilities M anual for 16 Bit Processors and online H elp for infor mation about linking and debugging Loading and Splitting U pon completing the debug cycle the processor hardware needs to run on its own without
70. ample for M ultiple D XE Boot d Finclude lt defBF532 h gt SECTION progra Pre Init SACLE TON KKK KKK KK KAKA KK KKK KKK KKK KK KK KK KKK KKK KK KK SP ASTAT SP RETS SP r7 0 SP p5 0 be Pa c lO bee SP iS 1 Pele Pai 2s PaaS Py Se 13 SP BOsE SPJ 2 Blsip SP B2 b SPJ B3 SP MO SP M1 SP M2 SP M3 SP LO SP L1 SP L2 SP L3 BRK RKKK KK KKK KKK KK KKK KK KK KK KK KK KKK KKK KKK KK KK KKK KKK KKK KKK KKK KK KK Init Code Section X Xx X Xkkkckk kk KKK KKK KKK KK KKK KKK KK KKK RO H RO L High Address of DXE Location Low Address of DXE Location RO for Flash Prom Boot R3 for SPI boot RO for Flash Prom Boot R3 for SPI boot KKK KK KK KKK KKK KKK KK KK KK KK KK KKK KKK KKK KK KK KKK KKK KKK KK KKK ke kk KK KK KKK Post nit SOCET ON KARR KKK KKKK KKK KKK KK KK KKK KK ke KK KK KK KKK LS SP L2 ES PAs OBL SES Pee o LOHS LSPA ds M3 LSPA M2 ESP MLS CSR MO ESPER B3 SP B2 SP Bl SP BO SP 3 ESPHt hs I2 pSPrrt IL SPetr IO SP p5 0 SP MAKE SURE NOT TO RESTORE RO for Flash Prom Boot R3 for SPI Boot r7 0 SP RETS SP ASTAT SP ERK KRKKK KK KKK KKK KK KKK KK KK KK KK KK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KK KK RTS VisualD SP Loader M anual for 16 B
71. bling 1 2 assembly initialization data files D AT A 3 asynchronous INDEX memory bank 0 2 53 B b boot mode loader switch 2 42 3 21 baud rate 2 49 baudrate loader switch 2 42 BDMA interface 5 3 5 4 transfers 5 7 bdma input start address loader switch 5 10 bdmaload loader switch 5 10 Blackfin loader default settings 2 40 2 47 output file settings 2 47 Blackfin loader switches 2 47 b prom flash spi 2 42 baudrate 2 42 enc dll filename 2 42 f format 2 42 ghc 2 43 help 2 43 H oldT ime 2 43 init filename 2 43 kb K ernelBootM ode 2 43 kenc dll filename 2 42 kf KernelFormat 2 43 kp 2 44 kW idth 2 44 userkernel 2 44 M 2 44 maskaddr 2 44 M axBlockSize 2 44 MM 2 44 VisualD SP Loader M anual for 16 Bit Processors INDEX M o filename 2 44 M t filename 2 45 no2kernel 2 45 0 filename 2 45 02 two output files 2 45 p 2 45 proc processor 2 45 romsplitter 2 45 S revision version 2 46 4 14 Verbose 2 46 4 14 Waits 2 46 width 2 46 width word width 2 46 Blackfin loader splitter 3 1 Blackfin processors 2 1 baud rate 2 49 boot formats 2 48 boot modes 2 48 boot ROM 2 17 boot sources 2 2 Flash see Flash memory full boot 2 5 2 17 hold time 2 48 loader file formats 2 8 multi file booting AD SP BF51 2 3 2 37 no booting bypass 2 2 2 45 PROM seePROM memory see also second stage loader specifying boot modes 2 43 SPI memor
72. boot source execute from 16 bit 1 Start executing from the external memory beginning of on chip L1 01 Use boot ROM to load memory or the beginning of from 8 bit flash ASYNC Bank 0 when 10 Use boot ROM to configure BMODE 1 0 b 00 and load boot code from SPI serial ROM 8 bit address range 11 Use boot ROM to configure and load boot code from SPI serial ROM 16 bit address range Figure 2 8 AD SP BF 533 Processors System Reset Configuration Register 3 Eventually if bit 4 of the syscr register is not set the on chip boot ROM performs the full boot sequence Figure 2 9 VisualD SP Loader M anual 2 17 for 16 Bit Processors Blackfin Processor Booting ADSP BF531 BF532 BF533 Processor PROM Flash or SPI Device 10 Byte Header for Block 1 Block 1 10 Byte Header for Block 2 Block 2 App 10 Byte Header for Block3 Code Data Block 3 10 Byte Header for Block n Block n Figure 2 9 ADSP BF531 BF532 BF533 Processors Booting Sequence T he booting sequence for AD SP BF531 AD SP BF532 and AD SP BF533 processors is quite different from that of AD SP BF535 pro cessors T heon chip boot ROM for the former processors behaves similar to the second stage loader of AD SP BF535 processors T he boot ROM has the capability to parse address and count information for each boota ble block T his alleviates the need for a second stage loader for AD SP BF531 BF532 BF533 processors because a f
73. cFC Then the D SP starts fetching and executing instructions at address 0x00 0000 3 10 VisualD SP Loader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter It is recommended that the host parses the boot stream and downloads segment by segment T he e1f10oader exe may store the boot stream as an Intel hex 32 filetypically required by embedded host devices PC based hosts may favor the ASCII format which stores one byte or one 16 bit word per line UART Booting W hen booting via the UART port a host downloads a boot stream for matted program to the D SP following an auto baud handshake sequence T he auto baud feature simplifies system design because you do not need to calculate boot clock rates as a function of crystal frequency core clock divider peripheral clock mode and so on T he booting host can select a baud rate including a non standard rate anywhere within the UART clocking capabilities Following a hardware or software reset the AD SP 219x D SP monitorsthe UART transceiver channel and expects the predefined character 0xA4 to determine the bit rate The D SP replies an ox string to acknowledge the bit rate Afterwards the host may send the complete boot stream 8 data bits no parity 1 stop bit without further handshake T he boot stream is decoded by the D SP and starts program execution automatically Compared to other formats the AD SP 2191 2195 2196 UART boot stream suppresses the v
74. cannot access off chip addresses lower than 0x010000 T ypically this address space is accessed by taking advantage of address aliasing T he memory strobe Ms0 covers an address range from 0x010000 to 0x400000 For example if the EPROM sizeis less than 4M wordsand the EPROM istheonly device connected to MS0 the first 64K words can be accessed through addresses 0x200000 tO Ox20FFFF If a project consists only of two segments seg ext data and seg ext code a 128K x 16 bit EPROM device would be sufficient to store all the required data and instructions If the loader utility is invoked with the maskaddr 17 Switch on page 3 22 all physical address bits greater than or equal to A17 are masked out T heloader AN D s all physical addresses with oxoirrrr The resulting EPROM image maps segment seg ext code into the unused space below 0x010000 see T able 3 3 T his way a 128K x 16 bit EPROM can be burned properly At runtime seg ext code aliases back to the addresses above 0x020000 when address lines A17 through 421 are not connected 3 14 VisualD SP Loader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter Table 3 3 EPROM Image Two Segments O nly Address range Purpose 0x000000 OxOOFFFF seg ext data 0x010000 OxO1FFFF seg ext code T ypically the loader utility generates an Intel hex 32 file which is read able by most EPROM s If theimage must be post processed the loader may
75. ce code T his symbol should contain the start address of the overlay table and the overlay table can be declared and defined in your assembly source code T he loader gets this symbol s value and makes the j aef ine statement along with the other def ine statement for example define COREO OVL MGR TBL 0 define COREO OVL COUNT 3 T he first def ine statement provides the start address of the overlay table Thisiszero when the loader fails to find the symbol in the input nxe file Correct the value by manually changing the value or by defining it in the assembly source code and re building the loader file T he second define statement provides the number of overlay for core 0 T he run time loader later uses the provided overlay table start address to find the entry for the live start address each overlay and changes it before loading the overlay table into D SP memory VisualD SP Loader M anual 4 9 for 16 Bit Processors ADSP 2192 DSP Loader Guide ADSP 2192 DSP Loader Guide T his section provides reference information on the AD SP 2192 loader s command line interface W hen using the loader from within VisualD SP settings on the Load page of the Project O ptions dialog box correspond to the loader s com mand line switches For more information see the VisualD SP 3 5 U ser s Guide for 16 bit Processors or onlineH elp A list of switches and a description of each appear in Loader Com mand Line Switches on p
76. d ModeD ModeC ModeB ModeA D escription 0 1 0 0 BD MA is used to load the first 32 program memory words from the byte memory space Program execu tion is held off until all 32 words have been loaded Chip is configured in Host mode IACK has active pull down 2 N ote Requires additional hardware IDMA is used to load any internal memory as desired Program execution is held off until the host writes to internal program memory location 0 Chip is config ured in Host mode 1ACK has active pull down BDMA is used to load the first 32 program memory words from byte memory space Program execution is held off until all 32 words have been loaded Chip is configured in H ost mode IACK requires external pull down N ote Requires additional hardware IDMA isused to load any internal memory as desired Program execution is held off until the host writes to internal program memory location 0 The chip is con figured in H ost mode 1ACK requires external pull down 2 1 Considered as standard operating settings U sing these configurations allows easier design and better memory management T able 5 3 lists D SPs that support M ode D operation Mode D pin Table 5 3 AD SP 218x D SPs Supporting M ode D O peration AD SP 2184N ADSP 2185M ADSP 2185N AD SP 2186M AD SP 2186M ADSP 2187L ADSP 2187N AD SP 2188M AD SP 2188N AD SP 2189M AD SP 2189N
77. d by data blocks Block Headers Each block header consists of four or six 16 bit words e The first word consists of a flag that indicates whether the follow ing block of data is a 24 bit or 16 bit payload or zero initialized data T he flag uniquely identifies the last block that needs to be transferred Thesecond word contains the lower 16 bits of the 24 bit start address for data loading destination T he first octet is the 8 LSBs followed by the next most significant bits 15 8 and so on Thethird word contains the upper most 8 bits of the 24 bit desti nation address padded suffixed with one byte of zeros e The fourth word contains the payload s word count Similar to the address the first octet isthe 8 LSBs and the second octet is the 8 M SBs An extra word appears when a checksum function is used to verify booting accuracy T his fifth word also a 16 bit field isthe CRC 16 checksum for the header and the data block immediately follows it The CRC checksum word is optional Activate the checksum by running the loader utility with the checksum Command line switch on page 3 21 T he header is buffered with a dummy word of zeros to ease the EM addressing issue EPROM booting can be performed in an 8 bit or 16 bit scenario T his information is controlled by the width switch and is finally embed ded in the boot stream U nlike non boot mode bus width is not VisualD SP Loader M anual 3 5 for
78. d descrip tion of BDMA capabilities You can debug the EPROM booting process using the VisualD SP simulator by loading the Bn file Settings gt Sim ulator and then resetting D ebug gt R eset the D SP to start booting T he loader outputs files in industry standard file formats Intel hex 32 and M otorolaS which are readable by most EPROM burners For advanced usage other file formats are supported refer to Appendix A File Formats for details T he default file extension is BNM ADSP 218x BDMA Loader Command Line Reference This section details the AD SP 218x BDMA loader s command line interface T he syntax for the loader s command line is elfspl21 sourcefile outputfile 218 x 1 switch VisualD SP 3 5 Loader M anual 5 7 for 16 Bit Processors ADSP 218x DSP Loader Guide where D sourcefile dentifies the executable file Dx amp to process into a single processor boot loadable file A file name can include the drive and directory Enclose long file names within straight quotes long file name output fi 1e Specifies the output file T he optional parameter can include the drive directory file name and file extension 8NM switch O ptional switches to process T he loader provides many switches to select operations and modes see T able 5 5 on page 5 10 218 x 1 Specifies the target processor Always specify either 2181 Or 218x when working with an AD SP 218x D
79. d into internal memory via the on chip boot ROM it has full control over the boot process N ow the second stage loader can use the pxe byte counts to boot in one or more DXxES from external memory VisualD SP Loader M anual 2 37 for 16 Bit Processors Blackfin Proc essor Booting 10 Byte Header for Block 1 Block 1 10 Byte Header for Block 2 Block 2 10 Byte Header for Block 3 Block 3 Figure 2 13 AD SP BF531 BF32 BF33 BF561 M ulti Application Booting 2 Usethe initialization block switch init filename where file name is the name of the executable file containing the init code This option allows you to change the external memory pointer and boot a specific oxe via the on chip boot ROM A sample initialization code is included in Listing 2 2 The ro and R3 registers are used as external memory pointers by the on chip boot ROM The no register is for Flash PROM boot and n3 is for SPI memory boot Within the initialization block code change the value of no or R3 to point to the external memory location at which the specific application code starts After the processor returns from the initialization block code to the on chip boot ROM the on chip boot ROM continues to boot in bytes from the location specified in the Ro or n3 register VisualD SP Loader M anual for 16 Bit Processors Blac kfin Processor Loader Splitter Listing 2 2 Initialization Block Code Ex
80. d preloader 32 instructions address opcodes ax0 0x0060 dm 0x3fe2 ax0 BEAD 0x0000 400600 93FE20 ax0 0x0020 dm 0x3fel ax0 BIAD 0x0002 400200 93FE10 ax0 0x0000 dm 0x3fe3 ax0 CTRL 0x0004 400000 93FE30 ax0 0x0087 dm 0Ox3fe4 ax0 BWCOUNTOx0006 400870 93FE40 ifc 0x0008 nop BDMA IRQ 0x0008 3C008C 000000 imask 0x0008 0x000A 3C0083 idle 0x000B 028000 jump 0x0020 nop nop nop 0x000C 18020F 000000 nop nop nop nop 0x0010 000000 000000 5 6 VisualD SP 3 5 Loader M anual for 16 Bit Processors ADSP 218x DSP Loader Splitter nop nop nop nop 0x0014 000000 000000 nop nop nop nop 0x0018 000000 000000 rti nop nop nop 0x001C 0A001F 000000 T he page loaders are generated dynamically by the e1fsp121 depending on the number of overlay pages to be initialized A page loader sets up BD MA transfers Since BD M A transfers cannot target off chip DM and PM memories overlay pages 1 and 2 directly the corresponding page loaders first BD M A load the data into on chip memory and then copy the data by core instructions The final BD MA sequencehasthe BCR bit set It overwrites the preloader and page loaders resident in internal PM memory and issues a context reset once it has finished The program counter resets to 0x0000 and pro gram execution begins Refer to the AD SP 218x DSP H ardware Reference for a detaile
81. ddressable SPI 11 OxFFAO 8000 OxFFAO 0000 memory A description of each boot mode is as follows ADSP BF531 BF532 BF533 Processor O n Chip Boot ROM on page 2 17 ADSP BF531 BF532 BF533 Processor Boot Streams on page 2 19 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter ADSP BF531 BF532 BF533 Processor On Chip Boot ROM The on chip boot ROM for AD SP BF531 BF532 BF533 processors does the following 1 Sets up supervisor mode by exiting the RESET interrupt service rou tine and jumping into the lowest priority interrupt 1v615 2 Checks whether the RESET was a software reset and if so whether to skip the entire boot sequence and jump to the start of L1 memory OxFFAO 0000 for AD SP BF533 processor oxrrAo 8000 for AD SP BF531 and AD SP BF532 processors for execution T he on chip boot ROM doesthis by checking bit 4 of the System R eset Configuration Register Figure 2 8 If bit 4 is not set the on chip boot ROM performs the full boot sequence If bit 4 is set the on chip boot ROM bypasses the full boot sequence and jumps to the start of L1 memory System Reset Configuration Register SYSCR X state is initialized from mode pins during hardware reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset dependent on pin sero PT To Po P To eT PT TTE n No Boot on Software Reset LLL pe BMODE 1 0 Boot Mode RO 0 Use BMODE to determine 00 Bypass boot ROM
82. de ADSP 218x Splitter Command Line Reference T he splitter e1 fsp121 exe generates non bootable PRO M image files for AD SP 218x D SPs by processing executable files Dxt T he splitter command line is case sensitive Run the splitter from the command line using the following syntax elfspl21 sourcefile outputfile pm amp dm switch where sourcefile Name of the executable file DxE to be processed for a non bootable PRO M image file A filename can includethe driveand directory Encloselong file names within straight quotes long file name outputfile O ptional name of the splitter s output aPROM file with the BNL BNU Or BNM file extension e switch Oneor more optional switches to process Switches select operations and modes for the splitter pm amp dm Indicates that either pm or dm or both can be used Example T he following two command lines run the splitter twice first producing PROM filesfor program memory and then producing PROM files for data memory elfspl21 my proj dxe pm stuff pm elfspl21 my proj dxe dm stuff dm 5 16 VisualD SP 3 5 Loader M anual for 16 Bit Processors ADSP 218x DSP Loader Splitter T he switches on these command lines are as follows pm dm Select program memory or data memory as the source in the exe cutable for extraction and placement into the image Because these are the only switches used to identify the memory sou
83. e proc processor Part number of the processor for which the loader file isto be built Provide a part number for every input DXE if designing multi processor systems Running the loader without proc results in an error e switch One or more optional switches to process Switches select operations and modes for the loader See T able 3 5 on page 3 20 for a complete list of the loader command line switches VisualD SP Loader M anual 3 19 for 16 Bit Processors ADSP 219x DSP Loader Guide Example elfloader p0 dxe proc ADSP 2191 In the above example the loader runs with e p0 dxe the name of the executable file to be processed into a boot loadablefile T he output file s nameis po 1dr because a name is not specified e proc ADSP 2191 the target processor AD SP 2191 D SP File Searches M any loader switches take a file name as an optional parameter T able 3 5 on page 3 20 lists the expected filetypes File searches are important in the loader operation T heloader supports relative and absolute directory names default directories File searches occur as described on page 1 9 File Extensions T able 3 5 lists and describes file types input and output by the loader Table 3 5 File Extensions for AD SP 218x Loader O peration File Extension D escription DXE Executable files and boot kernel files 0VL O verlay memory files T he loader recognizes overlay memory files but does not expect
84. e entire VisualD SP documentation set for any topic of interest For easy print ing supplementary Por files for the tools manuals are also provided A description of each documentation file type is as follows VisualD SP Loader M anual XV for 16 Bit Processors Product Information File Description CHM H elp system files and V isualD SP tools manuals HTM or Dinkum Abridged C library and FlexLM network license manager software doc HTML umentation Viewing and printing the HTML files require a browser such as Inter net Explorer 4 0 or higher PDF VisualD SP manuals in Portable Documentation Format one PDF file for each manual Viewing and printing a PDF file require a PDF reader such as Adobe Acrobat Reader 4 0 or higher If documentation is not installed on your system as part of the software installation you can add it from the VisualD SP CD ROM at any time by rerunning the T ools installation Access the online documentation from the V isualD SP environment W indows Explorer or Analog D evices W eb site From VisualDSP e Access VisualD SP online H elp from the H elp menu s Contents Search and Index commands e Open online H elp from context sensitive user interface items toolbar buttons menu commands and windows From Windows In addition to shortcuts you may have constructed there are many ways to open VisualD SP online H elp or the supplem
85. e second stage loader jumps to the start of L2 memory oxrooo 0000 for application code execution Figure 2 7 ADSP BF535 Processor PROM Flash or SPI Device Application Code Data SDRAM Figure 2 7 AD SP BF535 Processors Starting Application Code ADSP BF535 Processor Boot Streams T he loader generates the boot stream and places the boot stream in the output loader file LDR The loader prepares the boot stream in such a way that the on chip boot ROM and the second stage loader can correctly load the application code and data to the processor memory T herefore the boot stream contains not only the user application code but also header and flag information that is used by the on chip boot ROM and the second stage loader 2 8 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter Diagrams in this section illustrate boot streams utilized by the AD SP BF535 processor s boot kernel T he elements are covered as follows Output Loader Files on page 2 9 e Global H eaders on page 2 12 Block H eaders on page 2 13 Flags on page 2 13 Output Loader Files An output loader file for 8 bit PRO M Flash booting and 8 16 bit addressable SPI booting without the second stage loader Output LDR File Byte Count for Application Code 4 Application Code VisualD SP Loader M anual 2 9 for 16 Bit Processors Blackfin Processor Booting An output loader f
86. entary documentation from W indows H elp system files cuw files are located in the He1p folder and por files are located in the Docs folder of your VisualD SP installation T he Docs folder also contains the D inkum Abridged C library and FlexLM net Work license manager software documentation Xvi VisualD SP Loader M anual for 16 Bit Processors Preface U sing Windows Explorer Double click any file that is part of the VisualD SP documenta tion set e Doubleclick the vdsp help chm file which is the master H elp sys tem to access all the other cu files Using the W indows Start Button Access V isualD SP online H elp by clicking the Start button and choos ing Programs Analog D evices VisualD SP for 16 bit processors and VisualD SP D ocumentation From the Web T o download the tools manuals point your browser at www analog com technology dsp developmentTools gen purpose html Select a D SP family and book title Download archive z1P files one for each manual U se any archive management software such as W inZip to decompress downloaded files Printed Manuals For general questions regarding literature ordering call the Literature Center at 1 800 AN ALO GD 1 800 262 5643 and follow the prompts VisualDSP Documentation Set VisualD SP manuals may be purchased through Analog D evices Customer Service at 1 781 329 4700 ask for a Customer Service representative T he man
87. er programs 3 19 AD SP 2192 Boot Loader switches dAD SP2192 4 14 AD SP 2192 loader switches help 4 13 AD SP 2192 12 D SPs boot loader utility 4 10 CM SR settings 4 3 loader 4 2 4 4 AD SP 2192 12 loader switches f format 4 13 M 4 13 MM 4 13 M o filename 4 14 M t filename 4 14 0 filename 4 14 proc AD SP 2192 4 14 verbose 4 14 AD SP 219x D SPs boot streams 3 4 elfloader exe 3 2 AD SP 219x loader switches b type 3 21 blocksize 3 21 checksum 3 21 clkdivide 3 21 f format 3 21 forcefirstbyte 3 21 host3bytes 3 21 M 3 21 maskaddr 3 22 MM 3 21 M o filename 3 22 M t filename 3 22 N oD xeA ddrH dr 3 22 0 filename 3 22 opmode 3 22 p address 3 22 pd address 3 23 pdAddrN ext address 3 23 pEqualPd address 3 22 pEqualZ ero address 3 22 VisualD SP Loader M anual for 16 Bit Processors proc processor 3 23 readall 3 23 romsplitter 3 23 split 3 23 verbose 3 23 waits 3 24 width 3 24 AD SP 219x loader splitter 3 1 AD SP BF531 BF532 BF533 processors boot streams 2 19 memory ranges 2 25 SPI memory booting 2 26 AD SP BF535 processors boot streams 2 8 memory ranges 2 13 AD SP BF561 processors boot ROM 2 28 boot streams 2 29 2 31 dual core 2 28 2 29 initialization blocks 2 35 memory ranges 2 34 multi D XE booting 2 36 on chip boot ROM 2 34 application code start address 2 8 2 45 2 48 archive files A 6 see library files A 6 assembler source files ASM A 3 assem
88. ery first byte T o force the loader util ity to include the first byte use the forcefirstbyte switch on page 3 21 T his boot operation is controlled by a UART boot routine in the internal ROM space While booting via UART the highest 16 locations in page 0 program memory block 0x7FFO to 0x7FFF and the top 272 locations of page 0 data memory block oxFEFO to oxFFFF are reserved for use by the ROM boot routine VisualD SP Loader M anual 3 11 for 16 Bit Processors ADSP 219x DSP Booting Serial EPROM Booting T he SPIO port is used when booting from an SPI compatible EPROM T he SPI port selects a single serial EPROM device using the Pro pin asa chip select submits a read command and address 0x00 and begins to clock consecutive data into memory internal memory or external mem ory at a sck clock frequency of H CLK 60 The D SP streams the complete boot image in and processes it without further handshake with the SPI EPROM T wo types of SPI EEPROM devices are supported devices of 4K bytes and smaller 12 bit address range and those larger than 4K bytes 16 bit address range T he SPI boot stream may not exceed 64 kilobytes T his boot operation is controlled by an SPI boot routinein internal ROM space W hile booting via serial EPROM the highest 16 locations in page 0 program memory block 0x7FFO to ox7rrr and the top 272 loca tions of page 0 data memory block oxFEFO to oxrrrr are reserved for use by theROM bo
89. ess counter Figure 5 1 on page 5 12 illustrates the algorithm the host processor must compute to boot the D SP successfully VisualD SP 3 5 Loader M anual 5 11 for 16 Bit Processors ADSP 218x DSP Loader Guide Read next word count N Read IDMA Control value and perform Address Latch Cycle Bypass this step if elfspl21has not Read IDMA Overlay value and A been invoked by the 218x switch perform Address Latch Cycle Read next 16 bit Data value and write to IDMA Decrement N Figure 5 1 H ost Processor Algorithm T he loader generates an ASCII file 1pm Every segment data is headed by the following information word count ID M A control value and over lay page number Since the ID M A interface is a 16 bit interface the 1 DM file is organized in 16 bit portions Typically embedded processors cannot directly process ASCII files in IDM format It is up to the user to post process this filein a customized Way D ueto hardware restrictions ID M A booting of off chip memories is not possible Refer to the description of ID M A capabilities in the ADSP 218x D SP Hardware Reference 5 12 VisualD SP 3 5 Loader M anual for 16 Bit Processors ADSP 218x DSP Loader Splitter ADSP 218x IDMA Loader Command Line Reference To createan IDM A boot file use the following syntax for the AD SP 218x loader s command line elfspl21 sourcefile outputfile 218 x 1 idma T
90. f Filel dxe Starts at EPROM address 0x000000 If thereisa pd addr switch specified for an executable file Fi7e dxe the switches between pd and ri e dxe are called a pd grouping The addr parameter is the address in the byte based PROM address space T he address should be a hex value If pd addr is absent from a command line no pd grouping is associated with the executable file but the address in the byte based PROM address space remains associated with the DXE Usually the pd addr switch is applied if the individual boot streams need to be located a given addresses For example when the individual boot streams need to reside is certain pages of a Flash memory device If the dif ferent boot streams are going to reside in different physical PROM devices this syntax enables the user to assign different settings such as wait states or even output file name to the individual DXES VisualD SP Loader M anual 3 7 for 16 Bit Processors ADSP 219x DSP Booting If more than one pxe file is listed at the command line without pa switch the loader utility appends the boot stream of the second DXxE immediately to the one of the first bxe and so on Executable files inherit boot stream settings from previous one if not explicitly set by a pd grouping The pd grouping enables various options for the loader stream of the input dxe file In the multiinput Dxr scenario the loader stream for each executable is same as when
91. h switch e For SPI booting the size of the output LDR file is the same for both width 8 and width 16 The only difference is the header information 2 46 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter Using Base Loader T he Load page of the Project O ptions dialog consists of multiple panes and is the same and for all Blackfin processors W hen you open the Load page the default loader settings Loader options for the selected proces sor are already set As an example Figure 2 14 shows the AD SP BF532 processor s default Load settings for PROM booting Command line switches equivalent to the dialog box options are also identified Refer to Command Line Switches on page 2 42 for more information on the switches Project Options Load dl Project General VIDL Compile Assemble Link Category Loader options b r Boot mode Boot format Output width Start address p 4 PROM ntelhex 8 bit 0x0 l C Flash ASCII C 16 bit mn C SPI C Binary Verbos V baudrate Wait state waits e 500k holdtime Hold time Baud rate Initialization file Es sad Dutput file Additional options init Figure 2 14 Base Load Page Loader File O ptions Pane VisualD SP Loader M anual for 16 Bit Processors 2 47 Blackfin Processor Loader Guide U s
92. he default For PROM booting Intel nex istheonly valid entry When f ASCII and romsplitter are selected regardless of the b file type setting an ASCII file is produced forcefirstbyte Forces the writing of the first byte of the UART boot stream Usethis option when the bit rate is high for 16 Bit Processors h Invokes the command line help outputs a list of command line switches or to standard output and exits By default the h switch alone provides help help for the loader driver To obtain a help screen for the AD SP 2191 processor type elfloader proc ADSP 2191 h host3bytes Uses three bytes to represent 24 bit data The default is four bytes with one byte of zero padding Note Used with H ost boot only when width is 8 bit M Shows dependencies only MM Generates make dependencies while producing the output files VisualD SP Loader M anual 3 21 ADSP 219x DSP Loader Guide Table 3 6 Loader Command Line Switches Cont d Switch Description Mo filename Writes make dependencies to the named specified The Mo option is for use with either the M or MM option If Mo is not present the default is lt stdout gt display Mt targetname Specifies the make dependencies target name The Mt option is for use with either the M or MM option If Mt is not present the default is the name of the input file with the DoJ extension maskaddr M asks al
93. he incoming byte is not a zero the on chip boot ROM sends another byte 0x00 and verifies if the incoming byte is a zero The last byte is a zero when a 24 bit addressable SPI memory device is connected VisualD SP Loader M anual for 16 Bit Processors Blac kfin Processor Loader Splitter The miso line must be pulled high for BmMope 11 Since the miso lineis pulled up high the processor receives one of the following Aoxrr if the part is not responding back with valid data e A 0x00 if the part is responding back with valid data T he boot uses Slave Select 2 that maps to PF2 The on chip boot ROM sets the Baud Rate register to 133 which based on a 133 M Hz system clock results in a 133 M H z 2 133 2500 kHz baud rate Analog D evices recommends the following SPI memory devices e 8 bit addressable SPI memory 25LC 040 from M icrochip http www microchip com download lit pline mem ory spi 21204c pdf e 16 bit addressable SPI memory 25CL 640 from M icrochip http www microchip com download lit pline mem ory spi 21223e pdf e 24 bit addressable SPI memory M 25P80 from ST M icroelectronics http www st com stonline books pdf docs 8495 pdf VisualD SP Loader M anual 2 27 for 16 Bit Processors Blackfin Proc essor Booting ADSP BF561 Processor Booting T he booting sequence for the AD SP BF561 dual core processor is similar to theAD SP BF531 BF532 BF533 processor booting sequence described on
94. heRTBL isa driveimplemented by the user the RTBL is responsible for transporting the loadable executable into the D SP Visu alD SP includes a reference RT BL that can be used to boot load an AD SP 2192 12 EZ KIT Lite evaluation system on Windows 98 and W indows 2000 platforms You can run the loader from a command line or directly from within the VisualD SP ID DE When working from the V isualD SP specify the loader options via the Load page of the Project O ptions dialog box O ption setting on the Load page correspond to switches displayed on the command line T o ensure correct operation of the loader familiarize yourself with e ADSP 2192 DSP Reset T ypes on page 4 2 e ADSP 2192 DSP RTBL on page 4 4 ADSP 2192 DSP RBTL and O verlays on page 4 8 ADSP 2192 DSP Reset Types The AD SP 2192 D SP supports booting via the PCI interface or the U SB interface Theinternal ROM includes a small boot kernel program which determines how the D SP boots 4 2 VisualD SP Loader M anual for 16 Bit Processors ADSP 2192 12 DSP Loader U pon recovering from reset the AD SP 2192 DSP jumps to the first location of the boot ROM at address 0x14000 which is the start of the boot kernel The first task performed by the kernel is to determine the type of RESET and the source of booting PCI or USB The kernel then sets up and initializes appropriate D SP registers to facilitate the booting T hree methods for resetting the A
95. hen download those structures to the target through a driver The reference RT BL provided with the EZ KIT Lite evaluation System does not support U SB booting VisualD SP Loader M anual 4 7 for 16 Bit Processors ADSP 2192 DSP Booting The EZ KIT Lite evaluation system driver can be reused for targets other than Analog D evices EZ KIT Lite evaluation systems but this simple driver may be inadequate for anything other than prototyping Further more the EZ KIT Lite driver can be reused only on so called plug and play W indows operating systems like Windows 98 and W in dows 2000 ADSP 2192 DSP RBIL and Overlays U sing overlays in an executable can greatly complicate the use of the RTBL and PCI driver for two main reasons e Theoverlay s live space ison the PC host and not the D SP Asa result the linker is not aware of these addresses at build time The PCI driver must patch executables as they are downloaded to the D SP to insert the correct addresses at runtime TheDSP cannot access the W indows virtual memory space An overlay must be copied from virtual memory spaceto PCI memory space which can only be allocated in limited quantities by the PCI driver H owever the loader output considers the need for run time patches of the executable A portion of the data structure created by the loader isfor the express purpose of enabling user code in the RT BL to set up these addresses at runtime Refer to the reference
96. ile for 16 bit PRO M Flash booting without the sec ond stage loader Output LDR File Byte Count for 2nd Stage Loader Application Code N words D15 D8 D7 DO An output loader file for 8 bit PROM Flash booting and 8 or 16 bit addressable SPI booting with the second stage loader or kernel Output LDR File 4 Byte Count for 2nd Stage Loader 4 2d Stage Loader N Bytes Application 4 Code in blocks 2 10 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter An output loader file for 16 bit PROM FLASH booting with the sec ond stage loader or kernel Output LDR File Byte Count for 2 d Stage Loader 4 2 4 Stage Loader Application 4 Code in blocks D15 D8 D7 DO Global H eaders and Blocks Following kernel code and kernel address in a loader file there is a 4 byte global header T he header provides the global settings for a booting process Output LDR File Byte Count for 4 Bytes 2nd Stage Loader N Bytes 4 Bytes Address of the Bottom of L2 Memory from which 2 4 Stage Loader runs 4 Bytes See Global Header 4 Bytes N1 Bytes VisualD SP Loader M anual 2 11 for 16 Bit Processors Blackfin Proc essor Booting A block is the basic structure of the output Lor file for application code when the second stage loader is used All the application code is grouped into blocks A block always has a
97. in Proc essor Booting AD SP BF561 Multiple D XE Booting A typical dual core application is separated into two executable files one for each core T he default linker description files LD Fs for the AD SP BF561 processor creates two separate executable files po dxe and p1 dxe and some shared memory files sm12 sm and sm13 sm By modify ing the LDF itis possibleto create a dual core application that combines both cores into a single pxe file This is not recommended unless the application is a simple assembly language program which does not link any C runtime libraries W hen using shared memory and or C runtime routines on both cores it is best to generate a separate xt file for each core T heloader combines the contents of the shared memory files sm12 sm sm13 sm into the pxe file for coreA po dxe The boot ROM only loads one single executable beforethe ROM jumps to the start of core A instruction SRAM oxFFAO 0000 When two DXEs must be loaded a second stage loader should be used T he second stage boot loader must start at oxrrAo 0000 Theboot ROM loads and executes the second stage loader A default second stage loader is provided for each boot mode and can be customized by the user U nlike the initialization block the second stage loader takes full control over the boot process and never returnsto the boot ROM T he second stage loader can use the pxe byte count blocks to find spe cific pxE sin external memory
98. ing code on both cores the core A program is responsi ble for releasing core B from the idle state by clearing bit 5 in core A s System Configuration Register T hen core B begins execu tion at address oxrreo 0000 M ultiple oxe files are often combined into a single boot stream VisualD SP Loader M anual 2 29 for 16 Bit Processors Blackfin Proc essor Booting Unlike the AD SP BF531 BF532 BF533 processor the AD SP BF561 boot stream begins with a 4 byte global header which contains informa tion about the external memory device T he global header also contains a signature in the upper 4 bits that prevents the boot ROM from trying to read a boot stream from a blank device Table 2 6 AD SP BF561 Global H eader Structure Bit Field D escription 0 1 16 bit Flash 0 8 bit Flash default is 0 1 4 Number of wait states default is 15 5 Unused bit 6 7 Number of hold time cycles for Flash default is 3 8 10 Baud rate for SPI boot 00 500k 01 2 1M 10 2M 11 27 Reserved for future use 28 31 Signature that indicates valid boot stream Following the global header isa pxe count block which contains a 32 bit byte count for the first bxe in the boot stream T hough this block con tains only a byte count it is encapsulated by a 10 byte block header just like the other blocks T he 10 byte header tells the boot ROM where in memory to place each block how many bytes to copy and whethe
99. ing the page controls you can select or modify the loader settings T able 2 10 describes each loader control and corresponding setting W hen you are satisfied with default settings click OK to complete the loader setup Table 2 10 Base Loader Page Settings Setting Description Category Selections in the drop down box display panes of options The options are Loader options default booting options this section Boot kernel options specification for a second stage loader see on page 2 49 ROM splitter options specification for the no boot mode see on page 2 51 If you do not usethe boot kernel for AD SP BF535 processors the second Load pane appears with all kernel option fields grayed out T he loader does not search for the boot kernel if you boot from the on chip ROM by setting the no2kernel command line switch as described on page 2 45 For ADSP BF531 BF532 BF533 and AD SP BF561 processors which do not have software boot kernels by default you need to select the boot kernel to use one Boot mode Specifies PRO M Flash or SPI as a boot source Boot format Specifies Intel hex ASCII or binary formats O utput width Start address Specifies 8 or 16 bits If BMODE 01 or 001 and Flash PROM is 16 bit wide the 16 bit option must be selected Specifies a PRO M Flash output start address in hex format for the application code Verbose G enerates status information as
100. it Processors 2 39 Blackfin Processor Loader Guide Blackfin Processor Loader Guide Loader operations depend on the loader options which control how the loader processes executable files letting you select features such as boot mode boot kernel and output file format T hese options are specified on the loader s command line or via the Load page of the Project O ptions dialog box in the VisualD SP environment T he Load page consists of multiple panes and is the same for all Blackfin processors W hen you open the Load page the default loader settings for the selected processor are already set O ption settings on the Load page correspond to switches displayed on the command line T hese sections describe how to produce a bootable or non bootable loader file LDR e Using Loader Command Line on page 2 40 Using Base Loader on page 2 47 e Using Second Stage Loader on page 2 49 Using ROM Splitter on page 2 51 Using Loader Command Line T he Blackfin loader uses the following command line syntax For a single input file elfloader sourcefile proc processor switch For multiple input files elfloader sourcefilel sourcefile2 proc processor switch ml 2 40 VisualD SP Loader M anual for 16 Bit Processors where D Blackfin Processor Loader Splitter sourcefile N ame of the executable file DxE to be processed into a single boot loadable or non bootablefile An input filename can
101. kernel file at a specific location within the Flash PRO M in the loader file 7 For AD SP BF535 processors only modify the Wait states and H old time cycles for Flash PROM booting or the Baud rate for SPI booting 8 Click OK to complete the loader setup Using ROM Splitter Unlike the loader utility the splitter does not format the application data when transforming an oxe file to an Lor file It emits raw data only W hether data and or instruction segment are processed by the loader or VisualD SP Loader M anual 2 51 for 16 Bit Processors Blackfin Processor Loader Guide splitter utility is controlled by the LDF s Type command Segments declared with TyPE RAM are consumed by the loader utility and segments declared by rvPE CROM are consumed by the splitter Figure 2 16 shows an example ROM splitter options pane of the Load page With the Enable ROM splitter box unchecked only TYPE RAM seg ments are processed and all TyPE ROM segments are ignored by the elfloader utility If the box is checked rvPE RAM segments are ignored and rYPE ROM segments are processed by the splitter utility Project Options Project General VIDL Compile Assemble Link Load K gt Category ROM splitter options Y v Enable ROM splitter romsplitter b Format Dutput Width Mask address Hex 8bit maskaddr width C ASCII C 16 bit Dutput file Additional options
102. l EPROM address bits above or equal to For example maskaddr 18 masks all the bits above and including A18 AN D ed by 0x3FFFF T he switch does not require romsplitter and affects ROM section address only NoDxeAddrHdr D oes not generate the address header in the loader stream for the input DXE file o filename Specifies the name of the output file If no filename is specified the output file takes the name of the input file T he extension is LDR For multi DXE processing when the o 7ename 1dr is specified inside the pd grouping the file relative byte address that is the value in the address portion of the Intel hex information is set to zero The value of zero is the default value but also can be set by PEqualZero T he value can be set to the value provided to the pd switch specified by the PEqua1PD switch Further it also can be set by specifying a p argument within the pd grouping See AD SP 219x D SP M ultiple DXE Support on page 3 7 and pd address inputfile for more information on pd groupings opmode Specifies whether the boot kernel sets the D SP to 3 SPO RT mode 0 or 2 SPORT 1 SPI mode 1 at the end of booting D efault is 0 p address Specifies a hexadecimal integer as the PRO M starting address For multi DXE processing if p is specified in the pd group a new LDR file must be created using o in the same pd group See o file name and pd address i
103. lue is between 0x0 OxFFFFFFFF A specified value must be greater than that specified by kp if both kernel and or ini tialization and application code are in the same output file do not Use 02 proc processor Specifies the target processor The processor can be one of the following ADSP BF531 ADSP BF532 ADSP BF533 ADSP BF535 and ADSP BF561 romsplitter Creates a non bootable image only T his switch overwrites the b switch and any other switch bounded by the boot modes Note In the LDF file declare memory segments to be splitted as type ROM T he splitter skips RAM segments resulting in an empty fileif all segments are declared as RAM The romsplitter switch supports hex and ASCII formats VisualD SP Loader M anual 2 45 for 16 Bit Processors Blackfin Processor Loader Guide Table 2 9 Blackfin Loader Command Line Switches C ont d Switch Description ShowEncryptionMessage Displays a message returned from the encryption function si revision version Provides a silicon revision of the specified processor The version parameter represents a silicon revision of the processor specified by the proc switch T he revision version takes one of two forms e Oneor more decimal digits followed by a point followed by one or two decimal digits Examples of revisions are 0 0 1 12 23 1 Version 0 1 is distinct from and lower than version 0 10
104. mation on macros and other preprocessor commands see the Visu alD SP 3 5 Assembler and Preprocessor M anual for 16 Bit Processors Linker Desc nption Files Linker Description Files LoF are ASCII text files that contain commands for the linker in the linker s scripting language For information on this scripting language see the VisualD SP 3 5 Linker and Utilities M anual for 16 Bit Processors A 4 VisualD SP Loader M anual for 16 Bit Processors File Formats Linker Command Line Files Linker command line files rxr are ASCII text files that contain command line input for the linker For more information on the linker command line see the VisualD SP 3 5 Linker and Utilities M anual for 16 Bit Processors Build Files Build files are produced by the VisualD SP development tools while building a project T his section describes the following build file formats e Assembler O bject Files on page A 5 e Library Files on page A 6 Linker Output Files on page A 6 Memory MapFiles on page A 7 Loader Output Files in Intel H ex 32 Format on page A 7 e Splitter O utput Filesin ASCII Format on page A 9 Assembler Object Files Assembler output object files 500J are binary executable and linkable files ELF O bject files contain relocatable code and debugging informa tion for a DSP program s memory segments T he linker processes object files into an executable file xe For information on
105. matting the output Lor file according to user specifications Supported formats are binary ASCII hex 32 and more Valid file formats are described in Appendix A on page A 1 Packing the code for a particular data format 8 or 16 bit e If specified adding a boot kernel on top of the user code f specified preprogramming the location of the Lor filein PROM space e Specifying processor ID s for multiple input oxes for a multipro cessor system Loader Files T he loader splitter output is essentially the same executable code as in the input oxe file T he loader repackages the executable as illustrated in Figure 1 1 Processor code in a loader fileis split into blocks Each code block is marked with a tag that contains information about the block such as a number of words or destination in processor s memory D epending on the processor family there may be additional information in the tag C om mon block types are zero memory is filled with 0s non zero code or data and final code or data D epending on the processor family there may be other block types 1 8 VisualD SP 3 5 Loader M anual for 16 Bit Processors Introduction DXE File LDR File A DXE file includes Gesla An LDR file includes Symbol table and section DSP instructions code and Target processor s memory Rudimentary formatting layout Degugging information All of the debugging information Code instructions I J has been taken out
106. nary If the f switch does not appear on the command line the default boot mode format is hex for Flash PROM and ASCII for SPI 2 42 VisualD SP Loader M anual for 16 Bit Processors Blac kfin Processor Loader Splitter Table 2 9 Blackfin Loader Command Line Switches Cont d Switch Description h Invokes the command line help outputs a list of command line or switches to standard output and exits By default the h switch alone help provides help for the loader driver To obtain a help screen for your target Blackfin processor add the proc switch to the command line For example type elfloader proc ADSP BF535 hto obtain help for the AD SP BF535 processor ghc Specifies a 4 bit value global header cookie for bits 31 28 of the global header HoldTime Allows the loader to specify a number of hold time cycles for PRO M Flash boot T he valid values are from 0 through 3 The default valueis 3 Note Currently supported only for AD SP BF535 processors init filename Directs the loader to include the initialization block from the named file The loader places the code from the initialization section of the specified DXE filein the boot stream T he kernel loads the block and then calls it It is the responsibility of the code within the block to save restore state registers and then perform a RT S back to the ker nel Note T his switch cannot be applied to AD SP BF535 p
107. ned into an external memory device within your target system A splitter generates non bootable PRO M image files by processing exe cutable files and producing an output PROM file A non bootablePRO M image file executes from D SP external memory A 6 VisualD SP Loader M anual for 16 Bit Processors File Formats Memory Map Files The linker can output memory map files mapP which are ASCII text files that contain memory and symbol information for your executable file s T he map contains a summary of memory defined with MEMORY com mands in the Lor file and provides a list of the absolute addresses of all symbols Loader Output Files in Intel Hex 32 Format T he loader can output Intel hex 32 format files LDR The files support 8 bit wide PRO M s and are used with an industry standard PROM pro grammer to program memory devices O ne file contains data for the whole series of memory chips to be programmed T he following example shows how the Intel hex 32 format appears in the loader s output file Each linein the Intel hex 32 file contains an extended linear address record a data record or the end of file record 020000040000FA Extended linear address record 0402100000FE03FO0F9 D ata record 00000001FF End of file record Extended linear address records are used because data records have a 4 character 16 bit address field but in many cases the required PRO M size is greater than or equal to oxrrrr bytes
108. ng of on chip L2 memory 001 Use boot ROM to load or the beginning of ASYNC Bank 0 from 8 bit 16 bit FLASH when BMODEQ 2 0 b 000 010 Use boot ROM to configure and load boot code from SPIO serial ROM 8 bit address range 011 Use boot ROM to configure and load boot code from SPIO serial ROM 16 bit address range 100 111 Reserved Figure 2 3 AD SP BF535 Processors System Reset Configuration Register 3 Finally if bit 4 of the syscr register is not set the on chip boot ROM performs the full boot sequence T he full boot sequence includes v Checking the boot source either Flash PROM or SPI mem ory by reading BM0DE 2 0 from the syscr register v Reading the first four bytes from location 0x0 of the exter nal memory device T hese four bytes contain the byte count N which specifies the number of bytes to boot in v Booting in n bytes into internal L2 memory starting at loca tion 0xF000 0000 v Jumping to the start of L2 memory for execution Theon chip boot ROM boots in n bytes from the external memory T hese N bytes can define the size of the actual application code or a second stage loader boot kernel that boots in the application code VisualD SP Loader M anual 2 5 for 16 Bit Processors Blackfin Proc essor Booting ADSP BF535 Processor Second Stage Loader The only situation where a second stage loader is unnecessary is when the application code contains only one section starting at the
109. nputfile for details pEqualPd U sed inside the pd address inputfile grouping Sets the default value for p when o specified in the pd group is the value of the argument to pd pEqualZero U sed inside the pd address inputfile grouping Sets the default value for p when o specified in the pd group is zero default behavior 3 22 VisualD SP Loader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter Table 3 6 Loader Command Line Switches Cont d Switch Description pd address Appends another application program DXE at the specified address inputfile You can specify options applicable to the boot stream general header between address and inputfile f no pd address is specified application starts from the next free PROM location T hereisno restric tion on the number of time the switch is used pdAddrNext Specifies the value contained in the D XE address header block W hen elfloader is invoked multiple times to create loader files this option specifies the next address to be placed in the new header record for the last DXE on the command line T he address is in the byte based PRO M address space proc processor or dADSP 21xx readall T he mandatory switch specifies the processor for which the loader fileis created For example proc ADSP 2191 or proc ADSP 21990 Note proc ADSP 21xx isthe preferred form dADSP 21xx is for leg
110. o output file is specified the default output file is named p0 h File Searches M any loader switches take a file name as an optional parameter T able 4 4 on page 4 13 lists types the loader expect on files File searches are impor tant in the loader operation T he loader supports relative and absolute directory names default directories File searches occur as follows Specified path If you include relative or absolute path informa tion in a file name the loader searches only in that location for the file Default directory If you do not include path information in the file name the loader searches for the file in the current working directory W hen you provide an input or output file name as a command line parameter use the following guidelines Encloselong file names within straight quotes 1ong file name Append the appropriate file extension to each file 4 12 VisualD SP Loader M anual for 16 Bit Processors ADSP 2192 12 DSP Loader File Extensions T able 4 3 lists and describes file types input and output by the loader Table 4 3 AD SP 2192 D SP Loader File Extensions File Extension D escription DXE Executable files 0VL O verlay memory files T he loader recognizes overlay memory files but does not expect these files on the command line Place ovL filesin the same directory as the DXE file that refers to them the loader can locate them when processing the DXE
111. oader core0 sourcefileO corel sourcefilel proc ADSP 2192 switch where e core0 sourcefile0 Identifies the sourcefileo asthe input file to process for core 0 T heloader creates the array and structure names according to the supplied core number Before running the loader ensure that all ovL and sm filesresidein the same working directory as the executables T he loader automatically opens the overlay and shared memory files to read in the data while process ing the executables e corel sourcefilel Identifies the sourcefite1 asthe input file to process for core 1 The loader utility creates the array and struc ture names according to the supplied core number proc ADSP 2192 T he mandatory switch produces an output file for the AD SP 2192 12 processor By default the output fileisa C language header file 4 e switch Oneor more optional switches to pass to the loader Command line switches may be placed in any order VisualD SP Loader M anual 4 11 for 16 Bit Processors ADSP 2192 DSP Loader Guide Example elfloader proc ADSP 2192 coreO p0 dxe corel pl dxe This command line runs the loader utility with e proc ADSP 2192 Directs the loader to produce an output file for the AD SP 2192 12 processor e core0 p0 dxe Identifies the input file po dxe to be processed for core 0 e corel pl dxe Identifies the input file p1 dxe to be processed for core 1 By default since n
112. oader processes the input files in order the files appear on the com mand line starting with the one from the project Using Second Stage Loader If you to use a second stage loader select Boot kernel options in the C at egory drop down menu T he page shows how to configure the loader for boot loading and to output file generation using the boot kernel Figure 2 15 shows an example boot kernel Load pane for a Blackfin processor T o create a loader file which includes a second stage loader 1 Usethe Loader options pane to set up base booting options see U sing Base Loader on page 2 47 2 Select Boot kernel options from the Category drop down box to open the second Load pane with the second stage loader settings shown in Figure 2 15 VisualD SP Loader M anual 2 49 for 16 Bit Processors Blackfin Processor Loader Guide Project Options Project General VIDL Compile Assemble Link Category Boot kernel options Y v Use boot kernel v Output kemel in seperate file Load Lebl 02 kb Boot mode Boot format Output width Start address PROM Intelhex amp bit kp Se C Flash ASCII C 16 bit kwidth C SPI Binary Kernel file C Program Files Analog Devices WisualDSP 3 5 16 Bi Blac pu l filename Additional options oooO Figure 2 15 AD SP BF53x Processors Boot Kernel Pane 3 Select
113. of the file Debug Information Debug Information Figure 1 1 D XE Files versus LDR Files File Searc hes File searches are important in the loader operation T he loader supports relative and absolute directory names default directories File searches occur as follows Specified path If you include relative or absolute path informa tion in a filename the loader searches only in that location for the file Default directory If you do not include path information in the file name the loader searches for the file in the current working directory Overlay and shared memory files the loader recognizes overlay memory files but does not expect these files on the command line Place the files in the same directory as the executable file that refers to them T he loader can locate them when processing the executable VisualD SP 3 5 Loader M anual 1 9 for 16 Bit Processors Loader Files W hen providing an input or output file as a loader splitter command line parameter use the following guidelines e Enclose long file names within straight quotes long file name Append the appropriate file extension to each file 1 10 VisualD SP 3 5 Loader M anual for 16 Bit Processors 2 BLACKFIN PROCESSOR LOADER SPLITTER This chapter explains how the loader splitter program e1floader exe is used to convert executable files 0x into boot loadable or non bootable files for the AD SP BF 5xx Blackfin
114. or H ardware Reference manual for more information on system configura tion peripherals registers and operating modes You can run the loader splitter program from a command line or from within the VisualD SP ID DE When working within the VisualD SP specify options via the Load page of the Project O ptions dialog box O ption setting on the Load page correspond to switches displayed on the command line T o ensure correct operation of the loader familiarize yourself with e ADSP 219x DSP Boot M odes on page 3 3 e ADSP 219x DSP Boot Kernel on page 3 4 e ADSP 219x DSP Boot Streams on page 3 4 Parallel EPROM Boot Streams on page 3 4 Host Booting on page 3 10 UART Booting on page 3 11 Serial EPROM Booting on page 3 12 e No booting on page 3 12 3 2 VisualD SP Loader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter ADSP 219x DSP Boot Modes At powerup after the reset the processor transitions into a boot mode sequence configured by the BMopE2 0 pins T he B amp Mobt pins are dedicated mode control pins the pin states are captured and placed in the Reset Configuration register as BMODEO BMODE1 and opmoDE see T able 3 1 The register is also known as the System Configuration Register syscr with I O address 0x0 0204 Table 3 1 AD SP 219x D SP O peration M odes BMODE1 BMODEO OPMODE Description Pin Pin Pin 0 0 0 N o boot mode Run from ex
115. ormation 5 14 VisualD SP 3 5 Loader M anual for 16 Bit Processors ADSP 218x DSP Loader Splitter ADSP 218x DSP Splitter Guide Use the splitter e1fsp121 exe to process an executable file to produce a non bootable PRO M image file n most cases developers working with AD SP 21xx D SPs usethe loader instead of the splitter T his section contains the following information on the splitter Using Splitter on page 5 15 D escribes how to usethe splitter from a command line ADSP 218x Splitter Command Line Reference on page 5 16 Summarizes and describes the splitter command line switches Using Splitter You must run the splitter PROM splitter from a command line You cannot generate a non bootable PROM filefrom within the VisualD SP environment T o automate the process specify the splitter command line within VisualD SP from the Post Build page of the Project O ptions dialog box The AD SP 218x splitter generates images for external pmovLay 1 and 2 and pmovLay 1 and 2 memory pages If you use the splitter to produce ROM images for example the AD SP 2181D SP s program memory pages 1 and 2 the generated code must target RO M D efine the appropriate ROM segmentsin the Lor file Splitter options control how the splitter processes executable files letting you select features such as memory type and file format VisualD SP 3 5 Loader M anual 5 15 for 16 Bit Processors ADSP 218x DSP Splitter Gui
116. ot routine Refer to the Application N ote EE 145 for SPI booting examples No booting W hen amp wopt2 0 is strapped to a 000 or 001 the AD SP 219x D SP comes out of hardware reset and begins to execute code from page 1 memory Space 0xo1 0000 T he specified packing mode depends on the state of the BMoDEO pin 0 8 bit ext 24 bit int 1 2 16 bit ext 24 bit int By default the External Port Interface EPI is configured to operate with the divide by 128 clock and a read wait state count of 7 N o boot mode does not use boot stream format After reset the D SP starts program execution from external address 0x010000 W hen the no boot option is selected the D SP typically expects an 8 or 16 bit EPROM or Flash device connected to the memory strobe 3 12 VisualD SP L oader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter signal mso Splitter capabilities of the AD SP 219x loader utility support the generation of the required EPROM image files Refer to the loader s romsplitter switch see on page 3 23 for more information N on bootable memory segments are declared by the TyPE ROM command in the Linker D escription File LoF ThewrprH command specifies the physical EPROM width which equals to the EM I port setting Every LDF file that belongs to a no boot project should define a proper memory segment as in the following example MEMORY seg ext code TYPECPM ROM START 0x010000 END OXO17FFF
117. output files 2 46 5 8 5 10 5 16 overlays live address table 4 9 pages AD SP 218x D SPs 5 7 start address 4 9 O vIM grT bl symbol 4 9 O vIPciAdrT bl symbol 4 9 P p loader switch 2 45 3 22 page loaders 5 6 5 10 PCI drivers run time boot loader 4 8 pd loader switch 3 23 pdAddrN ext loader switch 3 23 INDEX pEqualPd loader switch 3 22 pEqualZero loader switch 3 22 pm memory 5 7 5 11 pm splitter switch 5 18 PM OVLAY memory page 5 15 power ups 1 5 preloader 5 10 preloaders AD SP 218x D SPs 5 6 proc loader switch 2 45 3 23 4 14 processor blocks 2 21 processor loadable files 1 5 program development flow 1 1 program memory pm 5 17 Project O ptions dialog box 2 47 5 2 5 6 5 15 PROM booting 2 6 2 9 2 14 2 47 booting mode 1 6 image 5 2 5 6 5 16 5 18 memory 1 3 1 7 2 29 5 3 splitter 5 1 5 15 PROM Flash booting 2 12 memory 2 28 R RO register 2 35 R3 register 2 35 RAM memory 5 18 READ command 2 26 readall loader switch 3 23 splitter switch 5 18 references VisualD SP Loader M anual for 16 Bit Processors INDEX file formats A 10 reset 2 2 2 3 2 16 5 2 5 6 5 11 AD SP 2192 D SPs 4 3 RESET interrupt 2 17 2 28 ROM images 5 15 memory 5 18 ROM splitter Setting options 2 52 romsplitter loader switch 2 45 3 23 RT BL see run time boot loader 4 6 run time boot loader 4 2 creating 4 7 handling overlays 4 9 overlays over PCI 4 8 reference 4 7 running 4 6 S S lo
118. pecifies the make dependencies target name The mt option is for use with either the M or MM option If Mt is not present the default is the name of the input file with the LDR extension o file proc ADSP 2192 or dADSP2192 Specifies the name of the output file Produces an output file for the AD SP 2192 12 processor Note proc ADSP 2192 is the preferred form T he dADSP2192 Switch is for legacy support only si revision version Provides a silicon revision of the specified processor The version parameter represents a silicon revision of the processor specified by the proc switch T he revision version takes one of two forms e Oneor more decimal digits followed by a point followed by one or two decimal digits Examples of revisions are 0 0 1 12 23 1 Version 0 1 is distinct from and lower than version 0 10 The digits to the left of the point specify the chip tapeout number the digits to the right of the point identify the metal mask revision number T he number to the right of the point can not exceed decimal 255 A none version value is also supported indicating that the VDSP tool should ignore silicon errata T his switch either generates a warning about any potential anomalous conditions or generates an error if any anomalous conditions occur Note In the absence of the silicon revision switch the loader selects the greatest silicon revision it is aware of if any Note In the ab
119. r ated by the e1fsp121 utility automatically determine the BWCOUNT value which mirrors the numbers of instructions required by the page loaders Customized preloaders do not have access to this length infor mation and should always set BWCOUNT by assuming the maximal possi ble page loader length In this software version the maximal number of instructions required for the page loader is 658 T his may change in future releases offsetaddr Provides byte memory address offset valid only with 2181 noloader or with 218x noloader offsetpage Provides byte memory page offset valid only with 2181 noloader or with 218x noloader Host Booting IDMA W hen booted through the ID M A interface an AD SP 218x D SP behaves like a slave After reset it does not start program execution until internal PM location 0x0000 is overwritten by an ID M A write access T he host processor initializes all on chip memories of the D SP but finally writes to PM address 0x0000 T hen the D SP starts program execution T he host is responsible for handling the ID M A traffic properly Typically the host boots the D SP page by page segment by segment T o boot a segment the host first performs an address latch cycleto program the IDMA Control register and the ID M A Overlay register on AD SP 2184 through AD SP 2189 D SPsonly Afterwards the host writes 16 or 24 bit words to the ID M A port T he D SP auto increments its addr
120. r Boot Streams on page 2 8 e ADSP BF535 Processor M emory Ranges on page 2 13 VisualD SP Loader M anual 2 3 for 16 Bit Processors Blackfin Processor Booting ADSP BF535 Processor On Chip Boot ROM The on chip boot ROM for the AD SP BF535 processor does the follow ing Figure 2 2 ADSP BF535 Processor PROM Flash or SPI Device Figure 2 2 AD SP BF535 Processors O n Chip Boot ROM 1 Sets up Supervisor mode by exiting the RESET interrupt service rou tine and jumping into the lowest priority interrupt 1v615 2 Checks whether the RESET was a software reset and if so whether to skip the entire boot sequence and jump to the start of L2 memory 0xF000 0000 for execution T he on chip boot ROM does this by checking bit 4 of the syscr If bit 4 is not set the on chip boot ROM performsthe full boot sequence If bit 4 is set theon chip boot ROM bypasses the full boot sequence and jumps to 0xrooo 0000 T he register settings are shown in Figure 2 3 2 4 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter System Reset Configuration Register SYSCR X state is initialized from mode pins during hardware reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DTP TESTIS TS ISTSTSTS Je dependent on pin ae No Boot on Software Reset BMODE 2 0 RO 0 Use BMODE to determine 000 Bypass boot ROM boot source execute from 16 bit wide Start executing from the external memory beginni
121. r data initialization the assembler reads the data file and initializes the buffer in the output object file dou D ata files have one data value per line and may have any number of lines The paAT extension is explanatory or mnemonic A directive to include lt file gt can take any file name and extension as an argument Fixed point values integers in data files may be signed and they may be decimal hexadecimal octal or binary base values T he assembler uses the prefix conventions listed in T able A 1 to distinguish between numeric formats For all numeric bases the assembler uses 16 bit words for data storage 24 bit data is for the program code only T he largest word in the buffer determines the size for all words in the buffer If you have some 8 bit data VisualD SP Loader M anual A 3 for 16 Bit Processors Source Files in a 16 bit wide buffer the assembler loads the equivalent 8 bit value into the most significant 8 bits into the 8 bit memory location and zero fills the lower eight bits Table A 1 Numeric Formats Convention D escription Oxnumber H exadecimal number Hi tnumber ifnumber number Decimal number D tnumber d number Bitnumber Binary number b number OfFnumber Octal number of number Header Files H eader files H are ASCII text files that contain macros or other prepro cessor commands which the preprocessor substitutes into source files For infor
122. r s external memory bypassing the build in boot mechanisms Preparing a non boota ble EPROM imageis called splitting In most cases developers working with 16 bit processors use the loader instead of the splitter A processor s booting sequence and an application program s design dic tate the way you call the loader splitter programs to consume and transform executables For 16 bit processors splitter and loader features are handled by a single program T he splitter is invoked by a completely different set of command line switches than the loader Refer to the guide sections of the following chapters for information about splitting 1 4 VisualD SP 3 5 Loader M anual for 16 Bit Processors Introduction Booting Modes A fully debugged program can be automatically downloaded to the proces sor after power up or after a software reset T his process is called booting T he way the loader creates a boot loadable file depends upon how your program is booted into the processor Oncean executable is fully debugged it is ready to be converted into a processor loadable file T he exact boot mode of the processor is determined by sampling one or more of input flag pins Booting sequences highly processor specific are detailed in the following chapters AD SP 218x AD SP 219x and Blackfin processors support different boot mechanisms G enerally spoken the following schemes can be used to pro vide program instructions to the processo
123. r the block needs any special processing T he header structure is the same as that of the AD SP BF531 BF532 BF533 processors described in Blocks and Block H eaders on page 2 19 Each header contains a 4 byte start address for the data block a 4 byte count for the data block and a 2 byte flag word indicating whether the data block is a zero fill block or a final block the last block in the boot stream 2 30 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter For the pxe count block the address field is irrelevant since the block is not going to be copied to memory T he ignore bit is set in the flag word of this header so the boot loader does not try to load the pxe count but skips the count For more details see Flags of Block H eader on page 2 20 Following the oxe count block are the rest of the blocks of the first DxE A bit by bit description of the boot steam is presented in T able 2 7 W hen learning about the AD SPP BF561 boot stream structure keep in mind that the count byte for each pxe is itself a block encapsulated by a block header Table 2 7 AD SP BF561 Processor Boot Stream Structure Bit Field D escription 0 7 LSB of the Global H eader 8 15 8 15 of the Global H eader 16 23 16 23 of the Global H eader 24 31 M SB of the Global H eader 32 39 LSB of the address field of 1st D XE coun
124. rce the sources areany PM or DM ROM memory segments Because no other contents switches appear on these command lines the format for the output defaults to M otorola S3 format and the output PROM width defaults to 8 bits for all PRO M s pm stuff dm stuff Specify names for the output files without file extension U se dif ferent names so the output of the second run does not overwrite the output of the first run The output names are pm stuff s 4 and dm stuff s 4 my proj dxe Specify an executable file to process into a non bootable PROM image file File Searches M any splitter switches take a file name as an optional parameter T able 5 7 lists the type of files names and extensions that the splitter expects on files File searches are important in the splitter s process T he splitter supports relative and absolute directory names default directories and user selected directories for file search paths W hen you provide an input or output file name as a command line parameter use the guidelines stated on page 1 9 Splitter File Extensions T able 5 7 lists and describes file types input and output by the splitter VisualD SP 3 5 Loader M anual 5 17 for 16 Bit Processors ADSP 218x DSP Splitter Guide Table 5 7 Splitter File Name Extensions File Extension File D escription DXE Executable files and boot kernel files BNU Splitter binary output file upper BNM Splitter binar
125. ritical parts of the program directly from the EPROM whereas real time algorithms have been booted into on chip memory W hen invoked with the reada11 switch on page 3 23 the loader pro cesses all kinds of LDF segments tyPE RAM segments are passed to the loader s boot stream generator and TyPE ROM segments are passed to its splitter Boot stream and splitter data can be combined within a single EPROM image Assuming a cost sensitive application comprising an AD SP 2196 D SP and a 64 K byte EPROM the boot stream probably does not exceed 40 kilobytes 8K x 3 bytes 8K x 2 bytes of length T he rest of the EPROM can be used to store different sets of coefficients and the slow ini tialization and control code A reasonable organization of the 8 bit EPROM is described in T able 3 4 Since the D SP cannot access off chip memories with addresses lower than 0x010000 it needs to access segments seg ext data and Seg ext code through alias windows If only address lines AO through A15 are con nected address 0x00 A000 aliases to any 0x00 A000 address Segment seg ext data Stores 16 bit data T hus its physical addresses must be 3 16 VisualD SP Loader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter Table 3 4 EPROM Image With No boot D ata Address range Purpose 0x000000 0x009FFF Boot stream 0x00A000 0x00AFFF seg ext data External read only data 0x00B000 0x00FFFF seg ext code Ex
126. rmat us Produces a byte stacked format file for 8 bit memory us2 us yields M otorola S1 output format ui us2 yields M otorola S2 output format ui yields Intel hex output format VisualD SP 3 5 Loader M anual 5 19 for 16 Bit Processors ADSP 218x DSP Splitter Guide 5 20 VisualD SP 3 5 Loader M anual for 16 Bit Processors A FILE FORMATS VisualD SP development tools support many file formats in some cases several for each development tool T his appendix describes file formats that are prepared as inputs and produced as outputs T he appendix describes three types of files e Source Files on page A 2 Build Files on page A 5 Debugger Files on page A 9 M ost of the development tools use industry standard file formats T hese formats are described in Format References on page A 10 VisualD SP Loader M anual A 1 for 16 Bit Processors Source Files Source Files T his section describes the following input file formats e C C Source Files on page A 2 Assembly Source Files on page A 3 Assembly Initialization D ata Files on page A 3 Header Files on page A 4 Linker D escription Files on page A 4 Linker Command LineFiles on page A 5 C C Source Files C C source files are text files c cPP cxx and so containing C C code compiler directives possibly a mixture of assembly code and direc tives and typically preprocessor commands
127. rocessors kb prom Specifies the boot mode PRO M Flash or SPI for the boot kernel kb flash output file if you select to generate two output files from the loader kb spi onefor the boot kernel and another for the user application code T his switch must be used in conjunction with the 02 switch If the kb switch is absent on a command line the loader generates the file for the boot kernel in the same boot mode as used to output the user application code file kf hex Specifies the output file format hex ASCII or binary for the boot kf ascii kernel if you select to output two files from the loader one for the kf binary boot kernel and another for user application code T his switch must be used in conjunction with the 02 switch If the kf Switch is absent from the command line the loader generates the file for the boot kernel in the same format as for the user application program VisualD SP Loader M anual 2 43 for 16 Bit Processors Blackfin Processor Loader Guide Table 2 9 Blackfin Loader Command Line Switches Cont d Switch Description kp Specifies a hex PRO M Flash output start address for kernel code A valid value is between 0x0 OxFFFFFFFF The specified value will not be used if no kernel or and initialization code is included in the loader file kWidth 4 Specifies the width of the boot kernel output file when there are two output files one for boot kernel and one
128. rough a communication port For exam ple a AD SP 218x 219x processor brings a 256 word program in internal memory for execution T his small program is called a boot kernd The boot kernel then bringsthe rest of the booting routines into the proces sor s memory Finally the boot kernel overwrites itself with thefinal block and jumpsto the beginning of the application program On the AD SP 219x D SPs the highest 16 locations in page 0 program memory and the highest 272 locations in page 0 data memory are reserved for use by theROM boot routines typically for setting up DM A data structures and for bookkeeping operations Ensurethat the boot sequence entry code or boot loaded program do not need to initialize this space at boot time H owever the program can use these locations at run time Some of the newer Blackfin processors AD SP BF531 AD SP BF532 and AD SP BF533 do not require a boot kernel the advanced on chip boot ROM allowsthe entire application program body to be booted into the internal memory of the processor T he on chip boot ROM for the former processors behaves similar to the second stage loader of AD SP BF535 pro cessors The boot ROM has the capability to parse address and count information for each bootable block VisualD SP 3 5 Loader M anual 1 7 for 16 Bit Processors Loader Tasks Loader Tasks Common tasks perform by the loader include Processing loader option settings or command line switches e For
129. rs after reset No boot M ode e PROM Booting M ode Host Booting M ode No boot Mode T he processors starts fetching and executing instructions from EPROM Flash memory devices directly T his scheme does not require any loader mechanism It is up to the user program to initialize volatile memories T he splitter utility helpsto generate a file that can be burned into the PROM memory VisualD SP 3 5 Loader M anual 1 5 for 16 Bit Processors Booting Modes PROM Booting Mode After reset the processor starts reading data from any parallel or serial PROM device ThePROM stores a formatted boot stream rather than raw instruction code Beside application data the boot stream contains addi tional data such as destination addresses and word counts A small program called kernel or loader kernel described on page 1 7 parses the boot stream and initializes memories accordingly T he loader kernel runs on the target processors D epending on the architecture the loader kernel may execute from on chip boot ROM or may be pre loaded from the PROM deviceinto on chip SRAM and execute from there T he loader utility generates the boot stream from the linker s executable file and stores it to file format that can be burned into the PROM Host Booting Mode In this scheme the target processor is slave to a host system After reset the processor delays program execution until it gets signalled by the host System that the boot
130. runtime typically the Msx strobes are used Touseone EPROM for both booting and run time issues set the proper BMS control bits in the amp srAr register If several devices are connected to the individual msx strobes an off chip AN D gate is recommended to OR the 8Ms and the mso strobes properly Please refer to the Application N ote EE 164 for further details and code example 3 18 VisualD SP Loader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter ADSP 219x DSP Loader Guide T his section provides reference information about the loader s command line interface A list of the command line switches appears in T able 3 6 on page 3 21 W hen using the loader within VisualD SP settings on the Load page of the Project O ptions dialog box correspond to the loader s command line switches For more information see the VisualD SP 3 5 U ser s Guide for 16 Bit Processors or online H elp ADSP 219x Loader Command Line Reference U se the following syntax for the loader s command line elfloader sourcefile outputfile proc processor switch where e sourcefile dentifies the executable file DxE to be processed into a single processor boot loadable file A file name can include the drive and directory Enclose long file names within straight quotes long file name outputfile Optional name of the loader s output a file with the LDR extension Each run generates a single output fil
131. ry and the highest 272 locations in page 0 data memory are reserved for use by theROM boot routines for setting up DMA data structures and for initializing registers among other tasks Ensure that the boot sequence entry code or boot loaded program are not allowed into this space ADSP 219x DSP Boot Streams TheAD SP 219x ROM resident loader is designed to parse and load a spe cific boot stream format W hen booting from an external 8 or 16 bit EPROM the boot stream consists of header and block fields T he first header in the boot stream is a common word that applies to all booting modes except U ART T his header field specifies whether the stream is guarded by a checksum Individual bits within this word are set or cleared based on the booting method and specific command line switches specified by the user Parallel EPROM Boot Streams W hen booting from an external 8 or 16 bit EPROM the first 16 bit header field contains information on the number of wait states and the physical width 8 or 16 bit of the EPROM The first header is also known as a global header or a control word 3 4 VisualD SP Loader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter T his first header is followed by the regular boot stream that is a series of headers and data blocks M ost headers are followed by corresponding blocks of data but some headers indicate regions of memory that need to be zero filled and are not followe
132. s 2 16 AD SP BF535 processors 2 3 Blackfin processors 2 2 difference between Blackfin processors 2 18 differences between processors 2 28 EPROM BDM A 5 3 5 6 host 3 10 host ID M A 5 3 no boot mode 2 3 2 16 3 12 5 3 5 15 parallel EPROM 3 4 ROM bypass 2 4 see also SPI booting INDEX serial EPROM 3 12 UART part 3 11 viaUART on AD SP 219x 3 11 without boot kernel 2 45 boot loadable files 1 4 5 1 bootstraps 2 45 5 4 5 6 build files description of A 5 loader options 4 6 BUSM ODE pin settings 4 3 bypassing boot 2 29 byte loader switch 5 10 splitter switch 5 18 byte stacked format file 5 19 C C runtime routines 2 36 C C H source files A 2 Cache SRAM memory 2 34 checksum loader switch 3 21 clkdivide loader switch 3 21 CM SR settings 4 3 code alignment 2 14 command line AD SP 218x loader BD M A mode 5 7 AD SP 218x loader ID M A mode 5 13 AD SP 218x splitter 5 16 5 18 AD SP 2192 12 loader 4 10 AD SP 219x loader 3 19 3 21 Blackfin loader splitter 2 40 compiling 1 2 VisualD SP Loader M anual for 16 Bit Processors INDEX core A ranges 2 34 B ranges 2 34 count blocks 2 30 headers 2 35 2 37 creating run time boot loader 4 7 D data banks 2 34 blocks 3 6 debugger files A 9 development flow 1 1 dm data memory 5 7 5 17 dm splitter switch 5 18 DMODE pin settings 5 5 DMOVLAY memory page 5 15 DRAM memory 2 34 drivers downloading for AD SP 2192 12 DSPs 4 7 run time boot loader 4
133. sence of the version parameter a valid version value si revision aloneor with an invalid value the loader generates an error O utputs verbose loader messages and status information as the loader processes files 4 14 VisualD SP Loader M anual for 16 Bit Processors 5 ADSP 218X DSP LOADER SPLITTER This chapter explains how the loader splitter program e1fsp121 exe is used to convert executable files into boot loadable or non bootable files for AD SP 218x D SPs Refer to Introduction on page 1 1 for the loader splitter overview the introductory material applies to all processor families Loader and splitter operations specific to AD SP 218x D SPs are detailed in the following sections e AD SP 218x DSP Loader Guide on page 5 1 Explains how a boot loadable file is created written to and run from an AD SP 218x D SP s internal memory e ADSP 218x DSP Splitter Guide on page 5 15 Explains how a non bootable PROM image file is created and exe cuted from an AD SP 218x D SP s external memory ADSP 218x DSP Loader Guide T he loader splitter e1fsp121 exe processes an executable file DxE producing a boot loadable LDR or non bootable file 8NL BNM Or BNU T he preparation of a non bootable image is also called splitting or PROM splitting In most cases developers working with AD SP 218x D SPs usethe loader instead of the splitter VisualD SP 3 5 Loader M anual
134. ssors Blac kfin Processor Loader Splitter ISR The boot ROM then checks to see if it has been invoked by a soft ware reset by examining bit 4 of the System Reset Configuration R egister SYSCR If bit 4 isnot set the boot ROM presumes that a hard reset has occurred and performs the full boot sequence If bit 4 isset the boot ROM under stands that the user code has invoked a software reset and restarts the user program by jumping to the beginning of core A SL1 memory OxFFAO 0000 bypassing the entire boot sequence W hen developing an AD SP BF561 processor application you start with compiling and linking your application code into an executable file 0xE The debugger loads the oxe into the processor s memory and exe cutes it With two cores two xt files can be loaded at once In the real time environment there is no debugger which allows the boot RO M to load the executables into memory ADSP BF561 Processor Boot Streams T he loader converts the nxe into a boot stream file LDR by parsing the executable and creating blocks Each block is encapsulated within a 10 byte header The Lor file is burned into the external memory device Flash PROM or EEPROM Theboot ROM reads the external memory device parsing the headers and copying the blocks to the addresses where they reside during program execution After all the blocks are loaded the boot ROM jumps to address oxrrAo 0000 to execute the core A program W hen runn
135. sthe loader converts the code from an input pxe file into blocks com prising the output loader file each block is getting preceded by a 10 byte header Figure 2 10 followed by a block body if it is a non zero block or no block body if it isa zero block A description of the header struc ture can be found in T able 2 3 Table 2 3 ADSP BF531 BF532 BF533 Block H eader Structure Bit Field D escription Address 4 byte address at which the block resides in memory Count 4 byte number of bytes to boot Flag 2 byte flag containing information about the block Flags of Block H eader on page 2 20 describes the flag structure VisualD SP Loader M anual 2 19 for 16 Bit Processors Blackfin Proc essor Booting Block 10 Byte Header See Flag Information Figure 2 10 AD SP BF531 BF532 BF533 Processor Boot Stream Structure Flags of Block H eader Refer to the following figure and T able 2 4 for the flag s bit descriptions EE EE ESTIS LES RE E ICT Last Block 1 last block 0 not last block Ignore Block 1 ignore block 0 do not ignore block Initialization Block 1 init block 0 non init block Processor Type 1 ADSP BF533 0 ADSP BF531 BF532 Zero Fill 1 zero fill block 0 non zero fill block Bits 14 5 are reserved for future use 2 20 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter Table 2 4 Flag Structure
136. t block no care 40 47 8 15 of the address field of 1st D XE count block no care 48 55 16 23 of the address field of 1st D XE count block no care 56 63 M SB of the address field of 1st D XE count block no care 64 71 LSB 4 of the byte count field of 1st D XE count block 72 19 8 15 0 of the byte count field of 1st D XE count block 80 87 16 23 0 of the byte count field of 1st DXE count block 88 95 M SB 0 of the byte count field of 1st D XE count block 96 103 LSB of theflag word of 1st D XE count block ignore bit set 104 111 M SB of theflag word of 1st D XE count block 112 119 LSB of the first 1st DXE byte count VisualD SP Loader M anual 2 31 for 16 Bit Processors Blackfin Proc essor Booting Table 2 7 AD SP BF561 Processor Boot Stream Structure C ont d Bit Field D escription 20 127 8 15 of the first 1st DXE byte count 28 135 16 23 of the first 1st DXE byte count 36 143 24 31 of the first 1st DXE byte count 44 151 LSB of the address field of the 1st data block in 1st DXE 52 159 8 15 of the address field of the 1st data block in 1st DXE 60 167 16 23 of the address field of the 1st data block in 1st DXE 68 175 M SB of the address field of the 1st data block in 1st DXE 76 183 LSB of the byte count of the 1st data block in 1st DXE 84 191 8 15 of the byte count of the 1st data block in 1st DXE 92 199 16 23 of the byte count of the
137. tant data in Async Bank 0 zJ MEM_DATA_ROM TYPECROM START 0x200A0000 END Ox200FFFFF WIDTH 8 On chip SRAM data is not booted automatically MEM_DATA_RAM TYPE RAM START OXFF903000 END OXFF907FFF WIDTH 8 VisualD SP Loader M anual 2 53 for 16 Bit Processors Blackfin Processor Loader Guide Listing 2 4 ROM Segment D efinitions LD F File PROCESSOR pO OUTPUT COMMAND_LINE_OUTPUT_FILE SECTIONS program_rom INPUT_SECTION_ALIGN 4 INPUT SECTIONSC 0BJECTS rom code j MEM PROGRAM ROM data rom INPUT_SECTION_ALIGN 4 INPUT SECTIONS 0BJECTS rom data MEM DATA ROM data sra INPUT_SECTION_ALIGN 4 INPUT SECTIONSC OBJECTS ram data MEM DATA RAM With the LDF file modified this way the source files can now take advan tage of the newly introduced sections as in Listing 2 5 Listing 2 5 Section H andling SourceFiles SECTION rom code reset vector 10 0 1 0 12 0 13 0 continue with setup and application code 2 54 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter BASE x SECTION rom data VAR myconst x Oxdeadbeef LEE sh tts Agr SECTION ram data VAR myvar y note that y cannot be initialized automatically VisualD SP Loader M anual 2 55 for 16 Bit Processors Blackfin Processor Loader Guide VisualD SP Loader M anual for 16
138. ternal 16 bit memory at logical address 0x10000 Bypass ROM 0 1 0 Boot from EPROM 1 0 0 Boot from H ost 1 1 0 Reserved 0 0 1 N o boot mode Run from external 8 bit memory at logical address 0x10000 Bypass ROM 0 1 1 Boot from UART 1 0 1 Boot from SPI up to 4K bits The opmode pin has a dual role it acts as a boot mode select during RESET and determines whether the D SP sthird SPORT functions asa SPORT or an SPI It is possible for an application to require oP opt to operate differ ently at runtime than at reset that is boot from an SPI but useSPORT2 during runtime In this case the boot kernel is responsible for setting OPMODE accordingly at the end of the booting process T herefore software can change opmobeE anytime during runtime as long as the corresponding peripherals are disabled at that time VisualD SP Loader M anual 3 3 for 16 Bit Processors ADSP 219x DSP Booting ADSP 219x DSP Boot Kemel A loader boot kernel refers to the resident program stored in a 24 bit wide 1K portion of ROM space responsible for booting the D SP T he starting address of the boot ROM isoxrr 0000 to oxrr O3FF thefirst location of page 256 in 1 wait stated memory A boot interrupt vectors to address oxFF 0000 When a AD SP 219x D SP comes out of a hardware reset program control jumpsto oxrr 0000 and execution of the boot ROM code begins On ADSP 219x D SPs the highest 16 locations in page 0 program mem o
139. ternal program divided by 2 to obtain the corresponding logical address T he first alias window of seg ext data that can accessed properly is range 0x02 4000 to 0x02 AFFF this results in the logical range 0x01 5000 to 0x01 57FF Similarly the addresses of segment seg ext code can be calculated by dividing the physical addresses by 4 For example the alias window between 0x04 8000 and 0x04 rrrr can be used resulting in the logical addresses 0x01 2C00 to 0x01 3FFF T he corresponding LoF file would include the following MEMORY seg int code TYPECPM RA START 0x000000 END 0x000000 DTH 24 seg_int_data TYPECDM RA START 0x008000 END OxOO9FFF DTH 16 seg_ext_code TYPECPM RO START 0x012C00 END Ox013FFF DTH 8 seg_ext_data TYPECDM RO START 0x015000 END 0x0157FF DTH 8 By default the ei floader emits true EPROM addresses by multiplying thelogical addresses accordingly T he address aliasing which this example takes advantage of can be corrected if the loader is invoked with the VisualD SP Loader M anual 3 17 for 16 Bit Processors ADSP 219x DSP Booting maskaddr 16 Switch see on page 3 22 Then all EPROM addresses are AN D ed by oxrrrr and the resulting EPROM image fits into a 64 K byte EPROM The EPROM boot process assumes the boot device is connected to the D SP s Bms strobe During
140. ters are set to be read only and the D SP isto respond to PCI requests from the sys tem host For USB the DSP isto enter an idle loop allowing the system host to detect and configure the part T he final task performed by the kernel after configuring the bus and trans ferring control to PCI or USB isto enter an infinite loop waiting for instructions A predefined memory address DM 0x000000 is regularly checked for commands O ncethe PCI or USB device has completed boot ing theD SP they can writean instruction to this predefined location and have the D SP execute any of supported commands Refer to the datasheet AD SP 219x 2192 D SP H ardware Reference and Application N ote EE 124 for further details ADSP 2192 DSP RTBL The VisualD SP linker produces files with oxe ovL and sm exten sions T ypically these file are not shipped with your applications Instead the linker s output is run through the loader that repackages the linker output asan H file which is consumed by an RTBL as illustrated in Figure 4 1 TheRT BL output file exe is used by a bootable device PCI or USB Given that booting from PCI or USB involves code running on the PC host you must create a program which executes on the host to initiate and conduct the actual PCI or USB transfer Because of this the loader 4 4 VisualD SP Loader M anual for 16 Bit Processors ADSP 2192 12 DSP Loader Loader The loader consumes the linker s o
141. the loader processes the files Wait state Specifies the number of the wait states for external access 0 15 The selection is active for AD SP BF535 processors For AD SP BF531 AD SP BF532 and AD SP BF533 processors the field is grayed out H old time Specifies the number of the hold time cycles for PRO M Flash boot 0 3 The selection is active for AD SP BF535 processors For AD SP BF531 AD SP BF532 and AD SP BF533 processors the field is grayed out 2 48 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter Table 2 10 Base Loader Page Settings C ont d Setting Description Baud rate Specifies a baud rate for SPI booting 500 kHz 1 MHz and 2 M HZ T he selection is active for AD SP BF535 processors For AD SP BF531 AD SP BF532 and AD SP BF533 processors the field is grayed out Initialization Directs the loader to include the initialization file Init code T he Initialization file file selection is active for AD SP BF531 BF532 BF533 and AD SP BF561 pro cessors For AD SP BF535 processors the field is grayed out Kernel file Specifies the boot kernel file Can be used to override the default boot kernel if there is one by default as on AD SP BF535 processors O utput file N ames the loader s output file Additional Specifies additional loader switches You can specify additional input files for a options multiinput system Note T he l
142. the object file s ELF format see the Format References on page A 10 VisualD SP Loader M anual A 5 for 16 Bit Processors Build Files Library Files Library files 5 8 the archiver s output are binary executable and link able files ELF Library files called archive files in previous software releases contain one or more object files archive elements T he linker searches through library filesfor library members used by the code For information on the ELF format used for executable files refer to Format References on page A 10 T hearchiver automatically converts legacy input objects from COFF to ELF format Linker Output Files T he linker s output files DxE sM ovL are binary executable and link able files ELF T he executable files contain program code and debugging information T he linker fully resolves addresses in executable files For information on the ELF format used for executable files seethe TIS Com mittee texts cited in Format References on page A 10 T he loaders splitters are used to convert executable files into boot load able or non bootable files Executable files are converted into a boot loadable file DR for the ADI processors using a loader program O nce an application program is fully debugged it is ready to be converted into a boot loadable file A boot loadable file is transported into and run from a processor s internal memory This file is then programmed bur
143. there is only one input executable supplied to elfloader with an exception of 1 An artificial loader block with header and data block is created right after the first global 16 bit header and before the regular boot stream T he destination address in the header is same as that of the first loader block in the regular boot stream T his means that any data booted by the artificial loader block is to be overwritten by the real data from the regular boot stream T he content of this block s payload is the pd value for the next DXE If no pd grouping is specified for the next dxe the pd value for the next pxe is calculated by adding the pd value of the current DXE and the size in bytes of the current bxe loader stream If there are no other pxesin the stream the default value is zero You can overwrite the default by the pdAddrNext switch T heartificial loader block can be removed by turning on the noDxeAddrHdr command line option 2 Theloader stream version which is 4 bitsin the first 16 bit header N ote that both of these modifications are backward compatible with the AD SP 2191 boot kernel T he optional switches specific to dxe file that follows may include Example 3 8 VisualD SP Loader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter 0 Output file LDR for the current and following DXES see o filename on page 3 22 opmode O pmode for the current and follo
144. these files on the command line Place ovL filesin the same directory as the DXE file that refers to them the loader can locate them when processing the BNM file LDR Loader output file 3 20 VisualD SP Loader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter Loader Switches A description of each loader command line switch appears in T able 3 6 Table 3 6 Loader Command Line Switches Switch Description filename Specifies an executable file to be processed into a single processor load able file For multiprocessor system use the iditexe file switch b prom Specifies the boot mode Prepares a boot loadable file for the PROM b host default H ost U ART SPI or no boot booting T he specified mode Men must correspond to the boot kernel selected with the 1 switch and the zb spi file format selected with the f switch blocksize Specifies the size decimal 4 in words for each block of data in the boot stream D efault is 6K words Valid block sizes may vary up to 6K words checksum Calculates and generates checksums for each block of code and data clkdivide Specifies the base clock divide factor Valid values are 0 to 7 inclusive T he default is 5 Note Appliesto EPROM and Host boot modes only f hex Specifies the boot file s format f ASCII Valid selections are nex Intel hex 32 ASCII and binary T he hexa f binary decimal format is t
145. this symbol 9S A caution providing information about critical design or program ming issues that influence operation of a product In the online version of this book the word Caution appears instead of this symbol Code has been formatted to fit this manual s page width VisualD SP Loader M anual xix for 16 Bit Processors Notation Conventions Xx VisualD SP Loader M anual for 16 Bit Processors 1 INTRODUCTION T he majority of this manual describes the loader program or loader util ity as well as the process of loading and splitting the final phase of a D SP application program s development flow T he process of initializing on chip and off chip memories is often referred to as booting T he majority of this chapter applies to all 16 bit processors Information applicable to a particular target processor or to a particular processor fam ily is provided in the following chapters Chapter 2 Blackfin Processor Loader Splitter on page 2 1 e Chapter 3 AD SP 219x D SP Loader Splitter on page 3 1 e Chapter 4 AD SP 2192 12 DSP Loader on page 4 1 e Chapter 5 AD SP 218x D SP Loader Splitter on page 5 1 Program Development Flow T he flow can be split into three phases 1 Compiling and Assembling 2 Linking 3 Loading and Splitting A brief description of each phase is as follows VisualD SP 3 5 Loader M anual 1 1 for 16 Bit Processors Progr
146. uals can be purchased only as a kit For additional information call 1 603 883 2430 VisualD SP Loader M anual xvii for 16 Bit Processors Product Information If you do not havean account with Analog D evices you will be referred to Analog D evices distributors T o get information on our distributors log onto http www analog com salesdir continent asp Hardware Manuals H ardware reference and instruction set reference manuals can be ordered through the Literature C enter or downloaded from the Analog D evices W eb site The phone number is 1 800 AN ALO GD 1 800 262 5643 T he manuals can be ordered by a title or by product number located on the back cover of each manual Datasheets All datasheets can be downloaded from the Analog D evices W eb site Asa general rule any datasheet with a letter suffix L M N can be obtained from the Literature C enter at 1 800 AN ALO GD 1 800 262 5643 or downloaded from the W eb site D atasheets without the suffix can be downloaded from the W eb site only no hard copies are available You can ask for the datasheet by a part name or by product number If you want to have a datasheet faxed to you the phone number for that service is 1 800 446 6212 Follow the prompts and a list of datasheet code numbers will be faxed to you Call the Literature C enter first to find out if requested datasheets are available Contacting DSP Publications Please send your comments and recommendation
147. ull application can be booted to the various memories with just the on chip boot ROM T he loader converts the application code 0xE into the loadable file by parsing the code and creating a file that consists of different blocks Each block is encapsulated within a 10 byte header which is illustrated in Figure 2 9 and detailed in the following section T hese headers in turn are read and parsed by the on chip boot ROM during booting The 10 byte header provides all the information the on chip boot ROM requires whereto boot the block to how many bytesto boot in and what to do with the block 2 18 VisualD SP Loader M anual for 16 Bit Processors Blackfin Processor Loader Splitter ADSP BF531 BF532 BF533 Processor Boot Steams T he following sections describe the boot stream header and flag frame work for AD SP BF531 AD SP BF 532 and AD SP BF533 processors Blocks and Block H eaders on page 2 19 Flags of Block H eader on page 2 20 Initialization Blocks on page 2 21 The ADSP BF531 BF532 BF533 processor boot stream is similar to the boot stream that uses a second stage kernel of AD SP BF535 processors detailed in AD SP BF535 Processor Boot Streams on page 2 8 H ow ever since the former processors do not employ a kernel their boot streams do not include the kernel code and the associated 4 byte header on thetop of the kernel code T here is also no 4 byte global header Blocks and Block H eaders A
148. utput files DXE to produce a C language source file H RTBL that contains data The run time boot loader compiles structures representing the the H file and any other source files executable lies typically C C using host deve lopment tools e g Microsoft Visual C The resulting EXE file can be executed on a host PC Figure 4 1 AD SP 2192 12 DSP Loader Sequence output file H is the C language source code for inclusion and compila tion into a host program ExE using a C compiler such as M icrosoft Visual C to create the RT BL T he source code emitted by the loader is essentially arrays and structures representing the executable s sections and their contents Refer to the comments contained within the generated 4 file for specific information about the data structures and their usage Building DXE Files You must build two pxt files which serve as input to the loader T hen you build the u file Lastly you create the xe file see Creating a EXE File on page 4 6 T he following procedure suggests one method to build the DxE file using the VisualD SP environment You may choose to combine steps or use the loader s command line instead To build the oxe files from VisualD SP 1 Open the Project page of the Project O ptions dialog box 2 Under Processor select AD SP 2192 12 VisualD SP Loader M anual 4 5 for 16 Bit Processors ADSP 2192 DSP Booting Under Type select
149. wing DXEs see opmode on page 3 22 p Thelntel hex offset for the current loader file see p address on page 3 22 width Width for the current and following DXEs see width on page 3 24 wait T he number of wait states for this and following DXEs see waits on page 3 24 clkdivide Clkdivide for this and following Dxts see clkdivide on page 3 21 maskaddr Address bits to be masked off for this and following DXEs see maskaddr on page 3 22 T here are four executable files streams e Application 1 app1 dxe starts at byte address 0x000000 ROM Application 2 app2 dxe appends to Application 1 ROM Application 3 app3 dxe starts at 0x020000 flash page 1 Application 4 app4 dxe starts at 0x030000 flash page 2 T he task is to create two loader files oneis 16 bit ROM from 0x000000 to OxO1FFFF and one is 8 bit Flash from 0x020000 to 0xO3FFFF T here are two different ways to accomplish the task 1 Use VisualD SP Flash Programmer plug in to burn the Flash In this scenario the real byte address is expected elfloader proc ADSP 2191 b PROM width 16 appl dxe app2 dxe pd 0x20000 p 0x20000 width8 o flash ldr app3 dxe pd 0x30000 app4 dxe Since the p value is reset to a zero whenever an o is specified the addresses in the Intel hex record starts at zero for t1asn 1dr 2 Equivalently invoke the loader twice VisualD SP Loader M anual 3
150. y 128 clock and 7 wait states to access the EPROM While booting via EPROM boot space the highest 16 locations in page 0 pro gram memory block 0x7FFO to oxzrrr and the top 272 locations of page 0 data memory block oxFEFO to oxrrrr are reserved for use by the RO M boot routines 3 6 VisualD SP Loader M anual for 16 Bit Processors ADSP 219x DSP Loader Splitter ADSP 219x DSP Multiple DXE Support VisualD SP 3 5 introduces support for multiple oxe booting in Parallel EPROM booting mode Boot streams of multiple projects or applications can be stored in asingle EPROM Theon chip boot kernel always boots in application number 0 Its boot stream starts at EPROM address 0x000000 U ser defined second stage loaders or boot management soft ware may boot any application depending on application specific circumstances Alternatively one application can be loaded and executed after the other terminates T he loader splitter utility can consume multi ple oxt files and arrange their boot streams in several manners U se the following syntax to submit two or more executable files to the loader elfloader Filel dxe outputfile proc processor switch m pd addr switches specific to dxe file that follows File2 dxe pd addr switches specific to dxe file that follows File3 dxe Filel dxe is the default application that is booted by the on chip boot kernel after reset Unless the p switch is specified the boot stream o
151. y booting 2 26 start addresses 2 16 SYSCR register 2 29 block flags 2 13 headers 2 13 2 18 2 30 2 35 3 5 structure 2 19 blocksize loader switch 3 21 BM ODE pin settings 2 2 AD SP 2181 D SPs 5 4 AD SP 2183 D SPs 5 4 AD SP 2184 5 6 7 8 9 D SPs 5 4 AD SP 219x D SPs 3 3 AD SP BF 531 32 33 processors 2 16 AD SP BF535 processors 2 3 boot file format specifying 2 42 3 21 boot kernel 1 7 omitting in output 2 45 setting for Blackfin processors 2 49 specifying boot mode 2 43 specifying hex address 2 44 specifying kernel amp app files 2 50 specifying user kernel 2 44 boot loader kernel AD SP 2192 D SP 4 2 boot management AD SP 218x D SPs 5 6 boot modes 1 3 1 5 AD SP 218x D SPs 5 4 AD SP 219x D SPs 3 3 AD SP BF 531 32 33 processors 2 16 AD SP BF535 processors 2 3 AD SP BF561 processors 2 28 specifying in 219x processors 3 21 specifying AD SP 218x D SPs 5 4 specifying Blackfin processors 2 42 VisualD SP Loader M anual for 16 Bit Processors boot ROM 1 7 2 3 2 6 2 18 2 29 2 36 boot sequences 1 4 1 7 AD SP BF531 32 33 processors 2 16 AD SP BF535 processors 2 4 boot streams 2 35 AD SP 219x 3 4 AD SP 219x D SPs 3 4 AD SP BF531 32 33 processors 2 19 AD SP BF535 processors 2 8 2 9 AD SP BF561 processors 2 29 block headers 2 19 blocks 2 19 flags 2 13 flags of block headers 2 20 global headers 2 12 headers 2 11 booting 1 5 AD SP 2192 12 D SPs 4 2 4 4 AD SP 219x D SPs 3 2 AD SP BF531 32 33 processor
152. y output file middle BNL Splitter binary output file lower Splitter Switches T able 5 8 lists and describes the available splitter command line switches Table 5 8 Splitter Command Line Switches Switch D escription sourcefile outputfile Specifies the source DXE for the splitter operation Specifies the splitter s output file If not specified the name of the sourcef 1e executable file is used for the output T he extension depends on the output format byte Produces byte stream output format dm pm Extracts data memory Extracts segments from the executable declared as data memory T he splitter generates two one byte files BNM contains the upper bytes of the 16 bit data words BNL contains the lower bytes Produces Intel hex output format Extracts program memory Extracts segments from the executable declared as program memory The splitter generates three one byte files BNU contains the upper bytes of the 24 bit words BNM contains the middle bytes BNL contains the lowest bytes readall IncludesRAM and ROM in PROM Extracts both RAM and ROM segments from the input file By default only ROM segments are extracted VisualD SP 3 5 Loader M anual for 16 Bit Processors ADSP 218x DSP Loader Splitter Table 5 8 Splitter Command Line Switches Cont d Switch Description s Produces M otorola S1 output fo

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