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ADSP-TS201S EZ-KIT Lite Evaluation System

1. PLACE LABEL EXPANSION INTERFACE TYPE A NEAR MIDDLE CONNECTOR sij S T s da WARNING WHEN CONNECTING TO ANOTHER BOARD KA KA K EA fx C C C C C MAKE SURE TX CONNECTOR GOES TO A RX CONNECTOR DO NOT USE CROSSOVER CABLE L bosi lt gt e M e LI Ah lt gt J4 J3 4 2 1 JI J2 2 LABEL DSP A TX H 2 1 de e 2 1 NI 4 B 4 B 4 3 6 5 34 w mera ero s en DSP A TX 1 CLKOUT EXPI SDWE L DPA IDMARO 1 5 ro 5 BM B dr niis a se iil ae MN LA 7 ve L CAS 3 ISDAIO__1 u IDMARLA 6 rl rev B DO PSE za LASI 10 P iAd i i SDCKEI 10 P IRAS i DMAR3 Bj 12 11 IDMAR2 B 7 VA 12 11 A6 pe 12 11 PERS INE Lc 14 13 K 1 HDOM LDQM _ L JOWRI MSH o 14 nz Ss da 14 nz IMSSDO i i _ MSSDII JE ns ORD CON I A0 16 15 IA10 A 16 15 al CSS 18 17 IMSED2 1 CON Le vm pm wf NPE MM K mmm mm rt P I Ao Hag Ipi sss CA 18 17 GC 049 18 17 ID 1 20 19 BMB ds A15 20 19 A1 Sech 20 19 Ser 22 21 N p i At 22 21 IAT6 D53 22 21 D52 F 24 23 TE za Aid 24 23 IAT _D55 24 23 1D54 1 26 25 DAA es D
2. A B C D 1V DSP A CY e e e e e e e e e e e e e VDD 1 0V Bypass Caps per DSP 8 1nF C173 C174 C175 C176 C177 C178 C179 C180 C219 C218 C216 C220 C221 C222 C223 C224 C225 4 0 01uF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 0 01UF 0 01UF 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 5 0 1uF 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 1 100uF e e e e e e e e e e e e S 1V DSP B KA ALL BYPASS CAPS SHOULD BE PLACED AS CLOSE AS POSSIBLE TO THE CORISPONDING IG TRACES FROM COMPONENT TO CAPACITOR AND FROM THE CAPACITOR TO GND SHOULD BE AS SHORT AS POSSIBLE C206 C196 C207 C208 C209 C210 C195 C211 C203 C204 C205 C202 C201 C200 C199 C198 C197 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 0 01UF 0 01UF 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF THE PRIORITY FOR THE PLACEMENT 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 1V DSP X 1 5V DSP X e e e e e e e e e e e e 2 5V DSP X 1 5V DSP A O 1 5V DSP B CA Sa e e e e e e VDD DRAM 1 5V Bypass Caps per DSP 6 1nF C67 C168 C169 C170 C171 C172 C68 C167 C165 C166 C75 C69 C21
3. A C D D2 Fi FER5 SCHOT RECT 2 5A CHOKE_COIL 3A FUS001 DO214AB 4 3 NM mj un gt LUNREG IN OCI 2 EN Y YS e D1 ee S2A RECT 1206 DO 244AA DA FER7 CON005 600 MH MH2 MH3 MH 2 5MM JACK 1206 ES FPSS JEN TP ma TP4 TP5 4 AA rN O O O n Ka n N N A A Y FER6 C47 600 1000PF 1206 1206 e FV V Y Y e e oe s y y za 4 SHGN SHGN 1 8V PA A EE 5V ASV i UNREGIN O O 3 3V sa dl O R234 m 332K 3 3V 805 O R178 FER3 0 00 600 ANN IN VR6 1206 1206 VR4 VR3 1 R202 INT OUT1 e HEC DM UNRES TN 777 I 8 b e INPUT ERRE 1205 o NES IN a cs e SINPUT OUTPUT eno OUT2 d 1 GND 5 5D OUTPUT N A e T ADP3339AKC 33 SH SC SOT 223 6 5 SD GND FB GND R228 dore C247 cres C248 A ADP3336ARM R190 C70 C54 C72 4 ADP3331ART C74 R192 100K 10UF 0 1UF 10UF 0 1UF MSOP8 210K 4UF 1UF 1UF C73 SOT23 6 0 47UF 340K 1206 NE 805 INE 805 805 T 805 T 805 T 805 0 47UF T 805 805 805 C71 e e e e 1UF T 805 R201 698K R191 805 64 9K 805 e e e e NZ Si 2 5V U35 C x I UNREG IN ir _ UNREG IN E UNREGIN D6 m CMDSH 3 pi 2 l6 tov SOD 323 1 5V 3 Le 7 O R219 R227 0 01 4 8 10 5K VR2 2512 1206 C58 2 1 0 18UF L5
4. A B C D DS P A LABEL DSP A near this DSP ro Abat lt gt Does q i A0 H24 D17 KEEP THESE NETS THE SAME LENGTH BEL ADDRO DATAO pe a LAG Drop para r AA1 1 124 H22ADDR2 DATA2P 7 ro DEE H21 ADDR3 DATAS gom mg Ai D nn DATA4P16 FER E 623 ADDR5 DATAS B e v LAG G22 DRe DATA6 16 ra LAG G21 DDR7 DATA7CIS i AB F24 D15 PLACE CLOSE TO IDT5v929 PINS LZ ADDR8 DATA8 SY eV NG a pesi LA FS Dro DATASATS 22 TATO L A10 FM pas DATA10P15 309 ls i ATI E23 A14 U11 L ISCLK DSRA _ see ADDR11 DATA11 su E y L Ate D nz DATA12P14 m M bee es C18 AC7 805 I A13 F21 C14 RD lt 2 RD CPA lt gt MR TEE SEN SE ADDR13 DATA13 3 ISCLK DSP B i CA E22 D14 I Wao Orr oa gt e ez ENE a J ad IADDR14 DATA14 rer B18 22 CA E21 A13 WE ann 805 a o Pappe DATA15 spino C17 AAT 6 IN EE REN Ate peal bus ACK CO ACK DMR lt VDD Q0P gt ISDRAM CLKO i Mail IADDR16 DATA16 pece D18 Ap V pes cstas DAM D23 C12 i BRST lt gt PRST Pee VDDQ1 q A IADDR17 DATAI ff o Ince pe ho XT DMAR9 lt VDDQ2 Q2 L_A18 B24 DR18 DATA18P 1 lang ee ki PAIS D22 h12 I Ven so DMR J VDDQ3 Q3 805 ali IADDR19 DATA19 gt e sis 7 A mu MS1 81 VDDQ4 ARE D ISDRAM CLK1 1 L A20 C21 DDR20 DATA20P 12 SEH ACS i Capo onem ds Pl MSH SH IOWR o2 ASI A23 nei DATA21
5. Start Address End Address Content Internal 0x0000 0000 Ox 0001 FFFF Internal Memory 0 Memoly 0x0004 0000 0x0005 FFFF Internal Memory 2 0x0008 0000 0x0009 FFFF Internal Memory 4 0x000C 0000 0x000D FFFF Internal Memory 6 0x0010 0000 0x0011 FFFF Internal Memory 8 0x0014 0000 0x0015 FFFF Internal Memory 10 0x001E 0000 0x001E 03FF Internal Registers 0x001F 0000 0x001F 03FF SOC Registers 0x0C00 0000 OxOFFF FFFF Broadcast 0x1000 0000 0x13FF FFFF Processor ID 0 0x1400 0000 Ox17FF FFFF Processor ID 1 External 0x3000 0000 0x37FF FFFF External Memory Space Bank 0 MSO Memory MSO includes Flash Memory which ends at 0x3007 FFFF 0x3800 0000 Ox39FF FFFF External Memory Space Bank I 0x4000 0000 0x43FF FFFF External Memory Space MSSD0 MSSDO includes SDRAM which ends at 0x407F FFFF 0x8000 0000 OxFFFF FFFF Host ADSP TS201S EZ KIT Lite Evaluation System Manual 2 3 Using SDRAM Interface Using SDRAM Interface The SDRAM on the EZ KIT Lite evaluation board is 32 MB To access SDRAM the SYSCON and SDRCON registers must be configured properly The SDRAM default values are e SYSCON 0x00189067 e SDRCON 0x00005983 For the supplied memory the SDRCON register should be configured as follows SDRAM enable CAS latency of two cycles pipe depth of zero page boundary of 256 words refresh rate of every 3700 cycles precharge to RAS of two cycles RAS to precharge of five cycles init sequence is
6. I Default settings Clock Mode Settings The resistors on the clock generator U1 and the resistors on the SCLKRAT pins 2 0 of each of the processors determine the frequency at which the two processor operate The frequency supplied to CLKIN of the processor may also be changed by replacing the 20 MHz oscillator U18 shipped with the board with a different oscillator Ensure that the selected clock mode and frequency do not exceed the minimum and maximum specifica tions of the ADSP TS201S processor as noted in the datasheet The final frequency at which the DSPs operate is determined by the fol lowing equation Freq of U18 Mult Factor of Ul Mult Factor of SCLKRAT pins Final Oper Freg The default frequency factory setting is 20 MHz 5 5 500 MHz Table 3 12 through Table 3 14 show the resistor settings for the clock generator and the SCLKRAT pins For more information on the clock modes see the ADSP TS201S Embedded Processor Datasheet The DSP A and DSP B SCLK ratios must be of the same value 3 12 ADSP TS201S EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Table 3 12 Clock Generator U1 Settings R215 R224 R3 R223 Multiplication Factor Not populated Populated Not populated Populated 2 Not populated Populated Populated Populated 3 Not populated Populated Populated Not populated 4 Populated Populated Not populated Po
7. 2xi VSS55 VSS132175 vigVDD58 VDD 1031 p25 VSS57 VSS134T17 vraVDD55 VDD 102815 DNP ONSE VSS13371g veVDD59 VDD lO32p5 4 VSS58 VSS135r20 v17VDD56 VDD 102959 VSS57 VSS134T17 v7VDD60 VDD 103350 gVSS59 VSS136r5 vigVDD57 VDD 10305 4 VSS58 VSS135r20 va DD VDD_1034p5 gVSS60 VSS137ra vigVDD58 VDD 1031 p25 gVSS59 VSS136r5 ygVDD62 VDD 103552 KTOVSS61 VSS13 veVDD59 VDD lO32p5 gVSS60 VSS137g wroVDD63 VDD 103695 K11VSS62 VSS 1391 v7VDD60 VDD 103359 KTOVSS61 VSS138g wr3VDD64 VDD_1087y29 KT2VSS63 VSS140g veVDD61 VDD 10345 K11VSS62 VSS139y wraVDD65 VDD IO38yyzp KTgVSS64 VSS14 174 vgVDDe2 VDD 103552 KT2VSS63 VSS140g W17VDD66 VDD 103 KTAVSS65 VSS1425 wroVDD63 VDD 103605 K13VSS64 VSS14 174 w1aVDD67 VDD 1040v79 K15 S966 VSS143p wr3VDD64 VDD_1087y29 KTAVSS65 VSS142p w19VDD68 VDD 1041y KT8VSS67 VSS144y17 W14VDD65 VDD IO38yyzp K15 S966 VSS143576 wevDD69 VDD 1042y KT7NSS68 VSS145gg W17VDD66 VDD_103 y KT8VSS67 VSS144p w7VDD70 VDD 1043y KgVSS69 VSS1469 WT8VDD67 VDD_1040v7y KT7NSS68 VSS145gg wavDD71 VDD d er KGVSS70 VSS147y wryVDD68 VDD_1041y Ke VSS69 VSS1469 vvsVDD72 VDD 1045y L10VSS71 VSS148y we Deg VDD 1042y KgVSS70 VSS147y VDD73 VDD 1046y LTIVSS72 VSS149y1g w7VDD70 VDD_1043y ToVSS71 VSS148y75 EEN N3 VDD 1047y19 12VSS73 VSS150y 0 WaVDD71 VDD 1044y LTTVSS72 VSS149y1g I AV DSP SR N4VDD_A1 VDD 1048yg LT3VSS74 VSS151y5 waVD
8. Figure 1 2 Windows 98 Add New Hardware Wizard 2 Click Next 1 8 ADSP TS201S EZ KIT Lite Evaluation System Manual Getting Started 3 Select Search for the best driver for your device as shown in Figure 1 3 Add New Hardware Wizard What do you want Windows to do Recommended Display a list of all the drivers in a specific location so you can select the driver you want lt Back Cancel Figure 1 3 Windows 98 Searching for Driver 4 Click Next 5 Select CD ROM drive as shown in Figure 1 4 Add New Hardware Wizard Windows will search for new drivers in its driver database on your hard drive and in any of the following selected locations Click Next to start the search Floppy disk drives Iv CD ROM drive lt Back Cancel Figure 1 4 Windows 98 Searching for CD ROM ADSP TS201S EZ KIT Lite Evaluation System Manual 1 9 Installation Tasks 6 Click Next Windows 98 locates the WmUSBEZ inf file on the installation CD as shown in Figure 1 5 Add New Hardware Wizard Figure 1 5 Windows 98 Locating Driver 7 Click Next The Copying Files dialog box appears Figure 1 6 Copying Files m Figure 1 6 Windows 98 Searching for SYS File 1 10 ADSP TS201S EZ KIT Lite Evaluation System Manual Getting Started 8 Click Browse The Open dialog box shown in Figure 1 7 appears on the screen WmUSBEz sys
9. Figure 1 7 Windows 98 Opening SYS File 9 In Drives select your CD ROM drive 10 Click OK The Copying Files dialog box Figure 1 8 appears Copying Files el Figure 1 8 Windows 98 Copying SYS File ADSP TS201S EZ KIT Lite Evaluation System Manual 1 11 Installation Tasks 11 Click OK The driver installation is now complete as shown in Figure 1 9 Add New Hardware Wizard Hui ADSP TS2015 EZ KIT Lite Windows has finished installing the software that your new hardware device requires Figure 1 9 Windows 98 Completing Software Installation 12 Click Finish to exit the wizard Verify the installation by following the instructions in Verifying Driver Installation on page 1 15 Windows 2000 USB Driver VisualDSP 3 5 installation software pre installs the necessary drivers for the selected EZ KIT Lite The install also upgrades an older driver if such is detected in the system Q Prior to running the VisualDSP 3 5 installer ensure there are no other Hardware Wizard windows running in the background If there are any wizard windows running close them before starting the installer 1 12 ADSP TS201S EZ KIT Lite Evaluation System Manual Getting Started To install the USB driver 1 If VisualDSP 3 5 is already installed on your system go to step 2 Otherwise run VisualDSP 3 5 installation Refer to the VisualDSP 3 5 Installation Quick Reference
10. L6 s VIN BOOST T 805 1 5UH 1UH IND003 SOIC8 IND004 SEHEN 9 NY VRS NY SHDN SW e e e e 8 b 2 55K VIN saje ui SYNC FB 805 9 1 5 D4 SYNC FCB SENSE e C66 R225 C60 4 7 0 1UF n TT 22UF 9 GND vc Se _ tene n 2 6 805 1206 805 se SATA K 00UF m dal DI LTT765 2200PF C61 C51 Ten SO 8 T 1206 4 7UF 0AUF 150UF 0 1UF 2 6 4 B 805 805 IN D 805 po DS BG 5 4 e e e e ND VFB Se Lens C65 MBRS340T3 e E 3A Mone DIO002 A C53 R221 100PF 80 6K D7 1206 805 Lieto CMDSH 3 L UNREG IN 100MA Hi sea SOD 323 2 5V m x VRI C55 2 1 0 18UF L4 R189 VIN BOOST 805 1 5UH 0 00 R226 IND003 1206 0 00 ISHDN d FVNTV 805 SHDN SW e e 8 6 10 7K E 7 bo ANALOG 20 Cotton Road D5 C59 cup vol SL22 Ferz Nashua NH 03063 ma i ci DO 214AA 100UF DE V IC ES PH 1 800 ANALOGD LT1765 2200PF C76 SO 8 T 1206 4 7UF m 805 A itle pprovals Date 4 4 ADSP TS201S EZ KIT LITE POWER Drawn Size Board No Rev Checked C A01 78 2002 1 1C Engineerin 8 8 Date 3 1 2004 10 59 Sheet 13 of 15 A C D
11. 1 ADE 2 18 gt LS FA A21 D11 BMS BMS IORD K1 as 805 Er ADDR22 DATA22 css ig DEE E ENS IOEN X2 O 07 2 gt ICLKOUT EXP I 2 L A23 Bel DDRES paTA23A NI a EE O O O O A O ui sn evi I BR 0 7 RO 4 C20 DDR24 pra 024 o 22 i a BR1 OoE Me DAS DEOR para 8 sa pal me CERRI BR2 IDO GND1 _ a 20 CIS Rag DATA26 H b i ASI BR3 So GND2 e Los pera DATA27010 m gt VEU BRA ID2 S1 GND3 e L 428 Apps DATA28 0 17 ee BR5 GND4 e L A29 B20 DR29 DATA29 p bi A30 A19 B9 BR6 SCLKRATO REF GND5 o IADDR30 DATA30 pe q P PERSI BR7 LA Boas Ici N40 Te EE T2 0SC001 D9 SCLKRAT2 2 TSSOP24 DATA32 E EE lag I BMA lt gt BM DATA33 m ep elin AC8 WI RE f a q AMB 58 BOFFI gt OFF CONTROLIMPO lt ICONTROLIMPO I N A SNC DATA34 bus 13 ABE Va O ABA ke BUSLOCK lt gt BUSLOCK CONTROLIMP1 CONTROLIMP1 1 NC2 DATA35 PLACE TEST POINTS NEXT TO EACH OTHER Pal cg DATA36P gt AAB T4 A7 L HBR 5 HBR Dso e DATA37 ADR U4 B7 HBG lt 66 m DATA38 Sat vo C7 DS2 PLACE CLOSE TO EACH OTHER DATA39 di D7 L RAS Oras DATA40 3 ee SENER lag L CAS lt gt CAS ENEDREG 1 DATA41 ETE RR i EMU lt emu DATARS egies Fc ae NR la ae Y2 AS L_LDOMI DOM TMROE MROEA 3 TOK DSP Ai gt rok DATAS O Ka
12. 2 10UH X 10 L1 2 PANASONIC ELJ FC100KF 75 11122 1 10W 5 R4 R6 R11 VISHAY DALE CRCW0805220JRT1 R24 R32 R34 35 R129 R205 207 76 2 0 47UF 16V 10 C73 74 AVX 0805YC474KAT2A 77 4 1UF 10V 10 C37 C41 C44 AVX 0805ZC105KAT2A C46 78 6 1000PF 10V 20 C38 40 YAGEO 1206CG229C9B200 C42 43 C45 A 6 ADSP TS201S EZ KIT Lite Evaluation System Manual Bill Of Materials Reference Quantity Description Reference Design Manufacturer Part Number I LA 4 7UF 6 3V 10 C61 C65 C76 AVX 08056D475KAT2A o 53 0 1UF 10V 10 C69 C75 C79 84 C155 162 C108 C110 115 C118 C120 122 C141 C144 C165 166 C182 C184 185 C187 C197 201 C221 225 C228 231 C237 239 C241 AVX 0402ZD104KAT2A 81 82 46 0 01UF 16V 10 4 7K 31MW 5 C68 C85 90 C92 99 C103 104 C107 C109 C129 140 C167 C181 C183 C202 205 C216 C218 220 C227 C232 C240 C242 RN3 4 AVX CTS 0402YC103KAT2A 746X101472 83 16 499 1 10W 1 R23 R25 R45 R51 R111 R114 R124 R133 R140 146 R154 VISHAY CRCW08054990FRT1 84 1UH 5 9MOHMS 30 L6 DIGIKEY 919AS 1RON P3 ND 85 1 5UH 45MOHM 20 L4 5 TYCO DS6630 1R5M ADSP TS201S EZ KIT Lite Evaluation System Manual A 7 P v 2 v 2 HE dje g s 8 bb s 2 ER ii E a
13. ADT854JRS SSOP28 DAC RIGHT _ Cap PB 330PF R75 805 U8 68UF Ge N C21 gt 1206 100PF 7 1206 s q 5 G8OPF m R69 805 R72 SOIC8 SLAVE MODE 5 49K 1 65K 1206 1206 MCLK IS 256 x Fs e 9 48 kHZ SAMPLE RATE I S I F MODE 5V ASV ASV O O O R73 C32 2 74K 220PF 1206 T 1206 o C142 C143 C153 0 1UF 04UF 0 1UF T 805 T 805 T 805 AGND AD1854 AD1854 NEAR U8 ANALOG 20 Cotton Road Nashua NH 03063 DEVICES PH 1 800 ANALOGD Titl Approvals Date ADSP TS201S EZ KIT LITE AUDIO OUT Drawn Size Board No Rev C A01 78 2002 110 Engineering Date 3 1 2004 10 59 Sheet 9 of 15 A B C D B C D 3 3V N 3 3V R89 10K 805 LABEL IRO A 3 3V LABEL FLAGO_A R94 R99 O 100 805 e 805 U14 U30 R95 STA S I gt gt MRG AS 7 100 SW4 U14 74LVC14A 74L
14. Drawn Engineerin 8 8 Date 3 1 2004 10 59 Sheet 11 of 15 A B C D 3 3V O K PLACE CLOSE TO OSC R41 All USB interface circuitry is considered proprietary and has 10K been omitted from this schematic 805 3 3V R129 When designing your JTAG interface please refer to the O U2 22 Engineer to Engineer Note EE 68 which can be found at 805 http www analog com loe oui ANN EIN 2 288MHZ e 1 OSC003 1 R182 R213 R214 10K 10K 10K R186 805 805 805 4 7K 805 PLACE CLOSE TO FPGA R205 22 3 3V U22 805 O R181 r A NANA EE 1 2 u 0 00 L Mea AMAYA MOLES I IDA YA 805 3 LEE R206 USB TMS gt A T ANN 5 MS 22 5 7 805 108 YB R210 L BOK C NNN Ms 1 USB TEK gt Sing V YY ival8 HI R207 D IOC vc A A2 AL NNN gt ITRST Sob R203 R187 USB TRST gt c S143 watt o bor AAAA 1 10K 10K 14 12 8 12 805 I LRELKI C AAAA HSC 805 805 10D YD 1A4 vd 3 3 USB TDI gt Sip d 1 b Ee Lum IDO PAI xi 0 00 ue US Ries
15. EMU aas aya o D 0 23 i 2 Ri N se i MIR wee op 805 PAS NI R212 I RD gt AUDIO RD AUDIO DO 17 b 0 00 w AUDIO WRL AUDIO Di Aue e 2 FT FLAGS Al gt AUDIO EN AUDIO D2 Joe m o i DMARO lt EMADUIO_DMAR AUDIO_D3 3 a ez o L MSI gt Milan SELECT AUDIO D4 5 b a SN7ALVTZ4ADW IC2 AUDIO D5 7 b T SOIC20 e i DT lt LS AUDIO pour AUDIO_D6 g 10 2 M jela se L14 IOA YA I DR gt AUDIO DIN AUDIO D7 1 12 tT 3 pronus id T5 e USB EMU lt HA L BCLK SI AUDIO BCLK AUDIO D8 13 14 5 7 rittene ci e 10B Y i LROLK S AUDIO LRCLK AUDIO D9 mass 6 SCENE 7X2 USB TDO MB U37 R184 AUDIO D10 e 1 b 0 00 er e oc YC 805 1 MCLK sa uni MCLK AUDIO D11 10 10 gt u tn Lea P eem o 110 IN A OUT MENN TER DSP A I AUDIO_D12 14 42 Be ee E fan N Z oD Kg 3 3V OUT A2 R185 L AUDIOCLK M ao CLK AUDIO D13 13 a A 0 00 GE HD OUT_A3 805 AUDIO Di C H 2 ABBA HERE ANN RR fetale SI DSP JTAG HEADER f OUT A4 HOKDSPB 1 AUDIO_D15 S 9 Gr VEE b sie 15 e OE A OUT AB AUDIO D16 e E AUDIO D17 AUDIO D18 QSOP16 ia IN B our Bill ES our pat _ AUDIO D19 17 OUT_B3 AUDIO_D20 15 OUT B4 AUDIO D21 m 120E p OUT pell PLACE CLOSE TO FPGA PINS CRITICAL 805 AUDIO D22 L DSP RESET lt AAA lt bsp RESET AUDIO_D23 ha A DNP MONT 3 3 ni ia pmo P LA DATOO gi gt BANA KA 77773 sa ee ss m 805 31 A DATIO N LA DATOO NM4 LLODATIO
16. NA 1 Becket LODATOO PAR AMAYA MR a ml MLA CLKIN P LA CLKO PF gt ILOCLKNPA 1 se se se 3 100 DD LA cun N LA CLKO NF gt ALOCLKINNA ____1 v EE TE ON n 805 I L3 A ACKO LA ack C ILOACKO A O I LOCLKOUT P AH AAA Re eege en SEE E A i i MARRON LA BCOMPO gt T OBCMPLA____ R208 100 De paro P LB DATOO p gt paro P_B_____1 cis 610 cia oss passes EE i e pario N LB DATOO N gt LODATIO_N B 1 m oo E E mE or ne AE L_IDOAIL gt 1 V VM I wem sm 3 LODATOO P Bik Ko ll 2 SSS gt 8 CLKIN P LB CLKO P gt ILOCLKIN P B OJ fij I D ON LB cuo N Z Diane mica rat m 805 Es HI B acko LB ACKPI lt ILOACKO B _ LOCLKOUT P BE HA ee rs sss cba s io cow LB BCOMPOK gt ILOBOMPIB____ SC L TDO lt 12 288MHz IDT74FCT3244 093257 053257 ANA I OG I 20 Cotton Road Nashua NH 03063 4 DE V IC ES PH 1 800 ANALOGD 4 Title Approvals Date XC2STSOE ADSP TS201S EZ KIT LITE JTAG FPGA Drawn Engineerin 8 8 Date 3 4 2004 11 17 Sheet 12 of 15 A B C D
17. gt H3BOMPO B R 2 5V DSP B 2 5V DSPA BP576 O BP576 O ANALOG Cotton Road R235 R236 R237 R238 Nashua NH 03063 R108 R116 R119 R153 10K 10K 10K 10K DE V ICES 4 2nn 10K 10K 10K 10K 805 805 805 805 PH 1 800 ANALOGD 805 805 805 805 DNP DNP Tid itle Approvals Date 77 OBRA loss EL ADSP TS201S EZ KIT LITE DSP LINK PORTS aaa I m I_____kIBCMPIAI m ml sre pek zrele m Drawn ma L ist Si Board No Rev I L2BCMPI A m Ize oar sa j m Checked C A0178 2002 14C i L3BCMPI A BE PAPA er pais ngineerin 8 8 Date 3 1 2004 10 59 Sheet 4 of 15 A B C D A B C D 1V DSP A IV DSP B CN C Cu ar 10UH 10UH 1008 gt 1008 DSP SCLK VREF IN DSP VREF MEN ZZ LM mem lai eli d m AIV DSP A aati pose e AV DSP B ve RR E ETT Rege cat C37 1UF 1UF C44 C46 805 T 805 1UF 1UF TT 805 805 e PLACE CLOSE TOGETHER USE at least 3 vias per connection D S B PLACE CLOSE TOGETHER USE at least 3 vias per connection D S P A 1
18. just log on Your user name is your email address Embedded Processor Product Information For information on embedded processors visit our website at www analog com processors which provides access to technical publica tions data sheets application notes product overviews and product announcements ADSP TS201S EZ KIT Lite Evaluation System Manual xv Product Information You may also obtain additional information about Analog Devices and its products in any of the following ways Email questions or requests for information to dsp supporteanalog com Fax questions or requests for information to 1 781 461 3010 North America or 49 0 89 76903 157 Europe Related Documents For information on product related development software see the follow ing publications Table 1 Related Processor Publications Title Description ADSP TS201S Embedded Processor Datasheet General functional description pinout and timing ADSP TS201 TigerSHARC Processor Hardware Reference Description of internal processor architecture and all register functions ADSP TS201 TigerSHARC Processor Program ming Reference Description of all allowed processor assembly instructions Table 2 Related VisualDSP Publications Title Description VisualDSP 3 5 Users Guide for 32 Bit Proces SOTS Detailed description of VisualDSP 3 5 fea tures and usage VisualDSP 3 5 Assemb
19. 1 R225 PANASONIC ERJ 8ENF1302V 107 2 RED SMT GULL WING LED2 LED8 PANASONIC LN1261C 108 1 GREEN SMTGULL WING LEDI PANASONIC LN1361C 109 2 604 1 8W 1 R74 75 DALE CRCW12066040FRT1 110 6 1uF 25V 20 TANT CT8 13 PANASONIC ECS TIEY105R 111 2 OUICKSWITCH 257 1122 03 ANALOG ADG774ABRQ DEVICES 112 1 IDC7X2 P4 BERG 54102 T08 07 113 1 2 5A RESETABLE Fl RAYCHEM SMD250 2 114 2 3 5MM STEREO JACK P1 2 AID ELEC ST 323 5 ADSP TS201S EZ KIT Lite Evaluation System Manual A 9 s 5 o 2 o a HE dje g e E 2 b 3 2 2 2 QE E v 5 o o v 3 a2 el OO co az 115 5 10uF 6 3V 10 TANT C91 C100 AVX 08056D106KAT2A C154 C163 C164 A 10 ADSP TS201S EZ KIT Lite Evaluation System Manual ADSP TS2015 EZ KIT Lite NTG DEVICES PH 1 800 ANALOGD Approvals Date i ADSP TS201S EZ KIT LITE TITLE Drawn Checked C Board No A 0178 2002 L Engineering Date 3 1 2004 10 59 Sheet 1 of 15 B C D
20. AT49BV040 TSOP86 TSOP86 3 3V N 3 3V N CY KA Na x ANALOG 20 Cotton Road Leste Tom Log Los les Les Less Leto Lote Lom Lem Les DEVICES pri 1 stoavaLo 402 402 402 402 402 402 402 402 402 402 402 402 PH 1 800 ANALOGD Title Approvals Date ADSP TS201S EZ KIT LITE MEMORY Drawn SDRAM SDRAM G LAG Engineerin 8 8 Date 3 4 2004 11 06 Sheet 7 of 15 A B C D B C D O KEEP ALL OF THESE COMPONENTS OVER THE AGND PLANE PLAGE NEAR CONNECTOR CT5 i i Uk z N E INL AMPIN 3 TRY TO KEEP ALL TRACES AS SHORT AS POSSIBLE ELBE AA ANA C16 C20 120PF 100PF 1206 1206 e i 3 3V R52 3 2 U6 237 TER 1206 XK M III AAN e De 3 Se DE 805 e 576K 576K LABEL LINE IN ___VREF AUDIO Me re fodpr ADC LEFT AD C nu Rag 1206 10K Pi 805 805 1 va 5 AUDIO IN LEFT AGND ct U9 NT oi o 0 001UF Er III gt 8 P iain dai SLAVE MODE B LOOPBACK RIGHT 1506 12 APLP b A p TAUBIO IN RIGHT TTT ti j NL ner XOTRL
21. AVX 12065A102JAT2A 16 4 2200pF 50V 5 C22 C24 AVX 12065A222JAT050 C56 57 17 1 O 1uF 50V 20 C5 AVX 12065E104MAT2A 18 1 VOLTAGE SUPERVISOR U5 ANALOG ADM708SAR DEVICES 19 1 3 3V 1 5A REGULATOR VR3 ANALOG ADP3339AKC 3 3 RL DEVICES 20 4 DUALAUDIO OP AMP U6 8 U26 NATIONAL LMV722M 21 1 STERO DAC U3 ANALOG AD1854JRS DEVICES 22 1 STERO DAC U9 ANALOG AD1871YRS DEVICES 23 1 JADJ500MA REGULATOR VR6 ANALOG ADP3336ARM REEL DEVICES 24 2 TigerSHARC ADSP TS201S U11 12 ANALOG ADSP TS201SABP ENG Processor DEVICES 25 4 RUBBER FEET BLACK MH 1 2 MH4 5 MOUSER 517 SJ 5018BK A 2 ADSP TS201S EZ KIT Lite Evaluation System Manual Bill Of Materials r 3 v 2 v 8 2 HE m 5 b el E H b 3 2 g gl 3 t E SLE alya ZA 5 Z 26 1 PWR 2 5MM JACK P3 SWITCH SC1152 ND12 CRAFT 27 7 SPST MOMENTARY 6MM SW3 9 PANASONIC EVQ PAD04M 28 3 10 05 45X2 SMT Ji 3 SAMTEC SFC 145 T2 F D A 29 2 DIP6 SW2 SW10 DIGIKEY CKN1364 ND 30 4 RJ45 8PIN RIGHT ANGLE J4 7 TYCO 1 1609214 1 31 1 4 PIN SMT SWITCH SWI DIGIKEY CKN1363 ND 32 12 0 00 1 8W 5 R76 R91 R104 YAGEO 0 0ECT ND R107 R109 110 R113 R118 R178 179 R189 R202 33 4 AMBER SMT LED3 6 PANASONIC LN1461C TR 34 2 330pF SOV 5 NPO C25 C30 AVX 08055A331JAT 35 4 0 01uF 100V 10 CERM C1 2 C7 8 AVX 08051C103KAT2A 36 15 0 1uF 50V 10 CERM C4 C51 C63 AVX 08055C104KAT C66 C142 143 C145 149 C247 249 37
22. Card for a detailed installation description When installing VisualDSP 3 5 on Windows 2000 ensure the appropriate EZ KIT Lite component is selected for the installation 2 Connect the EZ KIT Lite device to your PC s USB port Windows 2000 automatically detects an EZ KIT device and auto matically installs the appropriate driver for the selected device see step 1 3 Verify the installation by following the instructions in Verifying Driver Installation on page 1 15 Windows XP USB Driver VisualDSP 3 5 installation software pre installs the necessary drivers for the selected EZ KIT Lite The install also upgrades an older driver if such is detected in the system Q Prior to running the VisualDSP 3 5 installer ensure there are no other Hardware Wizard windows running in the background If there are any wizard windows running close them before starting the installer To install the USB driver 1 If VisualDSP 3 5 is already installed on your system go to step 2 Otherwise run VisualDSP 3 5 installation Refer to the VisualDSP 3 5 Installation Quick Reference Card for a detailed installation description When installing Visual DSP 3 5 on Windows XP ensure the appropriate EZ KIT Lite component is selected for the installation ADSP TS201S EZ KIT Lite Evaluation System Manual 1 13 Installation Tasks 2 Connect the EZ KIT Lite device to your PC s USB port By connecting the device to the USB port you act
23. D I L MSH BE e MARS A R6 imin ova SMS o MRD 1 e KE a aos D11 1D22 L BMS BMS IORD ER a I BOFF 87 Ae Alla opR22 DATA22 1 Dee _ ES gt NOEN DMART BB Seg V A23 Bet A11 1D23 idi FE lake e EC ADDR23 DATA23 E I BROZ BRO n iD24 7 EE L4 C20ADDR24 DATA24P D SCH RNET8 17 A251 A10 1D25 m s s E E ADDR25 BR2 DON TT M6 B 1 an I7 381 Bio iD26 p T It 28 C19 DR26 DATA26 BR3 DP KBB 1 5 17 az C10 iD27 pa ene E DATA27 BRA vi lt iB LM Mea 17 4281 D10 iD28 ET RE RETIUM a A20 DDR28 DATA28 BR5 1 DMARLA S COM2 17 TAB A9 ID29 7 De A NEDE EEN 29 B20 DDR29 DATA29 E BR6 SCLKRATOHA J ISCIKRATOB 1 Eus DER Rs 301 B9 iD30 pr ubi sss asss s EENS 2 18 appR30 DATA30 Aer BR7 SCLKRATIME C SCLKRATI_B 1 __ DMAR2BII T Fan Co ID3i oaoa EU 5 P ppra1 DATAS iie SCLKRAT2L lt ISCLKRAT2 B 1 L_BRSI ii A ERRATA SOUPAT B DATA32P9 3 MT P4 i EUM A e 4 BM C ENN rai pala oe Borri gt bopr CONTROLIMPO 4 CONTROLMPO 1 Lo T AA15 B8 1D34 o poleni gt MA m m a 1 IT Baal R8 MO sin ET O BUSLOCK ADSBUSLOCK CONTROLIMP1 CONTROLIMP1 1 ur AB4 Co DATA35 La E p De 44 f f ooo LLLI R21 5 DATA36 1 HBR mo ABR po 4 Den B I A7 D I LZ U4 di DATA37 cessi 17 HBG OE EG DST DSB iD L HB
24. DSP A DSP B DSPA DSP B Use With Position 1 Position 2 Position 3 Position 4 Position 5 Position 6 ZS FLAGO FLAG1 FLAGO FLAG1 IRQ0 IRQO OFF OFF OFF OFF OFF OFF External source ON ON ON ON ON ON On board push button switch 1 Default settings ADSP TS201S EZ KIT Lite Evaluation System Manual 3 9 Configuration Resistors Configuration Resistors This section describes the function of the two TigerSHARC processors configuration resistors The location of the configuration resistors and their respective default settings are shown in Figure 3 3 CONTROLIMP 1 0 DSPB DSPA ty ID 2 0 qj SCLKRAT 2 0 PER Z wc Tue De psPB OU DsPB H DSPA DS 2 0 SCLKRAT 2 0 ID 2 0 DSPA DS 2 0 g teks a Ut Clock Generator Configuration Resistors Figure 3 3 Resistor Locations Bottom View of Board Processor ID Settings The two ADSP TS201S processors on the EZ KIT Lite are factory config ured to set the DSP A to an ID value of zero and DSP B to an ID value of one This means that in the cluster DSP A is the master Although it is not 3 10 ADSP TS201S EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference recommended the ID value of each processor can be varied by placing 500 Ohm resistors in the appropriate position Table 3 10 and Table 3 11 show the available ID settings D tialization of SDRAM external memory Internal pull up or pull downs on certain pins such as memory int
25. MCLK IS 256 x Fs M UN CCLK 256 512 8 e 48 kHZ SAMPLE RATE STEEN Coup e I S I F MODE 5 LM CIN DF1 a fa CLATCHAM S 2 N 7 VINRN AGND 5 DE bapan LRCLKES iLRCLK 1 A Hw Um p MN ad sm E e NY e N NA ANEN CO E A A o min 1 ina E Z I vol MCLK DIN C18 100K oF 1906 L RESET RESET VREF 4 gt IVREF AUDIO 7 1 1206 1206 e l U SSOP28 deu I o us R48 es 2 04UF 10UF 2 237 c a 805 B M 7 7 1 INR AMPOUT S INR 5 AGND Mo AV X L 4 3 I PLACE NEAR CONNECTOR m o c13 c3 Ce SOIC8 Q 001UF 100PF 100PF N Se 805 1206 1206 5 76K 5 76K e o YA 1206 1206 e AGND nn d ADC RIGHT G r Gor cour 601ur i 85 780 1 805 T 805 S 10 0 001UF 3 R46 E i 237 KEEP THESE CLOSE TO AD1871 1206 7 4 4 e NR N i Gg J TMV722M i H J SOIC8 EN NEM m non E fe P4 x E VA E P d THE GND AND AGND PLANES SHOULD GO FROM PIN 8 to PIN 21 of U9 R179 ASV ASV ASV ASV 3 3V 5V 0 00 E O O O O Z O O 1206 AN V x fe Ni imu pe uu ee l WHEN USING AN ELECTRET MICROPHONE 805 me 805 805 805 805 PLACE RESISTOR BETWEEN AD1871 and AD1854 PLACE SW1 1 AND SW1 2 IN ON POSITION PLACE SW1 3 AND SW1 4 IN OFF POSITION 4 2 R E ANALOG 2 coton noai Ca site Nashua NH 03063 AM AO NAG i x xx A X PH 1 800 ANALOGD 4 pa 2 m 7 AUDIO UN ET 77777 E AG D AGND AGND AGND DEVICES pies 3 6 e aa 7 NEARUS NEARU7 NEARU26 AD
26. MRS cycle follows refresh e e e e e O The SYSCON and SDRCON registers define bus control configuration They can be written once only after reset and cannot be changed during system operation In emulation space the SYSCON and the SDRCON registers can be written to as many times as needed The USB debug monitor oper ates in emulation space and allows always writable mode for these registers Using Flash Memory The AT49BV040 chip provides a total of 512K x 8 bits of external Flash memory arranged into eight uniform 64 Kb memory blocks The block addresses are shown in Table 2 2 2 4 ADSP TS201S EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Table 2 2 Flash Memory Map Start Address End Address Content 0x3000 0000 0x3000 FFFF Uniform Block 0 0x3001 0000 0x3001 FFFF Uniform Block 1 0x3002 0000 0x3002 FFFF Uniform Block 2 0x3003 0000 0x3003 FFFF Uniform Block 3 0x3004 0000 0x3004 FFFF Uniform Block 4 0x3005 0000 0x3005 FFFF Uniform Block 5 0x3006 0000 0x3006 FFFF Uniform Block 6 0x3007 0000 0x3007 FFFF Uniform Block 7 To program the Flash memory with your boot code you must first create a loader file from your processor code You set up the loader in Visu alDSP depending on how you plan to boot the Flash For information on creating a loader file refer to VisualDSP online help and the Visu alDSP 3 5 L
27. N A L1BCMPO Al lt p L1BCMPO BI lt E L2BCMPO AI REALLY LTBCMPO BI L2BCMPI AI lt r r ae eee R131 DEFAULT NORMAL L L3BCMPO AI lt L___L3BCMPO BI lt 499 CONTROLIMPO has an internal 5Kohm pull down resistor 805 CONTROLIMP1 has an internal 5Kohm pull up resistor DNP a CONTROLIMP 1 0 Driver Mode R134 R23 R51 R106 R111 R114 00 Normal 499 499 499 499 499 499 L____ CONTROLIMPOI C 10 AD Mode Dip ee E P ET ES CONTROLMP1I DI 11 Pulse Mode A D Mode R143 499 805 aaa I ENEDREG A eae SL a 2 5V 25V s aa a ek L _ _ _ENEDREG B lt O O R25 499 R154 805 499 805 R132 R139 499 499 805 805 DNP DNP DS1 has internal 5Kohm pull down resistor Ta Ds i lt TE DS Bi Fm DS2 and DSO have internal 5Kohm pull up resistors aaa aa eee DS 2 0 Drive Strength OUTPUT IMP __Ds1_Al L Dep 000 11 26 580 AI C i __bso Bi C 010 36 5 40 011 49 2 50 100 61 9 62 101 74 6 70 DEFAULT 110 87 3 96 111 100 120 ANALOG 2 coton Road Nashua NH 03063 D E V IC ES PH 1 800 ANALOGD Title Approvals Date ADSP TS201S EZ KIT LITE CONFIG Drawn Engineerin 8 8 Date 3 4 2004 10 58 Sheet 6 of 15 A B C D A B C D LABEL SDRAM LOW LABEL SDRAM HIGH ma I A 0 1
28. Rev Checked C A0178 2002 1 1C Engineering Date 3 1 2004 10 59 Sheet 3 of 15 A B G s A B C D DSPA DSP B ALL NETS ON THIS PAGE EXCEPT L ACK and L BCMP ARE DIFFERETIAL PAIRS zia TE a 7 andL 7 I Da Link Port 1 EXP INT EXP INT THESE SIGNAL SHOULD BE ROUTING ACCORDING THE GUIDELINES SET IN EE 179 Link Port 2 DSP B DSPA Link Port 3 RJ45 RJ45 2 5V DSP A 2 5V DSP B Y Y DSPA DSP B U11 U12 PLACE CLOSE TO DSP A PINS CRITICAL 1 god VP A A ba a L_____LODATIO PA J24 opatio p LODATOO PF21 gt ILODATOO PA 1 PLACE CLOSE TO DSP B PINS CRITICAL L_____ LODATIO_ PB 4 patio P LODATOO PP24 gt LODATOO PB _ 1 oc L ve LODATIO N A 23 ODATIO N LODATOO N 25 gt LODATOO_N I A 1 F Tres LODATIO_N BI gt S opar ON LODATOO N gt LODATOO_N_ B o TT 1 eee EE JE PE a e opar p LODATO1 PP22 m e 2 opar p LODATO1 PP22 LODATIO P Ai IEAA LODATIO N A I m DZ e K LODATI1_N LODATO1 N aspas m sss a 805
29. System Manual Found New Hardware Wizard Windows 2000 1 14 G general purpose IO xi H Help online xvii 2 9 host 2 3 I installation summary 1 3 installing EZ KIT Lite USB driver 1 7 VisualDSP and EZ KIT Lite license 1 5 software 1 4 interface connectors xi internal DRAM power regulator 3 2 memory 2 2 2 3 3 4 interrupt enable settings 3 8 mode switch SW10 3 9 modes 3 8 pins 2 6 3 18 push buttons SW4 SW5 3 18 IO xi power regulator 3 2 push buttons 3 18 IRQO A SW4 interrupt pin 2 7 3 18 IRQO B SW5 interrupt pin 2 7 3 18 INDEX J JTAG emulation port 3 4 emulator x header 3 21 jumper settings 1 5 L LOCLKIN pins 2 8 LEDs 1 5 LED1 power 1 6 3 16 LED2 USB reset 1 6 3 17 LED FLAG3 B 2 5 2 6 3 17 LED4 FLAG2 A 2 5 2 6 3 17 LED5 FLAG2 B 2 5 2 6 3 17 LED6 FLAG3 A 2 5 2 6 3 17 LEDS processor reset 1 6 1 15 3 17 LEDO USB mono dels TA 3 17 license restrictions 2 2 link ports 2 8 3 8 loader file 2 5 LVDS signaling 2 8 M master processor 3 10 memory blocks see flash memory map see ADSP TS201S processor microphone 3 6 ADSP TS201S EZ KIT Lite Evaluation System Manual I 3 INDEX N networking cable 2 8 noise 2 8 O oscillator U18 3 3 3 12 P package contents 1 1 PC configuration 1 3 peripheral interfaces 3 21 power connector P3 3 20 LED LEDI 3 16 supply 3 22 processor ID 2 3 3 10 pro
30. is a high performance single chip stereo audio DAC deliv ering 113 dB dynamic range and 112 dB SNR at a 48 kHz sample rate Because the ADSP TS201S processor does not have any SPORTS an Xil inx field programmable gate array FPGA generates the audio interface control signals between the processor and the audio circuit Setting the FLAG3 signal of DSP A high enables the audio interface inside of the FPGA Once the audio interface has been enabled the audio data can be transferred to and from the processor by generating a DMARO cycle The audio data interfaces with the processor via the lowest 24 bits of the data bus D23 0 Refer to the audio example program included in the EZ KIT Lite s instal lation directory for more information on how to use the audio interface Refer to Audio P1 2 on page 3 20 for information about the audio connectors ADSP TS201S EZ KIT Lite Evaluation System Manual 2 7 Using Processor Link Ports Using Processor Link Ports The link ports on the ADSP TS201S processor use LVDS signaling to communicate with each another Each processor has a TX transmit port and RX receive port for each of its link ports The RJ 45 connectors J4 and J5 are the TX and RX for DSP A Similarly J6 and J7 are TX and RX for DSP B The TX and RX of one processor s link ports should be respectively connected to RX and TX of another processor s link port In this manner the TX of one processor connects to the RX of the
31. lit for a few seconds and then turns off Connect the USB cable to the evaluation board After the RESET LED8 turns off verify that the yellow USB mon itor LED LED9 is lit This signifies that the board is communicating properly with the host PC and is ready to run VisualDSP Verify that the USB driver software is installed properly Open Windows Device Manager and verify that ADSP TS201S EZ KIT Lite shows under ADI Development Tools with no excla mation point as in Figure 1 12 If using an EZ KIT Lite on Windows 98 disconnect the USB cable from the board before booting the PC When Windows 98 is booted and you are logged on re connect the USB cable to the board The operation should continue normally from this point ADSP TS201S EZ KIT Lite Evaluation System Manual 1 15 Installation Tasks Device Manager n x File Action View Help e mim m E S WISELABS EB ADI Development Tools Sai ADSP T52015 EZ KIT Lite e d Computer o ze Disk drives 1 5 Display adapters FE DSP Emulators El DVD CD ROM drives 66 3 Floppy disk controllers H Floppy disk drives FE 4 IDE ATAJATAPI controllers FE up Keyboards E Mice and other pointing devices E Monitors EEE Network adapters E Ports COM amp LPT ESR Processors o E Sound video and game controllers E System devices E Universal Serial Bus controllers Figure 1 12 Device Manager Window Starting VisualDSP To set up a s
32. other processor The link ports should be connected using a standard CAT 5E networking cable The length of the cable may affect the maximum frequency at which the data can be transferred Refer to the ADSP TS201S Embedded Proces sor Datasheet for more information There are four link ports on each of the processors on the EZ KIT Lite Link Porto of both processors connects to the field programmable gate array FPGA at U20 Link Port1 of both processors connects to J3 of the expansion interface Link Port2 of each of the processors connects to each other Finally Link Port3 connects to the RJ 45 connectors J4 J7 The LOCLKIN P of both DSP A and DSP B are pulled up internally in the FPGA Similarly LOCLKININ_N of both DSP A and DSP B are pulled down internally in the FPGA Finally R12 and R28 are not populated All of this is done to avoid noise affecting the EZ KIT Lite operation To suppress noise from the expansion interface a similar pull up or pull down scheme has been used on Link Portl The board s R240 and R239 are used to pull up LICLKIN_P of both processors Similarly R242 and R241 are used to pull down LICLKIN_N of both processors Finally R14 and R30 are not populated to avoid a short between 2 5V power and GND The link ports can be reactivated by removing the pull up and pull downs and adding a 100 Ohm resistor on R14 and R30 2 8 ADSP TS201S EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Example Progr
33. seas I HDOMI lt DOM TDI iyi pr P e FLAG 3 0 A I TDO AI lt Wo DATAS EG sve KI Ho I SDA101 lt SDA10 I TMS o Atras DATA46D slet sete Ko Sv 33V zoo AD4L C5 L SDCKEI lt SDCKE FLAG2 PLACE CLOSE TO DSP PINS TRST 2 RST DATA47 zoro LL r D5 L SDWE lt SDWE FLAG3 for DATA48 I SCLK DSP Al gt ha es ie sla nk DATA4J a HO o U1 Bu 15577 rn MSSDI0 3 SSD0 IRQ 3 0 A bi be DATA50 MSSD1i 0 00 0 00 A2 MSSD1 805 805 DATAS1 MSSD2i C108 C107 C103 C104 C141 C4 Mr 0 1UF gor 0 01UF 0 01UF 0 1UF DATA52 MSSD3 402 402 402 402 TT 402 P1 Bi 15 1 MN oo M MSSD3 SCLK1 DATA53 e Deck DATA54P gt e e T T asso BP576 10PF 10PF D2 805 805 DATA56 DNP DNP TN E N Z Uu o nass IDT5V928PGI 20MHz i DSP RESET Oo RSTAN DATASI N A DATAGO 4 RI U RST OUT DATAGI 0 00 E2 Ee is A N A LO G 20 Cotton Road POR IN DATA63 NNN POR Nashua NH 03063 4 i DE V IC ES PH 1 800 ANALOGD BP576 Title Approvals Date ADSP TS201S EZ KIT LITE DSP A Drawn Size Board No Rev Checked C A01 78 2002 1 1C Engineerin 8 8 Date 3 1 2004 10 59 Sheet 2 of 15 A B C D U
34. speed at which the core operates is determined by pull up and pull down resistors on both the clock generator U1 and the SCLKRAT 2 0 bit of each of the processors For more information see Clock Mode Settings on page 3 12 By default the processor core runs at 500 MHz 20 MHz x 5 U1 x 5 sclkrat 500 MHz External Port The external port EP connects to a 512K x 8 bit Flash memory The Flash memory connects to the boot memory select pin BMS and memory bank zero pin MS0 allowing the memory to be used to boot the proces sor as well as to store information during normal operation Refer to Using Flash Memory on page 2 4 for information about the Flash mem ory locations The EP also connects to a 4M x 64 bit SDRAM Refer to Using SDRAM Interface on page 2 4 for information on how to configure the SDRAM registers Expansion Interface The expansion interface consists of three connectors The following table shows the interfaces each connector provides For the exact pinout of these connectors refer to Appendix B Schematics ADSP TS201S EZ KIT Lite Evaluation System Manual 3 3 System Architecture Table 3 1 Expansion Interface Connectors Connector Interfaces JI 5V GND Address Data J2 2 5V GND SDRAM control signals FLAGs IROs TIMERs Data J3 GND Reset DMA Memory Control CLKOUT Link Ports signals When you use the expansion interface limits to the current and
35. the processor s external port EP Purpose of This Manual The ADSP TS201S EZ KIT Lite Evaluation System Manual provides instructions for using the hardware and installing the software on your PC The manual provides guidelines for running your own code on the ADSP TS201S EZ KIT Lite This manual also describes the operation ADSP TS201S EZ KIT Lite Evaluation System Manual xi Intended Audience and configuration of the components on the evaluation board Finally a schematic and a bill of materials are provided as a reference for future ADSP TS201S board designs Intended Audience This manual is a user s guide and reference to the ADSP TS201S EZ KIT Lite evaluation system Programmers who are familiar with the Analog Devices TigerSHARC processor architecture operation and program ming are the primary audience for this manual Programmers who are unfamiliar with Analog Devices TigerSHARC pro cessors can use this manual in conjunction with the ADSP TS201 TigerSHARC Processor Hardware Reference and the ADSP TS201 Tiger SHARC Processor Programming Reference which describe the processor architecture and instruction set Programmers who are unfamiliar with VisualDSP should refer to the VisualDSP online Help and the Visu alDSP user s or getting started guides For the locations of these documents refer to Related Documents xli ADSP TS201S EZ KIT Lite Evaluation System Manual Preface Manual Contents Th
36. zack LACK ASKO A R19 ADA BCMPI tBoMPOPC gu ILBBCMPO A R98 ADA BCMPI Geescht e 2BOMPLA 1 100 100 805 805 LL LO PA AAA ZETA SDATIO P L3DATOO PASS gt SDATOO PA ____i EKOUT P AA zi KOO NA TT DATO PB DA spato P L3DATOO P gt ESDATOO PB ACI par N LaDATO0 NC IC AR O par v LaDATO0 MC gt NE I e 4814 spart P L3DATO1 P S10 e 4814 spart P L3DATO1 P 810 e AMA spar N LaDATO N ATO id e AMA spar N LsDATO1 N ATO e 4815 spare p L3DATO2 pAD1 e e 805 ann Neo e BS spar p L3DATO2 PAPI L3DATIO P Bill ANA Y DAT N B 1 e D IN apati N L3DATO2 NAC Hesse SE Mk e apati N L3DATO2 NAC iod e 212 spart p L3DATO3 PAS e 212 spart p L3DATOS3 PAST PENE 895 PTE NA eE 4 AGIZ 3DATIS N L3DATO3 NAAM A ASIZ spATI3 N L3DATO3 Mil L3DATIO P AI AVNA N A 3DATIO N A m ae TE EEE L meters NT NTN I ee de Zx zre nan me LSCLKIN PA gt AD18 scikin P L3CLKO PAD10 gt IL3CLKOUT P A 1 persia sa ll PREJE ZEM ee cuan PBI DP scLKIN_P L3CLKO P P10 gt IL3CLKOUT P B SVEN pk AC13 AC10 gt de o tal to L L3CLKIN P BI AJA MOILSCLKIN N B etnia AC13 AC10 rn en fee oe on R21 TOMO L3CLKIN N Al gt A3CLKIN N L3CLKO N gt ILBCLKOUTNA MEM co ccc ccc a ii L_____LSCLKIN NB gt LL3CLKIN_N L3CLKO_N gt ILSCLKOUT NB m nen M zen Lanci DS GACKO B C sacko EE UT CON PAE AAA S K N NA AL LSBOMPLAT DS gone L3BCMPO 7 gt ESBOMPO A LT L88CMPI Bi 5 E L3BCMPO 7
37. 0 000 Digi Key ED90003 ND Mating Connector USB cable provided with the kit Assman AK672 2 3 Digi Key AE1302 ND Expansion Interface J1 3 Three board to board connectors provide signals for most of the proces sor s peripheral interfaces The connectors are located at the bottom of the board For more information about the expansion interface see Expan sion Interface on page 3 3 ADSP TS201S EZ KIT Lite Evaluation System Manual 3 21 Specifications Part Description Manufacturer Part Number 90 Position 0 05 Spacing Samtec SFC 145 T2 F D A Mating Connector 90 Position 0 05 Spacing Samtec TFM 145 x1 Series Through Hole 90 Position 0 05 Spacing Samtec TFM 145 x2 Series Surface Mount 90 Position 0 05 Spacing Samtec TFC 145 Series Low Cost Link Ports J4 7 There are four RJ 45 connectors on the EZ KIT Lite Two connectors are used for Link Port 3 of DSP A and two are used for Link Port 3 of DSP B Part Description Manufacturer Part Number 8 Pin RJ 45 Connector TYCO 1 1609214 1 Mating Cables BLK CAT 5E Cable 1 Foot E FILLIATE 119 5136 Gray CAT 5E Cable 1 Meter Digi Key AE1233 ND Specifications This section provides the reguirements for powering the board Power Supply The power connector supplies DC power to the EZ KIT Lite board Table 3 21 shows the power connector pinout 3 22 ADSP TS201
38. 0V 1V_DSP_B O O 1 5V DSP B 1 5V Cy CY 1 0V 1V_DSP_A 1_5V_DSP_A 1 5V R110 O O O O 0 00 U12 MEE 1206 U12 R76 UTI es AAA Bnp VDD DRAMI Ad L16 0 00 uit 7VDD2 VDD DRAM2 127 VSS1 VSS78 1206 At Lis VDD3 VDD DRAM3 R113 nog VSS2 VSS79 F10 n22VS81 VSS78 R109 gVDD4 VDD_DRAM4 0 00 A3VSS3 VSS8 g e AAA VDD1 VDD DRAMI n24VSS2 VSS79rg 0 00 gVDD5 VDD_DRAM5 1206 KAT2VSS4 VSS811w10 VDD2 VDD_DRAM2 A3VSS3 VSS80r9 1206 VDD6 VDD DRAM6 KADINSSS VSS82y R91 VDD3 VDD DRAM3 AA12VS84 VSS81MT0 VDD7 VDD_DRAM7 AA4VSS6 VSS83iy 0 00 gVDD4 VDD_DRAM4 AANER VSS82y e AAA gVDD8 VDD_DRAM8 78 ABTVSS7 VSS84y 1206 gVDD5 VDD_DRAM5 AA4VSS6 VSS83y gVDD9 VDD DRAMSK 1g ABT2VSS8 VSSB5 y12 VDD6 VDD_DRAM6 ABTVSS7 VSS84iy VDD10 VDD DRAM Or 18 AB15VSS9 VSS86jy s AAA VDD7 VDD DRAM7 KBToVSS8 VSS85w11 VDD11 VDD DRAM11r7g AB2VSS10 VSS87w gVDD8 VDD_DRAM8 ABT5VSS9 VSS86V P9 VDD12 VDD_DRAM12p78 P12 AB22VSS11 VSS88VT7 gVDD9 VDD_DRAM9 AB2VSS10 VSS87MT6 1 gt G17VDD13 VDD_DRAM13p7g 1 p AB3VSS12 VSS89 y 2 oVDD10 VDD DRAM10 AB22VSS11 VSS88y Fd GTEVDDI4 VDD_DRAM14p7g 4 AC2VSS13 VSS90y VDD11 VDD DRAM11 AB3VSS12 VSS89y IDC2x1 gVDD15 VDD_DRAM15 IDC2X1 AC23VSS14 VSS9 ra P8 VDD12 VDD_DRAM12 AC2VSS13 WER 2X1 VDD16 VDD_DRAM16 2X1 AD1VSS15 VSS92 po VDD13 VDD DRAM13 AC23VSS14 VSS9 ra DNP VDD17 VDD DRAM17 DNP AD2aVSS16 VSS93N10 4 GTEVDDI4 VDD DRAM14 AD1VSS15 VSS921yg gVDD18 VDD DRAM18 B2VSS17 VSS94N IDGS gVDD15 VDD_DRAM15 AD24VSS16 VSS9
39. 1 and CONTROLIMPO resistors set the impedance and driver mode of the processors as described in Table 3 15 The resistors are used together with the drive strength pins to determine the actual impedance and drive strength Refer to the ADSP TS201S Embedded Processor Datasheet for more information Table 3 15 Control Impedance Selection R143 CONTROLIMP1 R131 CONTROLIMPO Driver Mode Populated Not populated Normal Populated Populated Pulse mode Not populated Not populated A D mode Not populated Populated Pulse mode A D mode I Default settings 3 14 ADSP TS201S EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Drive Strength Selection The DS 2 0 pins of each processor determine the digital drive strength as described in Table 3 16 and Table 3 17 Refer to the ADSP TS201S Embedded Processor Datasheet for more information Table 3 16 Drive Strength Setting for DSP A R136 DS2 R132 DS1 R135 DS0 Drive Strength Output Impedance Populated Not populated Populated 11 1 260 Populated Not populated Not populated 23 8 320 Populated Populated Populated 36 5 400 Populated Populated Not populated 49 2 500 Not populated Not populated Populated 61 9 62Q Not populated Not populated Not populated 74 6 70Q Not populated Populated Populated 87 3 96Q Not populated Populated Not po
40. 12 scalza LABEL DSP B near this DSP FLAGS gt Re i Ao D17 DO L 20 H24 DDRO DATAO C ATI 1 E ATI H23 ca UN SE er ADI B17 D2 L A2 H22 ppR2 DATAZ L A L AS Hel bas Dara DE 25V 25V i Ad D16 jD4 O za L Ad D nn DATA4 a ARI L AS G23 pprs para S DE 47K A6 B16 ID6 gr de NM DATAG 1D6 i BRO i A7 G21 C15 D7 BRY Eats ADDR7 DATA AB L AS FA ppns DATAS D Sie DA I A15 jD9 L AS Fi pro patag Ba ABRE AYNA TAO Sl LAO E24 ppR10 DATA EE U12 I avla ipti AN E29 operi bara SEU 2 5V EE B14 iDT2 7 SEE _A12 F22ADDR12 DATA12 VED C1855 PA oOo iCPA O zni Cia DIS one AS F 1 DDR13 DATA13 CWD gt MB DPAPD7 lt BRA 57 4 DIFU xem ps A Pia DATA14P 1 ee Maer ma IT Aib E21 A13 1D15 dren 17 AA7 r _ O NS 2 13 me Ce CO hack Dan lt iDMARO rs COM ACK 4 _BR3 _A16 D24 DDR16 DATA16 E de BRST lt gt Di er DMARIBB7 4 IDMARIB I BR2 200 com2 e 17 47 OI LB a _BR2 A D29 DDRI7 DATA17 2 DU z DMAR2 O DESS 1 BATIN ds 1481 D12 iD18 ir E e 318 52 DDRI8 DATA18 aa Tia TEN DMA MARS P I ee 4 znam a zt L MS0 lt M80 Oo O DMARs amp IDMARS_B X I SDCKEIE n4 IT TAST D22 DATA19 1 ID19 dmi iod se LE d mmo DAS or L MSI i DMAR2 Al R5 I A201 C21 B12 ID20 Ne eed pe hcs lt r 7 ADDR20 DATA20 os I SH IOWR gt lIOWR I ABT A23 C11
41. 1871 AD1871 AD1871 Title SE JM KEN jm eege Approvals Date a EO aka SR ADSP TS201S EZ KIT LITE AUDIO IN SO DIP4 Na Drawn EE V LL INLCAMPINIBE AA Z Checked je SE A0178 2002 i C Engineering Date 3 4 2004 10 58 Sheet 8 of 15 B C D KEEP ALL OF THESE COMPONENTS OVER THE AGND PLANE e R65 C27 5 49K 100PF 1206 T 1206 R62 R66 11 0K 3 32K 1206 1206 eoe e e THE GND AND AGND PLANES SHOULD GO FROM PIN 10 to PIN 20 of U3 DAC LEFT pe 330PF CT7 R74 805 2 U8 68UF BT m E 1308 A 100PF 1 m D C 1206 e 3 us 660PF Deen R64 805 R67 106 48 emm s OE 1208 1808 e 5584 256 Gimn SR e e e X2MCLK L MCLKI Z MCLK pipa SUE 1 BOU gt ac k Sum gt OM 2 JAK mE PE PUR E 1206 1206 se 27 14 LABEL LINE OUT i DT SDATA FILTR FILTB 9 LL e ad 4 r VREF AUDIO gt e se p EE kek o ERE 3 bo Ten C5 ccn 5 LATCH ZEROL Z 10UF Ou 10UF ii L e _ CDATA zEROR S 1808 3 er L_____LOOPBACK LEFT C EN LOOPBAGK RIGHTI 3 O FI 1 I RESET P RESET i ex TOK pri STEREO JACK 9 31 808 DEEMP 5 49K 100PF e mute 1206 1206 S R61 R71 21 AGND 11 0K 3 32K IDPMO 1206 1206 e ppi
42. 2 C226 C217 C215 C214 C213 C232 C227 C229 C228 C230 C231 2 0 01uF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 4 0 1uF 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 1 100uF 2 5V DSP A 2 5V DSP B FA C e e e e e e e e e e e e e e e e e e e e e VDD 10 2 5V Bypass Caps per DSP 8 1nF 2 0 01uF C194 C193 C192 C191 C190 C189 C188 C186 C181 C183 C182 C187 C185 C184 C234 C246 C236 C245 C233 C244 C243 C235 C242 C240 C241 C237 C238 C239 4 0 1uF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 1000PF 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 1 100uF 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 e e e e e e e e e e e e e e e e e e e e e ANALO I 20 Cotton Road Nashua NH 03063 DE V ICES PH 1 800 ANALOGD Title Approvals Date ADSP TS201S EZ KIT LITE DSP BYPASS Drawn Engineerin 8 8 Date 3 1 2004 10 59 Sheet 14 of 15 A B C D A B C D 3 3V 3 3V O O U20 RI 5RO
43. 21 e e El2ycCINT6 GND22 gt e e M5yccINT7 GND23 e e MA ccinte GND24 e NiyccINT9 GND25 e e NISyVcCINT10 GND26 e e NCONT11 GND27 e PIAVCCINTI2 GND28 _e FT256 ANALOG 20 Cotton Road Nashua NH 03063 DEVICES PH 1 800 ANALOGD Title Po Klek ADSP TS201S EZ KIT LITE CONTROLLER Drawn Checked C Board No A0178 2002 LE Engineering Date 3 1 2004 10 59 Sheet 15 of 15 A B C D I INDEX Symbols BMS boot memory select pin 2 3 3 3 MSO memory bank zero pin 2 3 3 3 A AD1854 x 2 7 AD1871 x 2 7 Add New Hardware Wizard Windows 98 1 8 ADSP TS201S processor clock freguency 3 12 core speed 3 3 core voltage 3 3 drive strength 3 15 driver modes 3 14 external Flash memory 2 3 impedance selection 3 14 input clock 3 3 internal memory 2 2 memory map 2 2 pm memory restrictions 2 2 SDRAM interface 2 3 amplification 3 6 analog to digital converters ADCs 2 7 audio amplification 3 6 connectors P1 P2 3 20 data transfer 2 7 interface xi 2 7 see also AD 1854 see also AD1871 B bill of materials A 1 board peripherals x boot code 2 5 memory select pin MS0 3 3 memory space 2 3 strap settings 3 7 broadcast 2 3 bus control configuration 2 4 C clock frequency 3 12 generator Ul 3 3 3 12 modes 3 12 ratios 3 12 configuration resistors 3 10 connecting EZ KIT Lite board 1 5 conne
44. 23 22 Dari P L1DATO3 pW24 Bo e 22 IDATI3_P L1DaTog pW24 e P ipaTIS N LIDATO3 NW28 e 21 IDATI3 N LIDATO3 N23 E U22 eL P L1iCLKO pW22 gt ILICLKOUT PA 1 oo 072 cikin P L1CLKO P DNE ioun N LIGLKO NP gt ILICLKOUTNA Sek cikin N LICLKO_N AANV 129 1ACKO nacke 0 Lacka UI UL LICLKIN P Bi LICLKIN N B 123 1ACKO L1ACKI T24 1BCMPI L1BCMPO 22 gt ILIBCMPO A 124 BCMPI L1BCMP R15 R36 be AD21 gt patig P L2DATOO p le mi L2DATOO PA 1 don AD naro P L2DATOO P HEG ANA AY pario N Leoaroo AS WAT C77 DDATOT PA ASE para N L2DATOO N R16 AB20 ATH P L2DATO1 por e DATO E A i R43 AB20 part P L2DATO1 P he BAZO DDATH N L2DATO1 N EDAT NA Ci aoe AZO oDATIIN L2DATO1_N Wu o AD20 AD18 i ze 3 onto AD20 L2DATH P AI AMA Ai 2DATI NA 2DATI2 P L2DATO2 P EE IL2DATO2 PA L____ L2DATOI P AUI A I L2DATI2 P L2DATO2 P RI7 AC20 opar 2N L2DATO2 NA n L2DATO2NA 1 R83 AC20 spar 2N L2DATO2_N NO he AD19 5 ATIS P L2DATOS PP 9 Eri AI Be AB S opatig P L2DATO3 p pm L2DAT TB PA SMI i AC19 W in m 1 nom AC19 AA18 m 1 DATE PA BH A A AMY 2DATI3_N L2DATO3 N W 2DATO3NA o 1 TT IZDATO2 P All A N Ai 2DATO NA LY 2DATI3 N L2DATO3N II 2DATISNA 1 nis ASTA cru P uoo pP A A ABTS oLan P uoo T ERAN A TT 805 ART 2CLKIN N izotko NAA Edge 805 AA NN Loun NA sn N iun C2DATIS EAR A AB th cKo LACK BIER O m PAN M V AB21
45. 3NT0 G VDD19 VDD DRAM19 B22VSS18 VSS95N 2X1 VDD16 VDD_DRAM16 2x1 B2VSS17 VSS9AR HTgVDD20 VDD_DRAM20 B23VSS19 VSS96N DNP VDD17 VDD DRAM17 DNP B22VSS18 VSS95N H1gVDD21 VDD_DRAM21 2 5V DSP B B3VSS20 VSSI7NTA gVDD18 VDD_DRAM18 B23VSS19 VSS96N 6 VDD22 VDD DRAM22y mi Z VSS21 VSS98N GavDD19 VDD DRAM19 B3VSS20 VSS97NT4 H7VDD23 VDD DRAM23 VSS22 VSSIINTE HTgVDD20 VDD_DRAM20 2 5V DSP A VSS21 VSS98N gVDD24 VDD DRAM24 VSS23 VSS100N HTgVDD21 VDD DRAM21 SE VSS22 VSSIINTE gVDD25 VDD DRAM25 VSS24 VSS101R H6VDD22 VDD DRAM22y VSS23 VSS100N VDD26 VSS25 VSS102Ng H7 VDD23 VDD DRAM23 VSS24 VSS101n VDD27 AB23 D13VSS26 VSS103N9 gVDD24 VDD_DRAM24 VSS25 VSS102Ng KevDD28 VDD ies D21VSS27 VSS104p79 gVDD25 VDD_DRAM25 D13VSS26 VSS103N9 K7VDD29 VDD_IO2A DaVSS28 VSS105p a VDD26 p21VSS27 VSS104p7g gVDD30 VDD 103A03 VSS29 VSS106p VDD27 AB23 DaVSS28 VSS105p VDD31 VDD 1O4ap2z gVSS30 VSS107p KevDD28 VDD 10 tap gVSSs29 VSS106p ure VDD32 VDD n 0VSS31 vSS108pr K7VDD29 VDD 102 gVSS30 VSS107p vg DZ VDD 106523 25V VSS32 VSS109p75 gVDD30 VDD 103A03 25V 0VSS31 vSS108pr via VDD34 VDD 107524 A VSS33 VSS110p VDD31 VDD Oder A VSS32 VSS109p 7 VDD35 VDD IO8E10 gVSS34 VSS111p77 ure VDD32 VDD lO5ap VSS33 vSS110prg NTSVDD36 VDD 109 VSS35 VSS112p viT9VDD33 VDD 106523 gVSS34 VSS111p N19 VDD37 VDD 1010 VSS36 VSS113pg vig V DD34 VDD 107 VSS35 VSS112p NevDD38 VDD 1011 H1VSS37 VSS114pg 7 VDD35 VDD IO8E10 VSS36 VSS113pg N7VDD39 VDD IO12pr HT0VSS38 VSS115p NT
46. 4 10 001uF 50V 5 NPO C10 11 C13 14 AVX 08055A102JAT2A 38 2 10uF 16V 10 TANT CT22 23 SPRAGUE 293D106X9016C2T ADSP TS201S EZ KIT Lite Evaluation System Manual A 3 P v 2 v z HE lt 5 g s 8 E bb s 2 ZS E FRE NA ZA AZ 39 39 10K 100MW 5 R3 R26 AVX CR21 103J T R39 42 R77 R86 87 R89 R92 R94 R100 R102 R108 R112 R116 R153 R158 160 R182 183 R187 R194 R195 R203 R213 215 R223 224 R235 236 R238 242 40 4 4 7K 100MW 5 R5 R98 R186 AVX CR21 4701F T R188 41 1 110 7K 1 8W 1 R217 DALE CRCW1206 1072FRT1 42 1 110 5K 1 8W 1 R227 BECKMAN BCR1 81052FT 43 6 2 00K 1 8W 1 R37 38 R88 DALE CR32 2001F T R121 R156 157 44 2 49 9K 1 8W 1 R60 R63 AVX CR32 4992F T 45 12 100pF 100V 5 NPO C3 C6 C9 C12 AVX 12061A101JAT2A C15 C20 21 C23 C27 C31 C52 53 46 3 10uF 16V 10 TANT CT1 3 AVX TAJB106K016R 47 1 3A SCHOT_RECT D2 MICRO SEMI HSM350J 48 6 100 100MW 5 R78 R85 R95 AVX CR21 101J T R99 R101 R103 A 4 ADSP TS201S EZ KIT Lite Evaluation System Manual Bill Of Materials 9 v 3 v 3 2 HE se 5 SI 8 b E 2 H ii U si eloo BA gt SZ 49 3 220pf 50V 10 NPO C28 C32 C62 AVX 12061A221 AT2A 50 1 2A SILICON RECTIFIER DI GENERAL S2A SEMI 51 5 1600 100MHZ 500MA FER FER1 3 FER6 7 DI
47. 5 sde J6 I bid 56 55 iDt 58 55 iii 58 57 ees c A i HE 579 58 57 iD18 si 58 57 60 5 li 2 Hb D21 60 59 iD20 60 59 62 61 3 LABEL DSP B TX CO2 62 61 iD22 1 62 61 penc 64 63 4 K mn wem mem L Gs 64 63 BET E 64 BB 66 65 5 DSP B TX nor na 89V 3 2133 a gd a aa eee de li HMROER E or O HBR i i 0 68 67 iD28 68 67 L HBG 70 69 7 3 ji ID30 A AS m ee SNO UM ug pa E EE SEL CEA C pe gt AA 73 L BM e gt iji je gt rele Fas z L ROSA lt z d gt REA i L MSO E IRD 1 CON pm T S sise CA O aL gt GE LS es Lm np AR CI W 15 gt EE mp REA ud I ID38 I z zm zm C Gei 78 77 iD38 A 78 77 H 80 79 an i DH 80 79 1D40 80 79 AGRO 82 BI ne Lace C G 82 B1 iD42 1 82 BI 84 83 J7 I D45 84 83 1D44 84 83 r BUCA 86 85 BRST 1 rd ee Sass I_BMAIL 2 BRAST L po 1 DA 86 85 Ga 86 85 88 87 i aS L3CLKIN P Bi lt be _ o M pa dh Hin Mo GREEN bon dod OOO mmm o pm pm pm pm pm pm z zm 2 e 58 87 A 88 87 Jz 90 89 i L3CLKIN N Bi lt LABEL DSP B RX Lexx HENG LSDATIO P Bi C 3 90 89 90 89 MAR AE CON019 4 DSP B RX 45X2 45X2 CONO19 CON019 e L___LSACKO BI 3 em rm pm rem rm rem rm rm ee rm 6 e e m L3DATIO N Bi CI LC D r 7 N N Z NA A 8 Comp ANAI OG I 20 Cotton Road Nashua NH 03063 DE V IC ES PH 1 800 ANALOGD Title Approvals Date ADSP TS201S EZ KIT LITE EXPANSION INT
48. 8 lt gt U24 U25 U10 pec gs a av Ss ex A0 42 13 DO r 1 r 1 r 1 i I Ja AO DO LAM 2540 pad 120 LAN g Dar D CE FAM di 14 mm rj pi i r darli E A1 DI Pl LA Z oof 121 VAZ 26 pa P33 _ z ET e IDE rosa rot r pne A2 pars vE LM jg Dp E LASI jg puc T g ET rial CT ruj s A3 pa 2 LA Bis pag 188 LAM Bs pos JS r 8 i8 D4 PE Ec r sisi Es vi Dal 1D4 MES Mg pose 105 3 Loop d pur P8 KEN 2 ver ET dev n rei al ME A ps DAS 62 10 155 FAG e 10 iD37 A5 DQ5 A5 DQ5 I A6 e bo D6 ben init Sage LAT M AG pe CS L Di 63 A6 pae 1 OG L A 63 pag 1 EE B TAJ 5 pr D rosa ret r L A A7 y Lo LS Me pop D LAM Be por AR 27 ql Ba i raggi Ee AB AB pag Di Le Se pos AI 26 E vn 97 ig vri rr LI A9 LUE Pig poo 3 LG 66 9 poe MA FM amp SCENE m el DOE i A10 i SDA101 24 A10 Denge DIO _ i DATOI 24 A10 pain PE FAR 25 _ SDA10 Sens BE a sene I A11 M ER paje Lo E p 9 Tal A aoa Tr a A12 pe DE bip o TTAB 28 DTT TI EEN EG A13 Bao paige LS BAD paige TAJA 29 EE ERES PE A14 Sen pojas PU bami Fan gp POR a TETI mari E A15 baje o Io Dig gt 2 ii gt FEE ARA siii ES A16 SDRAM CSI ES Doug FT SDRAM cen os pairt EF Re mo arr OZ 71 A mao A17 ener gt ke por S i SDCKELI ke bai BP _ SES i aaa oa a edad mia 7I SE TEA TI JA18 J SDRAM CIR Dok paia BE i SDRAM CLK Der baje 1220 EE y U31 U38 Pan ani DIS TI Rc SR TR MSO w e PE
49. ADSP TS201S EZ KIT Lite Evaluation System Manual Revision 1 0 March 2004 Part Number 82 000770 01 Analog Devices Inc One Technology Way O ANALOG Norwood Mass 02062 9106 DEVICES Copyright Information 2004 Analog Devices Inc ALL RIGHTS RESERVED This docu ment may not be reproduced in any form without prior express written consent from Analog Devices Inc Printed in the USA Limited Warranty The EZ KIT Lite evaluation system is warranted against defects in materi als and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer Disclaimer Analog Devices Inc reserves the right to change this product without prior notice Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli cation or otherwise under the patent rights of Analog Devices Inc Trademark and Service Mark Notice The Analog Devices logo TigerSHARC TigerSHARC logo Visu alDSP the VisualDSP logo CROSSCORE the CROSSCORE logo and EZ KIT Lite are registered trademarks of Analog Devices Inc All other brand and product names are trademarks or service marks of their respective owners Regulatory Compliance The ADSP TS201S EZ KIT Lite evaluation system has be
50. ADSP TS201S EZ KIT Lite Evaluation System Manual 3 19 Connectors Audio P1 2 There are two 3 5 mm stereo audio jacks Part Description Manufacturer Part Number 3 5 mm stereo jack Shogyo SJ 0359AM 5 Mating Connector 3 5 mm stereo plug to 3 5 mm ste Radio Shack L12 2397A reo cable Power P3 The power connector provides all the power necessary to operate the EZ KIT Lite board 7 5V Power Supply GlobTek Part Description Manufacturer Part Number 2 5 mm Power Jack P3 SWITCHCRAFT RAPC712 Digi Key SC1152 ND Mating Power Supply shipped with the EZ KIT Lite TR9CC2000LCP Y 3 20 ADSP TS201S EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference JTAG P4 The JTAG header is the connecting point for a JTAG in circuit emulator pod For more information about designing JJ TAG into a custom board or to learn more about the JTAG interface please refer to EE 68 found at Analog Devices website Pin 3 is missing to provide keying Pin 3 in the mating connector should have a plug When an emulator is connected to the JTAG header the USB debug interface is disabled Q When using an emulator with the EZ KIT Lite board follow the connection instructions provided with the emulator USB P5 The USB connector is a standard Type B USB receptacle Part Description Manufacturer Part Number Type B USB receptacle Mill Max 897 30 004 9
51. AGI B SW7 FLAG2 A LED4 The FLAG2 and FLAG3 pins are connected to the LEDs to supply feedback during program execution FLAG3_A LED6 PP y 8 prog FLAG2 B LED5 FLAG3_B LED3 Using Interrupt Pins The ADSP TS201S processor includes four interrupt pins IR03 0 for interaction with the running program One external interrupt from each processor is directly accessible through push button switches SW4 and SW5 on the EZ KIT Lite board Interrupts are summarized in Table 2 4 For more information on configuring the interrupt pins see the ADSP TS201S TigerSHARC Processor Hardware Reference 2 6 ADSP TS201S EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Table 2 4 Interrupt Pin Summary Interrupt Connected To Use IRQO A SW4 The IRQ0 interrupt is connected to push buttons to supply feedback for program execution For instance you can write your code to perform a different function when an interrupt is detected TRQO_B SW5 Using Audio Interface The audio interface of the EZ KIT Lite board allows you to interface with the board s analog to digital converter ADC and digital to analog con verter DAC The audio interface consists of two main ICs AD1871 and AD1854 The AD 1871 is a stereo audio ADC intended for digital audio applica tions requiring high performance analog to digital conversion The AD1871 provides 97 dB THD N and 107 dB dynamic range The AD 1854
52. D72 VDD 1045y 12VSS73 VSS150ysp TT VDD A2 VDD_1049yg 14VSS75 VSS152y VDD73 VDD 1046y 13VSS74 VSS151y5 8 ieren EE P2 VDD 1050 15VSS76 VSS153yg lio N3 VDD_1047y LTAVSS75 VSS152y p DSP SCLK VREF INI R3S0LK VREF Moa ae NSS77 VSS154 AV DSP AR e Rav DD At VDD_1048yg 115 VSS76 VSS 153 yg TTT Tse SCLK VREF2 VRE e DSP VREF A VDD_A2 VDD 1049yg NSS77 VSS154 MM UNS gt IC P2 z Z BP576 DSP SCLK VREF ME SOLK VREFI ie L posi Ruf e dues HSC VREF VREF e DSP VREF BP576 BERTO NO NE BP576 NZ C45 C39 C43 1000PF 1000PF 1000PF C40 C42 C38 GE JS 1 1000PF 1000PF 1000PF 805 TT 805 TT 805 Te PLACE CLOSE TO DSP B PINS ANALOG 20 coton Road PLAGE CLOSE TO DSP A PINS NU SA EE 4 DEVICES ru 1 800 ANALOGD N Title Approvals Date ADSP TS201S EZ KIT LITE DSP POWER Drawn Engineerin 8 s Date 3 1 2004 10 59 Sheet 5 of 15 A B C D Ri20 R123 R124 499 499 499 805 805 805 DNP DNP i __ID2 AI LIDIA CT i __IDOAI lt DSP A DSP B Default ID 0 Default ID 1 I SCLKRAT2 Al lt Ka si s a SS DSP A I SCLKRAT2 BI lt Es ge E na E pa m kas Sech n R133 R45 499 499 805 805 DSP B ID 2 0 have internal 5Kohm pull down resistors ID 2 0 Proc ID 000 U 001 1 010 2 011 3 100 4 101 5 110 6 111 7 THESE RES
53. Enable OE cn 3 8 Mae Port ei 3 8 FLAGs and IRQs Switch Settings SV ID uuu rinc n 3 9 FE Bento Ln 3 10 Processor ID elle 3 10 Clock Mode SEINES cara 3 12 Control Impedance Selection nat 3 14 Drive Sopas MM A 3 15 LEDs sud Push Buttons salaria 3 16 TESE EEE RE as 3 16 Rost LEDs LED and VEDE rr 3 17 PLAG LEDs NNN ai 3 17 USB Monitor LED LED Lanna 3 17 ADSP TS201S EZ KIT Lite Evaluation System Manual vii CONTENTS Programmable FLAG Push Buttons SW6 9 3 18 Interrupt Push Buttons SW and SWS sir 3 18 Reset Push Button SW3 iii 3 19 Fv EE 3 19 Sado TT mM 3 20 illo 3 20 E e a EE 3 21 LIB IPS darai 3 21 Expansion Interlace 0 bd lla 3 21 Ellie 3 22 Ke ara kk mila didik gili 3 22 oe MT 3 22 BILL OF MATERIALS INDEX viii ADSP TS201S EZ KIT Lite Evaluation System Manual PREFACE Thank you for purchasing the ADSP TS201S EZ KIT Lite Analog Devices ADI evaluation system for TigerSHARC floating point embedded processors The TigerSHARC processor is a Static Super Scalar SSS architecture tar geted at software defined radio applications In these wireless infrastructure applications the TigerSHARC processor is replacing field programmable gate arrays FPGAs in the Chip Rate processing applications for third generation cellular The performance flexibility multiprocessing and IO capabilities of the TigerSHARC processor makes it superior to FPGA implementations The evaluation board i
54. FLAGs Table 3 19 shows the FLAG signals and the corresponding switches Table 3 19 FLAG Push Buttons FLAG Pin Push Button Reference Designator FLAGO A SW9 FLAG1_A SW8 FLAGO B SW6 FLAGI B SW7 Interrupt Push Buttons SW4 5 Two push buttons SW4 and SW5 are provided for user interrupts The push buttons connect to the processor s interrupt pins The push buttons are active low and when pressed send a low 0 to the processor Refer to Using Interrupt Pins on page 2 6 for more information on how to use the interrupts Table 3 20 shows the interrupt signals and the corre sponding switches Table 3 20 Interrupt Push Buttons Interrupt Pin Push Button Reference Designator IRQ0 A SW4 IRQO B SW5 3 18 ADSP TS201S EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Reset Push Button SW3 The RESET push button SW3 resets all the ICs on the board except the USB interface after it has been configured Connectors This section describes the connector functionality and provides informa tion about mating connectors The locations of the connectors are shown in Figure 3 5 nl ei FT 3333 3333 ITA e JE I DSPA DSPA DSPB DSPB LINKPORT3 RX LINKPORT3TX LINKPORT3RX LINKPORT3 TX 5 44 47 Je Power Connector P3 3 use Connector 3 P5 LINE IN LINE OUT P1 P2 Figure 3 5 Connector Locations
55. G sei DATA38 e DSA lt fg BT LI 0 1 J S DEE patas EZ res di D7 iD40 eee e NE DATO essa I Gast GAS ENeDREGW2__ lt IENEDREG B l Esa lt lt 000 00 0d rf e8e e ci_ GR bata DEL m p Be 1D42 SE I EMU C Emu DATA42 HE TIOM C K3 Dam TMROE lt gt HMROEB T DABA L d Em mm m m mmm TG BSP BI DD rok DATAS EE TRDO 4 Dam O TDI Bi gt oi DATA44 gt na e msc WA ew D Ii TDOBI C TDO DATA45 So e i SDAIO KlspAto as AC4 De Do es Ka L TMS gt TMS e ae FT SDOKEI SDCKE G TRST ADATRST DATA4705 D47 amis Mi PLACE CLOSE TO DSP PINS TAST gt be Ex SDE lt SDWE DATA48 i SCLK DSP BI e A D LI SCUK DSP BI gt DATA49 fee pesci MSSDOI Ulysspo IRQ 3 0 B R8 R9 DATASI T NE _ MSSDII Gips 0 00 0 00 A2 MOST A MSSDA vi 805 DATASI 0 MSS V MSSD2 908 C4 iD52 7 475553 DATA52 a MSSDSi__H3 5655 ms BR PISCLKI baje 2 DET e Pa CLK patas4PS BE Di B BP576 DATA55 m C36 C35 Do mE 10PF 10PF DATASE 56 _ 805 805 Es Der DNP DNP DATA57 ID58 pan A mm F3 D597 I DSP RESET gt RST N DATAS am ini F4 iD60 A DATA60 ee E1 iD6i RTO V RST OUT DATASI E ANA OG 20 Cotton Road E2 iD62 805 DATASET zam Nashua NH 03063 v Fi ID63 SAVI PR SU Ga DEVICES p 1 800 ANALOGD BP576 Approvals Date Title DE ADSP TS201S EZ KIT LITE DSP B Drawn Size Board No
56. GIKEY 240 1019 1 ND RITE BEAD 52 4 1237 1 8W 1 R46 R48 R50 AVX CR32 2370F T R52 53 2 1750K 1 8W 1 R47 R49 DALE CRCW12067503FRT1 VISHAY 54 8 5 76K 1 8W 1 R44 R53 57 PHYCOMP 9C12063A5761FKHFT R150 R152 55 2 11 0K 1 8W 1 R61 62 DALE CRCW12061102FRT1 56 4 120PF 50V 5 NPO C16 19 PHILLIPS 1206CG121J9B200 57 4 1UF 16V 10 X7R C54 C70 72 MURATA GRM40X7R105K016AL 58 1 47PF 100V 10 C64 KEMET C1206C470K1GACTU 60 1 340K 1 8W 1 R192 DALE CRCW0805 3403FT 61 1 698K 1 8W 1 R201 DALE CRCW0805 6983FT 62 2 680PF 50V 1 NPO C26 C29 AVX 08055A681FAT2A 63 2 2 74K 1 8W 1 R68 R73 DALE CRCW12062741FRT1 64 4 5 49K 1 8W 1 R64 65 R69 70 PANASONIC ERJ 8ENF5491V 65 2 3 32K 1 8W 1 R66 R71 DALE CRCW12063321FRT1 ADSP TS201S EZ KIT Lite Evaluation System Manual A 5 P v 2 v a HE dje 5 g s 8 E bb s 2 3 ES a EE gt AZ 66 2 1 65K 1 8W 1 R67 R72 PANASONIC ERJ 8ENF1651V 67 2 10UF 16V 20 ELEC CT4 5 DIGO1 PCE3062TR ND 68 2 68UF 25V 20 ELEC CT6 7 PANASONIC EEV FC1E680P 69 2 2A SL22 SCHOTTKY D4 D5 GENERAL SL22 SEMI 70 1 1332K 1 10W 1 R234 PHILIPS 9C08052A3323FKRT R 71 1810 00 100MW 5 R1 2 R7 10 VISHAY CRCW0805 0 0 RT 1 R130 R155 R161 R181 R184 185 R208 212 R226 72 1 1190 100MHZ 5A FERRITE FER5 MURATA DLW5BSN191SQ2 BEAD 73 1 35 7K 1 10W 1 R220 YAGEO 9C08052A3572FKHFT 74
57. GRAM PROGRAM_D0 T T A5PRoGRAM CCLK PROGRAM D1 R194 R195 Ata C155 C156 C157 C162 C158 C159 C160 C161 C154 C99 C92 C93 C94 C95 ci C100 10K gt 10K PROGRAM CS PROGRAM D2 EP E E EE EE E E E E Ed ES ES vom acan vr emma il PROGRAM Dall e T2EPGA_MO PROGRAM_D5 RTE GA MI PROGRAM D6 S D ren M2 PROGRAM D7 SPARTANIIe FPGA EB 6601 Bo PROGRAM INIT e vcco2 Bo PROGRAM DONE E e Fcco3 Bo e ESyccO4 BI FPGA TCK e Nccos Bt FPGA TDIC S 3 e YWccos BI FPGA_TDO e S yccoz ge FPGA TMS e Hilyccos B2 e H 0009 B2 JllycCO10_B3 anpi e cco11 Ba GND IE e e KllyccO12_B3 GND3 2 e 25V Ncco13 B4 GND4 4 O EE 4 B4 GND5 e NCCO15 B4 GND6 e 23 vccot6 Bs GND78 A e e vcco17 Bs GND e if e MB8ycco18_B5 anD e C96 C97 C98 C85 C86 C87 C88 C89 C90 C164 C79 C80 C81 C82 C83 C84 C163 J5 G9 0 01UF 001UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 10UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 10UF VCCO19 B6 GNDIG e 402 TT 402 402 T 402 402 402 402 402 402 805 402 402 402 402 402 402 805 600020 B6 GND11 A Bucco pe GND12H7 e e vcco22 87 GND13 e e 00023 B7 GND 14 Pe N Z H VCCO24 B7 GNDiS O 6 SPARTANIIe FPGA SPARTANIIe FPGA GND16 e O CCINTA GND e e Yom GND18 e VcciNT3 GND192 e e SVcciNTa GND20 e e coins GND
58. ISTORS DO NOT NEED TO BE VERY CLOSE TO THE DSP IF POSSIBLE I WOULD LIKE THEM ALL ON THE BOTTOM OF THE BOARD ORGANIZED IN GROUPS SIMILAR TO SHOW HERE DEPENDING ON HOW MUCH ROOM YOU CAN LEAVE NEAR THEM I WOULD LIKE TO LABEL SOME OF THEM SCLKRAT 2 0 have internal 5Kohm pull down resistors SCLKRAT 2 0 PLL Ratio 000 4 001 5 010 6 011 7 100 8 101 10 110 12 111 RESERVED Default PLL Ratio 5X CCLK 500MHz Default PLL Ratio 5X CCLK 500MHz PLACE A LABEL HIGH NEAR SW2 12 PLACE A LABEL FOR THE SIGNAL NAME NEXT TO SW2 PINS 1 6 I Brel BMS EEE AAN I BUSLOCK R142 R144 R145 R146 499 499 499 499 805 805 805 805 000000 vo la JR O N DIP6 All strap pins have internal 5Kohm pull down resistors during DSP reset Switch OFF Signal Pulled Low Switch ON Signal Pulled High BMS BM TMROE BUSLOCK ik ik ik ik EPROM Boot Disable interupts level sensitive 1 bit Link Port Data Width SYSCON SDRCON one time writable External or link port boot Enable interupts edge sensitive 4 bit Link Port Data Width SYSCON SDRCON always writable indicates DEFAULT KEEP STUB TO THE SIGNAL AS SMALL AS POSSIBLE 2 5V N
59. Manual I 5 INDEX I 6 ADSP TS201S EZ KIT Lite Evaluation System Manual
60. NA EE gt AZ 86 1 10 01 1 5W 5 R219 IRC LR2512 01 R010 F 87 1 2 55K 1 10W 1 R105 VISHAY CRCW08052251FRT1 88 1 30K 1 10W 5 R218 VISHAY CRCW0805303JRT1 89 1 80 6K 1 10W 1 R221 VISHAY CRCW08058062FRT1 90 2 SUPERMINISCHOTTKY D6 7 CENTRAL CMDSH 3 SEMI 9I 1 3A MBRS340T3 D3 ON SEMI MBRS340T3 92 1 680uF 6 3V 10 CT15 AVX TPSE687K006R0045 TANT LOW ESR 93 2 10 18uF 25V 10 CERM C55 C58 AVX 08053C184KAT2A 94 2 100uF 10V 1096 CT16 17 AVX TPSC107K010R0075 TANT LOW ESR 95 1 150uF 10V 1096 CT14 KEMET T494D157K010AS TANT LOW ESR 96 2 2 2uF 10V 10 CERM C59 60 AVX 0805ZD225KAT2A 97 44 1000PF 50V 5 CERM C67 C168 180 AVX 04025C102JAT2A C186 C188 196 C206 215 C217 C226 C233 236 C243 246 98 1 64 9K 1 10W 1 R191 VISHAY CRCW08056492FRT1 99 2 157 6K 1 4W 1 R147 148 VISHAY CRCW12065762FRT1 A 8 ADSP TS201S EZ KIT Lite Evaluation System Manual Bill Of Materials r 3 v 2 v B 2 HE se z El 9 b 3 2 3 ES alya ZA 5 amp z 100 1 210K 1 4W 1 R190 VISHAY CRCW08052103FRT1 101 22 1100 1 10W 1 R13 R15 22 VISHAY CRCW08051000FRT1 R27 R29 R31 R33 R36 R43 R83 R96 R98 R230 233 102 3 100K 1 8W 5 R58 59 R228 AVX CR1206 1003FRT1 103 7 270 1 8W 5 R79 82 R84 LAN CR32 271J T R90 R151 104 1 20MHZ 1 2 U18 ECLIPTEK EC1100HS 20 000M 105 2 10 0K 1 8W 1 R216 R222 DALE CRCW1206 1002FRT1 106 1 13 0K 1 8W
61. S EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Table 3 21 Power Connectors Terminal Connection Center pin 47 5 VDC 2amps Outer Ring GND ADSP TS201S EZ KIT Lite Evaluation System Manual 3 23 Specifications 3 24 ADSP TS201S EZ KIT Lite Evaluation System Manual A BILL OF MATERIALS e 3 3 A 3 3 PITT PE 3 E 2 3 2 UE 8 p E o a v o 9 3 a2 elo na eon ez 1 1 3 3V OCTAL BUFFER U28 TI SN74LVT244BDW 2 2 HEX INVER SCHMITT TR U14 U30 TI 74LVC14AD IGGER 3 1 3 3V OCTAL BUFFER U13 IDT IDT74FCT3244APY 4 1 ADJ200MAREGULATOR VR4 ANALOG ADP3331ART DEVICES 5 3 ISINGLE 2 INPUT NAND U15 U31 U38 TI SN74AHC1G00DBVR 6 1 12 288MHz SMT OSCILLA U2 DIGIKEY SG 8002CA PCC ND TOR 7 2 ADJUST VRI 2 LINEAR LT1765ES8 ABLE 3A SWITCH REG TECH 8 1 P CHANNEL MOSFET U35 FAIRCHILD FDS6375 SEMI 9 1 ADJ 7A SWITCH REG CN VR5 LINEAR LTC1773EMS TRLR TECH 10 1 N CHANNEL MOSFET U36 VISHAY SI9804DY 11 2 4MX32 SDRAM 166MHZ U24 25 MICRON MT48LC4M32B2TG 7 ADSP TS201S EZ KIT Lite Evaluation System Manual A 1 e 3 3 9 EN 3 8 e 5 8 S 3 3 a K Ep 3 ER i E LE Z OA ZA gt amp z 12 1 3 3V CLK GENERATOR Ul IDT IDT5V928PGI 13 1 3 3V 1 5 CLK DRIVER U37 IDT IDT49FCT3805AQ 14 1 512K X 8 BIT FLASH 3 3V U10 ATMEL AT49BV040 90JC 15 2 1000pF 50V 5 C47 48
62. SMT y AMBER SMT AMBER SMT GREEN SMT 3 3V 13 12 JLEDO01 LEDOO1 LEDOO1 I 4 LEDOO I 4 LEDO01 O 3 3 3 74 VC14A SSOP20 SOIC14 R79 R80 R81 R82 R151 sinji 270 270 270 270 270 R102 SMO y 1206 1206 1206 1206 1206 10K 1 12 805 m gt IFLAGO I LABEL FLAG1 B 2 n Dr ME R101 om HAGA JJ 9 8 4 b O LL tirn O O e gt m 2 FLAG BO LABEL FLAG3 B LABEL FLAG2 B sW7 mayan 5 8 SC 3 3V 3 3V 3 3V 3 3V 3 3V SUE as mea 7 ROA S m Lom 3 a 3 3 LABEL FLAG3 A AUDIO LABEL FLAG2 A SPST MOMENTARY IL 6 7 s me ton 1 L___RQOB s m 7 M RME 1 DA DIP6 T 20 Cotton Road Switch ON Pushbutton will drive DSP net Gita cHe cut umo cia ANALOG Switch OFF DSP net can come from an external source 402 402 402 402 402 Nashua NH 03063 XA DEFAULT All Switches ON DEVICES ph 1 800 anatoco Title Approvals Date ADSP TS201S EZ KIT LITE RESET PB LED Drawn SN74AHC1G00 74LVC14 74LVC14 IDT74FCT3244APY ADM708 i Engineerin 8 8 Date 3 1 2004 10 59 Sheet 10 of 15 B C D
63. SVDD36 VDD 109 H1VSS37 VSS114pg p8VDD40 VDD 1013 H11VSS39 VSS116R10 N19 VDD37 VDD 1010 HTOVSS38 VSS115p p7VDD41 VDD 1014 R118 AT2VSS40 VSS117p Nje VDD38 VDD 1011 H11VSS39 VSS116R10 RE VDD42 VDD 101579 0 00 HT3VSS41 VSS118p y7VDD39 VDD 1012e73 H12VSS40 VSS117p R7VDD43 VDD 1016 g 1206 HT4VSS42 VSS119p pgVDD40 VDD 1013 HT3VSS41 VSS118p BVDD44 VDD 101753 HT5VSS43 VSS120p14 p7VDD41 VDD 1014 R107 HT4VSS42 VSS119p gVDD45 VDD 101879 AT VSS44 VSS121p Rg VDD42 VDD 101579 0 00 HT5VSS43 VSS120f713 gVDD46 VDD 1019 H17VSS45 VSS122p H7VDD43 VDD 1016 g 1206 HTeVSS44 VSS121p VDD47 VDD O20 55 HaVSS46 VSS123p17 B VDD44 VDD IO17E8 H17VSS45 vSS122gre UTOVDD48 VDD 10212 HgVSS47 VSS124p gVDD45 VDD 101879 H8VSS46 VSS123p UT8VDD49 VDD 102255 O VSS48 VSS125pg S VDD46 VDD 1019 HgVSS47 VSS124p UrgVDD50 VDD 1023x39 P13 VSS49 VSS126p9 VDD47 VDD 102029 0VSS48 VSS125pg U6VDD51 VDD 1024 1 p VSS50 VSS127Tf0 UTOVDD48 VDD 102120 VSS49 VSS126p9 U7VDD52 VDD 102550 4 VSS51 VSS128711 UTgVDD49 VDD s VSS50 VSS127TT0 vroVDD53 VDD 102655 4 IDC2x1 aVSS52 VSS129715 UTgVDD50 VDD 102325 4 P11 VSS51 VSS128711 vrgVDD54 VDD 1027 20 2X1 VSS53 VSS130713 3 U6VDD51 VDD 1024 j Te aVSS52 VSS 129172 vraVDD55 VDD 10285 DNP VSS54 VSS131r14 07 VDD52 VDD 102555 4 VSS53 VSS130T15 V12VDD56 VDD 102950 JVSS55 VSS132T16 V10VDD53 VDD 10265 he E VSS54 VS8 13114 VT8VDD57 VDD a 0VSS56 VSS133r15 vrgVDD54 VDD 1027 20
64. VC14A 805 SWT013 S Mi 1 410 SPST MOMENTARY ja PODIRA SOJA My Na T9 SW9 1UF 3 3V R92 74LVC14A SES MOMENTARY SOIC14 Mb C 805 CTs N Z UF TNA v USB CONFIGURED gt e R86 LABEL RESET 10K N Z 805 U15 3 3V U5 Y O rm A I SEE B Ot USB RESET 1 SN O O e MR RESET 2 Ber Pesca SU iS pF RESET SOT23 5 SPST MOMENTARY Pe e RESET R130 0 00 R100 SOIC8 805 R77 LABEL IRO B 805 NANA DSP RESET 1 10K LABEL FLAG1_A 805 R85 _ R78 805 U14 U30 SOFT RESET gt r 805 U14 O O 3 3 gt Mirco p s d 6 e Le gle 74 VC14A 74 VC14A SW8 AEA SPST MOMENTARY SOIC14 SOIC14 SWT013 Gui Nach 3 3V SPST MOMENTARY ma IU T13 A 1UF NE TNA 3 3V SZ o USB RESET RESET N LABEL USB RESET LED2 LED8 LABEL RESET RED SMT RED SMT I 4 LEDOO LEDOO1 3 3V E 3 y e R84 R90 R112 R160 R158 R159 270 270 10K 10K gt 10K S10K 1206 1206 805 805 lt 805 lt 805 R87 10K U13 805 EGG LABEL FLAGO B U30 ape EE 2 18 R103 5 6 i USB RESET 1A1 1Y1 100 4 16 U14 i RESET 1A2 1Y2 805 L RESET E 6 74LVC14A 6 vi e SOIC14 1A3 1Y3 3 3V SVA zalvor 4A U30 e Bag 1val2 O SPST MOMENTARY 9 8 Jens r 1 9 e I FLAG2 Aj bat 2Y1 mw 74 NC14A e eia i je L SOIC14 I FLAG2 Bj ba 2Y2 V uoo ALTER Song 11 10 I FLAGS BI Daag 2va 74LVC14A 1 N Z SOIC14 S OE FLAG3 B FLAG3 A AUDIO FLAG2 B FLAG2 A POWER 19 LED3 LED6 LED5 LEDA LED U30 6 OE2 AMBER SMT AMBER
65. age 3 10 Shows the location and describes the function of each configura tion resistor LEDs and Push Buttons on page 3 16 Shows the location and describes the function of the LEDs and push buttons Connectors on page 3 19 Shows the location of and gives the part number for all of the con nectors on the board In addition provides the manufacturer and part number information for the mating parts Specifications on page 3 22 Describes the power connector ADSP TS201S EZ KIT Lite Evaluation System Manual 3 1 System Architecture System Architecture This section describes the processor s configuration on the EZ KIT Lite board Cc der e ernal Bus Ji Interface Unit ADSP TS201 ee na ll Los Interface Unit PL y ono 2 820 Figure 3 1 System Architecture The EZ KIT Lite has been designed to demonstrate the capabilities of the ADSP TS201S TigerSHARC processor The processor is powered by three separate regulators for the core the internal DRAM and the IO 3 2 ADSP TS201S EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference The processor core voltage is set to 1 15V The internal DRAM is pow ered by an external 1 5V regulator Finally the external interface IO operates at 2 5V but can accept up to 3 3V levels A 20 MHz SMT oscillator in conjunction with a clock generator set to 5x supply the input clock to the processors The
66. ams Example programs are provided with the ADSP TS201S EZ KIT Lite to demonstrate various capabilities of the evaluation board These programs are installed with the EZ KIT Lite software and can be found in VisualDSP 3 5 32 Bit TS EZ KITs ADSP TS201 Examples Please refer to the readme file provided with each example program for more information Using Flash Programmer Utility The ADSP TS201S EZ KIT Lite evaluation system includes a Flash Pro grammer utility The utility allows you to program the Flash memory on the EZ KIT Lite The Flash Programmer is installed with VisualDSP Once the utility is installed it is accessible from the Tools pull down menu For more information on the Flash Programmer utility select Start and choose Programs gt Analog Devices gt VisualDSP for 32 bit Proces sors gt VisualDSP Documentation ADSP TS201S EZ KIT Lite Evaluation System Manual 2 9 Using Flash Programmer Utility 2 10 ADSP TS201S EZ KIT Lite Evaluation System Manual 3 EZ KIT LITE HARDWARE REFERENCE This chapter describes the hardware design of the ADSP TS201S EZ KIT Lite board The following topics are covered System Architecture on page 3 2 Describes the configuration of the ADSP TS201S processor and explains how the board components interface with the EZ KIT Lite Switch Settings on page 3 5 Shows the location and describes the function of each configura tion DIP switch Configuration Resistors on p
67. ctors 1 5 3 19 ADSP TS201S EZ KIT Lite Evaluation System Manual I 1 INDEX J1 J3 expansion interface 3 4 3 21 J4 J7 link ports 3 22 P1 audio 3 6 3 20 P2 audio 3 20 P3 power 1 6 P4 JTAG 3 4 3 21 P5 USB 1 7 3 21 contents EZ KIT Lite package 1 1 control impedance 3 14 CONTROLIMP resistors 3 14 conventions manual xix core power regulator 3 2 current limit 3 4 customer support xiv D data bus D23 0 2 7 memory 2 2 transfer 2 8 Device Manager window 1 15 digital to analog converters DACs 2 7 DIP switches see switches DMARO cycle 2 7 DRAM 3 3 drive strength 3 15 DSP A 2 7 2 8 3 10 3 15 DSP B 2 8 3 10 3 15 E electrostatic discharge 1 2 emulation 2 2 2 4 port 3 4 space 3 7 EPROM boot 3 7 example programs 2 9 expansion header 3 9 interface 3 3 3 21 external interface regulator 3 3 interrupts 2 6 memory xi 2 3 3 4 ports xi 3 3 external regulator 3 3 EZ KIT Lite board architecture 3 2 features x F features EZ KIT Lite board x field programmable gate arrays EPGA ie 297 28 FLAG LEDs LED3 6 3 17 pins 2 5 3 17 3 18 push buttons SW6 9 3 18 source switch SW10 3 9 FLAGO signal 2 5 2 6 3 18 FLAGI signal 2 5 2 6 3 18 FLAG signal 2 5 2 6 3 17 FLAG3 signal 2 5 2 6 2 7 3 17 FLAGREG register 2 5 flash memory x 2 4 3 3 programmer utility 2 9 I 2 ADSP TS201S EZ KIT Lite Evaluation
68. d electret microphone can be used by simply varying the switch setting to the values shown in Table 3 2 An amplification gain of a factor of 10 can be achieved by set ting the switch into electret microphone use Table 3 2 Audio Amplification Selection SW1 Position 1 Position 2 Position 3 Position 4 Audio Amplification Mode OFE OFF ON ON No amplification ON ON OFF OFF For electret microphone use I Default settings Processor Mode Selections SW2 The SW2 switch configures several processor strap pins which set the pro cessor s operating modes after power up or hard reset Processor Boot Strap Settings e SYSCON SDRCON Mode Settings Interrupt Enable Settings Link Port Width Settings The switch settings should not be changed while power is applied to the board Many of the strap pin settings may be re configured in software after the processor is powered up Refer to the ADSP TS201S Embedded Processor Datasheet for more information ADSP TS201S EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Processor Boot Strap Settings Position I of the SW2 switch determines how the processor boots Table 3 3 shows the available boot mode settings Refer to the ADSP TS201S Embedded Processor Datasheet for more information Table 3 3 Processor Boot Strap Settings SW2 Position 1 Position 1 Boot Mode 0 FE EPROM Boot ON External Boot or Li
69. data sheets with a letter suffix L M N S can be obtained from the Literature Center at 1 800 ANALOGD 1 800 262 5643 or downloaded from the website Data sheets without the suffix can be downloaded from the website only no hard copies are available You can ask for the data sheet by part name or by product number xviii ADSP TS201S EZ KIT Lite Evaluation System Manual Preface If you want to have a data sheet faxed to you the phone number for that service is 1 800 446 6212 Follow the prompts and a list of data sheet code numbers will be faxed to you Call the Literature Center first to find out if reguested data sheets are available Contacting DSP Publications Please send your comments and recommendations on how to improve our manuals and online Help You can contact us by emailing dsp techpubs analog com Notation Conventions The following table identifies and describes text conventions used in this manual Additional conventions which apply only to specific chapters may appear throughout this document Example Description Close command File menu or OK Text in bold style indicates the location of an item within the VisualDSP environment and boards menu system and user interface items this that Alternative required items in syntax descriptions appear within curly brackets separated by vertical bars read the example as this or that this that Optional items in
70. e manual consists of Chapter 1 Getting Started on page 1 1 Provides software and hardware installation procedures PC system requirements and basic board information Chapter 2 Using EZ KIT Lite on page 2 1 Provides information on the EZ KIT Lite from a programmer s perspective and outlines the board s memory map Chapter 3 EZ KIT Lite Hardware Reference on page 3 1 Provides information on the hardware aspects of the EZ KIT Lite Appendix A Bill Of Materials on page A 1 Provides a list of components used to manufacture the EZ KIT Lite board Appendix B Schematics on page B 1 Provides the resources to allow making modifications to the EZ KIT Lite or to use as a reference design This appendix is not part of the online Help The online Help viewers should go the PDF version of the ADSP TS201S EZ KIT Lite Evaluation System Manual located in the Docs EZ KIT Lite Manuals folder on the installation CD to see the schematics What s New in This Manual This is the first edition of the ADSP TS201S EZ KIT Lite Evaluation Sys tem Manual The manual documents the hardware tools support for ADSP TS201S TigerSHARC processors ADSP TS201S EZ KIT Lite Evaluation System Manual xiii Technical or Customer Support Technical or Customer Support You can reach DSP Tools Support in the following ways Visit the DSP Development Tools website at www analog com technology dsp developmentTools index html Email question
71. en certified to comply with the essential reguirements of the European EMC directive 89 336 EEC inclusive 93 68 EEC and therefore carries the CE mark The ADSP TS201S EZ KIT Lite evaluation system had been appended to the Technical Construction File referenced DSPTOOLS1 dated December 21 1997 and was awarded CE Certification by an appointed European Competent Body as listed below Technical Certificate No Z600ANA1 019 Issued by Technology International Europe Limited 41 Shrivenham Hundred Business Park Shrivenham Swindon SN6 8TZ UK The EZ KIT Lite evaluation system contains ESD electrostatic discharge sensitive devices Electro static charges readily accumulate on the human WARNING S body and equipment and can discharge without _ amp detection Permanent damage may occur on devices Wagn Afp subjected to high energy discharges Proper ESD FAD SFEBSITEE DEVICE precautions are recommended to avoid performance degradation or loss of functionality Store unused EZ KIT Lite boards in the protective shipping package iv ADSP TS201S EZ KIT Lite Evaluation System Manual CONTENTS PREFACE Purpose of This Manual E xi E me e ane ele li e ei xli A ilari xili Whats New m alza xiii Technical or Cusromer Support aaa xiv Supported MODE xiv Payta ri OU EENEG xv GE E xv Embedded Processor Product Information xv Related Documents sra er brat MER xvi Onl
72. erface and bus arbi tration are enabled only when the 10 000 Refer to the ADSP TS201S TigerSHARC processor Hardware Reference for more information Table 3 10 DSP A ID Pins Configuration The EZ KIT Lite must have a processor with the processor ID set to zero 0 on the board ID0 must be present in order to allow ini R115 Net ID2 A R117 Net DI A R120 Net IDO A ID 2 0 Value Not populated Not populated Not populated 0 Not populated Not populated Populated 1 Not populated Populated Not populated 2 Not populated Populated Populated 3 Populated Not populated Not populated 4 Populated Not populated Populated 5 Populated Populated Not populated 6 Populated Populated Populated 7 1 Default settings Table 3 11 DSP B ID Pins Configuration R122 Net ID2_B R123 Net ID1_B R124 Net ID0_B ID 2 0 Value Not populated Not populated Not populated 0 Not populated Not populated Populated 1 Not populated Populated Not populated 2 ADSP TS201S EZ KIT Lite Evaluation System Manual Configuration Resistors Table 3 11 DSP B ID Pins Configuration Contd R122 Net ID2 B R123 Net ID1 B R124 Net IDO B ID 2 0 Value Not populated Populated Populated 3 Populated Not populated Not populated 4 Populated Not populated Populated 5 Populated Populated Not populated 6 Populated Populated Populated 7
73. es ADSP TS201S processors v 500 MHz Core Clock Speed v Configurable Core Clock Mode Analog Devices AD1871 96 kHz Analog to Digital Converter v Line In 3 5 mm Stereo Jack Analog Devices AD1854 96 kHz Digital to Analog Converter v Line Out 3 5 mm Stereo Jack SDRAM Memory 32 MB 4 Meg x 64 Flash Memory v 512K Main Flash Memory USB Debugging Interface ADSP TS201S EZ KIT Lite Evaluation System Manual Preface e Interface Connectors v 14 Pin Emulator Connector for JTAG Interface v LVDS Link Ports via RJ 45 Connectors v Expansion Interface Connectors not populated General Purpose IO v 4 Push Button FLAGS two for each processor v 2 Push Button Interrupts one for each processor v 4 LED FLAG Outputs two for each processor Analog Devices ADP3331 ADP3336 and ADP3339 for Voltage Regulation The EZ KIT Lite board contains two external memories Flash memory and SDRAM The Flash memory can be used to store user specific boot code By configuring the boot mode switch SW2 and programming the Flash memory the board can run as a stand alone unit The SDRAM is shared by both processors and can be used to store data external to the processors For more information see Memory Map on page 2 2 The EZ KIT Lite board contains an audio interface facilitating creation of audio signal processing applications Additionally the EZ KIT Lite board provides expansion connectors allowing you to connect to
74. ession in VisualDSP 1 Verify that the yellow USB monitor LED LED9 located near the USB connector is lit This signifies that the board is communicat ing properly with the host PC and is ready to run VisualDSP Press and hold down the keyboard Control CTRL key Select the Start button on the Windows taskbar then choose Pro grams gt A nalog Devices gt VisualDSP 3 5 for 32 bit processors gt VisualDSP Environment If you are running VisualDSP for the first time go to step 5 If you already have existing sessions the Session List dialog box appears on the screen Click New Session 1 16 ADSP TS201S EZ KIT Lite Evaluation System Manual Getting Started 5 The New Session dialog box shown in Figure 1 13 appears on the screen li New Session Debug target Multiprocessor System TigerSHARC Emulators EZ KITs MDSP B ID1 ADSP T52015 V DSP A IDO ADSP TS2015 Platform ADSP T52015 EZ KIT Lite via DBG v Session name ADSP T52015 EZ KIT Lite via DBG aq Figure 1 13 New Session Dialog Box 6 In Debug Target choose TigerSHARC Emulators EZ KITs 7 In Platform choose ADSP TS201EZ KIT Lite via DBG port 8 Type a new target name in Session Name or accept the default name 9 Click OK to return to the Session List dialog box 10 Highlight the new session and click Activate ADSP TS201S EZ KIT Lite Evaluation System Manual 1 17 Installat
75. gm m yes j BE 8 e s o i AI 28 27 A22 059 28 27 1D58 T RESET 30 29 naso L3GLKIN P AT DI 1 ata ica ea see cei co ia E faenza i TASEI ADA TI sisi kem sa ase GE FE SSE A se EE ege enn ege Di LL LIDATOO NAJ E d BATON PA 3 D NA LABEL DSP A RX p 32 a GER EL 32 a pez i BOLKOUT A 34 Ba iLiCLKOUT PA as 3DATIO P Al I 3 _ ntm mio set D i ag NTN EEE ep Pa NS Li ee E i E I ADS cea I aa TT Eee eee AAA ee NO se i AR 34 pa ea j FLAGT A a BS IFLAGO A I LIBCMPO Al lt SE po gt ILIACKLA 1 4 DSP A RX Ri TR ne EO NUM LUN MONS NK NON ales a EEUU usas 34 P ai FLAGS A 4 P PLAGER PT LIDATIONAI C gt hipaa PA 1 LT Ga A e ve I ___FLAGI_BI pr IFLAGO B A LICLKIN N A C gt LTCLKIN P A L_____LSDATIO NAI C 3 F 1 ess ME re EN NERE ME E oe a si cd II RE cala Lou h ot i FLAGS BI FLAGEB I BOMPA G LIAGROA TU i DH 7 i DI 42 41 D2 42 41 44 43 8 momo e rasi ma NO a e o ll lu LU a MN ae E oq e ee ee etek B cai ES D di 44 E LIDATOO N Bi 48 ke LIDATOO P B I L 57 46 45 LEN EM E 1 7 LicLKOUT N BI 48 id CTS E i rasi are oo o aed e m o L E Y a ji i LIBGMPO BI lt x Fe gt LAGRER TTI NA NUT 50 ke DILE 50 m AR LADA TIO Bi lt 32 pi gt IBA BB 7777 1 SEO EEE EET EE EE SEE CD 52 si DE 52 pl E LICLKIN N Bi lt 54 gt o PB Lo 1 css css Las O APA care B D15 54 53 1D14 54 53 C T BGMPLBI 56 5
76. gram memory 2 2 programmable FLAG pins see FLAG pins push buttons SW3 reset 3 19 SW4 interrupt 2 6 3 18 SW5 interrupt 2 6 3 18 SW6 FLAGO B 2 6 3 18 SW7 ELAGI B 2 6 3 18 SW8 FLAGI A 2 6 3 18 SW9 FLAGO A 2 6 3 18 R registering this product 1 2 1 5 reset LEDs LED2 LED8 3 17 push button SW3 3 19 resistors 3 10 3 12 3 14 locations of 3 10 RJ 45 connectors xi 2 8 3 22 S SCLKRAT bit 3 3 3 12 SDRAM x xi 2 4 default values 2 4 memory 2 3 registers 3 3 SDRCON registers 2 4 3 7 setting EZ KIT Lite hardware 1 5 simulator session 2 2 SOC registers 2 3 specifications power connector 3 22 SOSTAT registers 2 6 starting VisualDSP 1 16 switches 3 5 SWI 3 6 SW10 3 9 SW2 xi 3 7 3 8 SW6 9 2 5 2 6 SYSCON registers 2 4 3 7 system architecture EZ KIT Lite board 3 2 reguirements PC 1 3 U USB cable 1 2 1 7 connector P7 3 21 debug monitor 2 4 3 7 driver installation Windows 2000 1 12 I 4 ADSP TS201S EZ KIT Lite Evaluation System Manual INDEX driver installation Windows 98 1 8 documentation xviii driver installation Windows XP 1 13 Flash Programmer utility 2 5 interface 3 17 installation 1 4 monitor LED LED9 3 17 license 1 5 port x online Help xvii requirements 1 3 V starting 1 16 verifying USB driver installation 1 15 Voltage regulators xi VisualDSP ADSP TS201S EZ KIT Lite Evaluation System
77. ine Documentation sir xvii Ai ii xvili VisualDSP Documentation Set sai ii xvill iaia xvili Dara aaa xvili TT R R cai xix Notation Conventions ries nila AN xix ADSP TS201S EZ KIT Lite Evaluation System Manual CONTENTS GETTING STARTED Capten ol TEEN ul Aa 1 1 950 MAC 1 3 OL VINILI o MT 1 3 Installing VisualDSP and EZ KIT Lite Software 1 4 Installing and Registering VisualDSP and EZ KIT Lite License 1 5 Setting Up EZ KIT Lite Hardware ici 1 5 Installing EZ KIT Lie USB Diwep cn 1 7 ners 9p USB DEAE usq dir bcm dts o faa le Cn qiiod 1 8 Windows 2000 A 1 12 Windows XP USB A 1 13 Vesitving Driver Installation sucia 1 15 Startine Visual IP rr ia 1 16 USING EZ KIT LITE EZ KIT Lite License MONO nava sikkeli bk lili alkil 2 2 Men Mi ri a ra an 2 2 Usia SORAM Inter aaa 2 4 Leme pha ki apu asa Nk sasaqa aa ua say 2 4 Using Programmable FLAG ft scia 2 5 Uang Deerton TI en e nama akbas 2 6 ET TETT sd 2 7 Using Processor L k Ports ciclica 2 8 EE sera 2 9 vi ADSP TS201S EZ KIT Lite Evaluation System Manual CONTENTS Using Flash Programmer Velg cr 2 9 EZ KIT LITE HARDWARE REFERENCE HA ssa 3 2 EIA O uuu INN BUS MEE 3 3 OO PRA 3 3 Rea 3 4 O RR O OA 3 5 Audio Amplification Selection SYL Juanqa riali 3 6 Processor Mode Selections SW2 3 6 Processor Boot Strap FNS rara 3 7 SYSCONSDRCON Mode Reine ca 3 7 h g
78. ion process refer to Tasks 1 2 and 3 Setting Up EZ KIT Lite Hardware The EZ KIT Lite evaluation system contains ESD electrostatic discharge sensitive devices Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection Per manent damage may occur on devices subjected to high energy discharges Proper ESD precautions are Fil EK ITKE DEVICE recommended to avoid performance degradation or loss of functionality Store unused EZ KIT Lite boards in the protective shipping package The ADSP TS201S EZ KIT Lite board is designed to run outside your personal computer as a stand alone unit You do not have to open your computer case To connect the EZ KIT Lite board 1 Remove the EZ KIT Lite board from the package O Be careful when handling the boards to avoid the discharge of static electricity which may damage some components Figure 1 1 shows the default jumper settings DIP switches con nector locations and LEDs used in installation ADSP TS201S EZ KIT Lite Evaluation System Manual 1 5 Installation Tasks 2 Confirm that your board is set up in the default configuration Figure 1 1 before going to step 3 Power Reset LED1 LEDs SW2 Power Connector P3 USB Reset PR O LED2 USB Monitor LED9 f li USB Connector E B PS swi SW10 Figure 1 1 EZ KIT Lite Hardware Setup 3 Plug the provided power supply int
79. ion Tasks 1 18 ADSP TS201S EZ KIT Lite Evaluation System Manual 2 USING EZ KIT LITE This chapter provides specific information to assist you with developing programs for the ADSP TS201S EZ KIT Lite evaluation board The information appears in the following sections EZ KIT Lite License Restrictions on page 2 2 Describes the restrictions of the VisualDSP license shipped with the EZ KIT Lite Memory Map on page 2 2 Describes the ADSP TS201S EZ KIT Lite board s memory map Using SDRAM Interface on page 2 4 Defines the register values needed to configure the external mem ory for SDRAM access Using Flash Memory on page 2 4 Describes how to program and use the Flash memory Using Programmable FLAG Pins on page 2 5 Describes the function and use of the programmable FLAG pins on the EZ KIT Lite evaluation system Using Interrupt Pins on page 2 6 Describes the function and use of the interrupt pins on the EZ KIT Lite evaluation system Using Audio Interface on page 2 7 Describes how to use and configure the audio interface ADSP TS201S EZ KIT Lite Evaluation System Manual 2 1 EZ KIT Lite License Restrictions e Using Processor Link Ports on page 2 8 Describes how to use and configure the link ports Example Programs on page 2 9 Provides information about the example programs included in the ADSP TS201S EZ KIT Lite evaluation system e Using Flash Programmer Utility on page 2 9 Pro
80. is not configured Once it has been configured you must remove power to reset the USB interface When LED8 is lit it indicates that the master reset of all the major ICs is active FLAG LEDs LED3 6 The FLAG LEDs connect to the processor s FLAG pins FLAG2 and FLAG3 These LEDs are active high and are lit by an output of 1 from the processor Refer to Using Programmable FLAG Pins on page 2 5 for information on how to utilize the FLAGs when programming the proces sor Table 3 18 shows the FLAG signals and the corresponding LEDs Table 3 18 FLAG LEDs FLAG Pin LED Reference Designator FLAG2 A LED4 FLAG3_A LED6 FLAG2_B LED5 FLAG3_B LED3 USB Monitor LED LED9 The USB monitor LED indicates that USB communication has been ini tialized successfully allowing you to connect to the processor using VisualDSP If LED9 is not lit try resetting the board and or reinstalling the USB driver see Installing EZ KIT Lite USB Driver on page 1 7 ADSP TS201S EZ KIT Lite Evaluation System Manual 3 17 LEDs and Push Buttons Programmable FLAG Push Buttons SW6 9 Four push buttons are provided for general purpose user input The SW6 SW7 SW8 and SW9 push buttons connect to the processor s programmable FLAG pins The push buttons are active high and when pressed send a high 1 to the processor Refer to Using Programmable FLAG Pins on page 2 5 for more information on how to use the
81. ivate the Win dows XP Found New Hardware Wizard shown in Figure 1 10 Found New Hardware Wizard Welcome to the Found New Hardware Wizard This wizard helps you install software for ADSP TS201S EZ KIT Lite e If your hardware came with an installation CD 2 or floppy disk insert it now What do you want the wizard to do O Install the software automatically Recommended O Install from a list or specific location Advanced Click Next to continue Figure 1 10 Windows XP Found New Hardware Wizard 3 Select Install the software automatically Recommended and click Next When Windows XP completes the driver installation for the selected device see step 1 a window shown in Figure 1 11 appears on the screen Found New Hardware Wizard Completing the Found New Hardware Wizard The wizard has finished installing the software for a ADSP TS2015 EZ KIT Lite Click Finish to close the wizard Back Cancel Figure 1 11 Windows XP Completing Driver Installation 1 14 ADSP TS201S EZ KIT Lite Evaluation System Manual 4 Getting Started Verify the installation by following the instructions in Verifying Driver Installation Verifying Driver Installation Before you use the EZ KIT Lite evaluation system verify that the USB driver software is installed properly 1 Remove power and unplug the USB cable then apply power to the evaluation board Verify that the RESET LED LED8 stays
82. ler and Preprocessor Manual for TigerSHARC Processors Description of the assembler function and commands for TigerSHARC processors VisualDSP 3 5 C C Complier and Library Manual for TigerSHARC Processors Description of the complier function and com mands for TigerSHARC processors xvi ADSP TS201S EZ KIT Lite Evaluation System Manual Preface Table 2 Related VisualDSP Publications Contd Title Description VisualDSP 3 5 Linker and Utilities Manual Description of the linker function and com for 32 Bit Processors mands for the 32 bit processors VisualDSP 3 5 Loader Manual for 32 Bit Description of the loader function and com Processors mands for the 32 bit processors The listed documents can be found through online Help or in the Docs folder of your VisualDSP installation Most documents are available in printed form If you plan to use the EZ KIT Lite board in conjunction with a JTAG emulator refer to the documentation that accompanies the emulator Online Documentation Your software installation kit includes online Help as part of the Win dows interface These help files provide information about VisualDSP and the ADSP TS201S EZ KIT Lite evaluation system To view VisualDSP Help click on the Help menu item or go to the Windows task bar and select Start gt Programs gt Analog Devices gt Visu alDSP 3 5 for 32 bit Processors gt VisualDSP Documentati
83. nk Port Boot 1 Default settings SYSCON SDRCON Mode Settings Position 2 of the SW2 switch determines how the processor handles writes to the SYSCON and SDRCON registers Table 3 4 shows the setting for the type of write Refer to the ADSP TS201S Embedded Processor Datasheet for more information Table 3 4 SYSCON SRDCON Mode Settings SW2 Position 2 Position 2 SYSCON SDRCON Mode m SYSCON SDRCON one time writable ON SYSCON SDRCON always writable 1 Default settings In emulation space the SYSCON and SDRCON registers can be written to as many times as needed The USB debug monitor operates in emulation space and allows always writable mode for these registers ADSP TS201S EZ KIT Lite Evaluation System Manual 3 7 Switch Settings Interrupt Enable Settings Positions 3 and 5 of the SW2 switch determine how each of the processor handles interrupts Table 3 5 and Table 3 6 show the settings for the interrupt modes Refer to the ADSP TS201S Embedded Processor Datasheet for more information Table 3 5 Interrupt Enable Settings SW2 Position 3 Position 3 Interrupt Enable Mode for DSP A U11 OFF Disable interrupts level sensitive mode ON Enable interrupts edge sensitive mode I Default settings Table 3 6 Interrupt Enable Settings SW2 Position 5 Position 5 Interrupt Enable Mode for DSP B U12 OFF Disable interrupts level sensitive m
84. o P3 on the EZ KIT Lite board Verify that the green power LED LED1 is on Also verify that the RESET LED8 and USB RESET LED2 LEDs go on quickly and then go off 1 6 ADSP TS201S EZ KIT Lite Evaluation System Manual Getting Started 4 While the board is booting the processor RESET LED LED8 stays lit Once the LED turns off connect the USB cable to an available full speed USB port and to P5 on the ADSP TS201S EZ KIT Lite board 5 Follow the USB driver installation instructions in Installing EZ KIT Lite USB Driver Installing EZ KIT Lite USB Driver The EZ KIT Lite evaluation system reguires one full speed USB port The USB driver can be installed on the following platforms Windows 98 as described on page 1 8 Windows 2000 as described on page 1 12 Windows XP as described on page 1 13 The USB driver used by the debug agent is not Microsoft certified because it is intended for a development or laboratory environment not a com mercial environment ADSP TS201S EZ KIT Lite Evaluation System Manual 1 7 Installation Tasks Windows 98 USB Driver Before using the ADSP TS201S EZ KIT Lite for the first time the Win dows 98 USB driver must be installed To install the USB driver 1 Insert the CD into the CD ROM drive The connection of the ADSP TS201S EZ KIT Lite evaluation board to the USB port activates the Windows 98 Add New Hard ware Wizard shown in Figure 1 2 Add New Hardware Wizard
85. oader Manual for TigerSHARC DSPs Next the loader file must be programmed into the Flash memory This can be done using the VisualDSP Flash Programmer utility see Using Flash Programmer Utility on page 2 9 Using Programmable FLAG Pins Each ADSP TS201S processor has four programmable FLAG pins Two FLAG pins from each processor FLAGO and FLAG1 allow interaction with the running program through the use of a switch SW6 9 The FLAG and FLAG3 pins from each processor are connected to LEDs LED3 6 After the processor is reset the programmable FLAGs are configured as inputs The direction of each programmable FLAG is configured in the FLAGREG register If the FLAG is configured for an output the value to be ADSP TS201S EZ KIT Lite Evaluation System Manual 2 5 Using Interrupt Pins Output is set in the FLAGREG register If the FLAG is configured for an input the value on the FLAG pin is read from the SOSTAT register Pro grammable FLAGs are summarized in Table 2 3 For more information on how to configure the programmable FLAG pins see the ADSP TS201S TigerSHARC Processor Hardware Reference Table 2 3 Programmable FLAG Pin Summary FLAG Connected To Use FLAGO_A SW9 The FLAGO and FLAGI pins are connected to the push buttons to supply feedback for program execution For FLAGI A SW8 instance you can write user input to trigger a routine when the push button is pressed FLAGO B SW6 FL
86. ode ON Enable interrupts edge sensitive mode I Default settings Link Port Width Settings Positions 4 and 6 of the SW2 switch determine the link port data width Table 3 7 and Table 3 8 show the settings for the two types of link ports data widths Refer to the ADSP TS201S Embedded Processor Datasheet for more information Table 3 7 Link Port Width Settings SW2 Position 4 Position 4 Link Port Data Width for DSP A U11 OFE 1 Bit link port data width ON 4 Bit link port data width 3 8 ADSP TS201S EZ KIT Lite Evaluation System Manual 1 Default settings EZ KIT Lite Hardware Reference Table 3 8 Link Port Width Settings SW2 Position 6 Position 6 Link Port Data Width for DSP B U12 OFF 1 Bit link port data width ON 4 Bit link port data width 1 Default settings FLAGs and IRGs Switch Settings SW10 The SW10 switch determines the source of the FLAG and IRQ signals con nected to each of the prospective DSPs The source can be modified so that the nets can be driven by either a push button switch or an external source via the Expansion Header Refer to Programmable FLAG Push Buttons SW6 9 and Interrupt Push Buttons SW4 and SW5 on page 3 18 for information on FLAGs IRQs and the associated push but tons Table 3 9 shows the setting for the interrupt modes Table 3 9 FLAGs and IRQs Switch Settings SW10
87. oid performance degradation or loss of functionality Store unused EZ KIT Lite boards in the protective shipping package 1 2 ADSP TS201S EZ KIT Lite Evaluation System Manual Getting Started PC Configuration For correct operation of the VisualDSP software and the EZ KIT Lite your computer must have the minimum configuration Windows 98 Windows 2000 or Windows XP Intel or comparable 166 MHz processor VGA Monitor and color video card 2 button mouse 50 MB free on hard drive 32 MB RAM Full speed USB port CD ROM Drive EZ KIT Lite does not run under Windows 95 or Windows NT unless using a JTAG emulator Installation Tasks The following task list is provided for the safe and effective installation of the ADSP TS201S EZ KIT Lite Follow these instructions in the pre sented order to ensure correct operation of your software and hardware 1 VisualDSP and EZ KIT Lite software installation 2 VisualDSP and EZ KIT license installation and registration 3 EZ KIT Lite hardware setup 4 EZ KIT Lite USB driver installation ADSP TS201S EZ KIT Lite Evaluation System Manual 1 3 Installation Tasks 5 6 USB driver installation verification VisualDSP startup Installing VisualDSP and EZ KIT Lite Software This EZ KIT Lite comes with the latest version of VisualDSP 3 5 for 32 bit processors VisualDSP installation includes EZ KIT Lite installati
88. on To view ADSP TS201S EZ KIT Lite Help which now is part of the Visu alDSP Help system go to the Contents tab of the Help window and select Manuals gt ADSP TS201S EZ KIT Lite For more documentation please go to http www analog com processors resources technicalLibrary ADSP TS201S EZ KIT Lite Evaluation System Manual xvii Product Information Printed Manuals For general guestions regarding literature ordering call the Literature Center at 1 800 ANALOGD 1 800 262 5643 and follow the prompts VisualDSP Documentation Set Printed copies of Visual DSP manuals may be purchased through Ana log Devices Customer Service at 1 781 329 4700 ask for a Customer Service representative The manuals can be purchased only as a kit For additional information call 1 603 883 2430 If you do not have an account with Analog Devices you will be referred to Analog Devices distributors To get information on our distributors log onto www analog com salesdir continent asp Hardware Manuals Printed copies of hardware reference and instruction set reference manuals can be ordered through the Literature Center or downloaded from the Analog Devices website The phone number is 1 800 ANALOGD 1 800 262 5643 The manuals can be ordered by a title or by product number located on the back cover of each manual Data Sheets All data sheets can be downloaded from the Analog Devices website As a general rule printed copies of
89. ons To install VisualDSP and EZ KIT Lite software 1 2 Insert the VisualDSP installation CD into the CD ROM drive If Autoplay is enabled on your PC you see the Install Shield Wiz ard Welcome screen Otherwise choose Run from the Start menu and enter D VADI Setup exe in the Open field where D is the name of your local CD ROM drive Follow the on screen instructions to continue installing the software At the Custom Setup screen select your EZ KIT Lite from the list of available systems and choose the installation directory Click an icon in the Feature Description field to see the selected system s description When you have finished click Next At the Ready to Install screen click Back to change your install options click Install to install the software or click Cancel to exit the install When the EZ KIT Lite installs the Wizard Completed screen appears Click Finish 1 4 ADSP TS201S EZ KIT Lite Evaluation System Manual Getting Started Installing and Registering VisualDSP and EZ KIT Lite License VisualDSP and EZ KIT Lites are licensed products You may run only one copy of the software for each license purchased Once a new copy of the VisualDSP or EZ KIT Lite software is installed on your PC you must install register and validate your licence The VisualDSP 3 5 Installation Quick Reference Card included in your package will guide you through the licence installation and registrat
90. ovides a list of the components shipped with the EZ KIT Lite evaluation system e PC Configuration on page 1 3 Describes the minimum requirements for the PC to work with the EZ KIT Lite evaluation system Installation Tasks on page 1 3 Provides the step by step procedures for setting up the EZ KIT Lite hardware and software Contents of EZ KIT Lite Package Your ADSP TS201S EZ KIT Lite package contains the following items ADSP TS201S EZ KIT Lite board EZ KIT Lite Quick Start Guide VisualDSP 3 5 Installation Quick Reference Card ADSP TS201S EZ KIT Lite Evaluation System Manual 1 1 Contents of EZ KIT Lite Package ADSP TS201S EZ KIT Lite Evaluation System Manual this document CD containing v VisualDSP 3 5 for 32 bit processors with a limited license v ADSP TS201 EZ KIT Lite debug software v USB driver files v Example programs Universal 7 5V DC power supply e USB 2 0 type cable Registration card please fill out and return If any item is missing contact the vendor where you purchased your EZ KIT Lite or contact Analog Devices Inc The EZ KIT Lite evaluation system contains ESD electrostatic discharge sensitive devices Electro static charges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur on devices subjected to high energy discharges Proper ESD Fat SEBSITNE DEVICE precautions are recommended to av
91. paige EI 5 PNE E s 225E BEN KEEN Bus x X SS L SDWE D ve poso DEL L SDWE mg _ WE paso P352 _ a HC1G00 Deng RD gt be 18 89 iD2i 18 89 iD53 50723 5 SSES IL 31 i cast gt as DQ21 dai cas cas DQ21 wall De LG RSS oe FRASI as pa PE FRASI Ras page P54 _ PER ID23 I Er IDES TI pass D23 ossi D55 PLCC32RS c DoJ EEE IDEAR I IDOM 1659m0 posa D24 _ IT ADAM 1659m0 pasate 106 FE mos I sua INEF I bom Das 1025 _ Zion pass D57 Mag Dom base 18 _ Dome page P58 _ Ino7 inso ams pese P27 Doma Ba P39 IDEA 1 pose 1788 _ pose 1760 _ ag met ei pos P29 Tue pages 1267 man mao l nice bose P30 Nc bos _ mea nog paz 10st _ nos poser 1De68 nica 59 ca oY Die o 7 s cs cs up vssif up vssi ss 33V d e ope vss2 e e ope vss2 e e pps vss3 e e ops vss3 e e vona vss e e vona vss e s R155 0 00 vonar vssait e e vonar vssait e asso O S NINA MSSDO i C113 C112 C109 9 12 9 12 MSSD 0 1 lt gt Wl ISDRAM CS I 0 1UF 0 1UF 0 01UF e Nope veel e e upps vsso2 e Enn SE ES 6 Pyppas vssas e e vnnos vssas e e pas vssq4P e e pas vssq4P e MSSDII vopas vssas e e vopas vss EE Pus 6 Spas vssa6 e vppoe vssa6 e Ge ant Se n riti N ova vsso7 e ova vsso7 e io ea sl css TT 81UDDQ8 yi SN74AHC1G00 SN74AHC1G00
92. pulated 100 120Q 1 Default settings Table 3 17 Drive Strength Setting for DSP B R138 DS2 R139 DS1 R137 DS0 Drive Strength Output Impedance Populated Not populated Populated 11 1 260 Populated Not populated Not populated 23 8 320 Populated Populated Populated 36 5 400 Populated Populated Not populated 49 2 520 Not populated Not populated Populated 61 9 620 Not populated Not populated Not populated 74 6 700 Not populated Populated Populated 87 3 960 Not populated Populated Not populated 100 1200 1 Default settings ADSP TS201S EZ KIT Lite Evaluation System Manual 3 15 LEDs and Push Buttons LEDs and Push Buttons This section describes the function of the LEDs and push buttons Figure 3 4 shows the locations of the LEDs and push buttons Power Reset LED1 LED8 e Reset e SW3 USB Reset M LED2 USB Monitor i LED9 FLAG3_A FLAG2 A AUDIO FLAG2 B FLAGS B LED4 LED6 LEDS LED3 m eee ve ge eg vss e eg lt eg e 9 eg e EH m ca AREE o GZ oz co 25 25 EG 25 lt 5 2 2 else H u u u Figure 3 4 LED and Push Button Locations Power LED LED1 The green LED LED1 indicates that power is being properly supplied to the board 3 16 ADSP TS201S EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Reset LEDs LED2 and LED8 When LED is lit the USB interface is being reset This interface is only reset when it
93. pulated 4 25 Populated Populated Populated Populated 5 Populated Populated Populated Not populated 6 Populated Not populated Not populated Populated 6 25 Populated Not populated Populated Populated 8 Populated Not populated Populated Not populated Reserved Test mode 1 Default settings Table 3 13 SCLK Ratio Settings for DSPA R128 SCLKRAT2 R127 SCLKRATI R133 SCLKRATO Multiplication Factor Not populated Not populated Not populated 4 Not populated Not populated Populated 5 Not populated Populated Not populated 6 Not populated Populated Populated 7 Populated Not populated Not populated 8 Populated Not populated Populated 10 Populated Populated Not populated 12 Populated Populated Populated Reserved I Default settings ADSP TS201S EZ KIT Lite Evaluation System Manual 3 13 Configuration Resistors Table 3 14 SCLK Ratio Settings for DSP B R126 SCLKRAT2 R125 SCLKRATI R45 SCLKRATO Multiplication Factor Not populated Not populated Not populated 4 Not populated Not populated Populated 5 Not populated Populated Not populated 6 Not populated Populated Populated 7 Populated Not populated Not populated 8 Populated Not populated Populated 10 Populated Populated Not populated 12 Populated Populated Populated Reserved I Default settings Control Impedance Selection The CONTROLIMP
94. s designed to be used in conjunction with the Visu alDSP development environment to test the capabilities of the ADSP TS201S TigerSHARC processor The VisualDSP development environment gives you the ability to perform advanced application code development and debug such as Create compile assemble and link application programs written in C C and ADSP TS201S assembly Load run step in step out step over halt and set breakpoints in application program Read and write data and program memory Read and write core and peripheral registers Plot memory ADSP TS201S EZ KIT Lite Evaluation System Manual ix Access to the ADSP TS201S processor from a personal computer PC is achieved through a USB port or an optional JTAG emulator The USB interface gives unrestricted access to the ADSP TS201S processor and the evaluation board peripherals Analog Devices JTAG emulators offer faster communication between the host PC and target hardware Analog Devices carries a wide range of in circuit emulation products To learn more about Analog Devices emulators and processor development tools go to http www analog com processors tools The ADSP TS201S EZ KIT Lite provides example programs to demon strate the capabilities of the evaluation board The VisualDSP license provided with this EZ KIT Lite evalua tion system limits the size of a user program s code to 128K words The board features Two Analog Devic
95. s to dsptools supporteanalog com Phone questions to 1 800 ANALOGD e Contact your ADI local sales office or authorized distributor Send questions by mail to Analog Devices Inc DSP Division One Technology Way P 0 Box 9106 Norwood MA 02062 9106 USA Supported Processors The ADSP TS201S EZ KIT Lite evaluation system supports ADSP TS201S TigerSHARC Analog Devices embedded processors xiv ADSP TS201S EZ KIT Lite Evaluation System Manual Preface Product Information You can obtain product information from the Analog Devices website from the product CD ROM or from the printed publications manuals Analog Devices is online at www analog com Our website provides infor mation about a broad range of products analog integrated circuits amplifiers converters and embedded processors MyAnalog com MyAnalog com is a free feature of the Analog Devices website that allows customization of a webpage to display only the latest information on products you are interested in You can also choose to receive weekly email notification containing updates to the webpages that meet your interests MyAnalog com provides access to books application notes data sheets code examples and more Registration Visit www myanalog com to sign up Click Register to use MyAnalog com Registration takes about five minutes and serves as means for you to select the information you want to receive If you are already a registered user
96. syntax descriptions appear within brackets and sepa rated by vertical bars read the example as an optional this or that this Optional item lists in syntax descriptions appear within brackets delim ited by commas and terminated with an ellipsis read the example as an optional comma separated list of this PF9 0 Registers connectors pins commands directives keywords code exam y W ples and feature names are in text with letter gothic font filename Non keyword placeholders appear in text with talic style format ADSP TS201S EZ KIT Lite Evaluation System Manual XIX Notation Conventions Example Description A note providing information of special interest or identifying a A caution providing information about critical design or programming issues that influence operation of a product In the online version of this related topic In the online version of this book the word Note appears instead of the symbol book the word Caution appears instead of the symbol xx ADSP TS201S EZ KIT Lite Evaluation System Manual 1 GETTING STARTED This chapter provides information you need to begin using ADSP TS201S EZ KIT Lite evaluation system For correct operation install the software and hardware in the order presented in Installation Tasks on page 1 3 The chapter includes the following sections e Contents of EZ KIT Lite Package on page 1 1 Pr
97. to the interface speed must be taken into consideration The maximum current limit depends on the capabilities of the regulator Additional circuitry can also add extra loading to signals decreasing their maximum effective speed Analog Devices does not support and is not responsible for the effects of additional circuitry JTAG Emulation Port The JTAG emulation port allows an emulator to access the processor s internal and external memory as well as the special function registers through a 14 pin header See JTAG P4 on page 3 21 for more infor mation about the JTAG connector To learn more about available emulators contact Analog Devices as described in Embedded Processor Product Information on page xv For more information about designing JTAG into a custom board or to learn more about the JTAG interface please refer to EE 68 found at Ana log Devices website 3 4 ADSP TS201S EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Switch Settings This section describes the function of the DIP switches SW1 SW2 and SW10 The location of the switches and their respective default settings are shown in Figure 3 2 SW2 SW1 SW10 Figure 3 2 Switch Locations ADSP TS201S EZ KIT Lite Evaluation System Manual 3 5 Switch Settings Audio Amplification Selection SW1 The SW1 switch determines the amplification of right and left signals con nected to the Line IN connector P1 A non powere
98. u Bi LODATI1 N LODATO1 N L LODATIO P Bil AAA I DAT NB 1 A e Sonar 2 P LO DATO pN22 L__ 3 0 o vv V Renn e onar 2P LODATO2 pN22 em e 29 opari2 N LODATO2 N21 AE e 29 opari2 N LODATO2 NN EE L22 M24 805 L22 M24 KC LOCLKIN P AB A A A E LOCLKINZN A ZZ LO0DATIS P LODATO3 PE DNP e opartI3 P LODATO3 PE e onar s N LODATO3_NM23 L_____LOGLKIN P Bill V A LOCLKINNB 1 e onar s N LODATO3_NM23 K2 OCLKIN_P LOCLKO PNE gt ILOCLKOUT PA cuan PBI gt 4 0CLKIN P LOCLKO PNE gt I D I OCLKIN N LOCLKO NN28 gt ILOCLKOUT NA i I LOCLKIN N Bi o PS corkin N LOCLKO NN28 gt I 2 LOACKO LOACKIPES E 0ACKO Bl C 321 acko LOAGKIP2 i JA oBCMPI LOBCMPO 23 gt E Lo LOBCMPI BI gt 22 9BCMPI LOBCMPO 3 gt L_____LIDATIO P At 124 1DATIO_P LIDATOO P gt DATO PA 1 2 5V DSP B LITT Upati PB gt Ed LIDATOO P DI SE ES j ke NA AO ELO s s Ty bre pi 2 5V DSP A RI3 5 L1DATIO N Ai T ADATIO N LiDATOO NAA23 gt LIDATOO_N_A 1 A LDATIO N Bi C gt 2 ar N LiDATOO NAA23 gt li DEE A Saga oe don e 4 Dat p LIDATO1 PI ioo e 4 Dat p LIDATO1 p 22 ANNA AM LADATIO NA O 1 e 2 DAT N EG NER a e e 6 2 parit N LIDATOY NEL ms mms V24 V24 LIDATIO PB V V VL DAT N B V24 V24 6 L1DATI2 P Do aa Re m GN ME m aaa 6 L1DATI2 P LIDATO2 PS e 23 IDATI2 N LiDATO2 N23 i 23 IDATI2 N L1DATO2 N
99. vides information on the Flash Programmer utility included with VisualDSP For detailed information about programming the ADSP TS201S Tiger SHARC processor see the documents referred to as Related Documents EZ KIT Lite License Restrictions The license shipped with the EZ KIT Lite imposes the following restrictions The size of a user program is limited to program s code to 128K words No connections to simulator or emulator sessions are allowed The EZ KIT Lite hardware must be connected and powered up in order to use VisualDSP with a kit license Memory Map The ADSP TS201S processor has 24 Mbits of internal memory that can be used for program storage or data storage The configuration of internal memory is detailed in the ADSP TS201 TigerSHARC Processor Hardware Reference 2 2 ADSP TS201S EZ KIT Lite Evaluation System Manual Using EZ KIT Lite The ADSP TS201S EZ KIT Lite board contains 512K x 8 bit of external Flash memory The memory is divided into eight uniform 64 Kb sections This memory connects to the processor s BMS and MSO pins The Flash memory can be accessed in boot memory space as well as the external memory bank zero space The board also contains 4M x 64 bit of external SDRAM memory This memory connects to the processor s SDRAM interface Table 2 1 EZ KIT Lite Evaluation Board Memory Map

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