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TP-Link H5R Network Router User Manual

1. YMF744B VAMA 5 Hardware Volume Control The hardware volume control determines the AC 97 master volume without using any software control using the external circuit listed below Two pins VOLUP for increasing the volume and VOLDW for decreasing the volume are used Push SW 1k VOLUP P ush SW tk es VOLDW 1000p S ir 1000p DS 1S provides a shadow register for the AC 97 master volume When the software accesses the AC 97 master volume it is always reflected in the shadow register Bringing the VOLUP pin LOW level increments the left and right channel shadow register by 1 5dB respectively If either one of channel shadow registers have been already set to maximum value 00000b the corresponding channel shadow register remains in the same value and the other channel shadow register will only be incremented If both of channel shadow registers have been already set to maximum values they remain in the same values Bringing the VOLDW pin LOW level decrements the left and right channel shadow register by 1 5dB respectively If either one of channel shadow registers have been already set to minimum value 11111b the corresponding channel shadow register remains in the same value and the other channel shadow register will only be decremented If both of channel shadow registers have been already set to minimum values they remain in the same values The master volume for the AC 97 is updated automatically via th
2. YMF744B VEXATUS F1h Scan In Out Data Read Write Default 00h b7 b6 bs bs b3 b2 bt bo b 7 0 SCAN DATA This is the data port for reading and writing the internal state F2h Current FM Synthesizer Index Read Only Default 00h b7 b6 bs bs b3 bz bt bo b 7 0 Current FM Synthesizer Index This register indicates current index of the FM Synthesizer F3h Current FM Synthesizer Array Read Only Default 00h b7 B6 b5 b3 b 0 ee EE EN CFA DO sao CFA Current FM Synthesizer Arary o ER o N o zi This bit indicates that the FM Synthesizer array is being currently set to Array O or 1 0 Array O default 1 Array 1 F4h FM Synthesizer MPU401 Status Read Only Default 80h EEE 4 o3 o2 EE FFEMP FFFUL mPus DO uuu MPUS MPU401 Status This bit indicates current MPU401 status 0 Default mode Intelligent mode default 1 UART mode b6 FFFUL FM Synthesizer FIFO Full This bit indicates whether or not FIFO followed by the FM Synthesizer is full 0 not Full default 1 Full February 3 1999 41 YMF744B DZ eee isa FFEMP FM Synthesizer Empty VAMA This bit indicates whether or not FIFO followed by the FM Synthesizer is empty 0 not Empty 1 Empty default i Scan Out
3. Latency Timer b 7 0 Latency Timer When DS 1S becomes a Bus Master device this register indicates the initial value of the Master Latency Timer OEh Header Type Read Only Default 00h Access Bus Width 8 16 32 bit 57 bo b5 ba b3 b2 bi bo b 7 0 Header Type This register indicates the device type of DS 1S This is hardwired to 00h 10 13h PCI Audio Memory Base Address Read Write Default 00000000h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b7 b6 b5 b4 b3 b2 bi bO MBA III MBA higher b 31 15 MBA Memory Base Address This register indicates the physical Memory Base address of the PCI Audio registers in DS 1S The base address can be located anywhere in the 32 bit address space Data in the DS 1S register is not prefetchable Size of the register to be mapped into the memory space is 32 768 bytes February 3 1999 14 YMF744B AAA 14 17h Legacy Audio I O Base Address Dummy for SB FM MPU D DMA Read Write Default 00000001h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 bio b9 b8 b7 b6 b5 b4 b3 b2 bi bO IOBASEO E SENE VO oo loas Des eso pss ws ws ws we ws sz f oer p wm ws we er poe bO IO Read Only This bit indicates that the base address is assigned to I O This bit is hardwired to 1 b 15 6
4. not ready for scanning internal state data inhibit further DMA internal state shutdown ready for scanning internal state data internal state read out reading internal state chee a Rre Uta Z 1 shifting internal state 8 times I I internal state scan data out Suspend Preparation N 34 byte Total Scan Data scan data out 1 bit at a time N times ii Scan In SBPDA 0 SBPDR 1 SBPDA 1 not ready for scanning internal state data inhibit further DMA internal state shutdown ready for scanning internal state data internal state write in writing internal state internal state scan data in l shifting internal state 8 times Resume Completion 268 bit 33 byte x 8 4 bit 42 scan data in 1 bit at a time I N times February 3 1999 YMF744B VA 2 2 4 SB IRQ Status F8h Interrupt Flag Register Read Only Default 00h b7 b6 bs bs b3 bz b bo A leale l e le se BU sagita SBI SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt This bitis read only Thus read the SB DSP read port to clearing the interrupt and this bit Then the value of the read port is invalid 2 3 MPU401 This block is for transmitting and receiving MIDI data It is compatible with UART mode of MPU401 Full duplex operation is possible using the 16
5. External Input Eso I O Pad Power Management Block 50h Capability ID Read Only Default 01h Access Bus Width 8 16 32 bit b7 be bs b4 b3 b2 bi bo b 7 0 Capability ID Capability Identifier This register indicates that the new capability register is for Power Management control This register is hardwired to 01h February 3 1999 27 YMF744B VA 51h Next Item Pointer Read Only Default 00h Access Bus Width 8 16 32 bit b7 bs bs b4 b3 be bt bo Next Item Pointer b 7 0 Next Item Pointer DS 1S does not provide other new capability besides Power Management This register is hardwired to 00h 52 53h Power Management Capabilities Read Only Default 0401h Access Bus Width 8 16 32 bit b15 bia bia b12 bt bio bo be b7 bo bo b4 ba b2 bi bo Lel l T I os 1 1 1 1 1 1 ves b 2 0 Version These bits contain the revision number of the Power Management Interface Specification They are hardwired to 001b b10 D2S D2 Support This bit indicates that DS 1S support D2 of the power state It is hardwired to 1 54 55h Power Management Control Status Read Write Default 0000h Access Bus Width 8 16 32 bit bis bia bia b12 bi bio bo b8 b7 b b5 b4 bs b2 bt bo Lel l EE ERES ERES
6. b 7 0 Capability Register Pointer This register indicates the offset address of the Capabilities register in the PCI Configuration register when 58 59h ACPI Mode register ACPI bit is 0 DS 1S provides PCI Bus Power Management registers as the capabilities The Power Management registers are mapped to 50h 57h in the PCI Configuration register and this register indicates 50h When ACPI bit is 1 this register indicates 00h 3Ch Interrupt Line Read Write Default 00h Access Bus Width 8 16 32 bit b7 b b5 b4 o3 b2 bi bo b 7 0 Interrupt Line This register indicates the interrupt channel that INTA is assigned to 3Dh Interrupt Pin Read Only Default 01h Access Bus Width 8 16 32 bit 57 be b5 ba bs b2 bi bo b 7 0 Interrupt Pin DS 1S supports INTA only This register is hardwired to 01h 3Eh Minimum Grant Read Only Default 05h Access Bus Width 8 16 32 bit Per o os o es e 5 7 b 7 0 Minimum Grant This register indicates the length of the burst period required by DS 1S This register is hardwired to 05h February 3 1999 17 YMF744B VAMA 3Fh Maximum Latenc Read Only Default 19h Access Bus Width 8 16 32 bit b7 be bs b4 b3 b2 bt tO Maximum Latency b 7 0 Maximum Latency This regist
7. IOBASEO This register is used so that the OS may secure I O resources for Sound Blaster Pro FM Synthesizer MPUA01 and D DMA controller Because this register is a dummy one each for the I O addresses of the above blocks is assigned with the I O addresses set to 4C 4Dh and 60 65h respectively by the software driver 18 1Bh Legacy Audio I O Base Address Dummy for Joystick Read Write Default 00000001h Access Bus Width 8 16 32 bit bis B14 b13 b12 b11 bio bo be b7 b b5 b4 b3 b2 bt bo IOBASE1 o AA AAA En En rem A AA A AS bO IO Read Only This bit indicates that the base address is assigned to I O This bit is hardwired to 1 b 15 2 IOBASE1 This register is used so that the OS may secure I O resource for the joystick port Because this register is a dummy one the joystick I O address is assigned with the I O address set to 66 67h by the software driver February 3 1999 15 YMF744B VAMA 2C 2Dh Subsystem Vendor ID Read Only Default 1073h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 bio b9 b8 b7 b6 b5 b4 b3 b2 bi bO l Subsystem Vendor ID b 15 0 Subsystem Vendor ID This register contains the Subsystem Vendor ID In general this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor This register is read only To
8. 1 AC 97 Warm Reset D3 ca ACLS AC Link Status Read Only This bit indicates whether or not the AC link is active This bit is 1 when the AC link remains in active state the BIT CLK signal is active This bit is 0 during the following conditions When the CRST pin is active CRST Low When either the PR4 bit or PR5 bit of 4A 4Bh DS 1S Power Control register is set to 1 0 AC 97 Inactive default 1 AC 97 Active February 3 1999 22 YMF744B VAMA 4A 4Bh DS 1S Power Control 1 Read Write Default 0000h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b2 b1 bo CAI Ea Ed EM Ed b0 usi DMC Disable Master Clock Oscillation Setting this bit to 1 disables the oscillation of the Master Clock 24 576 MHZ 0 Normal default 1 Disable D2 iseitis DPLL Disable PLL Clock Oscillation Setting this bit to 1 disables the oscillation of PLL 0 Normal default 1 Disable b6 JSR Joystick Reset This bit controls reset of the flip flop circuit following the analog comparator stage on the joystick port The Initial value is set to 0 immediately after power on reset or hardware reset O Normal default 1 Resets the flip flop circuit following the analog comparator stage on the joystick port b8 PRO AC 97 Power Down Contr
9. E AMAN t t XIHIGH XILOW txicyc Fig 1 XI24 Master Clock timing 4 2 Reset Fig 2 Reset Active Time after Power Stable t 1 m Power Stable to Reset Rising Edge tere 10 ms ReeSlwRae ie Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V C 250 pF 3 0V PVDD LVDD VDD CVDD t RSTOFF RST Fig 2 PCI Reset timing February 3 1999 53 YMF744B VAMA 4 3 PCI Interface Fig 3 4 rar E E tpHIGH E PCICLK Low Time tt be o a tov Busedsignal 2 n m otc snl vaa y a Mg pd O pu E H ua EE Actvero Moseley te Le tes Busedsignay 7 f fo Input Setup Time to PCICLK Ee eel od jm Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V C 10 pF 11 This characteristic is applicable to REQ and PCREQ signal 12 This characteristic is applicable to GNT and PCGNT signal PCICLK AS Srt AA 0 4 Vpp3 rape RR ea eg 0 3 Vpp3 tpeyc Fig 3 PCI Clock timing PCICLK OUTPUT Tri State OUTPUT Fig 4 PCI Bus Signals timing February 3 1999 54 YMF744B 4 4 AC 97 Master Clock Fig 5 Dem Symbl Mim Typ Max Unit wakceeme us eel p EEE CMCLK High Time CMCLK Low Time tcmHIGH CMHIGH t CMLOW tcmcyc F
10. 1 Enable the mapping of the Joystick block default b3 MEN MPU401 Enable This bit enables the mapping of the MPU401 block in the I O space specified by the MPUIO bits when LAD is set to 0 0 Disable the mapping of the MPU401 block 1 Enable the mapping of the MPU401 block default February 3 1999 18 YMF744B VAMA b4 MIEN MPU401 IRQ Enable This bit enables the interrupt service of MPU401 when LAD is set to 0 and MEN is set to 1 MPUA01 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin 0 The MPU401 block can not use the interrupt service 1 The MPU401 block can use interrupt signals determined by the MPUIRQ bits default b5 usns lO I O Address Aliasing Control This bit selects the number of bits to decode for the I O address of each block 0 16 bit address decode 1 10 bit address decode default b 7 6 SDMA Sound Blaster DMA 8 Channel Select These bits select the DMA channel for the Sound Blaster Pro block o DMA ch0 1 DMA ch1 default TO reserved ut DMA ch3 b 10 8 SBIRQ Sound Blaster IRQ Channel Select These bits select the interrupt channel for the Sound Blaster Pro block 0 IRQ5 default K IRQ7 D IRQ9 ge IRQ10 A IRQII 5 7 reserved b 13 11 MPUIRQ MPU
11. Bus Interface 54 pin racak 1 e o poc rset rre ree 5 5 appro fio Pr Address Data Icmmpop to Pr gammad Re Enable earn R frames r0 Pur Frame RDY fio Pur __ titiator Ready reve ro Pe _ Target Ready stoe fio Pur Iso mse 1 Py ID Select pbvsEL to pw Device Setect 3 mo O pw jrrmqes ons 1 j P Pra ETA Pereo o Pr POPCIRegus 3 POGNT ER Perre IO par Lann Error serre O Pod SytemBmor 3 gt juntas o Pod _ interrupt signal output for Pct bus serro to p SeizdiRQ cukrus 10 Pr chock Run 2 AC 97 Interface 8 pin crs O T oma Resetsignatforac7 cmar o C sma Master Clock for ac o7 24 576MH ax 1 T ACiimBitCloekforAC 97audiodata CSbO ACHink AC 97 Serial audio input data Primary Es CSDIO I CSDI2 T ENSE ON cec o r Ea AC link AC 97 Serial audio input data Secondary Docking Enable February 3 1999 YMF744B IIBER 3 External Audio Interface 5 pin SPDIFOUT EXER TH Digital Audio Interface output SPDIFIN ENSE CE Digital Audio Interface input ZVBCLK EDER Zoomed Video Port Bit Clock ZVLRCK ES Tapan T o Zoomed Video Port L R Clock ZVSDI rae eee Zoomed Video Port Serial Data 4 Legacy Device Interface 15 pin Function IO REINES Interrupt5
12. LO LO LO LO LO LO LO LO XO XO XO LO XO 58882888285f082882290222208 A Re G a abd x Ed Ed Ed p E OO S TETE B Qd SS ia Rl Rd E LD O Se E a Uae E Qu Bae mmm Ze 128 Pin LQFP Top View February 3 1999 YMF744B ESSA CATA LSAL axa CXL Odo Td cado cedo pdo Gd 9d9 Ld9 AJASTA CACAO VINI AJASSA YMF744B R 0 4mm pin pitch ddad 9SSAd FISH NIOIOd TINO HOM Tedy ocaw 6cdw SSSAd 8cav L7aw 92a ZadAd Sca Nm E A Mi oM o a OL Ea E AHOHL 1o HAR oN d QS deh h Gu OLD C O REE 800006BZEBHORSXE 4 AD RNa LO f OO QI ed Q OY O0 XO 10 rf OO QI 3 OQ OY 00 XO 10 Ss O3 OY O3 OY Ox Ov OO CD OO C OO C 00 0 OO A A Q 5 to Oo 73 E SPDIFIN 72 E IRQ11 71 EE IRO10 70 EI TROY 67 FJ GPIO2 66 EE GPIOL 65 EE GP100 69 E TRO7 68 EE IRO5 SUNT 6 AAAS TA Sud AJasa t Ads ANI S H Ads ANI S H AYASH ANS Dn pa p c e m Od IOA M SNOY OY Q c4 ON 00 SIN 00 OS C SP SP Si AP SPP SP MP SI ADI 132 AD10 131 MQ IOA OQWOSH INOA oaaao NATO Ouod INDOd OYIVES UUV OSSAd Tav 128 Pin LQFP Top View February 3 1999 YMF744B VAI AI ll PIN DESCRIPTION 1 PCI
13. SERR default 1 Drives SERR when DS 1S detects an Address Parity Error on normal target cycle or a Data Parity Error on special cycle 06 07h Status Read Write Clear Default 0210h Access Bus Width 8 16 32 bit pois b14 bis b12 b11 bio bo bs b7 b bs b4 b3 b2 bi bo Pore sse Ava ara sta Der Deo e 1 Bd sz CAP Capability Read Only This bit indicates that DS 1S supports the capability register This bit is read only When 58 59h ACPI Mode register ACPI bit is 0 the bit is 1 When ACPI bit is 1 the bit is 0 DS uu DPD Data Parity Error Detected This bit indicates that DS 1S detects a Data Parity Error during a PCI master cycle b 10 9 DEVT DEVSEL Timing This bit indicates that the decoding speed of DS 1S is Medium ea i asso STA Signaled Target Abort This bit indicates that DS 1S terminates a transaction with Target Abort during a target cycle DIZ sia RTA Received Target Abort This bit indicates that a transaction is terminated with Target Abort while DS 1S is in the master memory cycle b13 RMA Received Master Abort This bit indicates that a transaction is terminated with Master Abort while DS 1S is in the master memory cycle b14 SSE Signaled System Error This bit indicates that DS 1S asserts SERRA DID wie cone DPE Detected Parity Error This bit indicates that DS 1S
14. YMF744B VAMA 7 Zoomed Video Port Zoomed Video Port is defined in the PC Card Standard PCMCIA applicable to the notebook PC or other systems This port is used to directly output video and or audio signals onto the PCMCIA bus for D A conversion process and connect them directly to the video and or audio signal processing chips on the PC system Its major applications include MPEG decoder card and video capture card etc Because the video and or audio signals on the Zoomed Video Port have been output in synchronized condition DS 1S only converts input audio signal into analog signal through D A converter Audio signals to be transferred on the Zoomed Video Port include bit clock SCLK L R clock LRCK and serial data DATA and they are provided as outputs in the format defined below This is generally called S format LEFT Channel RIGHT Channel In the Zoomed Video Port synchronization with a master clock supplied from the bus is inherently required However DS 1S can asynchronously process audio signal input via the Zoomed Video Port eliminating the need for master clock Sampling rate of the audio signals input via the Zoomed Video Port is resampled to 96 0kHz sampling frequency at the stage followed by the SRC block then converted to 48 0kHz sampling rate in the SRC block stage Sampling rates to be supported on the Zoomed Video Port include 22 05kHz 32 0kHz 44 1kHz and 48 0kHz Interface connection arrangement betwee
15. buffer on the PC side or docking station side 8 2 4 Channel Speaker System 4 channel speaker system can be realized by the connection of DS 1S with two 2 channel AC 97s as described at 8 1 AC 97 Digital Docking or using the AC 97 that includes 4 channel D A converters Then 4 channel PCM data can be played back at one time February 3 1999 50 YMF744B VARA R ELECTRICAL CHARACTERISTICS 1 Absolute Maximum Ratings Symbol Min Vpps Power Supply Voltage PVDD VDD CVDD LVDD Input Voltage E WM REN Operating Ambient Temperature To 0 mw ecl Storage Temperature too so ms ecl Note PVSS VSS 0 V 2 Recommended Operating Conditions Dem Symb Mim Typ Max Unit Power Supply Voltage 3 60 Eundem al VDD CVDD R T Ambient Temperature Note PVSS VSS 0 V February 3 1999 51 ES YMF744B YA 3 DC Characteristics Penh ad A AE EA vu Ta Toma lo sm v y A I High Level Input Voltage 1 3 High Level Input Voltage 4 20 Low Level Input Voltage 4 ES Input Leakage Current dy O lt Vv lt Vos 10 High Level Output Voltage 1 5 Ion 0 5mA S p Eh Low Level Output Voltage 1 Vou amp luslSmA High Level Output Voltage 2 Low Level Output Voltage 2 V V IL OLI gt OH2 gt High Level Output Voltage 3 Low Level Output Voltage 3 High Level
16. byte FIFO for each direction transmitting and receiving The following shows the MPUBase I O map for MPU401 MPUBase R W MIDI Data port MPUBase lh R Status Register port MPUBase lh W Command Register port port D7 D6 D5 D4 D3 D2 D1 DO Data 2 4 Joystick JSBase R W omn or pe ns om os pm p o JBB2 JBB1 JAB2 JAB1 JBCY JBCX JACY JACX JACX Joystick A Coordinate X JACY Joystick A Coordinate Y JBCX Joystick B Coordinate X JBCY Joystick B Coordinate Y JABI Joystick A Button 1 JAB2 Joystick A Button 2 JBB1 Joystick B Button 1 JBB2 Joystick B Button 2 February 3 1999 43 YMF744B VAMA 3 DMA Emulation Protocol The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller 8237 ISA DMAC on the system to transfer the sound data from to the host For DS 1S however ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block Because signals to connect to the ISA DMAC are generally not available on the PCI bus there are two ways proposed from the industry to emulate the ISA DMAC on the PCI bus One is PC PCI and the other is D DMA DS 1S supports both protocols for transferring SB Pro sound data on the PCI bus 3 1 PC PCI DS 1S provides two signals PCREQ and PCGNT to realize the PC PCI The format of the signals is shown below DS 1S assert
17. detects Address Parity Error or Data Parity Error during a transaction February 3 1999 12 YMF744B VA E E 08h Revision ID Read Only Default 02h Access Bus Width 8 16 32 bit b7 b6 b5 b4 b3 b2 b1 bo b 7 0 Revision ID This register contains the revision number of DS 1S This register is hardwired to 02h 09h Programming Interface Read Only Default 00h Access Bus Width 8 16 32 bit b7 be bs b4 b3 b2 b bo Programming Interface b 7 0 Programming Interface This register indicates the programming interface of DS 1S This register is hardwired to 00h OAh Sub class Code Read Only Default 01h Access Bus Width 8 16 32 bit b7 b6 b5 b4 b3 b2 b1 bo l Sub class Code b 7 0 Sub class Code This register indicates the sub class of DS 1S This register is hardwired to 01h DS 1S belongs to the Audio Sub class 0Bh Base Class Code Read Only Default 04h Access Bus Width 8 16 32 bit 57 be bs b4 bs be bi bo Base Class Code b 7 0 Base Class Code This register indicates the base class of DS 1S This register is hardwired to 04h DS 1S belongs to the Multimedia Base Class February 3 1999 13 YMF744B VA ODh Latency Timer Read Write Default 00h Access Bus Width 8 16 32 bit b7 b6 b5 b4 b3 b2 bt bo
18. of Legacy Audio TIROS Ttr 12mA It is directly connected to the interrupt signal of System I O chip mor Jo Te I2mA tnterrupe7 of Legacy Audio IRQ9 ENE MES Interrupt9 of Legacy Audio IRQIO o Te I2mA Interrupt10 of Legacy Audio IRQII RE ERES Interruptl1 of Legacy Audio go Jif A Gameror cma 1 Tp j GmePot RD I po ae MIDI Data Receive MIDI Data Receive mxo Po j T ma MpiDwaTenfer 5 Miscellaneous 11 pin ROMCS FEZES Chip select for external EEPROM Serial clock for external EEPROM ROMSK VOLUP IO Tup 2mA or Hardware Volume Up Serial data output for external EEPROM ROMDO VOLDW IO Tup 2mA or Hardware Volume Down ROMDI EEE Serial data input for external EEPROM xa re J 24257MtzCrsta xo fo TRR Ena roor 1 A CapacitorforPIL 333 General purpose Input Output GPIO 2 0 IO Tup 2mA GPIO2 can use for a reset pin of Secondary AC 97 TEST EE GEI LSI Test pin Do not connect externally February 3 1999 YMF744B IIBER 6 Power Supply 22 pin PVDD 3 0 EE 3 3V Power supply for PCI Bus Interface PVSS 6 0 MO ei e Ground for PCI Bus Interface evoppo 53V Powersupply for Core toge vooo 53v Power suppy ysgo ooa voo o j j33vPowersppyforPLLEle 7 Reserve Pin 13 pin RESERVEO o Poa RESERVE 16 8 1 RESERV
19. the SB Pro engine Both SB and SB Pro commands are supported CMD Support Function 10h 0 8bit direct mode single byte digitized sound output 14h 0 8bit single cycle DMA mode digitized sound output 16h 8bit to 2bit ADPCM single cycle DMA mode digitized sound output 17h 8bit to 2bit ADPCM single cycle DMA mode digitized sound output with ref byte 1Ch 0 8bit auto init DMA mode digitized sound output 1Fh 8bit to 2bit ADPCM auto init DMA mode digitized sound output with ref byte 20h 1 0 8bit direct mode single byte digitized sound input 24h 1 0 8bit single cycle DMA mode digitized sound input 2Ch 1 0 8bit auto init DMA mode digitized sound input 30h 0 Polling mode MIDI input 31h 0 Interrupt mode MIDI input 34h 0 UART polling mode MIDI I O 35h 0 UART interrupt mode MIDI I O 36h 2 0 UART polling mode MIDI I O with time stamping 37h 2 0 UART interrupt mode MIDI I O with time stamping 38h 0 MIDI output 40h 0 Set digitized sound transfer Time Constant 48h 0 Set DSP block transfer size 74h 0 8bit to 4bit ADPCM single cycle DMA mode digitized sound output 75h 0 8bit to 4bit ADPCM single cycle DMA mode digitized sound output with ref byte 76h 8bit to 3bit ADPCM single cycle DAM mode digitized sound output 77h 8bit to 3bit ADPCM single cycle DMA mode digitized sound output with ref byte 7Dh 0 8bit to 4bit ADPCM auto init DMA mode digitized sound output with ref byte 7Fh 8bit to 3bit ADPCM auto init DMA mode digitized sound output with ref by
20. write the IHV s Vendor ID use 44 45h Subsystem Vendor ID Write Register IHVs must change this ID to their Vendor ID in the BIOS POST routine In case of the system such as Sound Card which BIOS can not control this ID can be changed by connecting EEPROM externally Then Subsystem Vendor ID Write Register is invalid In case EEPROM is not externally the default value is the YAMAHA s Vendor ID 1073h 2E 2Fh Subsystem ID Read Only Default 0010h Access Bus Width 8 16 32 bit b15 bia bis bi2 bt bio bo be b7 bo bo b4 bs b2 bt bo Subsystem ID b 15 0 Subsystem ID This register contains the Subsystem ID In general this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor This register is read only To write the IHV s Device ID use 46 47h Subsystem ID Write Register IHVs must change this ID to their ID in the BIOS POST routine In case of the system such as Sound Card which BIOS can not control this ID can be changed by connecting EEPROM externally Then Subsystem ID Write Register is invalid In case EEPROM is not externally the default value is the YAMAHA s Device ID 0010h February 3 1999 16 YMF744B VA 34h Capability Register Pointer Read Only Default 50h Access Bus Width 8 16 32 bit b7 be bs b4 b3 b2 bt tO Capability Register Pointer
21. 401 IRQ Channel Select When MIEN is set to 1 these bits select the interrupt channel for the MPU401 block o IRQ5 VEM IRQ7 2 IRQ9 default 3 IRQ10 4 IRQ11 5 7 reserved Same interrupt channels can be assigned to SBIRQ and MPUIRQ February 3 1999 19 YMF744B VAMA b14 SIEN Serialized IRQ enable DS 1S supports 3 types of interrupt protocols PCI interrupt INTA Legacy interrupt IRQs and Serialized IRQ The interrupt protocol is selected with IMOD and SIEN as follows The interrupt channels for IRQs and Serialized IRQ are determined by SBIRQ and MPUIRQ Only one protocol can be used at once SIEN IMOD Interrupt protocol 0 0 Legacy interrupt IRQs default 0 1 PCI interrupt INTA 1 Serialized IRQ b15 LAD Legacy Audio Disable This bit disables the Legacy Audio block 0 Enables the Legacy Audio block 1 Disables the Legacy Audio block default When this bit is set to 1 DS 1S does not respond to the I O Target transaction for legacy I O address on the PCI bus 42 43h Extended Legacy Audio Control Read Write Default 0000h Access Bus Width 8 16 32 bit b15 bia bis bi2 bit bio bo be b7 bo bo b4 ba b2 bt bo IMOD sever SMOD ENNIO wv NENNEN e AAA MAIM MPU401 Acknowledge Interrupt Mask This bit determine whether interrupt is ass
22. 4B VAMA 2 2 3 SB Suspend Resume The SB block can read the internal state as to support Suspend and Resume functions The internal state is made up of 268 flip flops To read the state these states are shifted in order and read 8 bits at a time from the SCAN DATA register These registers are mapped to the SB Mixer space see SB Mixer Register map The registers have the following functions FOh Scan In Out Control Read Write Default 00h b7 bo bs b4 b3 b2 bt bo sBPDA ss SM SE J SBPDR BU c esu SBPDR Sound Blaster Power Down Request This bit stops the internal state of the Sound Blaster block 0 Normal default 1 Stop l T SE Scan Enable This bit Shifts the internal state by 1 bit Setting a 1 followed by a O shifts the internal state b2 uus SM Scan Mode This bit sets whether to read or write the state 0 Write default 1 Read b3 Ln SS Scan Select This bit gives permission to read or write the internal data to the SCAN DATA register 0 Normal operation Do not allow read or write default 1 Allow read and write b7 un SBPDA Sound Blaster Power Down Acknowledgement This bit indicates that the SB Block is ready to read or write to the internal state after setting SBPDR This bit is read only 0 Read Write not possible 1 Read Write possible February 3 1999 40
23. 8 0kHz In DS 1S sampling rate of the SPDIF signal incoming from the SPDIFIN pin is converted to 48 0kHz in the frequency rate conversion stage in order to process all the signals at 48 0kHz frequency If input sampling frequency is 48 0kHz however this is resampled at 96 0kHz then decimated into 48 0kHz frequency The input signal applied to the SPDIFIN pin can be also provided as outputs to the SPDIFOUT pin 6 2 SPDIF OUT SPDIF output is selected from three types of data indicated below A Dolby digital AC 3 encoded data B Output data to be provided to the DAC slot on the AC link after digital mixing C Input data applied to the SPDIFIN pin When the above A and B data are supplied as outputs output sampling frequency is fixed at 48 kHz and when the above C data is supplied as an output output sampling frequency is dependent on the frequency available from the SPDIFIN input pin Control and category codes of the channel status are provided as sampling rate converter copyright protection available and commercially available recorded software in accordance with the serial copy management system Such a code arrangement allows output data to be digitally copied only to the next generation ones When input signal to the SPDIFIN pin is provided as output no modification is made for the channel status etc and output data is code dependent available from the SPDIFIN pin February 3 1999 48
24. Base 9h Base Ab NA Base Bh Base Ch Base Dh Base Eh ESA Base Fh R W Multi Channel Mask These registers can be accessed by 8 bit or 16 bit bus width DS 1S supports 8 bit DMA transfer only February 3 1999 45 YMF744B VAMA 4 Interrupt Routing DS 1S supports three types of interrupts interrupt signal on the PCI bus INTA interrupt signal on the ISA bus IRQ 5 7 9 10 11 and Serialized IRQ The IRQs on DS 1S are routed as shown below INTA INTA PCI Audio IEN 0 IMOD 1 5 SIEN 0 IMOD 0 IRQ5 2 Sound Blaster Pro IRQ7 Select Signal IRQ9 ISA IRQ sicci IRQ10 IRQ11 SIEN 0 IMOD 1 o SIEN 0 IMOD 0 IRQ MPU401 eo N MOD SIEN IMOD Select Signal MPUIRQ 2 0 PCI Audio can only use INTA but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block can use any of the three protocols The protocol can be switched using 40 43h Legacy Audio Control Register of the PCI Configuration Register 4 1 Serialized IRQ Serialized IRQ is a method to encode IRQs of 15 channels into one signal DS 1S provides the SERIRQ pin to support Serialized IRQ Only one channel out of the 5 channels IRQ5 IRQ7 IRQ9 IRQIO and IRQII can be encoded into the IRQ Data frame of Serialized IRQ The IRQ channel is selected using 40h 43h Legacy Audio Control Register of the PCI Configuration Register February 3 1999 46
25. E 3 2 1 m Reserve pins Do not connect externally MESS EA E TYPE T TTL A Analog Ptr Tri State PCI Ttr Tri State TTL C CMOS Pstr Sustained Tri Sate PCI Tup Pull up Max 300kohm TTL P PCI Pod Open Drain PCI February 3 1999 YMF744B VAI AL EH BLOCK DIAGRAM EEPROM I F SPDIF Input GPIO ZV Port PCI Side Band Legacy Audio PC PCI S IRQ Selector FM Synthesizer SB Pro D DMA Engine PCI MPU401 ds Interface Sampling Joystick Converter PCI Bus Master AC Link Audio DMA Controller Interface Function Revision2 1 Config Register PCI Native Audio XG Synthesizer DirectSound Acc Wave In Out February 3 1999 YMF744B VEXATUS R FUNCTION OVERVIEW 1 PCI INTERFACE DS 1S supports the PCI bus interface and complies to PCI revision 2 2 1 1 PCI Bus Command DS 1S supports the following PCI Bus commands 1 1 1 Target Device Mode CBE 0 0 Interrupt Acknowledge not support o o o o o ojo ES I E P U Memory Read 0 Memory Write reserved 1 Memory Write and Invalidate not support nizi i 2 _ oco o o j o j o j Tj o TlIo oc he io oi i icocioi i 4 Ke l e l a l a l C9 l C3 l a l a l e l e l a l a l C9 l C3 l 2 pa DS 1S does not assert DEVSEL when accessed with commands tha
26. E Ps b 1 0 PS Power State These bits determine the power state of DS 1S DS 1S supports the following power states 0 DO PIT DI not supported ROG D2 Tor D3 hot When the power state is changed from D3 to DO DS 1S resets the PCI Configuration register 00 3Fh DS 1S transits to DO Uninitialized state Though the power state of this register is changed the power consumption of DS 1S is not changed To support low power Windows driver controls DS 1S Power Control Register DS 1S can support the power state of DO D1 D2 and D3 with ACPI In this case set ACPI bit 58 59h ACPI Mode Register to 1 to disable Capabilities of PCI Bus Power Management February 3 1999 28 YMF744B VIA 58 59h ACPI Mode Read Write Default 0000h Access Bus Width 8 16 32 bit O E C o a AA ACPI ACPI Mode Select This bit select either PCI Bus Power Management or ACPI Mode for power management of DS 1S 0 PCI Bus Power Management is used CAP bit 06 07h Status Register and Capabilities Pointer 34h are enabled default 1 ACPI Mode is used CAP bit and Capabilities Pointer are hardwired 0 and disabled 5A 5Bh DS 1S Secondary AC 97 Power Control Read Write Default 0000h Access Bus Width 8 16 32 bit bi4 b13 biz bi bio bo be b7 bo b5 b4 bs b2 bi EMEN SPR7 she SPR5 SPR4 SPR3 SPR2 SPRi
27. Output Voltage 4 Low Level Output Voltage 4 High Level Output Voltage 5 Input Pin Capacitance E x Clock Pin Capacitance Cay IDSEL Pin Capacitance Cp 2 0 10 2 4 2 4 5 5 5 Output Leakage Current 10 oo MUNI Vora oma 24 Low Level Output Voltage 5 E MEET Cin zai RES RE lo ao Power Supply Current EUN SS TBD Power Save 910 Tep Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V Applicable to all PCI Iuput Output pins and Iunput pins Applicable to XI24 pin Applicable to CBCLK CSDIO and CSDD pins 4 Applicable to ZVBCLK ZVLRCK ZVSDI GP 7 4 RXD VOLUP VOLDW GPIO 2 0 DOCKEN ROMDI SPDIFIN and TESTA pins N Uo UA Applicable to all PCI Input Output pins and output pins Applicable to XO24 pin 7 Applicable to CRST CSYNC CSDO and CMCLK pins 8 Applicable to SPDIFOUT ROMSK ROMDO ROMCS TXD and GPIO 2 0 pins Applicable to IRQ5 IRQ7 IRQ9 IRQIO and IRQ11 pins 10 AII DS 1S Power Control bits are set to 1 ON oo NO February 3 1999 52 YMF744B VAMA 4 AC Characteristics 1 Master Clock Fig 1 X04 Cycle Time tac 4069 m X4 High Time ton 13 n xi4towTime www B 2 n Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V GRE
28. Psoir Psor Pszv Pssnc PsPcA PsJov Psveu essa paru CMCD bO CMCD CODEC Master Clock Disable Setting this bit to 1 disables the oscillation of the CMCLK To stop a clock when the CMCLK is supplied to the AC 97 it is required that b13 PR5 bit of 4A 4Bh register is set to 1 If the Secondary AC 97 is used it is also necessary that b5 SPR5 bit of 5A 5Bh register is set to 1 0 Normal default 1 Disable b1 uiuere PSFM Power Save FM Synthesizer Setting this bit to 1 stops a clock supplied to the FM synthesizer block 0 Normal default 1 Disable Dl PSSB Power Save Sound Blaster Setting this bit to 1 stops a clock supplied to the Sound Blaster block 0 Normal default 1 Disable e AA PSMPU Power Save MPU401 Setting this bit to 1 stops a clock supplied to the MPU401 block 0 Normal default 1 Disable A PSJOY Power Save Joystick Setting this bit to 1 disables the comparator of the Joystick block 0 Normal default 1 Disable BS PSPCA Power Save PCI Audio Setting this bit to 1 stops a clock supplied to the PCI Audio block 0 Normal default 1 Disable DG sans PSSRC Power Save SRC Setting this bit to 1 stops a clock supplied to the SRC block 0 Normal default 1 Disable February 3 1999 25
29. SPRO DO seis SPRO Secondary AC 97 Power Down Control 0 This bit controls the power state of the ADC and Input Mux in the Secondary AC 97 0 Normal default 1 Power down Di sche SPR1 Secondary AC 97 Power Down Control 1 This bit controls the power state of the DAC in the Secondary AC 97 0 Normal default 1 Power down AA SPR2 Secondary AC 97 Power Down Control 2 This bit controls the power state of the Analog Mixer Vref still on in the Secondary AC 97 This power state retains the Reference Voltage of the AC 97 0 Normal default 1 Power down b3 eee SPR3 Secondary AC 97 Power Down Control 3 This bit controls the power state of the Analog Mixer Vref off in the Secondary AC 97 This power state removes Reference Voltage of the AC 97 0 Normal default 1 Power down February 3 1999 29 MANU YMF744B DATA l EE E SPR4 Secondary AC 97 Power Down Control 4 This bit controls the power state of the AC link in the Secondary AC 97 0 Normal default 1 Power down b5 i SPR5 Secondary AC 97 Power Down Control 5 Setting this bit to 1 disables the internal clock of the Secondary AC 97 In case the AC 97 is used with DS 1S the master clock is supplied from DS 1S Therefore when the clock is stopped completely set SPRS bits to 1 firstly then the CMCD bit should be set to 1 after
30. System Technology 100 Century Center Court San Jose CA 95112 Tel 1 408 467 2300 Fax 1 408 437 8791 February 3 1999 60
31. TO INTELLECTUAL PROPERTY LICENSE FROM YAMAHA OR ANYTHIRD PARTY AND YAMAHA MAKES NO WARRANTY OR REPRESENTATION OF NON INFRINGEMENT WITH RESPECT TO THE PRODUCTS YAMAHA SPECIFICALLY EXCLUDES ANY LIABILITY TO THE CUSTOMER OR ANY THIRD PARTY ARISING FROM OR RELATED TO THE PRODUCTS INFRINGEMENT OF ANY THIRD PARTY S INTELLECTUAL PROPERTY RIGHTS INCLUDING THE PATENT COPYRIGHT TRADEMARK OR TRADE SECRET RIGHTS OF ANY THIRD PARTY 5 EXAMPLES OF USE DESCRIBED HEREIN ARE MERELY TO INDICATE THE CHARACTERISTICS AND PERFORMANCE OF YAMAHA PRODUCTS YAMAHA ASSUMES NO RESPONSIBILITY FOR ANY INTELLECTUAL PROPERTY CLAIMS OR OTHER PROBLEMS THAT MAY RESULT FROM APPLICATIONS BASED ON THE EXAMPLES DESCRIBED HEREIN YAMAHA MAKES NO WARRANTY WITH RESPECT TO THE PRODUCTS EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR USE AND TITLE Note The specifications of this product are subject to improvement change without prior notice YAMAHA CORPORATION Address inquires to Semi conductor Sales Department AGENCY Head Office 203 MatsunokiJima Toyooka mura Iwata gun Shizuoka ken 438 0192 Tel 81 539 62 4918 Fax 81 539 62 5054 Tokyo Office 2 17 11 Takanawa Minato ku Tokyo 108 8568 Tel 81 3 5488 5431 Fax 81 3 5488 5088 Osaka Office 1 13 17 Namba Naka Naniwa ku Osaka City Osaka 556 0011 Tel 81 6 6633 3690 Fax 81 6 6633 3691 U S A Office YAMAHA
32. Vendor ID 46 47h Subsystem ID Write Register Read Write Default 0010h Access Bus Width 16 bit bi5 b14 bis bi2 bi bio bo be b7 b b b4 bs b2 bi bo Subsystem ID Write b 15 0 Subsystem ID Write Register This register sets the Subsystem ID that is read from 2E 2Fh Subsystem ID register The default value is the DS 1S Device ID 0010h IHVs must change this ID to their ID in the BIOS POST routine In case EEPROM connects externally this register is invalid and do not reflect to Subsystem ID February 3 1999 21 YMF744B VIA 48 49h DS 1S Control Read Write Default 0001h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b2 B1 bo DEDE ee ee E bO CRST AC 97 Software Reset Signal Control This bit controls the CRST signal 0 Inactive CRST High 1 Active CRST Low default Ba badczct WRST AC 97 Warm Reset This bit places the AC 97 in warm reset condition when the BIT CLK signal on the AC 97 remains in inactive state If this bit is set to 1 it will automatically return to 0 after 1 3us time duration This bit is valid only while the ACLS bit is set to 0 Except in this case even if this bit is attempted to be set to 1 no warm reset will be generated write operation of 1 remains disabled 0 Normal default
33. YMF744B VAMA b7 e PSZV Power Save Zoomed Video port Setting this bit to 1 stops a clock supplied to the Zoomed Video port block 0 Normal default 1 Disable DO eer PSDIT Power Save Digital Audio Interface Transmitter Setting this bit to 1 stops a clock supplied to the DIT block 0 Normal default 1 Disable e A PSDIR Power Save Digital Audio Interface Receiver Setting this bit to 1 stops a clock supplied to the DIR block 0 Normal default 1 Disable b10 PSACL Power Save AC Link Setting this bit to 1 stops a clock supplied to the AC Link block 0 Normal default 1 Disable B T iiaiai PSIO Power Save I O Pad Setting this bit to 1 fixes the levels of the I O pins except for the PCI interface and AC Link Output pins retain current level and any signals from input pins are ignored 0 Normal default 1 Fix the level of the I O pad e AAA PSHWV Power Save Hardware Volume Setting this bit to 1 stops a clock supplied to the Hardware Volume block 0 Normal default 1 Disable February 3 1999 26 YMF744B VEXATUS MOD AC97 Master Clock PSFM FM Synthesizer PSMPU MPU401 24 576MHz essre so E ESOO f spoFin PSHWV RM H W Vol PSACL Ss eme Sp AC link PCI I F PC PCI S IRQ EEPROM I F
34. d to the IRQ input pins on the PCI to ISA bridge February 3 1999 33 YMF744B 2 1 FM Synthesizer Block VAMA FM Synthesizer Block is register compatible with YMF289B However Power Management register has been deleted because it is now controlled by the PCI Configuration Register The following shows the FMBase I O map of FM Synthesizer FMBase FMBase FMBase 1 FMBase 2 FMBase 3 The default FMBase value is 0x0388 R W R W W R W Status Register port Address port for Register Array O Data port Address port for Register Array 1 Data port The following shows the FM Synthesizer Block registers 2 1 1 Status Register FM Synthesizer Status Register RO eso ufa To T9 o mo rn re j j s February 3 1999 34 YMF744B VARA 2 1 2 FM Synthesizer Data Register FM Synthesizer Data Register Array O R W eo eps o e Jo Pom te S om er a an ELA EEN ma ao Coo SS wm o o TT aw ow ove mw sw so row vo wi FM Synthesizer Data Register Array 1 R W ea oe T9 9 T T9 T Pon To comemos Lew ASS LL L 1 L CA mew we er faso 0 Tom i mmm Mm o RO pra A ras won nook wwm Feo e pem To E e mel AAA 26h 27h 2Eh and 2Fh do not exist 46h 47h 4Eh and 4Fh do not exist 66h 67h 6Eh and 6Fh do no
35. duration of 20us or longer 0 Normal default 1 Disable BD scars SPR6 Secondary AC 97 Power Down Control 6 This bit controls PR6 bit status of the power control register in the Secondary AC 97 b7 ei SPR7 Secondary AC 97 Power Down Control 7 This bit controls PR7 bit status of the power control register in the Secondary AC 97 Respective data set to b 7 0 are correspondingly set into the Power down Control Status register in the Secondary AC 97 via the AC Link These are not set into the power down register in the Primary AC 97 60 61h FM Synthesizer Base Address Read Write Default 0000h Access Bus Width 8 16 32 bit b15 bia bia bi2 bt bio bo be b7 bo bs b4 ba b2 bi bo DO FM Synthesizer Base Address o b 15 2 FM Synthesizer Base Address This register sets the base address of the FM synthesizer If b5 I O bit of 40h register is set to 1 b 9 2 bits are decoded by ignoring b 15 10 bits 62 63h Sound Blaster Base Address Read Write Default 0000h Access Bus Width 8 16 32 bit b15 bia bis bi2 bt bio bo be b7 bo bs b4 ba b2 bt bo Sound Blaster Base Address O j b 15 4 Sound Blaster Base Address This register sets the base address of the Sound Blaster If b5 I O bit of 40h register is set to 1 b 9 4 bits are decoded by ignoring b 15 10 bits Feb
36. e AC Link by setting corresponding values to the shadow registers When both of the VOLUP and VOLDW pins are at LOW level at the same time the MUTE bit of the shadow register is enabled to automatically set the MUTE bit of the AC 97 master volume via the AC Link When either one of the VOLUP or VOLDW pins is at LOW level mute condition of the AC 97 is deactivated via the AC Link At this point of time the master volume is set to the value before the mute When the AC Link is busy in case the register is controlled by the AC 97 Control Register shadow register values will be set to the AC 97 on the next frame At this time BUSY is set at the AC 97 control register When the master volume is changed or muted depending on the logic level transition status of the VOLUP and VOLDW pins an interrupt is generated at the host The interrupt is used to notify the driver that the master volume has been changed When the AC 97 is not connected or it is placed in power down mode the shadow register values will remain in the same even if the VOLDW and VOLUP pins are at LOW level February 3 1999 47 YMF744B VAMA 6 Digital Audio Interface DS 1S supports each system of the SPDIF input output port compliant with the IEC958 specification 6 1 SPDIF IN DS 1S provides the SPDIF input capability by switch over operation of the zoomed video port SPDIF input sampling frequency is 32 0kHz 44 1kHz or 4
37. er indicates how often DS 1S generates the Bus Master Request This register is hardwired to 19h 40 41h Legacy Audio Control Read Write Default 907Fh Access Bus Width 8 16 32 bit b15 bia bis b12 bt bio bo be b7 bo bo b4 ba b2 bt bo BO uuu SBEN Sound Blaster Enable This bit enables the mapping of the Sound Blaster Pro block in the I O space specified by the SBIO bits when LAD is set to 0 The FM Synthesizer registers can be accessed via SB I O space while the SB block is enabled even if FMEN is set to 0 0 Disable the mapping of the SB block to the I O space 1 Enable the mapping of the SB block to the I O space default bl s FMEN FM Synthesizer Enable This bit enables the mapping of the FM Synthesizer block in the I O space specified by the FMIO bits when LAD is set to 0 FM Synthesizer registers can be accessed via SB I O space while the SB block is enabled even if FMEN is set to 0 0 Disable the mapping of the FM Synthesizer block to the FMIO space 1 Enable the mapping of the FM Synthesizer block to the FMIO space default After setting FMEN to 1 about 100 msec is necessary before accessing these I O space b2 GPEN Gameport Enable This bit enables the mapping of the Joystick block in the I O space specified by the JSIO bits when LAD is set to 0 0 Disable the mapping of the Joystick block
38. erted when the acknowledge which is occurred by changing MPU401 mode form default to UART is returned 0 Interrupt is asserted when the acknowledge is returned default 1 Interrupt is masked when the acknowledge is returned b 12 11 SMOD SB DMA mode These bits determine the protocol to achieve the DMAC 8237 function on the PCI bus 0 PC PCI default PI reserved Rus Distributed DMA 3 reserved February 3 1999 20 YMF744B VAMA b 14 13 SBVER SB Version Select These bits set the version of the SB Pro DSP The value set in these bits is returned by sending the Elh DSP command 0 ver 3 01 default s ver 2 01 22 ver 1 05 3 reserved BTS IMOD Legacy IRQ mode The legacy interrupt protocol is selected with IMOD and SIEN Refer to the explanation of SIEN bit 44 45h Subsystem Vendor ID Write Register Read Write Default 1073h Access Bus Width 16 bit b14 b13 bi2 b bio bo be b7 bo bo b4 bs b2 bi Subsystem Vendor ID Write b 15 0 Subsystem Vendor ID Write Register This register sets the Subsystem Vendor ID that is read from 2C 2Dh Subsystem Vendor ID register The default value is the YAMAHA Vendor ID 1073h IHVs must change this ID to their Vendor ID in the BIOS POST routine In case EEPROM connects externally this register is invalid and do not reflect to Subsystem
39. evision 2 2 This register is hardwired to 1073h 02 03h Device ID Read Only Default 0010h Access Bus Width 8 16 32 bit bis bia bis b12 bii bio bo be oz bo b5 ba b3 b2 bi bo b 15 0 Device ID This register contains the Device ID of DS 1S This register is hardwired to 0010h 04 05h Command Read Write Default 0000h Access Bus Width 8 16 32 bit b15 bia bia bi2 bt bio bo be b7 bo bo b4 ba b2 bt bo A ee ser IM PER NENNEN CME MS 10S DO luus IOS I O Space This bit is a dummy one that is capable of writing This bit indicates for BIOS or OS that DS 1S includes I O devices Dias mass MS Memory Space This bit enables DS 1S to response to Memory Space Access 0 DS 1S ignores Memory Space Access default 1 DS 1S responds to Memory Space Access b2 unii BME Bus Master Enable This bit enables DS 1S to act as a master device on the PCI bus 0 Do not set DS 1S to be the master device default 1 Set DS 1S to be the master device February 3 1999 11 YMF744B VAMA Dari PER Parity Error Response This bit enables DS 1S responses to Parity Error 0 DS 1S ignores all parity errors 1 DS 1S performs error operation when DS 1S detects a parity error BB eiis SER SERR Enable This bit enables DS 1S to drive SERR 0 Do not drive
40. iant Xa XG logo is a trademark of YAMAHA Corporation 9 p l i J p SONDIUS XG logo is a trademark that Stanford University in the United States and YAMAHA Corporation hold jointly O Se nsaura Sensaura logo is a trademark of Central Research Laboratories Limited 1 GM system level 1 GM system level 1 is a world standard format about MIDI synthesizer which provides voice arrangements and MIDI functions 2 XG XG is a format about MIDI synthesizer that is proposed by YAMAHA and keeps the upper compatibility of GM system level 1 The good points are the voice arrangements kept extensively a large number of the voices modification of the voices 3 kinds of effects and so on 3 SONDIUS XG Products bearing the SONDIUS XG logo are licensed under patents of Stanford University and YAMAHA Corporation as listed on lt http www sondius xg com gt The SONDIUS XG produces acoustic sound outputs by running a virtual simulation of the actual acoustic instrument operation Therefore it provides much more real world acoustic sound outputs fundamentally different from the Wavetable sound generator that simply processes the recorded acoustic sound sources only The SONDIUS XG adds the technology of virtual acoustic sound to the XG format 4 Sensaura Sensaura is a technology which provides 3D positional audio and moving effect by HRTF Head Related Transfer Function with 2 speakers or headphone This feature makes it possible to en
41. ig 5 Master Clock timing for AC 97 55 0 5 VDD3 0 2 VDD3 February 3 1999 YMF744B VAMA 4 5 AC link Fig 6 CBCLKCydeTime tmwe 814 os S CBCLKHighTime ann 3 407 45 m CBCLKLowTime teow 35 407 45 35 ns CSYNCCydeTime l eee 208 m E RR REE CSYNC High Time us CSYNC Low Time a us 3 input Setup TimetoCBCLK tosu 4 S Input Hold Time for CBCLK 14 Warm Reset Width Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V C 250 pF 13 This characteristic is applicable to CSYNC and CSDO signal 14 This characteristic is applicable to CSDI signal t CBICYC CBCLK ELE e t CBILOW SYNC tesycyc CSDO CSDI Fig 6 AC link timing February 3 1999 56 YMF744B VEXATUS 4 6 Zoomed Video Port Fig 7 ZVLRCK Delay Time tuo 2 m ZVLRCK Setup Time te 32 m ZVBCLKLowTime ta 22 m ZVBCLKHighTime tai 22 Jom ZVSDI Setup Time tws 32 m ZVSDIHold Time t 2 Jom Note Top 0 70 C PVDD 3 3 0 3 V VDD 3 3 0 3 V CVDD 3 3 0 3 V LVDD 3 3 0 3 V C 50 pF ZVLRCK ZVSCLK tsps A gt toon SCLKH SCLKL ZVSDI Fig 7 Zoomed Video Port
42. joy invariable and unchangeable sound feelings in all positional area covering as wide as 360 degrees February 3 1999 YMF744B VIA R PIN CONFIGURATION YMF744B V 0 5mm pin pitch 126 E 2 pvss5 125 E AD29 120 LS PCICLK 119 ET RST 118 E 1 Pvss6 117 E PVDD3 116 E RESERVEO 115 ft INTA 114 ET cvDD2 113 E RESERVEL 127 E AD28 124 EX AD30 123 EH AD31 122 REO 121 ET Tt a o a oo N AD26 Co 1 DT TEST PVDD2 L 2 O 1 VDD2 AD25 E 3 LL VSS3 AD24 EX 4 1 VDD1 CBE34 E 5 E CMCLK IDSEL CJ 6 E CSDO AD23 HO 7 E CBCLK Pvss4 EXA 8 E CSDIO AD22 Coy 9 LL CSYNC AD21 E 10 C CRST AD20 Co 11 O VDDO AD19 ES 12 E VSS2 AD18 1 13 LL RESERVE2 AD17 CW 14 C RESERVE3 AD16 EOS 15 CL CSDI2 CBE C 16 1 DOCKE PVSS3 CJ 17 E VSS1 FRAME CZ 18 DI XI24 IRDY E 19 X024 TRDY ES C LOOPF DEVSEL4 LD DI LVDD PVDD1 EX 1 CVDD1 STOP4 C E ZVBCLK PERRE ES C ZVLRCK SERR EJ 1 ZVSDI PAR E E SPDIFOUT CBE Dm 1 SPDIFIN PVSS2 E 1 TRO11 AD15 DT LC IRO10 AD14 EE TI IRO9 AD13 DT CL IRQ7 AD12 E TI IRO5 AD11 DT LL GPIO2 AD10 C4 E GP TO ADI C E GPIO0 ADS C 1 RESERVES8 PVSS1 C Cd RESERVE9 CBEO C C RESERVE10 o CO c CON 00 sf 10 XO 000 OMANDO o LO LO
43. lowing logical IDs To control the device with the BIOS the logical device IDs must be defined in the PnP BIOS extended ROM space The logical IDs are determined by how it is configured IDs and configuration are as follows Functions used Block Logical Device ID A MPU401 YMH0100 YMHOI0 E Sto o3 8i 74 The blocks pertain to the following FM Points to the FM synthesizer mapped to AdLibBase 0x0388 SB Pro Points to the Voice Playback section only These devices are independent from each other and can be Enabled Disabled individually However both AdLib and Sound Blaster must be disabled to disable the internal FM Synthesizer Disabling just AdLib only masks the access The driver by Yamaha supports only logical device ID YMH0100 For YMH0101 use the driver provided by Microsoft February 3 1999 32 YMF744B Du AAA DS 1S supports PC PCI and D DMA protocols to emulate the DMA of SB Pro on the PCI In addition DS 1S supports the old type of interrupts used by ISA and the Serialized IRQ protocol Yamaha recommends the combination of PC PCI and Serialized IRQ The system block diagram when using Intel chip set is shown below North Brigde 430TX 440BX PCI E Mot E Control IRQ5 3 South Bridge iros PIIX4E SERIRQ DS 1S Na Select either protocols The PCI to ISA bridge needs to support PC PCI IRQ is directly connecte
44. n Control 6 This bit controls PR6 bit status of the power control register in the Primary AC 97 b15 PR7 AC 97 Power Down Control 7 This bit controls PR7 bit status of the power control register in the Primary AC 97 Respective data set to b 15 8 are correspondingly set into the Power down Control Status register in the Primary AC 97 via the AC Link These are not set into the power down register in the Secondary AC 97 4C 4Dh D DMA Slave Configuration Read Write Default 0000h Access Bus Width 8 16 32 bit b15 bia bia bi2 bit bio bo be b7 bo bo b4 ba b2 bi bo DO uuu CE Channel Enable This bit enables the Distributed DMA function O Disable Distributed DMA default 1 Enable Distributed DMA b 2 1 TS Transfer Size These bits indicate the size of the DMA transfer Since DS 1S supports only 8 bit DMA transfer the bits are hardwired to OOb b3 EA Extended Address DS 1S does not support extended address mode This bit is hardwired to Ob b 15 4 Base Address D DMA Slave Base Address These bits indicate the D DMA slave base address February 3 1999 24 YMF744B VAMA 4E 4Fh DS 1S Power Control 2 Read Write Default 0000h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 b10 b9 b8 b2 b1 bO b7 b6 b5 b4 b3 Psw Psio psact
45. n the DS 1S and the Zoomed Video Port is as illustrated below DS 1S ZV Port ZVBCLK 48 sCLK ZVLRCK 4 LRCK ZVSDI 4 DATA 9 MCLK Open The Zoomed Video Port can be used to be selected between the SPDIFIN input February 3 1999 49 YMF744B VAMA 8 Multiple AC 97 amp Multi Channel DS 1S allows connection with up to two AC 97s and plays back up to 4 channel PCM data Therefore the following applications can be realized 8 1 AC 97 Digital Docking AC 97 digital docking can be realized by mounting the secondary AC 97 on the docking station side Typical example of digital docking connection between DS 1S and AC 97s is represented in the circuit diagram below XTL IN BIT CLK SYNC Primary SDATA OUT Audio CODEC lecsdo somn RESET Isolation Buffer PC Side A Docking Station DVDD XTL_IN BIT CLK SYNC Secondary SDATA OUT Audio CODEC o RESETE AC 97 Rev2 1 SDATA IN T duia CODEC ID 01 TIT When digital docking interface is made with the main side PC side powered on but docking station side powered off it may be not desirable for the secondary AC 97 that each output signal from the AC Link is applied to the secondary AC 97 that remains in powered off state In order to avoid such a situation it is necessary to place an additional isolation
46. ol O This bit controls the power state of the ADC and Input Mux in the Primary AC 97 0 Normal default 1 Power down A PR1 AC 97 Power Down Control 1 This bit controls the power state of the DAC in the Primary AC 97 0 Normal default 1 Power down b10 PR2 AC 97 Power Down Control 2 This bit controls the power state of the Analog Mixer Vref still on in the Primary AC 97 This power state retains the Reference Voltage of the AC 97 O Normal default 1 Power down b11 ss PR3 AC 97 Power Down Control 3 This bit controls the power state of the Analog Mixer Vref off in the Primary AC 97 This power state removes Reference Voltage of the AC 97 0 Normal default 1 Power down February 3 1999 23 YMF744B VAMA b12 PR4 AC 97 Power Down Control 4 This bit controls the power state of the AC link in the Primary AC 97 0 Normal default 1 Power down Did ont PR5 AC 97 Power Down Control 5 Setting this bit to 1 disables the internal clock of the Primary AC 97 In case the AC 97 is used with DS 1S the master clock is supplied from DS 1S Therefore when the clock is stopped completely set PRS bits to 1 firstly then the CMCD bit should be set to 1 after duration of 20us or longer 0 Normal default 1 Disable b14 PR6 AC 97 Power Dow
47. pliant DMAC 8237 emulation PCI Bus Power Management rev 1 0 Compliant Supports I S serial input for Zoomed Video Port Support DO D2 and D3 state Supports Consumer IEC958 Output SPDIF OUT Supports clock run Supports Consumer IEC958 Input SPDIF IN PCI Bus Master for PCI Audio e Supports AC 97 Interface AC Link Revision 2 1 True Full Duplex Playback and Capture with AC 97 Digital Docking different Sampling Rate Supports 4 Channel Speaker Maximum 64 voice XG capital Wavetable Hardware Volume Control Synthesizer including GM compatibility EEPROM Interface DirectSound Hardware Acceleration e Single Crystal operation 24 576MHz DirectMusic Hardware Acceleration 3 3V Power supply 5V tolerant Downloadable Sound DLS level 1 e 128 pin LQFP YMF744B V 0 5mm pin pitch Legacy Audio compatibility YMF744B R 0 4mm pin pitch FM Synthesizer Hardware Sound Blaster Pro compatibility midi O S l N l l Y6 E n MPUA401 UART mode MIDI interface Joystick Xe Y Sensaura Supports Serialized IRQ The contents of this catalog are target specifications and are subject to change i without prior notice When using this device please recheck the specifications YAMAHA CORPORATION CATALOG No LSI AMF744B00 February 3 1999 YMF744B VAMM B LOGOS i GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry AMEI and indicates GM system level 1 Compl
48. pu YAMAHA DS 1S R OVERVIEW YMF744B DS 1S is a high performance audio controller for the PCI Bus DS 1S consists of two separated functional blocks One is the PCI Audio block and the other is the Legacy Audio block PCI Audio block allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without utilizing the CPU or causing system latency By using the Software Driver from YAMAHA PCI Audio provides 64 voice XG wavetable synthesizer with Reverb and variation It also supports DirectSound hardware accelerator Downloadable Sound DLS and DirectMusic accelerator Legacy Audio block supports FM Synthesizer Sound Blaster Pro MPU401 UART mode and Joystick function in order to provide hardware compatibility for numerous PC games on real DOS without any software driver To achieve legacy DMAC compatibility on the PCI DS 1S supports both PC PCI and Distributed DMA protocols DS 1S also supports Serialized IRQ for legacy IRQ compatibility DS 1S supports the connection to AC 97 which provides high quality DAC ADC and analog mixing and it can connect two AC 97s In addition it supports consumer IEC958 Audio Digital Interface SPDIF to connect external audio equipment by digital R FEATURES PCI 2 2 Compliant Supports PC PCI and Distributed DMA for legacy e PC 98 PC 99 specification Com
49. rent from the shape in this diagram The figure in the parenthesis should be used as a reference Plastic body dimensions do not include burr of resin UNIT mm Note The LSIs for surface mount need especial consideration on storage and soldering conditions For detailed information please contact your nearest agent of Yamaha February 3 1999 59 YMF744B VIA IMPORTANT NOTICE 1 Yamaha reserves the right to make changes to its Products and to this document without notice The information contained in this document has been carefully checked and is believed to be reliable However Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document 2 These Yamaha Products are designed only for commercial and normal industrial applications and are not suitable for other uses such as medical life support equipment nuclear facilities critical care equipment or any other application the failure of which could lead to death personal injury or environmental or property damage Use of the Products in any such application is at the customer s sole risk and expense 3 YAMAHA ASSUMES NO LIABILITY FOR INCIDENTAL CONSEQUENTIAL OR SPECIAL DAMAGES OR INJURY THAT MAY RESULT FROM MISAPPLICATION OR IMPROPER USE OR OPERATION OF THE PRODUCTS 4 YAMAHA MAKES NO WARRANTY OR REPRESENTATION THAT THE PRODUCTS ARE SUBJECT
50. ruary 3 1999 30 YMF744B VBA 64 65h MPU401 Base Address Read Write Default 0000h Access Bus Width 8 16 32 bit bis bia bia bi2 bit bio bo be b7 bo bo b4 bs b2 bi bo MPU401 Base Address E b 15 1 MPU401 Base Address This register sets the base address of the MPU401 If b5 I O bit of 40h register is set to 1 b 9 1 bits are decoded by ignoring b 15 10 bits 66 67h Joystick Base Address Read Write Default 0000h Access Bus Width 8 16 32 bit b14 b13 bi2 bi bio w9 be b7 bo b5 b4 bs b2 bi b 15 0 Joystick Base Address This register sets the base address of the Joystick If b5 I O bit of 40h register is set to 1 b 9 0 bits are decoded by ignoring b 15 10 bits February 3 1999 31 YMF744B VAMA 2 ISA Compatible Device DS 1S contains the following functions to maintain the compatibility with the past ISA Sound Devices These devices are considered Legacy devices and the functions are referred to as Legacy Audio Legacy Audio is independent from PCI Audio and can be used simultaneously The configuration is set in the Legacy Audio Control Register in the PCI Configuration Register space Basically these registers are configured by the BIOS Also logical device IDs are assigned to the devices to support Plug and Play Yamaha defines the fol
51. s PCREQ and sets PCREQ to HIGH using the PCICLK corresponding to the DMA channel it is going to use In addition DS 1S determines whether the next PCI I O cycle is its own from the channel information that is encoded in PCGNTH Ons 100ns 200ns 300ns 400ns PCICLK REQ start_ CHO KCH1 XCH2 XCH3 CH4 KCH5 X CHp X cH7 GNT start_ bitd Xbiti TRS PCGNT is encoded as follows bito GNT Bits 0 DMAChannel 0 0 DMAChamei Reserved DMA Channel 5 0 DMA Channel 6 1 DMA Channel 7 DS 1S supports only 8 bit DMA channels DMA Channel 0 3 It also only supports Single DMA transfer 2 bit 0 o a 1 1 DMAChamel3 o o o a ES February 3 1999 44 YMF744B VA 3 2 D DMA DS 1S provides the following registers to support D DMA D DMA Slave Configuration Register 4C 4Dh of the PCI Configuration register is used to set the Base address of the Slave Address Slave Address Base Oh Base Oh Base 1h Base 1h Register Name S PR Current Address 7 R Current Address RS Base 2h Bue 2h R Current Address 1623 Base 3h Base 3n R Current Address2431 Base dh Base 4n R Curent Word Coum07 Base Sh m Ew Base 5h Current Word Count 8 15 Base 6h Base Word Count 16 23 Base 6h Base Bh Base Bh
52. s marked with exist but do not function DS 1S does not have the circuit that corresponds to the SB Mixer Therefore the volume settings on the SB Mixer are converted to the DSP coefficients of DS 1S or to AC 97 register values The conversion for each case is described below 1 SB Mixer 2 DSP The volume of master MIDI and Voice are applied to this case When the SB register is set a 14 bit coefficient value is determined from the following conversion table and used as the DSP coefficient The attenuation value of Master Volume MIDI and voice are summed together to obtain the coefficient These volumes cannot be controlled from PCI Audio block February 3 1999 38 YMF744B VARA 1 Volume for MIDI MIDI Vol 26h Pion EEE TESE poe medo runde aec qued cms nm EE Ee ee AE wer EM 0000h 0335h 0A24h 143Dh 2013h 2861h 32D6h 3FFFh Master Vol 22h The default is Master 4 MIDI 4 12dB 2 Volume for Voice Voice Vol 04h A ee REFERI pou senno ec Maa The default is Master 4 Voice 4 16dB T N or o gt v D 2 o 2 SB Mixer gt AC 97 The volume of CD Line and MIC are applied to this case AC 97 volume are not updated automatically when these values are changed Thus the SB Mixer values need to be written to the AC 97 register with the software February 3 1999 39 YMF74
53. t are indicated as not supported or reserved 1 1 2 Master Device Mode C BE 3 0 Command 1 1 0 1 1 1 When DS 1S becomes a Master Device it generates only memory write and read cycle commands February 3 1999 YMF744B YAMARA 1 2 PCI Configuration Register In addition to the Configuration Register defined by PCI Revision 2 2 DS 1S provides proprietary PCI Configuration Registers in order to control legacy audio function such as FM Synthesizer Sound Blaster Pro MPU401 and Joystick These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation The following shows the overview of the PCI Configuration Register Reserved Header Type Latency Timer Reserved 1C 2Bh Reserved 2C 2Fh Subsystem ID Subsystem Vendor ID 30 33h Reserved aes 38 3Bh Reserved es O 40 43h Legacy Audio Control SC SFh registers are hardwired to 0 All data written to these registers are discarded The values read from these registers are all zero DS 1S can be accessed by using any bus width 8 bit 16 bit or 32 bit February 3 1999 10 YMF744B VEXATUS 00 01h Vendor ID Read Only Default 1073h Access Bus Width 8 16 32 bit b15 b14 b13 b12 b11 bio b9 b8 b7 b6 b5 b4 b3 b2 bi bO l Vendor ID b 15 0 Vendor ID This register contains the YAMAHA Vendor ID registered in R
54. t exist 86h 87h 8Eh and 8Fh do not exist E6h E7h EEh and EFh do not exist The bits exist but do not function Nn Bu Ne February 3 1999 35 YMF744B VAMA 2 2 Sound Blaster Pro Block This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro Only playback functions are supported record functions are not supported However to maintain compatibility for games it is designed so that every DSP command receives a correct response The DMA transfer of this block uses PC PCI or D DMA protocol The following shows the SBBase I O map of SB Pro SBBase R FM Synthesizer Status port SBBase W FM Synthesizer Address port for Register Array 0 SBBase 1h R W FM Synthesizer Data register SBBase 2h W FM Synthesizer Address port for Register Array 1 SBBase 3h R W FM Synthesizer Data port SBBase 4h W SB Mixer Address port SBBase 5h R W SB Mixer Data port SBBase 6h W SB DSP Reset port SBBase 8h R FM Synthesizer Status port SBBase 8h W FM Synthesizer Address port for Register Array 0 SBBase 9h R W FM Synthesizer Data port SBBase Ah R DSP Read Data port SBBase Ch R DSP Write buffer status port SBBase Ch W DSP Write Command Data port SBBase Eh R DSP Read buffer status port February 3 1999 36 YMF744B VAMA 2 2 1 DSP Command The following shows the list of DSP Commands that are supported by
55. te 80h 0 Pause DAC for a duration 90h 0 8bit high speed auto init DMA mode digitized sound output 91h 0 8bit high speed single cycle DMA mode digitized sound output 98h 1 0 8bit high speed auto init DMA mode digitized sound input 99h 1 0 8bit high speed single cycle DMA mode digitized sound input AOh 1 0 Set input mode to mono A8h 1 0 Set input mode to stereo DOh 0 Pause 8bit DMA mode digitized sound I O D1h 3 0 Turn on speaker D3h 3 0 Turn off speaker D4h 0 Continue 8bit DMA mode digitized sound UO D8h 0 Get speaker status DAh 0 Exit 8bit auto init DMA mode digitized sound I O Eth 0 Get DSP version number Note 1 The SB Block responds correctly to the commands for recording and also executes the DMA transfer 80h is always transferred 2 Only output is supported for this command 3 This command only changes Speaker Status D8h Undocumented commands other than the ones listed above are also supported February 3 1999 37 YMF744B VA 2 2 2 Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro Voice Volume L Voice Volume R own MG Wane oa ES Ls p oe EL ENE gt SW T Master Volume L 1 Master Volume R Lem it E mt voune 8 CD Volume L CD Volume R Fon sepa ss SM SE SBPDR a Resume SCAN DATA Fm SUN TAS o CT s ros The register
56. timing 57 February 3 1999 YMF744B VAMA MW EXTERNAL DIMENSIONS YMF744B V 22 00 0 40 a 20 00 0 30 0 15Typ or 0 17Typ LEAD THICKNESS 102 65 LUUD LEUTE D ELLO LIT 103 64 d E E o o E E m 3S c LE e o Sl E E o e o 9 128 SO E39 E OTT OVO TUU TUO TUO TUO TUU TUUU UD UU 1 38 P 0 50Typ PE 0 20 0 10 T LL O S 8 E X q lt o E E Tu m Ss or 1 00 i po Y J 0 15 0 50 0 30 Unit mm The shape of the molded corner may slightly different from the shape in this diagram The figure in the parenthesis should be used as a reference Plastic body dimensions do not include burr of resin UNIT mm Note The LSIs for surface mount need especial consideration on storage and soldering conditions For detailed information please contact your nearest agent of Yamaha February 3 1999 58 YMF744B VAMA YMF744B R 16 00 0 40 14 00 0 30 97 14 00 0 30 16 00 0 40 O 1 32 0 16 0 10 P 0 40Typ 128 1 40 0 20 P o Em IL ie J JL 0 50 0 20 LEAD THICKNESS 0 125Typ or 0 15Typ ee 0 Min STAND OFF 1 70MAX Unit mm The shape of the molded corner may slightly diffe

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