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Nexus 21 1066MT/s Interposer Computer Hardware User Manual

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1. 66 6 3 DDR3D 2 Mnemonics Description a 66 6 4 B DDR3D 2G Mnemonics Description n n 66 6 5 Viewing Timing Data on the TLA 67 TIPS tS s n 8 69 7 1 Symbolic Triggering a Command using DDR3D XX Suppotts 69 7 3 Capturing MRS Mode Register Set 70 VIS Clock Capture accu s sasa aaa 71 We Thresholds 72 APPENDIX How DDR Data is Clocked 73 AT Background u annus ahin t 73 S2 DDR Acquisition Generals u 73 DDR3D 20 2G 34 Data Acduisition n a 74 APPENDIX B 5 ConstleratlOnsu u ans asap 75 1 NEX DDR3INTR THIN Bus Loading n nasa 75 2 DIMM connector location for best quality signal capture 75 8 3 TLA7BB4 Module to APPENDIX 240 pin DDR3 DIMM Pinotut APPENDIX D Data Flow Through the Probes coax cable to channel APPEND
2. 1 or NEX PRB2X T probe The NEX PRB1X T or NEX PRB2X T probe in turn connects to the input of the logic analyzer modules The connection between the LEASH Probes and the logic Analyzer is a Samtec connector with a pin out as shown below on the LEASH probe Refer to 3 2 to determine if a NEX PRB1X T or NEX PRB2X T connects to each LEASH probe The strain relief the LEASH to NEXPRB1X 2X interface while designed for bench handling can be damaged by twisting the coax cables Bends of over 45 degrees in this area should be avoided The coax connection points under any circumstances are not to be bent 3 5 1 Samtec connector on the LEASH probe pins 5 Figure 2 Samtec connector the LEASH probe The LEASH probe connects to the NEX PRB1X T or NEX PRB2X T probe using two plastic nuts and screws with a plastic spacer between the two boards These parts are supplied 3 5 2 LEASH probe to NEX PRB1X 2X connection Probe tip the NEX PRB1X T NEX PRB2X T 1 Two each plastic LI Spacers Screws H Interposer Nuts here Hold each probe together Transition board on the LEASH Cable end Figure 3 LEASH probe to NEX PRB1X 2X connection 3 5 3 Alternate use of NEX PRB1X or NEX PRB2X probes The NEX PRB1X or NEX PRB2X can be used in place of the probes but will have to be secured for long term conn
3. amp D Search t Cursor 1 Cursor 2 v 800ps 2 WEE 13 460ns 14 160ns 15 160ns 16 160ns 17 160ns 18 416005 19 160ns 20 1600 21 1600 5 IV gt B yVu Address 00000 Vu SOF n qivu DORK RASSE E Vu CAS B pvu Strobes 1FF 000 1FF 000 iFF D 000 OFF 000 B Databyte7 14 55 00 1 55 00 II X 9 X DX 5 X X I B I Databyte5 54 B Vu DataByte4 00 55 00 55 00 B IV DataByte 55 X 55 00 X s 00 7 7 X _ X 1X 9 X I Ey Vu DstaBytet 55 15 55 0 55 00 FF 00 FF B Vu D taByte0 55 15 14 55 9 55 00 FF lt gt gt For Help press F1 Tektronix Figure 14 Viewing Individual 8 bit Read Data Groups Custom Options B DDR3E CMidfx 7BB4 B DDR3E CMidf Cape Mears DDR3 lt Ranks DFX Clocking DDR3 Bus Specs RL ALL WL 5 BL 8 RDIMMs Setup Hold Window Clock 15 088ns s 7 617ns RdADatB3 gt Group Channel Setup Hold Window RdADatB7 1 055ns 1 289ns RdADatB6 1 113 1 348ns RdADatB5 2115 1 445ns RdADatB4 1 465ns 1 539ns Figure 15 Setting Individual Setup amp Hold Values for the 8 bit Read Data Groups Note Values shown are for illustration purposes only DDR3THIN MN XXX 61 Doc Rev 1 11 5 8 Setting B DDR3D Read
4. Optional Flying Lead Probe Connection used with B DDR3D 2G software M 2 1 0 DDR3THIN MN XXX 83 Doc Rev 1 11 APPENDIX B DDR3D 3A Support Pinout DIMM Slot 1 Samte Coax TLA DDR3 Samte Coax TLA DDR3 c Pin Pin Channe Signal c Pin Channe Signal 1 1 I 15 J15 6 J16 6 CK3 A13 29 J15 10 J16 10 C3 7 BAI 25 J15 9 J16 9 C3 6 RAS 28 J16 11 J15 11 C3 5 CAS 24 J16 12 J15 12 C3 4 21 J15 8 5 J16 8 C3 3 19 J15 7 J16 7 C3 2 20 J16 13 J15 13 C3 1 16 J16 14 J15 14 3 0 12 6 15 15 15 72 7 10 J16 16 J15 16 C2 6 11 J15 5 J16 5 C2 5 J15 4 J16 4 C2 4 J16 17 J15 17 C2 3 J16 18 J15 18 C2 2 J15 3 J16 3 C2 1 J15 2 J16 2 C2 0 J16 6 J15 6 01 J16 10 15 10 7 116 9 J15 9 C1 6 J15 11 J16 11 CI 5 J15 12 J16 12 J16 8 J15 8 J16 7 3 J15 7 J15 13 J16 13 J15 14 J16 14 J15 15 J16 15 C J15 16 2 116 16 16 5 15 5 4 16 4 15 4 15 17 16 17 15 18 J16 18 NC J16 3 J15 3 NC J16 2 NC 2X Probe Connection used with 1X Probe Connection used with B_DDR3D_2D software B DDR3D 2D software M A3 2 A1 0 M C3 2 1 0 S2 A3 2 D3 2 Logic Analyzer Probe 62 C3 2 1 0 Logic Analyzer Probe APPENDIX G B DDR3D Support Pinout DIMM Slot 1 cont d Samtec 2X Probe Connection used with 2X Probe Connection used with B_DDR3D_2D software B DDR3D 2D software S A3 2 1 0 S C3 2 E3 2 S2 1 0 D1 0 Logic Analyzer Probe S2 E3 2 1 0 Logic Analyzer Probe APPENDIX II Data Gro
5. the connector of the DIMM MB gt Replace 75 ohm resistor with Tektronix input load model Replace 60 ohm input impedance with the below CLK 80 Diff 2 ol Address CMD 50 DDR3THIN MN XXX 89 Doc Rev 1 11 APPENDIX L References JEDEC PC3 6400 PC3 8500 10660 DDR3 SDRAM Unbuffered DIMM Design Specification Revision 0 1 March 20 2006 Tektronix TLA7000 Series Installation Manual Tek part number 071 1747 03 Tektronix TLA7000 Series Technical Reference Manual Tektronix part number 071 1764 00 Nexus Low Profile Distributed Probe Manual Part number LowProfileProbes MN XXX JEDEC DDR3 SDRAM Standard JESD79 3 June 2007 PPENDIX Support About Nexus Technology Inc NEXUS TECHNOLOGY Established in 1991 Nexus Technology Inc is dedicated to developing marketing and supporting Bus Analysis applications for Tektronix Logic Analyzers We can be reached at Nexus Technology Inc P O Box 6575 Nashua NH 03063 TEL 877 595 8116 FAX 877 595 8118 Website http www nexustechnology com Support Contact Information Technical Support techsupport nexustechnology com General Information support nexustechnology com Quote Requests quotes nexustechnology com We will try to respond within one business day If Problems Are Found Document the problem and e mail the information to us If at all possible please forward a Saved System Setup with acquired data that shows the
6. 0030 RD 0029 RD 2028 RD B DQ27 RD B DQ26 RD B DQ25 RD B DQ24 RD B DQ23 RD B DQ22 RD B DQ21 RD B DQ20 RD B 0019 RD B 2018 RD B DQI7 RD 0016 0015 RD 0014 RD 1013 RD 0012 RD 0011 RD 0010 RD DQ9 RD 208 RD DQ7 RD B DQ6 RD B DQ5 RD DQ4 RD B DQ3 RD B DQ2 RD B DQI RD B M 0 671 M 0 371 S 2 0 1 S C2 141 M 0 4 1 M 0 1 1 S C22 l S 2 3 1 S 2 4 1 S 2 571 S C32 l S 3 3 1 S C2 6 l S 2 771 S C3 1 l S 3 471 S 3 6 1 S C3 7 l S 3 4 1 S 3 1 1 S 3 5 1 S 771 S 3 3 1 S 3 2 1 S E3 0 1 S 2 771 S 2 3 1 2 2 1 03 1 2 5 1 2 1 1 E2 0 1 Table 3 B DDR3D lt 1066MT s Read and Write TLA Channel Grouping cont d Notes 1 All signals on this page are required for accurate post processing of acquired data 2 The M in front of a TLA channel denotes the Master card of the merged set 3 The S in front of a TLA channel denotes Slave card 1 of the merged set 4 signals on this page are stored in the TLA7BB4 s Prime memory and will not have MagniVu display value DDR3 TLA DDR3 TLA Pin Input Pin Input DQ63 1 RdA _RD A 031 A 0062 Hex A DQ30 DQ61 _ DQ29 DQ60 _ DQ28 _ 0059 _ DQ27 _ 2058 A 0057 _ 2056 _ 2055 A LX054 _ 053 A 2052 _ DQS1 _ DQSO _ 0049 _ DQ48 _ DQ47 _ DQ46 A DQ45 A DQ44 A DQ43 _ DQ42 _
7. 56 Figure 8 Measuring B DDR3D XX DatHi Lo Read Data Setup amp Hold 57 Figure 9 Setting B DDR3D XX and Lo Sample Points 57 Figure 10 Locating Minimum Valid B DDR3D XX Write Data Window 58 Figure 11 Measuring B DDR3D XX DatHi Lo Write Data Setup amp Hold 59 Figure 12 Measuring B DDR3D_XX WrB_DatHi Lo Write Data Setup amp Hold 59 Figure 13 Setting B DDR3D XX DatHi Lo and WrB DatHi Lo Sample Points 60 Figure 14 Viewing Individual 8 bit Read Data Groups eee 61 Figure 15 Setting Individual Setup amp Hold Values for the 8 bit Read Data Groups 61 Figure 16 B DDR3D XX Lasting Display 63 Fio nte L7 Disassembly Properties tona quseque totas ha ARR 64 Figure 18 B DDR3D XX Listing Display Control Flow eene 65 Figure 19 B DDR3D XX MagniVu Display on TLA eeeeeereeeeennnen een 68 Figure 20 B_ DDR3D_2D MRS Trigger eene dva ms etes 71 Figure 21 MRS Cycle Acquisition Disassembly es a plor 71 TABLE OF TABLES Table 1 B DDR3D 2D lt 1066MT s Read and Write TLA Channel Grouping 19 Table 2 B DDR3D 2G lt 1066MT s Read and Wri
8. DQ41 _ DQ40 A DQ39 _ DQ38 _ DQ37 _ DQ36 DQ35 A DQ34 A DQ33 A DQ32 1 RdA DatHi Hex _RD _RD _RD _RD RD A DQ26 _ DQ25 _ 0024 _ 0023 _ 0022 _RD 0021 _ 0020 _ 0019 _RD 0018 _ 0017 RD 0016 _ 01015 RD DQI4 _ 0013 _RD 0012 0011 RD A 0010 D A DQ9 D A DQ8 D A DQ7 D A DQ6 D A 005 D A DQ4 D A DQ3 D A DQ2 D A D A DQ0 A LA Lm D _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R R R R R R R R R R R R R R R R R R R R R R R R R R R R R 1 1 1 1 1 1 1 1 1 1 Table 3 B_DDR3D_3A lt 1066MT s Read and Write TLA Channel Grouping cont d Notes 1 These signals are acquired from the second DIMM slot 2 signals on this page are required for accurate post processing of acquired data 3 The S2 in front of a TLA channel denotes Slave card 2 of the merged set Signal T Signal Name i Name D 0063 S2 A0 0 l 1 RdB S2 2 6 1 B 2062 2_ 0 1 1 Hex RDB S2 2 31 0061 S2 0 571 RDB 2_ 2 0 1 DQ60 S2 CKI l RDB 82 2
9. SOF Vu RASE Mu CASE lt lt WEF B yVu Strobes 166 B anu Data Hi 55555555 00000000 55555555 00000000 FFFFFFFF B Data 10 55555515 55555555 00000000 55555555 00000000 FFFFFFFF EP Vu DataByte7 00 55 00 1 55 FF lt gt For Help press F1 Figure 12 Measuring B DDR3D XX WrB DatHi Lo Write Data Setup amp Hold The sample point positions must now be set for the WrA DatHi WrA_DatLo WrB DatHi WrB_DatLo groups in the Setup window Figure 13 Note that if the Upper Strobes being DDR3THIN MN XXX 59 Doc Rev 1 11 used as Data Masks then the WrtMasks group should have a Setup amp Hold value that matches that of the Write Data groups Custom Options B_DDR3E_CMidfx 7884 B DDR3E CMidf Cape Mears DDR3 lt Ranks DFX Clocking DDR3 Bus Specs RL ALL Setup Hold Window Clock 15 098ns Strobes 117 117ps Group Channel Setup Hold Window WiA 742ps 508ps WiA DatLo 430ps 195ps WiAChkBits Support Package Default ADatMsks Support Package Default Figure 13 Setting B DDR3D XX WrA_DatHi Lo and WrB DatHi Lo Sample Points Because of the speeds of DDR3 data it may be necessary to program Setup amp Hold values for each of the 8 bit groups that are associated with a given Strobe This could be required if there 1s significant skew between the DDR Strobes Figure 14 shows some of these additio
10. 6 PRE PRECHARGE BANK 1 DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND PRE PRECHARGE BANK DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND Search 0000 FOO OOFFFFOO OOOOF FOO 00000000 00000000 000000 FFFFFFOD FFFFOOFF FF000000 OOFFFFOO OOOOF FFF FF000000 FF000000 FFFFOOFF 00000000 FFFFFFOO FFOOOOFF FF000000 OOFFFFOO FFFFFFFF 0000FF00 DOFFFFFF FFFFOOFF FFFFFFOO 00000000 OOFFFFOO OOFFFFFF OOF FOOFF FFFFFFFF 000000FF FFOOOOFF FFOOOOFF 0000FF00 OOF FOOFF FFOOOOFF 00 70000 FF000000 OOOOF FFF FFFFFFFF FF000000 000000FF 0000FF00 00000000 Figure 16 B DDR3D XX Listing Display DDR3THIN MN XXX 2 375 n 2 500 2 500 2 500 Doc Rev 1 11 To change the display it is necessary to bring up the window s Properties window perform right mouse click the State display window and select the Disassembly tab This will bring up the configuration window shown in Figure 17 Properties B_DDR3D_2D About Data Listing Window Column Marks Disassembly Module B_DDR3D_2D Ni Show Hardware C Disassemble Across Gaps Hardware Highlight Software DDR3D 2D Controls Control Flow Burst Length Subroutine CAS Latency 15 CAS Addit
11. B DDR3D 2G Control Symbol Table Signals left to right bCKE1 bCKE0 CKE1 CKEO cS1 cSOZ bS1 bSOZ S32 S22 S12 50 BA2 BAI A15 A14 A13 Al2 BC A10 AP RAS CASZ WEZ 7 3 Capturing MRS Mode Register Set Cycles If the characteristics of the DDR target latency burst length are not known it is possible to acquire this information using the TLA so that the post processing Control settings can be properly set This information is programmed into the DDR memory upon system boot by use of the MRS Mode Register Set command and is required when using the NEX DDR3INTR THIN supports for the post processing software to properly decode the acquisitions The TLA trigger shown in Figure 19 can be used to acquire the MRS cycles when using either of these supports Note that because there is no Trigger event defined in this example that it will be necessary to Stop the TLA acquisition manually to display the MRS data A trigger could certainly be added in either or both of the Trigger events but the method shown ensures that the last valid MRS cycles will be acquired regardless of the memory depth setting of the acquisition card EA TLA off line Trigger DDR3D 3A E inl x File Edi View System Tools Window Help 811 JU Waveform Status Ide tel tit Storage None Z Force Main Prefill Trigger Pos J Mag
12. B yVu Data Hi AAAABABA AAAABAAA 00000000 100000000 00000000 B iniVu Data Lo EFAFBAFF EFABBAFF 00000000 FFFFFFFF 00000000 00000000 B Vu DataByte7 00 00 lt gt Help press F1 Figure 7 Measuring B DDR3D XX RdA_DatHi Lo Read Data Setup amp Hold Zoom in further to determine the Setup and Hold sample point necessary to acquire valid data at that point Figure 7 and use the cursors to measure the time from the clock edge to the start of valid Read data In this example the delay from edge to data is approximately 1 05ns after the clock edge meaning that a suitable Setup amp Hold value for the RdA DatHi capture group would be 1 055ns 1 289ns Note that the Data Lo group is valid somewhat later than the Data Hi group with its valid time starting at approximately 1 23ns after the clock edge so the Setup amp Hold sample point for the RdA capture group would be set to 1 23ns 1 465ns Now the sample point for the DatHi and groups must be determined see Figure 8 The next valid Read data after the cycle measured above occurs approximately 2 37ns after the rising edge of DDRCKO so a suitable Setup amp Hold value for DatHi capture group would be 2 383ns 2 617ns As with the A data the Data Lo group is somewhat later than the Data Hi group The Data Lo valid time starts at approximately 2 52ns so a suitable Setup amp Hold value for the RdB DatLo capture gro
13. CB7 RD A CB6 RD A 5 RD A 4 RD A CB3 RD A CB2 RD A CBI RD CBO RD B CB7 RD B CB6 RD B CB5 RD B CB4 RD B CB3 RD B CB2 RD CBI RD B CBO A 0M7 00 16 A DM6 DQSI5 A 0M5 00 14 DM4 DQS13 A_DM3 DQS12 A_DM2 DQS11 A_DMI DQS10 DM0 DQS9 DDR3 TLA Pin Input M 1 571 M 4 1 M 0 1 M AQ0 7 l M AL l M 3 1 M CKI l M 0 571 WrAChkBits OFF WrBChkBits OFF BDatMsks BIN Signal Name WR A 7 WR A CB6 WR A CB5 WR A CB4 WR A CB3 WR A CB2 WR A WR A CBO WR B CB7 WR B CB6 WR B 5 WR B CB4 WR B CB3 WR 2 WR B WR B CB0 B_DM7 DQS16 B_DM6 DQS15 B DMS5 DQS14 DM4 DQS13 B DM3 DQS12 B_DM2 DQS11 B DMI DQS10 B DM0 DQS9 M D1 541 M DI 4 l M D1 041 M D0 7 1 M DI 6 1 M DI 3 1 M 0071 0 5 1 S 2 4 1 S 6 1 S 1 0 1 M C2 0 l M 0 2 1 S 1 S 3 5 1 S E2 6 1 Table 2 B DDR3D 2G lt 1066MT s Read and Write TLA Channel Grouping cont d Notes 1 denotes a low true signal The S in front of a TLA channel denotes the Slave card of the merged set The M in front of a TLA channel denotes the Master card of the merged set signals on this page are stored in the TLA7BB4 s Prime memory and will not have MagniVu display value Group Name Control 2 SYM Unprobed Signal Name cCKE1 cCKE0 bCLK1 bCLK0 1 CKEO cS1 cS0 bS1 bS0 S3 S2 51 5
14. NEX DDR3INTR THIN Silkscreen WWW NexusTerchnolagy com L All Right 5 Nexus Technelagy lac Copyright 2007 DDR3INTR BB THIN A0 Made in 1 5 4 Front Silk screen DDR3THIN MN XXX 87 Doc Rev 1 11 APPENDIX I Keep area EGRESS OUT OF TOP oF S 8 lt gt 430 110 92 1 2973 75 51 jl 2X 2 463 62 56 2X 1 024 _ Cog 824 20 92 1 307 78 000 0 MOTHERBOARS gt SURFACE 8 33 85 82 25 85 N ow NOTES 1 ALL DIMS INCHES MM DIMM CONNECTOR VII OPEN LATCH OUTLINE NEXUS DDR3 INTERPOSER KEEPOUT VOLUME 5LIM VERSION STANDARD INTERPOSED DIMM CARD DDR3THIN MN XXX 88 Doc Rev 1 11 APPENDIX Simulation Model Double this if you using two Interposers the same memory channel DIR Straddle Con 1 I 30 achn 3 18 nH Customer DDRDIMM 1 DIMM board to be added 1 1 1 1 1 I 1 1 pss 1 1 1 1 1 i 96 96 tde 175 68 _______ Pantec 20 45 204 7 1 10500 ps Connector 78406 510 Com 78406 i 10 75 Pair 1 hedded Resisto i 34 Coax 1 1 ponnector reat as mechanical 1 antec td 2100 ps 10 75 Logic load DOR3 signal gt
15. permits setting Data Mask functionality to Write Masks default Strobes When set to Write Mask the DM signals will be used to mask Write Data to show which data bytes were valid in the cycle In addition to these Disassembly Properties selections changing the settings in the Show field results in display changes as well Hardware default displays all acquired cycles Software suppresses all idle or wait cycles Control Flow shows Address Command and valid Read Write data cycles Subroutine shows valid Read Write data cycles only E DDR3 List D ge a activity A HS Search gt Cursor 1 y Cursor 2 5ns 1 0 2 C2 2 Delta Time DDR3UA3A DDR 3UAA DDR3UA3A DDR3UA3A DDR3UA3A s T OOFFFFOO 0000FF00 00000000 000000 00000000 FF000000 FFOOOOFF FFFFFFOO FFFFOOFF FF000000 OOFFFFOO OOOOF FFF FF000000 FF000000 FFFFOOFF 00000000 FFFFFF00 FFOOOOFF FF000000 OOFFFFOO FFFFFFFF 0000FF00 OOFFFFFF FFFFOOFF FF000000 FFFFFFOO OOFFFFOO OOF FOOFF FFFFOOOO OOFFFFFF FFFFFFOO 000000 00000000 FFOOFFFF FFFF0000 FFFF0000 OOF FOOFF OOO00F FOO Figure 18 DDR3D XX Listing Display Control Flow 002 0000 0000 00FF0000 FFFFOOFF FFFFFFOO 00000000 0066 6600 OOFFFFFF OOF FOOFF FFFFFFFF 000000FF FFOOOOFF FFOOOOFF 0000FF00 DOFFOOFF FFOOOOFF 00FF0000 FF000000 OOOOF
16. 2 A13 M CK3 ERR OUT M A2 7 A12 BC A2 4 TEST M A3 7 10 M M A3 6 RAS M_C3 6 ODTI M_C3 1 CAS M_C3 5 ODTO M C32 WE C1 7 Misc gt MISCI M A3 5 MISCO M A3 4 DDRCK0 M 1 4 Table 4 B DDR3D 2D 2G lt 1333MT s Read and Write TLA Channel Grouping cont d Notes 1 denotes a low true signal 2 These signals are required for accurate acquisition and post processing of acquired data 3 The 5 in front of a TLA channel denotes the Slave card of the merged pair 4 The M in front of a TLA channel denotes the Master card of the merged pair 5 MISCI and MISCO are placeholders only and will not have interesting data on them Group Signal TLA Group Signal TLA Name Name Input Name Name Input Data H DQ63 Data L DQ31 i 0 2062 2030 2061 0029 2028 0059 0027 0058 2026 0057 0025 0056 2024 0055 2023 0054 2022 0053 1021 1052 2020 0051 2019 2050 0018 DQ49 DQ17 DQ48 016 0047 0015 2046 2014 2045 2013 2044 0012 2043 0011 2042 2010 1041 209 2040 208 2039 207 2038 2037 005 2036 204 0035 2034 202 2033 001 2032 DQO Table 5 B DDR3D TLA MagniVu Channel Grouping Notes 1 The S in front of a TLA channel denotes the Slave card of the merged pair 2 The M in front of a TLA channel denotes the Master card of the merged pair Signal TLA Group Signal TLA Name Name Input Name Name Input DataByte 2063 S_A2 0 Data
17. 20ps increments Each 32 bit data group RdA_DatHi RdA DatLo RdB DatHi will require its own value programmed from the measurements noted in the MagniVu window Custom Options B DDR3E CMidfx DDR3 Bus Specs RL ALL Data Filtering Enabled Setup Hold Window Clock 15 038ns s 7 617ns RdB_Da Group Channel Setup Hold Window RdA_DatHi 1 289ns RdA_DatLo 23ns 1 465ns RdAChkBits Support Package Default RdB_DatHi 2 383ns 2 617 ns Figure 9 Setting B DDR3D XX RdA_DatHi Lo and DatHi Lo Sample Points DDR3THIN MN XXX 57 Doc Rev 1 11 Setting the Setup amp Hold values for acquiring Write data 1 similar process determine the Write Data group sample points first make an appropriate acquisition of Write data by triggering on a Write Command Then as above create a timing window display of MagniVu data and display the Data Hi and Data Lo 32 bit data groups the individual Command group signals and the DDR3 clock that was used for the data acquisition DDRCK0 A sample waveform display of MagniVu Write data 15 shown in Figure 10 To determine the sample point locate the smallest window of valid Write data during the acquired burst see Figure 10 Note that in this instance the first piece of valid data happens before the rising edge it is associated with This shift must be taken into account or data
18. 2X connection essere 17 3 5 3 Alternate use of NEX PRB1X or NEX PRB2X probes 17 3 6 Slot Numbering 18 37 Display Groups not in Tables 1 2 or 3 39 40 CLOCK SELECTION 40 41 B_DDR3D 2D Clocking Selections 40 42 B_DDR3D 2C Clocking Selections 41 43 B _DDR3D 34 Clocking Selections 43 5 0 CONFIGURING FOR READ WRITE DATA ACQUISITION 44 5 1 A Note About the Different Data Groups 44 2 2 MasniN s ese m ee attese a tto Eoo ae 44 5 3 Adjusting Input Thresholds for Proper Data Acquisition 53 od nnt adotta 53 5 5 Selecting DDR3E XX Read Data Sample Points sse 53 5 6 Selecting B DDR3D XX Write Data Sample 18 54 57 B_DDR3D 55 5 8 Setting DDR3D Read Data Sample Points 62 GO VIEWING DIA a EE A 63 6 1 Viewing B DDR3D XX uelit e 63 6 2 Viewing Raw DDR3 Data using B DDR3D XX
19. 3 Bank x Write command initiates a burst write access to active row Slot A B or C Chip Select 0 3 Bank x Valid Write data on the bus ZQ Calibration Long Slot A B or C Chip Select 0 3 ZQ Calibration Short Slot A B or C Chip Select 0 3 Table 7 B DDR3D 2G Mnemonics Definition 6 5 Viewing Timing Data on the TLA By default the TLA will display an acquisition in the Listing State mode However the same data can be displayed in Timing form by adding a Waveform Display window This is done by clicking on the Window pull down selecting New Data Window clicking on Waveform Window Type then choosing the Data Source Two valid choices are presented DDR3D XX and B DDR3D XX MagniVu The first will show the exact same data same acquisition mode as that shown in the Listing window except in Waveform format The second selection will show all of the channels in 8 MagniVu mode so that edge relationships can be examined around the MagniVu trigger point MagniVu is very useful and in some cases necessary to see resolve DDR3 data With either selection all channels can be viewed by scrolling down the window Refer to the TLA System User s Manual for additional information on formatting the Waveform display Figure 19 DDR3D_XX MagniVu Display TLA DDR3THIN MN XXX 68 Edit view Data System Tools Window
20. 527 in front of a TLA channel denotes Slave card 2 of the merged set All signals on this page are stored in the TLA7BB4 s Prime memory and will not have a MagniVu display value ae tae WrA DatHi Hex Table 3 B DDR3D lt 1066MT s Read and Write TLA Channel Grouping cont d Notes 1 Allsignals on this page are required for accurate post processing of acquired data Signal Name WR A DQ63 WR A DQ62 WR A DQ61 WR DQ60 WR A DQS9 WR A DQS8 WR A 0057 WR A DQS6 WR A DQSS WR A 054 WR DQS3 WR A 052 WR A DQSI WR A DQSO WR A 049 WR A DQ48 WR A DQ47 WR A DQ46 WR DQ45 WR A DQ44 WR A DQ43 WR A DQ42 WR A 041 WR 040 WR DQ39 WR A DQ38 WR A DQ37 WR A DQ36 WR A DQ35 WR A DQ34 WR A DQ33 WR A DQ32 DDR3 TLA Pin Input WrA DatLo Hex Signal Name WR A DQ31 WR A DQ30 WR A DQ29 WR A DQ28 WR A DQ27 WR A DQ26 WR A DQ25 WR A DQ24 WR A DQ23 WR A 022 WR 021 WR A DQ20 WR A DQI9 WR A 0018 WR A 0017 WR A 016 WR A 0015 WR A 0014 WR A DQI3 WR A DQI2 WR A WR A 0010 WR A DQ9 WR A WR A DQ7 WR A DQ6 WR A DQS WR A DQ4 WR A DQ3 WR A DQ2 WR A WR A DQO DDR3 TLA Pin 2 The in front of a TLA channel denotes the Master card of the merged set 3 The S in front of a TLA channel denotes Slave card 1 of the merged set Input Signal DDR3 TLA Signal Name Pin Input Name WrB_DatHi WR DQ63 5 2 071 WrB_DatLo WR D
21. A DQ26 WR A DQ25 WR A DQ24 WR A DQ23 WR A 022 WR 021 WR A DQ20 WR A DQI9 WR A 0018 WR A 0017 WR A 016 WR A 0015 WR A 0014 WR A DQI3 WR A DQI2 WR A WR A 0010 WR A DQ9 WR A WR A DQ7 WR A DQ6 WR A DQS WR A DQ4 WR A DQ3 WR A DQ2 WR A WR A DQO DDR3 TLA Pin 2 The in front of a TLA channel denotes the Slave card of the merged pair Input WrB_DatHi Hex Signal Name WR B DQ63 WR B DQ62 WR B DQ61 WR B DQ60 WR B 0059 WR B DQS8 WR 0057 WR 0056 WR 0055 WR 0054 WR 0053 WR 0052 WR 0051 WR 0050 WR 0049 WR B 01048 WR B DQ47 WR B DQ46 WR B DQ45 WR B DQ44 WR B DQ43 WR B DQ42 WR 0041 WR 01040 WR 0039 WR DQ38 WR B DQ37 WR B DQ36 WR B DQ35 WR B DQ34 WR 0032 WR B DQ33 DDR3 Pin TLA Input S D2 0 1 S 2 171 S 2 571 S 071 5 2 271 S 2 371 5 2 771 S D3 0 1 5 D32 1 S D3 3 1 5 D3 7 1 S 01 571 S 03 1 1 5 03 4 1 S 01 7 1 S 01 6 1 S 01 4 1 S 1 1 1 S D0 7 1 S D0 6 1 S_D1 341 S 01 2 1 S 0 571 S D0 4 1 S D0 3 1 S D0 2 1 M 0 171 M 0 471 S D0 1 1l S D0 0 1 M 0 671 M 0 771 WrB_DatLo Hex Signal Name WR B DQ3I WR B DQ30 WR B DQ29 WR B DQ28 WR B DQ27 WR B DQ26 WR B DQ25 WR B DQ24 WR B DQ23 WR B DQ22 WR B DQ 2I WR B DQ20 WR B DQI9 WR B 1018 WR B 0017 WR B 2016 WR B 0015 WR B 1014 WR B 0013 WR B DQI2 WR B WR B DQIO WR B DQ9 WR B DQS8 WR B DQ7 WR B DQ6
22. DQ30 RD A DQ29 RD A DQ28 RD A DQ27 RD A DQ26 RD A DQ25 RD A DQ24 RD A DQ23 RD A DQ22 RD A 021 RD A DQ20 RD A DQI9 RD A DQIS8 RD A 0017 RD A 0016 RD A 0015 RD A 0014 RD A DQI3 RD A DQI2 RD A 0011 RD A DQIO RD A DQ9 RD RD A DQ7 RD A DQ6 RD A 005 RD A 004 RD A DQ3 RD A DQ2 RD A RD A DQO Table 1 B DDR3D 2D lt 1066 5 Read and Write TLA Channel Grouping DatHi Signal Name RD_B_DQ63 RD_B_DQ62 RD B DQ61 RD B DQ60 RD B DQ59 RD 2058 RD 2057 RD 0056 RD 2055 RD 2054 RD 0053 RD 0052 RD DQSI RD B DQ50 RD B DQ49 RD B DQ48 RD B DQ47 RD B DQ46 RD B DQ45 RD B DQ44 RD B DQ43 RD B DQ42 RD B DQ41 RD B DQ40 RD B DQ39 RD B DQ38 RD B DQ37 RD B DQ36 RD B DQ35 RD B DQ34 RD B DQ33 RD B DQ22 S A2 0 l S 2 1 1 S 2 571 S S 2 2 1 S 2 371 A2 7 l S 3 071 S A32 l S 3 371 S 7 S 1 571 S A3 1 l S 3 471 S AL 7 S AL6 l S 14 S 11 S A0 7 l 0 671 S AL3 l S 12 0 571 0 471 S 0 371 S A02 l M C2 141 2 471 S 0 171 8 0 071 C2 6 1 2 7 1 Signal Name RD 0031 RD 0030 RD 0029 RD 2028 RD B DQ27 RD B DQ26 RD B DQ25 RD B DQ24 RD B DQ23 RD B DQ22 RD B DQ21 RD B DQ20 RD B 0019 RD B 2018 RD B DQI7 RD 0016 0015 RD 0014 RD 1013 RD 0012 RD 0011 RD 0010 RD DQ9 RD 208 RD DQ7 RD B DQ6
23. DQ57 VSS DQS7 DQS7 VSS 0058 0059 VSS SAO SLC SA2 VIT Back Side right 181 240 X64 Non Parity DM6 DQS15 DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 DQS16 DQS16 VSS DQ62 DQ63 VSS VDDSPD SAI SDA VSS 72 DM6 DQS15 DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 DQS16 DQS16 VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT APPENDIX D Data Flow Through Probes coax cable to channel Data flow Slave1 C3 2 1 0 Master A3 2 D3 2 Master C3 2 1 0 Slave1 A3 2 D3 2 Slave1 E3 2 1 0 Master A1 0 D1 0 Slave1 A1 0 D1 0 Plastic Housing that plugs into TLA 7BB4 522 Samtec Connectors plug together at this 114412 J15 x top J16 x 415 1 edge 416 1 edge Interposer Master A3 2 amp Slave1 A3 2 amp A1 0 Slave1 C3 2 amp E3 2 Master APPENDIX D Data Flow Through the Probes 4 Coax wire A3 2 1 0 A3 2 1 0 C3 2 E3 2 Channel Channel Channel Channel APPENDIX E DDR3D 2D Support Pinout DIMM Slot 0 Samtec Coax TLA DDR3 Samte Coax TLA DDR3 Pin Pin Channe Signal c Pin Signal 1 1 1 CK3 A13 C3 7 BA1 C3 6 RAS C3 5 CAS C3 4 51 C3 3 50 C3 2 ODTO C3 1 ODTI C3 0 52 2 7 2032 2 6 2033 2 5 538 2 4 2036 2 3 DQS4 C
24. Data Sample Points The same procedure outlined above for setting Read Data sample points should be used to determine the sample points for Read Data from teh second DIMM slot Set the sample points for the groups named RdA DatHi 1 RdA 1 DatHi 1 and 1 6 0 VIEWING DATA 6 1 Viewing B DDR3D XX Data When using the NEX DDR3INTR THIN support packages the raw Address and Data groups are suppressed and are replaced with post processed data in new groups This data is displayed in new groups that have the support package name preceding it 1 B DDR3D XX Address B DDR3D XX DataHi etc The raw data groups are suppressed so that the display of data can be done in a more user friendly fashion The Command group is suppressed because its function is replaced with a column labeled DDR3D XX Mnemonics The Interposer support software includes post processing code that permits masking out all invalid Read Write and non Command data providing the user a much better overview of bus activity Figure 16 shows the default B DDR3D XX display where all DDR3 data is displayed EZ 0083 List 3 ES ERG t Cursor 1 Y top Cursor 2 w 51 0 2 2 Delta Time 5ns DDR3UA3A ppr ZAAGA DDR3UA3A DDR3UA3A PDDR3UA3A DDR3UA3A dress Mnemonics DataHi DataLo DataMasks ss DESL IGNORE COMMAND D NOR OMMAND PRE PRECHARGE BANK
25. Help 74 Sample Point Import Tool u Protocol Designer E Verify S AutoDeskew Tl setup A Trigger 257 Waveform Listing Run Tek Idle 6 X 3 1 Activity value Q Time Div 1 St Cursor 1 to 2 19ps gt 2 Waveform 4 500 3ns 1 500ns 1 500ns 3n 4 500ns Bns 7 500 5 10 500 5 12ns 13 500ns 1515 16 500 5 18ns 19 500ns 21ns 6 289 21 054 19 B miu Address 00000 40098 00000 JagniVu KEO SOF Vu DDRCLKC L L E Ll L I Ld LU I Vu RAS C45 V WEF Mu 2057 L I L L B Vu DataByte7 55 M 14 90 Y 55 og 55 00 X L B DataByte ss X 55 X 00 ss Y oo B Vu D taByte5 55 55 54 00 55 00 55 00 fagniVu B Vu Databyte4 ss 55 51 00 55 00 55 00 fagniVu 2053 LJ Ld L I 8 B Vu D taByte2 ss 55 00 55 00 BP Vu D taByte2 55 55 X 00 55 T 00 M Y jj wu lt gt For Help press F1 Tektronix Doc Rev 1 11 7 0 HINTS amp TIPS 7 1 Symbolic Triggering on a Command using B DDR3D XX Supports A Symbol Table has been included for the Control data groups defined in each of the support packages The Symbol Table for the B DDR3D 2D 3A supports is shown in Table 8 the Symbol Table for the B DDR3D 26 support is shown in Table 9 The use of Symbol Tables when triggering makes it easier fo
26. Import Tool Protocol Designer iverify SE AutoDeskew setup Trigger MY waveform foi Listing p Idle gt BS X view Manyu activity OF value Q d Time Div 1 5 C D Search E E At v 2 1 4 S6ns Waveform 3 1 500ns Ops 1 500ns 3ns 4 500ns amp ns 7 50015 Ons 10 500ns 1215 13 500ns 15ns 16 500ns 18ns 19 500ns 21ns 22 500ns 24ns 5 4 003 ns H 24 297 ns VI Sampi 2 Eb 2 Actress 00000 40006 00000 4agniVu KEO Latency My SOF d Minimum BPV RAS R E ead Command Read S amp H WEF Data Begins B Strobes 000 B 3nVu Data Hi 00000000 Ep Vu Data to 00000000 B Vu DataByte7 00 lt For Help press F1 Figure 6 Locating Minimum Valid B DDR3D XX Read Data Window DDR3THIN MN XXX 55 Doc Rev 1 11 R File Edit view Data System Tools Window Help 4 Sample Point Import Tool a Protocol Designer iverify SE AutoDeskew il setup trigger waveform 9292 Listing D RS 1 activity OF value Q 4 Time Div 500 D Search to Cursor 2 v 1 0513 Waveform 14 460ns 15 460ns 18 480 lt 5 21 460 21 895 ns Eb miu Actress iVu SOF DDR CL RAS CASE B Strobes 1FF 1FF
27. RD B DQ5 RD DQ4 RD B DQ3 RD B DQ2 RD B DQI RD B M 0 671 M 0 371 S 2 0 1 S C2 141 M 0 4 1 M 0 1 1 S C22 l S 2 3 1 S 2 4 1 S 2 571 S C32 l S 3 3 1 S C2 6 l S 2 771 S C3 1 l S 3 471 S 3 6 1 S C3 7 l S 3 4 1 S 3 1 1 S 3 5 1 S 771 S 3 3 1 S 3 2 1 S E3 0 1 S 2 771 S 2 3 1 2 2 1 03 1 2 5 1 2 1 1 E2 0 1 Table 1 B DDR3D 2D lt 1066MT s Read and Write TLA Channel Grouping cont d 1 All signals on this page are required for accurate post processing of acquired data 2 The in front of a TLA channel denotes the Slave card of the merged pair 3 Allsignals on this page are stored in the TLA7BB4 s Prime memory and will not have a MagniVu display value WrA DatHi Hex Table 1 B DDR3D 2D lt 1066MT s Read and Write TLA Channel Grouping cont d Notes 1 Allsignals on this page are required for accurate post processing of acquired data Signal Name WR A DQ63 WR A DQ62 WR A DQ61 WR DQ60 WR A DQS9 WR A DQS8 WR A 0057 WR A DQS6 WR A DQSS WR A 054 WR DQS3 WR A 052 WR A DQSI WR A DQSO WR A 049 WR A DQ48 WR A DQ47 WR A DQ46 WR DQ45 WR A DQ44 WR A DQ43 WR A DQ42 WR A 041 WR 040 WR DQ39 WR A DQ38 WR A DQ37 WR A DQ36 WR A DQ35 WR A DQ34 WR A DQ33 WR A DQ32 DDR3 TLA Pin Input WrA DatLo Hex Signal Name WR A DQ31 WR A DQ30 WR A DQ29 WR A DQ28 WR A DQ27 WR
28. Search v At 2 14 365 2 1 450 3ns 1 5001 Ops 1 50015 4 5005 7 5001 95 10 500ns 1215 13 5005 1815 16 500 18ns 19 5005 24ns 6 328 ns 21 446 ns B Address 00000 4000 00000 SOF Mu DDROLK L T EI i E ES L I L I L L RASH CASH Sample LL 2 _ WEF Sample Pt 1 BP 2 Vu Strobes 000 1 000 EP Data Hi 00000000 B Vu D tagyte7 00 Measurements Trigger Tektronix For Help press F1 Figure 4 Read Data Latency CAS Latency CAS Additive Latency RDIMM 5 0 1 6 cycles 5 6 Selecting B DDR3D XX Write Data Sample Points Unlike valid DDR Read data valid Write data is bisected by the Strobes Since valid DDR3 Write data is bisected by the Strobes see Figure 5 the Setup amp Hold sample point must be set for the valid data that occurs closest to the clock edge The appropriate clock edge for Writes is determined by counting the number of clock cycles specified by the Write Latency MRS value from the Write Command to the first valid Write Data If these values are not known the technique described in Section 7 3 can be used to determine them In Figure 5 the total Write latency is 6 cycles Write Latency plus the additional one cycle delay for RDIMM memory File Edit
29. View Data System Tools Window Help Sample Point Import Tool wm Protocol Designer iverify XE AuteDeskew trigger 1 waveform IV Listing z Sutus gt By h ES view a Maniu activity OF value Q Q Time Div 15 e HO Search 20 At 1 2 1505 Waveform 500ns 3ns 1 500ns Ops 1 500ns 3ns 4 500ns 6ns 7 500ns 10 500 5 12ns 13 500ns 15ns 16 500ns 18ns 19 500ns 21ns 22 500ns gniVu 4 668 ns 23 633 ns B miu Address 00000 40098 AagniVu KED Vu SOF qu DDRCL K RASH Vu CASE Sample Pt 1 Sample Pt 2 WEF Strobes Write Data Preamble 2 B pn Data Hi 55555555 B miu Data 55555555 By Vu Databyte7 55 gt press F1 Figure 5 Write Data Latency CAS Write Latency RDIMM 5 1 6 cycles DDR3THIN MN XXX 54 Doc Rev 1 11 The B DDR3D XX supports acquire two samples of valid Write data each rising edge of the DDR3 clock So to acquire both pieces of data the WrA DatHi Lo data groups must have their sample point set to that shown by Sample Pt 1 in the Figure and DatHi Lo data groups must have their sample point set to that shown by Sample Pt 2 NOTE It is important to note that because of the design of the TLA acquisition card inputs and the Strobe activity prior to Write data be
30. denotes the Master card of the merged pair Notes 1 eb Signal TLA Group Signal TLA Name Name Input Name Name Input ChkBits ChkBits_1 1_CB7 1 CB6 1 5 1 CB4 1 1 CB2 1 1 1 Strobes 17 DataMasks Address BA2 M_A3 0 BAI M_C3 7 BAO C1 6 15 14 42 5 13 M CK3 AI2 BCK A24 A2 6 Control M 3 2 A10 AP M C1 3 CKE0 A31 9 A21 S3 S2_C2 5 8 42 0 S2 S2 C3 0 42 3 Sl M_C3 4 A6 C02 50 M C33 AS M A22 BA2 M A3 0 A4 BAI M C3 7 A3 BAO M CI 6 A2 A15 M Al A14 M A2 5 A0 A13 M CK3 Orphans PAR IN AI2 BCK A2 4 ERR OUT 10 C1 3 TEST RAS amp M C3 6 RESET CASH M 3 5 ODTI WE 7 ODTO Misc MISC A3 5 MISCO 43 4 DDRCK0 4 Table 5 B DDR3D 3A lt 1333MT s Read and Write TLA Channel Grouping cont d denotes low true signal These signals are required for accurate acquisition and post processing of acquired data The S in front of a TLA channel denotes the Slave card of the merged pair The M in front of a TLA channel denotes the Master card of the merged pair and MISCO are placeholders only and will not have interesting data on them 5 3 Adjusting Input Thresholds for Proper Data Acquisition The Interposer DDR3 support was designed to work with the new Nexus Low Profile Distributed probes To maximize the electrical chara
31. made up of two DIMM slots with single or dual rank DDR3 DIMMS running 1066MT s orless This is total disassembly for the 2 DIMM memory channel This support requires 5ea NEX PRBI X T and 3ea NEX PRB2X T Low Profile Distributed probes and three merged Tektronix TLA7BB4 acquisition cards This support also requires two NEX DDR3INTR THIN Interposer products This support be used with Single Rank and Dual Rank DIMMs Note that this manual uses some terms generically For instance references to the TLA700 7000 apply to all suitable TLA700 7000 Logic Analyzers or PCs being used to control the TLA NEX DDR3INTR THIN refers to the B DDR3D_2D 2G 3A software support packages Appendix G has a silk screened print of the NEX DDR3INTR THIN Logic Analyzer Interposer board Referring to this drawing while reading the manual is suggested This manual assumes that the user is familiar with the DDR3 SDRAM Specification and the Tektronix TLA Logic Analyzers It is also expected that the user is familiar with the Windows environment used with the TLA 1 3 Eye size required The Eye size stable data required at the input resistor to the Nexus passive probes NEX PRBIX T amp NEX PRB2X T is 330ps and 0 2V Capture accuracy may be affected if a stable eye can not meet this requirement The eye is a perfectly shaped diamond with each side equal distant from the center 2 0 SOFTWARE INSTALLATION To Install the NEX DDR3INTR THIN software supp
32. should be connected to the DDR3 DIMM Interposer as follows using 1 NEX PPRB1X T probes and three 3 NEX PRB2X T probes with the additional NEX PRB1X T connected to the NEX PRBCOAX TLA Master Connect the NEX PRB1X T C probe head to DDR3 Interposer s LEASH soldered on coax cable that is attached to ML C position on the Interposer Connect the NEX PRB2X T A3 2 amp A1 0 probe head to DDR3 Interposer s LEASH that is attached to _ A3 2 1 0 position on the Interposer Connect the NEX PRB1X T E probe head to the NEX PRBCOAX Note the leads 9 12 of the NEX PRBCOAX must be connected to the second slots Chip Select lines CS near the second and third DIMM socket usually on the back of the mother board Match the label on the end of the NEX PRBI X T 2X T probes with the labels on the front of the Tektronix Logic Analyzer Master module and connect TLA Slave Connect the NEX PRB2X T A3 2 amp A1 0 probe head to DDR3 Interposer s LEASH that is attached to 5 A3 2 A1 0 position on the Interposer Connect the NEX PRB2X T 3 2 amp E3 2 probe head to DDR3 Interposer s LEASH that is attached to 5 C3 2 E3 2 position on the Interposer See Figure 1 for connections Table 2 shows the Channel Grouping Wiring for use with the B DDR3D 29G support 3 4 B DDR3D 3A Support To acquire DDR3 Read and Write data from a two DIMM slots for total memory channel disassembly at speeds up to 1066MT
33. the Tektronix Analog Mux will display amplitudes and thresholds that are not an exact representation of the actual analog waveform The Nexus passive probes used on DDR3 NEXVu and Interposer products are designed to supply maximum voltage swing to the Logic analyzer to insure correct digital signal swing capture at the high DDR3 rates While the Tektronix active P69xx and P68xx series of probe being general purpose probes divide the input voltage swing by 20 the passive probes from Nexus divide the signals by approximately 7 5 Since the divide value is different than the standard Tektronix probe the voltage swing and offset will be higher than expected and the thresholds will be different Instead of the expected 0 75 threshold of approximately 1 9V threshold will be required This was designed specifically for DDR3 signals to allow the best possible capture of the digital representation of these signals Viewing the output of the Logic Analyzer analog mux should be used as a tool to provide fine adjustment of the logic analyzer signal Vref The threshold value determined in this manner should be used as the threshold setting for the Nexus DDR3 product Please note Only the vertical resolution is affected by the Nexus passive probes APPENDIX How DDR Data is Clocked Background Demultiplexing means that the TLA s Logic Analyzer card can have one data probe connected to the target yet store incoming data in two or four separate data s
34. will not be aligned properly in the Listing display window Note that A and B data corresponding to ADataHi Lo and BDataHi Lo data groups have been indicated Refer to section 5 6 for important information on properly determining the Write data sample points A o B File Edit View Data System Tools Window Help Sample Point Import Tool E Protocol Designer iverify SE AutoDeskew il setup trigger waveform 292 Listing Status amp X 8 view 1 activity OF value Q Q Time Div 1 515 f Search At 2 15 Waveform 5005 1 500ns Ops 1 500ns 4 500 7 500ns 9ns 10 500ns 12ns 13 500ns 15ns 16 500ns 18ns 19 500ns 21ns 22 500ns 4 668 ns H 23 633 ns Sampi 2 1 BP miu Address 00000 40098 00000 KEO Latency Magnivu SOF DDRCLK RAS lt Write Command gt Vu CASE B VagniVu WEF M B pu Strobes 100 i Write Data B pivu Data Hi 55555555 Preamble Minimum S amp H B miu Data 55555555 y Databyte7 1 55 gt For Help press F1 Figure 10 Locating Minimum Valid B DDR3D XX Write Data Window Zoom in further to determine the Setup and Hold sample point necessary to acquire valid data at that point Figure 11 and use the cursors to measure the time from the cl
35. 0 842 1 840 15 14 13 A12 BC RAS CAS WE MISCI MISCO DDRCK0 All DQSx DDRCK1 SAI SDA SA0 SCL From Slot C From Slot C From Slot B From Slot B 169 50 From Slot C From Slot C From Slot B From Slot B 49 48 76 193 52 190 71 171 172 196 174 70 192 74 73 Placeholder Placeholder 184 185 M A3 5 M A3 4 M 4 Address Hex Ungrouped Signal Name BA2 BAI 15 14 13 A12 BC All 9 8 7 6 5 4 2 1 0 0098 1 0098 DM8 ERR_OUT RESET TEST ODTO ODTI PAR IN TLA Input DDR3 Pin Table 2 B DDR3D 2G lt 1066MT s Read and Write TLA Channel Grouping cont d Notes 1 denotes a low true signal 2 These signals are required for accurate acquisition and post processing of acquired data 3 The S in front of a TLA channel denotes the Slave card of the merged set 4 The in front of a TLA channel denotes the Master card of the merged set RdA_DatHi Hex Notes Signal Name RD A DQ63 RD A DQ62 RD A DQ6I RD A DQ60 RD A DQS9 RD A 2058 RD A DQ57 RD A DQS6 RD A DQSS RD A 2054 RD A DQS3 RD A 0052 RD A DQSI RD A 0050 RD A DQ49 RD A DQ48 RD A DQ47 RD A DQ46 RD A 0045 RD A DQ44 RD A DQ43 RD A DQ42 RD A DO4I RD A 2040 RD A DQ39 RD A DQ38 RD A DQ37 RD A DQ36 RD A DQ35 RD A DQ34 RD A DQ33 RD A DQ32 DDR3 Pin TLA Input RdA DatLo Hex Sig
36. 0 and 51 are active equivalent to one Single Rank DIMM and two Dual Rank DIMMs C 10 8 10 0 2r2rir cS1 cSOZ bS1 bS0 and S0 are active equivalent to two Dual Rank DIMM and a Single Rank DIMM 10 10 10 2r2r2r cS1 cSOZ 551 bSOZ 51 and 50 are active equivalent to three Dual Rank DIMMs 4 3 B DDR3D 3A Clocking Selections There is one clocking option field available when using the B DDR3D 34A support package This select field sets up the TLA acquisition as follows SDRAM DDR CLKO Clocking Permits selecting the Clocking Mode to be used to acquire DDR3 data Only one choice is available Every Rising Edge As the name implies this will cause the acquisition card to acquire data on every Rising edge of the DDR Clock 0 5 0 CONFIGURING FOR READ WRITE DATA ACQUISITION Prior to configuring your NEX DDR3INTR THIN support package it is strongly recommended that Appendix A How DDR Data is Clocked section 5 4 Selecting DDR Read Sample Points and section 5 5 Selecting DDR Write Sample Points be read This background information is very helpful and facilitates proper support configuration 5 1 Note About the Different Data Groups The NEX DDR3INTR THIN support software have three different areas where signal groups are defined to provide specific functionality There are the MagniVu data groups see Table 4 are the groups that contain raw MagniVu data Storage data groups
37. 1 1 DQ59 S2 A02 l RDB S2 2 4 1 DQ58 S2 0 371 82 02 14 DQ57 S2 A0 7 l RDB S2 E2 2A1 DQ56 2_ 1 0 1 B 2_ 2 3 1 9055 S2 A12 l RD S2 2 4 1 DQ54 S2 1 3 1 RDB S2 E2 5 l DQ53 S2 1 7 1 RDB S2 E3 2A1 DQ52 S2 1 5 1 B S2 3 3 1 _DQ51 2_ 1 1 1 _RD_ S2 2 671 _ 050 S2 1 4 1 RDB 82 2 771 DQ49 S2 0174 RDB S2 E3 1 l DQ48 S2 01 64 RD S2 E3 4 1 DQ47 S2 1 4 1 _RD B_ S2 671 DQ46 S2 01 11 RDB S2 E3 7 l 9045 S2 D0 7 l RDB S2 1 4 1 DQ44 S2 0 6 1 RDB 2_ 1 1 1 _I0043 S2 01 31 B S2 E3 5 l DQ42 S2 1 2 1 2_ 1 7 1 DO4I S2 D0 5 l RDB 2_ 1 3 1 DQ40 S2 D0 4 l RD S2 EI2 l DQ39 S2 D0 3 l RDB S2 1 0 1 DQ38 S2 D02 l RDB S2 0 771 _ 037 2_ 2 1 1 gt gt S2 E0 3 l DQ36 S2 2 4 1 RDB S2 0 271 DQ35 S2 D0 l l RDB 82 0271 DQ34 S2 D0 0 1 B S2 0 5 1 DQ33 S2 2 671 RDB S2 0 171 DQ32 S2 2 7 1 RDB S2 0 071 1 RdB DatHi Hex 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R _R a Table 3 B_DDR3D_3A lt 1066MT s Read and Write TLA Channel Grouping cont d Notes 1 These signals are acquired from the second DIMM slot All signals on this page are required for accurate post processing of acquired data The
38. 12 BC RAS CAS WEZ Symbol Definition CCCC SSSSSSSS XXXXXI 1110 for 50 ssssssss xxxx1x 1101 for S1 SSSSSSSS xxxxx1 1011 for S2 ssssssss 1 0111 for S3 ssssssss xxxxx1 1110 for bSO ssssssss xxxx1x 1101 for bS1 ssssssss xxxxx 1011 for cSO ssssssss xxxx1x 0111 for cS1 x in Definition Don t Care MRS Sx MODE REGISTER SET CCCC SSSSSSSS XXX Xxx xx000 MRS bSx MODE REGISTER SET CCCC SSSSSSSS XXX XXx xx000 MRS cSx MODE REGISTER SET CCCC SSSSSSSS xx000 REF Sx REFRESH 55555555 xx001 PRE Sx SINGLE BANK PRECHARGE CCCC SSSSSSSS Xxx 0010 PREA Sx PRECHARGE ALL BANKS CCCC SSSSSSSS Xxx 1010 ACT Sx ACTIVATE BANK SSSSSSSS XXX XXX 011 WR Sx WRITE CCCC SSSSSSSS xxx x0100 WRA Sx WRITE WITH AUTO PRECHARGE SSSSSSSS x1100 RD Sx READ SSSSSSSS Xxx 0101 RDA Sx READ WITH AUTO PRECHARGE NOP Sx NO OPERATION CCCC SSSSSSSS XXX X1101 CCCC SSSSSSSS XXX XXX 111 DES DEVICE DESELECT CCCC SSSSSSSS XXX XXX XXXXX ZQCL Sx ZQ CALIBRATION LONG Ssssssss xxx xxx x1110 55555555 xxx xxx x0110 ZQCS 5 ZQ CALIBRATION SHORT Table 9
39. 2 2 NC C2 1 2037 2 0 DM4 01 2 1 7 WE C1 6 BAO 1 5 0 1 4 CKO 3 1 2 1 C1 0 0 7 C0 6 0 5 C0 4 C0 3 C0 2 C0 1 C0 0 2X Probe Connection used with 1X Probe Connection used with B DDR3D 2D software B DDR3D 2D software M A3 2 A1 0 C3 2 C1 0 APPENDIX E DDR3D 2D Support Pinout DIMM Slot 0 Cont d Samtec Coax TLA DDR3 Samtec Coax TLA DDR3 Pin Pin Channel Signal Pin Pin Channel Signal J15 6 J15 6 Q3 DQ3 J15 10 J15 10 E3 7 DQ10 J15 9 J15 9 E3 6 0051 J16 11 J16 11 E3 5 DMI J16 12 J16 12 E3 4 0013 J15 8 J15 8 E3 3 DQ9 J15 7 J15 7 E3 2 16 13 J16 13 0012 J16 14 J16 14 E3 0 DQ7 J16 15 J16 15 E2 7 DQ6 J16 16 J16 16 E2 6 DM0 J15 5 J15 5 E2 5 DQ2 J15 4 J15 4 E2 4 DQS0 J16 17 J16 17 E2 3 005 J16 18 J16 18 E2 2 DQ4 J15 3 J15 3 E2 1 001 J15 2 J15 2 E2 0 DQ0 J16 6 J16 6 CK3 DM2 J16 10 J16 10 C3 7 DQ14 J16 9 J16 9 C3 6 0015 75 1 115 11 C3 5 0011 15 12 15 12 C3 4 2016 J16 8 J16 8 C3 3 DQ20 J16 7 J16 7 C3 2 2021 15 13 15 13 C3 1 0017 I15 14 J15 14 C3 0 DQS2 15 15 15 15 C2 7 0018 15 16 15 16 2 6 2019 J16 5 J16 5 C2 5 DQ22 J16 4 J16 4 C2 4 DQ23 J15 17 J15 17 C2 3 DQ24 J15 18 15 18 C2 2 DQ25 J16 3 J16 3 C2 1 DQ28 J16 2 J16 2 C2 0 DQ29 2X Probe Connection used with 2X Probe Connection used with B DDR3D 2D software B DDR3D 2D software S A3 2 1 0 S C3 2 2 APPENDIX DDR3 2G Support Pinout DIMM Slot 0 Auxiliary Signals TLA DDR3 Channe Signal
40. 515 AAAAAAAA 55555555 00000000 55555555 00000000 FFFFFFFF Ep Mu DataByte7 14 00 55 f 00 55 oo FF sS gt EN 5 For press F1 Tektronix Figure 11 Measuring B_DDR3D_XX WrA_DatHi Lo Write Data Setup amp Hold Now the sample point for the WrB_DatHi and WrB_DatLo groups must be determined see Figure 12 The next valid Write data after the cycle measured above occurs approximately 500ps after the rising edge of DDRCK0 so a suitable Setup amp Hold value for the WrB_DatHi capture group would be 508ps 742ps As with the A data the Data Lo group is somewhat later than the Data Hi group The Data valid time starts at approximately 800ps so a suitable Setup amp Hold value for the WrB_DatLo capture group would be 801ps 1 035ns A R m El Eile Edit View Data System Tools Window Help 74 Sample Point Import Tool Protocol Designer iverify lt 8 AutoDeskew Al setup Trigger MY waveform 155 Listing Run Tek status Idle 9 959 X iview Magu Activity OF value 500 v D Search v 1 hd toll Cursor 2 430ps Waveform 60ns 13 260ns 14 260ns 15 260ns 16 260ns 17 260ns 1 18 260ns 19 260ns 20 260ns 21 260ns 2 Mu HnInc Q B miu Address 00000 CKED
41. 68 X64 Non Parity A2 VDD CK1 VDD VDD VREF NC Par In VDD 0 VDD WE CAS VDD SI RSVD ODTI VDD RSVD SPD VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 0041 V55 0085 0085 VSS DQ42 DQ43 VSS DQ48 DQ49 X72 ECC A2 VDD VDD VDD VREF NC Par In VDD A10 AP BAO VDD WE CAS VDD 51 RSVD ODTI VDD RSVD Spd3 VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS 2040 0041 V55 DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 Back Side right 181 240 Pin 181 182 183 184 185 86 X64 Non Parity Al VDD VDD CK0 CK0 VDD X72 ECC Al VDD VDD CK0 CK0 VDD TEST NC A0 A0 A13 VDD Free VSS DQ36 DQ37 VSS DM4 DQS13 DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5 DQS14 DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS APPENDIX 240 DDR3 DIMM Pinout cont d Front Side left 1 60 X64 Non Parity VSS DQS8 DQS8 VSS NC NC VSS Free KEY RESET CKE0 VDD NC ERR OUT VDD All A7 VDD A5 A4 VDD X72 ECC VSS DQS8 DQS8 VSS CB2 CB3 VSS Free RESET CKEO VDD BA2 NC ERR OUT VDD All A7 VDD A5 A4 Back Side right 121 180 X64 X72 Non Parity ECC Front Side left 61 120 X64 Pin X72 Non Parity FCC VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56
42. Byte DQ31 7 3 DQ62 S_A2 1 DQ30 2061 S_A2 5 DQ29 5 CKO 2028 2059 5 A22 2027 2058 5 2 3 2026 2057 5 27 2025 2056 S A3 0 DQ24 DataByte DataByte DQ23 6 2 DQ22 DQ21 DQ20 DQ19 DQ18 2017 2016 DataByte DataByte 2015 5 1 2014 2013 2012 2011 2010 209 DataByte DataByte DQ7 4 0 DQ6 DQ5 DQ4 DQ3 DQ2 1 DQ0 Table 5 B DDR3D TLA MagniVu Channel Grouping cont d Notes 1 The front ofa TLA channel denotes the Slave card of the merged pair 2 The M in front of a TLA channel denotes the Master card of the merged pair Signal TLA Group Signal TLA Name Name Input Name Name Input Data L0_ 1 Table 5 B DDR3D TLA MagniVu Channel Grouping Notes 1 The S in front of a TLA channel denotes the Slave card of the merged pair 2 The M in front of a TLA channel denotes the Master card of the merged pair Signal TLA Group Signal TLA Name Name Input Name Name Input DataByte7_ DataByte3_ 12031 1 1 1 2030 1 2029 1 2028 1 2027 1 2026 1 2025 12024 DataByte6_ DataByte2_ 1 2023 1 1 1 2022 1 2021 1 2020 1 0019 1 2018 1 DQI7 1 2016 DataByte5_ DataBytel_ 1 2015 1 1 12014 1 2013 1 2012 1 1 2010 1 209 1208 DataByte4_ DataByte0_ 1 1 Table 5 B DDR3D 3A TLA MagniVu Channel Grouping cont d Notes 1 The in front of a TLA channel denotes the Slave card of the merged pair 2 The M in front of a TLA channel
43. FFF FFFFFFFF FF000000 000000 0000 FOO 00000000 00000000 7000000 FFFF0000 OOF FOOFF FFOOFFOO FFFFOOOO FF000000 00FF0000 FFFFFFOO 00000000 FFFFOOOO OOF FFFFF 00FF0000 FFFF0000 FFFF0000 Changing the Show field setting in the display of Figure 16 from Hardware to Control Flow results in the display of Figure 18 where only Row and Column Address commands and valid DDR3THIN MN XXX 65 Doc Rev 1 11 data displayed Note that the timestamp is updated to reflect the time between displayed cycles 6 2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports In order to make the display of DDR3 data more user friendly the raw data from the Address all Data and other groups is suppressed in the B DDR3D 2D Listing display Instead the post processing display software formats and reorders the data to tag and display valid DDR3 Address Commands and Data In the case of the B DDR3D 2D supports which stores two Read and two Write data cycles in each TLA Sample location the data is reordered chronologically in the display with the oldest data being shown on the line above the newer data To see the raw data using the Interposer support package perform a right mouse click in the Listing window select Add Column then click on the group to be added Refer to the TLA User s Manual or online help for further information on added or deleting data groups 6 3 B DDR3D 2 Mnemonics Description Table 6 gives a br
44. IX E DDR3D 2D Support Pinout DIMM Slot O sse APPENDIX F DDR3 2G Support Pinout DIMM Slot 0 Auxiliary Signals APPENDIX G B DDR3D Support Pinout DIMM Slot 1 APPENDIX Data Group Data Byte Strobe Cross Reference APPENDIX I NEX DDR3INTR THIN 2 2 02 2020 000 000000000000 APPENDIX J Keep Out uoto au et iiit APPENDIX Simulation Model connate eva gut eem au APPENDIX dc APPENDIX M Support TABLE FIGURES Figure 1 Drawing of Interposer with probes attached serene 15 Figure 2 Samtec connector on the LEASH 16 Figure 3 LEASH probe to 2 connection aaa 17 Figure 4 Read Data Latency CAS Latency CAS Latency RDIMM 5 0 1 6 So ue maaa An DU D Mu E EE 54 Figure 5 Write Data Latency CAS Write Latency RDIMM 5 1 6 cycles 54 Figure 6 Locating Minimum Valid B DDR3D XX Read Data Window 55 Figure 7 Measuring DDR3D XX DatHi Lo Read Data Setup amp Hold
45. MI DQS10 B DM0 DQS9 M D1 541 M DI 4 l M D1 041 M D0 7 1 M DI 6 1 M DI 3 1 M 0071 0 5 1 S 2 4 1 S 6 1 S 1 0 1 M C2 0 l M 0 2 1 S 1 S 3 5 1 S 2 671 Table 1 B DDR3D 2D lt 1066MT s Read and Write TLA Channel Grouping cont d Notes 1 denotes a low true signal 2 The S in front of a TLA channel denotes the Slave card of the merged set 3 The M in front of a TLA channel denotes the Master card of the merged pair 4 Signals in these groups are acquired using the TLA s demux capability and will not have a MagniVu display value DDR3 TLA Signal Pin Input Name Control CKE1 Address BA2 SYM CKEO Hex BAI 538 0 S2 15 51 14 50 13 2 A12 BC BAI All BAO A10 AP 15 9 14 8 13 7 A12 BC A10 AP 5 RAS A4 CAS A3 WE A2 Strobes Al HEX A0 MISCI Placeholder MISCO Placeholder DDRCKO0 184 185 M 4 Ungrouped 2058 DM8 ERR_OUT Unprobed All DQSx RESET DDRCK1 63 64 TEST SAI 237 ODTO SDA 238 ODTI SAO 117 PAR_IN SCL 118 Table 1 B_DDR3D_2D TLA Channel Grouping cont d Notes 1 denotes low true signal These signals are required for accurate acquisition and post processing of acquired data The S in front of a TLA channel denotes the Slave card of the merged pair The M in front of a TLA channel denotes the Master card of the merged pair Signals in these groups are acquired us
46. NEXUS TECHNOLOGY NEX DDR3INTR THIN DDR3 800 1066MT s Interposer For use with the TLA7BB4 Logic Analyzer Modules Including these Software Support packages B DDR3D 2D Single Dual Quad Rank single slot with Selective Clocking DDR3D 2G 2 or 3 DIMM slots two Rank 800MT s DDR3D 2 DIMM slots two Rank 1066MT s Optional Software Copyright O 2007 Nexus Technology Inc All rights reserved Contents of this publication may not be reproduced in any form without the written permission of Nexus Technology Inc Brand and product names used throughout this manual are the trademarks of their respective holders DDR3THIN MN XXX 1 Doc Rev 1 11 Product Warranty Due to wide vartety of possible customer target implementations this product has a 30 day acceptance period by the customer from the date of receipt If the customer does not contact Nexus Technology within 30 days of the receipt of the product it will be said that the customer has accepted the product If the customer 15 not satisfied with this product they may return it within 30 days for a refund This Nexus Technology product has a warranty against defects in material and workmanship for a period of 1 year from the date of shipment During the warranty period Nexus Technology will at its option either replace or repair products proven to be defective For warranty service or repair this product must be returned to the factory For products retu
47. NEXUS Technology for other available DDR3 Products The Nexus Technology web site www NexusTechnology com contains information on the latest software release 1 2 Software Package description The NEX DDR3INTR THIN support includes the following software packages B_DDR3D_2D allows the user to acquire Read AND Write data from a single dual or quad rank DDR3 DIMM running 1066MT s or less This support requires lea NEX and NEX PRB2X T Low Profile Distributed probes and two merged Tektronix TLA7BB4 acquisition cards This support can use selective clocking to reduce the number of Idle states acquired by the logic analyzer Optional software available for the NEX DDR3INTR THIN support includes the following software packages B_DDR3D_2G allows the user to acquire Read AND Write data from a memory channel made up of two or three DIMM slots with one or two rank DDR3 DIMMs running 800MT s or less This is total disassembly for the 3 DIMM memory channel This support requires 2ea NEX PRB1X T and 3ea NEX PRB2X T Low Profile Distributed probes and two merged Tektronix TLA7BB4 acquisition cards This support also requires the NEX PRBCOAX product This support can be used with Single Rank and Dual Rank DIMMs will also support a single quad rank DIMM Reads for the three DIMMs must have a common data eye over lap of 330ps No selective clocking B DDR3D 3A allows the user to acquire Read AND Write data from a memory channel
48. PRBI X T probes and three 3 NEX PRB2X T probes TLA Master Connect the NEX PRBIX T probe head to DDR3 Interposer s LEASH soldered on coax cable that is attached to M C position on the Interposer Connect the NEX PRB2X T A3 2 amp A1 0 probe head to DDR3 Interposer s LEASH that is attached to A3 2 A1 0 position on the Interposer Match the label on the end of the NEX PRBI X T 2X T probes with the labels on the front of the Tektronix Logic Analyzer Master module and connect TLA Slave Connect the NEX PRB2X T A3 2 amp A1 0 probe head to DDR3 Interposer s LEASH that is attached to 5 A3 2 A1 0 position on the Interposer Connect the NEX PRB2X T 3 2 amp E3 2 probe head to DDR3 Interposer s LEASH that is attached to 5 C3 2 E3 2 position on the Interposer See Figure 1 for connections Table 1 shows the Channel Grouping Wiring for use with the B DDR3D 2D support 3 3 B DDR3D 2G Support To acquire DDR3 Read and Write data from two or three DIMM slots for total memory channel disassembly at speeds up to 800MT s requires two merged TLA7BB4 136 channel with 1 4G state option acquisition cards and the use ofthe B DDR3D 26 optional support software The Master card will be in the lower numbered of the two cards Slave card 1 will be in the adjacent high numbered slots This support requires additional NEX PRB1X T for a total of 2 and the NEX PRBCOAX product The logic analyzer modules
49. Q3I M D0 6 1 Hex WR B DQ62 S 2 171 Hex WR B DQ30 M D0 3 1 WR B DQ6I S 2 571 WR B DQ29 S C0 0 1 WR B DQ60 S 071 WR B DQ28 S 0 171 WR DQ59 5 2 271 WR DQ27 M D0 4 1 WR B DQS 8 S D2 3 1 WR B DQ26 M 0 171 WR 2057 S 2 771 WR B DQ25 S 0 271 WR B DQ56 S D3 0 1 WR B DQ24 S C0 3 1 WR B 2055 5 D32 1 WR B DQ23 S C0 4 1 WR B DQ 54 S D3 3 1 WR B DQ22 S C0 5 1 WR DQ 3 5 D3 7 1 WR B DQ I S C1 2 1 WR 2052 S 01 571 WR B DQ20 S CI 3 1 WR B 1051 S 03 1 1 WR B DQI9 S C0 6 1 WR 050 5 03 4 1 WR B 0018 S C0 7 1 WR B DQ49 S 01 7 1 WR B 0017 S WR B DQ48 S 01 6 1 WR B 016 5 C1 4 1 WR DQ47 S 01 4 1 WR 015 S CI 6 1 WR B DQ46 S 1 1 1 WR B 0014 S CI 7 1 WR B DQ45 S D0 7 1 WR DQI3 5 1 471 WR B DQ44 S D0 6 1 WR B DQI2 S WR B DQ43 S_D1 341 WR 5 571 WR B DQ42 S DI 2 1 WR B 0010 S 1 771 WR B DQ41 S 0 571 WR B DQ9 S 1 371 WR B DQ40 S D0 4 1 WR B DQ8 S EL2 1 WR B DQ39 S D0 3 1 WR B DQ7 S 1 071 WR B DQ38 S D0 2 1 WR B DQ6 S E0 7 1 WR B DQ37 M 0 171 WR B 5 S 0 371 WR B DQ36 M 0 471 WR B DQ4 S E0 2 1 WR B DQ35 S D0 1 1l WR B DQ3 S 271 WR B DQ34 S D0 0 1 WR B DQ2 S 0 571 WR B DQ232 M 0 671 WR B 001 S 0 171 WR B DQ33 M 0 771 WR B DQO S E0 0 1 Table 3 B DDR3D lt 1066MT s Read and Write TLA Channel Grouping cont d Notes 1 All signals on this page are required for accurate post processing of acquired data 2 The M in front of a TLA channel
50. RD_B_DQ37 RD_B_DQ36 RD_B_DQ35 RD_B_DQ34 RD_B_DQ33 RD 0032 2 0 1 2 1 1 2 571 S 2 2 1 2 371 2 7 1 3 0 1 A32 l 3 1 7 1 571 1 1 17 1 6 1 4 1 1 1 1 0 7 1 S 0 6 1 S 1 3 1 S 1 2 1 S 0 571 0 471 0 371 0 271 M C2 1 l M C2 4 l S 0 171 S 0 0 1 M C2 6 1 M 2 7 1 RdB DatLo Hex Signal Name RD 0031 RD B DQ30 RD B DQ29 RD B DQ28 RD B DQ27 RD B DQ26 RD B DQ25 RD B DQ24 RD B DQ23 RD B DQ22 RD 0021 RD 2020 RD 0019 RD 1018 RD 2017 RD B 0016 RD B 015 RD B 014 RD B DQI3 RD B DQI2 RD B 0011 RD B DQIO RD B DQ9 RD B RD B DQ7 RD B DQ6 RD B 005 RD B 004 RD B DQ3 RD B DQ2 RD B RD B DQO M 0 671 M A0 3 1 S C2 0 1 S 2 1 1 M 0 471 M 0 171 S 2 2 1 S 2 3 1 S C2 4 1 S 2 5 1 S 3 271 S C3 3 1 S C2 6 1 S 2 7 1 S 3 171 S C3 4 1 C3 6 1 S 3 771 S E3 4 1 S E3 1 1 S C3 5 1 S E3 7v S E3 3 1 S E32 1 S E3 0 1 S E2 7 1 S E2 3 1 S 2 271 S 0371 S 2 571 S E2 1 1 S E2 0 1 Table 2 B DDR3D 2G lt 1066MT s Read and Write TLA Channel Grouping cont d 1 All signals on this page are required for accurate post processing of acquired data 2 The S in front of a TLA channel denotes the Slave card of the merged set 3 signals on this page are acquired using the TLA s demux capability and will
51. WR 005 WR 004 WR B DQ3 WR B DQ2 WR B DQI WR B M D0 6 l M D0 3 l S C0 0 l S 0 171 M D0 4 l M DO0 l l S 0 271 S 0 371 S 0 471 S 0 571 S 1 2 1 S 1 3 1 S 0 671 S C0 7 l S C1 141 S 1 44 S CL6 l S CL7 l S 1 4 1 S 1 1 1 S 1 5 1 S 174 S 1 3 1 S EL2 l S 1 0 1 S E0 7 1 S 0 371 S E0 2 1 S CK2 l S 0 5 1 S 0 171 S E0 0 1 1 All signals on this page are required for accurate post processing of acquired data 2 The S in front of a TLA channel denotes the Slave card of the merged pair 3 Allsignals on this page are stored in the TLA7BB4 s Prime memory and will not have a MagniVu display value RdAChkBits OFF RdBChkBits OFF ADatMsks BIN RD CB7 RD A CB6 RD A 5 RD A 4 RD A CB3 RD A CB2 RD A CBI RD CBO RD B CB7 RD B CB6 RD B CB5 RD B CB4 RD B CB3 RD B CB2 RD CBI RD B CBO A 0M7 00 16 A DM6 DQSI5 A 0M5 00 14 DM4 DQS13 A_DM3 DQS12 A_DM2 DQS11 A DMI DQSIO DM0 DQS9 DDR3 TLA Pin Input M 1 571 M 4 1 M 0 1 M AQ0 7 l M AL l M 3 1 M CKI l M 0 571 WrAChkBits OFF WrBChkBits OFF BDatMsks BIN Signal Name WR A 7 WR A CB6 WR A CB5 WR A CB4 WR A CB3 WR A CB2 WR A WR A CBO WR B CB7 WR B CB6 WR B 5 WR B CB4 WR B CB3 WR 2 WR B WR B CB0 B_DM7 DQS16 B_DM6 DQS15 B DMS5 DQS14 DM4 DQS13 B DM3 DQS12 B_DM2 DQS11 B D
52. WR B DQ37 WR B DQ36 WR B DQ35 WR B DQ34 WR 0032 WR B DQ33 DDR3 Pin TLA Input S D2 0 1 S 2 1 1 S D2 5 1 S 01 S D2 2 1 S D2 3 1 S D2 7 1 S D3 0 1 S D3 2 1 S D3 3 1 S D3 7 1 S_D1 5 1 S_D3 1 1 S_D3 4 1 S_D1 7 1 S_D1 6 1 S_D1 4 1 S_D1 1 1 S_D0 7 1 S_D0 6 1 S_D1 3 1 S_D1 2 1 S_D0 5 1 S_D0 4 1 S D0 3 1 S D0 2v M 0 171 M 0 471 S 0 1 S D0 0 1 M 0 6 1 M C0 7 1 WrB_DatLo Hex Signal Name WR B DQ3I WR B DQ30 WR B DQ29 WR B DQ28 WR B DQ27 WR B DQ26 WR B DQ25 WR B DQ24 WR B DQ23 WR B DQ22 WR B DQ 2I WR B DQ20 WR B DQI9 WR B 1018 WR B 0017 WR B 2016 WR B 0015 WR B 1014 WR B 0013 WR B DQI2 WR B WR B DQIO WR B DQ9 WR B DQS8 WR B DQ7 WR B DQ6 WR 005 WR 004 WR B DQ3 WR B DQ2 WR B DQI WR B M D0 6 l M D0 3 l S C0 0 l S 0 171 M D0 4 l M DO0 l l S 0 271 S 0 371 S 0 471 S 0 571 S 1 2 1 S 1 3 1 S 0 671 S C0 7 l S C1 141 S 1 44 S CL6 l S CL7 l S 1 4 1 S 1 1 1 S 1 5 1 S 174 S 134 S 1 241 S 1 0 1 S 0 7 1 S E0 3 1 S E0 2 1 S CK2 l S 0 571 S 0 171 S E0 0 1 1 All signals on this page are required for accurate post processing of acquired data 2 The S in front of a TLA channel denotes the Slave card of the merged set 3 Allsignals on this page are stored in the TLA7BB4 s Prime memory and will not have a MagniVu display value RdAChkBits OFF RdBChkBits OFF ADatMsks BIN RD
53. cteristics of the acquired waveforms the probe input resistors values were placed at 510 ohms This value results in a divide by ten of the signals to the logic analyzer when using the NEX PRB1X T and NEX PRB2X T probes The logic analyzer expects a divide by 20 Since the divide value is different than the standard Tektronix probe the voltage swing and offset will be higher than expected and the thresholds will be different Instead of the expected 0 75 threshold of approximately 1 9V threshold will be required Use of the logic analyzer output to a scope will be required to determine the exact threshold for the system under test 5 4 DDR3 and DDR3SPA It is strongly recommended that Nexus DDR3SPA DDR3 Sample Point Analyzer be used to determine the proper sample point setting necessary for accurate Read and Write data acquisition Given the correct DDR bus parameters Latency Burst Length etc SPA will analyze any Read and or Write bus transactions in MagniVu memory and return suggested sample points Refer to the DDR SPA documentation for more specific information on using this software If for whatever reason DDR3SPA doesn t appear to provide good sample point setting information the following sections describe how to evaluate acquired DDR3 data to determine the proper sample points manually 5 5 Selecting B_DDR3E_XX Read Data Sample Points For the DDR3 Read data to be properly acquired it is necessary to choose the proper sample poi
54. d not yet specified the module to module skew that will be displayed in MagniVu and timing modes This skew is around 300ps It is expected that in future releases Tektronix will remove this skew Contact Tektronix for updates APPENDIX 240 pin DDR3 DIMM Pinout Front Side left 1 60 X64 Non Parity VREF VSS DQ0 1 V55 0080 0090 VSS DQ2 DQ3 VSS 008 009 V55 DQS1 DQSI vss 0010 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS 0018 0019 VSS DQ24 DQ25 VSS DQS34 DQS3 VSS DQ26 DQ27 VSS NC NC X72 ECC VREF VSS DQ0 001 V55 DQS0 DQS0 VSS DQ2 DQ3 VSS 008 009 V55 DQS1 DQSI vss 0010 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS 0018 0019 VSS DQ24 DQ25 VSS DQS34 0093 VSS DQ26 DQ27 VSS CB0 1 Back Side right 121 180 X64 Non Parity VSS DQ4 005 VSS DM0 DQS9 NC DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM DQS10 NC DQS10 VSS DQ14 0015 VSS DQ20 0021 VSS DML2 DQS11 DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 DQS12 DOS 12 VSS DQ30 0031 VSS NC NC VSS X72 ECC VSS DQ4 DQ5 VSS DM0 DQS9 NC DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DMI DQS10 NC DQS10 VSS 0014 0015 VSS DQ20 0021 VSS DML2 DQS11 DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 DQS12 DQS12 VSS DQ30 DQ31 VSS CB4 CB5 VSS Front Side left 61 120 Pin 61 62 63 64 65 66 67
55. denotes the Master card of the merged set 3 The S in front of a TLA channel denotes Slave card 1 of the merged set 4 All signals on this page are stored in the TLA7BB4 s Prime memory and will not have a MagniVu display value RdAChkBits OFF RdBChkBits OFF 1 RdAChkBits OFF ADatMsks BIN Signal Name RD A CB7 RD A CB6 RD A 5 RD A CB4 RD A CB3 RD A CB2 RD A 1 RD A CBO RD B CB7 RD B CB6 RD B CB5 RD B CB4 RD B CB3 RD B 2 RD RD B CBO A DMT DQSI6 A_DM6 DQS15 A_DMS5 DQS14 A_DM4 DQS13 A_DM3 DQS12 A_DM2 DQS11 A_DM1 DQS10 A DMO0 DQS9 DDR3 TLA Pin Input M AL5 l M AL4 l M 0 1 A0 7 1 M 6 1 M 3 1 M CKI l 0 5 1 WrAChkBits 4 OFF WrBChkBits OFF 1_RdBChkBits OFF BDatMsks 4 BIN Signal Name WR 7 WR CB6 WR A CB5 WR A CB4 WR A CB3 WR A CB2 WR WR A CBO WR B CB7 WR B CB6 WR B 5 WR B CB4 WR B CB3 WR B CB2 WR B WR B CB0 B 0M7 00516 B DM6 DQSI5 B 0 5 0814 B DM4 DQS13 B DM3 DQS12 B_DM2 DQS11 B DM1 DQS10 B DM0 DQS9 DDR3 TLA Pin Input M D1 541 M DI 4 l M D1 041 M D0 7 1 M DI 6 1 M DI 3 1 M 004 0 5 1 S2 DX 5 l S2 D3 4 1 S2 D3 0 1 S2 2 7 1 S2 D3 6 1 S2 D3 3 l 82 0071 S2 D2 5 l S 2 471 S A3 6 l S 1 0 M C2 0 1 M 0 271 S S 3 5 1 S 2 671 Table 3 B DDR3D lt 1066MT s Read and Write TLA Channel Grouping co
56. e second Interposer Connect the NEX PRBIX T 1 0 D1 0 probe head to DDR3 Interposer s LEASH that is attached to 5 A3 2 AT 0 position on the second Interposer Connect the NEX PRB1X T probe head to DDR3 Interposer s LEASH that is attached to ML C3 2 C1 0 position on the second Interposer Connect the NEX PRBIX T probe head to DDR3 Interposer s LEASH that is attached to 5 C3 2 E3 2 position on the second Interposer See Figure 1 for connections Table 3 shows the Channel Grouping Wiring for use with the B DDR3D support 3 5 Short LEASH probes The standard product includes 4 probes connected to this Interposer product These short probes are soldered directly onto the interposer and interface the Interposer to the Passive probes that connect to the logic analyzer These LEASH probes are to allow the user to easily install and remove the Interposer product in their system with out the added weight of the passive probe attached There may be other probing options in the future Contact Nexus for any updates Figure 1 below shows the location on the Interposer of the LEASH probe connections Location of HCD connectors right under metal compression plate and probe tip board PRIMARY SIDE VIEW Figure 1 Drawing of Interposer with probes attached The four 4 each 1 foot long LEASH probes that are soldered onto the Interposer are in turn connected to either
57. ection by tie wraps 3 6 Slot Numbering The Interposer must be installed in the furthest slot from the memory controller For 1066MT s support only the two furthest slots may be used Slots are named as shown below Slot naming for a three slot system Memory controller m ES SlotC SIOtB Slot A cS0 1 bS0 1 S0 3 cCLKEO 1 bCLKEO 1 CLKEO from NEX from NEX PRBCOAX PRBCOAX If only one slot is used it must be the furthest slot from the memory controller If two slots are used they must be the furthest slots from the memory controller Quad rank is only supported in the single slot configuration Interposer in any two or three slot configuration must be in the furthest slot 1066MT s full channel support B DDR3D 34A requires two interposers in the two furthest slots from the memory controller RdA_DatHi Hex Notes 1 All signals on this page are required for accurate post processing of acquired data 2 The S in front of a TLA channel denotes the Slave card of the merged pair Signal Name RD A DQ63 RD A DQ62 RD A DQ6I RD A DQ60 RD A DQS9 RD A 2058 RD A DQ57 RD A DQS6 RD A DQSS RD A 2054 RD A DQS3 RD A 0052 RD A DQSI RD A 0050 RD A DQ49 RD A DQ48 RD A DQ47 RD A DQ46 RD A 0045 RD A DQ44 RD A DQ43 RD A DQ42 RD A DO4I RD A 2040 RD A DQ39 RD A DQ38 RD A DQ37 RD A DQ36 RD A DQ35 RD A DQ34 RD A DQ33 RD A DQ32 DDR3 Pin TLA Input RdA DatLo Hex Signal Name RD A DQ3I RD A
58. ections of the card For instance the A3 data section 8 bits can be connected to the target and data can be stored in the A3 section and the D3 section Using the equivalent of 4X demux by utilizing both the cross point switch and prime memory capabilities of the acquisition card connections made to the A3 channels permit data to be stored in the A3 A3B prime channels D3 and D3B sections A very useful side benefit of using demux is that since only one set of TLA data channels has to be connected only one probe load is added to the target even though data is stored in two or four different locations of the acquisition card 2 DDR Acquisition General All of the above is background necessary to understand how the TLA is able to acquire data at rates that initially look too fast The speeds of DDR3 1066 MT s require different setups to enable proper data acquisition In addition instead of trying to use the 8 Data Strobes to acquire data our solution uses CLKO of the DDR SDRAM Clocks and all data acquisition is adjusted in relation to the clock edges The 8 Data Strobes cannot be easily used to acquire data as some TLA configurations only support 4 Clock Inputs Also the Strobes cannot be used to acquire Address and Command information B DDR3D 20 2 Data Acquisition These supports requires two 2 merged 136 channel with 1 4G state option TLA7BB4 acquisition cards used in a TLA7XX logic analyzer Data is acquired usi
59. es a brief description of each of the text lines displayed in the B DDR3D_2G post processing software display Mnemonic ACT BANK ACTIVATE 5 9 cS Bank DESL IGNORE COMMAND E MRS EXTENDED MODE REGISTER SET x Sx4 bS cS NO OPERATION Sx bS cS PRE SINGLE BANK PRECHARGE Sx bS cS Bank PREA PRECHARGE ALL BANK Sx bS CV RDA READ W AUTO PRECHARGE Sx bS cS Bank RD READ Sx bS cS Bank READ DATA REF REFRESH Sx bS 5 WRA WRITE W AUTO PRECHARGE Sxit bS cS Bank WR WRITE Sx bS cS Bank WRITE DATA ZQCL 70 CALIBRATION LONG Sx bS cS ZQCS ZQ CALIBRATION SHORT Sx 5 cS Description Active command activate a row in a bank for subsequent access Slot A B or C Chip Select 0 3 Bank x Deselect function no new command Mode Register Set command registers 0 3 Slot A B or C Chip Select 0 3 No Operation command Slot A B or C Chip Select 0 3 Precharge command Slot A B or C Chip Select 0 3 Bank x Precharge All command Slot A B or C Chip Select 0 3 Read command with auto precharge Slot A B or C Chip Select 0 3 Bank x Read command initiates burst read access to active row Slot A B or C Chip Select 0 3 Bank x Valid Read data on the bus Self Refresh command Slot A B or C Chip Select 0 3 Write command with auto precharge Slot A B or C Chip Select 0
60. ief description of each of the text lines displayed in the B DDR3D 2A 3A post processing software display Mnemonic Description ACT BANK ACTIVATE Sx Bank Active command activate row in a bank for subsequent access Chip Select 0 3 Bank x DESL IGNORE COMMAND Deselect function no new command E MRS EXTENDED MODE Mode Register Set command registers 0 3 REGISTER SET x Sx Chip Select 0 3 NO OPERATION 5 No Operation command Chip Select 0 3 PRE SINGLE BANK PRECHARGE Sx Precharge command Chip Select 0 3 Bank x Bank PREA PRECHARGE ALL BANK Sx Precharge All command Chip Select 0 3 RDA READ W AUTO PRECHARGE Read command with auto precharge Chip Select 0 3 Bank x Sx Bank RD READ Sx Bank Read command initiates burst read access to active row Chip Select 0 3 Bank x READ DATA Valid Read data on the bus REF REFRESH Sx Self Refresh command Chip Select 0 3 WRA WRITE W AUTO PRECHARGE Write command with auto precharge Chip Select 0 3 Bank x Sx Bank WR WRITE Sx Bank Write command initiates a burst write access to active row Chip Select 0 3 Bank x WRITE DATA Valid Write data on the bus ZQCL ZQ CALIBRATION LONG Sx ZQ Calibration Long Chip Select 0 3 ZQCS ZO CALIBRATION SHORT Sx ZQ Calibration Short Chip Select 0 3 Table 6 B DDR3D 2 Mnemonics Definition 6 4 B DDR3D 2G Mnemonics Description Table 7 giv
61. ing placed on the data bus it will appear as if the Strobes indicate valid Write data earlier than the data is actually there see the circle indicated as Write Data Preamble in Figure 5 These Write Preamble Strobe edges should NOT be used to determine where valid Write data 15 on the data bus 5 7 B DDR3D XX Support Setup Using the B DDR3D XX supports it is possible to acquire both Read and Write data by setting the sample point of the data groups appropriately To adjust the Read Data group sample points first make an appropriate acquisition of Read data by triggering on a Read command Then create a timing window display of MagniVu data and display the Data Hi and Data 32 bit data groups the individual Command group signals and the DDR3 clock that was used for the data acquisition DDRCKO A sample waveform display of MagniVu Read data is shown in Figure 6 To determine the sample point locate the smallest window of valid Read data during the acquired burst see Figure 6 Note that in this instance the first piece of valid data happens significantly after the rising edge it is associated with In fact the initial valid data appears at the DDR Clock falling edge This delay must be taken into account or data will not be aligned properly in the Listing display window Note that A and B data corresponding to ADataHi Lo and BDataHi Lo data groups have been indicated A o RD El File Edit View Data System Tools Window 54 Sample Point
62. ing the TLA s demux capability and will not have a MagniVu display value dra E RdA_DatHi Hex Notes 1 All signals on this page are required for accurate post processing of acquired data 2 The S in front of a TLA channel denotes the Slave card of the merged set Signal Name RD_A_DQ63 RD A DQ62 RD A DQ6I RD A DQ60 RD A 0059 RD A 2058 RD A 0057 RD A DQS6 RD 02055 RD 2054 RD 2053 RD 2052 RD 2051 RD 12050 RD 0049 RD 2048 RD 0047 RD 2046 RD 2045 RD DQ44 RD DQ43 RD A DQ42 RD A 041 RD A DQ40 RD A DQ39 RD A DQ38 RD A DQ37 RD A DQ36 RD A DQ35 RD A DQ34 RD A DQ33 RD A DQ32 DDR3 Pin TLA Input RdA DatLo Hex Signal Name RD A DQ3I RD A DQ30 RD A DQ29 RD A DQ28 RD A DQ27 RD A DQ26 RD A DQ25 RD A DQ24 RD A DQ23 RD A DQ22 RD A DQ I RD A DQ20 RD A DQI9 RD A DQ18 RD A DQI7 RD A 0016 RD A 0015 RD A 0014 RD A 0013 RD A DQI2 RD A RD A DQIO RD A DQ9 RD RD A DQ7 RD A DQ6 RD A 005 RD A 004 RD A DQ3 RD A DQ2 RD A RD A DQO Table 2 B DDR3D 2G lt 1066MT s Read and Write TLA Channel Grouping DatHi Signal Name RD_B_DQ63 RD_B_DQ62 RD_B_DQ61 RD_B_DQ60 RD_B_DQ59 RD_B_DQ58 RD_B_DQ57 RD_B_DQ56 RD_B_DQ55 RD_B_DQ54 RD_B_DQ53 RD_B_DQ52 RD_B_DQ51 RD_B_DQ50 RD_B_DQ49 RD_B_DQ48 RD_B_DQ47 RD_B_DQ46 RD_B_DQ45 RD_B_DQ44 RD_B_DQ43 RD_B_DQ42 RD_B_DQ41 RD_B_DQ40 RD_B_DQ39 RD_B_DQ38
63. ive Latency CAS Write Latency Registered DM Signal Use write Masks Figure 17 Disassembly Properties There are several select fields available in this window some of which must be set correctly for the post processing software to work properly These fields and their selections are Burst Length permits setting the burst length for Read and Write data Valid choices are 4 the default 8 and 4 8 On the Fly This value must be set properly for all valid Read and Write data to be displayed CAS Latency CL sets the delay in clock cycles from the Read command until the first piece of valid Read data is available This value must be set properly for all valid Read Data to be displayed Valid choices are 5 default 6 7 8 9 or 10 cycles CAS Additive Latency additional latency for data cycles This value must also be set properly for valid Read Data to be displayed Valid choices are 0 default CL 1 or CL 2 cycles CAS Write Latency number of clock cycles from Write command to the first Write Data This value must be set properly for all valid Write Data to be displayed Valid choices are 5 default 6 7 or 8 cycles Registered must be set to reflect whether or not Registered DDR memory is used Default is No When set to Yes an additional clock cycle delay is added to CAS Latency and to valid Read and Write Data tagging DDR3THIN MN XXX 64 Doc Rev 1 11 DM Signal Use
64. lot are active equivalent to Dual Rank DIMM C B 3210 0L0L4L S0 S1 S2 and S3 in the Interposer slot are active equivalent to a Quad Rank DIMM 0 A 0 Oririr 50 in the slot between the Interposer and the memory controller and 50 in the Interposer slot are active equivalent to two Single Rank DIMMs C 0 10 Orir2r 550 S0 and S1 are active equivalent to Single Rank DIMM and one Dual Rank DIMM C 10 0 Or2rlr bS1 550 and 50 are active equivalent to a Dual Rank DIMM and a Single Rank DIMM C 10 A 10 Or2r2r bS1 bS0 S1 and 0 are active equivalent to two Dual Rank DIMMs 0 B 0 0 Iririr cS0 15 the slot nearest the memory control if three slot channel 550 is the slot in the middle of a three slot channel and 50 in the Interposer slot are active equivalent to three Single Rank DIMMs C 0 B 0 A 10 Irir2r 50 bS0 S0 and S1 are active equivalent to two Single Rank DIMMs and one Dual Rank DIMM C 0 8 10 A 0 cS0 bS1 bS0 and 50 are active equivalent to a Dual Rank DIMM and two Single Rank DIMMs C 0 10 A 10 1r2r2r cS0 bS1 bS0 51 and SO are active equivalent to a Single Rank DIMM and two Dual Rank DIMMs 10 B 0 A 0 2rlrlr cS1 50 bS0 and SOZ are active equivalent to two Single Rank DIMMs and a dual rank DIMM 10 0 10 2rlr2r cS1 cSOZ 550 5
65. ment carefully before opening the CD case Rights in the software are offered only on the condition that the customer agrees to all terms and conditions of the license agreement Opening the CD case indicates your acceptance of these terms and conditions If you do not agree to the licensing agreement you may return the unopened package for a full refund License Agreement In return for payment for this product Nexus Technology grants the Customer a SINGLE user LICENSE in the software subject to the following Use of the Software Customer may use the software on only one Tektronix mainframe logic analysis system at any given time Customer may make copies or adaptations of the software see Copies and Adaptations below for more information Customer may NOT reverse assemble or decompile the software Copies and Adaptations Are allowed for archival purpose only When copying for adaptation is an essential step in the use of the software with the logic analyzer and or logic analysis mainframe so long as the copies and adaptations are used in no other manner Customer has no right to copy software unless it acquires an appropriate license to reproduce from Nexus Technology Customer agrees that it does not have any title or ownership of the software other than the physical media Ownership Customer acknowledges and agrees that the software is copyrighted and protected under the copyright laws Transfer of the right of o
66. nal Name RD A DQ3I RD A DQ30 RD A DQ29 RD A DQ28 RD A DQ27 RD A DQ26 RD A DQ25 RD A DQ24 RD A DQ23 RD A DQ22 RD A 021 RD A DQ20 RD A DQI9 RD A DQIS8 RD A 0017 RD A 0016 RD A 0015 RD A 0014 RD A DQI3 RD A DQI2 RD A 0011 RD A DQIO RD A DQ9 RD RD A DQ7 RD A DQ6 RD A 005 RD A 004 RD A DQ3 RD A DQ2 RD A RD A DQO Table 3 B DDR3D lt 1066 5 Read and Write TLA Channel Grouping 1 All signals on this page are required for accurate post processing of acquired data 2 The M in front of a TLA channel denotes the Master card of the merged set 3 The S in front of a TLA channel denotes Slave card 1 of the merged set DatHi Signal Name RD_B_DQ63 RD_B_DQ62 RD B DQ61 RD B DQ60 RD B DQ59 RD 2058 RD 2057 RD 0056 RD 2055 RD 2054 RD 0053 RD 0052 RD DQSI RD B DQ50 RD B DQ49 RD B DQ48 RD B DQ47 RD B DQ46 RD B DQ45 RD B DQ44 RD B DQ43 RD B DQ42 RD B DQ41 RD B DQ40 RD B DQ39 RD B DQ38 RD B DQ37 RD B DQ36 RD B DQ35 RD B DQ34 RD B DQ33 RD B DQ22 S A2 0 l S 2 1 1 S 2 571 S S 2 2 1 S 2 371 A2 7 l S 3 071 S A32 l S 3 371 S 7 S 1 571 S A3 1 l S 3 471 S AL 7 S AL6 l S 14 S 11 S A0 7 l 0 671 S AL3 l S 12 0 571 0 471 S 0 371 S A02 l M C2 141 2 471 S 0 171 8 0 071 C2 6 1 2 7 1 Signal Name RD 0031 RD
67. nal data groups DataByte7 0 added to the same Waveform display shown in Figure 12 Note that it is now possible to determine the skew between data groups and place these values into the Setup amp Hold Window settings in the TLA Setup window see Figure 15 Refer to Appendix F Data Group Byte Strobe Cross Reference for details on which 8 bit groups make up a 32 bit group When setting the individual Setup amp Hold values it is suggested that the settings for the associated 32 bit group RdA DatHi RdA DatLo RdB DatHi RdB DatLo WrA DatHi WrA DatLo WrB DatHi WrB DatLo be reset to Support Package Default This will prevent the TLA from displaying warnings that conflicting values have been set for the data bits The Support Package Default Setup amp Hold values are the same as the TLA default values 117ps 117ps It will also be necessary to program the Setup amp Hold values for all of the 8 bit groups in the affected 32 bit group If conflicting Setup amp Hold points are programmed then the values will have exclamation marks beside them to denote the conflict File Edt view Data System Tools Window Help 2 sample Point Import Tool Protocol Designer Verify lt 8 AutoDeskew setup trigger Waveform 25 Listing T8 kl Status Idle X view Activity Value Q Q Time Div 500
68. nd will not have a MagniVu display value 3 7 Display Groups not in Tables 1 2 or 3 There are several groups in the List window that are not documented in the tables as these groups are used only by the post processing display software To ensure correct data display these groups must not be modified These groups e DataHi e DataLo ChekBits Command e DataMasks e MRSAddr 4 0 CLOCK SELECTION 41 B DDR3D 2D Clocking Selections There are two clocking option fields available when using the B DDR3D 2D support package These select fields permit the user to setup the TLA acquisition as follows SDRAM Clocking Permits selecting the Clocking Mode to be used to acquire DDR3 data It is important to note that the selection chosen will force unused Chip Selects and 1 into inactive states The field choices are S07 Every Rising Edge default Clocks data using every rising edge of DDR Clock 0 Forces CKEI low and S1 3 high No Idle Cycle filtering is done S04 amp S12 Every Rising Edge Clocks data using every rising edge of DDR Clock 0 Forces S2 3 high No Idle Cycle filtering is done 50 34 Every Rising Edge Clocks data using every rising edge of DDR Clock 0 No Idle Cycle filtering is done S07 Total L 5 utilizes Selective Clocking to reduce acquisition of Idle bus states Forces CKE1 low and S1 3 high 50 amp S1 Total L lt 5 utilizes Selective Clocking to reduce acquisi
69. ng the rising edge of the DDR clock A Data information is earlier older data than the information stored in Data Different Sample Points must be set for each of the four 32 bit Data groups and if necessary sample points can be set for any of the 8 bit data groups or for individual data bits Clock 1 1 1 Read 1 1 1 gt lt RdA S amp H i RdB S amp H Write WrA S amp H WrB S amp H APPENDIX B Considerations NEX DDR3INTR THIN Bus Loading It must be noted that the NEX DDR3INTR THIN Interposer is designed to minimal effect on the user s circuit The acquired signals are sampled at top edge connector and then passed through isolation resistors to the probe There will be an effective 600 ohm load on all probed signals The DDR3D support will use two Interposers and will double probe all signal Thus the DC load will be near 300 ohms The DDR3 Interposer has been tested via detailed simulations and by actual in circuit testing B 2 DIMM connector location for best quality signal capture An interposer is subject to reflected noise and the quality of the acquisitions should improve if the Interposer is in the furthest slot away from the memory controller If the memory channel contains two DIMM slots and only one will be used the slot used must be the furthest away from the memory controller 3 TLA7BB4 Module to module skew At print time Tektronix ha
70. ni u fi 25ps Magnu Trigger Pos PowerTrigger jdx3 V IL EasyTrigger Jat P State 1 Store MRS cycle to 508 or S1 Run H If Group Control MRS MODE REGISTER SET SO Or Group Control MRS MODE REGISTER SET 51 Then Store Sample For Help press F1 Figure 20 B_DDR3D_2D MRS Trigger In the trigger example a Storage condition has been created so that only MRS cycles will be stored In testing multiple MRS cycles were seen during the boot process and the example triggers shown will ensure that all of the MRS cycles will be acquired an example of which is shown in Figure 20 The last acquired MRS cycle will reflect the settings used in the DDR target in this case a CAS latency of 2 cycles with a Burst length of 8 EE DDR2M 3A MRS ma AAI I Seach z C2 50 Delta Time 1 297 Lock Delta Time ICIXI 297 414 375 357 826 750 Figure 21 MRS Cycle Acquisition Disassembly 7 4 Clock Capture quality The clock captured by the logic analyzer may exhibit ringing If this ringing is such that a clock reference voltage can not be determined it is suggested that the capacitor on the DIMM across DDR3THIN MN XXX 71 Doc Rev 1 11 the differential pair by removed The added capacitance of the logic analyzer compensates for this missing capacitor 7 5 Thresholds Analog waveforms and their associated thresholds viewed using
71. not have a MagniVu display value WrA DatHi Hex Table 2 B DDR3D 2G lt 1066MT s Read and Write TLA Channel Grouping cont d Notes 1 All signals on this page are required for accurate post processing of acquired data Signal Name WR_A_DQ63 WR A DQ62 WR A DQ61 WR DQ60 WR A DQS9 WR A DQS8 WR A 0057 WR A DQS6 WR A DQSS WR A 054 WR DQS3 WR A 052 WR A DQSI WR A DQSO WR A 049 WR A DQ48 WR A DQ47 WR A DQ46 WR DQ45 WR A DQ44 WR A DQ43 WR A DQ42 WR A 041 WR 040 WR DQ39 WR A DQ38 WR A DQ37 WR A DQ36 WR A DQ35 WR A DQ34 WR A DQ33 WR A DQ32 DDR3 TLA Pin Input WrA DatLo Hex Signal Name WR A DQ31 WR A DQ30 WR A DQ29 WR A DQ28 WR A DQ27 WR A DQ26 WR A DQ25 WR A DQ24 WR A DQ23 WR A 022 WR 021 WR A DQ20 WR A DQI9 WR A 0018 WR A 0017 WR A 016 WR A 0015 WR A 0014 WR A DQI3 WR A DQI2 WR A WR A 0010 WR A DQ9 WR A WR A DQ7 WR A DQ6 WR A DQS WR A DQ4 WR A DQ3 WR A DQ2 WR A WR A DQO DDR3 TLA Pin 2 The S in front of a TLA channel denotes the Slave card of the merged set Input WrB_DatHi Hex Signal Name WR B DQ63 WR B DQ62 WR B DQ61 WR B DQ60 WR B 0059 WR B DQS8 WR 0057 WR 0056 WR 0055 WR 0054 WR 0053 WR 0052 WR 0051 WR 0050 WR 0049 WR B 01048 WR B DQ47 WR B DQ46 WR B DQ45 WR B DQ44 WR B DQ43 WR B DQ42 WR 0041 WR 01040 WR 0039 WR DQ38
72. nt d Notes 1 denotes low true signal The M in front of a TLA channel denotes the Master card of the merged set The 57 in front of a TLA channel denotes Slave card 1 of the merged set The 527 in front of a TLA channel denotes Slave card 2 of the merged set Signals in these groups are acquired using the TLA s demux capability and will not have s MagniVu display value Notes Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin Input Name Name Pin Input Control CKEI BA2 SYM CKEO BAI 53 52 15 51 14 50 13 2 12 C BAI 11 A10 AP 15 9 14 8 13 AT 12 C 6 A10 AP 5 RAS A4 CAS A3 WE A2 Strobes Al HEX AO MISCI Placeholder M A3 5 MISCO Placeholder M A3 4 DDRCKO0 184 185 M 1 4 Ungrouped 2058 DM8 ERR_OUT Unprobed All DQSx RESET DDRCKI1 63 64 TEST 5 1 237 SDA 238 ODTI 5 0 117 PAR IN SCL 118 Table 3 B DDR3D TLA Channel Grouping cont d denotes low true signal These signals are required for accurate acquisition and post processing of acquired data The M in front of a TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The 527 in front of a TLA channel denotes Slave card 2 of the merged set Signals in these groups are acquired using the TLA s demux capability a
73. nt of a TLA channel denotes the Slave card of the merged pair 2 The M in front of a TLA channel denotes the Master card of the merged pair Signal TLA Group Signal TLA Name Name Input Name Name Input DataByte 2063 S_A2 0 DataByte DQ31 7 3 DQ62 S_A2 1 DQ30 2061 S_A2 5 DQ29 5 CKO 2028 2059 5 A22 2027 2058 5 2 3 2026 2057 5 27 2025 2056 S A3 0 DQ24 DataByte DataByte DQ23 6 2 DQ22 DQ21 DQ20 DQ19 DQ18 2017 2016 DataByte DataByte 2015 5 1 2014 2013 2012 2011 2010 209 DataByte DataByte DQ7 4 0 DQ6 DQ5 DQ4 DQ3 DQ2 1 DQO Table 4 B DDR3D 2D 2G TLA MagniVu Channel Grouping cont d Notes 1 The S in front of a TLA channel denotes the Slave card of the merged pair 2 The M in front of a TLA channel denotes the Master card of the merged pair Signal TLA Group Signal TLA Name Name Input Name Name Input CheckBit DataMasks DM7 S_A2 4 5 5 6 S 1 0 2 0 0 2 S CK3 S E3 5 S E2 6 Strobes Address M A3 0 BAI M C3 7 M 6 15 14 2 5 13 M_CK3 Al2 BC 2 4 2 6 Control 3 2 9 2 1 CKEO M A3 8 2 0 53 2 5 7 M 2 3 528 3 0 6 0 2 51 3 4 5 M 2 2 50 3 3 4 0 5 2 A3 0 0 BAI C3 7 2 01 0 C1 6 1 M 15 0 5 14 2 5 Orphans PAR IN M
74. nts to ensure that data is acquired at the proper point in the transaction Since valid DDR3 Read data is straddled by the Strobes see Figure 4 the Setup amp Hold sample point must be set for the valid data that occurs closest to the clock edge The appropriate clock edge for Reads is determined by adding the Additive Latency value to the CAS Latency value and adding one if Registered memory RDIMMs are being used resulting in the total number of clock cycles from the Read Command to the first valid Read Data If these values are not known the technique described in Section 7 3 can be used to determine the necessary values with the exception of whether or not the memory is RDIMM or UDIMM In Figure 4 the total Read latency is 6 cycles The B DDR3D XX supports acquire two samples of valid Read data on each rising edge of the DDR3 clock So to acquire both pieces of data the RdA_DatHi Lo data groups must have their sample point set to that shown by Sample Pt 1 in the Figure and DatHi Lo data groups must have their sample point set to that shown by Sample Pt 2 File Edit view Data System Tools Window Help m x 74 sample Point Import Tool Protocol Designer BE iverify SH AutoDeskew i setup trigger MY waveform fon Listing gt Idle RB amp X iw Magivu Activity OF value Time Div 1 5 e H
75. ock edge to the start of valid Write data In this example the data leads the clock edge by approximately 740ps meaning that a suitable Setup amp Hold value for the WrA DatHi capture group would be 742ps 508ps Note that the Data Lo group is valid somewhat later than the Data Hi group with its valid time starting at approximately 430ps prior to the clock edge so the Setup amp Hold sample point for the WrA DatLo capture group would be set to 430ps 195ps DDR3THIN MN XXX 58 Doc Rev 1 11 Fie Edit View Data System Tools Window sample Point Import Tool Protocol Designer El iverify lt 8 AutoDeskew trigger waveform 3 Listing gt Tek ICI Idle 9 2 E Activity OF value Q Q Time Div 500 Search EI j Cursor 1 tog Cursor 2 v 7400 2 Waveform Ons 43 260ns 14280ns 15 260 16 2605 1 47260ns 18 260ns 19 260ns 20 260ns 21260ns gnu Ep miyu 499959 100000 JagniVu Vu SOF RASH lt Vu CASE WEF Strobes 1FF 000 000 000 OFF 000 B pvu Data Hi AAAAAAAA ssssssss 00000000 55555555 90000000 Gua t B miu Data 10 55555
76. ode is disabled when the SDRAM Clocking choice is set to a Every Rising Edge selection 4 2 B DDR3D 2G Clocking Selections There is one clocking option field available when using the B DDR3D 2G support package These select fields permit the user to setup the TLA acquisition as follows Active Chip Selects Permits selecting which of 8 possible Chip Selects are active on the target The rising edge of the DDR Clock is always used to acquire data How the display software interprets which Chip Selects are active will be based on this field setting With 8 possible Chip Selects and 6 Clock Enable signals it is possible to support data acquisition from a 3 slot channel at 800 See section 3 6 for channel configuration This support only allows one quad rank support in slot A the interposer slot or most combinations of single and dual rank DIMMs in the three slots The slot is the DIMM slot between the Interposer and the memory controller The slot is the slot nearest the memory controller in a three slot system The field choices shown correspond to the Chip Select number defined in the channel map and are as follows Chip Select s Equivalent Memory DIMM configuration C B A 0 OrOrlr default Only S0 in the Interposer slot is active all other Chip Selects will be forced inactive high by the support package Equivalent to one Single Rank DIMM A 10 OrOr2r 50 S1 in the Interposer s
77. ort place the B DDR3D XX Install CD in the CD drive of the TLA or the PC being used to control the TLA Using Windows Explorer select the CD navigate to the support software folder select the folder of the support to be installed DDR3D 2D B DDR3D 2G or B DDR3D and then run the MSI file within the folder The selected software will be installed on the TL A s hard disk To load the support into the TLA first select the desired Logic Analyzer module different supports require different module counts in the Setup window select Load Support Package from the File pull down then choose the software package name you are want to load and click on Okay Note that this support requires two or more merged modules and that the TLA acquisition cards must be configured properly for the software to load 3 0 CONNECTING to the NEX DDR3INTR THIN INTERPOSER 3 1 General Care should be taken to support the weight of the acquisition probes so that the Logic Analyzer Interposer board and or target socket are not damaged 3 2 B DDR3D 2D Support To acquire DDR3 Read and Write data at speeds up to 1066MT s requires two merged TLA7BB4 136 channel with 1 4G state option acquisition cards and the use of the B DDR3D 2D support software The Master card will be in the lower numbered of the two cards Slave card 1 is in the adjacent high numbered slots The logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using 1 NEX P
78. problem Please do not send a text listing alone as that does not contain enough data for analysis To prevent corruption during the mailing process it is strongly suggested that the Setup be zipped before transmission DDR3THIN MN XXX 91 1 11
79. r the user to define a given cycle to be triggered on Rather than trying to remember what signals make up the Control group the Symbol Table has the appropriate bits already set for the given cycle It is important to note that changing the channel definition of the Control group can result in incorrect symbol information being displayed Definition Symbol 5555 1110 for 50 5555 IX 1101 for S1 ssss x1 1011 for S2 ssss IX 0111 for S3 x in Definition Don t Care MRS Sx MODE REGISTER SET SSSS XXX xxx 000 REF Sx REFRESH SSSS xxx 001 Sx SINGLE BANK PRECHARGE cc ssss xxx x0010 PREA Sx PRECHARGE ALL BANKS ACT Sx ACTIVATE BANK 5555 xxx 1010 SSSS XX01 1 WR Sx WRITE 5855 xxx xxx X0100 WRA Sx WRITE WITH AUTO PRECHARGE RD Sx READ CC SSSS XXX x1100 SSSS 0101 RDA Sx READ WITH AUTO PRECHARGE ssss xxx 1101 NOP Sx NO OPERATION DES DEVICE DESELECT SSSS xxx xx111 SSSS XXXXX ZQCL Sx ZQ CALIBRATION LONG SSSS xxx x1110 20 5 Sx ZQ CALIBRATION SHORT ssss xxx x0110 Table8 B DDR3D 2 Control Symbol Table Signals left to right CKE1 53 S272 S12 50 BA2 BAI BAO A15 A14 A13 A
80. rned to Nexus Technology for warranty service the Buyer shall prepay shipping charges to Nexus Technology and Nexus Technology shall pay shipping charges to return the product to the Buyer However the Buyer shall pay all shipping charges duties and taxes for products returned to Nexus Technology from another country Nexus Technology warrants that its software and hardware designated by Nexus Technology for use with an instrument will execute its programming instructions when properly installed on that instrument Nexus Technology does not warrant that the operation of the hardware or software will be uninterrupted or error free Limitation of Warranty The foregoing warranty shall not apply to defects resulting from improper or inadequate maintenance by the Buyer Buyer supplied software or interfacing unauthorized modification or misuse operation outside of the environmental specifications for the product or improper site preparation or maintenance NO OTHER WARRANTY IS EXPRESSED OR IMPLIED NEXUS TECHNOLOGY SPECIFICALLY DISCLAIMS THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Exclusive Remedies THE REMEDIES PROVIDED HERIN ARE BUYER S SOLE AND EXCLUSIVE REMEDIES NEXUS TECHNOLOGY SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY Software License Agreement IMPORTANT Please read this license agree
81. s requires three merged TLA7BBA 136 channel with 1 46 state option acquisition cards and the use ofthe B DDR3D optional support software The Master card will be in the lower numbered of the three cards Slave card 1 will be in the adjacent high numbered slots Slave card 72 will be in the adjacent low numbered slots This support also requires two NEX DDR3INTR THIN Interposer products The logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using 5 NEX probes and three 3 NEX PRB2X T probes TLA Master Connect the NEX PRB1X T probe head to DDR3 Interposer s LEASH soldered on coax cable that is attached to M C position on the Interposer Connect the NEX PRB2X T A3 2 amp A1 0 probe head to DDR3 Interposer s LEASH that is attached to A3 2 1 0 position on the Interposer Match the label on the end of the NEX PRBI X T 2X T probes with the labels on the front of the Tektronix Logic Analyzer Master module and connect TLA Slavel Connect the NEX PRB2X T A3 2 amp A1 0 probe head to DDR3 Interposer s LEASH that is attached to 5 2 A1 0 position on the Interposer Connect the NEX PRB2X T C3 2 amp E3 2 probe head to DDR3 Interposer s LEASH that is attached to S_C3 2 E3 2 position on the Interposer TLA Slave2 Connect the NEX PRBIX T 3 2 03 2 probe head to DDR3 Interposer s LEASH that is attached to 3 2 1 0 position on th
82. see Tables 1 2 and 3 can be seen in the acquisition card Setup window and contain the data stored in Main Memory which is used for the Listing display Capture data groups not defined in this manual are the groups seen in the TLA s Setup amp Hold dialog box and are the groups used to capture data during each DDR clock cycle The MagniVu and Capture data groups will be referred to in the following explanation on determining and setting the correct sample points to acquire Read and Write data Please contact your local Tektronix representative for a detailed explanation of the different data group areas and what they mean 5 2 MagniVu Signals Because of the design of the Tektronix TLA7BB4 acquisition cards different data groups need to be defined for use within MagniVu Table 4 shows the MagniVu group definitions present in the B DDR3D 2D 2G supports Table 5 shows the MagniVu group definitions present in the B DDR3D support Group Signal TLA Group Signal TLA Name Name Input Name Name Input Data_H DQ63 Data_L DQ31 i 0 2062 2030 2061 2029 2028 2059 2027 2058 2026 2057 2025 2056 2024 2055 2023 2054 2022 2053 2021 2052 2020 2051 2019 0050 2018 2049 2017 2048 2016 2047 2015 2046 2014 2045 2013 2044 2012 2043 2011 2042 2010 2041 DQ9 DQ40 DQ8 DQ39 DQ7 DQ38 DQ6 DQ37 DQ5 DQ36 DQ4 DQ35 DQ3 DQ34 DQ2 DQ33 1 DQ32 DQO Table 4 B DDR3D 2D 2G TLA MagniVu Channel Grouping Notes 1 The S in fro
83. te TLA Channel Grouping 25 Table 3 B DDR3D lt 1066MT s Read and Write TLA Channel Grouping 31 Table 4 B DDR3D 2D 2G TLA MagniVu Channel Grouping eee 45 Table 5 B DDR3D TLA MagniVu Channel Grouping 48 Table 6 B DDR3D 2 Mnemonics Definition eene enne tn enne ennn 66 Table 7 B DDR3D 2G Mnemonics 2002022 100000000000 67 Table 8 B DDR3D 20 Control Symbol 2 69 Table 9 B DDR3D 2G Control Symbol 222 70 DDR3THIN MN XXX 8 Doc Rev 1 11 1 0 OVERVIEW 1 1 General Information DDR3 Interposer Products are designed for ease of use Interposers extra signal trace length also an extra connector that might affect the quality of the system operation in some systems e This Product is designed for capture of 1066MT s or slower and may only be used with the Tektronix TLA7BB4 acquisition modules This product requires the use of the new NEX PRB1X T PRB2X T Low Profile Distributed probes available from Nexus Tektronix P68xx or P69xx probes can not be used This Interposer has been designed to provide a quick and easy connection to interface to a Tektronix TLA7BB4 Logic Analyzer acquisition cards to a 240 pin DDR3 Double Data Rate 3 bus Contact
84. tion of Idle bus states Forces 2 3 high S0 3 Total L lt 5 utilizes Selective Clocking to reduce acquisition of Idle bus states S0 Total L lt 6 50 amp S1 Total L lt 6 S0 3 Total L lt 6 S0 Total L lt 25 0 amp S1 Total L lt 25 S0 3 Total L lt 25 The above selections reduce the number of Idle cycles stored by the acquisition card to provide optimum use of the acquisition memory Data is stored whenever RAS or CAS is asserted low along with a valid Chip Select After every assertion of CAS paired with a valid Chip Select samples are taken during the next X DDR Clock cycles to ensure that all valid memory cycles have been acquired The acquisition then pauses and waits for the next Command If CAS and a Chip Select are asserted during these clock cycles the count is reset The X clock cycle value is determined by adding the maximum Burst Length of 8 clock cycles to the selected maximum Read Latency So for a selected Total Latency of lt 5 cycles the support software will store total of 13 clock cycles worth of data after the Read or Write Command appears on the bus Refresh Cycles Permits choosing whether Refresh Cycles will be stored or not The field choices are Acquire default Refresh Cycles will be stored Do Not Acquire This mode will reduce the number of Refresh cycles stored by the acquisition card to provide optimum use of the acquisition memory NOTE This m
85. up Byte Strobe Cross Reference 32 bit Data Group 8 bit Data Group Strobe Data Bits RdADatHi RdADatB7 2057 653 62 61 60 59 58 57 56 RdADatB6 DQS6 55 54 53 52 51 50 49 48 RdADatB5 2055 47 46 45 44 43 42 41 40 RdADatB4 2054 39 38 37 36 35 34 33 32 RdADatLo RdADatB3 2053 31 30 29 28 27 26 25 24 RdADatB2 DQS2 23 22 21 20 19 18 17 16 RdADatB1 2051 15 14 13 12 11 10 9 8 RdADatB0 DQSO 17 6 5 4 3 2 1 0 WrADatHi WrADatB7 2057 653 62 61 60 59 58 57 56 WrADatB6 DQS6 55 54 53 52 51 50 49 48 WrADatB5 2055 147 46 45 44 43 42 41 40 WrADatB4 2054 39 38 37 36 35 34 33 32 WrADatLo WrADatB3 2053 31 30 29 28 27 26 25 24 WrADatB2 DQS2 23 22 21 20 19 18 17 16 WrADatBl 2051 15 14 13 12 11 10 9 8 WrADatBO DQSO 17 6 5 4 3 2 1 0 RdBDatHi RdBDatB7 653 62 61 60 59 58 57 56 RdBDatB6 DQS6 55 54 53 52 51 50 49 48 RdBDatB5 2055 47 46 45 44 43 42 41 40 RdBDatB4 2054 39 38 37 36 35 34 33 32 RdBDatLo RdBDatB3 2053 31 30 29 28 27 26 25 24 RdBDatB2 DQS2 23 22 21 20 19 18 17 16 RdBDatB1 2051 15 14 13 12 11 10 9 8 RdBDatBO 2050 17 6 5 4 3 2 1 0 WrBDatHi WrBDatB7 2057 653 62 61 60 59 58 57 56 WrBDatB6 DQS6 55 54 53 52 51 50 49 48 WrBDatB5 DQS5 47 46 45 44 43 42 41 40 WrBDatB4 2054 39 38 37 36 35 34 33 32 WrBDatLo WrBDatB3 2053 31 30 29 28 27 26 25 24 WrBDatB2 DQS2 23 22 21 20 19 18 17 16 WrBDatB1 2051 15 14 13 12 11 10 9 8 WrBDatB0 DQSO 17 6 5 4 3 2 1 0 B_DDR3D_XX Groups Bytes Strobes Cross Reference APPENDIX I
86. up would be 2 52ns 2 754ns DDR3THIN MN XXX 56 Doc Rev 1 11 A RD File Edit view Data System Tools Window Help 54 Sample Point Import Tool Protocol Designer iverify SE AutoDeskew A setup trigger 11 Waveform 1292 Listing Run Idle gt amp X iview 1 Activity OF value ig Time Div 500 D Seach At Cursor 2 gt 237ns Waveform 10 lt 14 4105 15 410 15 16 410 15 47 410 15 18 410 15 19 4105 20 410ns 21 410ns 22 410ns 2 3 418 ns H 22 832 ns QUIDDAM y B miu Actress 00000 Vu SOF RASH Vu CAS WEF B Strobes 000 B pvu Data Hi 00000000 00000000 00000000 B yVu Data to EFAFBAFF EFABBAFF 00000000 FFFFFFFF 00000000 00000000 B Vu DataByte7 00 FF 00 00 lt Help press F1 Figure 8 Measuring B DDR3D XX RdB_DatHi Lo Read Data Setup amp Hold Now the sample point positions must be set for the RdA_DatHi RdA DatLo RdB DatHi and RdB DatLo capture groups in the Setup window see Figure 9 This window is found by going to the LA Card s Setup window then clicking on the More button to the right of the clock select field The TLA acquisition cards require a valid data window of approximately 300ps and this window can be placed to begin from 15 098ns prior to the clock edge to 7 383ns after the edge in roughly
87. wnership shall only be done with the consent of Nexus Technology Sublicensing and Distribution Customer may not sublicense the software or distribute copies of the software to the public in physical media or by electronic means or any other means without the prior written consent of Nexus Technology Compliance with WEEE and RoHS Directives This product is subject to European Union regulations on Waste Electrical and Electronics Equipment Return to Nexus Technology for recycle at end of life Costs associated with the return to Nexus Technology are the responsibility of the sender TABLE CONTENTS TO OVERVIEW tae ees eda hada Laas 9 LT General Information _ IRR Hn QE UAR 9 1 2 Software Package description e 9 Ey sizeTeg ired een eo nsn aquqa Qua aD D Monit Gam uwa u pu auqa says 11 2 0 SOFTWARE eee 11 30 CONNECTING to the NEX DDR3INTR THIN INTERPOSER 12 12 3 2 B DDR3D 2D Support 12 3 3 B DDR3D 2G Support EAE N EREE AERA 12 34 DDR3D SA SUDDOFRL 13 35 9 short EEASH probes mesen dst mb ete O 15 3 5 1 Samtec connector on the LEASH probe pins 1 1 16 3 5 2 LEASH probe to NEX PRB1X

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