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National Instruments 6024E Switch User Manual

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1. STARTSCAN CONVERT A Scan Counter Figure 4 17 Typical Posttriggered Acquisition 4 32 ni com Chapter 4 Signal Connections TRIG1 TRIG2 STARTSCAN CONVERT Scan Counter Don t Care 0 As til 2 1 i 2 i i 2 0 Figure 4 18 Typical Pretriggered Acquisition SCANCLK Signal SCANCLK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external analog input multiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 19 shows the timing for the SCANCLK signal CONVERT i ty SCANCLK i lt i ti i ta 50 to 100 ns tw 400 to 500 ns Figure 4 19 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of the EXTSTROBE signal A 10 us and a 1 2 us clock are av
2. 5 ppm C max Long term stability eee 15 ppm 1 000 h Power Requirement 5 VDC 45 A 0 7A Maya Note Excludes power consumed through V available at the I O connector Power available at I O connector 4 65 to 5 25 VDC at1 A Physical Dimensions not including connectors POL devices vi css sevesicscoaees teseeasnavstvans 17 5 by 10 6 cm 6 9 by 4 2 in PXI device cocinera 16 0 by 10 0 cm 6 3 by 3 9 in National Instruments Corporation A 9 6023E 6024E 6025E User Manual Appendix A Specifications for PCI and PXI Buses T O connector 6023E 6024E siseses 68 pin male SCSI II type 1010020 E roa reer 100 pin female 0 05D type Operating Environment Ambient temperature 0 0 0 0 eee 0 to 55 C Relative humidity oer 10 to 90 noncondensing PXI 6025E only Functional SHOCK issis MIL T 28800 E Class 3 per Section 4 5 5 4 1 Half sine shock pulse 11 ms duration 30 g peak 30 shocks per face Operational random vibration 5 to 500 Hz 0 31 Sims 3 axes Storage Environment Ambient temperature 0 0 0 eee 20 to 70 C Relative humidity ooooccnnnicnnonnncnconcnnnnonen 5 to 95 noncondensing PXI 6025E only Non operational random vibration 5 to 500 Hz 2 5 Sms 3 axes 3 Note Random vibration profiles for the PXI 6025E were developed in accordance with MIL T 28800E and MIL STD 810E Method 514 Test levels exceed those recommended in MIL STD 810E for Cat
3. A 6 T 10 V ties 0 1 Q max 5 mA max Short circuit to ground 200 mV ee 1 1V 2 0 ms we 2 2 V 4 2 us 10 us to 0 5 LSB accuracy 10 V us 200 UV ms DC to 1 MHz 45 mV 2 0 us 50 uV C 25 ppm C ni com Digital 1 0 Appendix A Specifications for PCI and PXI Buses Number of channels 025 iii in a S 32 input output 6023E and 6024E oes 8 input output Compatibility eseese TTL CMOS DIO lt 0 7 gt Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vin 0 V 320 uA Input high current Vin 5 V 10 uA Output low voltage Io 24 mA 0 4 V Output high voltage Ion 13 mA 4 35 V Power 0N statenes Input High Z 50 KQ pull up to 5 VDC Data transfers iia iia Programmed I O PA lt 0 7 gt PB lt 0 7 gt PC lt 0 7 gt 6025E only Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2 2 V 5V Input low current V 0 V 100 KQ pull up 75 HA Input high current Vin 5 V 100 KQ pull up 10 uA Output low voltage Ip 2 5 mA 0 4 V Output high voltage Ion 2 5 mA 3 7 V National Instruments Corporation A 7 6023E 6024E 6025E User Manual Appendix A Specifications for PCI and PXI Buses Handshaking oooocnoccnococonccnnnananncnnnannnnnano 2 wire Power on state PASO dt Input High Z 100 k
4. 45 46 47 48 49 50 1 Not available on the 6023E AIGND ACH8 ACH9 ACH10 ACH11 ACH12 ACH13 ACH14 ACH15 DACOOUT RESERVED DGND DIO4 DIO5 DIO6 DIO7 5 V SCANCLK PFIO TRIG1 PFI2 CONVERT PFI4 GPCTR1_GATE PFI5 UPDATE PFI7 STARTSCAN PFI9 GPCTRO_GATE FREQ_OUT Figure B 3 50 Pin E Series Connector Pin Assignments B 5 6023E 6024E 6025E User Manual Appendix B Custom Cabling and Optional Connectors 6023E 6024E 6025E User Manual Figure B 4 shows the pin assignments for the 50 pin extended digital input connector PC7 PC6 PC5 PC4 PC3 PC2 PC1 PCO PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO 5 V O Nao o 11 13 19 21 31 41 O AJN 8 10 12 14 15 17 16 18 20 22 24 23 25 27 26 28 30 29 32 33 35 37 39 42 43 45 47 34 36 38 40 44 46 48 50 49 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Figure B 4 50 Pin Extended Digital Input Connector Pin Assignments B 6 ni com Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of your device General Information What is the DAQ STC The DAQ STC is the system timing control application specific integrated ci
5. 65 Q o 64 N co 63 XV 00 62 N Y 61 mM O 60 m al 59 Nm A 58 N wo 57 N N 56 N 55 DS o 54 co 53 00 52 N 51 es O 50 al 49 A 48 ies 47 M 46 45 o 44 o 43 42 41 40 39 38 37 36 PO wo BR MO OM jo 35 PC7 GND GND PC4 GND GND PC1 GND GND PB6 GND GND PB3 PB2 GND GND PA7 GND GND PA4 GND GND PA1 GND GND N C N C N C N C N C N C N C N C N C Figure B 2 68 Pin Extended Digital Input Connector Pin Assignments B 4 ni com National Instruments Corporation Appendix B Custom Cabling and Optional Connectors Figure B 3 shows the pin assignments for the 50 pin E Series connector AIGND ACHO ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 AISENSE DAC10UT1 AOGND DIOO DIO1 DIO2 DIO3 DGND 5 V EXTSTROBE PFM TRIG2 PFI3 GPCTR1_SOURCE GPCTR1_OUT PFI6 WFTRIG PFI8 GPCTRO_SOURCE GPCTRO_OUT Na a Go MD AJN 9 o 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
6. GPCTR1_OUT Toggle Output on TC Figure 4 40 GPCTR1_OUT Signal Timing GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I O connector General purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and National Instruments Corporation 4 47 6023E 6024E 6025E User Manual Chapter 4 Signal Connections leave the DIO7 pin free for general use Figure 4 41 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your device 4 tsc Pit tsp A tsp V i i i h SOURCE ONO XN V IL gt tgsu t gt ton t V i GATE IH X V i i IL lt tgw i 4 tout O Vou UT V L OL Source Clock Period to 50 ns minimum Source Pulse Width tsp 23 ns minimum Gate Setup Time tgsu 10 ns minimum Gate Hold Time toh Ons minimum Gate Pulse Width tw 10 ns minimum Output Delay Time tout 80 ns maximum Figure 4 41 GPCTR Timing Summary The GATE and OUT signal transitions shown in Figure 4 41 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of
7. Figure 4 4 summarizes the recommended input configuration for both types of signal sources National Instruments Corporation 4 11 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Signal Source Type Grounded Signal Source Floating Signal Source Not Connected to Building Ground Examples Examples e Ungrounded Thermocouples Plug in instruments with e Signal conditioning with isolated outputs nonisolated outputs e Battery devices Differential DIFF See text for information on bias resistors NOT RECOMMENDED Single Ended Ground Referenced RSE Ground loop losses Vg are added to measured signal Single Ended Nonreferenced AIGND See text for information on bias resistors Figure 4 4 Summary of Analog Input Connections 6023E 6024E 6025E User Manual 4 12 ni com Chapter 4 Signal Connections Differential Connection Considerations DIFF Input Configuration A DIFF connection is one in which the analog input signal has its own reference signal or signal return path These connections are available when the selected channel is configured in DIFF input mode The input signal is connected to the positive input of the PGIA and its reference signal or return is connected to the negative input of the PGIA When you configure a channel for DIFF input each signal uses two multiplexer inputs one for the signal and one for its reference signal Therefore
8. PCI 6025E PXI 6025E DAQCard 6024E 1 2 ni com Chapter 1 Introduction L 6023E 6024E 6025E User Manual Q One of the following software packages and documentation LabVIEW for Windows Measurement Studio VirtualBench Q NI DAQ for PC Compatibles Q Your computer equipped with one of the following PCI bus for a PCI device PXI or CompactPCI chassis and controller for a PXI device Type II PCMCIA slot for a DAQCard device 3 Note Read Chapter 2 Installation and Configuration before installing your device Always install your software before installing your device Software Programming Choices When programming your National Instruments DAQ and SCXI hardware you can use National Instruments application software or another application development environment ADE In either case you use NI DAQ National Instruments Application Software LabVIEW features interactive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of virtual instruments for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to NI DAQ software Measurement Studio which includes LabWindows CVI tools for Visual C and tools for Visual Basic is a development suite that allows you to use ANSI C Visual C and Visual Basic to desi
9. System noise LSB s not including quantization Gain Dither Off Dither On 0 5 to 10 0 1 0 6 100 0 7 0 8 Crosstalk cintas 60 dB DC to 100 kHz Stability Recommended warm up time 15 min Offset temperature coefficient Prepa estatal 15 uv C A ss saeastesesaeis 240 uV C Gain temperature coefficient 20 ppm C Analog Output 6024E and 6025E only Output Characteristics Number of channels ceeceseeeseeseeeee 2 voltage ResolutiON isanne 12 bits 1 in 4 096 Max update rate DMA ito 10 kHz system dependent Internpts cveci detected 1 kHz system dependent Type Ot DA Ce ise winnie Double buffered multiplying 6023E 6024E 6025E User Manual A 4 ni com Appendix A Specifications for PCI and PXI Buses FIFO buffer size cccccccncnnnnnnnnananananonon None Data transfers ooooooncncnnccncnccnnnnnnnnnnnanines DMA interrupts programmed I O DMA MOGES ccccoccocnconcnnncnnconconncnnccnnonncinnos Scatter gather Single transfer demand transfer Accuracy Information Absolute Accuracy Absolute Nominal Range V of Reading Accuracy at Temp Drift Full Scale Positive FS Negative FS 24 Hours 90 Days 1 Year Offset mV Jl C mV 10 10 0 0177 0 0197 0 0219 5 93 0 0005 8 127 Note Temp Drift applies only if ambient is greater than 10 C of previous external calibration Transfer Characteri
10. National Instruments Corporation G 9 Glossary PFI7 start of scan PFI8 general purpose counter 0 source PFI9 general purpose counter 0 gate programmable gain instrumentation amplifier 1 a digital port consisting of multiple I O lines on a DAQ device 2 a serial or parallel interface connector on a PC programmable peripheral interface parts per million pullup multiple pulses the inherent uncertainty in digitizing an analog value due to the finite resolution of the conversion process signal sources with voltage signals that are referenced to a system ground such as the earth or a building ground Also called grounded signal sources the smallest signal increment that can be detected by a measurement system Resolution can be expressed in bits in proportions or in percent of full scale For example a system has 12 bit resolution one part in 4 096 resolution and 0 0244 of full scale a flat cable in which the conductors are side by side the difference in time between the 10 and 90 points of a system s step response root mean square the square root of the average value of the square of the instantaneous signal amplitude a measure of signal amplitude 6023E 6024E 6025E User Manual Glossary RSE RTSI bus sample counter scan scan clock scan rate SCXI SE self calibrating sensor settling time signal conditioning 6023E 6024E 6025E User Manual referenced single ended mode
11. DGND PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT oo E 68 9 de 67 ow N 66 ww 65 ww o 64 N co 63 pe 00 62 N Y 61 Nm O 60 N al 59 mM p 58 N ww 57 N N 56 N k 55 pe o 54 co 53 00 52 N 51 o 50 al 49 ee 48 w 47 N 46 k a 45 o 44 o 43 42 41 40 39 38 37 36 N AJAN oo 35 1 Not available on the 6023E ACHO AIGND ACH9 ACH2 AIGND ACH11 AISENSE ACH12 ACH5 AIGND ACH14 ACH7 AIGND AOGND AOGND DGND DIOO DIO5 DGND DIO2 DIO7 DIO3 SCANCLK EXTSTROBE DGND PFI2 CONVERT PFIS GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT DGND PFI7 STARTSCAN PFI8 GPCTRO_SOURCE DGND DGND Figure B 1 68 Pin E Series Connector Pin Assignments B 3 6023E 6024E 6025E User Manual Appendix B Custom Cabling and Optional Connectors 6023E 6024E 6025E User Manual Figure B 2 shows the pin assignments for the 68 pin extended digital input connector GND PC6 PC5 GND PC3 PC2 GND PCO PB7 GND PB5 PB4 GND GND PB1 PBO GND PA6 PA5 GND PA3 PA2 GND PAO 5 V N C N C N C N C N C N C N C N C N C oo A 68 wo de 67 0 N 66 wo
12. Duration esheets ee Dynamic Characteristics Settling time for full scale step Slew Tate es 6 is ible seit ncionsi masts Midscale transition glitch Magnitude occconccconnconncnonncnnnaninnnns Dira avia idad O National Instruments Corporation A 15 0 01 of output max 0 75 of output max 10V DC 0 1 Q max 5 mA max Short circuit to ground 200 mV wth 5 V 10s we FLSV 1 0s 10 us to 0 5 LSB accuracy 10 V us 200 uVrms DC to 1 MHz 20 mV 2 5 Us 6023E 6024E 6025E User Manual Appendix A Specifications for PCMCIA Bus Digital 1 0 Timing 1 0 6023E 6024E 6025E User Manual Stability Offset temperature coefficient Gain temperature coefficient Number of channels oooonnnnnnnnnnunonnc 50 1H V 9C E25 ppm C 8 input output Compatibility seese TTL CMOS DIO lt 0 7 gt Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vin 0 V 320 uA Input high current Vi 5 V 10 uA Output low voltage Ior 24 mA 0 4 V Output high voltage lon 13 mA 4 35 V Power on StatO occccccccnnnnnncnanananananon Data trans erS ccccccccnoninnnananananinanones Number of channels oooonnnnnnnnununoncc Resolution Counter tiMerS s es Frequency scalers ooooonnccnnncnnn Compatibili
13. FS FS 24 Hours 1 Year mV Single Pt Averaged C mV Single Pt Averaged 10 10 0 0872 0 0914 8 83 3 91 1 042 0 0010 19 012 5 89 1 37 5 3 0 0272 0 0314 4 42 1 95 0 521 0 0005 6 517 2 95 0 686 0 5 0 5 0 0872 0 0914 0 462 0 452 0 052 0 0010 0 972 0 516 0 069 0 05 0 05 0 0872 0 0914 0 066 0 063 0 007 0 0010 0 119 0 073 0 009 Note Accuracies are valid for measurements following an internal E Series calibration Averaged numbers assume dithering and averaging of 100 single channel readings Measurement accuracies are listed for operational temperatures within 1 C of internal calibration temperature and 10 C of external or factory calibration temperature Transfer Characteristics Relative accuracy 0 5 LSB typ dithered 1 5 LSB max undithered DNB hited tected th lek thd al 0 75 LSB typ 0 9 to 1 5 LSB max No missing COdES ooooconoccnocccocanicncnnncnnnnnnno 12 bits guaranteed Offset error Pregain error after calibration 12 uV max Pregain error before calibration 28 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Before calibration 0 eee 2 75 of reading max Gain 1 with gain error adjusted to 0 at gain Lo 0 05 of reading max 6023E 6024E 6025E User Manual A 12 ni com Appendix A Specifications for PC
14. 4 16 Timing I O Connections oooccnncnnoncnnconncnncnnnonncononnnonn nro ncnnonn cnn nro conc rancios 4 31 Figure 4 17 Typical Posttriggered Acquisition ooncnncnicnnnnconnnonconnnnncnn cnn nonccanccnncnnos 4 32 Figure 4 18 Typical Pretriggered Acquisition onoononnnnononinoncononononnnononancnnnonncnncnnccnnos 4 33 Figure 4 19 SCANCLK Signal Timing cooonnocnocnnoncnnnonncononnncnncnnncnnonnnonn cnn ncnnonnnonncnnos 4 33 Figure 4 20 EXTSTROBE Signal Timing ooooonccnncnnnnnoncnnnnnnonnnonncnn cnn n cono nn ccnncrnncnnos 4 34 Figure 4 21 TRIG1 Input Signal Timing ooncnncnnnnnnoninncnnnnnncnncnnncnnonononnnoncnnncnnncnncnnos 4 34 Figure 4 22 TRIG1 Output Signal Timing oooncnnnnninninnconnnoncnnnnncnnnnononncnn nono nnnonncnnss 4 35 Figure 4 23 TRIG2 Input Signal Timing conocnnnonncnnonioncnanonncanonnonnnnnncnnnonncnncnnnonncnnos 4 36 Figure 4 24 TRIG2 Output Signal Timing oconccnncnnnnnonconnnancnnonnonnnnnncnncnnncnncnnncnncnnos 4 36 Figure 4 25 STARTSCAN Input Signal Timing eee eeeeseeneeeeeeeeeees 4 37 Figure 4 26 STARTSCAN Output Signal Timing oononnncnnnnonnnoncononnncnncnnnonnconcnnnonno 4 37 Figure 4 27 CONVERT Input Signal Timing 0 0 cece eeeereeneeeseeneeees 4 38 Figure 4 28 CONVERT Output Signal Timing eee eeeereeeeeeeeneeeees 4 39 Figure 4 29 SISOURCE Signal Timing ccoconnnnocnnonnonnnoncnncnnnonncnnncnncnnnnnn cnn non ncnnconncnnos 4 40 6023E 6024E 6025E User Manual viii ni com Conten
15. 6023E and PCI 6024E Honda 68 position solder cup female connector Honda backshell DAQCard 6024E Honda 68 Position VHDCI National Instruments Corporation B 1 6023E 6024E 6025E User Manual Appendix B Custom Cabling and Optional Connectors 6025E AMP 100 position IDC male connector AMP backshell 0 50 max O D cable AMP backshell 0 55 max O D cable Mating connectors and a backshell kit for making custom 68 pin cables are available from National Instruments Optional Connectors The following table shows the optional connector and cable assembly combinations you can use for each device Device Connector Cable Assembly PCI 6023E 6024E 68 Pin E Series SH6868 R6868 50 Pin E Series SH6850 R6850 DAQCard 6024E 68 Pin E Series SHC68 68 EP RC68 68 50 Pin E Series 68M 50F adapter plus SHC68 68 EP or RC68 68 cable 6025E MIO 16 68 Pin 68 Pin Extended SH1006868 Digital Input 50 Pin E Series 50 Pin Extended RIO05050 Digital Input 6023E 6024E 6025E User Manual B 2 ni com National Instruments Corporation Appendix B Custom Cabling and Optional Connectors Figure B 1 shows the pin assignments for the 68 Pin E Series connector ACH8 ACH1 AIGND ACH10 ACH3 AIGND ACH4 AIGND ACH13 ACH6 AIGND ACH15 DACOOUT DAC10UT RESERVED DIO4 DGND DIO1 DIO6 DGND 5 V DGND DGND PFIO TRIG1 PFI1 TRIG2 DGND 5 V DGND PFI5 UPDATE PFI6 WFTRIG
16. APPLICATION Contents About This Manual Conventions Used in This Manual cesceesccssceceseceseeesseceeeececsaeeeeeeeaeeearessneeeaeeeees xi Related Documentation xii Chapter 1 Introduction Features of the 6023E 6024E and 6025E ooooncnccccconocnononocononocononnnnnanananononcnnnnncnccanocinns 1 1 Using PXI with CompactPCl iecccononi iniiaiee dees sdveaiesaseesdases deaseadepestadaceastdeaeasea 1 2 What You Need to Get Started iinan ainin n ici s la tetona a 1 2 Software Programming CHOICES eee eeeeseeesceseeeeeseceeeeseeseeeaecaeeeseceeesesneeeaeeaees 1 3 National Instruments Application Software ooooonncnocnnonconnnoncononncnncnnncnncrnnonnos 1 3 NI DAQ Driver Software ccccccccsscceesseeesneeeeeseeeessneeeseneecseeeenessesssneeessaeens 1 4 Optional Equipment ssie m etisi a toi dl dicas 1 5 Chapter 2 Installation and Configuration Software Installation nia 2 1 UnpackidS a Rede sees abba dees E T E N REN 2 1 Hardware Installation neenon aa iesirea iriri aeieea iie 2 2 Hardware Configuration iii 2 3 Chapter 3 Hardware Overview Analog INPUT E dada 3 2 Input Modest lid 3 2 Input Range ee E TE E A E A RN E RaT 3 3 MSTA E e A AA 3 4 Multichannel Scanning Considerations ooooonocnnoconnnonnconcnnnnononanonccononnncnnconccnnos 3 5 Analog OUtpUt hit 3 6 Analog Output Glitter 3 6 Digital VO nenese tte haben oben 3 7 Timing Signal ROUND da 3 7 Programmable Function Inputs oooonncnnncnncnnoncnnnnnncononnnc
17. If you use a PXI compatible plug in card in a standard CompactPCI chassis you cannot use PXI specific functions but you can still use the basic plug in card functions For example the RTSI bus on your PXI E Series device is available in a PXI chassis but not in a CompactPCI chassis The CompactPCI specification permits vendors to develop sub buses that coexist with the basic PCI interface on the CompactPCI bus Compatible operation is not guaranteed between CompactPCI devices with different sub buses nor between CompactPCI devices with sub buses and PXI The standard implementation for CompactPCI does not include these sub buses Your PXI E Series device works in any standard CompactPCI chassis adhering to PICMG CompactPCI 2 0 R2 1 core specification PXI specific features are implemented on the J2 connector of the CompactPCI bus Table 3 3 Pins Used by PXI E Series Device lists the J2 pins used by your PXI E Series device Your PXI device is compatible with any Compact PCI chassis with a sub bus that does not drive these lines Even if the sub bus is capable of driving these lines the PXI device is still compatible as long as those pins on the sub bus are disabled by default and not ever enabled Damage can result if these lines are driven by the sub bus What You Need to Get Started 6023E 6024E 6025E User Manual To set up and use your device you need the following U One of the following devices PCI 6023E PCI 6024E
18. NRSE configuration 4 18 to 4 19 summary of input connections table 4 12 types of signal sources 4 8 to 4 9 floating signal sources 4 9 ground referenced signal sources 4 9 analog input specifications PCI and PXI buses A 1 to A 4 accuracy information A 2 amplifier characteristics A 3 6023E 6024E 6025E User Manual Index dynamic characteristics A 4 input characteristics A 1 to A 2 stability A 4 transfer characteristics A 3 PCMCIA bus A 11 to A 14 accuracy information A 12 amplifier characteristics A 13 dynamic characteristics A 13 input characteristics A 11 stability A 13 to A 14 transfer characteristics A 12 analog output analog output glitch 3 6 common questions C 2 to C 3 overview 3 6 signal connections 4 19 to 4 20 analog output specifications PCI and PXI buses A 4 to A 6 accuracy information A 5 dynamic characteristics A 6 output characteristics A 4 to A 5 stability A 6 transfer characteristics A 5 voltage output A 6 PCMCIA bus A 14 to A 16 accuracy information A 14 dynamic characteristics A 15 output characteristics A 14 stability A 16 transfer characteristics A 14 to A 15 voltage output A 15 AOGND signal 6023E 6024E 6025E User Manual analog output signal connections 4 19 to 4 20 description table 4 4 signal summary table 4 7 B bipolar input 3 3 block diagrams 6023E 6024E 6025E devices 3 1 DAQCard 6024E 3 2 C cables See also I O connect
19. V us AOGND AO DGND DO VCC DO 0 1 Q Short circuit 1A fused to ground DIO lt 0 7 gt DIO Vec 0 5 13 at Vec 0 4 24 at 1 1 50 kQ pu 0 4 PA lt 0 7 gt DIO Vec 0 5 2 5 at 3 7min 2 5 at 5 100 kQ 6025E only 0 4 pu PB lt 0 7 gt DIO Vec 0 5 2 5 at 3 7min 2 5 at 5 100 kQ 6025E only 0 4 pu PC lt 0 7 gt DIO Vec 0 5 2 5 at 3 7min 2 5 at 5 100 kQ 6025E only 0 4 pu SCANCLK DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 KQ pu EXTSTROBE DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFIO TRIG1 DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 KQ pu PFI1 TRIG2 DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI2 CONVERT DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI3 GPCTR1_SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 KQ pu National Instruments Corporation 4 7 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Table 4 3 1 0 Signal Summary Continued Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias PFI4 GPCTR1_GATE DIO Vec 0 5 3 5 at Voc 0 4 5 at 0 4 1 5 50 kQ pu GPCTR1_OUT DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 KQ pu PFIS UPDATE DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu PFI6 WFTRIG DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5
20. WFTRIG 6023E 6024E 6025E User Manual National Instruments driver software for DAQ hardware an undesirable electrical signal Noise comes from external sources such as the AC power line motors generators transformers fluorescent lights soldering irons CRT displays computers electrical storms welders radio transmitters and internal sources such as semiconductors resistors and capacitors Noise corrupts signals you are trying to send or receive nonreferenced single ended mode all measurements are made with respect to a common measurement system reference but the voltage at this reference can vary with respect to the measurement system ground output pin a counter output pin where the counter can generate various TTL pulse waveforms Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA It is achieving widespread acceptance as a standard for PCs and work stations it offers a theoretical maximum transfer rate of 132 Mbytes s programmable function input PFIO trigger 1 PFI1 trigger 2 PFI2 convert PFI3 general purpose counter 1 source PFI4 general purpose counter 1 gate PFIS update PFI6 waveform trigger G 8 ni com PFI7 STARTSCAN PFI8 GPCTRO_ SOURCE PFI9 GPCTRO_GATE PGIA port PPI ppm pu pulse trains Q quantization error R referenced signal sources resolution ribbon cable rise time rms
21. a maximum timing resolution of 50 ns The DAQ STC makes possible such applications as buffered pulse generation equivalent time sampling and seamless changing of the sampling rate PCI 6023E PCI 6024E PCI 6025E and PXI 6025E only With many DAQ devices you cannot easily synchronize several measurement functions to a common trigger or timing event These devices have the Real Time System Integration RTSI bus to solve this problem In a PCI system the RTSI bus consists of the National Instruments RTSI bus interface and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ devices in your computer In a PXI system the RTSI bus consists of the National Instruments RTSI bus interface and the PXI trigger signals on the PXI backplane to route timing and trigger signals between several functions on as many as seven DAQ devices in your system O National Instruments Corporation 1 1 6023E 6024E 6025E User Manual Chapter 1 Introduction Using PXI with These devices can interface to an SCXI system the instrumentation front end for plug in DAQ devices so that you can acquire analog signals from thermocouples RTDs strain gauges voltage sources and current sources You can also acquire or generate digital signals for communication and control CompactPCI Using PXI compatible products with standard CompactPCI products is an important feature provided by PXI Specification Revision 1 0
22. an analog input common signal that routes directly to the ground connection point on the devices You can use this signal for a general analog ground connection point to your device if necessary The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to your device Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the device The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the 4 10 ni com Chapter 4 Signal Connections gain setting of the amplifier The amplifier output voltage is referenced to the ground for the device The A D converter ADC of your device measures this output voltage when it performs A D conversions Reference all signals to ground either at the source device or at the device If you have a floating source reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors see the Differential Connections for Nonreferenced or Floating Signal Sources section If you have a grounded source do not reference the signal to AIGND You can avoid this reference by using DIFF or NRSE input configurations Analog Input Signal Connections The following sections discuss the use of single ended and DIFF measurements and recommendations for measuring both floating and ground referenced signal sources
23. connections NRSE configuration 4 18 to 4 19 H hardware configuration 2 3 installation 2 2 to 2 3 hardware overview analog input 3 2 to 3 6 dithering 3 4 to 3 5 input modes 3 2 to 3 3 input range 3 3 analog output 3 6 block diagram 6023E 6024E 6025E devices 3 1 DAQCard 6024E 3 2 digital I O 3 7 timing signal routing 3 7 to 3 11 device and RTSI clocks 3 9 programmable function inputs 3 8 to 3 9 RTSI triggers 3 9 to 3 11 ni com IBF signal description table 4 25 mode input timing figure 4 27 mode 2 bidirectional timing figure 4 29 input modes 3 2 to 3 3 See also analog input input range exceeding common mode input ranges caution 4 10 measurement precision table 3 3 overview 3 3 installation common questions C 2 hardware 2 2 to 2 3 software 2 1 unpacking 6023E 6024E 6025E 2 1 INTR signal description table 4 26 mode input timing figure 4 27 mode output timing figure 4 28 mode 2 bidirectional timing figure 4 29 T O connectors 4 1 to 4 8 exceeding maximum ratings warning 4 1 I O connector details table 4 1 optional connectors B 2 to B 6 50 pin E Series connector pin assignments figure B 5 50 pin extended digital input connector pin assignments figure B 6 68 pin E Series connector pin assignments figure B 3 68 pin extended digital input connector pin assignments figure B 4 pin assignments table 6023E 6024E 4 2 6025E 4 3 National In
24. latch IBF Output Input buffer full a high signal on this handshaking line indicates that data has been loaded into the input latch A low signal indicates the device is ready for more data This is an input acknowledge signal National Instruments Corporation 4 25 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Table 4 5 Signal Names Used in Timing Diagrams Continued Name Type Description ACK Input Acknowledge input a low signal on this handshaking line indicates that the data written to the port has been accepted This signal is a response from the external device indicating that it has received the data from your DIO device OBF Output Output buffer full a low signal on this handshaking line indicates that data has been written to the port INTR Output Interrupt request this signal becomes high when the 82C55A requests service during a data transfer You must set the appropriate interrupt enable bits to generate this signal RD Internal Read this signal is the read signal generated from the control lines of the computer I O expansion bus WR Internal Write this signal is the write signal generated from the control lines of the computer I O expansion bus DATA Bidirectional Data lines at the specified port for output mode this signal indicates the availability of data on the data line For input mode this signal indicates when the data on the data lines sho
25. lt 0 9 gt lt Sample Interval Counter TC 3 gt GPCTRO_OUT MPAA PCI and PXI Buses Only Figure 3 4 CONVERT Signal Routing Figure 3 4 shows that CONVERT can be generated from a number of sources including the external signals RTSI lt 0 6 gt PCI and PXI buses only and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTRO_OUT On PCI and PXI devices many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTS Triggers section in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmable Function Inputs Ten PFI pins are available on the device connector as PFI lt 0 9 gt and connect to the internal signal routing multiplexer of the device for each timing signal Software can select any one of the PFI pins as the external source for a given timing signal It is important to note that you can use any of the PFI pins as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing 6023E 6024E 6025E User Manual 3 8 ni com Chapter 3 Hardware Overview scheme reduces the need to change physical connections to the I O connector for different applications You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector s
26. misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks CVI DAQ STC LabVIEW Measurement Studio MITE National Instruments ni com NI DAQ NI PGIA PXI RTSI SCXI and VirtualBench are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN ANY APPLICATION INCLUDING THE ABOVE RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILER
27. of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTRO_GATE signal reflects the actual gate signal connected to general purpose counter 0 This is true even if the gate is externally generated by another PFI This output is set to high impedance at startup Figure 4 36 shows the timing requirements for the GPCTRO_GATE signal 6023E 6024E 6025E User Manual 4 44 ni com Chapter 4 Signal Connections Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 36 GPCTRO_GATE Signal Timing in Edge Detection Mode GPCTRO_OUT Signal This signal is available only as an output on the GPCTRO_OUT pin The GPCTRO_OUT signal reflects the terminal count TC of general purpose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup Figure 4 37 shows the timing of the GPCTRO_OUT signal GPCTRO_SOURCE GPCTRO_OUT Pulse on TC GPCTRO_OUT Toggle Output on TC i TC I q Figure 4 37 GPCTRO_OUT Signal Timing GPCTRO_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general
28. one scan period O National Instruments Corporation 4 37 6023E 6024E 6025E User Manual Chapter 4 Signal Connections A counter on your device internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIG1 signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence can be gated by either the hardware AIGATE signal or software command register gate CONVERT Signal Any PFI pin can externally input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer to Figures 4 17 and 4 18 for the relationship of CONVERT to the DAQ sequence As an input the CONVERT signal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion The ADC switches to hold mode within 60 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next Separate the CONVERT pulses by at least 5 us 200 kHz sample rate As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC This is true even if the conversions are externally ge
29. purpose counter 0 counts down when this pin is at a logic low and count up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free for general use National Instruments Corporation 4 45 6023E 6024E 6025E User Manual Chapter 4 Signal Connections GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal which is available as an output on the PFI3 GPCTR1_SOURCE pin As an input the GPCTR1_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR1_SOURCE monitors the actual clock connected to general purpose counter 1 This is true even if the source clock is externally generated by another PFI This output is set to high impedance at startup Figure 4 38 shows the timing requirements for the GPCTR1_SOURCE signal tp 50 ns minimum tw 23 ns minimum Figure 4 38 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE p
30. shows the timing requirements for the SISOURCE signal tp 50 ns minimum tw 23 ns minimum Figure 4 29 SISOURCE Signal Timing Waveform Generation Timing Connections The analog group defined for your device is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you select internally generated UPDATE 6023E 6024E 6025E User Manual 4 40 ni com Chapter 4 Signal Connections As an output the WFTRIG signal reflects the trigger that initiates waveform generation This is true even if the waveform generation is externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup Figures 4 30 and 4 31 show the input and output timing requirements for the WFTRIG signal Rising Edge Polarity Falling Edge Polarity tw 10ns minimum Figure 4 30 WFTRIG Input Signal Timing 1 4 1 I 1 1 1 1 i ty 50 100 n
31. the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE 4 42 ni com Chapter 4 Signal Connections signal You must configure the PFI pin you select as the source for the UISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 34 shows the timing requirements for the UISOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 34 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections The general purpose timing signals are GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT GPCTRO_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT GPCTRO_SOURCE Signal Any PFI pin
32. timing I O common questions C 3 to C 5 specifications PCI and PXI buses A 8 PCMCIA bus A 16 to A 17 timing signal routing 3 7 to 3 11 CONVERT signal routing figure 3 8 device and RTSI clocks 3 9 programmable function inputs 3 8 to 3 9 RTSI triggers 3 9 to 3 11 timing specifications 4 25 to 4 29 mode input timing figure 4 27 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 signal names used in diagrams table 4 25 to 4 26 TRIGI signal 4 34 to 4 35 TRIG2 signal 4 35 to 4 36 trigger specifications PCI and PXI buses digital trigger A 9 RTSI trigger A 9 PCMCIA bus A 17 digital trigger A 17 triggers RTSI See RTSI trigger lines 6023E 6024E 6025E User Manual Index U UISOURCE signal 4 42 to 4 43 unpacking 6023E 6024E 6025E 2 1 UPDATE signal 4 41 to 4 42 V VCC signal table 4 7 VirtualBench software 1 4 voltage output specifications PCI and PXI buses A 6 PCMCIA bus A 15 W waveform generation questions about C 2 to C 3 6023E 6024E 6025E User Manual 1 10 waveform generation timing connections 4 40 to 4 43 UISOURCE signal 4 42 to 4 43 UPDATE signal 4 41 to 4 42 WFTRIG signal 4 40 to 4 41 Web support from National Instruments D 1 WFTRIG signal 4 40 to 4 41 Worldwide technical support D 2 WR signal description table 4 26 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 ni com
33. with a DIFF configuration for every channel up to eight analog input channels are available Use DIFF input connections for any channel that meets any of the following conditions e The input signal is low level less than 1 V e The leads connecting the signal to the device are greater than 3 m 10 ft e The input signal requires a separate ground reference point or return signal e The signal leads travel through noisy environments DIFF signal connections reduce picked up noise and increase common mode noise rejection DIFF signal connections also allow input signals to float within the common mode limits of the PGIA National Instruments Corporation 4 13 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Differential Connections for Ground Referenced Signal Sources Figure 4 5 shows how to connect a ground referenced signal source to a channel on the device configured in DIFF input mode n ACH o oo Ground o oe Referenced it Signal Y Programmable Gain S Vs Instrumentation oe e Amplifier o So PGIA ACH gt Lo oo Measured Common Bl Voltage Mode EN o co e Noise and V o Cos Ground cm s 4 Potential iF 7 o so Input Multiplexers AISENSE a AIGND 1 0 Connector Selected Channel in DIFF Configuration Figure 4 5 Differential Input Connections for Ground Referenced Si
34. your device for one of three input modes nonreferenced single ended NRSE referenced single ended RSE and differential DIFF With the different configurations you can use the PGIA in different ways Figure 4 3 shows a diagram of the PGIA of your device National Instruments Corporation 4 9 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Programmable Gain Instrumentation Amplifier Vins O PGIA Vm Measured Voltage Vm Vins Vin Gain Figure 4 3 Programmable Gain Instrumentation Amplifier PGIA In single ended mode RSE and NRSE signals connected to ACH lt 0 15 gt are routed to the positive input of the PGIA In DIFF mode signals connected to ACH lt 0 7 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 gt are routed to the negative input of the PGIA Caution Exceeding the DIFF and common mode input ranges distorts your input signals Exceeding the maximum input voltage rating can damage the device and the computer National Instruments is not liable for any damages resulting from such signal connections The maximum input voltage ratings are listed in the Protection column of Table 4 3 6023E 6024E 6025E User Manual In NRSE mode the AISENSE signal connects internally to the negative input of the PGIA when their corresponding channels are selected In DIFF and RSE modes AISENSE is left unconnected AIGND is
35. 23E 6024E 6025E User Manual A 2 ni com Appendix A Specifications for PCI and PXI Buses Transfer Characteristics Relative accuracy 0 0 cece eeeeseeseeseeeees 0 5 LSB typ dithered 1 5 LSB max undithered DN ui 0 5 LSB typ 1 0 LSB max NO missing codes ccoooccoccnoccconncnonanonncnnnnos 12 bits guaranteed Offset error Pregain error after calibration 12 uV max Pregain error before calibration 28 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Before calibration oooncnninnnn n 2 75 of reading max Gain 1 with gain error adjusted to 0 at gain Lo 0 05 of reading max Amplifier Characteristics Input impedance Normal powered on 1 0 0 eee 100 GQ in parallel with 100 pF Powered Offenen as 4 KQ min Overload cooociit inca diticiis 4 KQ min Input bias current eee eters 200 pA Input offset current eee eee 100 pA CMRR DC to 60 Hz Gain 05 1 Ob cota nites 85 dB Gait TOY TOO oca 90 dB National Instruments Corporation A 3 6023E 6024E 6025E User Manual Appendix A Specifications for PCI and PXI Buses Dynamic Characteristics Bandwidth Signal Bandwidth Small 3 dB 500 kHz Large 1 THD 225 kHz Settling time for full scale step 5 us max to 1 0 LSB accuracy
36. 25E User Manual Index EXTSTROBE signal DAQ timing connections 4 33 to 4 34 description table 4 5 signal summary table 4 7 F field wiring considerations 4 49 floating signal sources description 4 9 differential connections 4 15 to 4 16 single ended connections RSE configuration 4 18 FREQ_OUT signal description table 4 6 general purpose timing signal connections 4 49 signal summary table 4 8 frequently asked questions See questions and answers fuse self resetting C 1 G gain error adjusting 5 3 general purpose timing signal connections 4 43 to 4 49 FREQ _ OUT signal 4 49 GPCTRO_GATE signal 4 44 to 4 45 GPCTRO_OUT signal 4 45 GPCTRO_SOURCE signal 4 43 to 4 44 GPCTRO_UP_DOWN signal 4 45 GPCTR1_GATE signal 4 46 to 4 47 GPCTR1_OUT signal 4 47 GPCTR1_SOURCE signal 4 46 GPCTR1_UP_DOWN signal 4 47 to 4 49 glitch analog output 3 6 GPCTRO_GATE signal 4 44 to 4 45 6023E 6024E 6025E User Manual 1 4 GPCTRO_OUT signal description table 4 6 general purpose timing signal connections 4 45 signal summary table 4 8 GPCTRO_SOURCE signal 4 43 to 4 44 GPCTRO_UP_DOWN signal 4 45 GPCTR1_GATE signal 4 46 to 4 47 GPCTR1_OUT signal description table 4 5 general purpose timing signal connections 4 47 signal summary table 4 8 GPCTR1_SOURCE signal 4 46 GPCTR1_UP_DOWN signal 4 47 to 4 49 ground referenced signal sources description 4 9 differential connections 4 14 single ended
37. 4 V signal connects to channel 0 and a 1 mV signal connects to channel 1 and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1 When the multiplexer switches to channel 1 and the PGIA switches to a gain of 100 the new full scale range 1s 50 mV O National Instruments Corporation 3 5 6023E 6024E 6025E User Manual Chapter 3 Hardware Overview The approximately 4 V step from 4 V to 1 mV is 4 000 of the new full scale range It can take as long as 100 us for the circuitry to settle to 1 LSB after such a large transition In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also increase when scanning high impedance signals due to a phenomenon called charge injection where the analog input multiplexer injects a small amount of charge into each signal source when that source is selected If the impedance of the source is not low enough the effect of the charge a voltage error has not decayed by the time the ADC samples the signal For this reason keep source impedances under 1 kQ to perform high speed scanning Due to the previously described limitations of settling times resulting from these conditions multiple channel scanning is not recommended unless sampling rates are low enough or it is necessary to sample several signals as nearly simultaneously as possible The data is much more accurate and channel to channel independent i
38. 4E Figure 4 2 shows the pin assignments for the 100 pin I O connector on the PCI 6025E Refer to Appendix B Custom Cabling and Optional Connectors for pin National Instruments Corporation 4 1 6023E 6024E 6025E User Manual Chapter 4 6023E 6024E 6025E User Manual Signal Connections assignments of the optional 50 and 68 pin connectors A signal description follows the figures ACH8 ACH1 AIGND ACH10 ACH3 AIGND ACH4 AIGND ACH13 ACH6 AIGND ACH15 DACOOUT DAC10UT RESERVED DIO4 DGND DIO1 DIO6 DGND 5 V DGND DGND PFIO TRIG1 PFI1 TRIG2 DGND 5 V DGND PFI5 UPDATE PFI6 WFTRIG DGND PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT 1 Not available on the 6023E wo A 68 e 9 67 ie N 66 w 65 ww Oo 64 N o 63 Nm 62 N NI 61 Nm O 60 N al 59 ho A 58 N wo 57 Nm N 56 m 55 S o 54 k o 53 52 e N 51 O 50 al 49 A 48 k wo 47 N 46 a 45 o 44 o 43 42 41 40 39 38 37 36 N AJAJ oN oo 35 ACHO AIGND ACH9 ACH2 AIGND ACH11 AISENSE ACH12 ACH5 AIGND ACH14 ACH7 AIGND AOGND AOGND DGND DIOO DIO5 DGND DIO2 DIO7 DIO3 SCANCLK EXTSTROBE DGN
39. 50 kQ pu PFI7 STARTSCAN DIO Voc 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 KQ pu PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5 at Voc 0 4 5 at 0 4 1 5 50 kQ pu PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 1 5 50 KQ pu GPCTRO_OUT DO 3 5 at Voc 0 4 5 at 0 4 1 5 50 kQ pu FREQ_ OUT DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu AI Analog Input AO Analog Output 100 KQ DIO Digital Input Output DO Digital Output pu pullup Note The tolerance on the 50 kQ pullup and pulldown resistors is very large Actual value can range between 17 kQ and Analog Input Signal Overview Types of Signal Sources The analog input signals for these devices are ACH lt 0 15 gt ASENSE and AIGND Connection of these analog input signals to your device depends on the type of input signal source and the configuration of the analog input channels you are using This section provides an overview of the different types of signal sources and analog input configuration modes More specific signal connection information is provided in the Analog Input Signal Connections section When configuring the input channels and making signal connections you must first determine whether the signal sources are floating or ground referenced 6023E 6024E 6025E User Manual 4 8 ni com Chapter 4 Signal Connections Floating Signal Sources A floating signal source is not connected in any way
40. A 14 to A 16 calibration A 17 digital I O A 16 environment A 18 ni com physical A 18 power requirements A 17 timing I O A 16 to A 17 triggers A 17 STARTSCAN signal 4 36 to 4 38 STB signal description table 4 25 mode input timing figure 4 27 mode 2 bidirectional timing figure 4 29 storage environment specifications PCI and PXI buses A 10 system integration by National Instruments D 1 T technical support resources D 1 timing connections 4 30 to 4 49 DAQ timing connections 4 32 to 4 40 AIGATE signal 4 39 CONVERT signal 4 38 to 4 39 EXTSTROBE signal 4 33 to 4 34 SCANCLK signal 4 33 SISOURCE signal 4 40 STARTSCAN signal 4 36 to 4 38 TRIG1 signal 4 34 to 4 35 TRIG2 signal 4 35 to 4 36 typical posttriggered acquisition figure 4 32 typical pretriggered acquisition figure 4 33 general purpose timing signal connections 4 43 to 4 49 FREQ_OUT signal 4 49 GPCTRO_GATE signal 4 44 to 4 45 GPCTRO_OUT signal 4 45 GPCTRO_SOURCE signal 4 43 to 4 44 GPCTRO_UP_DOWN signal 4 45 GPCTR1_GATE signal 4 46 to 4 47 National Instruments Corporation Index GPCTR1_OUT signal 4 47 GPCTR1_SOURCE signal 4 46 GPCTR1_UP_DOWN signal 4 47 to 4 49 overview 4 30 programmable function input connections 4 31 to 4 32 timing I O connections figure 4 31 waveform generation timing connections 4 40 to 4 43 UISOURCE signal 4 42 to 4 43 UPDATE signal 4 41 to 4 42 WFTRIG signal 4 40 to 4 41
41. ATE DGND Input PFI4 Counter 1 Gate as an input this is one of the PFIs Output As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTR1_OUT DGND Output Counter 1 Output this output is from the general purpose counter output National Instruments Corporation 4 5 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Table 4 2 1 0 Connector Signal Descriptions Continued Signal Name Reference Direction Description PFIS UPDATE DGND Input PFI5 Update as an input this is one of the PFIs Output As an output this is the UPDATE AO Update signal A high to low edge on UPDATE indicates that the analog output primary group is being updated for the 6024E or 6025E PFI6 WFTRIG DGND Input PFI6 Waveform Trigger as an input this is one of the PFIs Output As an output this is the WFTRIG AO Start Trigger signal In timed analog output sequences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input PFI7 Start of Scan as an input this is one of the PFIs Output As an output this is the STARTSCAN AI Scan Start signal This pin pulses once at the start of each analog input scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTRO_SOURCE DGND Input PFI8 Counter 0 Source as an input this is one of
42. D PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT DGND PFI7 STARTSCAN PFI8 GPCTRO_SOURCE DGND DGND Figure 4 1 1 0 Connector Pin Assignment for the 6023E 6024E 4 2 Chapter 4 Signal Connections AIGND AIGND ACHO ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DACOOUT DAC10UT RESERVED AOGND DGND DIOO DIO4 DIO1 DIO5 DIO2 DIO6 DIO3 DIO7 DGND 5V 5V SCANCLK EXTSTROBE PFIO TRIG1 PFM TRIG2 PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT PFI5 UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_SOURCE PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT 1 51 PC7 2 52 GND 3 53 PC6 4 54 GND 5 55 PC5 6 56 GND 7 57 PC4 Ce 58 anD 9 59 PC3 10 60 GND 11 61 PC2 12 62 GND 13 63 PC1 14 64 GND 15 65 PCO 16 66 GND 17 67 PB7 18 68 GND 19 69 PB6 20 70 GND 21 71 PB5 22 72 GND 23 73 PB4 24 74 GND 25 75 PB3 26 76 GND 27 77 PB2 28 78 GND 29 79 PB1 30 80 GND 31 81 PBO 32 82 GND 33 83 PA7 34 84 GND 35 85 PAG 36 86 GND 37 87 PA5 38 88 GND 39 89 PA4 40 90 GND 41 91 PA3 42 92 GND 43 93 PA2 44 94 GND 45 95 PA1 46 96 GND 47 97 PAO 48 98 GND 49 99 5 V so 100 enp O Na
43. DAQ 6023E 6024E 6025E User Manual Multifunction 1 0 Devices for PCI PXI CompactPCI and PCMCIA Bus Computers NATIONAL December 2000 Edition gt Part Number 322072C 01 Worldwide Technical Support and Product Information ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 794 0100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 284 5011 Canada Calgary 403 274 9391 Canada Ottawa 613 233 5949 Canada Qu bec 514 694 8521 China Shanghai 021 6555 7838 China ShenZhen 0755 3904939 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 5 280 7625 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 0 22 528 94 06 Portugal 351 1 726 9011 Singapore 2265886 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2528 7227 United Kingdom 01635 523545 For further support information see the Technical Support Resources appendix To comment on the documentation send e mail to techpubs ni com Copyright 1998 2000 National Instruments Corporation All rights reserved Important Information Warranty The DAQCard 6024E PCI 6023E PCI 6024E PCI 6025E and PXI 6025E dev
44. EQ_OUT pin The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to high impedance at startup Field Wiring Considerations Environmental noise can seriously affect the accuracy of measurements made with your device 1f you do not take proper care when running signal wires between signal sources and the device The following recommendations apply mainly to analog input signal routing to the device although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions e Use DIFF analog input connections to reject common mode noise e Use individually shielded twisted pair wires to connect analog input signals to the device With this type of wire the signals attached to the CH and CH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference National Instruments Corporation 4 49 6023E 6024E 6025E User Manual Calibration This chapter discusses the calibration procedures for your device If you are using the NI DAQ de
45. IG2 signal description table 4 5 signal summary table 4 7 PFI2 CONVERT signal description table 4 5 signal summary table 4 7 PFI3 GPCTR1_SOURCE signal description table 4 5 signal summary table 4 7 PFI4 GPCTR1_GATE signal description table 4 5 signal summary table 4 8 PFI5 UPDATE signal description table 4 6 signal summary table 4 8 PFI6 WFTRIG signal description table 4 6 signal summary table 4 8 6023E 6024E 6025E User Manual PFI7 STARTSCAN signal description table 4 6 signal summary table 4 8 PFI8 GPCTRO_SOURCE signal description table 4 6 signal summary table 4 8 PFI9 GPCTRO_GATE signal description table 4 6 signal summary table 4 8 PFIs programmable function inputs common questions C 4 to C 5 signal routing 3 8 to 3 9 timing connections 4 31 to 4 32 PGIA programmable gain instrumentation amplifier analog input modes 4 9 to 4 11 differential connections ground referenced signal sources figure 4 14 nonreferenced or floating signal sources 4 15 to 4 16 single ended connections floating signal sources figure 4 18 ground referenced signal sources figure 4 19 physical specifications PCI and PXI buses A 9 to A 10 PCMCIA bus A 18 pin assignments 6023E 6024E figure 4 2 6025E figure 4 3 Port C pin assignments description 4 23 signal assignments table 4 23 posttriggered acquisition figure 4 32 power connections 4 30 power requirement spe
46. MCIA Bus Amplifier Characteristics Input impedance Normal powered on eee 100 GQ in parallel with 100 pF Powered Off eeeseseseeeseeeeeeeeeenes 4 kQ min Overload is sirinin 4 KQ min Input bias current 0 eee eens 200 pA Input offset current eee 100 pA CMRR DC to 60 Hz Gain 0 5 L0 pemanan 85 dB Gain 10 100 asii ursii 90 dB Dynamic Characteristics Bandwidth Signal Bandwidth Small 3 dB 500 kHz Large 1 THD 225 kHz Settling time for full scale step 5 us max to 1 0 LSB accuracy System noise LSB not including quantization Gain Dither Off Dither On 0 5 to 1 0 10 0 65 10 0 45 0 65 100 0 70 0 90 Crosstalk oc eich atada 60 dB DC to 100 kHz Stability Recommended warm up time 30 min Offset temperature coefficient Pre Sain iis ciscssazi iste le eesistatdbestestetiens 15 uV C Postal occitano 240 uV C O National Instruments Corporation A 13 6023E 6024E 6025E User Manual Appendix A Specifications for PCMCIA Bus Gain temperature coefficient 20 ppm C Analog Output Output Characteristics Number of channels eseseeeseeseeeee 2 voltage ResolutiON coccccccccnnnnninnnanananananinannnnnns 12 bits 1 in 4 096 Max update rate A 1 kHz system dependent O cas Double buffered multiplying FIFO buffer SiZO oooooccincninnionnncnconccnnnnnon None Data transfers isoto
47. Mode 12 Bit Selection Sampling ADC Switches AD P FIFO 8 gt Muxes Converter Calibration Dither as 4 Mux Circuitry Ee 2 s EEPROM Confi uration S 2 Memory Al Control a S e IRQ O gt Q r xX Vv i _Analog Input Interrupt Analog i K PFI Trigger y Tigger i Timing Control Request ty Gono cet soe SA ee cee al ontrol i Counter Bus KZ Timing X Timing 1 O DAQ STC interface i DAQ PCMCIA oe Analog Output RTS Bus 7 T T Digital 1 0 7 2 1 DAQ STC Analog Digital 1 0 8 gt Timing Control Interface Bus Output meisce KN lt Daco l AO Control ES Calibration DACs PCMCIA Connector Analog Input Figure 3 2 DAQCard 6024E Block Diagram The analog input section of each device is software configurable The following sections describe in detail each of the analog input settings Input Mode The devices have three different input modes nonreferenced single ended NRSE referenced single ended RSE and differential DIFF input The single ended input configurations provide up to 16 channels The DIFF input configuration provides up to eight channels Input modes are programmed on a per channel basis for multimode scanning For example you can configure the circuitry to scan 12 channels four DIFF channels and eight RSE channels Table 3 1 describes the three input configurations 6023E 6024E 6025E User Manual 3 2 ni com Chapter 3 H
48. Output Transfer 6023E 6024E 6025E User Manual 4 28 ni com Chapter 4 Signal Connections Mode 2 Bidirectional Timing Timing specifications for a bidirectional transfer in mode 2 are shown in Figure 4 15 w i gt WR i i i T6 i 1 lt lt gt OBF INTR l i T7 i gt ACK T3 i i f STB a T s i h 1 110 DE i lt gt BF a RD E i T2 1154 TE ie T i 2 A DATA lt o D T Name Description Minimum Maximum Tl WR 1 to OBF 0 150 T2 Data before STB 1 20 T3 STB Pulse Width 100 T4 STB 0toIBF 1 150 TS Data after STB 1 50 T6 ACK 0 to OBF 1 150 T7 ACK Pulse Width 100 T8 ACK 0 to Output 150 T9 ACK 1 to Output Float 20 250 T10 RD 1 to IBF 0 150 All timing values are in nanoseconds Figure 4 15 Timing Specifications for Mode 2 Bidirectional Transfer O National Instruments Corporation 4 29 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Power Connections Two pins on the 1 0 connector supply 5 V from the computer power supply through a self resetting fuse The fuse resets automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and you can use them to power external digital circuitry The power rating is 4 65 to 5 25 VDC at 1 A for the PCI and PXI device
49. Q pull up to 5 VDC PROD Input High Z 100 kQ pull up to 5 VDC PESO Std Input High Z 100 kQ pull up to 5 VDC Data transfers c cecscsensacitsentenicsen decid Interrupts programmed I O Timing 1 0 Number of channels eee eee 2 up down counter timers 1 frequency scaler Resolution Counter timers cocccccccnccncnnnninnnnnnnnnns 24 bits Frequency scalers eee 4 bits Compatibility o ooonnccconccnoccnonnconncnanannnos TTL CMOS Base clocks available Counter timer oocccccccnccncnnnnnnnnnananane 20 MHz 100 kHz Frequency scalers ooooooncninnnocnnnncns 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency eee 20 MHz Min source pulse duration 10 ns in edge detect mode Min gate pulse duration 10 ns in edge detect mode Data transfers cui DMA interrupts programmed I O DMA Modesisiissadadd Scatter gather single transfer demand transfer 6023E 6024E 6025E User Manual A 8 ni com Appendix A Specifications for PCI and PXI Buses Triggers Digital Trigger Compatibility ooooonnnnocinoninnnonnnnnconnrnncnnos TTL A ea e eri EA Rising or falling edge Pulse Widthicsiiesa reniri 10 ns min RTSI Trigger Lines sissioni 7 Calibration Recommended warm up time 15 min Intervalo seria 1 year External calibration reference gt 6and lt 10V Onboard calibration reference Level talon pits 5 000 V 3 5 mV actual value stored in EEPROM Temperature coefficient
50. RSE mode ACH o OD o So 2 So Programmable Gain Instrumentation Amplifier Floating Signal Source E o Input Multiplexers o AISENSE Measured m Voltage o lt 1 0 Connector AIGND V Selected Channel in RSE Configuration Figure 4 7 Single Ended Input Connections for Nonreferenced or Floating Signals Single Ended Connections for Grounded Signal Sources NRSE Configuration To measure a grounded signal source with a single ended configuration you must configure your device in the NRSE input configuration Connect the signal to the positive input of the PGIA and connect the signal local ground reference to the negative input of the PGIA The ground point of the signal therefore connects to the AISENSE pin Any potential difference between the device ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the PGIA and this difference is rejected by the amplifier If the input circuitry of a device were referenced to ground in this situation as in the RSE input configuration this difference in ground potentials appears as an error in the measured voltage 6023E 6024E 6025E User Manual 4 18 ni com Figure 4 8 shows how to connect a grounded signal source to a channel configured for NRSE mode Chapter 4 Signal Connections Ground Referenced Signal So
51. S AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR
52. V 244 14 uV 100 0 50 to 50 mV 24 41 uV 1 The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note See Appendix A Specifications for absolute maximum ratings National Instruments Corporation 3 3 6023E 6024E 6025E User Manual Chapter 3 Hardware Overview Dithering 6023E 6024E 6025E User Manual When you enable dithering you add approximately 0 5 LSB ms of white Gaussian noise to the signal to be converted by the ADC This addition is useful for applications involving averaging to increase the resolution of your device as in calibration or spectral analysis In such applications noise modulation is decreased and differential linearity is improved by the addition of dithering When taking DC measurements such as when checking the device calibration enable dithering and average about 1 000 points to take a single reading This process removes the effects of quantization and reduces measurement noise resulting in improved resolution For high speed applications not involving averaging or spectral analysis you may want to disable dithering to reduce noise Your software enables and disables the dithering circuitry Figure 3 3 illustrates the effect of dithering on signal acquisition Figure 3 3a shows a small 4 LSB sine wave acquired with dithering off The ADC quantization is clearly visible Figure 3 3b shows what happens when 50 such acq
53. Voltage Calibration REF i DACs Analog Mode Multiplexer Calibration Dither Mux Generator A D ADC Converter i FIFO Data Generic Bus Interface cam Address Data PFI Trigger Timing Digital 1 O 1 0 Connector Configuration Al Control Memory IRQ DMA i T Trigger Analog Input inei ee es Request Counter Bus Timing io DAQ STC interface Su 1 Analog Output RTSI Bus Digital O Timing Control Interface Address Analog IEEPROM DMA Input 1 Control 1 Interface 1 Pl DAQ APE Interface Analog 1 82055 Output Bus Control DIO 1 Interface Control AO Control i Analog Output 1 1 Not on 6023E DAC1 l lt Calibration DACs j 6025E Only DIO Control RTSI Connector PCI Connector for PCI 602X PXI Connector for PXI 6025E Figure 3 1 PCI 6023E PCI 6024E PCI 6025E and PXI 6025E Block Diagram O National Instruments Corporation 3 1 6023E 6024E 6025E User Manual Chapter 3 Hardware Overview Figure 3 2 shows the block diagram for the DAQCard 6024E Calibration DACs A el Co 8 J Analog Mux
54. ad these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed National Instruments Corporation 5 1 6023E 6024E 6025E User Manual Chapter 5 Calibration Self Calibratio This method of calibration is not very accurate because it does not take into account the fact that the device measurement and output voltage errors can vary with time and temperature It is better to self calibrate the device when it is installed in the environment in which it will be used Your device can measure and correct for almost all of its calibration related errors without any external signal connections Your National Instruments software provides a self calibration method This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application Initiate self calibration to minimize the effects of any offset gain and linearity drifts particularly those due to warmup Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relat
55. ailable for generating a sequence of eight pulses in the hardware strobe mode Figure 4 20 shows the timing for the hardware strobe mode EXTSTROBE signal O National Instruments Corporation 4 33 6023E 6024E 6025E User Manual Chapter 4 Signal Connections ia Me VOL ty 600 ns or 5 us Figure 4 20 EXTSTROBE Signal Timing TRIG1 Signal Any PFI pin can externally input the TRIG1 signal which is available as an output on the PFIO TRIG1 pin Refer to Figures 4 17 and 4 18 for the relationship of TRIG1 to the DAQ sequence As an input the TRIGI signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge The selected edge of the TRIGI signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions As an output the TRIG1 signal reflects the action that initiates a DAQ sequence This is true even if the acquisition is externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup Figures 4 21 and 4 22 show the input and output timing requirements for the TRIG1 signal Rising Edge Polarity Falling Edge Polarity tw 10 ns minimum 6023E 6024E 6025E User Manual Figure 4 21 TRIG1 Input Signal Timing 4 34 ni com Chapter 4 Signa
56. all measurements are made with respect to acommon reference measurement system or a ground Also called a grounded measurement system real time system integration bus the National Instruments timing bus that connects DAQ devices directly by means of connectors on top of the devices for precise synchronization of functions seconds samples the clock that counts the output of the channel clock in other words the number of samples taken On boards with simultaneous sampling this counter counts the output of the scan clock and hence the number of scans one or more analog samples taken at the same time or nearly the same time Typically the number of input samples in a scan is equal to the number of channels in the input group For example one scan acquires one new sample from every analog input channel in the group the clock controlling the time interval between scans the number of scans a system takes during a given time period usually expressed in scans per second Signal Conditioning eXtensions for Instrumentation single ended a term used to describe an analog input that is measured with respect to a common ground a property of a DAQ board that has an extremely stable onboard reference and calibrates its own A D and D A circuits without manual adjustments by the user a device that converts a physical phenomenon into an electrical signal the amount of time required for a voltage to reach its final value within spec
57. ardware Overview Table 3 1 Available Input Configurations Configuration Description DIFF A channel configured in DIFF mode uses two analog input lines One line connects to the positive input of the programmable gain instrumentation amplifier PGIA of the device and the other connects to the negative input of the PGIA RSE A channel configured in RSE mode uses one analog input line which connects to the positive input of the PGIA The negative input of the PGIA is internally tied to analog input ground AIGND NRSE A channel configured in NRSE mode uses one analog input line which connects to the positive input of the PGIA The negative input of the PGIA connects to analog input sense AISENSE For diagrams showing the signal paths of the three configurations refer to the Analog Input Signal Overview section in Chapter 4 Signal Connections Input Range The devices have a bipolar input range that changes with the programmed gain You can program each channel with a unique gain of 0 5 1 0 10 or 100 to maximize the 12 bit analog to digital converter ADC resolution With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 2 shows the input range and precision according to the gain used Table 3 2 Measurement Precision Gain Input Range Precision 0 5 10 to 10 V 4 88 mV 1 0 5 to 5 V 2 44 mV 10 0 500 to 500 m
58. are referenced to DGND This reference is demonstrated in Figure 4 16 which shows how to connect an external TRIG1 source and an external CONVERT source to two PFI pins 6023E 6024E 6025E User Manual 4 30 ni com Chapter 4 Signal Connections PFIO TRIG1 PFI2 CONVERT TRIG1 Source CONVERT Source DGND r 7 1 0 Connector Figure 4 16 Timing I O Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the device I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin Be careful not to drive a PFI signal externally when it is configured as an output As an input you can individually configure each PFI pin for edge or level detection and for polarity selection as well You can use the polarity selection for any of the 13 timing signals but the edge or level detection Na
59. ble with you device It has an extensive library of functions that you can call from your application programming environment These functions allow you to use all features of your 6023E 6024E 6025E NI DAQ addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using LabVIEW Measurement Studio or other programming languages your application uses the NI DAQ driver software as illustrated in Figure 1 1 6023E 6024E 6025E User Manual 1 4 ni com Chapter 1 Introduction Conventional LabVIEW Programming Environment Measurement Studio or VirtualBench NZ NI DAQ Driver Software ZN gt Computer or ai Personal SCXI Hardware Workstation Figure 1 1 The Relationship Between the Programming Environment NI DAQ and Your Hardware To download a free copy of the most recent version of NI DAQ click Download Software at ni com Optional Equipment National Instruments offers a variety of products to use with your device including cables connector blocks and other accessories as follows e Cables and cable assemblies shielded and ribbon Connector blocks shielded and unshielded screw terminals RTSI bus cables e SCXI modules and accessor
60. can externally input the GPCTRO_SOURCE signal which is available as an output on the PFI8 GPCTRO_SOURCE pin As an input the GPCTRO_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTRO_SOURCE signal reflects the actual clock connected to general purpose counter 0 This is true even if another PFI is externally inputting the source clock This output is set to high impedance at startup National Instruments Corporation 4 43 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Figure 4 35 shows the timing requirements for the GPCTRO_SOURCE signal tp 50 ns minimum tw 23 ns minimum Figure 4 35 GPCTRO_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRO_SOURCE signal unless you select some external source GPCTRO_GATE Signal Any PFI pin can externally input the GPCTRO_GATE signal which is available as an output on the PFI9 GPCTRO_GATE pin As an input the GPCTRO_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety
61. ciated with a bit or signal name for example DBIO lt 3 0 gt The symbol indicates that the text following it applies only to a specific product a specific operating system or a specific software version This icon denotes a note which alerts you to important information This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash Bold text denotes items that you must select or click on in the software such as menu items and dialog box options Bold text also denotes parameter names CompactPCI refers to the core specification defined by the PCI Industrial Computer Manufacturer s Group PICMG Italic text denotes variables emphasis a cross reference or an introduction to a key concept This font also denotes text that is a placeholder for a word or value that you must supply Monospace font denotes text or characters that you should enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories National Instruments Corporation xi 6023E 6024E 6025E User Manual About This Manual programs subprograms subroutines device names functions operations variables filenames and extensions and code excerpts NI DAQ NI DAQ refers to the NI DAQ driver software for PC compatible computers unless otherwise noted PXI PXI stands for PCI eXtensions for Instrumenta
62. cifications PCI and PXI buses A 9 PCMCIA bus A 17 ni com power up state digital I O 4 24 to 4 25 PPI Programmable Peripheral Interface 6025E only 4 22 to 4 23 changing DIO power up state to pulled low 4 24 to 4 25 digital I O connections block diagram figure 4 22 mode input timing figure 4 27 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 Port C pin assignments 4 23 power up state 4 24 to 4 25 signal names used in diagrams table 4 25 to 4 26 timing specifications 4 25 to 4 29 pretriggered acquisition figure 4 33 programmable function inputs PFIs See PFIs programmable function inputs programmable gain instrumentation amplifier See PGIA programmable gain instrumentation amplifier Programmable Peripheral Interface PPI See PPI Programmable Peripheral Interface PXI products using with CompactPCI 1 2 Q questions and answers C 1 to C 5 analog input and output C 2 to C 3 general information C 1 installation and configuration C 2 timing and digital I O C 3 to C 5 R RD signal description table 4 26 mode input timing figure 4 27 mode 2 bidirectional timing figure 4 29 O National Instruments Corporation 1 7 Index referenced single ended input RSE See RSE referenced single ended mode requirements for getting started 1 2 to 1 3 RSE referenced single ended mode configuration 4 9 to 4 10 description table 3 3 recommended confi
63. eeseeeseceseaeeeenaes AUD VIC rindas tias Programmable Peripheral Interface PPD oooonnconnncninccnocononnconcconnnconcconnnnonncnnnconnnconccnnno Port E BinAssISOMED S cutter setesoeeneseraetecs Power up States iia oil Changing DIO Power up State to Pulled Low eee Timing Specifications vecindad darian eo dais a dns AET aKa Es Mode 1 Input TINE dee ai esi ee eas Mode l Output Timing is sched cao eae ee ii Mode 2 Bidirectional TiMINB oooocnnncnocnnoninnonononnnonncononnnonn cono cono nn non cnn nc nc rancio Power Connections ii A ai Timing COMMECUONS temita bs Programmable Function Input Connections oooconocnnccnononononncononancnnnonnconccnncnnos DAQ Timing Connections ien cos cesee tec cac ets aars E EE a iea e EENES SCANCEK Signal ansias EXTSTROBE Sipha sais iio TRIGI Senado ido hi TRIG2 Signal cti tati STARTSCAN Sloan a CONVERT Siena litiasis E AL AIGATE Senaliucin li SISOURGE Signal ciar 6023E 6024E 6025E User Manual vi ni com Contents Waveform Generation Timing Connections ococonccnocnnonconconnnancnnnonncanaranonnnonnos 4 40 WETRIG Signal ias 4 40 UPDATE Sima iii 4 41 UISOUREE Signmalranrrta lecitina oie aii scenic 4 42 General Purpose Timing Signal Connections ooconcnocnnonconnnoncnnnnnncnnonnncnncnnnonnos 4 43 GPCTRO_SOURCE Signal ccccccessceestesessessssesogseoseseocsensnsantianes 4 43 GPCTRO GATE Signali ninie e ae a E a a 4 44 GPETROcOUT Signal oenen Mand rada 4 45 GPCTRO_UP_DOWN S
64. egory 1 Basic Transportation 6023E 6024E 6025E User Manual A 10 ni com PCMCIA Bus Appendix A Specifications for PCMCIA Bus Analog Input National Instruments Corporation A 11 Input Characteristics Number of channels 0 0 0 0 eee eee 16 single ended or 8 differential software selectable per channel Type Of ADC iii lan Successive approximation Resolution ccccccnnnnnnnncnccnnnccnononononineninis 12 bits 1 in 4 096 Sampling rate oococoncccnncconccnonaconcnnonaconcc nn 200 kS s guaranteed Input signal ranges oseere Bipolar only Board Gain Software Selectable Range 0 5 10 V 1 5 V 10 500 mV 100 50 mV Input Coupling 0 eee eee eeeeeeeeeeees DC Max working voltage signal common mode eseeeeee Each input should remain within 11 V of ground Overvoltage protection Signal Powered On Powered Off ACH lt 0 15 gt 42 35 AISENSE 40 25 FIFO buffer size eee eeeeeeee 2048 S Data transfers oooocccnoccnocononanonnnonnnconccnnnno Interrupts programmed I O Configuration memory size 512 words 6023E 6024E 6025E User Manual Appendix A Specifications for PCMCIA Bus Accuracy Information Absolute Accuracy Relative Accuracy Noise Quantization Absolute Nominal Range V of Reading mV Accuracy Resolution mV Temp at Full Positive Negative Offset Drift Scale
65. ence the source to AIGND The easiest way is to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well as to the negative input of the PGIA without any resistors at all This connection works well for DC coupled sources with low source impedance less than 100 Q However for larger source impedances this connection leaves the DIFF signal path significantly out of balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground Hence this noise appears as a DIFF mode signal instead of a common mode signal and the PGIA does not reject it In this case instead of directly connecting the negative line to AIGND connect it to AIGND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise couples onto both connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 6 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination
66. equivalent of a scan One or more analog or digital output samples Typically the number of output samples in an update is equal to the number of channels in the output group For example one pulse from the update clock produces one update which sends one new sample to every analog output channel in the group the number of output updates per second volts positive supply voltage volts direct current virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program volts input high volts input low volts in measured voltage volts output high volts output low reference voltage volts root mean square G 12 ni com Glossary W waveform multiple voltage readings taken at a specific sampling rate WFTRIG waveform generation trigger signal working voltage the highest voltage that should be applied to a product in normal use normally well under the breakdown voltage for safety margin See also breakdown voltage National Instruments Corporation G 13 6023E 6024E 6025E User Manual Index Numbers 5 V signal description table 4 4 self resetting fuse C 1 82C55A Programmable Peripheral Interface See PPI Programmable Peripheral Interface 6023E 6024E 6025E devices See also hardware overview specificat
67. es National Instruments Corporation 3 9 6023E 6024E 6025E User Manual Chapter 3 Hardware Overview 6023E 6024E 6025E User Manual RTSI Bus Connector 5 Trigger e a 7 fr Clock switch DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz Figure 3 5 PCI RTSI Bus Signal Connection ni com Chapter 3 Hardware Overview PXI Bus Connector Z PXI Star 6 PXI Trigger 0 5 PXI Trigger 7 switch lt TRIGI lt _ TRIG2 lt CONVERT lt WFTRIG lt gt GPCTRO_SOURCE lt t __ GPCTRO_GATE RTSI Switch lt _ _ STARTSCAN gt AIGATE gt SISOURCE gt GPCTR1_GATE DAQ STC UPDATE GPCTRO_OUT UISOURCE GPCTR1_SOURCE RTSI_OSC 20 MHz Figure 3 6 PXI RTSI Bus Signal Connection Table 3 3 lists the name and number of pins used by the PXI 6025E Table 3 3 Pins Used by PXI E Series Device PXIE Series Signal PXI Pin Name PXI J2 Pin Number RTSI lt O 5 gt PXI Trigger lt 0 5 gt B16 A16 A17 A18 B18 C18 RTSI 6 PXI Star D17 RTSI Clock PXI Trigger 7 E16 Reserved LBL lt 0 3 gt C20 E20 A19 C19 Reserved LBR lt 0 12 gt A21 C21 D21 E21 A20 B20 E15 A3 C3 D3 E3 A2 B2 Refer to the T
68. es as the starting address for programmable registers All other addresses are located by adding to the base address a voltage range spanning both negative and positive voltages the voltage high enough to cause breakdown of optical isolation semiconductors or dielectric materials Also see working voltage G 2 ni com bus bus master CH channel CMRR CONVERT counter timer crosstalk CTR current drive capability D D A DAC DACOOUT DACIOUT O National Instruments Corporation G 3 Glossary the group of conductors that interconnect individual circuitry in a computer Typically a bus is the expansion interface to which I O or other devices are connected Examples of PC buses are the ISA bus and PCI bus a type of a plug in board or controller with the ability to read and write devices on the computer bus Celsius channel pin or wire lead to which you apply or from which you read an analog or digital signal Analog signals can be single ended or differential For digital signals channels are grouped to form ports common mode rejection ratio a measure of the ability of a differential amplifier to reject interference from a common mode signal usually expressed in decibels dB convert signal a circuit that counts external pulses or clock pulses timing an unwanted signal on one channel due to an input on a different channel counter the amount of current a digital or analog output channel
69. et to PFI pin high to low and clock source string set to 5 3 Initiate analog input data acquisition which starts only when the analog output waveform generation starts 4 Initiate analog output waveform generation Timing and Digital 1 0 What types of triggering can be hardware implemented on my device Digital triggering is hardware supported on every device Will the counter timer applications that I wrote previously work with the DAQ STC If you are using NI DAQ with LabVIEW some of your applications drawn using the CTR VIs will still run However there are many differences in the counters between the E Series and other devices the counter numbers are different timebase selections are different and the DAQ STC counters are National Instruments Corporation C 3 6023E 6024E 6025E User Manual Appendix C Common Questions 24 bit counters unlike the 16 bit counters on devices without the DAQ STC If you are using the NI DAQ language interface or LabWindows CVI the answer is no the counter timer applications that you wrote previously will not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions will not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must rewrite the application with the GPCTR function calls I am using one of the general purpose counter timers on my device but I do not see the counter timer ou
70. f by using a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of your computer chassis before removing the device from the package e Remove the device from the package and inspect the device for loose components or any other sign of damage Notify National Instruments if the device appears damaged in any way Do not install a damaged device into your computer Never touch the exposed pins of connectors O National Instruments Corporation 2 1 6023E 6024E 6025E User Manual Chapter 2 Installation and Configuration Hardware Installation 6023E 6024E 6025E User Manual After installing your software you are ready to install your hardware Your device will fit in any available slot in your computer However to achieve best noise performance leave as much room as possible between your device and other devices The following are general installation instructions Consult your computer user manual or technical reference manual for specific instructions and warnings PCI device installation 1 Turn off and unplug your computer 2 Remove the top cover of your computer 3 Remove the expansion slot cover on the back panel of the computer 4 Touch any metal part of your computer chassis to discharge any static electricity that might be on your clothes or body 5 Insert the device into a 5 V PCI slot Gently rock the device to ease it into place It may be a tight fit but do not
71. f you acquire data from each channel independently for example 100 points from channel 0 then 100 points from channel 1 then 100 points from channel 2 and so on Analog Output 6025E and 6024E only These devices supply two channels of analog output voltage at the I O connector The bipolar range is fixed at 10 V Data written to the digital to analog converter DAC is interpreted in two s complement format Analog Output Glitch In normal operation a DAC output glitches whenever it is updated with a new value The glitch energy differs from code to code and appears as distortion in the frequency spectrum 6023E 6024E 6025E User Manual 3 6 ni com Chapter 3 Hardware Overview Digital 1 0 The devices contain eight lines of digital I O DIO lt 0 7 gt for general purpose use You can individually software configure each line for either input or output At system startup and reset the digital I O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines 6025E only The 6025E device uses an 82C55A programmable peripheral interface to provide an additional 24 lines of digital I O that represent three 8 bit ports PA PB PC You can program each port as an i
72. force the device into place 6 Screw the mounting bracket of the device to the back panel rail of the computer 7 Visually verify the installation Replace the top cover of your computer 9 Plug in and turn on your computer PCMCIA card installation Insert the DAQCard into any available Type II PCMCIA slot until the connector is seated firmly Insert the card face up It is keyed so that you can only insert it one way PXI device installation 1 Turn off and unplug your computer 2 Choose an unused PXI slot in your system For maximum performance the device has an onboard DMA controller that you can only use if the device is installed in a slot that supports bus arbitration or bus master cards National Instruments recommends installing the device in such a slot The PXI specification requires all slots to support bus master cards but the CompactPCI specification does not If you install in a CompactPCI non master slot you must disable the onboard DMA controller of the device using software 3 Remove the filler panel for the slot you have chosen 2 2 ni com Chapter 2 Installation and Configuration 4 Touch any metal part of your computer chassis to discharge any static electricity that might be on your clothes or body 5 Insert the device into a 5 V PXI slot Use the injector ejector handle to fully insert the device into the chassis 6 Screw the front panel of the device to the front panel mounting rail of the
73. from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory differential nonlinearity a measure in LSB of the worst case deviation of code widths from their ideal value of 1 LSB digital output software that controls a specific hardware device such as a DAQ device electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed Some SCXI modules contain an EEPROM to store measurement correction coefficients G 4 ni com electrostatically coupled EXTSTROBE F FIFO floating signal sources FREQ_OUT ft G 8 gain GATE glitch GPCTR GPCTRO_GATE GPCTRO_OUT GPCTRO_SOURCE GPCTRO_UP_DOWN GPCTR1_GATE GPCTR1_OUT GPCTR1_SOURCE Glossary propagating a signal by means of a varying electric field external strobe signal first in first out memory buffer signal sources with voltage signals that are not connected to an absolute reference or system ground Also called nonreferenced signal sources Some common example of floating signal sources are batteries transformers or thermocouples frequency output signal feet grams the factor by which a signal is amplified sometimes expressed in decibels gate signal an unwanted momentary deviation from a desired signal general purpose counter general purpose counter 0 gate signal general purp
74. from the input or switched to another signal EXTSTROBE DGND Output External strobe you can toggle this output under software control to latch signals or trigger events on external devices PFIO TRIG1 DGND Input PFIO Trigger 1 as an input this is one of the programmable function inputs PFIs PFI signals are explained in the Timing Connections section in this chapter As an output this is the TRIG AI start trigger signal Output In posttrigger data acquisition sequences a low to high transition indicates the initiation of the acquisition sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input PFI1 Trigger 2 as an input this is one of the PFIs Output As an output this is the TRIG2 AI stop trigger signal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications PFI2 CONVERT DGND Input PFI2 Convert as an input this is one of the PFIs Output As an output this is the CONVERT AI convert signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFIB GPCTR1_SOURCE DGND Input PFI3 Counter 1 Source as an input this is one of the PFIs Output As an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_G
75. gn your test and measurement software For C developers Measurement Studio includes LabWindows CVI a fully integrated ANSI C application development environment that features interactive graphics and the LabWindows CVI Data Acquisition and Easy I O libraries For Visual Basic developers Measurement Studio features a set of ActiveX controls for using National Instruments DAQ hardware These ActiveX controls provide a high level National Instruments Corporation 1 3 6023E 6024E 6025E User Manual Chapter 1 Introduction programming interface for building virtual instruments For Visual C developers Measurement Studio offers a set of Visual C classes and tools to integrate those classes into Visual C applications The libraries ActiveX controls and classes are available with Measurement Studio and the NI DAQ software VirtualBench features virtual instruments that combine DAQ products software and your computer to create a stand alone instrument with the added benefit of the processing display and storage capabilities of your computer VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word processors Using LabVIEW Measurement Studio or VirtualBench software greatly reduces the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software shipped with your 6023E 6024E 6025E is compati
76. gnals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground shown as Vom in Figure 4 5 6023E 6024E 6025E User Manual 4 14 ni com Chapter 4 Signal Connections Differential Connections for Nonreferenced or Floating Signal Sources Figure 4 6 shows how to connect a floating signal source to a channel configured in DIFF input mode ACH e Ho OO Bias resistors So see text o Oo Programmable Gain Instrumentation Amplifier Measured Voltage Floating Signal vs J Source fa 3 En o ACH e o oO O OO Bias 6 so Current Return v Paths Ko Input Multiplexers 1 0 Connector o o AISENSE Selected Channel in DIFF Configuration Figure 4 6 Differential Input Connections for Nonreferenced Signals Figure 4 6 shows two bias resistors connected in parallel with the signal leads of a floating signal source If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA The PGIA then saturates causing erroneous readings National Instruments Corporation 4 15 6023E 6024E 6025E User Manual Chapter 4 Signal Connections 6023E 6024E 6025E User Manual You must refer
77. guration figure 4 12 single ended connections for floating signal sources 4 18 RTSI clocks 3 9 RTSI trigger lines overview 3 9 signal connection PCI devices figure 3 10 PXI devices figure 3 11 PXI E series devices figure 3 11 specifications A 9 S sampling rate C 1 SCANCLK signal DAQ timing connections 4 33 description table 4 5 signal summary table 4 7 scanning multichannel 3 5 to 3 6 settling time in multichannel scanning 3 6 signal connections analog input 4 8 to 4 19 common mode signal rejection considerations 4 19 differential connection considerations 4 13 to 4 16 input modes 4 9 to 4 11 single ended connection considerations 4 17 to 4 19 summary of input connections table 4 12 types of signal sources 4 8 to 4 9 6023E 6024E 6025E User Manual Index analog output 4 19 to 4 20 digital I O 4 20 to 4 22 field wiring considerations 4 49 VO connectors 4 1 to 4 8 exceeding maximum ratings warning 4 1 T O connector details table 4 1 T O connector signal descriptions table 4 4 to 4 6 T O signal summary table 4 7 to 4 8 pin assignments figure 4 2 to 4 3 I O connectors optional B 2 to B 6 50 pin E Series connector pin assignments figure B 5 50 pin extended digital input connector pin assignments figure B 6 68 pin E Series connector pin assignments figure B 3 68 pin extended digital input connector pin assignments figure B 4 power connections 4 30 P
78. h a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass 6023E 6024E 6025E User Manual C 2 ni com Appendix C Common Questions deglitching filter to remove some of these glitches depending on the frequency and nature of your output signal Can I synchronize a one channel analog input data acquisition with a one channel analog output waveform generation on my PCI E Series device Yes One way to accomplish this is to use the waveform generation timing pulses to control the analog input data acquisition To do this follow steps 1 through 4 below in addition to the usual steps for data acquisition and waveform generation configuration 1 Enable the PFIS line for output as follows e If you are using NI DAQ call Select Signal deviceNumber ND PFI_5 ND_OUT_UPDATE ND HIGH TO LOW e Ifyou are using LabVIEW invoke the Route Signal VI with the signal name set to PFIS and the signal source set to AO Update 2 Set up data acquisition timing so that the timing signal for A D conversion comes from PFIS as follows e If you are using NI DAQ call Select_Signal deviceNumber ND_IN CONVERT ND_PFI_5 ND_HIGH TO LOW e If you are using LabVIEW invoke AI Clock Config VI with clock source code s
79. ices are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subseq
80. ies for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3 072 channels e Low channel count signal conditioning modules devices and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays National Instruments Corporation 1 5 6023E 6024E 6025E User Manual Chapter 1 Introduction For more information about these products refer to the National Instruments catalogue or web site or call the office nearest you 6023E 6024E 6025E User Manual 1 6 ni com Installation and Configuration This chapter explains how to install and configure your 6023E 6024E or 6025E device Software Installation Install your software before installing your device If you are using LabVIEW LabWindows CVI ComponentWorks or VirtualBench install this software before installing the NI DAQ driver software Refer to the software release notes of your software for installation instructions If you are using NI DAQ refer to your NI DAQ release notes Find the installation section for your operating system and follow the instructions given there Unpacking Your device is shipped in an antistatic package to prevent electrostatic damage to the device Electrostatic discharge can damage several components on the device To avoid such damage in handling the device take the following precautions e Ground yoursel
81. ified accuracy limits the manipulation of signals to prepare them for digitizing G 10 ni com SISOURCE software trigger software triggering SOURCE S s STARTSCAN STC synchronous TC THD THD N TRIG trigger TTL U UI unipolar UISOURCE National Instruments Corporation G 11 Glossary SI counter clock signal a programmed event that triggers an event such as data acquisition a method of triggering in which you simulate an analog trigger using software Also called conditional retrieval source signal samples per second used to express the rate at which a DAQ board samples an analog signal start scan signal system timing controller 1 hardware a property of an event that is synchronized to a reference clock 2 software a property of a function that begins an operation and returns only when the operation is complete terminal count the highest value of a counter total harmonic distortion signal to THD plus noise the ratio in decibels of the overall rms signal to the rms signal of harmonic distortion plus noise introduced trigger signal any event that causes or starts some form of data capture transistor transistor logic update interval a signal range that is always positive for example 0 to 10 V update interval counter clock signal 6023E 6024E 6025E User Manual Glossary update update rate V V Vcc VDC VI 6023E 6024E 6025E User Manual the output
82. ignal ciis tenian anina 4 45 GPCTRI SOURCE Signal c ccceccessseesessrsseserscseseseesesocseseneetens 4 46 GPCTR1 GATE Signal cinc cias ita os 4 46 GPCTRI OUT Signal citant ni 4 47 GPCTR1_UP_DOWN Signal oooconccnocccnoncnocnncnnnoncnncnnnnnonnonnonconnincnncno 4 47 FREQ OUT Sigal iaa 4 49 Field Wiring ConsideratiOWS oonoonocnnonnoonconcononononncnnnonncnnncnn canon nono non ncnn non cnn rro none rn a 4 49 Chapter 5 Calibration Loading Calibration Constant ooooconocnooncocnoonnoncononnonncnnncnnonnnonn cnn n iiaa 5 1 Selt Calibratio titi sor 5 2 External Calibration ins gis 5 2 Other ConsideratiOns tetitas nd ti 5 3 Appendix A Specifications Appendix B Custom Cabling and Optional Connectors Appendix C Common Questions Appendix D Technical Support Resources Glossary Index O National Instruments Corporation vii 6023E 6024E 6025E User Manual Contents Figures Figure 1 1 The Relationship Between the Programming Environment NI DAQ and Your Hardware cccceccccccssseessseceesneeeeseeeesneeessseeeesaees 1 5 Figure 3 1 PCI 6023E PCI 6024E PCI 6025E and PXI 6025E Block Diaria cda 3 1 Figure 3 2 DAQCard 6024E Block DiagraM ooooonnnicnnnnnonnnnncnncononancnnnonnconornncnnannos 3 2 Figure 3 33 Dithe ring il as eszbeses deesic siden sceasseud sgeaase oabaseeecsevtanesaysSaseas 3 5 Figure 3 4 CONVERT Signal Routing ee ceesseeseeeeeseceseeeenseeseenseeaes 3 8 Figure 3 5 PCI RTSI Bus Signal Connec
83. iming Connections section of Chapter 4 Signal Connections for a description of the signals shown in Figures 3 5 and 3 6 National Instruments Corporation 6023E 6024E 6025E User Manual Signal Connections This chapter describes how to make input and output signal connections to your device through the I O connector Table 4 1 shows the cables that can be used with the I O connectors to connect to different accessories Table 4 1 1 0 Connector Details Cable for Cable for Cable for Connecting Connecting Connecting to Device with O Number of to 100 pin to 68 pin 50 pin Signal Connector Pins Accessories Accessories Accessories PCI 6023E 68 N A SH6868 Shielded SH6850Shielded PCI 6024E Cable Cable R6868 Ribbon R6850 Ribbon Cable Cable DAQCard 6024E 68 N A SHC68 68EP 68M 50F Shielded Cable Adapter when RC68 68 Ribbon used with the Cable SHC68 68EP or RC68 68 6025E 100 SH100100 SH1006868 R1005050 Shielded Cable Shielded Cable Ribbon Cable Caution Connections that exceed any of the maximum ratings of input or output signals on the devices can damage the device and the computer Maximum input ratings for each signal are given in the Protection column of Table 4 3 National Instruments is not liable for any damages resulting from such signal connections A 1 0 Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the PCI 6023E PCI 6024E and DAQCard 602
84. in As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on 6023E 6024E 6025E User Manual 4 46 ni com Chapter 4 Signal Connections As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter This is true even if the gate is externally generated by another PFI This output is set to high impedance at startup Figure 4 39 shows the timing requirements for the GPCTR1_GATE signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 39 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC device general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup Figure 4 40 shows the timing requirements for the GPCTR1_OUT signal GPCTR1_SOURCE GPCTR1_OUT Pulse on TC
85. ion How do I set the base address for my device The base address of your device is assigned automatically through the PCI PXI bus protocol This assignment is completely transparent to you What jumpers should I be aware of when configuring my E Series device The E Series devices are jumperless and switchless Which National Instruments document should I read first to get started using DAQ software Your NI DAQ or application software release notes documentation is always the best starting place What version of NI DAQ must I have to use my 6023E 6024E 6025E You must have NI DAO for PC Compatibles version 6 5 or higher to use a PCI a PXI device To use the DAQCard 6024E you must have NI DAQ for PC compatibles version 6 9 or higher Analog Input and Output I m using my device in differential analog input mode and I have connected a differential input signal but my readings are random and drift rapidly What s wrong Check your ground reference connections Your signal can be referenced to a level that is considered floating with reference to the device ground reference Even if you are in differential mode you must still reference the signal to the same ground level as the board reference There are various methods of achieving this while maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter 4 Signal Connections I m using the DACs to generate a waveform but I discovered wit
86. ions block diagram 3 1 features 1 1 to 1 2 optional equipment 1 5 to 1 6 requirements for getting started 1 2 to 1 3 software programming choices 1 3 to 1 5 National Instruments application software 1 3 to 1 4 NI DAQ driver software 1 4 to 1 5 unpacking 2 1 using PXI with CompactPCI 1 2 A ACH lt 0 15 gt signal description table 4 4 signal summary table 4 7 ACK signal description table 4 26 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 acquisition timing connections See DAQ timing connections AIGATE signal 4 39 AIGND signal analog input mode 4 10 description table 4 4 signal summary table 4 7 National Instruments Corporation AISENSE signal description table 4 4 NRSE mode 4 10 signal summary table 4 7 analog input available input configurations table 3 3 common questions C 2 to C 3 dithering 3 4 to 3 5 input modes 3 2 to 3 3 input range 3 3 multichannel scanning considerations 3 5 to 3 6 analog input signal connections 4 8 to 4 19 common mode signal rejection considerations 4 19 differential connections 4 13 to 4 16 ground referenced signal sources 4 14 nonreferenced or floating signal sources 4 15 to 4 16 exceeding common mode input ranges caution 4 10 PGIA figure 4 10 recommended input connections figure 4 12 single ended connection 4 17 to 4 19 floating signal sources RSE configuration 4 18 grounded signal sources
87. is capable of sourcing or sinking while still operating within voltage range specifications digital to analog D A converter an electronic device often an integrated circuit that converts a digital number into a corresponding analog voltage or current analog channel 0 output signal analog channel output signal 6023E 6024E 6025E User Manual Glossary DAQ dB DC DGND DIFF differential amplifier differential input DIO dithering DMA DNL DO drivers driver software E EEPROM 6023E 6024E 6025E User Manual data acquisition 1 collecting and measuring electrical signals from sensors transducers and test probes or fixtures and processing the measurement data using a computer 2 collecting and measuring the same kinds of electrical signals with A D and or DIO boards plugged into a computer and possibly generating control signals with D A and or DIO boards in the same computer decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts direct current digital ground signal differential input configuration an amplifier with two input terminals neither of which are tied to a ground reference whose voltage difference is amplified the two terminal input to a differential amplifier digital input output the addition of Gaussian noise to an analog input signal direct memory access a method by which data can be transferred to
88. is manual 6023E 6024E 6025E User Manual D 2 ni com Glossary Prefix Meanings Value p pico 10 22 n nano 10 2 u micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 10 t tera 102 Numbers Symbols degree gt greater than lt less than negative of or minus Q ohm per percent plus or minus positive of or plus M square root of 5 V 5 VDC source signal National Instruments Corporation G 1 6023E 6024E 6025E User Manual Glossary A A AC ACH A D ADC ADC resolution Al AIGATE AIGND AISENSE ANSI AO AOGND ASIC base address bipolar breakdown voltage 6023E 6024E 6025E User Manual amperes alternating current analog input channel signal analog to digital analog to digital converter an electronic device often an integrated circuit that converts an analog voltage to a digital number the resolution of the ADC which is measured in bits An ADC with 16 bits has a higher resolution and thus a higher degree of accuracy than a 12 bit ADC analog input analog input gate signal analog input ground signal analog input sense signal American National Standards Institute analog output analog output ground signal Application Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions for a specific customer a memory address that serv
89. ive measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration 6023E 6024E 6025E User Manual Your device has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using your device at an extreme temperature or if the onboard reference has not been measured for a year or more you may wish to externally calibrate your device An external calibration refers to calibrating your device with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and you can save the results in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate your device by calling the NI DAQ calibration function To externally calibrate your device be sure to use a very accurate external reference Use a reference that is several times more accurate than the device itself 5 2 ni com Chapter 5 Calibration Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is desig
90. l Connections 1 I I i i lt gt I i 1 I f tw 50 100 ns i 1 Figure 4 22 TRIG1 Output Signal Timing The device also uses the TRIG1 signal to initiate pretriggered DAQ operations In most pretriggered applications the TRIG1 signal is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 18 for the relationship of TRIG2 to the DAQ sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIG1 signal initiates the data acquisition The scan counter indicates the minimum number of scans before TRIG2 can be recognized After the scan counter decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The device ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the device acquires a fixed number of scans and the acquisition stops This mode acq
91. n port C is configured as two 4 bit I O ports In modes 1 and 2 or handshaking configuration port C is used for status and handshaking signals with any leftover lines available for general purpose I O Table 4 4 summarizes the port C signal assignments for each configuration You can also use ports A and B in different modes the table does not show every possible combination 3 Note Table 4 4 shows both the port C signal assignments and the terminology correlation between different documentation sources The 82C55A terminology refers to the different 82C55A configurations as modes whereas NI DAQ ComponentWorks LabWindows CVI and LabVIEW documentation refers to them as handshaking and no handshaking Table 4 4 Port C Signal Assignments Configuration Terminology Signal Assignments 6023E National 6024E 6025E Instruments User Manual Software PC7 PC6 PCS PC4 PC3 PC2 PC1 PCO Mode 0 No vO TO TO TO TO TO YO TO Basic 1 0 Handshaking Mode 1 Handshaking TO TO IBFa STBA INTRa STB3 IBFBg INTRg Strobed Input Mode 1 Handshaking OBF ACK vO 10 INTRA ACKg OBF INTRy Strobed Output Mode 2 Handshaking OBFa ACKa IBF STBA INTRa TO YO T O Bidirectional Bus Indicates that the signal is active low Subscripts A and B denote port A or port B handshaking signals National Instruments Corporation 4 23 6023E 6024E 6025E User Manual Chapter 4 Signal Connection
92. n Powered Off ACH lt 0 15 gt 42 35 AISENSE 40 25 FIFO buffer SiZ8 ooooonoccnncococcconccnonncinnannn 512 S Da taittansfers cisoido eie DMA interrupts programmed I O DMA modegier Scatter gather single transfer demand transfer Configuration memory SiZe 512 words Accuracy Information Absolute Accuracy Relative Accuracy Noise Quantization Absolute Nominal Range V of Reading mV Accuracy Resolution mV Temp at Full Positive Negative Offset Drift Scale FS FS 24 Hours 1 Year mV Single Pt Averaged C mV Single Pt Averaged 10 10 0 0872 0 0914 6 38 3 91 0 975 0 0010 16 504 5 89 1 28 5 5 0 0272 0 0314 3 20 1 95 0 488 0 0005 5 263 2 95 0 642 0 5 0 5 0 0872 0 0914 0 340 0 195 0 049 0 0010 0 846 0 295 0 064 0 05 0 05 0 0872 0 0914 0 054 0 063 0 006 0 0010 0 106 0 073 0 008 Note Accuracies are valid for measurements following an internal E Series calibration Averaged numbers assume dithering and averaging of 100 single channel readings Measurement accuracies are listed for operational temperatures within 1 C of internal calibration temperature and 10 C of external or factory calibration temperature One year calibration interval recommended The Absolute Accuracy at Full Scale calculations were performed for a maximum range input voltage for example 10 V for the 10 V range after one year assuming 100 pt averaging of data 60
93. ned to work only with the internal 10 V reference Thus in general it is not possible to calibrate the analog output gain error when using an external reference In this case it is advisable to account for the nominal gain error of the analog output channel either in software or with external hardware See Appendix A Specifications for analog output gain error information National Instruments Corporation 5 3 6023E 6024E 6025E User Manual Specifications This appendix individually lists the specifications of each bus type and are typical at 25 C PCI and PXI Buses Analog Input Input Characteristics Number of channels cccceseeeeeeees 16 single ended or 8 differential software selectable per channel Type OP ADE Successive approximation Resolution ccccccnnonononconccnnnconaninnonononos 12 bits 1 in 4 096 Sampling rate oe eee eect eeeees 200 kS s guaranteed Input signal ranges ooooccnocccoccinncconnnonnoso Bipolar only Board Gain Software Selectable Range 0 5 10 V 1 5 V 10 500 mV 100 50 mV Input coupling cococnncnnocincnonanananininnannncnnos DC Max working voltage signal common mode eeeeeeeee National Instruments Corporation A 1 Each input should remain within 11 V of ground 6023E 6024E 6025E User Manual Appendix A Specifications for PCI and PXI Buses Overvoltage protection Signal Powered O
94. nerated by another PFI The output is an active low pulse with a pulse width of 50 to 150 ns This output is set to high impedance at startup Figures 4 27 and 4 28 show the input and output timing requirements for the CONVERT signal Polarity Rising Edge 1 t 1 gt Falling Edge Polarity tw 10 ns minimum 6023E 6024E 6025E User Manual Figure 4 27 CONVERT Input Signal Timing 4 38 ni com Chapter 4 Signal Connections ty 50 150 ns Figure 4 28 CONVERT Output Signal Timing The sample interval counter on the device normally generates the CONVERT signal unless you select some external source The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished It then reloads itself in preparation for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence can be gated by either the hardware AIGATE signal or software command register gate AIGATE Signal Any PFI pin can externally input the AIGATE signal which is not available as an output on the I O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for the AIGATE signal in either the level detection or edge detection mode You can config
95. nic Interrupts programmed I O Accuracy Information Absolute Accuracy Absolute Nominal Range V of Reading Accuracy at Temp Drift Full Scale Positive FS Negative FS 24 Hours 90 Days 1 Year Offset mV Jl C mV 10 10 0 0177 0 0197 0 0219 5 93 0 0005 8 127 Note Temp Drift applies only if ambient is greater than 10 C of previous external calibration Transfer Characteristics Relative accuracy INL After calibration eee 0 5 LSB typ 1 0 LSB max Before calibration oooooncconnnmm 4 LSB max DNL After calibration eee 0 5 LSB typ 1 0 LSB max Before calibration ooooncccnnnnnno 3 LSB max MOMOtonicity seriei s 12 bits guaranteed after calibration 6023E 6024E 6025E User Manual A 14 ni com Appendix A Specifications for PCMCIA Bus Offset error After calibration ccccccccccsssseeees 1 0 mV max Before calibration ooooooonnnnnccccncnns 200 mV max Gain error relative to internal reference After calibrati0N oooooononiccccccn Before calibration Voltage Output Rata iso Output coupling eee Output impedance 0 0 eee Current drive cooococcccccnnonconncnnnonncnnonnnonos Protec via in Power on state steady state Initial power up glitch Magnitude cococoocnconnconncnonncnonanannnno Duration nnne snie Power reset glitch Magnitude ococoncnconnconncnonncinnanannnno
96. nnonnncnnonn conc conc rnncrnnonnos 3 8 Device and RTSI Clocks eei iii ada caera Da 3 9 RES TTI Sge Siper a n e irer a E E 3 9 National Instruments Corporation v 6023E 6024E 6025E User Manual Contents Chapter 4 Signal Connections VO Comme NO Analog Input Signal OvervieW oooocnocnocnconconnconcnononncononnnonn cnn nonncrnnonn crono n nan ncn ai Types of Signal Sourcino aeae ne Floating Signal SourCES 00 00 een e e a T S Ground Referenced Signal SQUICES ooooconccnocnnonconnnononanonncnnnonncnnncnnono Analog Input Modest it ids Analog Input Signal ConNectiONS oooconcnocnonnnoncnanonnnonnnnncnnnnnncnnornnonn ono non n nn cnn cnn conc nnccnno Differential Connection Considerations DIFF Input Configuration Differential Connections for Ground Referenced Signal Sources Differential Connections for Nonreferenced or Floating Signal SOUF E S RN Single Ended Connection Considerations essssessessseesereresesrrsrsresresrsresrsee Single Ended Connections for Floating Signal Sources RSE Configura asomar etica traste Single Ended Connections for Grounded Signal Sources NRSE Configuration ccssscesscscscsesscerscsentecsssnscssnsessevenncenseee Common Mode Signal Rejection Considerati0NS ooocooncnocnnononnconncancnnnnnonnnn Analog Output Signal Connections 0 cece eeeeseceeceseeeeeeseeseceseeseesaecseceeecaeeeseeaeenaes Digital I O Signal Connections 0 0 eseseeeessceceeseeeeeesesseeeseeseees
97. nput or output port The 82C55A has three modes of operation simple I O mode 0 strobed I O mode 1 and bidirectional I O mode 2 In modes 1 and 2 the three ports are divided into two groups group A and group B Each group has eight data bits plus control and status bits from Port C PC Modes 1 and 2 use handshaking signals from the computer to synchronize data transfers Refer to Chapter 4 Signal Connections for more detailed information Timing Signal Routing The DAQ STC chip provides a flexible interface for connecting timing signals to other devices or external circuitry Your device uses the RTSI bus to interconnect timing signals between devices PCI and PXI buses only and the programmable function input PFI pins on the I O connector to connect the device to external circuitry These connections are designed to enable the device to both control and be controlled by other devices and circuits There are a total of 13 timing signals internal to the DAQ STC that you can control by an external source You can also control these timing signals by signals generated internally to the DAQ STC and these selections are fully software configurable Figure 3 4 shows an example of the signal routing multiplexer controlling the CONVERT signal National Instruments Corporation 3 7 6023E 6024E 6025E User Manual Chapter 3 Hardware Overview TRTSI Trigger lt 0 6 gt lt 3 gt gt CONVERT PFI
98. nput output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces current output high G 6 ni com kS L LabVIEW LED library linearity LSB MIO MSB Glossary current output low interrupt request kilo the standard metric prefix for 1 000 or 103 used with units of measure such as volts hertz and meters kilo the prefix for 1 024 or 210 used with B in quantifying data or computer memory 1 000 samples laboratory virtual instrument engineering workbench light emitting diode a file containing compiled object modules each comprised of one of more functions that can be linked to other object modules that make use of these functions NIDAQMSC LIB is a library that contains NI DAQ functions The NI DAQ function set is broken down into object modules so that only the object modules that are relevant to your application are linked in while those object modules that are not relevant are not linked the adherence of device response to the equation R KS where R response S stimulus and K a constant least significant bit multifunction I O most significant bit National Instruments Corporation G 7 6023E 6024E 6025E User Manual Glossary NI DAQ noise NRSE OUT PCI PFI PFIO TRIG1 PFI1 TRIG2 PFI2 CONVERT PFI3 GPCTR1_ SOURCE PFI4 GPCTR1_GATE PFIS UPDATE PFI6
99. ns e The input signal is high level greater than 1 V e The leads connecting the signal to the device are less than 10 ft 3 m e The input signal can share a common reference point with other signals DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions Using your software you can configure the channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the device provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the device should not supply one In single ended configurations more electrostatic and magnetic noise couples into the signal connections than in DIFF configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors National Instruments Corporation 4 17 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Single Ended Connections for Floating Signal Sources RSE Configuration Figure 4 7 shows how to connect a floating signal source to a channel configured for
100. oftware can turn on the output driver for the PFIS UPDATE pin Device and RTSI Clocks PCI and PXI buses Many device functions require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector These devices can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the device to use the internal timebase you can also program the device to drive its internal timebase over the RTSI bus to another device that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the device as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal This timebase is software selectable PXI 6025E The RTSI clock connects to other devices through the PXI trigger bus on the PXI backplane The RTSI clock signal uses the PXI trigger lt 7 gt line for this connection RTSI Triggers PCI and PXI buses The seven RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for any device sharing the RTSI bus These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in Figure 3 5 for PCI devices and Figure 3 6 for PXI devic
101. onncnncrnncnncrnncnno canon 3 3 Table 3 2 Measurement Precision oooonnccnncnonnnoncnnnnnnconnnnnonnconnonanonncnn cnn n cnn iei 3 3 Table 3 3 Pins Used by PXI E Series Device ooooonnonocnnonnocnonncononancononanonncnnncanonnnono 3 11 Table 4 1 YO Connector Detalls inisinia eni oiiaaie 4 1 Table 4 2 T O Connector Signal DescriptiONS oonocnononocnonnnonnnancnncnnconncnnorncnnonnnons 4 4 Table 4 3 VO Signal UM Y cicle 4 7 Table 4 4 Port C Signal Assignments ococconocnnonconnnnncnnnnnncnncnnnonnonnn cono nnncnnonnncnncnnnons 4 23 Table 4 5 Signal Names Used in Timing Diagrams ooooconccnoccnononncnnninncnnncnnconcnnnonos 4 25 O National Instruments Corporation ix 6023E 6024E 6025E User Manual About This Manual The 6023 6024 and 6025 E Series boards are high performance multifunction analog digital and timing I O boards for PCI PXI PCMCIA and CompactPCI bus computers Supported functions include analog input analog output digital I O and timing I O This manual describes the electrical and mechanical aspects of the PCI 6023E PCI 6024E DAQCard 6024E PCI 6025E and PXI 6025E boards from the E Series product line and contains information concerning their operation and programming Conventions Used in This Manual lt gt bold CompactPCI italic monospace The following conventions are used in this manual Angle brackets containing numbers separated by an ellipsis represent a range of values asso
102. or the digital signals at the I O connector as well as the 5 VDC supply All three ground references AIGND AOGND and DGND are connected on your device DIO lt 0 7 gt DGND Input or Output Digital I O signals DIO6 and 7 can control the up down signal of general purpose counters O and 1 respectively PA lt 0 7 gt DGND Input or Output Port A bidirectional digital data lines for the 82C55A programmable peripheral interface on the 6025E PA7 is the MSB PAO is the LSB PB lt 0 7 gt DGND Input or Output Port B bidirectional digital data lines for the 82C55A programmable peripheral interface on the 6025E PB7 is the MSB PBO is the LSB PC lt 0 7 gt 2 DGND Input or Output Port C bidirectional digital data lines for the 82C55A programmable peripheral interface on the 6025E PC7 is the MSB PCO is the LSB 5 V DGND Output 5 VDC Source these pins are fused for up to 1 A of 5 V supply on the PCI and PXI devices or up to 0 75 A from a DAQCard device The fuse is self resetting 6023E 6024E 6025E User Manual 4 4 ni com Chapter 4 Signal Connections Table 4 2 1 0 Connector Signal Descriptions Continued Signal Name Reference Direction Description SCANCLK DGND Output scan clock this pin pulses once for each A D conversion in scanning mode when enabled The low to high edge indicates when the input signal can be removed
103. ors custom cabling B 1 to B 2 field wiring considerations 4 49 optional equipment 1 5 calibration 5 1 to 5 3 adjusting gain error 5 3 external calibration 5 2 loading calibration constants 5 1 to 5 2 self calibration 5 2 specifications PCI and PXI buses A 9 PCMCIA bus A 17 charge injection 3 6 clocks device and RTSI 3 9 commonly asked questions See questions and answers common mode signal rejection considerations 4 19 CompactPCI products using with PXI 1 2 configuration common questions C 2 hardware configuration 2 3 connectors See I O connectors conventions used in manual xi xii CONVERT signal DAQ timing connections 4 38 to 4 39 signal routing figure 3 8 custom cabling B 1 to B 2 customer education D 1 ni com D DACOOUT signal analog output signal connections 4 19 to 4 20 description table 4 4 signal summary table 4 7 DACIOUT signal analog output signal connections 4 19 to 4 20 description table 4 4 signal summary table 4 7 DAQ timing connections 4 32 to 4 40 AIGATE signal 4 39 CONVERT signal 4 38 to 4 39 EXTSTROBE signal 4 33 to 4 34 SCANCLK signal 4 33 SISOURCE signal 4 40 STARTSCAN signal 4 36 to 4 38 TRIGI signal 4 34 to 4 35 TRIG2 signal 4 35 to 4 36 typical posttriggered acquisition figure 4 32 typical pretriggered acquisition figure 4 33 DAQCard 6024E block diagram 3 2 DAQ STC C 1 DATA signal description table 4 26 mode input timing figu
104. ose counter 0 output signal general purpose counter 0 clock source signal general purpose counter 0 up down general purpose counter gate signal general purpose counter output signal general purpose counter clock source signal National Instruments Corporation G 5 6023E 6024E 6025E User Manual Glossary GPCTR1_UP_DOWN GPIB grounded measurement system H h hex Hz INL input bias current input impedance input offset current instrumentation amplifier interrupt VO Ton 6023E 6024E 6025E User Manual general purpose counter 1 up down General Purpose Interface bus synonymous with HP IB The standard bus used for controlling electronic instruments with a computer Also called IEEE 488 bus because it is defined by ANSI IEEE Standards 488 1978 488 1 1987 and 488 2 1987 See RSE hour hexadecimal hertz cycles per second of a periodic signal integral nonlinearity a measure in LSB of the worst case deviation from the ideal A D or D A transfer characteristic of the analog I O circuitry the current that flows into the inputs of a circuit the measured resistance and capacitance between the input terminals of a circuit the difference in the input bias currents of the two inputs of an instrumentation amplifier a very accurate differential amplifier with a high input impedance a computer signal indicating that the CPU should suspend its current task to service a designated activity i
105. ow these steps 1 Install a load R1 Remember that the smaller the resistance the greater the current consumption and the lower the voltage 4 24 ni com Chapter 4 Signal Connections 2 Using the following formula calculate the largest possible load to maintain a logic low level of 0 4 V and supply the maximum driving current V IxRL gt RL VI where V 04V Voltage across RL I 46uA 10uA 4 6 V across the 100 KQ pull up resistor and 10 uA maximum leakage current Therefore RL 7 1kQ 0 4 V 56 UA This resistor value 7 1 kQ provides a maximum of 0 4 V on the DIO line at power up You can substitute smaller resistor values to lower the voltage or to provide a margin for V variations and other factors However smaller values draw more current leaving less drive current for other circuitry connected to this line The 7 1 kQ resistor reduces the amount of logic high source current by 0 4 mA with a 2 8 V output Timing Specifications 6025E only This section lists the timing specifications for handshaking with your 6025E PC lt 0 7 gt lines The handshaking lines STB and IBF synchronize input transfers The handshaking lines OBF and ACK synchronize output transfers Table 4 5 describes signals appearing in the handshaking diagrams Table 4 5 Signal Names Used in Timing Diagrams Name Type Description STB Input Strobe input a low signal on this handshaking line loads data into the input
106. rcuit ASIC designed by National Instruments and is the backbone of the E Series devices The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into the following three groups e Analog input two 24 bit two 16 bit counters e Analog output three 24 bit one 16 bit counters e General purpose counter timer functions two 24 bit counters You can configure the groups independently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalent time sampling and seamless changing of the sampling rate are possible What does sampling rate mean to me It means that this is the fastest you can acquire data on your device and still achieve accurate results For example these devices have a sampling rate of 200 kS s This sampling rate is aggregate one channel at 200 kS s or two channels at 100 kS s per channel illustrates the relationship What type of 5 V protection do the devices have The PCI and PXI devices have 5 V lines equipped with a self resetting 1 A fuse The PCMCIA cards have 5 V lines equipped with a self resetting 0 75 A fuse National Instruments Corporation C 1 6023E 6024E 6025E User Manual Appendix C Common Questions Installation and Configurat
107. re 4 27 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 device and RTSI clocks 3 9 DGND signal description table 4 4 digital I O signal connections 4 20 to 4 21 signal summary table 4 7 DIFF mode description table 3 3 recommended configuration figure 4 12 O National Instruments Corporation Index differential connections 4 13 to 4 16 ground referenced signal sources 4 14 nonreferenced or floating signal sources 4 15 to 4 16 when to use 4 13 digital I O See also PPI Programmable Peripheral Interface common questions C 3 to C 5 overview 3 7 signal connections 4 20 to 4 22 block diagram of digital I O connections figure 4 22 digital I O connections figure 4 21 digital I O specifications PCI and PXI buses A 7 to A 8 DIO lt 0 7 gt A 7 PA lt 0 7 gt PB lt 0 7 gt PC lt 0 7 gt A 7 PCMCIA bus A 16 DIO lt 0 7 gt A 16 digital trigger specifications A 9 DIO power up state changing to pulled low 4 24 to 4 25 DIO lt 0 7 gt signal description table 4 4 digital I O signal connections 4 20 to 4 21 digital I O specifications A 7 signal summary table 4 7 dithering 3 4 to 3 5 documentation conventions used in manual xi xii related documentation xii E EEPROM storage of calibration constants 5 1 environment specifications PCI and PXI buses A 10 PCMCIA bus A 18 environmental noise 4 49 equipment optional 1 5 to 1 6 6023E 6024E 60
108. rence signal Figure 4 9 shows how to make analog output connections to your device o DACOOUT OF Channel 0 VOUT 0 Load VOUT 1 Analog Output Channels DAC10UT Load T o4 Channel 1 1 0 Connector Figure 4 9 Analog Output Connections Digital 1 0 Signal Connections All Devices All devices have digital I O signals DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually as inputs or outputs Figure 4 10 shows signal connections for three typical digital I O applications UN Caution Exceeding the maximum input voltage ratings which are listed in Table 4 2 can damage the DAQ device and the computer National Instruments is not liable for any damages resulting from such signal connections 6023E 6024E 6025E User Manual 4 20 ni com Chapter 4 Signal Connections LED zA MM lq ot DIO lt 4 7 gt o Hal gt o P TTL Signal o DIO lt 0 3 gt o p 5V VVV gt Switch gt n ae DGND 1 O Connector Figure 4 10 Digital 1 0 Connections Figure 4 10 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external de
109. rogrammable Peripheral Interface 6025E only 4 22 to 4 23 mode input timing figure 4 27 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 Port C pin assignments 4 23 power up state 4 24 to 4 25 signal names used in diagrams table 4 25 to 4 26 timing specifications 4 25 to 4 29 timing connections 4 30 to 4 49 DAQ timing connections 4 32 to 4 40 general purpose timing signal connections 4 43 to 4 49 6023E 6024E 6025E User Manual 1 8 programmable function input connections 4 31 to 4 32 waveform generation timing connections 4 40 to 4 43 signal sources 4 8 to 4 9 floating signal sources 4 9 ground referenced signal sources 4 9 single ended connections 4 17 to 4 19 floating signal sources RSE configuration 4 18 grounded signal sources NRSE configuration 4 18 to 4 19 when to use 4 17 SISOURCE signal 4 40 software installation 2 1 software programming choices 1 3 to 1 5 LabVIEW and LabWindows CVI 1 3 to 1 4 Measurement Studio software 1 3 to 1 4 National Instruments application software 1 3 to 1 4 NI DAQ driver software 1 4 to 1 5 VirtualBench 1 4 specifications PCI and PXI buses analog input A 1 to A 4 analog output A 4 to A 6 calibration A 9 digital I O A 7 to A 8 operating environment A 10 physical A 9 to A 10 power requirement A 9 storage environment A 10 timing I O A 8 triggers A 9 PCMCIA bus A 11 to A 18 analog input A 11 to A 14 analog output
110. s Power up State 4 6023E 6024E 6025E User Manual 6025E only The 6025E contains bias resistors that control the state of the digital I O lines PA lt 0 7 gt PB lt 0 7 gt PC lt 0 7 gt at power up Each digital I O line is configured as an input pulled high by a 100 kQ bias resistor You can change individual lines from pulled up to pulled down by adding your own external resistors This section describes the procedure Changing DIO Power up State to Pulled Low Each DIO line is pulled to V approximately 5 VDC with a 100 KQ resistor To pull a specific line low connect between that line and ground a pull down resistor RL whose value gives you a maximum of 0 4 VDC The DIO lines provide a maximum of 2 5 mA at 3 7 V in the high state Using the largest possible resistor ensures that you do not use more current than necessary to perform the pull down task However make sure the value of the resistor is not so large that leakage current from the DIO line along with the current from the 100 kQ pull up resistor drives the voltage at the resistor above a TTL low level of 0 4 VDC Figure 4 12 shows the DIO configuration for high DIO power up state Device 5 V 100 k 82055 Digital I O Line 1 Ri Figure 4 12 DIO Channel Configured for High DIO Power up State with External Load Example A given DIO line is pulled high at power up To pull it low on power up with an external resistor foll
111. s and 4 65 to 5 25 VDC at 0 75A for PCMCIA cards UN Caution Under no circumstances connect these 5 V power pins directly to analog or digital grounds or to any other voltage source on the device or any other device Doing so can damage the device and the computer National Instruments is not liable for damages resulting from such a connection Timing Connections UN Caution Exceeding the maximum input voltage ratings which are listed in Table 4 3 can damage the device and the computer National Instruments is not liable for any damages resulting from such signal connections All external control over the timing of your device is routed through the 10 programmable function inputs labeled PFI lt 0 9 gt These signals are explained in detail in the Programmable Function Input Connections section These PFIs are bidirectional as outputs they are not programmable and reflect the state of many DAQ waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any DAQ waveform generation and general purpose timing signals The DAQ signals are explained in the DAQ Timing Connections section the waveform generation signals in the Waveform Generation Timing Connections section and the general purpose timing signals in the General Purpose Timing Signal Connections section All digital timing connections
112. s i 1 j Figure 4 31 WFTRIG Output Signal Timing UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFIS UPDATE pin As an input the UPDATE signal is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode O National Instruments Corporation 4 41 6023E 6024E 6025E User Manual Chapter 4 Signal Connections As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs This is true even if the updates are externally generated by another PFI The output is an active low pulse with a pulse width of 300 to 350 ns This output is set to high impedance at startup Figures 4 32 and 4 33 show the input and output timing requirements for the UPDATE signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum 6023E 6024E 6025E User Manual Figure 4 32 UPDATE Input Signal Timing tw 300 350 ns Figure 4 33 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The device UI counter normally generates
113. share their own techniques Customer Education National Instruments provides a number of alternatives to satisfy your training needs from self paced tutorials videos and interactive CDs to instructor led hands on courses at locations around the world Visit the Customer Education section of ni com for online course schedules syllabi training centers and class registration System Integration If you have time constraints limited in house technical resources or other dilemmas you may prefer to employ consulting or system integration services You can rely on the expertise available through our worldwide network of Alliance Program members To find out more about our Alliance system integration solutions visit the System Integration section of ni com National Instruments Corporation D 1 6023E 6024E 6025E User Manual Appendix D Technical Support Resources Worldwide Support National Instruments has offices located around the world to help address your support needs You can access our branch office Web sites from the Worldwide Offices section of ni com Branch office web sites provide up to date contact information support phone numbers e mail addresses and current events If you have searched the technical support resources on our Web site and still cannot find the answers you need contact your local office or National Instruments corporate Phone numbers for our worldwide offices are listed at the front of th
114. stics Relative accuracy INL After calibration 0 3 LSB typ 0 5 LSB max Before calibration ooooonnnnnnccnnnnn 4 LSB max DNL After calibration eee 0 3 LSB typ 1 0 LSB max Before calibration ooooooconnccccnnnns 3 LSB max Monotonicity oooococcccncnconccnnncnnnncnnnanonccancno 12 bits guaranteed after calibration Offset error After calibration 1 0 mV max 200 mV max Before calibration Gain error relative to internal reference After calibration eee 0 01 of output max Before calibration eee 0 75 of output max National Instruments Corporation A 5 6023E 6024E 6025E User Manual Appendix A 6023E 6024E 6025E User Manual Specifications for PCI and PXI Buses Voltage Output Rad iia E Output coupling sses Output impedance eee Current driven ires nininini Protections ernen oane Power on state steady state Initial power up glitch Magnitude eeseeeseeseeeeees Duration ccccnnnnnnonnanonononnnnnnnononnnons Power reset glitch Magnitude ceeeeseeeseeseeeeees Duration coconcncnnanoanonnnnnnnnnnnonononons Dynamic Characteristics Settling time for full scale step Slew rate occccccccccncncnoninnnnnananananonononos Midscale transition glitch Magnitude eeseesseeseeeeees Duration isisisi issiria Stability Offset temperature coefficient Gain temperature coefficient
115. struments Corporation 1 5 Index L LabVIEW and LabWindows CVI application software 1 3 to 1 4 manual See documentation Measurement Studio software 1 3 to 1 4 mode input timing figure 4 27 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 multichannel scanning considerations 3 5 to 3 6 NI Developer Zone D 1 NI DAQ driver software 1 4 to 1 5 noise environmental 4 49 NRSE nonreferenced single ended mode configuration 4 9 to 4 10 description table 3 3 differential connections 4 15 to 4 16 recommended configuration figure 4 12 single ended connections for ground referenced signal sources 4 18 to 4 19 0 OBF signal description table 4 26 mode 1 output timing figure 4 28 mode 2 bidirectional timing figure 4 29 operating environment specifications PCI and PXI buses A 10 PCMCIA bus A 18 optional equipment 1 5 to 1 6 6023E 6024E 6025E User Manual Index P PA lt 0 7 gt signal description table 4 4 digital I O specifications A 7 signal summary table 4 7 PB lt 0 7 gt signal description table 4 4 digital I O specifications A 7 signal summary table 4 7 PC lt 0 7 gt signal description table 4 4 digital I O specifications A 7 signal summary table 4 7 PCI and PXI bus specifications See specifications PCMCIA bus specifications See specifications PFIO TRIG1 signal description table 4 5 signal summary table 4 7 PFI1 TR
116. sum of the two resistors If for example the source impedance is 2 kQ and each of the two resistors is 100 kQ the resistors load down the source with 200 KQ and produce a 1 gain error Both inputs of the PGIA require a DC path to ground in order for the PGIA to work If the source is AC coupled capacitively coupled the PGIA needs a resistor between the positive input and AIGND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 KQ to 1 MQ In this case you can tie the negative input directly to AIGND If the source has high output impedance balance the signal path as previously described using the same value resistor on both the positive and negative inputs be aware that there is some gain error from loading down the source 4 16 ni com Chapter 4 Signal Connections Single Ended Connection Considerations A single ended connection is one in which the device analog input signal is referenced to a ground that it can share with other input signals The input signal is tied to the positive input of the PGIA and the ground is tied to the negative input of the PGIA When every channel is configured for single ended input up to 16 analog input channels are available You can use single ended input connections for any input signal that meets the following conditio
117. system 7 Visually verify the installation Plug in and turn on your computer The device is installed You are now ready to configure your hardware and software Hardware Configuration National Instruments standard architecture for data acquisition and standard bus specifications makes these devices completely software configurable You must perform two types of configuration on the devices bus related and data acquisition related configuration The PCI devices are fully compatible with the industry standard PCI Local Bus Specification Revision 2 2 The PXI device is fully compatible with the PXI Specification Revision 2 0 These specifications let your computer automatically set the device base memory address and interrupt channel without your interaction You can modify data acquisition related configuration settings such as analog input range and mode through application level software Refer to Chapter 3 Hardware Overview for more information about the various settings available for your device These settings are changed and configured through software after you install your device Refer to your software documentation for configuration instructions O National Instruments Corporation 2 3 6023E 6024E 6025E User Manual Hardware Overview This chapter presents an overview of the hardware functions on your device Figure 3 1 shows a block diagram for the PCI 6023E PCI 6024E PCI 6025E and PXI 6025E
118. the PFIs Output As an output this is the GPCTRO_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTRO_GATE DGND Input PFI9 Counter 0 Gate as an input this is one of the PFIs Output As an output this is the GPCTRO_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 GPCTRO_OUT DGND Output Counter 0 Output this output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output this output is from the frequency generator output Indicates that the signal is active low Not available on the 6023E 2 Not available on the 6023E or 6024E 6023E 6024E 6025E User Manual 4 6 ni com Chapter 4 Signal Connections Table 4 3 shows the I O signal summary for the 6023E 6024E and 6025E Table 4 3 1 0 Signal Summary Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias ACH lt 0 15 gt AI 100 GQ 42 35 200 pA in parallel with 100 pF AISENSE AI 100 GQ 40 25 200 pA in parallel with 100 pF AIGND AO DACOOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 10 6024E and 6025E only to ground V us DACIOUT AO 0 1 Q Short circuit 5 at 10 5 at 10 10 6024E and 6025E only to ground
119. the hardware This means that the device circuitry is not actively driving the output either high or low However these lines can have pull up or pull down resistors connected to them as shown in Table 4 3 O Signal Summary These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 is in the high impedance state 6023E 6024E 6025E User Manual C 4 ni com Appendix C Common Questions after power on and Table 4 3 O Signal Summary shows that there is a 50 KQ pull up resistor This pull up resistor sets the DIO O pin to a logic high when the output is in a high impedance state National Instruments Corporation C 5 6023E 6024E 6025E User Manual Technical Support Resources Web Support National Instruments Web support is your first stop for help in solving installation configuration and application problems and questions Online problem solving and diagnostic resources include frequently asked questions knowledge bases product specific troubleshooting wizards manuals drivers software updates and more Web support is available through the Technical Support section of ni com NI Developer Zone The NI Developer Zone at ni com zone is the essential resource for building measurement and automation systems At the NI Developer Zone you can easily access the latest example programs system configurators tutorials technical news as well as a community of developers ready to
120. the source signal applies when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on your device Figure 4 41 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by t and tsp in Figure 4 41 The gate signal is not required to be held after the active edge of the source signal 6023E 6024E 6025E User Manual 4 48 ni com Chapter 4 Signal Connections If you use an internal timebase clock the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the devices Figure 4 41 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ_OUT Signal This signal is available only as an output on the FREQ_OUT pin The frequency generator of the device outputs the FR
121. tion eee eeeseeseceeeneeeeeeeeeeeaes 3 10 Figure 3 6 PXI RTSI Bus Signal Connection eee eeseeeeeeeeneeeseeeeeeeeaes 3 11 Figure 4 1 I O Connector Pin Assignment for the 6023E 6024E eee 4 2 Figure 4 2 I O Connector Pin Assignment for the 6025E ote eee ee eeeeeeeee 4 3 Figure 4 3 Programmable Gain Instrumentation Amplifier PGIA 0 4 10 Figure 4 4 Summary of Analog Input Connections oooconccnonnnonconnonnnanonanonncanannnonnss 4 12 Figure 4 5 Differential Input Connections for Ground Referenced Signals 4 14 Figure 4 6 Differential Input Connections for Nonreferenced Signals 4 15 Figure 4 7 Single Ended Input Connections for Nonreferenced or Floating Signals sicrie aerei ltd italia 4 18 Figure 4 8 Single Ended Input Connections for Ground Referenced Signals 4 19 Figure 4 9 Analog Output Connections eee seeceeeseeeeeeseeeeeesecseeeseeneenaes 4 20 Figure 4 10 Digital I O Connections 0 0 ee eee ceeceseceeeeseeseeesecseceseeneseseeseenaes 4 21 Figure 4 11 Digital I O Connections Block DiagraM oooonnconcnonnnnnnonnnoncnnnonnnnncnncnnos 4 22 Figure 4 12 DIO Channel Configured for High DIO Power up State with External Loiola casi dot 4 24 Figure 4 13 Timing Specifications for Mode 1 Input Transfer 00 4 27 Figure 4 14 Timing Specifications for Mode 1 Output Transfer oe 4 28 Figure 4 15 Timing Specifications for Mode 2 Bidirectional Transfer 4 29 Figure
122. tion PXI is an open specification that builds off the CompactPCI specification by adding instrumentation specific features Related Documentation The following documents contain information you may find helpful e DAQ STC Technical Reference Manual e National Instruments Application Note 025 Field Wiring and Noise Considerations for Analog Signals e PCT Local Bus Specification Revision 2 2 e PICMG CompactPCI 2 0 R2 1 e PXI Specification Revision 2 0 e PC Card PCMCIA 7 1 Standard 6023E 6024E 6025E User Manual xii ni com Introduction This chapter describes the 6023E 6024E and 6025E devices lists what you need to get started gives unpacking instructions and describes the optional software and equipment Features of the 6023E 6024E and 6025E The 6025E features 16 channels eight differential of analog input two channels of analog output a 100 pin connector and 32 lines of digital T O The 6024E features 16 channels of analog input two channels of analog output a 68 pin connector and eight lines of digital I O The 6023E is identical to the 6024E except that it does not have analog output channels These devices use the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control analog input analog output and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and
123. tional Instruments Corporation Figure 4 2 1 0 Connector Pin Assignment for the 6025E 4 3 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Table 4 2 shows the I O connector signal descriptions for the 6023E 6024E and 6025E Table 4 2 1 0 Connector Signal Descriptions Signal Name Reference Direction Description AIGND Analog input ground these pins are the reference point for single ended measurements in RSE configuration and the bias current return point for DIFF measurements All three ground references AIGND AOGND and DGND are connected on your device ACH lt 0 15 gt AIGND Input Analog input channels 0 through 15 you can configure each channel pair ACH lt i i 8 gt i 0 7 as either one DIFF input or two single ended inputs AISENSE AIGND Input Analog input sense this pin serves as the reference node for any of channels ACH lt 0 15 gt in NRSE configuration DACOOUT AOGND Output Analog channel 0 output this pin supplies the voltage output of analog output channel 0 DACIOUT AOGND Output Analog channel output this pin supplies the voltage output of analog output channel 1 AOGND Analog output ground the analog output voltages are referenced to this node All three ground references AIGND AOGND and DGND are connected together on your device DGND Digital ground this pin supplies the reference f
124. tional Instruments Corporation 4 31 6023E 6024E 6025E User Manual Chapter 4 Signal Connections depends upon the particular timing signal you are controlling The detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detect mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there can be limits imposed by the particular timing signal that is controlled These requirements are listed in this chapter under the section for each applicable signal DAQ Timing Connections 6023E 6024E 6025E User Manual The DAQ timing signals are SCANCLK EXTSTROBE TRIG1 TRIG2 STARTSCAN CONVERT AIGATE and SISOURCE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 17 Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 18 shows a typical pretriggered DAQ sequence The description for each signal shown in these figures is included in this chapter under the section for each corresponding signal TRIG1 i
125. to the building ground system but has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolators and isolation amplifiers An instrument or device that has an isolated output is a floating signal source You must tie the ground reference of a floating signal to the analog input ground of your device to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the device assuming that the computer is plugged into the same power system Non isolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference can appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Analog Input Modes You can configure
126. tput on the I O connector What am I doing wrong If you are using the NI DAQ language interface or LabWindows CVI you must configure the output line to output the signal to the I O connector Use the Select Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are high impedance What are the PFIs and how do I configure these lines PFIs are programmable function inputs These lines serve as connections to virtually all internal timing signals If you are using the NI DAQ language interface or LabWindows CVI use the Select _Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config CTR Mode Config and CTR Pulse Config advanced level VIs to indicate which function the connected signal serves Use the Route Signal VI to enable the PFI lines to output internal signals UN Caution If you enable a PFI line for output do not connect any external signal source to it if you do you can damage the device the computer and the connected equipment What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by
127. ts Figure 4 30 WFTRIG Input Signal Timing 000 0 cece ceeceeeneeeeteeenaeenees 4 41 Figure 4 31 WHFTRIG Output Signal Timing cece ceecereeneetseeeeetseesees 4 41 Figure 4 32 UPDATE Input Signal Timing eee ceeceeeceeeeeetneeneeeaees 4 42 Figure 4 33 UPDATE Output Signal Timing oooonccnonnnonconnnnnonanonnnnncnncnnnonncnnncnncnnnoo 4 42 Figure 4 34 UISOURCE Signal Timing cece eeseeneceeeceeneeeaesneeeseenees 4 43 Figure 4 35 GPCTRO_SOURCE Signal Timing o0 eee cece eeeeseceeeeeeees 4 44 Figure 4 36 GPCTRO_GATE Signal Timing in Edge Detection Mode 4 45 Figure 4 37 GPCTRO_OUT Signal Timing cece eeeereeeseeseseeeeeeeees 4 45 Figure 4 38 GPCTR1_SOURCE Signal Timing ococoncnnonnonnnonconcnnncnnnnnncnnonaconncnn conos 4 46 Figure 4 39 GPCTR1_GATE Signal Timing in Edge Detection Mode 4 47 Figure 4 40 GPCTR1_OUT Signal Timing 000 ceeereeeseeeseeeeseenees 4 47 Figure 4 41 GPCTR Timing Summary eee eeceeseesseeseceeeeseeneeesesneeeaeenees 4 48 Figure B 1 68 Pin E Series Connector Pin Assignments ccoconcnnocnonnnoncononnonncnnccnnos B 3 Figure B 2 68 Pin Extended Digital Input Connector Pin Assignments B 4 Figure B 3 50 Pin E Series Connector Pin Assignments ocooconconocnonnnoncnncnnonncnncinnos B 5 Figure B 4 50 Pin Extended Digital Input Connector Pin Assignments B 6 Tables Table 3 1 Available Input Configurations ooooconocnonnnonconconnnononan
128. ty ooonconncninnnnonicnnoncnnonnnonos Input High Z 50 KQ pull up to 5 VDC Programmed I O 2 up down counter timers 1 frequency scaler ni com Appendix A Specifications for PCMCIA Bus Base clocks available Counter timers 0 0 0 eeeeeeee 20 MHz 100 kHz Frequency scalers ee eee 10 MHz 100 kHz Base clock accuracy sssr 0 01 Max source frequency eee 20 MHz Min source pulse duration 0 10 ns in edge detect mode Min gate pulse duration 10 ns in edge detect mode Data transfers criticas Interrupts programmed I O Triggers Digital Trigger Compatibility oooonnnnocinonionnnanonncnnnnancnnos TTL RESPONSE srpen o eree Rising or falling edge Pulse Width ooooocnnccnnnccnoccnonccnonccnnnnonanos 10 ns min Calibration Recommended warm up time 30 min A TE 1 year External calibration reference gt 6and lt 10V Onboard calibration reference TGV AA 5 000 V 3 5 mV actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability eee 15 ppm 1 000 h Power Requirement ES VIDE 45 isis 270 mA 3 Note Excludes power consumed through V available at the I O connector Power available at I O connector 4 65 to 5 25 VDC at 0 75 A National Instruments Corporation A 17 6023E 6024E 6025E User Manual Appendix A Specifications for PCMCIA Bus Physical PC card t p ssiininenines asnar T
129. ual start pulse that initiates a scan This is true even if the starts are externally triggered by another PFI You have two output options The first is an active high pulse with a pulse width of 50 to 100 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress STARTSCAN is 4 36 ni com Chapter 4 Signal Connections deasserted t after the last conversion in the scan is initiated This output is set to high impedance at startup Figures 4 25 and 4 26 show the input and output timing requirements for the STARTSCAN signal 1 ty lt q Rising Edge Polarity i Falling Edge Polarity J tw 10 ns minimum Figure 4 25 STARTSCAN Input Signal Timing i tw i lt gt STARTSCAN ss i tw 50 100 ns i a Start of Scan Start Pulse CONVERT STARTSCAN gt tog 10 ns minimum b Scan in Progress Two Conversions per Scan Figure 4 26 STARTSCAN Output Signal Timing The CONVERT pulses are masked off until the device generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT appears when the onboard sample interval counter reaches zero If you select an external CONVERT the first external pulse after STARTSCAN generates a conversion Separate the STARTSCAN pulses by at least
130. uent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse
131. uires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence This is true even if the acquisition is externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup National Instruments Corporation 4 35 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Figures 4 23 and 4 24 show the input and output timing requirements for the TRIG2 signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum 6023E 6024E 6025E User Manual Figure 4 23 TRIG2 Input Signal Timing ty 50 100ns Figure 4 24 TRIG2 Output Signal Timing STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 17 and 4 18 for the relationship of STARTSCAN to the DAQ sequence As an input the STARTSCAN signal is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter starts if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the act
132. uisitions are averaged together quantization is still plainly visible In Figure 3 3c the sine wave is acquired with dithering on There is a considerable amount of visible noise but averaging about 50 such acquisitions as shown in Figure 3 3d eliminates both the added noise and the effects of quantization Dithering has the effect of forcing quantization noise to become a zero mean random variable rather than a deterministic function of the input signal 3 4 ni com Chapter 3 Hardware Overview a Dither disabled no averaging b Dither disabled average of 50 acquisitions c Dither enabled no averaging d Dither enabled average of 50 acquisitions Figure 3 3 Dithering Multichannel Scanning Considerations The devices can scan multiple channels at the same maximum rate as their single channel rate however pay careful attention to the settling times for each of the devices No extra settling time is necessary between channels as long as the gain is constant and source impedances are low Refer to Appendix A Specifications for a complete listing of settling times for each of the devices When scanning among channels at various gains the settling times can increase When the PGIA switches to a higher gain the signal on the previous channel can be well outside the new smaller range For instance suppose a
133. uld be valid 6023E 6024E 6025E User Manual 4 26 ni com Chapter 4 Signal Connections Mode 1 Input Timing Timing specifications for an input transfer in mode are shown in Figure 4 13 i Ti i lt gt i T2 T4 a a STB IBF EA i i 1 oTe eoj AR INTR RD i A A Doo T3 oOo o a e gt DATA lt gt Name Description Minimum Maximum Tl STB Pulse Width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 T5 Data after STB 1 50 T6 RD 0 to INTR 0 200 T7 RD 1 to IBF 0 150 All timing values are in nanoseconds Figure 4 13 Timing Specifications for Mode 1 Input Transfer O National Instruments Corporation 6023E 6024E 6025E User Manual Chapter 4 Signal Connections Mode 1 Output Timing Timing specifications for an output transfer in mode 1 are shown in Figure 4 14 Eora WR i o ME 1 1 1 A oe aa ON Tr O14 TE lt gt INTR ACK DATA gt T2 LI Name Description Minimum Maximum Tl WR 0 to INTR 0 250 T2 WR 1 to Output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 NN 150 TS ACK Pulse Width 100 T6 ACK 1 to INTR 1 150 All timing values are in nanoseconds Figure 4 14 Timing Specifications for Mode 1
134. urce Common Mode Noise and Ground 2 ACH lt 0 15 gt oo So 5 so Instrumentation Amplifier o 6 Input Multiplexers Measured Potential JOP 1 O Connector Voltage P a Selected Channel in NRSE Configuration AISENSE D Figure 4 8 Single Ended Input Connections for Ground Referenced Signals Common Mode Signal Rejection Considerations Figures 4 5 and 4 8 show connections for signal sources that are already referenced to some ground point with respect to the device In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the device In addition with DIFF input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the device The PGIA can reject common mode signals as long as V and V input signals are both within 11 V of AIGND Analog Output Signal Connections O National Instruments Corporation 4 19 6024E and 6025E The analog output signals are DACOOUT DACIOUT and AOGND DACOOUT and DACIOUT are not available on the 6023E DACOOUT is the voltage output signal for analog output channel 0 DACIOUT is the voltage output signal for analog output channel 1 6023E 6024E 6025E User Manual Chapter 4 Signal Connections AOGND is the ground reference signal for both analog output channels and the external refe
135. ure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur In the edge detection mode the first active edge disables the STARTSCAN signal and the second active edge enables STARTSCAN The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan in other words once a scan has started AIGATE does not gate off conversions until the beginning of the next scan and conversely if conversions are gated off AIGATE does not gate them back on until the beginning of the next scan National Instruments Corporation 4 39 6023E 6024E 6025E User Manual Chapter 4 Signal Connections SISOURCE Signal Any PFI pin can externally input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for the SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source Figure 4 29
136. vice driver that software includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments For these devices these adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of device calibration is required for all but the most forgiving applications If you do not calibrate your device your signals and measurements could have very large offset gain and linearity errors Three levels of calibration are available to you and described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants Your device is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the device is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ software determines when this is necessary and does it automatically If you are not using NI DAQ you must lo
137. vice states such as the state of the switch shown in the Figure 4 11 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 4 11 Figure 4 11 depicts signal connections for three typical digital I O applications National Instruments Corporation 4 21 6023E 6024E 6025E User Manual Chapter 4 Signal Connections LED ao V O O O TTL Signal O 5V lt AN Y Switch po X 1 O Connector DIO Device Figure 4 11 Digital 1 0 Connections Block Diagram Programmable Peripheral Interface PPI 6025E only The 6025E device uses an 82C55A PPI to provide an additional 24 lines of digital I O that represent three 8 bit ports PA PB and PC You can program each port as an input or output port In Figure 4 11 port A of one PPI is configured for digital output and port B is configured for digital input Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 4 11 Digital output applications include sending 6023E 6024E 6025E User Manual 4 22 ni com Chapter 4 Signal Connections TTL signals and driving external devices such as the LED shown in Figure 4 11 Port C Pin Assignments 6025 only The signals assigned to port C depend on how the 82C55A is configured In mode 0 or no handshaking configuratio
138. ype II T O COMNECTON coocooccncccononancnncnnncnnonancnncnn nono 68 position VHDCI female connector Environment Operating temperature eee 0 to 40 C with a maximum internal device temperature of 70 C as measured by onboard temperature sensor Storage temperature eee 20 to 70 C Relative humidity oooconnccnoninnnoccnoncnnnnnnnn 10 to 95 non condensing 6023E 6024E 6025E User Manual A 18 ni com Custom Cabling and Optional Connectors This appendix describes the various cabling and connector options for the DAQCard 6024E PCI 6023E PCI 6024E PCI 6025E and PXI 6025E devices Custom Cabling National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change device interconnections If you want to develop your own cable however use the following guidelines e For the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground reference at the source Route the analog lines separately from the digital lines e When using a cable shield use separate shields for the analog and digital parts of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals The following list gives recommended connectors that mate to the I O connector on your device PCI

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