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Lucent Technologies MN102F75K Laptop User Manual

1. P2 CORE ROM RAM P3 P6 Interrupts lt Bus Controller P5 Timers 0 3 Serial 1 TM5IA gt i F TMBIB P4 Timers 4 5 ADC A Chip Level Timer 5 TM5BC Interrupt B TM5CA 5 R c Y S Q TM5CB Block Level Figure 4 39 Block Diagram of 4x Two Phase Capture Input Using Timer 5 TM5BC contents 0 x1000 x 1FFF Interrupt Figure 4 40 Configuration Example 1 of 4x Two Phase Capture Input Using Timer 5 As figure 4 41 shows you can set different values for A and B interrupts TMSLP must be 0 0 x 1000 x FF00 x FFFF A interrupt B interrupt Figure 4 41 Configuration Example 2 of 4x Two Phase Capture Input Using Timer 5 MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 111 Panasonic Timers 16 Bit Timer Setup Examples Use the MOV instruction for this setup and only use 16 bit write operations This step stops the TM5BC count and clears both TM5BC and the S R flip flop to 0 WB To set up timer 5 1 Set the operating mode in the timer 5 mode register TMSMD Disable timer 5 counting and interrupts The up down count bit is ignored in this instance Set the TM5NLP bit to 1 to select looped counting from 0 to the value in TMSCA Select the 4x two phas
2. TM2BR Load n Reload 02 2 binary counter S 2 gt 2 Underflow Count underflow interrupt L Y Bosc 4 0 Bosc 256 1 Cascade from timer 1 2 Bosc 512 Multiplexer Figure 4 5 Timer 2 Block Diagram Data bus EN 8 8 13 3 base register TM3BR Load Reload d 03 Timer 2 binary counter B gt 3 i Underflow derflow Count 4 0 Bosc 256 Cascade from timer 2 gt 2 E Bosc 512 Multiplexer Figure 4 6 Timer 3 Block Diagram Panasonic Semiconductor Development Company 80 Panasonic 102 75 75 85 85 LSI User Manual Timers 6 Bit Timer Timing 4 4 8 Bit Timer Timing BC value Load value Time TMnIO input Figure 4 7 Event Timer Input Timing 8 Bit Timers BC value Load value Time Interrupt TMnIO input 1 TMnIO fot f output 2 Figure 4 8 Clock Output and Interval Timer Timing 8 Bit Timers MNI02H75K F75K 85K F85K LSI User Manual 81 Panasonic Panasonic Semico
3. TM4EN 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 590 JU ttt tts suttu u o 5 13 TMA o E n r3 me 31 1 1 i i1 31 i iiy Figure 4 36 Single Phase Capture Input Timing Timer 4 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 107 Panasonic Timers 16 Bit Timer Setup Examples 4 11 5 Setting Up Two Phase Capture Input Using Timer 4 In this example timer 4 is used to divide the timer 0 underflow by 65 536 and measure the number of cycles from the rising edge of the TM4IA input signal to the rising edge of the TM4IB input signal An interrupt occurs on capture B and the software calculates the number of cycles by subtracting the contents of TMnCA from the contents of TMnCB P3 CORE ROM RAM P4 P6 Interrupts Bus Controller P5 Timers 0 3 Serial TM4IA P2 Timers4 5 ADC TM4IB z A Chip Level Timer 4 Timer 0 TM4BC underflow ae TM4CA TM4IA m TQ Interrupt B R Q e s TMAIB TM4CB T Q B Block Level Figure 4 37 Block Diagram of Two Phase Ca
4. TI 4 2 Block Diagram of 8 Bit 2 2 TI 4 3 0 Block Diagram a e Eee dels poeta ERE EHE 79 4 4 Timer J Block secos ges ey Sie UH De REI E M RIPE ex 79 4 5 Timer 2 Block Dia prams u scoetesbrere9nntesertreshr b rests REN queni pb 80 4 6 Timer 3 Block Diagram x tbe s pb erbe ED des dete us 80 4 7 Event Timer Input Timing 8 Bit 81 4 8 Clock Output and Interval Timer Timing 8 Bit Timers 81 4 9 Block Diagram of Event Counter Using 0 82 4 10 Event Counter Timing Timer 0 41 83 4 11 Configuration Example of Interval Timer Using Timers 1 2 84 4 12 Block Diagram of Interval Timer Using Timers 1 2 84 4 13 Interval Timer Timing Timers 1 2 4 4 86 4 14 Block Diagram of 16 Bit 1 88 4 15 Tamer4 Block Diagram gt RI epe eh RR ope RARE RR Rc 90 4 16 Timer 5 Block Diagram o
5. 249 11 1 I OPort PInS eg srt ER UMEN ERREUR eL RI USE dea ee EO e E 251 12 1 ROM Correction Address Match and Data Registers 290 occur oed EE ELER RES Erbe I ede deese da GRE Ert es 293 13 2 Operating Modes for Devices on an uya uci EROSA 294 13 3 Control Registers for Clamping 296 13 4 Registers Settings for SDAO SCLO or SDA1 SCL1 298 13 5 SDA and SCL Waveform Characteristics 299 13 6 STA and STO Settings cx fee dure hs ee tie Pee ok tees ER dero 304 14 1 H Counter Pins aah dac RAS als soak 308 1 Register x 007E00 to 007 312 2 Register Map x OOFCOO to 313 A 3 Register Map x OOFEO0 to X OOFFFF 314 B 1 Programmable Areas in Each Programming 316 B 2 PROM Writer Hardware inops Dp DDR EU CLP a QU ee Ee depen 318 B 3 Pin Descriptions for Target Board Serial Writer Connection 321 B
6. field CPUM example 00 00 15 14 13 12 11 10 9 6 5 4 3 2 1 0 NW WDM WDM OSC DEN 1 0 ID STOP HALT 1 OSC0 Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Clearing the watchdog timer 3 Setthe NWDEN bit in CPUM to 1 then immediately reset it to 0 The watchdog timer clears to 0 when NWDEN is 1 Panasonic Semiconductor Development Company 42 102 75 75 85 85 LSI User Manual Panasonic Interrupts Interrupt Setup Examples The main program normally gen If the CPU accepts an interrupt the program branches to address x 080008 erates and branches to the inter r pyst rt address The oscillator delay timer shares the counter for the watchdog timer The oscillator delay timer is activated when the circuit exits the STOP mode so the program must clear the WDID flag to 0 prior to entering the STOP mode It must also reclear WDID after returning to NORMAL mode For further details see section 2 6 Standby Function in the MN10200 Series Linear Addressing Version LSI User Manual Overflow RST woon mmm NWDEN CPUM li WDID WDICR Interrupt servicing Clear Registers R W CPUM W CPUM W CPUM W Sequence 1 2 3 2 Figure 2 7 Timing for Watchdog Timer Interrupt Setup Example MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconduc
7. 217 8 2 IR Remote Signal Noise 2 218 8 3 Reception of 8 Bit Data with No 1 219 8 4 Reception of 8 Bit Data with 219 8 5 Conditions for Detecting Data 220 8 6 Edge Detection cis nan eee ota eee BOW SERIO HS RE A ICE DER 221 9 1 Closed Caption Decoder Block Diagram 227 9 2 Recommended ADC Configuration 228 9 3 External Connection with Both and CCD1 228 9 4 External Connection with Only CCD1 228 9 5 Clamping eoe ekbenbrebepreeseEsSentESse reepQUeesRYs eDBR 4 aep pter 229 9 6 Sync Separator Circuit Block 7 231 9 7 HSYNC Securement and 232 9 8 VS YNG Maskin gossa Rp e d ER UR E RO CR 233 9 9 Data Slice Level Calculation a o been bee Ree rede 233 9 10 Sampling Clock Timing
8. 117 307 14 3 H Counter Input Signal 74 0 308 B 1 Memory Map for Onboard Serial Programming 316 B 2 PROM Writer Hardware Setup 2 2 317 B 3 Pin Configuration for Socket 2 317 B 4 Serial Writer Programming Configuration 319 B 5 senal Writer Hardware sa s an edhe Se A eR RE ee 320 B 6 Target Board Serial Writer 1 321 B 7 Serial Writer Interface Block Diagram 322 B 8 Timing for the Serial Writer 325 B 9 Load Program Start Flow Geese coe nee Nees E epe a e ee vex c Rea ees 326 B 10 of Branch to Reset Start Routine 327 B 11 of Branch to Interrupt Start 327 B 12 EEPROM Programming 2 328 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 15 Panasonic Abou
9. 1 145 6 4 3 Multiple Channel Single Conversion Timing 145 6 4 4 Single Channel Continuous Conversion Timing 146 6 4 5 Multiple Channel Continuous Conversion Timing 146 6 5 ADC Setup Examples A hd Re ERE ICE RU E UR md da b 147 6 5 1 Setting Up Software Controlled Single Channel A D Conversion 147 6 5 2 Setting Up Hardware Controlled Intermittent Three Channel A D Conversion 148 6 6 ADC Control Registers 1 Due Neo CERES Sane ee AER Ss E 150 6 7 Caution about Analog to Digital 152 7 On Screen Display u usus oe RIS E EM E 153 7 1 Description ob ades eed RE RN RE UR quedes eni en dae dee 153 7 2 Features zc ce Dee Deep rbd epe debe Pts 153 7 3 Block Diagram ee RC d Ep EP RU 154 7 4 Power Saving Considerations in the OSD 155 7 5 OSD Oper t on ESL EEUU GEN EO 156 7 5 1 OSD Clock pee datu uay pa aede d 156 7 5 2 External Input Sync 156 7 5 3 Mul
10. 31 1 11 Power Supply s ERE abu pus uy te beat beats Pedir ess 34 1 12 1 OSC2 Connection 34 1 13 Reset Pin Connection Example 1 34 1 14 OSDXI and OSDXO Connection 2 34 1 15 Memory Space in External Extension 35 2 1 Interrupt Controller Block Diagram 22 37 2 2 Interrupt Vector Group and Class 1 38 2 3 Interrupt Servicing Time arb ts Ease pU esu ve tpe sb eb ete Pee ses 39 2 4 Block Diagram of External Pin 40 2 5 Timing for External Pin Interrupt Setup 41 2 6 Block Diagram of Watchdog Timer 0 42 2 7 Timing for Watchdog Timer Interrupt Setup 43 3 1 GPU State Changes y vd Re oben pae Xen s eie tre pen 72 3 2 CPU Clock Switch NORMAL SLOW 73 4 1 Timer Configuration
11. HNUM HSYNC Count Register x 007E06 HNUMW x 007E26 Bit 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 VBI VBI VBI VBI SB HNU HNU HNU HNU HNU E en zy IRQ IRQ IRQ IRQ IRQ E M4 M3 M2 MI MO 4 3 2 1 0 Reset 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 R W R R R RW RW RW RW RW R R R R R R R This register allows you to time the interrupt occurring after the line 21 data capture to a line other than line 21 VBIIRQ 4 0 VBI interrupt timing control In this field set the H line number from 0 to 25 for the VBI interrupt You must set this field to x 13 or higher SBFLAG Start bit detection flag 0 No start bit detected 1 Start bit detected HNUM 4 0 HSYNC count during the VBI interval This field indicates the H line number from 0 to 25 1 ACQ Capture Timing Control Register 1 x 007E08 1 ACQ1W x 007E28 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 For designs using the closed cap pos Rog pos End tay 7 7 ery tion decoder always tie the ACQI Reset 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 register to x 1312 RW R R R RW RW RW RW RW R R RW RW RW RW RW ACQ1E 4 0 Stop position for capture 1 Valid range x 00 to x 25 ACQ1S 4 0 Start position for capture 1 Valid range x 00 to x 25 CAPDATA Caption Data Ca
12. Write to TMAMD TM4EN TM4BC 0 011 2 3 4 0 1 2 3 4 01 112131 41 01 1 2 3 ak CLRBC4 1 TMCB 4 All Os 54 R4 TM4OA PEPE yi E E EE ff 2 2 54 R4 TM40A Interrupts y 3 TMCB FFFF All 1s XE x s a S4 R4 TM4OA sees Sees Interrupts Os on first cycle since S4 has not gone high yet Figure 4 30 Single Phase PWM Output Timing Timer 4 MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 99 Panasonic Timers 16 Bit Timer Setup Examples Two potential types of errors are inherent with PWM output First because of the circuit configuration direction errors can occur The output circuit is configured with T flip flops so that even if one transition is missed the 1s and Os can reverse direction Timers 4 and 5 contain an S R flip flop to prevent this type of error Second if the duty cycle changes dynamically which often happens in PWM output the PWM waveform may skip a pulse see the single buffering section of figure 4 31 below To prevent these misses timers 4 and 5 provide a double buffer mode In this mode no matte
13. 70327 100 kHz x 06E 50 kHz x 039 89 6 kHz x 08C 40 kHz x 041 80 kHz x OBE 30 kHz x 04C 69 8 kHz x 122 20 kHz x 05A 60 kHz x 24E 10 kHz I2CBRST 2 Bus Reset Register X 007E48 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BRST Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R W R R R R R R R R R R R R W BRST Bus reset When a serious bus error occurs this bit can be set to 0 forcing the clock line low and resetting the bus This function works in all C modes After a forced reset the microcontroller is in slave receiver mode This reset does not change the contents of I2ZCM YAD and I2CCLK registers 0 Force bus to reset 1 Steady state I2CBSTS 2 Bus Status Register X 007E4A Bit 15 14 13 12 T1 10 9 8 7 6 5 4 3 2 1 0 SDAS 5 5 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R I2CBSTS is a two bit read only register that monitors the status of the Pc bus SDAS SDA data line status This bit monitors the state of the IC data line SDA SCLS SCL clock line status This bit monitors the state of the I C clock line SCL Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 306 Panasonic H Counter Description 14 H Counter 14 1 Description The MN102H75K 85K contains two H counter circuits that can be used to count the HSYNC
14. Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 Write a dummy data word of any value to In double buffer mode TM4CA is compared to TM4CAX The contents of TM4CA are loaded to TM4CAX when TMABC TM4CAX However since TM4CAX is undefined or x 0000 before this operation starts this initial dummy write prevents timing errors 5 Wirite a dummy data word of any value to TMACBX In double buffer mode TMACB is compared to TMACBX The contents of TMACB are loaded to TMACBX when TMABC TMACBX However since TMACBX is undefined or x 0000 before this operation starts this initial dummy write prevents timing errors 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 103 Panasonic Timers 16 Bit Timer Setup Examples 6 Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0 This enables TM4BC and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 7 Set TM4NLD and TM4EN to 1 This starts the timer Counting begins at the start of the next cycle Timer 4 can output a two phase PWM signal with any phase difference You must select up counting Timer 4 does not operate in STOP mode when Bosc is off If you use an external clock it must be synchronized to Bosc In this procedure you set the cycle
15. ADM2ICH Address 2 Match Interrupt Control Register High x O0FC7B Bit 7 6 5 4 3 2 1 0 ADM2 IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W ADM2ICH enables address match 2 interrupts It is an 8 bit access regis ter Use the MOVB instruction to access it The priority level for address match 2 interrupts is written to the ADM3LV 2 0 field of the ADM3ICH register ADMa2IE Address match 2 interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 62 Panasonic Interrupts Interrupt Control Registers ADM1ICL Address 1 Match Interrupt Control Register Low x 00FC7C Bit 7 6 4 3 2 1 0 ADMI ADMI p zm gt E ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R ADMIICL detects and requests address match 1 interrupts It is 8 bit access register Use the MOVB instruction to access it Address match 1 interrupt request flag 0 No interrupt requested Interrupt requested ADM1ID Address match 1 interrupt detect flag 0 Interrupt undetected Interrupt detected ADMt1ICH Address 1 Match Interrupt Control Register High x 00FC7D Bit 7 6 5 4 3 2 1 0 ADMI IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W ADMIICH enables address match 1 interrupts It is an 8 bit access register Use the MOVB ins
16. 173 7 10 setting Up the OSD 22 225 RR RR RA ERR EM 178 7 10 1 Setting Up the OSD Display 178 7 10 2 Text ayer EUncHons c uo usd resonet VN RN PEE PE 184 7 10 3 Display Siessen E E ARE Ted ub t decet dipende EE tp 187 7 10 4 Setting Up the OSD Display Position 189 7 11 and Interrupt Timing ces eee RE RE reae ee RR RR E RR 191 7 12 Selecting the OSD Dot Clock 193 7 13 Controlling the Shuttering 194 7 13 1 Controlling the Shuttered Area 7 194 7 13 2 Controlling Shutter 1 12 1 196 MN102H75K F75K LSI User Manual Panasonic Semiconductor Development Company 5 Panasonic Contents 7 13 3 Controlling Shuttering 198 7 13 4 Controlling Line 1 4 22 200 7 14 Field Detection Circuit am ves eee He kes hon DE NO ee Ae pode e 201 7 14 1 Block Diagram lt aaa Waku eed 201 7 14 2 D scriptionz l u usq
17. HCOUNT HSYNC count x 007F0C Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HCNT HCNT HCNT HCNT HCNT HCNT HCNT HCNT HCNT HCNT 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register holds the HS YNC count which indicates the vertical display position It is cleared to 0 on the leading edge of VSYNC MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 207 Panasonic 5 Display OSD Registers A write to the OSD bit of OSD1 takes effect on the next leading edge of VSYNC If you are turning the OSD on the OSD starts operating on the next VSYNC after the program writes a 1 to the OSD bit If you are turning the OSD off the OSD stops operating on the next VSYNC after the program writes a 0 to the OSD bit To turn off the OSD block to save power 1 Write a 0 to 050 0501 bit 10 2 Wait for the next VSYNC input 3 Write a 0 to OSDPOFF PONTO bit 7 turning the clock off If you turn the clock off before the VSYNC input power usage may not drop or the microcontroller may halt In using LC blocking oscillation the power comsumption becomes large To reduce it select another oscillation In case of of useing OSDX clock both LC blocking oscilation and external clock to prevent the current flow set OSDXI OSDXO terminal to port function P45 P46 and
18. 7 235 9 11 Caption Data Capture 2 2 235 9 12 SLSF SLHD Multiplexing 2122 224 5 238 9 13 Backporch Position 244 9 14 Sync Separator Level Re esa WES GIN ee eee eet 244 9 15 BSPand PSP Multipleiing us xeu ehe px RR RR REDE 245 10 1 PWM Output Waveform neben ESPERE Grd ae oe dpe HY ME eae ee 249 10 2 PWM Block Dia pram oer RUE HEUS 250 11 1 0 714 252 11 2 to PO7 ADINA 0 253 11 3 P10 ADINS IRQI P11 ADING IRQ2 P12 ADIN7 IRQ3 Port 1 254 11 4 P13Y ADINS WDOUT and P14 ADIN9 STOP Port 1 255 11 5 P15 ADIN10 PWMO P16 ADINII PWMI 1 256 11 6 2 Port 1 P20 PWM3 P21 PWMA P22 PWMS and P23 PWM6 Port 2 257 11 7 P2A TMAIC SBT I u sqa EGER ER 258 11 8 P27 TMOIO Port 932 lt
19. b 00 b 01 b 10 b 11 CHSZ 1 0 t t gt 16 32 b 00 T x1 b 01 x2 b 10 4 72 b 11 x6 108 CVSZ 1 0 Y L The settings shown are for interlaced displays In progressive displays the vertical size settings CVSZ 1 0 are as follows 01 1x 10 2x 11 3x 00 setting is reserved In addition in closed caption mode only the b 00 b 01 and b 11 m Settings are available for CVSZ 1 0 The b 10 setting is reserved Figure 7 28 Character Size Combinations Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 188 Panasonic 5 Display Setting Up the OSD When setting up the horizontal position you must allow at least 0 8 us between the end of a line and the leading edge of HSYNC or the display will flicker 7 10 4 Setting Up the OSD Display Position This section describes how to control the positioning of the OSD To set up the horizontal position Cursor Write the horizontal position of the
20. 0 129 5 6 Synchronous Serial Reception Timing 1 0 130 5 7 UART Transmission Timing 2 12 2 130 5 8 UART Reception TMINE gis RORIS ER C E E T SS f 130 5 9 Block Diagram of UART Transmission Using Serial Interface 0 131 5 10 UART Transmission Timing Serial Interface 0 1 133 5 11 Block Diagram of Serial Interface Clock 135 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 12 Panasonic List of Figures 5 12 Serial Interface Clock 5554 I EE AR 136 5 13 Master Transmitter Timing in PC Mode with ACK esos eee s da esee 138 5 14 Master Receiver Timing in Mode with AC KR e ete rete te tete eiTe 139 6 1 ADG Architecture z c ecl a e e UR nog boc ORI Re UR ce eed 143 6 2 ADE Block Diagram oce RUP pe RP Ee ENDE 144 6 3 AIC isd eet eee RS EU ent Te eui 144 6 4 Single Channel Single Conversion 1 145 6 5 Multiple Channel Single Conversion Timing 145 6 6 Single Channel Continuous Conver
21. Lost interrupt causing a PWM output error Figure 4 34 Two Phase PWM Output Timing with Dynamic Duty Changes Timer 4 MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 105 Panasonic Timers 16 Bit Timer Setup Examples 4 11 4 Setting Up a Single Phase Capture Input Using Timer 4 In this example timer 4 18 used to divide Bosc 4 by 65 536 and measure how long the TM4IA input signal stays high interrupt occurs on capture and the software calculates the number of cycles by subtracting the contents of TMnCA from the contents of TMnCB PEE cont ME Rom RaM HPP P6 Interrupts Bus Controller P5 Timers 0 3 Serial I Fs TMA4IA P2 Timers4 5 ADC A Chip Level Timer 4 Bosc 4 TM4BC gt TM4IA gt T 4 5 5 Interrupt i s Q O i TM4CB T Q B Block Level Figure 4 35 Block Diagram of Single Phase Capture Input Using Timer 4 To set up timer 4 1 Setthe operating mode in the timer 4 mode register TM4MD Disable timer 1 4 counting and interrupts Select up counting Set the TM4NLP bit to 0 to select looped counting from 0 to x FFFF Select Bosc 4 as the clock source Use the MOV i
22. P5 CORE ROM RAM P1 IRQO Interrupts Bus Controller P3 P2 Timers 0 5 Serial 1 ADC Figure 2 4 Block Diagram of External Pin Interrupt Enabling external interrupt 0 1 Setthe interrupt conditions for the IRQO 00 pin For this example set the IQOTG 1 0 bits of EXTMD to b 10 negative edge triggered interrupt EXTMD example x 00FCF8 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IQSTG IQ5TG IQ4TG IQ4TG IQ3TG IQ3TG IQ2TG IQ2TG IQ1 TG IQ1ITG IQ0TG IQ0TG 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Setting 0 0 0 0 0 0 0 0 0 0 1 0 2 Cancelany existing interrupt requests and enable IRQO interrupts To do this set the IQOIR bit of IQOICL to 0 set the IQOLV 2 0 bits of IQOICH to b 101 priority level 5 and set the IQOIE bit to 1 IQOICL example x 00FC48 Bit 7 6 5 4 3 2 1 0 Setting 0 0 0 0 0 0 0 0 IQ0ICH example x 00FC49 Bit 7 6 5 4 3 2 1 0 10012 IQOLv1 1001 0 100 Setting 0 1 0 1 0 0 0 1 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 40 Panasonic Interrupts Interrupt Setup Examples The main program normally gen erates and branches to the inter rupt start address During the interrupt service rou tine prevent the CPU fro
23. Rest 1 1 1 0 1 1 1 0 i 1 T 0 1 1 1 0 RA RA RA RA RW RA RA RW RW RA RA RM EW 33 30 EW 23 20 EW 13 10 EW 03 00 These fields contain the wait settings for external memory spaces 3 2 1 and O respectively One wait corresponds to one instruction cycle When the external oscillator is 4 MHz one wait is 83 ns The OSD VBIO VBII I2C IR remote signal receiver and H counter blocks apply to external memory space 0 Table 1 4 Wait Count Settings EW n3 n0 Setting Wait Count Cycles 0000 0 0 10 000 Reserved 0010 10 20 0011 Reserved 0100 20 30 010 Reserved 0110 30 40 011 Reserved 1000 40 50 100 Reserved 1010 50 60 011 Reserved 100 60 70 101 Reserved 1110 70 80 11 Reserved MEMMD1 Memory Mode Register 1 x O0FF82 Bi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EB31 EB32 21 20 11 10 EBO1 00 BRS1 BRS0 2 1 1 DW 0 Rest 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 RW RA RW RA RA R RA RW RW RW RA RW RW RA RA RA Write 05 to bits 15 to 2 IOW 1 0 Wait setting for internal I O space 00 1 wait 01 Reserved 10 2 waits 11 3 waits Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 36 Panasonic Interrupts Description 2 Interr
24. E 7 E ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R TM4UDICL detects and requests timer 4 underflow interrupts It is an 8 bit access register Use the MOVB instruction to access it TM4UDIR Timer 4 underflow interrupt request flag 0 No interrupt requested 1 Interrupt requested TM4UDID Timer 4 underflow interrupt detect flag 0 Interrupt undetected 1 Interrupt detected TM4UDICH Timer 4 Underflow Interrupt Control Register High x 00FC65 Bit 7 6 5 4 3 2 1 0 TM4UD IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W TM4UDICH enables timer 4 underflow interrupts It is 8 bit access regis ter Use the MOVB instruction to access it The priority level for timer 4 underflow interrupts is written to the TMACBLV 2 0 field of TM4CBICH register TM4UDIE Timer 4 underflow interrupt enable flag 0 Disable 1 Enable VBIICL VBI 1 Interrupt Control Register Low x 00FC66 Bit 7 6 5 4 3 2 1 0 p VBI VBI IR ID Reset 0 0 0 0 0 0 R W R R R R W R R R R VBIICL detects and requests VBI 1 interrupts It is an 8 bit access register Use the MOVB instruction to access it VBIIR VBI 1 interrupt request flag 0 No interrupt requested 1 Interrupt requested VBIID VBI 1 interrupt detect flag 0 Interrupt undetected 1 Interrupt detected 102 75 75 85 85 LSI User Manual Panasonic Sem
25. IQ2ICL External Interrupt 2 Interrupt Control Register Low x 00FC50 Bit 7 6 gt 4 3 2 1 0 IQ2IR IQ2ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R IQ2ICL requests and verifies interrupt requests for external interrupt 2 It is an 8 bit access register Use the MOVB instruction to access it IQ2IR External interrupt 2 interrupt request flag 0 No interrupt requested Interrupt requested IQ21D External interrupt 2 interrupt detect flag 0 Interrupt undetected Interrupt detected IQ2ICH External Interrupt 2 Interrupt Control Register High x 00FC51 Bit 7 6 5 4 3 2 1 0 IQLV2 IQUVI 021 0 IQ2IE Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R R R R W IQ2ICH sets the priority level for and enables external interrupt 2 It is an 8 bit access register Use the MOVB instruction to access it IQ2LV 2 0 External interrupt 2 interrupt priority level Sets the priority from 0 to 6 IQ2IE External interrupt 2 interrupt enable flag 0 Disable 1 Enable IQ3ICL External Interrupt 3 Interrupt Control Register Low x 00FC52 Bit 7 6 5 4 3 2 1 0 1031 Reset 0 0 0 0 0 0 R W R R R R W R R R R IQ3ICL requests and verifies interrupt requests for external interrupt 3 It is 8 bit access register Use the MOVB instruction to access it IQ3IR External interrupt
26. 0 P47 1 HSYNC 7 lt SEN 0 Port input 1 Port output P4DIR7 0 Port low output 1 Port high output Pin P4OUT7 P47 HSYNC Schmidt trigger P4IN7 lt HSYNC lt Figure 11 21 P47 HSYNC Port 4 MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 271 Panasonic Ports I O Port Circuit Diagrams off 1 Pullup on o P5PUPO 0 50 SYSCLK CER P5MDO Port input Port output mma Port low output Port high output P5OUTO 0 N SYSCLK or gt divided SYSCLK output X P50 SYSCLK P5INO Figure 11 22 P50 SYSCLK Port 5 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 272 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on P5PUP1 0 P51 v e lt pese 0 Port input 1 Port output P5DIR1 0 Port low output 1 Port high output M Pin r lt 1 P51 YS P5OUT1 YSOUT P5
27. 220 8 2 Long and Short Data Identification llle 220 8 3 Leader Detection Conditions O t 221 8 4 Differences between SLOW and NORMAL 222 102 75 75 85 85 1 81 User Manual Panasonic Semiconductor Development Company 9 Panasonic List of Tables 8 5 IR Remote Signal Receiver Registers 223 8 6 HEAMA and 5 6 Bit Data Pulse 1 6 223 9 1 Pins Used for CCDO and CCDL 5 5 n rette et rer ek ee Nome b tiere 227 9 2 Caption decoder register setting cs ie e Re RR Red 229 9 3 Clamping Reference and Compare Levels 229 9 4 Current Level Control ns rane ue usu RORIS 230 9 5 Control Registers for Clamping 2 230 9 6 Control Registers for Sync Separator 232 9 7 Control Registers for Data 8 234 9 8 Control Registers for Controller and Sampling 234 9 9 Closed Caption Decoder Register cli eR Red ERR ERR RET ER E 236 10 1 Register Settings for Internal PWM
28. 1 1 5 1 T T T T T it TM5CB 1000 TM5BC 0000 1FFF 1FFE 1FFD 1 1 0000 0001 OFFF 1000 1001 4 Y Y Y Y Y Y Y TM5IB Interrupts x x x x x x y x j Figure 4 46 1x Two Phase Encoder Input Timing Timer 5 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 116 Panasonic Timers 16 Bit Timer Setup Examples 4 11 8 Setting Up a One Shot Pulse Output Using Timer 5 In this example timer 5 outputs a one shot pulse The pulse width is two clock cycles P2 CORE ROM RAM P3 P6 Interrupts Bus Controller P5 Timers 0 3 Serial TM5OA lt i TMBIB P4 Timers 4 5 ADC A Chip Level Timer 5 Bosc 4 gt TM5BC m TM5CA _ TM5CAX 5 R TM5IB gt 5 s Q TM50A 5 TM5CBX B Block Level Figure 4 47 Block Diagram of One Shot Pulse Output Using Timer 5 set up the output port Set the PAMD2 bit of the port 4 output mode register PAMD to 1 selecting the TMSIOA pin and set the PADIR2 bit of the port 4 I O control register PADIR to 1 selecting output direction This step selects the TM5OA pin
29. Character V position control ID code Pee V size Interrupt V display start position 1 H scan line resolution 1024 steps Graphics layer 15 14 13 12 N 10 9 8 7 6 5 4 3 2 1 0 GTC 0 GCBF GCB3 GCB2 GCB0 GPRT GTC8 GTC7 GTC6 GTC5 GTC4 GTC3 GTC2 GTC0 Graphic tile code ID code a Number of blank tile repetitions Graphic address 512 tiles GHP 1 L GHSZI GHSZ0 GSHT GHP9 GHP8 GHP7 GHP6 GHP5 GHP4 GHP3 GHP2 GHPI GHPO Graphics H position control ID code H size Shutter H display start position 1 dot resolution 1024 steps GVP 1 1 GLAST 6 571 GVSZO GINT GVP9 GVP8 GVP7 GVP6 GVP5 GVP4 GVP3 GVP2 GVPI Graphics V position control ID code rs V size Interrupt V display start position 1 H scan line resolution 1024 steps Wi Don t care bits B Text Layer CC Character Code ID Code 00 CCH 9 0 Specifies the address of one of 1024 characters stored in the ROM COL Color Control Code Normal Mode ID Code 10 BSHAD 1 0 Specifies shadowing of the character box for a 3D button effect 00 Disable 01 Disable 10 Upper left white and lower right black shadows 11 Upper left black and lower right white shadows CSHAD Specifies character shadowing for a 3D effect 0 Disable 1 Enable FRAME Specifies character outlining black 0 Disable 1 Enable MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development
30. Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W PSMD is an 8 bit access register P5MD7 P57 output switch To use SBTO as an input pin set this field to 0 and set the PSDIR7 bit to 0 0 57 1 SBTO P5MD6 56 output switch If you set this bit to 1 select SBIO or SBDO in the bit 10 of PCNTO 0 P56 1 SBIO SBDO P5MD5 P55 output switch 0 P55 1 SBOO P5MD4 P54 function switch 0 PSA IRQS VSYNC 1 IRQ5 VSYNC P5MD3 This bit exists but contains no function P5MD2 P52 output switch 0 P52 IRQ4 VI0 1 IRQ4 VI0 P5MD1 P51 output switch 0 P51 1 YS P5MDO P50 output switch If you set this bit to 1 set the SYSCLK frequency in bits 15 14 of PCNTO 0 P50 1 SYSCLK divided SYSCLK output P6MD Port 6 Output Mode Register x 00FFFC Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 P6MDI P6MD0 Reset 0 0 0 0 0 0 0 0 R W R R R R R R R W R W P6MD is an 8 bit access register P6MD1 P61 function switch 0 P61 1 SCLO P6MDO P60 function switch 0 P60 1 SDAO Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 284 Panasonic Ports I O Port Control Registers PCNTO Port Control Register 0 x 00FF90 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCLK SCLK OD OD SIF SIF 2 OSD PLL ADCO HCNT VBIO Fi FO ASCII 5 0 SELI SELO SELI SELO POFF
31. 0 1 Port output ry P2DIR4 L dD 0 Port low output Pin 1 Port high output 9 P2OUT4 q SBT1 output 5 D 0 Push pull 1 Open drain 2 mode ODASCI1 P2IN4 lt di TMAIC input Schmidt trigger inpu SBT1 input lt Figure 11 7 P24 TM4IC SBT1 Port 2 i To use as SBT1 set P MD8 and P2MD9 to 0 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 258 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on lt gt P2PUP7 0 27 1 TM0IO P2MD14 0 1 output P2DIR7 0 Port low output 1 Port high output 200 7 0 Oo Tl M Pin HX x TMOIO output gt P2IN7 lt TMOIO input amp Figure 11 8 P27 TMOIO Port 2 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 259 Panasonic Ports 1 0 Port Circuit Diagrams Pin 0 Pullup off 1 Pull o P3PUPn P4PUPn 0 DAC output 1 Digital output OSD1 bp0 lt gt 0 P35 P36 P37 P40 1 DAROUT R DAGOUT G DABOUT B DAYMOUT YM P4MDn 0 Port input 1 Por
32. TM5CB Block Level Figure 4 43 Block Diagram of 1x Two Phase Capture Input Using Timer 5 TM5BC contents 0 x1000 x 1FFF Interrupt Figure 4 44 Configuration Example 1 of 1x Two Phase Capture Input Using Timer 5 As figure 4 45 shows you can set different values for A and B interrupts TMSLP must be 0 0 x 1000 x FF00 x FFFF A interrupt B interrupt Figure 4 45 Configuration Example 2 of 1x Two Phase Capture Input Using Timer 5 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 114 Panasonic Timers 16 Bit Timer Setup Examples To set up timer 5 1 Set the operating mode in the timer 5 mode register TM5MD Disable timer 1 5 counting and interrupts up down count bit is ignored in this instance Set the TM5NLP bit to 1 to select looped counting from 0 to the value in Use the MOV instruction for this TMSCA Select the 1x two phase encoder as the clock source setup and only use 16 bit write operations TM5MD example x 00FE90 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 This step stops the 5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 count and clears both 5 EN NLD m x UDI UDO ONE MD1 ECLR LP S2 81 50 and the S R flip flop to 0 Setting 0 0 0 0 0 0 0 0 0 0 0 1 lord 1 0 1
33. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW R W RW RW RW RW RW RW RW RW ROMCEN15 Address 15 ROM correction enable 0 Disable 1 Enable ROMCEN14 Address 14 ROM correction enable 0 Disable 1 Enable ROMCEN13 Address 13 ROM correction enable 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 290 Panasonic ROM Correction ROM Correction Control Registers ROMCEN 12 Address 12 ROM correction enable 0 Disable 1 Enable ROMCEN 1 1 Address 11 ROM correction enable 0 Disable 1 Enable ROMCEN 10 Address 10 ROM correction enable 0 Disable 1 Enable ROMCENS Address 9 ROM correction enable 0 Disable 1 Enable ROMCENS Address 8 ROM correction enable 0 Disable 1 Enable ROMCEN7 Address 7 ROM correction enable 0 Disable 1 Enable ROMCENE Address 6 ROM correction enable 0 Disable 1 Enable ROMCEN5 Address 5 ROM correction enable 0 Disable 1 Enable ROMCEN4 Address 4 ROM correction enable 0 Disable 1 Enable ROMCENS Address 3ROM correction enable 0 Disable 1 Enable ROMCEN2 Address 2 ROM correction enable 0 Disable 1 Enable ROMCEN 1 Address 1 ROM correction enable 0 Disable 1 Enable ROMCENO Address 0 ROM correction enable 0 Disable 1 Enable MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 291 Panasonic ROM Correction RO
34. 12 11 10 CB9 CB8 CB7 CB6 CB5 4 2 CB0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W RW RW RW RW RW RW R W RW RW RW RW RW RW RW RW MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 125 Panasonic Timers 16 Bit Timer Control Registers Reset R W TM4MD TM5MD Timer n Mode Register x 00FE80 x 00FE90 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn EN UDI UDO ONE MDI ECLR LP ASEL S2 51 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R RW RW RW RW RW RW RW RW RW RW RW RW TMnBC count 0 Disable 1 Enable TMnNLD T flip flop and S R flip flop operation select 0 Set all to 0 initialize 1 Operate all TMnUD 1 0 Timer n up down counter mode select Ignored when two phase encoding is selected 00 Up counter 01 Down counter 10 Up when TMnIOA is high down when low 11 Up when TMnIOB is high down when low External trigger enable for start count 0 Disable 1 Start count at falling edge of TMnIOB TMnONE Counter operating mode select 0 Repeat except with PWM output 1 One shot pulse counter stops on the next clock after TMnBC TMnCA TMnMD 1 0 TMn
35. 223 9 Closed Caption 227 9 1 Description oath Ea td au ust e ae pls Me bee UU rtp Noy 227 9 2 Block EPI 227 9 3 Functional Description 222525222 EE E 228 9 3 1 Analog to Digital Converter 4 228 9 3 2 Cl mping Circuit Cree Rer CERE CRDI e keke aan E NUR 229 9 3 3 Sync Separator Circuit sessile eee eso repe e GE Ea EE ere wu Q 230 9 3 3 1 HSYNG S parator men E RE pe ERROR pp E pr eS 232 9 3 3 2 ustusqa xU niv dae 233 9 3 3 3 Field Detection 233 9 3 4 Data 5licer oio te vp US owes otal i A hue bes tqq pu Da cbe 233 9 3 5 Controller and Sampling 234 9 3 5 1 CRI Detection for Sampling Clock 235 9 3 5 2 Data Capture Control ecseri MEE E e Re eR Ree Ren 235 9 4 Closed Caption Decoder Registers 236 10 Pulse Width 249 10 1 Description RR E wee ae CHE IR AE Eod Ss 249 10 2 Block
36. AMCHILA AMS AMCHIL9 AMCHIL8 registers 00FD30 AMCHILF AMC AMCHILE AMCHILD AMCHILC 00 040 DAT DAT2 DAT DATO 00FD50 DAT DAT DATS DATA correction data registers 00FD60 DATB DATA DAT bars 00FD70 DATF DATE DATD DATO 00FD80 5 SC1CTR wes Iste erm the SCOCTR Serial interface registers 00FD90 00FDA0 00FDBO 00FDCO 00FDDO 00FDEO 00FDFO 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 313 Panasonic Register Table A 3 Register Map 00 00 to x 00FFFF 20 4 LSBs Description MSBs F E D C B A 9 8 7 6 5 4 3 2 1 0 TM2 TM1 00 00 BC BC BC TM3 TM2 TM1 SUME BR BR IBR ES 8 bit timer registers DOFE20 TM2 TM1 9 MD MD MD MD 00 0 TM8TST test register 00 40 00 50 00 60 00 70 TM4CBX TM4CAX 00 80 ML x TM4BC TM4MD 16 bit timer 4 registers 5 5 00 90 NOE TMSCB 5 5 TM5MD 16 bit timer 5 registers 00 OOFEBO OOFECO OOFEDO OOFEEO OOFEFO 00FF00 AN3BUF AN2BUF AN1BUF ANOBUF ANTS ANCTR test register ADC registers 00 10 AN11BUF AN10BUF AN9BUF AN8BUF AN7BUF AN6BUF ANBBU
37. 08 07 02 03 ie eres e 06 Prec S 01 05 dads dai 02 DEBEAT 04 01 03 im 01 PP Sa a hae 02 Z a as Sa a aa a ees 00 01 00 Ee 00 See T re rene Si ae 00 36 bytes 72bytes 108 bytes 144 bytes 4 4 4 See fig 7 19 See fig 7 18 Seefig 7 17 See fig 7 16 Figure 7 12 Graphics ROM in the Four Color Modes 16W x 18H Tiles 102 75 75 85 85 LSI User Manual 175 Panasonic Panasonic Semiconductor Development Company 5 Display ROMEND 7F Line 1 data Line 1 ROMEND 77 Graphics tile heet 4J lt Line 2 Line 2 data 16 col d gt Line 3 ROMEND 70 16 color mode heet 3 ROMEND 6F Line 3 data heet 2 POMEND 67 ROMEND 7 Sheet 1 bits 7 to 0 EE ROMEND 6 Sheet 1 bits 15 to 8 N ROMEND 5 Sheet 2 bits 7100 1 dot 4 bits i ROMEND 4 Sheet 2 bits 15 to 8 16 colors ROMEND 10 ROMEND 3 Sheet 3 bits 7 to 0 ROMEND OF Line 15 data i ROMEND 2 Sheet 3 bits 15108 4 ROMEND 07 T ROMEND 1 Sheet4bits7t00 Bit 15 Bit 0 romeno Line 16 data 8 bytes powenp Sheet 4 bits 1510 8 1 byte Figure 7 13 Graphics Organization 16 Color Mode 16W x 16 Tiles ROMEND 5F ROMEND 5A Line 1 data ROMEN
38. E SET HUP deep Salk sins 35 1 7 1 Description scettr dE tat Ba get ete os e aco ee ER PR RUE ceu eoe 35 1 7 2 Bus Interface Control 36 2 Intertupts yy u rule XAR RUEDA EMI 37 2 1 Description aus qa yau eee DRE EE IUNGERE RIBUS 37 2 2 Interrupt Setup 1 14 40 2 24 Setting Up an External Pin 1 40 2 2 2 Setting Up a Watchdog Timer 42 2 3 Interrupt Control Registers vz hose edb eee Wes e ES p eR Rex s 44 3 Low Power Modes 72 3 1 CPU Bes ee M ea RES C S PI PS 72 3 1 1 D scription zl q ERES RUE He Ce A Sits 72 3 1 2 Exiting from SLOW Mode to NORMAL 73 3 1 3 Notes on Invoking and Exiting STOP and HALT 74 3 2 Turning Individual Functions On and 75 3 3 CPU Control Register o conor ORE IDEA EIUS ANGE GRIS RO EIU ID ER 76 4 Ulm TM ERICH 77 4 1 8 Bit Timer Description osse de RR RUE EUR ER TI 4 2 8 Bit Timer Featu
39. Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 Set the phase difference for timer 4 For a 2 cycle phase difference write 0001 to timer 4 compare capture register B TM4CB The valid range is 1 lt lt the TMACA value TMACB example x 00FE88 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM4 TM4 4 TM4 4 4 4 4 4 TM4 4 4 TM4 4 4 TM4 15 4 12 CB11 0 CB9 CB8 CB7 6 5 CB4 2 CBO Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 Setthe TMANLD bit of the TM4MD register to 1 and the TM4EN bit to 0 This enables and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 5 Set TMANLD and TMAEN to 1 This starts the timer Counting begins at the start of the next cycle Toenable timer 4 capture interrupts Cancel all existing interrupt requests Next set the interrupt priority level in the TMACBLV 2 0 bits of the TM4CBICH register levels 0 to 6 set the TMACBIE bit to 1 set the TMACBIR bit of TMACBICL to 0 set the TMACAIE bit of TMACAICH to 1 and set the TMACAIR bit of TMACAICL to 0 From this point On an interrupt request is generated whenever a timer 4 capture A or capture B event
40. x 0x82010 8bytes Branch instruction to reset service routine X 0x82017 Ex JMP 82100 0 82018 8bytes Branch instruction to interrupt service routine x 0x8201F Ex JMP 82200 x 0x82020 248 User program area x 0xBFFFF Serial writer load program area This kilobyte of ROM starting at address x 0x80000 holds the load program for the serial writer This area is write protected in the hardware Panasonic provides the load program Fixed user program area These 7 kilobytes of ROM starting at address x 0x80400 hold the fixed user program This area is write protected in the hardware You can program this area with a parallel writer Security code This byte holds the password for the serial writer Enter an 8 character ASCII code in this space B Reserved area Do not write to this area Branch instruction to reset service routine Normally reset servicing starts at address x 0x80000 but the soft branch instruction in the serial writer load program branches to x 0x82010 This address must hold a JMP instruction pointing to the real start address for the reset service routine MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 323 Panasonic MN102HF75K Flash Version Using the Onboard Serial Programming Mode Branch instruction to interrupt service routine Normally interrupt servicing starts at addr
41. 7 15 OSD Registers registers in OSD block cannot be written by byte by word only Read by byte is possible CROMEND Text ROM End Address Register x 007F00 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 17 16 15 14 12 10 9 8 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R RW RW RW RW RW RW RW RW RW RW A 17 8 holds the programmable portion of the text ROM end address The low order 8 bits of the address are always and the high order 6 bits are always b 000010 The available address range is x 0800FF to X OBFFFF with a programmable range from x 000 to x 3FF A17 A8 0000 10 11111 1111 Fixed Programmable Fixed 0800 0000 1000 0000 0000 1111 1111 OBFFFF 0000 1011 1111 111111111 1111 GROMEND Graphics ROM End Address Register x 007F02 Bi 15 14 13 10 9 8 7 6 5 4 3 2 1 0 17 Alo 15 14 AI3 12 AIO 9 A8 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R RW RW RW RW RW RW RW RW RW RW A 17 8 holds the programmable portion of the graphics ROM end address The low order 8 bits of the address are always x FF and the high order 6 bits are always b 000010 The available address range is x 0800FF to x OBFFFF with a programmable range from x 000
42. Figure 11 16 P30 CLH and P33 CLL Port 3 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 267 Panasonic Ports I O Port Circuit Diagrams 2 Pullup off 1 Pullup on P3PUP4 p P3MD4 x Port input Port output o Port low output Port high output Sn P3OUT4 X P34 VREF P3IN4 lt VREF lt Figure 11 17 P34 VREF Port 3 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 268 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on lt gt P4PUPn 0 Port input 1 Port output T Ew 0 P41 P42 P43 1 TM1IO TMSIOA TMBSIOB 0 Port low output Pin 1 Port high output 0 e X PA4OUTn M U 5 gt X 1 TIT TM11O output 5 output TM5IOB output P4INn TM1IO input TM5IOA input lt TM5IOB output HIO Figure 11 18 P41 TM11O P42 TM5IOA and 43 5 Port 4 0 Port input 1 Port output w 0 P44 1 TM5IC HI1 P4MD4 moe Lx Z Pin 0 Port low output gt x 1 Port high output lt P4OUT4 P44
43. SE Pu sb 259 11 9 P35 DAROUT R P36 DAGOUT G P37 DABOUT B Port 3 and P40 DAYMOUT YM Port 4 260 11 10 P25 TMAIOB SBII SBDI and P26 TMAIOA SBOI 2 261 1111 P55andP56 Pont S Lecture eer e e en ee Ea enin 262 11 12 PSZ SBTO Port bate UNE POP thu 263 11 13 02 5 Port 0 P61 SCLO 6 264 11 14 POI SDAI Port 1 and P60 SDAO 6 265 11 15 P31 CVBS0 and P32 CVBS1 3 266 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 14 Panasonic List of Figures 11 162 P30 CLHand P33 CLIL sos pede tac 267 11 177 PSA VREE Port tet iade LU 268 11 18 PAI TMIIO P42 TMSIOA and P43 TMSIOB HIO 4 269 11 19 PAA TMSIC HIL Port Bice ecco hls ak pee eoe Rupe 269 11 20 P45 OSDXO and PA6 OSDXI Port 4 sees 270 3PAWIEISY NE ore edu edades da E e 271 11 22 P30 SYSCEK Port 5 e obe Scottie abusi Ub Ep EE E E ORC 272 11 23 e Deere retos e eu ost 273 11 24 JP52 IRQA VIO Port 5
44. s baka gets usa E p EE M ER 274 11 25 PS3 RST S saa e eet apana a eec od RR e e Noe Radon s 275 11 26 5 5 55 create ste 276 12 1 Area Schematic 288 12 2 ROM Correction cs eL eee Needs tee aie a s R ee ERR 288 12 3 ROM Correction Block 2 289 13 1 Example of PC Bus Application 2 eieerephebeLteretl6ur eue epe uda eda etd 293 13 2 Connection of Two Microcontrollers to the PC 294 13 3 Bus Interface Op ration o ioco es UD Eb bete bt td bl eR NE ET 295 13 4 Bus Controller Block Diagram REM RP ES e DUE GE 296 13 5 Pin Control Circuit for the IC Bus Controller 298 13 6 SDA and SCL Waveforms gt IRE DR We b EIE Ier pr e ex 299 13 7 Waveform for Master Transmitter Transitioning to Master 301 13 8 Waveform for Slave Receiver Transitioning to Slave 303 14 1 H Counter Block Diagram ua anan EUER RUE RES pu Ee E eR eed 307 14 2 Counter Operation Example
45. 0 P54 IRQ5 1 IRQS VSYNC CT P5MD4 D 0 Port input 1 Port output P5DIR4 0 Port low output Pin 1 Port high output P5OUT4 e T P54 IRQ5 VSYNC P5IN4 lt Schmidt trigger IRQ5 lt VSYNC Figure 11 26 P54 IRQ5 VSYNC Port 5 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 276 Panasonic Ports I O Port Control Registers activate the pullup resis tors when the pins are in output mode This will cause incorrect output voltage levels and increase power and current con sumption 1 Writing 0 to causes reset to occur 11 3 1 0 Port Control Registers POPUP P5PUP Ports 0 5 Pullup Resistor Control Registers x O0FFBO x O0FFB5 P7PUP PS8PUP Ports 7 8 Pullup Resistor Control Registers x OOFFB8 x OOFFBA Bit 7 6 5 4 3 2 1 0 PnPUP7 PnPUP6 PnPUPS PnPUP4 PnPUP3 PnPUP2 PnPUPI PnPUPO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W P6PUP Port 6 Pullup Resistor Control Register x 00FFB6 Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 P6PUPI Reset 0 0 0 0 0 0 0 0 R W R R R R R R R W R W The PnPUP registers control the port pullup resistors The bit number cor responds to the associated pin number For instance POPUP7 applies to the P07 pin These are 8 bit
46. 0 Pullup off 1 Pullup on lt gt P6PUPO 0 P60 1 SDAO gt P6MD0 0 Port input 1 Port output lt P6DIR0 JA 0 Port low output Pin 1 Port high output 0 lt gt PeOUTO M P60 U lt SDA0 1 X P6IN0 lt 2 ox Schmidt trigger Figure 11 14 P01 SDA1 Port 1 P60 SDA0 Port 6 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 265 Panasonic I O Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on c P3PUPn 0 P31 P32 1 50 51 D 0 Port input 1 Port output BS P3DIRn 0 Port low output Pi 1 Port high output i P3INn CVBSO CVBS1 lt MAA Figure 11 15 P31 CVBS0 and P32 CVBS1 Port 3 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 266 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on c P3PUPn ls 0 P30 P33 1 CLH CLL P3MD2 so P3MD3 Da 0 Port input 1 Port output P3DIRn 0 Port low output Pin 1 Port high output P3OUTn p y P3INn amp pue CLH CLL lt AAA
47. 1 Impedance of analog input terminal must be below 8kQ 2 When impedance of analog input terminal is over 8 condenser which capacity is above 2000 pF must be connected to suppress the voltage changes of the analog input terminal 3 During conversion do not change the output level of the terminal from H to L or from L to H and not turn on and off the peripheral circuit cause these actions may influence the power supply voltage anabg signal output D micro computer equivalent circuit R L Analog to Digital i hput terminal 1 Vss K lt lt 8 or gt 200 F Figure 6 12 Cautions on Analog to Digital Converter Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 152 Panasonic 5 Display Description 7 On Screen Display If you use the OSD function the function executes for both the text and graphics layers even if your program does not use one of these layers To pre vent error program data for the 7 1 Description The MN102H75K 85K contains an on screen display OSD function composed of three layers a text layer a graphics layer and a cursor layer You can control each layer individually which gives you great freedom in positioning displays You can also modify the ROM space that contains the text characters and the graphic t
48. 310 Appendix A Register 312 Appendix MN102HF75K Flash EEPROM 316 1 Description eee PER ee s e gerens 316 B 2 hri CE prm E 317 B 3 Using the PROM Writer 317 4 Using the Onboard Serial Programming 319 4 1 Configuring the System for Onboard Serial Programming 320 MN102H75K F75K LSI User Manual Panasonic Semiconductor Development Company 7 Panasonic Contents B 4 2 Circuit Requirements for the Target Board 321 B 4 3 Microcontroller Hardware Used in Onboard Serial Programming 322 B 4 3 1 Serial Writer Interface Description 322 B 4 3 2 Serial Writer Interface Block Diagram 322 4 4 Microcontroller Memory Map Used During Onboard Serial Programming 323 B 4 4 1 Flash ROM Address Space cet a qasa ERR 323 B 4 4 2 RAM Address Space coser lb RETRO ER E Re Ue E 324 B 4 5 Microcontroller Clock on the Target 324 B 4 6 Setting Up the Onboard Serial Programming 325 B 4 7 Branching to
49. A register State S H bt7 6 5 4 3 2 1 0 Transfer In continuous mode S H bit 7 Reference 12 cycles Figure 6 3 ADC Timing Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 144 Panasonic Analog to Digital Converter A D Conversion Timing 6 4 2 Single Channel Single Conversion Timing When ANMD 1 0 b 00 the ADC converts one ADIN input signal a single time An interrupt occurs when the conversion ends Load the number of the channel to be converted to the ANICH 3 0 field of the ADC control register ANCTR ANNCH 3 0 field is ignored in this mode When the software starts the conversion write a 0 to the ANTC bit disabling conversion start at timer 1 underflow then write a 1 to ANEN If ANTC 1 ANEN goes high upon a timer 1 underflow ANEN remains high during the con version then clears to 0 when the conversion ends Start Stop Interrupt request Channel 0 Channel 1 Channel 2 State conversion conversion conversion ANEN Figure 6 4 Single Channel Single Conversion Timing 6 4 3 Multiple Channel Single Conversion Timing When ANMD 1 0 b 01 the ADC converts multiple consecutive ADIN input signals a single time An interrupt occurs when the conversion sequence ends Load 06 to the ANICH 3 0 field of the ADC control register ANCTR then load the number of the final channel
50. Line 1 data Line 2 data Line 3 data Line 15 data 16 color mode 16 color mode GROMEND 7 Sheet 1 bits 7 to 0 GROMEND Sheet 1 bits 15 to 8 GROMEND 5 Sheet 2 bits 7 to 0 GROMEND 4 Sheet 2 bits 15 to 8 GROMEND 3 Sheet 3 bits 7 to 0 In this example line 16 of the code 00 graphics tile is set in 16 color mode Setup example Line 16 data Graphics tile GROMEND 2 Sheet 3 bits 15108 1 GROMEND 1 Sheet 4 bits 7 to 0 Use graphics palette 7 Use graphics palette 6 Use graphics palette 5 r Use graphics palette 4 8 bytes Sheet 4 bits 15108 1 byte 0000 0000 Use graphics palette 3 Use graphics palette 2 Use graphics palette 1 Use graphics palette 0 Line 1 Line 2 Line 3 Line 16 Bit 15 A Bit 0 1010 1010 0000 0000 1100 1100 0000 0000 1111 0000 0000 0000 0000 0000 Figure 7 10 Graphics ROM Setup Example for a Single Line 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 173 Panasonic 5 Display Graphic Tile Codes 2 colors 4 colors 8 colors 16 colors ROMEND 80xN 1 4 1 N x 4 3 1 N 1 Nisa Nx
51. OSDGID OSD graphics interrupt detect flag 0 Interrupt undetected 1 Interrupt detected OSDGICH OSD Graphics Interrupt Control Register High x 00FC91 Bit 7 6 5 4 3 2 1 0 OSDG OSDG OSDG __ OSDG Lv2 LVO IE Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R R R R W OSDGICH sets the priority level for and enables OSD graphics inter rupts It is an 8 bit access register Use the MOVB instruction to access it OSDGLV 2 0 OSD graphics interrupt priority level Sets the priority from 0 to 6 OSDGIE OSD graphics interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 68 Panasonic Interrupts Interrupt Control Registers OSDCICL OSD Text Interrupt Control Register Low x 00FC92 Bit Z 6 4 3 2 1 0 OSDC _ DA ospc IR ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R OSDCICL detects and requests OSD text interrupts It is an 8 bit access register Use the MOVB instruction to access it OSDCIR OSD text interrupt request flag 0 No interrupt requested Interrupt requested OSDCID OSD text interrupt detect flag 0 Interrupt undetected Interrupt detected OSDCICH OSD Text Interrupt Control Register High x 00FC93 Bit 7 6 5 4 3 2 1 0 OSDC IE Reset 0 0 0 0 0
52. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R RW RW RW RW RW R W RW RW RW RW SPRTO Cursor 0 color palette select 0 Graphics color palette 1 1 Graphics color palette 2 STCO 8 0 Cursor 0 Tile Code Use the same ROM data as that used for the graphics STC1 Cursor Tile Code Register 1 x 007F2A Bit 15 14 13 12 11 10 9 8 7 6 2 4 3 2 1 0 SPRTI STC18 STC17 STC16 STC15 STC14 STC13 STC12 STC11 STC10 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R RW RW RW RW RW RW RW RW RW RW SPRT1 Cursor 1 color palette select 0 Graphics color palette 1 1 Graphics color palette 2 STC1 8 0 Cursor 1 Tile Code Use the same ROM data as that used for the graphics STC2 Cursor Tile Code Register 2 x 007F2C Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPRT2 STC28 STC27 STC26 STC25 STC24 STC23 STC22 STC20 STC20 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R RW RW RW RW RW RW RW RW RW RW SPRT2 Cursor 2 color palette select 0 Graphics color palette 1 1 Graphics color palette 2 STC2 8 0 Cursor 2 Tile Code Use the same ROM data as that used for the graphics Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 204 Panasonic 5 Display OSD Registers STC3 Cursor Tile Code Register 3 x 0
53. Table 2 4 provides a list of the interrupt control registers and a description of the fields in each register follows 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 45 Panasonic Interrupts Interrupt Control Registers Table 2 4 Interrupt Control Registers Register Address R W Description IAGR x 00FC0E R Accepted interrupt group number register WDICR x 00FC42 R W Watchdog interrupt control register PIICR x 00FC44 R W Undefined instruction interrupt control register EIICR 00 46 R Interrupt error interrupt control register EXTMD x 00FCF8 R W External interrupt mode register IQOICL x 00FC48 R W External interrupt 0 interrupt control register low IQOICH x 00FC49 R W External interrupt 0 interrupt control register high IQ1ICL x 00FC4A R W External interrupt 1 interrupt control register low IQ1ICH x 00FC4B R W External interrupt 1 interrupt control register high IQ2ICL x 00FC50 R W External interrupt 2 interrupt control register low IQ2ICH 00 51 R W External interrupt 2 interrupt control register high IQ3ICL x 00FC52 R W External interrupt 3 interrupt control register low IQ3ICH x 00FC53 R W External interrupt 3 interrupt control register high IQ4ICL x 00FC58 R W External interrupt 4 interrupt control register low IQ4ICH x 00FC59 R W
54. 1 V shutter 0 shutters above VSP1 0 V shutter 1 shutters below 1 shutter 0 shutters to the left HSP1 0 H shutter 1 shutters to the right vsuri SHTRAD 1 All shutters ORed Figure 7 31 Shuttered Area Setup Examples 102 75 75 85 85 LSI User Manual 195 Panasonic Panasonic Semiconductor Development Company 5 Display Controlling the Shuttering Effect 7 13 2 Controlling Shutter Movement Enabling the shutter movement function in the registers allows the shuttered area to expand or contract over time producing a wipe in or wipe out effect This allows the OSD display to appear or disappear without an abrupt transition Table 7 13 shows the register settings required for this function and figure 7 32 shows four setup examples There is no repeat operation for shutter movement so you must reset the bits each time Table 7 13 Bit Settings for Controlling Shutter Movement VShutterO VShutter1 HShutterO HShutter1 Function Bit Name Bit Name Bit Name Bit Name Description Shutter movement VSMO VSM1 HSMO HSM1 0 Move shutter enable disable 1 Don t move shutter Shuttering movement VSMPO VSMP1 HSMPO HSMP1 0 Move from top to bottom vertical shutters or direction from left to right horizontal shutters 1 Move from bottom to top vertical shutters or from right to left horizontal shutters Shuttering movement SHSPO SHTSP1 00 Move
55. 85 85 LSI User Manual Ports I O Port Control Registers P4MD Port 4 Output Mode Register x 00FFF8 Bit 7 6 5 4 3 2 1 0 P4MD7 PAMD6 P4MDS P4MD4 P4MD3 P4MD2 PAMDI PAMDO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W P4MD is an 8 bit access register 4 07 P47 function switch 0 P47 NHSYNC 1 NHSYNC P4MD6 This bit exists but contains no function P4MD5 P45 function switch To use P45 or P46 set the OSCSEL 1 0 field of OSDI to b 00 0 PAS OSDXO 1 P46 OSDXI P4MD4 P44 output switch 0 P44 TMSIC HIO 1 TMSIC HIO P43 output switch To use TMSIOB as an output pin set this bit to 1 and set the P4DIR3 bit to 1 0 1 TMSIOB HII P4MD2 P42 output switch To use TM5IOA an output pin set this bit to 1 and set the P4DIR2 bit to 1 0 42 1 5 P4MD1 P41 output switch To use TM1IO as an output pin set this bit to 1 and set the PADIRI bit to 1 0 P41 1 PAMDO P40 output switch If you set this bit to 1 select DAYMOUT or YM in the YCNT bit of ODSI 0 40 1 YM DAYMOUT MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 283 Panasonic Ports I O Port Control Registers P5MD Port 5 Output Mode Register x 00FFFA Bit 7 6 5 4 3 2 1 0 PSMD7 PSMD6 PSMDS PSMD4 PSMD3 PSMD2 PSMD1 PSMDO
56. Eg 76 4 1 8 Bit Timer Functions and Features 1 78 4 2 8 Bit Timer Control 87 4 3 16 Bit Timer Functions and Features 1 89 4 4 Count Direction for 4x Two Phase Encoder Timing Example 113 4 5 Count Direction for 1x Two Phase Encoder Timing Example 116 4 6 16 Bit Timer Control 4 125 5 1 Serial Interface Functions and 127 5 2 Example Baud Rate Settings for the UART 129 5 3 Serial Interface Control Registers 140 6 1 ADC Functions and Features 5 5 2 a ek Rea 3 94 eR HERE E ERU EP 143 6 2 ADC Control Registers voty sunaha anata aspa Aiba rd te end 150 7 1 OSD Functions and Features 2 eae RE RS 153 7 2 Power Saving Control Bits for the 5 155 7 3 OSDPOFF OSDREGE 5 155 7 4 Associated Tiles for Cursor Tile Code
57. External interrupt 4 interrupt control register high IQ5ICL x 00FC5A R W External interrupt 5 interrupt control register low IQ5ICH 00 5 R W External interrupt 5 interrupt control register high TM4CBICL 00 60 R W Timer 4 compare capture interrupt control register low TM4CBICH 00 61 R W Timer 4 compare capture interrupt control register high TM4CAICL x 00FC62 R W Timer 4 compare capture A interrupt control register low TM4CAICH x 00FC63 R W Timer 4 compare capture A interrupt control register high TM4UDICL x 00FC64 R W Timer 4 underflow interrupt control register low TM4UDICH x 00FC65 R W Timer 4 underflow interrupt control register high VBIICL x 00FC66 R W VBI 1 interrupt control register low VBIICH x 00FC67 R W VBI 1 interrupt control register high TM5CBICL x 00FC68 R W Timer 5 compare capture B interrupt control register low TM5CBICH x 00FC69 R W Timer 5 compare capture B interrupt control register high TM5CAICL 00 6 R W Timer 5 compare capture A interrupt control register low TM5CAICH x 00FC6B R W Timer 5 compare capture A interrupt control register high TM5UDICL x 00FC6C R W Timer 5 underflow interrupt control register low TM5UDICH x 0O0FC6D R W Timer 5 underflow interrupt control register high VBIWICL x 00FC6E R W VBI 2 interrupt control register low VBIWICH x 0OFC6F R W VBI 2 interrupt control register high TM2
58. HI HI1 input Figure 11 19 P44 TM5IC HI1 Port 4 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 269 Panasonic Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on lt P4PUP5 0 45 1 OSDXI gt P40UT5 0 Port input 1 Port output lt gt e P4DIRB me To internal circuit P4IN5 C 1 Pin gt T P45 OSDXO LCCNT is the OSDXI O Connect oscillation control signal from the OSD 0 Disable r1 2 1 Enable LCCNT 975 4 TT 0 Pullup off 1 Pullup on DO P4PUP6 0 46 1 OSDXI OSDXO 0 Port input 1 Port output lt gt e PADIR6 0 Port low output Pin 1 Port high outpiit lt gt e 400 6 X P46 OSDXI lt Figure 11 20 P45 OSDXO P46 OSDXI Port 4 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 270 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on lt P4PUP7
59. HVCOND 247 x007EDA x 007EFA Sync separator status register 9 3 3 1 HSYNC Separator The HSYNC separator extracts the HSYNC signal from the composite sync signal using the sampling clock generated by the sync separator clock pulse gen erator This circuit also secures and interpolates the HSYNC signal T Error HSYNC Missed Detected HSYNC resulting from HSYNC Q noise Window for securing and interpolating HSYNC hey 1 Window open OSEP setina HSEP2 setting O Interpolated Secured and HSYNC interpolated HSYNC HSEP1 setting gt Figure 9 7 HSYNC Securement and Interpolation As shown in figure 9 7 noise can cause the HSYNC detection circuit to both miss HSYNC pulses and add erroneous ones The HSYNC separator contains a window circuit to correct these errors The open and close timing for this window is set in the HSEP1 and HSEP2 registers and the unit is the sampling clock for the HSYNC separator The circuit counts a corrected and interpolated HSYNC signal If the count is greater than that set in the HLOCKLV register within the interval set in the HDISTW register the HLOCK bit of HVCOND sets to 0 indicating an asyn chronous state This allows the device to determine the quality of the signal Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 232 Panasonic Closed Caption Decoder Functiona
60. Lie Ate ei edad MERO gebe pete PERPE TRA eee 201 7 14 3 Considerations for Interlaced Displays 202 7 15 OSD Registers e E uu EWPSSE USER Deest dlc bl ee SW Part deis 203 8 IR Remote Signal Receiver 216 8 1 Descriptions iiu eee V ete e ee n en e pce dest edt 216 8 2 Block Diagram sere a ERE cs b E unite ust ee 217 8 3 IR Remote Signal Receiver 218 8 3 1 Operating UR ge akan ep AOR EVE Bele ens 218 8 3 2 Noise Eilter E atus eiut esp E Pe Em 218 8 3 3 8 Bit Data Reception tuos reve bee eret Pb e usu eben entes 219 8 3 4 Identifying the Data 220 8 3 5 Generating Inteft pts cssc eR ERE RM Ree RES EUER ee er ME 221 8 3 5 1 Leader Detection soror cR eere REUS 221 8 3 5 2 Trailer Detection ec e eee UN peres me E IER a een eroi Dees 221 8 3 5 3 8 Bit Data Reception 221 8 3 5 4 Pin Edge D tection o CEPI bene o NO IO IO pP dee 221 8 3 6 Controlling the SLOW 2 222 8 4 IR Remote Signal Receiver Control
61. MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 143 Panasonic Analog to Digital Converter Block Diagram 6 3 Block Diagram 0 ADINO ADI La ADIN3 128 64 15 Tie 8 j4 2 1 1 ADIN M ADIN5 o ADIN6 ADIN7 r V ADIN8 VES ADIN9 ADIN10 r ADIN11 T 4 Storage converted data Shift register for state information ANCTR ANNCH AN1CH 4 1 AN11BUF AN0BUF Bosc Divider Compare INC interrupt Data registers generate 8 bit x 12 Figure 6 2 ADC Block Diagram 6 4 A D Conversion Timing 6 4 1 Selecting the ADC Clock Source Calculate the A D conversion time as follows conversion time s 12 cycles x Bosc cycle s x divide by ratio ch For example if you set the clock source to Bosc 8 the conversion time is Bosc x 96 cycles Interrupt Write to
62. P2MD example x 00FFF4 Bit 15 14 13 12 11 10 9 8 Z 6 5 4 3 2 1 0 2 2 2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 MD14 MD13 MD12 MD10 MDS MD2 MDI MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 101 Panasonic Timers 16 Bit Timer Setup Examples P2DIR example x 00FFE2 Bit 7 6 5 4 3 2 1 0 P2 P2 P2 P2 P2 P2 P2 P2 DIR7 DIR6 DIRS DIR4 DIR3 DIR2 DIRI DIRO Setting 0 1 1 0 0 0 0 0 set up timer 0 1 Disable timer 0 counting in the timer 0 mode register TMOMD This step is unnecessary immediately after a reset since TMOMD resets to 0 TMOMD example x 00FE20 Bit 7 6 5 4 3 2 1 0 TM0 TM0 TM0 TM0 EN LD 81 50 Setting 0 0 0 0 0 0 2 Set the divide by ratio for timer 0 To divide 4 by two write x 01 to the timer 0 base register TMOBR The valid range for TMOBR is 0 to 255 x 00FE10 Bit 7 6 5 4 3 2 1 0 TMO TMO TMO TMO TMO TMO TMO TMO BR7 BR6 BR5 BR4 BR3 BR2 BRI BRO Setting 0 0 0 0 0 0 0 1 3 Set the TMOLD bit of the TMOMD register to 1 This loads the value in the 1 base register to binary counter At the same time select
63. POFF ON OFF OFF OFF OFF Rest 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PCNTO0 is a 16 bit access register SCLKF 1 0 SYSCLK frequency select 00 SYSCLK x 2 4 732 42 Hz 01 VCOCLK x 3 Enable PWM set PCNT1 bit 1 10 SYSCLK x 2 to 1 if you are outputting 11 SYSCLK sciK 2 ODASCI1 Serial port 1 output switch 1 Push pull 0 Open drain ODASCIO Serial port 0 output switch To use P57 as a port set this bit to 0 1 Push pull 0 Open drain SIFSEL1 Serial port 1 interface select 0 Three line enable SBI1 SBO1 SBT1 1 Two line enable SBD1 SBT1 SIFSELO Serial port 0 interface select 0 Three wire enable SBIO SBOO SBTO 1 Two wire enable SBDO 5 0 I2CSEL1 SDA1 SCL1 enable 0 Disable 1 Enable To use POI SDA1 and PO2 SCL 1 as general purpose port pins you must both select the ports in the port mode register and disable this bit I2CSELO SDAO SCLO enable 0 Disable 1 Enable To use P60 SDAO and P61 SCLO as general purpose port pins you must both select the ports in the port mode register and disable this bit MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 285 Panasonic Ports I O Port Control Registers 1 turn off the OSD block save power 1 Write a 0 to OSD OSD1 bit 10 2 Wait fo
64. VSTI VSTI VST1 VSTI ze 1 1 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW VSON t1 Vertical shutter 1 on off 0 Off 1 On VSP1 Vertical shutter 1 shuttering direction 0 Shutter below 1 Shutter above VSMP1 Vertical shutter 1 movement direction 0 Top to bottom 1 Bottom to top VSM1 Vertical shutter 1 movement control 0 Don t move 1 Move VST1 9 0 Vertical shutter 1 position HSHTO Horizontal Shutter 0 Register x 007F24 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 HSMP HSTO HSTO HSTO HST0 HST0 HST0 HST0 HST0 HSTO HSTO zi 2m 0 HSPO 0 H5MO 9 8 7 6 5 3 2 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R RW RW RW RW RW R W RW RW RW RW RW RW RW RW HSONO Horizontal shutter 0 on off 0 Off 1 On HSP0 Horizontal shutter 0 shuttering direction 0 Shutter to the right 1 Shutter to the left HSMPO Horizontal shutter 0 movement direction 0 Left to right 1 Right to left HSM0 Horizontal shutter 0 movement control 0 Don t move 1 Move HSTO 9 0 Horizontal shutter 0 position MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 211 Panasonic 5 Display OSD Registers HSHT1 Horizontal Shutter 1 Regist
65. Write to the fields described below GCOL 1 0 007F08 bits 9 and 8 sets the number of colors 2 4 8 or 16 GTC 8 0 GTC bits 8 to 0 in the RAM data specifies the code of the tile to be displayed GPRT GTC bit 9 in the RAM data selects tile color palette 1 or 2 GPTIn x 007FC0 x 007FDE or GPT2n x 007FEO0 x 007FFE speci fies the colors on the palettes corresponding to the tile data stored in the ROM Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 178 Panasonic 5 Display Setting Up the OSD To set up the text display colors Write to the fields described below CCOL 3 0 COL bits 3 to 0 in the RAM data sets the color of the charac ter This value is in reference to the selected color palette CPTO CPTF BCOL 3 0 COL bits 7 to 4 in the RAM data sets the background color As with CCOL this value is in reference to the selected color palette FRAME COL bit 9 in the RAM data enables character outlining when set to 1 Set the outline color in the FRAME color palette x 007FA2 CSHAD COL bit 10 in the RAM data enables character shadowing when set to 1 Set the shadowing color in the FRAME color palette x 007FA2 This function is unavailable in the closed caption mode BSHAD I 0 COL bits 12 to 11 in the RAM data enables character box shadowing This function is unavailable
66. 12MHz On On 0 0 1 1 SLOW 4MHz 2MHz Off On 0 1 0 HALTO Invoked 55 MHz 42MHz On Off from NORMAL HALT1 Invoked from SLOW 1 0 x x STOP Off Off Off Off 0 1 1 1 4 MHz 2 MHz Off Off Note All unindicated bit settings are reserved Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 76 Panasonic Timers 6 Bit Timer Description 4 Timers 4 1 8 Bit Timer Description The MN102H75K 85K contains four 8 bit timers that can serve as interval timers event timer counters clock generators divide by 2 output of the underflow reference clocks for the serial interfaces or start timers for A D con versions The clock source can be the internal clock oscillator frequency divided by 2 or the external clock 1 4 or less the oscillator frequency input A timer interrupt is generated by a timer underflow All passages below assume a The 8 bit timers are cascadable into true 16 bit timers For instance if you clock Bosc oh 24 MHZ cascade timers 0 and 1 timer 0 sends cascaded output to timer 1 The result is true 16 bit division rather than two successive 8 bit divisions Cascading Connections Y Y Y 8 bit x 4 Configuration example 16 bit 8 bit 8 bit 8 bit 8 bit 16 bit Clock output Interval Sync UART Event Event timer t
67. ADIN11 PWM1 P47 HSYNC lt 12 9p view 52 gt P17 PWM2 P81 4 13 51 P20 PWM3 P46 5 14 50 gt P21 PWM4 P45 OSDXO 4 gt 15 49 H4 P22 5 P44 5 H1 16 48 gt P23 PWM6 P43 TMSIOB HIO 4 9 17 47 gt P24 TM4IC SBT1 P42 4 gt 18 46 4 gt P25 TM4IOB SBI1 SBD1 P41 TM110 19 45 H4 26 SBO1 gt 20 44 4 gt P27 TMOIO PDO t 21 43 gt P74 GV cO GN Cc Q A QN QU CO CO sb e gt rFoerretoar sfSorag2z2e8foga EK 2 2 a Z gt gt m 20 9 orga 9 2 gt a gt amp 8 a go a Notes 1 Pins marked with an asterisk are N channel open drain pins 2 Pin 41 15 Vpp in the MN102H75K and Vpp in the MN102HF75K Figure 1 10 MN102H75K Pin Configuration in Single Chip Mode 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 31 Panasonic General Description Pin Descriptions Table 1 3 Pin Functions Block Pin Name lO Pin Count Description Vpp 1 Voltage supply Vss 2 AVpp 1 Analog voltage supply Vpp Vpp 1 Voltage supply Vpp in mask ROM version and Vpp in EEPROM version
68. Bujdues uonorulsu SIM MO Jejunoo UOISIAIP E S 68070 ZHN 21 H UUU Hl guBis 0 112 6 7 4 9 2 ouenboaJ4 1703 00 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 217 Panasonic IR Remote Signal Receiver IR Remote Signal Receiver Operation 8 3 IR Remote Signal Receiver Operation 6 3 1 Operating Modes The IR remote signal receiver has three operating modes HEAMA 5 6 bit and HEAMA 5 6 bit automatic detect Set the mode in the MODAUTO and MODSEL bits of the interrupt control register RMIR The FMTMON bit of the interrupt status register RMIS monitors the operating mode In automatic detect mode the microcontroller checks the interval between remote signal edges If the interval is n 4Ts to n 3Ts where n is the leader value set in the LD 3 0 field of the RMLD register it processes the data in HEAMA format If the interval is 28 to 35 Ts cycles it processes the data in 5 6 bit format 8 3 2 Noise Filter The IR remote signal receiver contains a noise filter to eliminate noise from the remote signal To enable the noise filter set the FILTRE bit of the interrupt control register RMIR to 1 The noise filter samples the remote input signal every PWM6 cycle 21 3 us or PWMS cycle 85 5 us then outputs the value that it sampled at least three times during the last fou
69. Color background COLBSHT 0 Shutter color background shuttering 1 Don t shutter color background Shutter blanking SHTBLK 0 Don t output blanks to the shuttered area 1 Output blanks to the shuttered area To shutter text layer characters text layer background and graphics layer Text Set the text shutter control bit CCSHT of the shutter control register SHTC x 007F28 to 1 Text background Set the text background shutter control bit BCSHT of SHTC to 1 Graphics Set the text background shutter control bit GSHT of SHTC to 1 Figure 7 33 shows three setup examples of text layer shuttering Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 198 Panasonic 5 Display Controlling the Shuttering Effect HSHT0 HSHT1 CCSHT 0 Shuttering of text foreground disabled VSHTO BCSHT 0 Shuttering of text background disabled VSHT1 Television screen Shuttered region HSHTO HSHT1 CCSHT 1 Shuttering of text foreground enabled VSHTO BCSHT 0 Shuttering of text background disabled VSHT1 Television screen HSHTO HSHT1 CCSHT 0 Shuttering of text foreground disabled BCSHT 1 Shuttering of text background enabled VSHT1 The text background disappears leaving only the characters visible Television screen Figure 7 33 Text Layer Shuttering Setup Examples shutter the color background
70. Contains the group number multiplied by four EXTMD External Interrupt Mode Register x 00FCF8 Bit 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 IQ5TG IQ5TG IQ4TG IQ4TG IQ3TG IQ3TG IQ2TG 1Q2TG IQ1TG IQ1TG IQ0TG IQ0TG 1 0 1 0 1 0 1 0 1 0 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R RW RW RW RW RW RW RW RW RW RW RW RW EXTMD sets the trigger conditions for external interrupts IQnTG 1 0 sets the interrupt mode on the associated IRQ pin Each IRQ pin can have any polarity or edge setting EXTMD is a 16 bit access register 00 Active low interrupt 01 Either edge triggered interrupt positive or negative 10 Negative edge triggered interrupt 11 Positive edge triggered interrupt WDICR Watchdog Interrupt Control Register x 00FC42 Bit 7 6 5 4 3 2 1 0 WDID Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W WDICR is an 8 bit access register WDID Watchdog interrupt detect flag 0 Interrupt undetected 1 Interrupt detected Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 48 Panasonic Interrupts Interrupt Control Registers PIICR Undefined Instruction Interrupt Control Register x 00FC44 Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W is an 8 bit access register PIID Undefin
71. LSI User Manual 88 Panasonic 16 Bit Timer Features 4 8 16 Bit Timer Features Table 4 3 16 Bit Timer Functions and Features Function Feature Timer 4 Timer 5 Interrupt request flag s TM4UDIR bit of TM4UDICL bit of TM4CAIR bit of TM4CBIR TMSUDIR bit of TMS5UDICL TMSCAICL bit of TM5CAIR TMSCBICL bit of TM5CBIR Interrupt sources Timer 4 underflow Timer 4 compare A match Timer 4 capture A Timer 4 compare B match Timer 4 capture B Timer 5 underflow Timer 5 compare A match Timer 5 capture A Timer 5 compare B match Timer 5 capture B Clock sources Timer 0 underflow Timer 1 underflow TM4IB signal 4x two phase encoder TM4IA and TM4IB signals 1x two phase encoder TM4IA and TM4IB signals Timer 0 underflow Timer 1 underflow TMBIB signal 4x two phase encoder and TMBIB signals 1x two phase encoder and TMBIB signals Count direction Up down counter Up down counter Interval timer function v v Event counter function PWM function One shot pulse output Single phase capture input Two phase capture input Two phase encoding 4x Two phase encoding 1x External count direction control SINSISINISISISIS 5 5 55 5 5 55 MNI02H75K F75K 85K F85K LSI User Manual 89 Panasonic Panasonic Semiconductor Development Company Timers 16 Bit T
72. NN NN NN NN NN 1 output 4 f 1 i i amp k To serial indicates 25 24 02 01 Figure 5 12 Serial Interface Clock Timing The interrupt process is repeated each time the buffer receives another byte of serial data Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 136 Panasonic Serial Interfaces Serial Interface Setup Examples 5 6 4 Setting Up Transmission Using Serial Interface 0 This example illustrates the microcontroller as a master transmitter in the mode using the SBOO and SBTO pins To set up the output ports mode requires open drain Set the PSMD7 and PSMDS bits of the port 5 output mode register PSMD to 1 pins To set this up set the This selects the SBOO and SBTO pins as the output port for the 2 interface ODASCIO bit of PONTO X OOFF90 to 1 In addition set the PSPUP7 and P5PUP5 bits of PSMD example X O0FFFA P5PUP x 00FFB9 to enable Bit 7 6 5 4 3 2 1 0 pullup control of the SBOO and P5 P5 P5 P5 P5 P5 P5 P5 STBO MD7 MD6 MDs MDI Setting 1 0 1 0 0 0 0 0 To set up the C interface The parity bits serve as the ACK Set the operating conditions in the serial control register SCOCTR Select 4 id 1 output for the transfer clock SCOPTY 2 0 b 101 8 bit character length nal select a fixed parit
73. P1DIRn 79 PWV0 PWM1 0 Port low output Pin 1 Port high output 4 P1OUTn 2 3 Bei po P1INn lt m ADIN10 ADIN11 Figure 11 5 P15 ADIN10 PWMO and P16 ADIN11 PWM1 Port 1 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 256 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on iN P1PUPn P2PUPn 0 17 20 21 22 23 H 1 PWM2 PWM4 PWM5 PWM6 S1 MD 2n 2 P2MD 2n 0 Port input 1 Port output aise P1DIRn 0 P2DIRn M U PWM2 PWM3 PWM4 lt PWM5 6 1 gt o 0 Port low output 1 Port high output P1OUTn 0 P2OUTn M pin H X lt Low output P1INn P2INn lt Figure 11 6 PWM2 Port 1 P20 PWM3 P21 PWM4 P22 PWM5 and P23 PWM6 Port 2 MNI02H75K F75K 85K F85K LSI User Manual 257 Panasonic Panasonic Semiconductor Development Company I O Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on lt gt P2PUP4 li 00 P24 01 SBT1 10 TM4IC P2MD8 P2MD9 b
74. P42 as the timer output port PAMD example x O0FFF8 Bit 7 6 5 4 3 2 1 0 P4 P4 P4 P4 P4 P4 P4 P4 MD6 MDS MI2 MDI Setting 0 0 0 0 0 1 0 0 P2DIR example x 00FFE4 Bit 7 6 5 4 3 2 1 0 P4 P4 P4 P4 P4 P4 P4 P4 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIRI DIRO Setting 0 0 0 0 0 1 0 0 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 117 Panasonic Timers 16 Bit Timer Setup Examples Use the MOV instruction for this setup and only use 16 bit write operations This step stops the TM5BC count and clears both TM5BC and the S R flip flop to 0 WB To set up timer 5 1 Set the operating mode in the timer 5 mode register TMSMD Disable timer 5 counting and interrupts Select up counting Select Bosc 4 as the clock source TM5MD example x 00FE90 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM5 TM5 TMS TMS TMS TMS 5 TMS TMS TMS 5 TMS TMS TMS EN NLD UDI UDO ONE MDI LP ASEL S2 51 SO Setting 0 0 0 0 0 0 1 1 0 0 0 1 lorO 0 1 1 2 Set the timer 5 pulse width TM5CA valid settings x 0001 to x FFFF Since the pulse width in this example is two cycles of the Bosc 4 clock write x 0003 to TM5CA 5 counts from 0
75. Port high output P1OUTn p t x lt P1INn lt f nd Schmidt trigger IRQ1 IRQ2 IRQ3 ADINS5 ADIN6 ADIN7 lt AAA Figure 11 3 P10 ADIN5 IRQ1 P11 ADIN6 IRQ2 and P12 ADIN7 IRQ3 Port 1 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 254 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on lt P1PUPn P 00 P13 P14 01 WDOUT STOP 10 ADIN8 ADIN9 E P1MD 2n 1 cs 2 0 Port input 1 Port output p P1DIRn 0 Port low output 1 Port high output T dA P1OUTn SE Pin rh gN WDOUT STOP gt L Cr ADIN8 ADIN9 lt Figure 11 4 P13 ADIN8 WDOUT P14 ADIN9 STOP Port 1 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 255 Panasonic Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on lt P1PUPn 00 15 16 01 PWMO PWM1 10 ADIN10 ADIN11 P1MD 2n D P1MD 2n 1 0 Port input 1 Port output g
76. SCnIST Serial port n 2 start sequence detect A read or write to SCnTRB clears this bit 0 No start sequence 1 Start sequence detected SCnFE Serial port n framing error A framing error occurs when a 0 is received during stop bit transfer Fram ing error data is updated each time the stop bit is received 0 No error Framing error occurred SCnPE Serial port n parity error A parity error occurs when the received parity bit is 1 and the parity setting is 0 when the received parity bit is 0 and the parity setting is 1 when the received parity bit is odd and the parity setting is even or when the received parity bit is even and the parity setting is odd Parity error data is updated each time the parity bit is received 0 No error Parity error occurred SCnOE Serial port n overrun error An overrun error occurs during reception when a data byte reception ends before the CPU has read the previous byte from SCnTRB Overrun error data is updated each time the last data bit seventh or eighth bit is received 0 No error 1 Overrun error occurred Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 142 Panasonic Analog to Digital Converter Description 6 Analog to Digital Converter 6 1 Description MN102H75K 85K contains an 8 bit charge redistribution A D converter ADO that can process up to 12 channels The reference clock is selectable to Bosc x 1 8 or 1 16
77. SYSCLK O 1 System clock output OSC1 1 Oscillator input connection with internal PLL Clocks OSC2 1 Oscillator output connection with internal PLL OSDXI 1 OSD oscillator input connection alt function 46 OSDXO O 1 OSD oscillator output connection alt function P45 Reset RST 1 Reset alt function P53 Interrupts external IRQ0 IRO5 6 Sy EN ED RU p d alt functions HSYNC 1 Horizontal sync signal input OSD VSYNC 1 Vertical sync signal input YS O 1 Video signal cut TMnIOA 4 5 2 Input capture output compare 16 bit 2 TMnIOB 4 5 2 Input capture output compare SR TMnIC n24 5 2 Timer counter clear signal 8 bit 4 TMnIO n 0 1 y o 2 Timer clock input timer output SBIO SBI1 2 Serial data input SBD0 SBD1 VO 2 Serial data input Serial interfaces 2 5 0 5 1 y o 2 Serial data output SBTO SBT1 2 Serial clock signal SDA0 SDA1 I O 2 data 2 interfaces 2 SCLO SCL1 2 remote signal RMIN 1 Remote signal input PWM 8 bit 7 channel PWMO PWM6 7 Pulse width modulator output Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 32 Panasonic General Description Pin Descriptions Table 1 3 Pin Functions Continued Block Pin Name lO Pin Count Description P00 P07 y o 8 General purpose port 0 I O P10 P17 y o 8 General purpose port 1 I O po
78. Serial 1 transmission end interrupt priority level Sets the priority from 0 to 6 SCT1IE Serial 1 transmission end interrupt enable flag 0 Disable 1 Enable SCRIICL Serial 1 Reception End Interrupt Control Register Low x O0FC9A Bit 7 6 5 4 3 2 1 0 m 20 SCRI _ _ SCRI ID Reset 0 0 0 0 0 0 0 0 RW R R R R W R R R R SCRIICL detects and requests serial 1 reception end interrupts It is an 8 bit access register Use the MOVB instruction to access 1t SCT1IR Serial 1 reception end interrupt request flag 0 No interrupt requested Interrupt requested SCT1ID Serial 1 reception end interrupt detect flag 0 Interrupt undetected Interrupt detected SCR1ICH Serial 1 Reception End Interrupt Control Register High x 00FC9B Bit 7 6 5 4 3 2 1 0 SCRI IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W SCRIICH enables serial 1 reception end interrupts It is 8 bit access register Use the MOVB instruction to access it The priority level for serial 1 reception end interrupts is written to the SCTILV 2 0 field of the SCT1ICH register SCR1 IE Serial 1 reception end interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 70 Panasonic Interrupts Interrupt Control Registers I2CICL 2 Interr
79. Set the color background shutter control bit COLBSHT of the shutter control register SHTC x 007F28 to 1 This function exists only when the program enables a color background It allows you to limit the area covered by the color background blank out the shuttered area Set the shutter blanking control bit SHTBLK of SHTC to 1 Shutter blanking outputs black to the entire shuttered area To output blanking to a display that uses a color background enable the color background shutter COLBSHT 1 so that the color background will also be blanked in the shuttered area Figure 7 34 shows two setup examples 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 199 Panasonic 5 Display Controlling the Shuttering Effect HSHT0 HSHT1 CCSHT 0 Shuttering of text disabled BCSHT 0 Shuttering of text background disabled vSHT0 SHTBLK 1 Shuttered area is blank ABCDE VSHT1 Television screen Shuttered area Shuttered area is blank black HSHT0 HSHT1 Color background CCSHT 0 Shuttering of text disabled BCSHT 0 Shuttering of text background disabled SHTBLK 1 Shuttered area is blank COLBSHT 1 Color background is shuttered oi Renee VSHTO soe VSHT1 Television screen Figure 7 34 Shutter Blanking Setup Examples 7 13 4 Controlling Line Shuttering It is possible to cancel shuttering of individual lines on the text an
80. The 102 75 and MN102HF85K are electrically programmable 256 kilobyte flash ROM versions of the MN102H75K and MNI02HS85K They are programmed in one of two modes B 2 Benefits Because you can maintain and upgrade the program in the 102 5 up to and immediately following product release this version of the device shortens time to market by as much as one month This device is ideal for applications in quickly changing markets since it allows you to revise the microcontroller program in an existing prod uct B 3 Using the PROM Writer Mode In this mode the MN102HF75K allows a PROM writer to program the internal flash memory as if it was a standalone memory chip The microcontroller is inserted into a dedicated adaptor socket which con nects to DATA I O s LabSite PROM writer When the microcontroller connects to the adaptor socket it automatically enters PROM writer mode The adaptor socket ties the microcontroller pin states to PROM writer mode and programming occurs without any reference to the microcontroller pin states Third party PROM writer MN102HF75K Adaptor socket for MN102HF75K B 2 Benefits Because you can maintain and upgrade the program in the MN102HF75K 85K up to and immediately following product release this version of the device shortens time to market by as much as one month This device is ideal for applications in quickly changing mar kets since it allows you to revise
81. The MN102HF75K and MN102HF85K are electrically programmable 256 kilobyte flash ROM versions of the MN102H75K and MN102H85K They are programmed in one of two modes PROM writer mode which uses a dedicated adaptor socket and writer In this mode the user program can occupy the entire 256 kilobyte ROM space Onboard serial programming mode which the CPU controls This mode requires an 8 kilobyte ROM area to hold a serial writer program In onboard serial programming mode the 256 kilobyte flash memory is divided into three main areas Load program area 1 kilobyte x 0x80000 to x 0x803FF This area stores the load program for the serial writer It is overwritten in PROM writer mode Fixed user program area 7 kilobytes x 0x80400 to x Ox81FFD This area stores a user program that is write protected in serial programming mode It is overwritten in PROM writer mode User program area 248 kilobytes x 0x82000 to x OXBFFFD This area stores the user program It is overwritten in both programming modes The two words x Ox81FFE and x OxBFFFE are test areas Do not use these two words in your programs Table B 1 summarizes the programmable areas for the modes Normal operation is guaranteed with up to ten programmings Table B 1 Programmable Areas in Each Programming Mode Programming Mode Programmable Area PROM writer programming mode Entire memory space 256 KB Onboard serial programming mode User pro
82. Y Program address Operand address Interrupt bus Y Bus controller i ROM bus RAM bus Peripherals extension bus anqa MES Rp uli M Y External interface Internal ROM Internal RAM Internal peripheral ondas Figure 1 8 Functional Block Diagram BUS BR BG functions Panasonic Semiconductor Development Company 28 Panasonic 102 75 75 85 85 LSI User Manual General Description Block Diagram Table 1 2 Block Diagram Explanation Block Description Clock generator An oscillation circuit connected to an external crystal supplies the clock to all blocks within the CPU Program counter The program counter generates addresses for queued instruc tions Normally it increments based on the sequencer indications but for branch instructions it is set as the branch head address and for interrupt servicing it is set as the result of the ALU opera tion Instruction queue This block contains up to four bytes of prefetched instructions Instruction decoder The instruction decoder decodes the contents of the instruction queue generates in the proper sequence the control signals nec essary for executing the instruction and controls every block in the chip to execute the instruction Quick decoder This block decodes instructions that are 2 bytes or larger in at a much faster rate than previously possible Instruction execution control
83. transfer clock by making the timer 1 underflow either two or eight times the desired baud rate The serial interface divides the timer underflow by two or eight Always select divide by eight for UART transactions For a baud rate of 19 200 since Bosc 4 6 MHz 6 MHz 39 8 19230 77 bps This means that the timer 1 underflow must be divided by 39 PO CORE ROM RAM P1 P2 Interrupts Bus Controller P3 P4 0 1 Serial l Fs P5 P6 Timers 2 3 ADC Timers 4 5 Figure 5 11 Block Diagram of Serial Interface Clock To set timer 1 1 Disable timer 1 counting in the timer 1 mode register TM1MD This step is unnecessary immediately after a reset since TM1MD resets to 0 TM1MD example x O0FE21 Bit 7 6 5 4 3 2 1 0 TM1 TMI TMI TMI EN LD 51 50 Setting 0 0 0 0 0 0 0 0 2 Set the divide by ratio for timer 1 To divide Bosc 4 by 39 write x 26 to the timer 1 base register TM1BR The valid range for TMIBR is 0 to 255 TM1BR example x O0FE11 Bit 7 6 5 4 3 2 1 0 TMI TMI TMI TMI TMI TMI TMI TMI BR7 BR6 BR5 BR4 BR3 BR2 BRI BRO Setting 0 0 1 0 0 1 1 0 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 135 Panasonic Serial Interfaces Serial Interface Setup Examples Do not change the cl
84. value TMnIOA TMnOA Figure 4 17 Single Phase PWM Output Timing 16 Bit Timers Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 90 Panasonic Timers 16 Bit Timer Timing BC value New value written Change reflected in to CCRB next clock cycle TMnIOA PM TMnOA Figure 4 18 Single Phase PWM Output Timing with Data Change 16 Bit Timers BC value CA CB M TMnOB Eq Figure 4 19 Two Phase PWM Output Timing 16 Bit Timers BC value TMnOA Figure 4 20 One Shot Pulse Output Timing 16 Bit Timers MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 91 Panasonic Timers 16 Bit Timer Timing BC value CA TMnIB TMnIA Figure 4 21 External Count Direction Control Timing 16 Bit Timers BC value Time we TLELU LU UU UI Figure 4 22 Event Timer Input Timing 16 Bit Timers BC value FFFF Time TMnIB e TMnIA TMncA EE 7 0033 Example I 5A87 Example Figure 4 23 Single Phase Capture Input Timing 16 Bit Timers Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 92 Pa
85. x 007EC4 007 4 Minimum sync level detection interval set register SYNCMIN 244 007 8 007 8 Sync and pedestal level register BPPST 243 x 007EC6 x 007EE6 Backporch position register CLAMP 245 x 007ECC 007 Clamping control register CLPCND 248 x 007EDC x 007EEC Clamping control signal status register 1 1 9 3 3 Sync Separator Circuit A low pass filter and a sync separator comprise this block The sync separator extracts HSYNC and VSYNC from the composite video signal Figure 9 6 shows a block diagram of the circuit and table 9 6 provides the registers used to control and monitor it See the page number indicated for register and bit descriptions Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 230 Panasonic Closed Caption Decoder Functional Description y5olg 4oleied s ou S 9 6 THSS8A9 0 81 1 13508 10 99 p ou S Buiduie o lo elisdda 0 0 HO3H4SH Sdd8 0 6133S010H q E eae 31voda Jang uo1odyoeg 10 99 p Jojeredes ONASH 1949 e s p q 018 L LLNO lo slasa o 9 NINONAS Joyesedas ou s aylsodwoy N3A3aao B 10 99 P p j dn ou s o S A
86. 0 Interrupt undetected 1 Interrupt detected TM2UDICH Timer 2 Underflow Interrupt Control Register High x 00FC71 Bit 7 6 5 4 3 2 1 0 TM2UD TM2UD TM2UD TM2UD Lv2 LVO m IE Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R R R R W TM2UDICH sets the priority level for and enables timer 2 underflow inter rupts It is an 8 bit access register Use the MOVB instruction to access it TM2UDLV 2 0 Timer 2 underflow interrupt priority level Sets the priority from 0 to 6 TM2UDIE Timer 2 underflow interrupt enable flag 0 Disable 1 Enable TM1UDICL Timer 1 Underflow Interrupt Control Register Low x 00FC72 Bit 27 6 5 4 3 2 1 0 _ _ _ m TM1UD IR ID Reset 0 0 0 0 0 0 R W R R R R W R R R R TMIUDICL detects and requests timer 1 underflow interrupts It is an 8 bit access register Use the MOVB instruction to access it TM1UDIR Timer 1 underflow interrupt request flag 0 No interrupt requested Interrupt requested TM1UDID Timer 1 underflow interrupt detect flag 0 Interrupt undetected Interrupt detected MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 59 Panasonic Interrupts Interrupt Control Registers TM1UDICH Timer 1 Underflow Interrupt Control Register High x 00FC73 Bit 7 6 5 4 3 2 1 0 TMIUD IE Reset 0 0 0 0 0
87. 0 0 0 R W R R R R R R R R W OSDCICH enables timer OSD text interrupts It is an 8 bit access register Use the MOVB instruction to access it The priority level for OSD text interrupts is written to the OSDGLV 2 0 field of the OSDGICH register OSDCIE OSD text interrupt enable flag 0 Disable 1 Enable 5 Serial 1 Transmission End Interrupt Control Register Low x 00FC98 Bit 7 6 5 4 3 2 1 0 SCTI SCTI m IR ID Reset 0 0 0 0 0 0 R W R R R R W R R R R SCTIICL detects and requests serial 1 transmission end interrupts It is an 8 bit access register Use the MOVB instruction to access it SCT1IR Serial 1 transmission end interrupt request flag 0 No interrupt requested Interrupt requested SCT1ID Serial 1 transmission end interrupt detect flag 0 Interrupt undetected Interrupt detected 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 69 Panasonic Interrupts Interrupt Control Registers SCT1ICH Serial 1 Transmission End Interrupt Control Register High 00 99 Bit 7 6 5 4 3 2 1 0 SCTI SCTI SCTI SCTI LV2 LV1 LVO 7 m IE Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R R R R W SCTIICH sets the priority level for and enables serial 1 transmission end interrupts It is an 8 bit access register Use the MOVB instruction to access it SCT1LV 2 0
88. 0 0 1 0 x 00FE22 5 Set TM2LD to 0 and TM2EN to 1 then set TMILD to 0 and TMIEN to 1 This starts the timers Counting begins at the start of the next cycle When both the timer 1 and 2 binary counters reach 0 and loads the values from the base registers in preparation for the next count a timer 2 underflow inter rupt request is sent to the CPU The timer 1 interrupt is unused Bosc 4 TM2 1BR 2 1 2 underflow interrupt Interrupt enable Sequence 00 EASF JI 00 EASE EASD 0002 0001 0000 EA5F 1 2 3 4 5 Figure 4 13 Interval Timing Timers 1 and 2 Panasonic Semiconductor Development Company 86 Panasonic MN102H75K F75K 85K F85K LSI User Manual Timers 8 Bit Timer Control Registers 4 6 8 Bit Timer Control Registers Table 4 2 shows the registers used to control the 8 bit timers A binary counter TMnBC a time base counter TMnBR and a timer mode register TMnMD is associated with each 8 bit timer Table 4 2 8 Bit Timer Control Registers Register Address R W Description Timer 0 TMOBC 00 00 R 0 binary counter TM0BR x OOFEIO Timer 0 base register TM0MD x 00FE20 Timer 0 mode register Timer 1 1 x 00FE01 R Timer 1 binary counter TMIBR x OOFEII Timer 1 base register TM
89. 0 4 a Eu Bit 15 pomenp Line 18 data 6 bytes 1 byte EU 108 bytes ROMEND 6B A Line 1 data f ROMEND 98 quem Graphics tile 16bits Lei ine 2 data ROMEND SF mode Line 2 Line 3 data hast Line 3 ROMEND 5A ROMEND 59 E Line 18 Bit 0 Figure 7 18 Graphics ROM Organization in 8 Color Mode 16W x 18H Tiles ROMEND 47 Line 1 data ROMEND 43 Une S gat Graphics tile 2 data i i ROMEND 40 4 color mode lt 16 bits tine ROMEND 3F po heet 214 Line 2 Line 3 data ROMEND 3C ROMEND 3B 1 dot 2 bits 4 colors ROMEND 08 ROMEND 3 Sheet 1 bits 7 to 0 POMEND U7 pine 17 data ROMEND 2 Sheet 1 bits 15 to 8 ROMEND 03 ROMEND 1 Sheet 2 bits 7 to 0 s t Line 18 data ROMEND Sheet 2 bits 15 to 8 it 72 bytes Line 3 heet 1 Line 18 Bit 0 Figure 7 19 Graphics ROM Organization in 4 Color Mode 16W x 18H Tiles ROMEND 23 Line 1 data ROMEND 22 ROMEND 21 Line 2 data ROMEND 20 Graphics tile 2 color mode ROMEND 03 Li d ROMEND o2 Line 17 data ROMEND 01 romeno Line 18 data Sheet 1 bits 15108 1 byte Bis ROMEND 1F i 16 bits i a ROMEND 1E ia Line 1 9 ROMEND 1D heet 11 Line 2 2 Line 3 e 1dot 1 bit 2 colors ROMEND 04 Line 18 Bit 0 Figure 7 20 Graphics ROM Organization in 2 Color Mode 1
90. 1 1 tion decoders caption 1 ON PCNTO bp1 0 ON PONTO bp5 1 Use one cap caption 0 ON PCNTO bp0 0 ON PCNTO bp4 1 P3MD bp3 2 1 1 0 1 tion decoder no caption 1 OFF PCNTO bp1 1 OFF PCNTO bp5 0 No use caption no caption 0 OFF PCNTO bp0 1 OFF PCNTO bp4 0 P3MD bp3 2 1 0 0 0 decoder no caption 1 OFF PCNTO bp1 1 OFF PCNTO bp5 0 9 3 2 Clamping Circuit This block clamps the input video signal CVBSO CVBS1 o Vidio in I External circuit CVBS0 1 Clamping Circuit Figure 9 5 Clamping Circuit ADDATA 7 0 Control circuit Data slice circuit Sync separator The clamping circuit internal to the MN102H75K 85K provides three current sources high medium and low You can modify these current sources using external resistors R1 and R2 Within the clamping circuit you can turn each of the current sources on and off in steps The control bits for these currents are the same for sync tip and pedestal clamping but the reference and compare levels are dif ferent Table 9 3 provides these values for the two types of clamping and table 9 4 shows how to control the three current levels so that the video signal matches the reference level Table 9 3 Clamping Reference and Compare Levels Compare Level CCDO CCD1 Output from minimum detection circuit value in SYNOMIN 007 8 bits 6 0 Output from minimum detection circuit value in SYNCMINW x 00
91. 10 TM4IOB P2MD12 11 Reserved 2 013 0 Port input 00 10 1 Port output P2DIR6 SBO1 01 PCNTO bit 13 ODASCI1 01 TMA4IOA output 10 0 X 0 Port low output 1 Port high output 00 P26 lt P2OUT6 SBO1 TM4IOA P2IN6 lt fj Schmidt trigger Figure 11 10 P25 TM4IOB SBI1 SBD1 and P26 TM4IOA SBO l Port 2 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 261 Panasonic I O Ports 1 0 Port Circuit Diagrams 0 Pullup off 5 1 Pullup lt gt P5PUP5 P 0 P55 1 SBO0 c P5MD5 FEX J 0 Port input 1 Port output lt P5DIR5 0 Push pull PCNTO bit i2 1 Open drain ODASCIO Egr T L gt SBO0 E L Pin I 7 M 0 Port low output U 1 Port high output ol X lt gt P5OUT5 P55 SBO0 P5IN5 lt 1 Schmidt trigger SBI0 lt 0 Pullup off 1 Pullup on lt P5PUP6 lo 0 P56 1 SBIO SBDO lt gt 5 6 0 Port input 1 Port output c BRUM P5DIR6 0 M 0 3 line SBIO SBOO SBTO U PCNTO bit 10 1 2 line SBDO SBTO 1 SIFSEL0 aly 1 5 800 5 2 M
92. 10 9 8 7 6 4 3 2 1 0 EP STS LRB AAS LAB BB D7 D6 D5 D4 D3 D2 DI DO Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R The I2CDREC register contains the status bits for monitoring the device and the reception data DDCDREC is a read only register MODE 1 0 2 device mode This field indicates which mode the microcontroller is in MODEI indicates slave or master and MODEO indicates receiver or transmitter If the microcontroller loses an arbitration or if a stop condition occurs the hardware clears MODE 1 0 to b 00 00 Slave receiver 10 Master receiver 01 Slave transmitter 11 Master transmitter STS Stop condition at slave receiver Set to 1 when a stop condition is detected while the microcontroller is in slave receiver mode LRB Last received bit Stores the last serial data bit received LRB normally indicates the ACK cycle data AAS Addressed as slave Set to 1 when the slave address on the bus matches the contents of the address register or matches the general address x 00 AAS resets after a read from the IZCDREC register LAB Lost arbitration bit Setto 1 when the microcontroller loses a bus arbitration LAB resets when I2CDTRM indicates a start condition STA 1 BB Bus busy bit A start condition on the bus sets this flag to 0 and a stop condition resets it to 1 The microcontroller considers the bus to be busy as long as BB 0 D 7 0 Received data The
93. 10 9 8 7 6 5 4 ST 51 50 E 2 1 Cx NX 2 ZF Rest 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST Saturation This bit controls whether or not the CPU calculates a saturation limit for an operation When it is set to 1 the CPU executes a saturate operation and when it is 0 the CPU executes a normal operation The PXST instruction can reverse the meaning of this bit for the next and only the next instruc tion S 1 0 Software control These bits are the control field for OS software It is reserved for the OS IE Interrupt enable If set this flag enables maskable interrupts if reset it disables them IM 2 0 Interrupt mask level This field indicates the mask level from 0 to 7 of interrupts that the CPU will accept from its seven interrupt input pins The CPU will not accept any interrupt from a pin at a higher level than that indicated here VX Extension overflow If the operation causes the sign bit to change in a 24 bit signed number this flag is set otherwise it is reset CX Extension carry flag If the operation resulted in a carry into from addition or a borrow out of from subtraction or a comparison the most significant bit this flag is set otherwise it is reset MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 21 Panasonic General Description MN102H Series Description NX Extension negative flag If the most significant bit of the result of an
94. 160 7 5 Example Graphics VRAM 161 7 6 Example Text VRAM Settings 20 05 55 psig pesan aaa 163 7 1 Bit Allocation in Internal 2 165 7 8 Color Palette Registef8 csbeoprpbernrs9enEksee6cke ere ES RIED ERIGI RESPON Ee RD RE 178 7 9 RGB and YS Output Control 181 7 10 OSD Dot Clock Source 193 7 11 OSD Dot Clock Division 1 193 7 12 Bit Settings for Controlling the Shuttered Area 194 7 13 Bit Settings for Controlling Shutter 1 2 2 196 7 14 Bit Settings for Controlling Shuttering 198 7 15 EOMON Output Cruterl S ner CENE E ER ere PE TERIS 202 7 16 Cursor Vertical Size Setting Sie aac oe dae CS RI AE T Da ID AIR etes 205 7 17 Graphics Vertical Size 206 7 18 Text Vertical Size Settings cca eR e Re RS EAR ER E 206 8 1 Logic Level Conditions for Data
95. 4 4 4 TM4 NLD zm m UDI UDO ONE MDI MDO ECLR LP ASEL S2 SI 50 This step stops the 4 count and clears both TM4BC Un v iu i A sque SE miss ssp and the S R flip flop to 0 2 Setthe divide by ratio for timer 4 To divide timer 0 underflow by 5 write x 0004 to timer 4 compare capture register A The valid range for is x 0001 to x FFFE example x 00FE84 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM4 4 4 TM4 4 4 4 4 4 TM4 4 4 4 4 TM4 TM4 15 14 CA13 CAI2 10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 Setthe phase difference for timer 4 For a phase difference of two timer 0 underflow cycles write 0001 to timer 4 compare capture register The valid range is 1 TMACB the TMACA value TMACB example x 00FE88 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM4 4 4 4 4 4 TM4 4 4 TM4 4 4 4 4 4 TM4 15 14 12 CB11 CB10 CB9 CB8 7 6 5 CB4 2 CBO
96. 4 3 2 1 0 TM4 TM4 4 4 4 4 4 4 4 TM4 4 4 4 4 4 TM4 15 14 12 CB11 CB10 CB9 CB8 CB7 6 CBS CB4 2 CBO Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 Write a dummy data word of any value to TM4CAX In double buffer mode is compared to TM4CAX The contents of TM4CA are loaded to TMACAX when TMABC TMACAX However since TMACAX is undefined or x 0000 before this operation starts this initial dummy write prevents timing errors 5 Write a dummy data word of any value to TMACBX In double buffer mode TMACB is compared to TMACBX The contents of TMACB are loaded to TMACBX when TMABC TMACBX However since TMACBX is undefined or x 0000 before this operation starts this initial dummy write prevents timing errors 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 97 Panasonic Timers 16 Bit Timer Setup Examples 6 Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0 This enables and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 7 Set TM4NLD and TMAEN to 1 This starts the timer Counting begins at the start of the next
97. Bit 7 6 5 4 3 2 1 0 IQ4LV2 IQ4LV1 IQ4LV0 IQ4IE Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R R R R W IQ4ICH sets the priority level for and enables external interrupt 4 It is an 8 bit access register Use the MOVB instruction to access it IQ4LV 2 0 External interrupt 4 interrupt priority level Sets the priority from 0 to 6 IQ4IE External interrupt 4 interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 52 Panasonic Interrupts Interrupt Control Registers IQ5ICL External Interrupt 5 Interrupt Control Register Low x 00FC5A Bit 7 6 5 4 3 2 1 0 R 105 Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R IQSICL requests and verifies interrupt requests for external interrupt 5 It is an 8 bit access register Use the MOVB instruction to access it IQ5IR External interrupt 5 interrupt request flag 0 No interrupt requested Interrupt requested IQ5ID External interrupt 5 interrupt detect flag 0 Interrupt undetected Interrupt detected External Interrupt 5 Interrupt Control Register High x 00FC5B Bit 7 6 5 4 3 2 1 0 IQSIE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W IQSICH enables external interrupt 5 It is an 8 bit access register Use the MOVB instruction to access it The priority lev
98. Control Code ID Code 11 CHSZ 1 0 Specifies the H size of the characters on the next line 00 1 dot 1 VCLK period 01 1 dot 2 VCLK periods 10 1 dot 3 VCLK periods 11 1 dot 4 periods CSHT Specifies shutter operation for the next line Setting this bit to 1 disables the shuttering function You can disable and enable shuttering on a line by line basis 0 Enable 1 Disable CHP 9 0 Specifies a VCLK indicating the horizontal start position for the next line 1024 steps are available CVP Character Vertical Position Control Code ID Code 11 CLAST Specifies the last line in the internal RAM text layer This resets the line pointer for character reads from the internal RAM to the first line 0 Disable 1 Enable CVSZ 1 0 Specifies the V size of the characters on the next line 00 1 dot 1 H scan line 01 1 dot 2 2 H scan lines 10 1 dot 4 H scan lines 11 1 dot 6 H scan lines CINT Specifies an OSD interrupt 0 Disable 1 Enable CVP 9 0 Specifies an H scan line indicating the vertical start position for the next line 1024 steps are available Graphics Layer GTC Graphic Tile Code ID Code 00 GCBF Repeat blank repeat tile select 0 Repeat blank 1 Repeat tile 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 167 Panasonic 5 Display 3 0 Specifies the number of times up to 16 a blank or graphic tile i
99. Counter Data Register 0 x 007EB4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HCD HCD HCD HCD HCD HCD HCD HCD HCD HCD 90 80 70 60 50 40 30 20 10 00 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R HCD 90 00 Count from HIO source signal This field stores the HIO clock source count It becomes x 3FF on over flow HCD1 H Counter Data Register 1 x 007EB6 Bit 15 14 13 12 11 10 9 8 7 6 5 4 9 2 1 0 HCD HCD HCD HCD HCD HCD HCD HCD HCD HCD 91 81 71 61 51 41 31 21 11 01 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 HCD 91 01 Count from HI1 source signal This field stores HI1 clock source count It becomes x 3FF over flow MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 311 Panasonic Register Appendix ARegister Table A 1 Register Map x 007E00 to x 007FFF Registers in this area cannot be written by byte only by word 20 4 LSBs D ription MSBs F E D C B A 9 8 7 6 5 4 3 2 1 0 escriptio CRM CRI3 CRI2 CRI VBI SL 007 00 Faw FQW CAPDA ACQ1 IRQ HNUM SLSF SLHD MAX MIN Gy FC 007 10 FCPNUM STAP DATAE DATAS CRI2E CRI2S CRI1S VBI 1 registers CRM CRI3 CRI2 CRI1 SL 007E20 Faw Faw Faw Faw CAPDAW ACQ1W w OW minw CNT FCW W W w Ww w VBI 2 registers 0
100. E Sco Sco TEN REN BRE DCS PTL OD DCM LN 2 PTYO SB 51 50 Setting 1 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 To enable serial 0 transmission end interrupts Cancel all existing interrupt requests Next set the interrupt priority level of 5 in the ANLV 2 0 bits of the ANICH register set the SCROIE bit of SCROICH to 1 and set the SCROIR bit of SCROICL to 0 From this point on an interrupt request is generated whenever a serial data reception ends ANICH example x 00FC81 Bit 7 6 5 4 3 2 1 0 ANLV2 ANLVO Setting 0 1 0 1 0 0 0 0 SCROICL example x 00FC84 Bit 7 6 5 4 3 2 1 0 B sem _ _ scro ID Setting 0 0 0 0 0 0 0 0 SCROICH example x 00FC85 Bit 7 6 5 4 3 2 1 0 SCRO IE Setting 0 0 0 0 0 0 0 1 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 134 Panasonic Serial Interfaces Serial Interface Setup Examples 5 6 3 Setting Up the Serial Interface Clock This example demonstrates how to set up a 19 200 bps transfer clock for the UART interface by using timer 1 to divide Bosc 4 by 39 The example uses the following settings Bosc 24 MHz Clock source timer 1 underflow x 1 8 Transfer clock baud rate x 8 The serial interface determines the baud rate from the 8 bit underflow Set up the
101. Fe gt max min 2 of this interval slice level computed in the hardware CRIS CRHE Figure 9 9 Data Slice Level Calculation 102 75 75 85 85 1 81 User Manual Panasonic Semiconductor Development Company 233 Panasonic Closed Caption Decoder Functional Description Table 9 7 provides the registers used to control and monitor the data slicer See the page number indicated for register and bit descriptions Table 9 7 Control Registers for Data Slicer CCDO CCD1 Register Page Address Address Description CRI1S 240 x007E10 x007E30 CRI capture start timing control register 1 CRHE 241 x007E12 x 007E32 CRI capture stop timing control register 1 MAXMIN 238 x007E02 x007E22 CRI interval maximum and minimum register SLICE 238 007 04 x 007E24 VBI data slice level register FCONT 237 x 007E00 x 007E20 VBI decoding format select register 9 3 5 Controller and Sampling Circuit The control circuit contains the CRI window generator and the caption data window generator The sampling circuit extracts the 16 bit caption data 503 kHz from the serial data output from the data slicer at the 12 MHz ADC sampling rate Table 9 8 provides the registers used to control and monitor these two blocks See the page number indicated for register and bit descriptions Table 9 8 Control Registers for Controller and Sampling Circuit
102. Manual Panasonic Semiconductor Development Company 83 Panasonic Timers 6 Bit Timer Setup Examples 4 5 2 Setting Up an Interval Timer Using Timers 1 and 2 In this example timers 1 and 2 cascaded to divide Bosc 4 by 60 000 and generate an underflow interrupt 16 bit timer Bosc 1 4 gt 1 2 Timer 2 24 MHz underflow Divide by 4 Divide by 60 000 lt 60 interrupt Figure 4 11 Configuration Example of Interval Timer Using Timers 1 and 2 P2 CORE ROM RAM P4 P6 Interrupts Bus Controller P5 Timers 0 3 Serial I Fs Timers 4 5 ADC Figure 4 12 Block Diagram of Interval Timer Using Timers 1 and 2 Disable timer 1 and 2 counting in the timer 1 and 2 mode registers TMIMD TM2MD This step is unnecessary immediately after a reset since TMIMD and TM2MD reset to 0 TM1MD example x O0FE21 Bit T 6 5 4 3 2 1 0 TMI TMI TMI TMI EN LD 51 50 Setting 0 0 0 0 0 0 0 0 TM2MD example x 00FE22 Bit 4 3 2 1 0 TM2 TM2 TM2 TM2 EN LD SI 50 Setting 0 0 0 0 0 0 0 0 2 Cancel all existing interrupt requests and enable timer 2 underflow inter rupts To do this set the TM2UDLV 2 0 bits of TM2UDICH priority level 4 in this example set the TM2UDIE bit to 1 set the TM2UDIR bit of TM2UDICL
103. P60 1 1 selects SCL0 0 selects P61 PONTO x 00FF90 8 1 enables SDAO SCL0 0 disables SDAO SCL0 9 0 disables SDA1 SCL1 1 enables SDA1 SCL1 Port control register 0 x 00FF90 bit 8 IPCSELO Ph o e spac IPCSELO SDA IN uum x 00FF90 bit 9 SDA1 SDA OUT Port control register 0 X O0FF90 bit 8 2 I2CSEL0 Circuit E secto I2CSELO SCLIN x 00FF90 bit 9 SCL OUT Figure 13 5 Pin Control Circuit for the I C Bus Controller Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 298 Panasonic I C Bus Controller SDA and SCL Waveform Characteristics 13 5 SDA and SCL Waveform Characteristics Figure 13 6 and table 13 5 provide the timing definitions and specifications for the for the MN102H75K 85K 1 bus interface A A X SDA L3 1 tsu STA 4 lup DAT I tsu DAT 1 m SU i I tsu STO SCL fv Loy 7 b Hi mp mem n EET luxSTA tow fr tman tr Figure 13 6 SDA and SCL Waveforms Table 13 5 SDA and SCL Waveform Characteristics Parameter Symbol Min Max Unit SCL clock frequency 0 100 kHz Bus free time between a stop and start condition tBUF 20 us Hold time repeated start condition tHD STA 4 0 Low period of the SCL clock tr ow 4 7 High period of the SCL clock tHIGH 4 0
104. Pin 0 Port low output U x 1 Port high output 0 x c P5OUT6 P56 SBIO SBDO 6 lt al Schmidt trigger Figure 11 11 P55 and P56 Port 5 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 262 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on c P5PUP7 lo 0 P57 1 SBTO lt P5MD7 0 Port input 1 Port output lt gt P5DIR7 0 Push pull 1 Open drain PCNTO bit12 For mode ODASCIO SBTO output 0 low outut 1 Port high output lt gt P5OUT7 X EM B P5IN7 SBTO input lt Schmidt trigger Figure 11 12 57 5 0 Port 5 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 263 Panasonic I O Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on c POPUP2 0 P02 1 SCL1 c POMD2 0 Port input 1 Port output lt PODIR2 J 0 Port lo
105. R R R W R R R R VBIWICL detects and requests VBI 2 interrupts It is an 8 bit access reg ister Use the MOVB instruction to access it VBIWIR VBI 2 interrupt request flag 0 No interrupt requested Interrupt requested VBIWID 2 interrupt detect flag 0 Interrupt undetected Interrupt detected VBIWICH VBI 2 Interrupt Control Register High x 00FC6F Bit 7 6 5 4 3 2 1 0 VBIW IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W VBIWICH register enables VBI 2 interrupts It is an 8 bit access register Use the MOVB instruction to access it The priority level for VBI 2 interrupts is written to the TMSCBLV 2 0 field of the TMSCBICH register VBIWIE VBI 2 interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 58 Panasonic Interrupts Interrupt Control Registers TM2UDICL Timer 2 Underflow Interrupt Control Register Low x 00FC70 Bit T 6 4 3 2 1 0 TM2UD TM2UD E 7 ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R TM2UDICL register detects and requests timer 2 underflow interrupts It is an 8 bit access register Use the MOVB instruction to access it TM2UDIR Timer 2 underflow interrupt request flag 0 No interrupt requested 1 Interrupt requested TM2UDID Timer 2 underflow interrupt detect flag
106. R W R W R W R W POMD is an 8 bit access register POMDT POMD6 POMDS POMD4 POMD3 POMD2 POMD1 POMDO P07 function switch 0 07 1 ADIN4 P06 function switch 0 06 1 ADIN3 P05 function switch 0 05 1 ADIN2 P04 function switch 0 P04 1 ADINI function switch 0 1 ADIN0 P02 function switch 0 P02 1 SCLI P01 function switch 0 P01 1 SDAI P00 output switch x O0FFFO Control the IRQO interrupt enable settings in the interrupt control registers 0 POO0 RMIN IRQO 1 RMIN IRQO MNI02H75K F75K 85K F85K LSI User Manual 279 Panasonic Panasonic Semiconductor Development Company Ports I O Port Control Registers P1MD Port 1 Output Mode Register x O0FFF2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIMD PIMD PIMD PIMD PIMD PIMD PIMD PIMD PIMD m PIMD nA PIMD a PIMD 14 13 12 11 10 9 8 7 6 4 2 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R RW RW RW RW RW RW RW RW RW R R W R R W R R W 1 is a 16 bit access register P1MD14 P17 output switch 0 P17 1 PWM2 P1MD 13 12 P16 output and function switch 00 P16 01 ADINI1 10 PWMI 11 Reserved P1MD 11 10 P15 output and function switch 00 P15 01 ADINIO 10 PWMO 11 Reserved P1MD 9 8 P14 output and function switch 00 P14 01 ADIN9 10 STOP 11 Reserved P1MD 7 6 P13 output switch 00 P13 01 AD
107. RW RW RW RW RW Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 206 Panasonic 5 Display OSD Registers CIVSZ 1 0 Text initial vertical size Table 7 18 Text Vertical Size Settings CIVSZ 1 0 1 Dot Size Setting Interlaced Displays Progressive Displays 00 1 H scan line Reserved 01 2 H scan lines 1H scan line 10 4 H scan lines 2H scan lines 11 6 H scan lines 3 H scan lines CIVP 9 0 Text initial vertical position EVOD Display Start Field Control Register x 007F0E Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FREG FREG FREG FREG FREG FREG FREG FREG SEL MON MON 23 22 21 20 13 12 10 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R W R R R R R EOSEL Even odd field select 0 Select the smaller counter value as the display start field 1 Select the larger counter value as the display start field FRMON Field register monitor Monitors which field register FREG loaded the counter value on the leading edge of VSYNC 0 Loaded FREG 23 20 1 Loaded to FREG 13 10 EOMON Even odd field monitor Set between display fields 0 No display start field detected 1 Display start field detected FREG 23 20 Field register 4 bit register 2 storing field counter value FREG 13 10 Field register 4 bit register 1 storing field counter value
108. Register Page CCDO Address CCD1 Address Description Registers for detecting CRI and generating sampling clock CRI2S 241 x 007E14 x 007E34 CRI capture start timing control register 2 CRI2E 241 x 007E16 x 007E36 CRI capture stop timing control register 2 CRIFA 240 x 007EOC x 007E2C CRI frequency width register A CRIFB 240 x 007EOE x 007E2E CRI frequency width register B Registers for contr olling data capture DATAS 241 x007E18 007 38 Data capture start timing control register DATAE 242 x 007E1A 007 Data capture stop timing control register CAPDATA 239 007 007 2 Caption data capture register HNUM 239 x 007E06 x 007E26 HSYNC count register Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 234 Panasonic Closed Caption Decoder Functional Description 9 3 5 1 CRI Detection for Sampling Clock Generation The decoder captures the caption data on the rising edge of the CRI pulse To achieve this it contains a circuit to accurately detect the CRI pulse rises and to generate a data sampling clock CRI Data 21HSYNC X X X T L CRI2S CRI2E h RI detection j _ This interval determines the sampling clock timing Figure 9 10 Sampling Cl
109. SCMING Minimum Sync Level Detection Interval Set Register x 007EC4 SCMINGW x 007EE4 Bit 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 SC SC SC SC SC SC SC SC SC SC MING MING MING MING MING MING MING MING MING MING 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 R W R R R R R R RW RW RW RW RW RW RW RW RW RW SCMING 9 0 Interval setting for the minimum sync level detection Set the HSYNC cycle in this field in ADC clock units This is the interval used for detecting the sync tip level for sync tip clamping The valid range is X 000 to x 3FF Note that the HSYNC cycle set in this register is only used for detecting the minimum sync level You must also set the correc tion HSYNC cycle in HSEPI For the NTSC format the setting for this register is 2 calculated as follows A D sampling frequency x HSYNC cycle 12 MHz x 63 us x 02FA BPPST Backporch Position Register x 007EC6 BPPSTW x 007EE6 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BP BP BP BP 5 8 PST7 PST6 PST5 PST4 PST3 PST2 PSTI PSTO Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 R R R R R R RW RW RW RW RW RW RW RW RW 57 8 0 Backporch start position for the leading edge of HSYNC MNI02H75K F75K 85K F85K LSI User Manual Panasonic S
110. TMO TMO EN LD 51 50 0 0 0 0 0 0 0 0 3 Cancel all existing interrupt requests and enable timer 0 underflow inter rupts To do this set the TM2UDLV 2 0 bits of TM2UDICH priority level 4 in this example set the TMOUDIE bit to 1 and set the TMOUDIR bit of TMOUDICL to 0 Note that you set the priority level for timer 0 interrupts in the timer 2 interrupt control register From this point on an interrupt request is generated whenever timer 0 underflows TM2UDICH example x 00FC71 7 6 5 4 3 2 1 0 TM2UD TM2UD TM2UD _ 20 Lv2 IV Lvo IE Setting 0 1 0 0 0 0 0 0 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 82 Panasonic Timers 8 Bit Timer Setup Examples TMOUDICL example x 00FC74 Bit 7 6 4 3 2 1 0 _ TMouD IR ID Setting 0 0 0 0 0 0 0 0 TMOUDICH example x 00FC75 Bit 7 6 5 4 3 2 1 0 TMOUD IE Setting 0 0 0 0 0 0 0 1 4 Setthe divide by ratio for timer 0 Since the timer will count 4 TMOIO cycles write x 03 to the timer 0 base register TMOBR The valid range for TMOBR is 0 to 255 TMOBR example x 00FE10 Bit 7 6 4 3 2 1 0 TM0 TM0 TM0 TM0 TM0 TM0 TM0 TM0 BR7 BR6 BR5 BR4 BR3 BR2 BRI BRO Setting 0 0 0 0 0 0 1 1 5 Setthe TMOLD bit of the TM
111. a 16 bit access register MODAUTO Automatic operating mode detection on off 0 Automatic detect 1 Fixed MODSEL Operating mode select 0 HEAMA format 1 5 6 bit format FILTRE Noise filter input multiplexer on off 0 Pin level 1 Noise filter POLSEL Input polarity 0 Positive edge triggered 1 Negative edge triggered LEADERE Interrupt enable for leader detection 0 Disable 1 Enable TRAILRE Interrupt enable for trailer detection 0 Disable 1 Enable DATS8E Interrupt enable for 8 bit data reception detection 0 Disable 1 Enable EDMEE Interrupt enable for RMIN pin edge detection 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 224 Panasonic Remote Signal Receiver IR Remote Signal Receiver Control Registers RMIS Remote Signal Interrupt Status Register x 007EA0 Bit 7 6 5 4 3 2 1 0 BC BC FMT DOMES MS6BIT TRAILR DAT8 EDGE RSTE EDGS MON D D D D D Reset 0 0 0 0 0 0 0 0 R W R W R W R R W R W R W R W R W RMIR indicates the detection and operation status of remote signal inter rupts It is a 16 bit access register BCRSTE 8 bit data reception binary counter reset enable 0 Disable 1 Enable BCEDGS 8 bit data reception binary counter reset edge select 0 Reset at Ist edge 1 Reset at 2nd edge FMTMON Format monitor 0 HEAMA format 1 5 6 bit format DOMESD Interrupt reques
112. associated bit PEDUP XPEDUP CLPP or SAFEP is 0 CLPP High clamping control pulse for high current source P channel CLPN High clamping control pulse for high current source N channel XPEDUP Clamping control pulse for medium current source P channel XPEDOWN Clamping control pulse for medium current source N channel PEDUP Clamping control pulse for low current source P channel PEDOWN Clamping control pulse for low current source N channel SBFNUM Sampling Start Position Register x 007E4C SBFNUMW x 007E6C Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SBF SBF SBF NUM NUM NUM NUM NUM NUM NUM NUM NUM NUM NUM 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R SBFNUM 10 0 Detected position of start bit flag detected by the hardware TESTA Test Register 13 12 11 10 9 8 7 6 5 x 007E4E x 007E6E 1 0 SLICE 5 SLICE 4 SLICE 3 SLICE 2 SLICE 1 SLICE 0 DATA CRI2G CRIIG ACQG SLD SAMP FCPIN FCP SLD TESTA Bit 15 14 SLICE SLICE 7 6 Reset 0 0 R W R R 0 R 0 R R R R R R R R R R R R R SLICE 7 0 Slicing value either from hardw
113. byte Load the data to the serial port O transmit receive buffer The sequence for the first data byte repeats To set up the stop sequence 1 When all the data has been transmitted set the SCOIIC bit of SCOCTR to 0 Never perform this step during transmission 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 137 Panasonic Serial Interfaces Serial Interface Setup Examples Reception must be enabled for 2 When you perform step 1 the SBTO output signal goes high One cycle later the circ itto detocta stop the SBOO output signal also goes high signalling the stop sequence The sequence 3 SCOISP flag of SCOSTR becomes 1 The SCOIST and SCOISP flags are both cleared by a write to or read from the serial port 0 transmit receive buffer Figure 5 13 shows an example timing chart sequence output bit Write to 5 SBO0 output b7 5 2 bo Ack b7 be b5 bo4b3 b2 b1 bo ac f E Tx interrupt request Tx interrupt request SBTO output Start detection bit 1 i i i Stop detection bit 1 Start sequence Data tx 1 Data tx 2 Stop sequence Figure 5 13 Master Transmitter Timing in PC Mode with ACK P
114. bytes GROMEND 80x n 1 1 Code n graphics data GROMEND 80xn 16 color mode GROMEND 7 GROMEND 6 GROMEND 5 GROMEND 4 GROMEND FF Code 01 graphics data GROMEND 80 GROMEND Notes 1 Alladdresses are expressed in hex notation Other values are decimal 2 GROMEND Graphics ROM end address programmable to any address 3 CROMEND Text ROM end address programmable to any address 4 M Number of characters 1 5 m 0 and up 6 N Number of graphic tiles 1 16 color mode 7 n 0 and up Figure 7 9 ROM Organization Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 172 Panasonic 5 Display ROM 7 9 2 Graphics ROM Organization in Different Color Modes The graphics layer supports up to sixteen colors in the 16 color mode but also supports 2 4 and 8 color modes The smaller the number of colors the less ROM area required per tile The figures in this section illustrate the organi zation for each color mode The example in figure 7 10 demonstrates the graphics ROM setup for line 16 of the code 00 data when the graphics layer is in 16 color mode The four bits of data for each pixel in sheets 1 2 3 and 4 determine the color palette used for that pixel Graphics tile am 1908 NE Line 1 eet 414 Line 2 I5 Sheet 3 rine 3 Sheet 2 Sheet 1 Line 16 1dot 4bits 16 colors Bit 15 Bit 0
115. calculating the baud rate for the UART mode Table 5 2 shows the baud rate settings when Bosc 24 MHz Bosc baud rate bps aud rate bps 32 x timer divisor Table 5 2 Example Baud Rate Settings for the UART Mode Baud Rate Timer 0 1 Divide by Ratio 19200 39 9600 78 4800 156 909 1250 300 2500 5 5 Serial Interface Timing 5 5 1 Synchronous Serial Mode Timing In these timing charts the character length is 8 bits and there is parity Tx SBO bo b1 b2 b3 b4 b5 b6 b7 PTY SBT Data write TXBUSY Tx interrupt Figure 5 5 Synchronous Serial Transmission Timing MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 129 Panasonic Serial Interfaces Serial Interface Timing ca SBI SBT RXBUSY Rx interrupt RXA 1 when Rx data in Data read b1 b2 b3 b4 b5 b6 b7 L j4 E l pe Figure 5 6 Synchronous Serial Reception Timing 5 5 2 UART Mode Timing In these timing charts the character length is 8 bits the parity is none and the stop bit 15 2 bit Tx SBO Data write sr bo bi b2 o3 bo4 b5 b6 b7 sP sP TXBUSY
116. celeb qaspa bb od ae e EDI UR PR Seb 90 4 17 Single Phase PWM Output Timing 16 Bit 90 4 18 Single Phase PWM Output Timing with Data Change 16 Bit 91 4 19 Two Phase PWM Output Timing 16 Bit Timers 91 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 11 Panasonic List of Figures 4 20 One Shot Pulse Output Timing 16 Bit 91 4 21 External Count Direction Control Timing 16 Bit 92 4 22 Event Timer Input Timing 16 Bit 92 4 23 Single Phase Capture Input Timing 16 Bit 92 4 24 Two Phase Capture Input Timing 16 Bit 93 4 25 Two Phase 4x Encoder Timing 16 Bit 93 4 26 Two Phase 1x Encoder Timing 16 Bit 93 4 27 Block Diagram of Event Counter Using 4 94 4 28 Event Counter Timing Timer 4 0 1 5 2 2 95 4 29 Block Diagram of Single Phase PWM Outp
117. clock after ANEN is set The conversion time is 12 cycles of the ag to 1 9 ADC clock When Bosc 24 MHZ this is 4 0 us or 4 0us 4 3 us after ANEN is set The ADC can also generate an 3 Wait for the conversion to end Since ANEN remains high during conver interrupt when the conversion ends once the data is stored in AN6BUF In this case the software does not need to wait sion then clears to 0 the program must wait until ANEN is 0 4 Read the ADIN6 conversion data buffer AN6BUF The converter divides 0 for the ANEN flag before reading to 3 3 volts into 256 segments so the digital result is a value from 255 AN6BUF MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 147 Panasonic Analog to Digital Converter ADC Setup Examples AN6BUF example 00 14 15 14 13 12 11 10 9 8 7 6 2 4 3 2 1 0 ANn ANn ANn ANn ANn ANn ANn ANn BUF7 BUF6 5 BUF4 BUF3 BUF2 BUFI BUFO ANCTR aoa EI set c cule 270 DIT e T 3 ANEN State LU UU VALID ANGBURT 10 pad qe dp 2b 5 55 Interrupt M Figure 6 9 Timing of Software Controlled Single Channel A D Conversion 6 5 2 Setting Up Hardware Controll
118. core hardware MN102H Series Instruction Manual Describes the instruction set MN102H Series C Compiler User Manual Usage Guide Describes the installation commands and options for the C compiler MNIO2H Series C Compiler User Manual Language Description Describes the syntax for the C compiler MNIO2H Series C Compiler User Manual Library Reference Describes the standard libraries for the C compiler MN102H Series Cross Assembler User Manual Describes the assembler syntax and notation MNIO2H Series C Source Code Debugger User Manual Describes the use of the C source code debugger MN102H Series Installation Manual Describes the installation of the C compiler cross assembler and C source code debugger and the procedures for using the in circuit emulator Figure 1 5 shows the address space for the MN102H75K The internal ROM contains the instructions and the font data for the on screen dis play OSD in any location The internal RAM contains the MCU data and the VRAM for the OSD in any location Figure 1 5 shows the address space for the MN102H75K 85K The internal ROM contains the instructions and the font data for the on screen display OSD in any location The internal RAM contains the MCU data and the VRAM for the OSD in any location VO ports Package 84 pin QFP 66 MN 2H75KIF75K 1 2 85 pin QFP MN102H75K F7
119. cycle Timer 4 can output a single phase PWM signal at any duty You must select up counting Timer 4 does not operate in STOP mode when Bosc is off If you use an external clock it must be synchronized to Bosc In this procedure you set the cycle x 0001 to x FFFE in TM4CA register and the duty in the TMACB register When the contents of TM4BC match those of the TM4CB register the S R flip flop resets at the beginning of the next cycle Please note the following When 1 lt TM4CB lt TMAOA output is low during the 0 to TMACB 1 cycles of the TM4CA 1 cycle period and high during the remainder of the cycles When TM4CA lt TMACB lt x FFFE TM4OA output is always low When TM4BC x FFFF output is always high The circuitry is configured so that there are no waveform errors even when the output is always high or always low Counting begins after the TM4EN bit is set in the TM4MD register Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 98 Panasonic Timers 16 Bit Timer Setup Examples Figure 4 30 below shows the output waveforms for TM4OA Both and B interrupts can occur but B interrupts can only occur if the TM4CB setting is from 0 to less than TM4CA This is because when TM4CB lt TM4BC never matches TM4CB
120. data into the LSB of the reception data shift register RMSR After it receives 8 bits it loads the contents of RMSR to the reception data transfer register RMTR Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 216 Panasonic Remote Signal Receiver Block Diagram VV3200X H LINH 0 116 6 7 5 91 weibeig 19419994 euDiS louu ti 1 8 nB d iq 940400 0v3700X SIINH 011 _ 2 1 5 d 11 1480 10 8 Toyunoo am E uonoejep jeuDis ajowey 0V3200X HIINH io rfe e v s o 7 19 UnOO 10 9 o rTe e v so 7 a 8V3400 X HSINH S 3 x ror o uollo l p uono l p uono l p uono l p 9 0 ea lepee m yous gt M9 MO 19 9 5 MO VIAV3H 9 N 5 9 Jejuno a 9V3400X s 558 uodn 50015 jddns 490 9 s rz ZH SZE 5 ENMd 1 AUe Odg uono l p enjeA 19junoo Mo JjaAQ Jejunoo 16 9 lt s 12 39 1911 SION d P3 yO mi
121. dds VENICE ERE 300 13 6 1 Setting Up a Transition from Master Transmitter to Master Receiver 300 13 6 1 1 Pre confIgurings x es e Seq a a a RR Ue DURER RU t 300 13 6 1 2 Setting Up the First 1 300 13 6 1 3 Setting Up the Second 1 301 13 6 1 4 Setting Up the Third Interrupt 00 ee eee eee 301 13 6 2 Setting Up a Transition from Slave Receiver to Slave 302 13 6 2 1 Pre configuting jasc he tee Wah ea aed ae Rog bn e ORTU AER ane 302 13 6 2 2 setting Up the First Interrupt se sete Re o 302 13 6 2 3 Setting Up the Second 2 303 13 6 2 4 Setting Up the Third 303 13 7 PC Bus Interface RESISters d PC P UI LEES 304 14 is e IRI RES EE AR UAR MUR Eu Sa SE EUR e 307 14 1 Description E TU b a cha d oec 307 14 2 Block Diagramas ay a E EISE MAUS PORE RE e REL RIA Ere aha 307 14 3 H Count r Operation re euch eA e IRR RAT GR RR IRR SR LR as 307 14 4 Counter Control Registers 1
122. effect Outlining Shadowing foreground and background Blinking In closed caption mode Italics Underlining Repeated tile or blank Selects one tile from the graphic tile area 16 x 16 Display position 1 dot resolution 1024 steps V 1H scan line resolution 1024 steps Maximum 60 characters 4 tiles in one line when using a 64 byte graphics line For example 1 If a graphics line contains 28 tiles then the corresponding line in the text layer can only contain 32 characters 2 If a text line contains 38 characters then the corresponding line in the graphics layer can only contain 22 tiles 2 Maximum 38 characters per line 60 characters tiles with the default text colors Each color assignment including outlining and blinking decreases this total by one 3 The maximum number of tiles per line is programmable in the GEXTE bit of the OSD2 register 18 tiles requires 40 bytes per line and 28 tiles requires 64 bytes per line The setting applies to all lines 4 Multiple modes cannot be used simultaneously the color mode applies to the entire display 5 The OSD dot clock frequency controls the horizontal position and size For details see section 7 9 4 Setting Up the OSD Dis play Position on page 180 and section 7 11 Selecting the OSD Dot Clock on page 186 6 This function be used for a wallpapering effect or to insert spaces One tile code can be repeated up to 16 times Repe
123. every VSYNC Speed control shared bits 01 Move every 2 VSYNCs 10 Move every 3 VSYNCs 11 Move every 4 VSYNCs Considerations for horizontal shutter movement Do not set the horizontal shutter position HSTO HST1 within the following ranges if you are only moving the horizontal shutter The shutter cannot move if you do x 000 to x 003 and x 3FC to x 3FF You can set these values if you wish to prevent horizontal shutter movement Note that the horizontal shutter position does not affect vertical movement Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 196 Panasonic 5 Display Controlling the Shuttering Effect HSHT0 Television screen VSHT1 VSONO VSON1 1 V shutters 0 and 1 on HSONO 5 1 1 H shutters 0 and 1 on VSPO 1 V shutter 0 shutters above VSP1 0 V shutter 1 shutters below HSP0 1 shutter 0 shutters to the left 0 shutter 1 shutters to the right SHTRAD 1 All shutters ORed Shuttered region This example shows V shutter 0 moving downward It shutters both the text and the background color in the text layer VSHTO VSHT1 VSHTO VSHT1 VSHT1 VSHTO VSMO 1 V shutter 0 movement enabled VSM1 0 V shutter 1 movement disabled HSM0 HSM1 1 Movement enabled for H shutters 0 and 1 VSMPO0 0 V shutter 0 moves downward SHTSPO SHTSP1 0 Shutter moves 1 HSYNC each VSYNC You must se
124. external location This enables system level examination of the internal status even with the mask ROM version To use the ROM correction function embed a routine such as that shown in figure 12 2 in the ROM I I I R M I u 5 ROM correction required I I Yes Necessary BOM ROM software settings I I address correction Set up the correction data I I 1 1 Instruction Instruction Enable the counter fetch correction function I L p CPU ns Figure 12 1 ROM Area Schematic Diagram Figure 12 2 ROM Correction Flow As figure 12 1 shows the function lies between the microcontroller and ROM blocks First set the correction data for any sixteen non OSD addresses in the ROM correction address match and data registers Follow the flow shown in figure 12 2 Once this is done the circuit will correct the ROM output for the designated addresses Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 288 Panasonic Correction Block Diagram 12 2 Block Diagram Figure 12 3 is a block diagram of the ROM correction circuit match detection circuit constantly monitors the ROM address specified by the CPU instruction pointer IP When the value matches a correction address the circuit replaces the data output from the ROM with the data in the appropriate correction data register It then sends the
125. feeds directly to the CPU without going through the PLL circuit This means that the program must switch the CPU from SLOW to NORMAL mode system clock 12 MHz For information on invoking SLOW mode from NORMAL mode see MN10200 Series Linear Addressing High Speed Version LSI User Manual For information on invoking SLOW mode from NORMAL mode see 102 Series LSI User Manual The 102 75 allows you to turn each peripheral function on or off P75 through writing to the registers You can significantly reduce power consumption by turning off unused functions Table 3 1 shows the register bits controlling on and off for each function block The ADC used for the OSD and CCD functions is turned off on reset Write a 1 to the function to enable it when necessary The MN102H75K 85K allows you to turn each peripheral function on or off through writing to the registers You can significantly reduce power consumption by turning off unused functions Table 3 1 shows the register bits controlling on and off for each function block The ADC used for the OSD and CCD functions is turned off on reset Write a 1 to the function to enable it when necessary 102 75 75 85 85 LSI User Manual 3 Panasonic Panasonic Semiconductor Development Company The MN102H75K contains four 8 bit timers that can serve as interval timers event timer counters clock generators divide by 2 output of the underflow
126. field in this register tie it to the setting indicated below FCPSEL Hard soft sampling start position select 0 Select hardware calculation 1 Select software setting set in SFTSTAP 10 0 field of STAP SYNCSEL Sync signal select HSYNC VSYNC Tie this bit to 0 HONTSEL 1 0 HSYNC count value select When this field is unused tie it to b 00 00 When odd add 1 to the HSYNC count value 01 When even add 1 to the HSYNC count value 10 No change to the HSYNC count value 11 Reserved SLICESEL Hard soft slice level select 0 Select hardware calculation 1 Select software setting SLICELD 2 0 Slice level load timing select When this field is unused tie it to b 000 000 1H 100 1 field 001 2H 101 2 fields 010 4H 110 4 fields 011 8H 111 8 fields SLPULSEL Polarity select for the CRI cycle transition detection 0 Detect O to 1 transitions 1 Detect 1 to O transitions CRICSEL Detection interval select for the CRI frequency width 0 CRIcapture interval only 1 CRIcapture interval and transition detection interval NCRIGSEL Sampling pulse generation interval 0 Disable the CRI capture interval 1 Enable the CRI capture interval CNTSTAP 4 0 Caption data sampling start position The higher the setting in this field the later the start position The valid range is x 00 to x IF 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 237 Panasonic C
127. first cycle Do not change any other operating modes during this step 5 Set TM5NLD and TMSEN to 1 This starts the timer Counting begins at the start of the next cycle To enable timer 5 capture B interrupts Cancel all existing interrupt requests Next set the interrupt priority level in the TMSCBLV 2 0 bits of the TM5CBICH register levels 0 to 6 set TMSBIE bit to 1 and set the TMSBIR bit of TMSCBICL to 0 From this point on an interrupt request is generated whenever a timer 5 capture B event occurs 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 115 Panasonic Timers 16 Bit Timer Setup Examples To service the interrupts Run the interrupt service routine The routine must determine the interrupt group then clear the interrupt request flag Timer 5 can input a two phase encoder signal Timer 5 does not operate in STOP mode when Bosc is off If you use an external clock it must be synchronized to Bosc Table 4 5 shows the count direction for the timing diagram in figure 4 46 In down counting when the binary counter reaches 0 it loops to the value in 5 interrupt B occurs when the contents of TM5BC match those of 5 Table 4 5 Count Direction for 1x Two Phase Encoder Timing Example Up Counting Down Counting T
128. in the above line include HP VP N the number of display code in the below line include HP VP n N 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 171 Panasonic 5 Display 7 9 1 Organization Text ROM Addresses Text character Each character requires 36 bytes 1596 a Line 1 Line 2 Line 3 18 bits 080000 PS En M Line 18 CROMEND 24x M 1 1 Code M n FC 1 text data Bit 15 Bit 0 croveno 2s lnelbis7oO CROMEND 22 III ata CROMEND 24xm _ text data Area CROMEND IF EN 2 CROMEND 47 Code 01 CROMEND 24 text data OROMEND3 Code 00 CROMEND 1 1 CROMEND B4MAH CROMEND text data iN CROMEND lbyle y Graphics ROM Addresses Graphics tile 16 color mode CROMEND 4 16 bits Line 1 In 2 Sissi Line 2 requires ytes SMART Line 3 Sheet 2 GROMEND 80x N 1 1 heet 1 16 color mode Line 16 Graphics 77 GROMEND 80x N 1 1 1 dot 4 bits ROM Code N 16 colors graphics data GROMEND 80xN n GROMEND Bit 15 Bit 0 16 color mode GROMEND 7F Line 1 data 9887 Line 2 data GROMEND 70 GROMEND 6F Line data GROMEND 68 GROMEND 3 Sheet 3 bits 7 to 0 E FH GROMEND 10 GROMEND 2 Sheet 3 bits 15 to 8 GROMEND 7F B 7 GROMEND 0F 7 ine ata jae is 128 bytes GROMEND O 4 GROMEND 1 Line 16 data 8
129. in the closed caption mode 00 and 01 No box shadowing 10 Upper left white and lower right black shadows 11 Upper left black and lower right white shadows x 007F80 x 007F9E specifies the colors available for text foreground and background colors FRAME x 007FA2 specifies the color for outlining or character shadowing BBSHD x 007FA4 specifies the black color for box shadowing WBSHD x 007FA6 specifies the white color for box shadowing set up functions applying to all layers Write to the fields described below Color background function The color background function allows you to fill the television screen areas that are uncovered by the OSD display text graphics or cursor layers with any color Specify the color in the COLB register 007 0 COLB x 007F08 bit 7 enables the color background function when set to 1 COLB x 007FA0 specifies the color of the background Transparency The TRPT bit allows you to make the color 0 transparent in all the palettes CPTO GPT10 and GPT20 RGB and YS are all output at 0 levels for that color See figure 7 21 x 007F02 bit 10 0 Make color 0 on all palettes transparent 1 Output color 0 as specified 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 179 Panasonic On Screen Display Setting Up t
130. in the sequence to the ANNCH 3 0 field The sequence always begins with channel 0 When the software starts the conversion write a 0 to the ANTC bit disabling conversion start at timer 1 underflow then write a 1 to ANEN If ANTC 1 ANEN goes high upon a timer 1 underflow ANEN remains high during the con version then clears to 0 when the conversion sequence ends Note that the ANICH 3 0 field holds the number of the channel being converted It clears to 0 when the sequence ends Start Stop Interrupt request Ch 10 1 12 State conversio Conversion Conversion ANEN Figure 6 5 Multiple Channel Single Conversion Timing MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 145 Panasonic Analog to Digital Converter A D Conversion Timing 6 4 4 Single Channel Continuous Conversion Timing When ANMD 1 0 610 the ADC converts one ADIN input signal contin uously An occurs each time the conversion ends Load the number of the channel to be converted in the ANICH 3 0 field of the ADC control register ANCTR The ANNCH 3 0 field is ignored in this mode When the software starts the conversion write a 0 to the ANTC bit disabling conversion start at timer 1 underflow then write a 1 to ANEN If ANTC 1 ANEN goes high upon a timer 1 underflow ANEN remains high during the con version To end the A D conversion writ
131. interrupt request flag 0 No interrupt requested Interrupt requested IQ3ID External interrupt interrupt detect flag 0 Interrupt undetected Interrupt detected MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 51 Panasonic Interrupts Interrupt Control Registers IQ3ICH External Interrupt 3 Interrupt Control Register High x 00FC53 Bit 7 6 4 3 2 1 0 IQ3IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W IQ3ICH enables external interrupt 3 It is an 8 bit access register Use the MOVB instruction to access it The priority level for external interrupt 3 is written to the IQ2LV 2 0 field of the IQ2ICH register IQSIE External interrupt 3 interrupt enable flag 0 Disable 1 Enable IQ4ICL External Interrupt 4 Interrupt Control Register Low x 00FC58 Bit 7 6 5 4 3 2 1 0 IQ4IR IQ4ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R IQ4ICL requests and verifies interrupt requests for external interrupt 4 It is 8 bit access register Use the MOVB instruction to access it IQAIR External interrupt 4 interrupt request flag 0 No interrupt requested Interrupt requested IQ4ID External interrupt 4 interrupt detect flag 0 Interrupt undetected Interrupt detected IG4ICH External Interrupt 4 Interrupt Control Register High x 00FC59
132. libraries for the C compiler B MNIO2H Series Cross Assembler User Manual Describes the assembler syntax and notation B 2 Series C Source Code Debugger User Manual Describes the use of the C source code debugger B MN102H Series Installation Manual Describes the installation of the C compiler cross assembler and C source code debugger and the procedures for using the in circuit emulator MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 17 Panasonic General Description MN102H Series Overview 1 General Description 1 1 MN102H Series Overview The 16 bit MN102H series is the high speed linear addressing version of the MN10200 series The new architecture in this series is designed for C language programming and is based on a detailed analysis of the requirements for embedded applications From miniaturization to power savings it provides for a wide range of needs in user systems surpassing all previous architectures in speed and functionality This series uses a load store architecture for computing within the registers rather than the accumulator system for computing within the memory space which Panasonic has used in most of its previous major series The basic instructions are one byte one machine cycle drastically shrinking code size and improving compiler efficiency The circuit is designed for submicron technology providing optimized hardware and low system power co
133. low speed devices With a 12 oscillator the maximum setting is 100 kHz and the minimum setting is 10 kHz Bus state monitoring With the I2CBSTS register the IC bus controller determines the logic levels of the SCL and SDA lines 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 297 Panasonic Bus Controller Setting Up the Bus Connection 13 4 Setting Up the I C Bus Connection Set the IC connection in the I2CSELO and I2CSELI bits of the PCNTO register x OOFF90 Since the SCLO SDAO SCL1 and SDAI pins also serve as general purpose port pins and reset to the general purpose function you must set these bits every time the program uses the function You must also select the PC function in the port mode registers For bus connection 0 set bits 0 and 1 of the P6MD register x OOFFFC For PC bus connection 1 set bits 1 and 2 of the POMD register x OOFFFO Table 13 4 shows the register settings required to use either SDAO SCLO or SDA1 SCL1 alone and figure 13 5 shows the control circuit for this pin setup Table 13 4 Registers Settings for SDAO SCLO or SDA1 SCL1 Ports Register SDAO SCLO Only SDA1 SCL1 Only POMD x OOFFFO 1 0 selects 01 1 selects SDA1 2 0 selects P02 1 selects SCL1 P6MD x 00FFFC 0 1 selects SDAO 0 selects
134. mode I 16 bits gt 7 Linet heet 114 Line 2 Line 3 1 dot 1 bit 2 colors Line 16 ROMEND 1 Bit 15 Bit 0 Sheet 1 bits 7 to 0 ROMEND Sheet 1 bits 15 to 8 Figure 7 16 Graphics ROM Organization in 2 Color Mode 16W x 16H Tiles Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 176 Panasonic 5 Display ROM ROMEND 8F ROMEND 88 bine cata 16 bits ROMEND 87 Graphics tile Line 1 0 Line 2 data 16 color mode heet 4 Hn Line 3 data ee net ROMEND 7 ROMEND 7 Sheet 1 bits 7 to 0 heet 2 z ROMEND 6 Sheet 1 bits 15 to 8 heet 1 i 5 Sheet 2 bits 7 to 0 gt ROMEND 4 Sheet 2 bits 15 to 8 Line 18 ROMEND 10 ROMEND 3 Sheet 3 bits 7 to 0 16 colors ROMENDA data ROMEND 2 Sheet 3 bits 1510 8 ROMEND OF ROMEND 1 Sheet 4 bits 7 to 0 romeno Line 18 data 8 bytes Sheet 15108 1 byte Bit 0 Figure 7 17 Graphics ROM Organization in 16 Color Mode 16W x 18H Tiles ROMEND 5 Sheet 1 bits 7 to 0 1 dot 3 bite ROMEND 4 Sheet 1 bits 15 to 8 8 colors ROMEND 1 ROMEND 3 Sheet 2 bits 7 to 0 ROMEND 1B i I ROMEND 2 Sheet 2 bits 15 to 8 061 Line 17 data i ROMEND 205 ROMEND 1 Sheet 3 bits 7 to
135. occurs Timer 4 can operate as an event counter but timer 4 does not operate in STOP mode when Bosc is off If you use an external clock it must be synchronized to Bosc This means that the frequency of the event counter clock must be 1 4 or less that of the oscillator 6 MHz with a 24 MHz oscillator Figure 4 28 shows an example timing chart 0004 TM4CB 0001 TM4BC 0000 0001 0002 0003 0004 0000 0001 0002 0003 0004 h h h k 4 4 n TMAIB E um Rr d Rc M 72 Interrupts RENE ZEN EE 0 Figure 4 28 Event Counter Timing 4 MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 95 Panasonic Timers 16 Bit Timer Setup Examples 4 11 2 Setting Up a Single Phase PWM Output Signal Using Timer 4 In this example timer 4 is used to divide Bosc by 5 and generate a five cycle single phase PWM signal The duty of this signal is 2 3 To accomplish this the program must load the divide by ratio of 5 actual setting 4 into compare capture register A and a cycle count of 2 actual setting 1 into compare capture register B P3 CORE ROM RAM Interrupts Bus Controller P5 PG Time
136. pixels 16 pixels A Standard Mode 16W x 16H B Extended Mode 16W x 18H Figure 7 3 Graphic Tiles in Standard and Extended Modes Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 160 Panasonic 5 Display Display Setup Examples 7 7 Display Setup Examples 7 7 1 Setting Up the Graphics Layer This section shows how to set up the graphics display data in the VRAM Register settings RAMEND x 007F04 x 80FF Graphics RAM end address x 980F GIHP x 007F16 x 0822 GIHP x 22 GIHSZ GIVP x 007F18 x 1803 x 03 GIVSZ x 3 OSD2 x 007F08 x 0047 1 line maximum 18 tiles 16 color mode graphics take priority Table 7 5 Example Graphics VRAM Settings Line No RAM Addr RAM Data Data Type Description 1 980E 4000 GTC Graphic GCB x 0 GPRT 0 GTC x 000 980C 4255 GTC Graphic GCB x 0 GPRT 1 GTC x 055 980A 02 GTG Blank tile GCB x 0 GPRT 1 0 9808 4100 GTC Graphic tile GCB x 0 GPRT 0 GTC x 100 9806 C004 GHP GHSZ x 0 GSHT 0 GHP x 04 9804 C040 GVP GLAST 0 GVSZ x 0 GINT 0 GVP x 40 2 97E6 4010 GTC Graphic GCB x 0 GPRT 0 GTC x 010 97E4 4011 GTC Graphic GCB x 0 GPRT 0 GTC x 011 97E2 4012 GTC Graphic GCB x 0 GPR
137. program branches to the user program at address x 0x82010 B 4 7 2 Branching to the Interrupt Start Routine Interrupt start JMP x 82018 instruction address x Ox80008 3 bytes 2 cycles Branch to address Write a branch instruction x 0x82018 to address x 82018 t Execute user interrupt service routine Generate 2 cycle delay Figure B 11 Flow of Branch to Interrupt Start Routine In the interrupt start address place a simple branch instruction pointing to address x 0x82018 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 327 Panasonic MN102HF75K Flash EEPROM Version Reprogramming Flow B 5 Reprogramming Flow Figure B 12 shows the flow for reprogramming erasing and programming the flash memory Write Os to entire memory Erase routine Reverse Write user program 1 Figure 12 Programming Flow LI As the figure shows the write occurs after the memory is completely erased The Always program after erasing is erase routine consists of three steps first writing all zeros to the entire memory completed Erasing is sometimes not done finely even though PROM 2 D space next erasing the memory and finally reversing writer or onboard serial writer shows PASS in blank check And in that situation the data programed B 6 Pro gramm in g Times successfully may Table B 7 shows the time
138. read starts 12 system clock cycles 12 after the leading edge of the HSYNC pulse The transfer takes 4Ts for each display data word In line 1 or when graphics and text line begin simultaneously the data transfer requests for both layers occur simultaneously The text data transfer always takes priority The graphics data transfer begins 5Ts after the text data transfer ends Ifa DMA transfer occurs at the same time as the leading edge of a VSYNC pulse the screen flickers To avoid this do not set a display position in the last line Interrupts For both graphics and text displays the microcontroller processes the GINT and CINT interrupt request bits of the display data s GVP and CVP fields during DMA transfer If GINT or CINT is set to 1 when the associated transfer ends GVP or CVP transfer the OSD generates an interrupt request Note that if the interrupt bit is set to 1 in the line 1 display data the interrupt occurs at the first scan line If the interrupt bit is set to 1 in the line 2 display data the interrupt occurs at the first display line 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 191 Panasonic 5 Display DMA Interrupt Timing Graphic Graphic display display 1278 4176 578 4nTs Television Screen Y Scan line 1 Text DMA Graphics Piya aa asua u Sui Bop ce sci S
139. read write setting bit 0 1 read 13 6 1 2Setting Up the First Interrupt When an 0 signal returns from the slave device the bus controller generates an interrupt At this point implement the following settings To set up the interrupt Set the I2COICH and I2COICL register pair x OOFC9C to x 0100 This enables interrupts and clears the previous interrupt request To set up the C registers 1 Read the I2ZCDREC register x 007E42 to determine the PC bus controller Status 2 Sincethe microcontroller will become a receiver on the next operation set the I2CDTRM register x 007E40 to x 0000 This sets STA STP and the transmission data to Os With this setting the microcontroller returns an 0 signal on the ninth clock Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 300 Panasonic I C Bus Controller Interface Setup Examples slave address 13 6 1 3Setting Up the Second Interrupt When the microcontroller receives the data 85 from the slave device it returns an ACK 0 signal and the bus controller generates an interrupt At this point implement the following settings To set up the interrupt Set the I2COICH and I2COICL register pair x OOFC9C to x 0100 This enables interrupts and clears the previous interrupt request To set up the registers 1 Read the IZ2CDREC re
140. reference clocks for the serial interfaces or start timers for A D conversions The clock source can be the internal clock oscil lator frequency divided by 2 or the external clock 1 4 or less the oscil lator frequency input A timer interrupt is generated by a timer underflow The MN102H75K 85K contains four 8 bit timers that can serve as interval timers event timer counters clock generators divide by 2 out put of the underflow reference clocks for the serial interfaces or start timers for A D conversions The clock source can be the internal clock oscillator frequency divided by 2 or the external clock 1 4 or less the oscillator frequency input A timer interrupt is generated by a timer underflow The MN102H75K contains two 16 bit up down timers timers 5 and 6 Associated with each timer are two compare capture registers that can capture and compare the up down counter values generate PWM sig nals and generate interrupts The PWM function has a double buffering mode that causes cycle and transition changes to occur at the beginning of the next clock cycle This prevents PWM signal losses and mini mizes waveform distortion during timing changes The MN102H75K 85K contains two 16 bit up down timers timers 5 and 6 Associated with each timer are two compare capture registers that can capture and compare the up down counter values generate PWM signals and generate interrupts The PWM function has a double buffering mode tha
141. registers with eight internal CPU registers divided functionally into four address registers AO and four data registers DO D3 The program can address a register pair in four or less bits and basic instructions such as register to register operations and load store operations occupy only one byte Conventional code assignment for general register instructions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W s Register specification Rn Register specification An Dn New Panasonic code assignments Figure 1 1 Conventional vs MN102H Series Code Assignments B High speed pipeline throughput The MN102H series executes instructions in a high speed three stage pipeline fetch decode execute With this architecture the MN102H series can execute single byte instructions in only one machine cycle 50 ns at 40 MHz 1 machine cycle gt Time Instruction 1 gt Instruction 2 gt gt Figure 1 2 Three Stage Pipeline Simple instruction set The MN102H series uses a streamlined set of 41 instructions designed spe cifically for the programming model for embedded applications To shrink code size instructions have a variable length of one to seven bytes and the most frequently used basic instructions are single byte MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 19 Panasonic General Description MNIO2H Series Features Fast interr
142. select 0 to 127H VSYNC separation mask 1 No mask VSEPLMT 2 0 VSYNC separation detection threshold HVCOND Sync Separator Status Register x 007EDA HVCONDW x 007EFA Bit 7 6 5 4 3 2 1 0 STPN HSEP HLOCK Reset 0 0 0 1 1 0 0 0 R W R R R R R R R R Use this register to monitor the status of the sync separator STPN Status of clamping control pulse signal during STOP COMPSY Composite sync signal status VSEP VSYNC signal status HSEP HSYNC signal status Sync detection 0 Asynchronous 1 Synchronous MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 247 Panasonic Closed Caption Decoder Closed Caption Decoder Registers CLPCND1 Clamping Control Signal Status Register 1 x 007EDC CLPCNDW x 007EFC Bit 15 14 13 12 11 10 9 8 7 6 5 4 9 2 1 0 SAFEP d CLPP CLPN pin MCA ie eee Reset 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 R W R R R R R R R R R R R R R R R R SAFEP Low clamping control pulse for high current source P channel SAFEN Low clamping control pulse for high current source N channel This register is for monitoring the status of the clamping current source switch shown in figure 9 5 on page 229 An N channel transistor is on when the associated bit PEDOWN XPEDOWN CLPN or SAFEN is 1 A P channel transistor is on when the
143. serial data received from the C bus is shifted into this field MSB first I2CMYAD I C Self Address Register x 007E44 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 4 2 1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R RW RW RW RW RW RW A 6 0 Microcontroller address This register is formed from a 7 bit field address latch It holds the micro controller s own address used for a compare when the microcontroller is addressed as a slave When a match occurs AAS is set to 1 MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 305 Panasonic Bus Controller Bus Interface Registers 2 2 Clock Control Register x 007E46 Bit 15 14 13 12 11 10 9 8 7 6 2 4 3 2 1 0 C9 C8 C7 C6 C5 C4 C3 C2 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R RW RW RW RW RW RW RW RW RW RW C 9 0 Output clock frequency select 1 This 10 bit field determines the SCL output With 12 MHz system clock E calculate the frequency as follows To conform to the specification the clock signal must be 12 MHz between 0 and 100 kHz sat SCL 2x Register setting 10 isfy this requirement always set I2CCLK to x 032 or higher In this case the following settings apply
144. set this field to b 00 and set the P2DIR4 bit to 0 P2MD6 P2MD4 P2MD2 P2MDO 00 P24 01 10 SBT1 11 Reserved P23 output switch 0 P23 1 PWM6 P22 output switch 0 P22 1 5 P21 output switch 0 P21 1 PWMA P20 output switch 0 P20 1 PWM3 MNI02H75K F75K 85K F85K LSI User Manual 281 Panasonic Panasonic Semiconductor Development Company R W Ports I O Port Control Registers P3MD Port 3 Output Mode Register x 00FFF6 7 6 5 4 3 2 1 0 P3MD7 P3MD6 P3MD5 P3MD4 P3MD3 P3MD2 P3MDI P35MDO 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W P3MD is an 8 bit access register P3MD7 P37 output switch If you set this field to 1 select DABOUT or B in the RGBC bit of ODSI 0 P37 1 DABOUT or B P3MD6 P36 output switch If you set this field to 1 select DAGOUT or G in the RGBC bit of ODSI 0 P36 1 DAGOUT or G P3MD5 P35 output switch If you set this field to 1 select DAROUT or R in the RGBC bit of ODSI 0 P35 1 DAROUT or R P3MD4 P34 function switch 0 P34 1 VREF P3MDJ 8 1 P33 P30 function switch Set P3MD3 to 1 only when P3MD 2 1 is 01 otherwise set it to 0 000 P30 P31 P32 P33 101 CLH CVBS0 P32 CLL 010 CLH P31 CVBS1 CLL 011 CLH CVBSO CVBSI CLL P3MDO This bit exists but contains no function Panasonic Semiconductor Development Company 282 Panasonic 102 75 75
145. the MCU from SLOW to NOR MAL mode 3 1 2 Exiting from SLOW Mode to NORMAL Mode The MN102H75K 85K contains a PLL circuit that in NORMAL mode mul tiplies the clock input through the 5 and OSC2 pins by 12 divides the signal by 2 then sends the resulting clock to the CPU See figure 3 2 The MCU starts in SLOW mode on power up and on recovery from a reset In SLOW mode system clock 2 2 the clock from the OSC pins feeds directly to the CPU without going through the PLL circuit This means that the program must switch the CPU from SLOW to NORMAL mode system clock 12 MHz Clock select 12x PLL Divide by 2 24 MHZ CPUM register il i circuit 48 MHz circuit NORMAL mode M To all function blocks 4 MHz i U cu L i SLOW mode X System clock Noha x Oscillator EMN Eo Sk Figure 3 2 CPU Clock Switch NORMAL SLOW Modes Below is an example routine for exiting SLOW mode You should run this routine immediately after power up Example 3 1 Exiting SLOW Mode OV x FCO0 A1 OV A1 DO Read CPUM register AND x FFFD DO Invoke IDLE mode OV D0 A1 OV Al D0 Read CPUM register AND x FFFO DO Invoke NORMAL mode OV D0 A1 Because the system clock in SLOW mode is 2 MHz the OSD does not function Y The specifications also differ for the PWM function and functions such as the
146. the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 3 Set TM4NLD and TM4EN to 1 This starts the timer Counting begins at the start of the next cycle To enable timer 4 capture B interrupts Cancel all existing interrupt requests Next set the interrupt priority level in the TMACBLV 2 0 bits of the TMACBICH register levels 0 to 6 set the TMABIE bit to 1 and set the TMABIR bit of TMACBICL to 0 From this point on an interrupt request is generated whenever a timer 4 capture B event occurs 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 109 Panasonic Timers 16 Bit Timer Setup Examples To service the interrupts and calculate the signal width 1 Run the interrupt service routine The routine must determine the interrupt group then clear the interrupt request flag Ignore the flags when calculat 2 Calculate the number of cycles the TMAIA signal stays high Save the con ing the Signal width even when tents of TMACA and TMACB to the data registers then subtract the contents s of TM4CA from the contents of TM4CB Since TM4LP is set to 0 the dif ference will be the correct value even if TMACA is greater than TMACB Timer 4 can input a two phase capture signal You must select up counting Timer 4 does not operate in STOP mode whe
147. the system clock supplied to them 3 1 Modes 3 1 1 Description The MN102H75K 85K has two CPU operating modes NORMAL and SLOW and two CPU standby modes HALT and STOP Effective use of these modes can sig nificantly reduce power consumption Figure 3 1 shows the CPU states in the dif ferent modes The MN102H75K 85K recovers from power up and reset in SLOW mode For normal operation the program must switch the MCU from SLOW to NORMAL mode The MN102H75K 85K recovers from power up and reset in SLOW mode For normal operation the program must switch the MCU from SLOW to NORMAL mode The 102 75 contains a PLL circuit that in NORMAL mode multiplies the clock input through the OSC1 and OSC2 pins by 12 divides the signal by 2 then sends the resulting clock to the CPU See figure 3 2 The MCU starts in SLOW mode on power up and on recovery from a reset In SLOW mode system clock 2 MHz the clock from the OSC pins feeds directly to the CPU without going through the PLL circuit This means that the program must switch the CPU from SLOW to NORMAL mode system clock 12 MHz The MN102H75K 85K contains a PLL circuit that in NORMAL mode multiplies the clock input through the OSCI and OSC2 pins by 12 divides the signal by 2 then sends the resulting clock to the CPU See figure 3 2 The MCU starts in SLOW mode on power up and on recovery from a reset In SLOW mode system clock 2 MHz the clock from the OSC pins
148. to 0 set the TM IUDIE bit of TMIUDICH to 0 and set the TM1UDIR bit of TMIUDICL to 0 Note that you set the priority level for both timer 1 and 2 interrupts in the timer 2 interrupt control register From this point on an interrupt request is generated whenever timer 2 underflows Timer 1 underflows are unused Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 84 Panasonic Timers 8 Bit Timer Setup Examples TM2UDICH example x 00FC71 Bit 7 6 5 4 3 2 1 0 TM2UD TM2UD TM2UD _ __ TM2UD Lv2 LVO IE Setting 0 1 0 0 0 0 0 1 TM2UDICL example x 00FC70 Bit 7 6 5 4 3 2 1 0 _ ES __ TM2uD IR ID Setting 0 0 0 0 0 0 0 0 TM1UDICH example x 00FC73 Bit 7 6 5 4 3 2 1 0 TMOUD IE Setting 0 0 0 0 0 0 0 0 TM1UDICL example x 00FC72 Bit 7 6 5 4 3 2 1 0 TMIUD ao _ TMIUD ID Setting 0 0 0 0 0 0 0 0 3 Setthe divide by ratio for timer 0 Since the timer will count 60 000 cycles X 607 write 5 to the timer 1 base register TMIBR and to the timer 2 base register TM2BR The valid range for TMnBR is 0 to 255 TM1BR example x O0FE11 Bit 7 6 5 3 2 1 0 TMI TMI TMI TMI TMI TMI TMI TMI BR7 BR6 BR5 BR4 BR3 BR2 BRI BRO Se
149. to 3 and TM5OA outputs a high signal while the count is 1 2 and 3 The timer operates essentially the same as it does during two phase PWM output TM5CA example x 00FE94 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 15 14 CAI3 12 10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO Stings 0 0 0 0 0 0 0 0 o 0 o o 9 0 i 1 3 Write x 0001 to 5 TM5CB example x 00FE98 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 15 4 12 CB11 CB10 CB9 CB8 CB7 6 CBS 4 2 CBO Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 Set the TM5NLD bit of the TM5MD register to 1 and the TMSEN bit to 0 This enables 5 and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 5 On the falling edge of the TMSIB signal the hardware sets the TMSEN bit to 1 This means that counting begins at the start of the next cycle after the TMSIB
150. to TMOS 1 0 TMOMD example x 00FE20 Bit 7 6 4 3 2 1 0 TMO TMO TMO TMO EN LD SI 50 Setting 0 1 0 0 0 0 0 0 4 Set TMOLD to 0 and TMOEN to 1 This starts the timer Counting begins at the start of the next cycle When the binary counter reaches 0 and loads the value x 01 from the base register in preparation for the next count a timer 0 underflow interrupt request is sent to the CPU To set up timer 4 1 Set the operating mode in the timer 4 mode register TM4MD Disable timer 4 counting and interrupts Select up counting Set the TMANLP bit to 0 to select looped counting from 0 to x FFFF Select timer 0 underflow as the clock source setup and only use 16 bit write TM4MD example x 00FE80 operations Bit 1514 B R nN 10 9 8 7 6 5 4 3 2 1 0 TM4 TM4 TM4 TM4 TM4 This step stops the TM4BC EN NLD UDI UDO TGE ONE MDI ECLR LP ASEL 52 s SO count and clears both ENT m 5 7 7 i T 9 5 and the S R flip flop to 0 When TM4MD 1 0 b 11 dur ing capture TMACA and become read only regis ters To write to or TM4CB you must first set TM4MDf 1 0 b 00 2 Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0 This enables TM4BC and
151. to enable transmission To enable serial 0 transmission end interrupts Cancel all existing interrupt requests Next set the interrupt priority level of 5 in the ANLV 2 0 bits of the ANICH register set the SCTOIE bit of SCTOICH to 1 and set the SCTOIR bit of SCTOICL to 0 From this point on an interrupt request is generated whenever a serial data transmission ends ANICH example x 00FC81 Bit 7 6 5 4 3 2 1 0 ANLV2 ANLVO ANIE Setting 0 1 0 0 0 0 0 SCTOICL example x 00FC82 Bit 7 6 5 4 3 2 1 0 _ soo _ u SCTO IR ID Setting 0 0 0 0 0 0 0 0 SCTOICH example x 00FC83 Bit 7 6 5 4 3 2 1 0 SCTO IE Setting 0 0 0 0 0 0 0 1 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 132 Panasonic Serial Interfaces Serial Interface Setup Examples Transmission sequence 1 Write the first data byte to SCOTRB Once this data is in the register trans mission begins synchronized to timer 0 2 When an interrupt occurs the program branches to the interrupt service rou tine The routine must determine the interrupt group then clear the interrupt request flag 3 Write the next data byte to SCOTRB Once the write is complete transmis sion begins in 1 or 2 cycles of the transfer clock timer 0 underflow Figure 5 10 shows an example ti
152. up the transmission data Tosetup the interrupt Set the I2COICH and I2COICL register pair x OOFC9C to x 0100 This enables interrupts and clears the previous interrupt request To set up the C registers 1 Read the IZ2CDREC register x 007E42 to determine the PC bus controller status AAS should be 1 2 Set the I2CDTRM register x 007E40 to x 0155 This sets STA to 0 STP to 0 ACK to 1 and the transmission data to x 55 The microcontroller does not need to issue an ACK signal in this transfer so the ACK bit should be 1 3 Begin transmitting data in sync with the clock from the master Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 302 Panasonic I C Bus Controller Interface Setup Examples 13 6 2 3Setting Up the Second Interrupt The master sends an ACK 0 signal so the microcontroller must send the next data byte Set up the transmission data as follows set up the interrupt Set the I2COICH and I2COICL register pair x OOFC9C to x 0100 This enables interrupts and clears the previous interrupt request To setup the C registers 1 Read the I2ZCDREC register x 007E42 to determine the bus controller status The previous read from I2CDREC cleared the AAS so AAS should be 0 2 Set the I2CDTRM register x 007E40 to x 01 AAO This sets STA to 0 STP to 0 ACK to 1 and the transmission da
153. virtual registers used only in double buffer mode during PWM output They do not exist in the hardware and are not readable or writable Depending on the write signal they load the value in the associated CA or CB register TMABC TMBBC Timer n Binary Counter x 00FE82 x 00FE92 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn BCI5 BC14 2 11 BCIO BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BCO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TM4CA TM5CA Timer n Compare Capture Register x 00FE84 x 00FE94 Y Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn 15 CA14 13 CA12 11 CA10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO TMnCA and TMnCB 16 bit Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 access registers Use the MOV RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW instruction to write to them TM4CB TM5CB Timer n Compare Capture Register B x 00FE88 x 00FE98 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn 15 14 CB13
154. x 0001 to x FFFE in TM4CA register and the phase difference in the TMACB register When the contents of TM4BC match those of the register T flip flop B reverses at the beginning of the next cycle When the contents of TM4BC match those of the register T flip flop A reverses and resets at the beginning of the next cycle The circuitry is configured so that there are no waveform errors even when the output is always high or always low Counting begins after the TM4EN bit is set in the TMAMD register Figure 4 30 below shows the output waveforms for TM4OA and TMAOB Both A and B interrupts occur when the contents of the binary counter matches those of the associated compare capture register However B interrupts can only occur if the TMACB setting is from 0 to less than This is because when TMACB TMACA TM4BC never matches TM4CB Write to TMAMD TM4EN TM4BC 0 Oo 1 2 3 4101121314 OF 17 2 3 4 0 11213 CLRBC4 i I I i i 1 E E i i i 1 1 2 4 4 TM4OB B Figure 4 33 Two Phase PWM Output Timing Timer 4 Panasonic Semiconductor Development Company MN102H75
155. x 100 6x Palette 1 Palette 2 Palette 1 VP x 40 Line 2 HSZ 0 1 Y Hex ofi 012 O19 1 013 013 014 Bank Biank Blank 016 vsz o Palette 1 Palette 1 Palette 1 Palette 1 Palette 1 Palette 1 Palette 1 Palette 2 Palette 2 1x usaspa a ulead Repeated tile VP x58 anes Y HSZ 3 4x peser aem a GTC x 181 GTC x 182 Palette 1 Palette 2 VSZ 1 2 Display Figure 7 4 Graphics Display Example Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 162 Panasonic 5 Display Display Setup Examples 7 7 2 Setting Up the Text Layer This section shows how to set up the text display data in the VRAM Register settings RAMEND x 007F04 x 80FF Text RAM end address 9 CIHP x 007F1A x 1020 CIHP x 20 CIHSZ x 2 CIVP x 007F1C x 1803 CIVP x 03 CIVSZ x 3 OSD3 x 007F0A x 0000 CAPM x 0 Table 7 6 Example Text VRAM Settings Line No RAM Addr RAM Data Data Type Description 1 9FFE 0000 CC Character code x 000 9FFG 825A COL BSHAD 0 CSHAD 0 FRAME 1 BCOL x 5 CCOL x A 9FFA 0001 CC Character code x 001 9FF8 0002 CC Character code x 002 9FF6 C004 CHP CHSZ x 0 CSHT 0 CHP x 04 9FF4 C840 CVP CLAST 0 CVSZ x1 CINT 0 CVP x 40 2 9F
156. 0 it 21 Lie 200 ns VSYNGcourted on thefalling edge Note In this example HIO is active high and VSYNC is active low Figure 14 3 H Counter Input Signal Timing The 10 bit counter counts the HSYNC signal from 0 to x 3FF and the 10 bit register stores the count The H counter uses the four pins shown in table 14 1 Table 14 1 H Counter Pins Pin No Pin Name H75K Description Alternative Functions HI0 17 45 Count source pin P43 TM5IOB HI1 16 46 Count source pin P44 TM5IG VIO 6 53 Count reset pin P52 IRQ4 VSYNC 2 55 Count reset pin P54 IRQ5 To use the H counter set the port 4 and 5 output control registers PAOUT and P5OUT to 0 and set the H counter pins to input To use HIO set the PADIR3 bit x OOFFE4 to 0 To use HII set the P4DIR4 bit x 00FFE4 to 0 To use VIO set the PSDIR2 bit x OOFFES5 to 0 a To use VSYNC set the PSDIRA bit x O0FFES to 0 Panasonic Semiconductor Development Company 308 Panasonic MN102H75K F75K 85K F85K LSI User Manual H Counter Operation To use the H counter you must always set the HCNTOFF bit of the PCNTO0 register to 0 To use the PWM function always set the PWMOFF bit of the PONT2 register 00 92 to 0 The H counter counts the HSYNC signal for the interval set in the HCCNTO x 007EBO or x 007EB2 register l
157. 0 Nu 19509 10 99 p NONE NOWOS NNOOH 10 01 Jejunoo Jeou A youms Ajuejod 4 uiejs s MIOSAS fido WH ZHN 8b Tid ETT 21980 O IXaso ONASH ONASA MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 154 Panasonic 5 Display Power Saving Considerations the OSD Block 1 OSDPOFF resets 0 operate the OSD you must first set this bit to 1 To turn off the OSD block to save power 1 Write a 0 to OSD OSD1 bit 10 2 Wait for the next VSYNC input 3 Write a 0 to OSDPOFF bit 7 turning the clock off If you turn the clock off before the VSYNC input power usage may not drop or the microcontroller may halt 7 4 Power Saving Considerations in the OSD Block Table 7 2 shows bits that can decrease the power consumption of the OSD block This section explains how to use these bits Table 7 2 Power Saving Control Bits for the OSD Bit Name Register Address Bit Description Reset OSDPOFF PCNTO xOOFF90 7 0 System clock off to OSD 0 1 System clock on to OSD OSDREG 2 xOOFF92 0 0 R W disabled for OSD registers 0 E 1 R W enabled for OSD registers Using OSDPOFF to conirol the syst
158. 0 1 L PWM2 7 PWM3 0 PWM4 P2PUP 1 PWM5 00 2 2 PWM6 3 The microcontroller writes the pulsewidth modulated data for a PWM block to its associated 8 bit data register PWMn The data register settings determine how long the waveform stays low With a 4 MHz oscillator the PWM output pulse width has a resolution of 1 33 us and a cycle of 341 3 us 28 fpwm Note that when and only when the data changes between x 00 and x 01 the resolution is 1 34 us 2 PWM Data Output Wave 00 High level 01 341 3 us 2 ms for SLOW mode m 1 33 us 8 us for SLOW mode FE FF Low level Figure 10 1 PWM Output Waveform MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 249 Panasonic Pulse Width Modulator Block Diagram 10 2 Block Diagram Data bus 8 Y PWMO PWMe MSB 007 70 007 7 71615 4 3 2 PnPUP PLT TTT id PWMn fewa PWM 8 bit output 15 17 contro MUX P20 P23 PnDIR Port 1 Note With a 4 MHz oscillator fpwM 16 Output pulse cycle 28 fpwm 341 3 us Not using internal pullup func Minimum pulse width 1 fpww 1 33 us tion Figuer10 2 connect the tLow PWMn 1 x 0 67 us external pullup registance N Figu
159. 0 MING Output select for noise filter detecting minimum sync tip 0 Low pass filter 1 1 Low pass filter 2 3 or 4 setin NFSW 1 0 NFSW 1 0 Noise filter switch for composite sync separator 00 Low pass filter 3 01 Low pass filter 4 10 Low pass filter 2 11 Low pass filter 1 The cutoff frequencies for low pass filters 1 to 4 are lower in ascending order so that low pass filter 4 eliminates the highest amount of noise Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 242 Panasonic Closed Caption Decoder Closed Caption Decoder Registers FQSEL Frequency Select Register x 007EC2 FQSELW x 007EE2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 9 2 1 0 VFQ VFQ VFQ VFQ FQ FQ FQ FQ E m DIV5 DIVA DIV3 DIV2 DIVI DIVO E ud DIV3 DIV2 DIVI DIVO Reset 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 R W R R RW RW RW RW RW R R R R RW RW RW In this register set the sampling cycle for separating the HSYNC and VSYNC signals from the composite sync signal The recommended setting is x 1F01 VFQDIV 5 0 Sampling frequency setting for VSYNC separator In this field set the ratio by which to divide the sampling frequency for the HSYNC separator FQDIV 3 0 Sampling frequency setting for HSYNC separator In this field set the ratio by which to divide the A D sampling frequency
160. 0 RW R R R R R R RW RW RW RW RW RW RW RW Panasonic Semiconductor Development Company 212 Panasonic MN102H75K F75K 85K F85K LSI User Manual 5 Display OSD Registers CPTO CPTF Text Palette Colors 0 15 Registers 007 80 007 9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPTn CPTn CPTn CPTn CPTn CPTn CPTn CPTn CPTn CPTn CPTn CPTn CPTn CPTn CPTn CPTn 2 YMI YMO B3 B2 0 G3 G2 Gl GO R3 R2 RI RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W w w w w w w w w w w w w w w These registers contain the colors used in the text layer When digital out put is selected CPTnYMO is output as YM CPTnB0 as CPTnG0 as G and CPTnR0 as R When the YS color palette is selected CPTnYM3 is output as YS CPTnYMI 3 0 YM color code CPTnB 3 0 Blue color code CPTnG 3 0 Green color code CPTnR 3 0 Red color code COLB Color Background Register x 007FA0 14 13 12 11 10 9 8 7 6 4 3 2 1 0 15 COLB COLB COLB COLB COLB COLB COLB COLB COLB COLB COLB COLB COLB COLB COLB COLB 2 YM0 B2 Bl BO G3 G2 GI GO R3 R2 RI RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W w w w w w w w w w w w w w w This register contains the color used for the color background When digi
161. 0 0 0 R W R R R R R R R R W TM1UDICH enables timer 1 underflow interrupts It is an 8 bit access reg ister Use the MOVB instruction to access it The priority level for timer 1 underflow interrupts is written to the TM2UDLYV 2 0 field of the TM2UDICH register TM1UDIE Timer 1 underflow interrupt enable flag 0 Disable 1 Enable TMOUDICL Timer 0 Underflow Interrupt Control Register Low x 00FC74 Bit 7 6 5 4 3 2 1 0 _ _ TMUD _ u TMouD IR ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R TMOUDICL register detects and requests timer 0 underflow interrupts It is an 8 bit access register Use the MOVB instruction to access it TMOUDIR Timer 0 underflow interrupt request flag 0 No interrupt requested 1 Interrupt requested TMOUDID Timer 0 underflow interrupt detect flag 0 Interrupt undetected 1 Interrupt detected TMOUDICH Timer 0 Underflow Interrupt Control Register High x 00FC75 Bit 7 6 5 4 3 2 1 0 TM0UD IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W TM0UDICH enables timer 0 underflow interrupts It is an 8 bit access reg ister Use the MOVB instruction to access it The priority level for timer 0 underflow is written to the TM2UDLV 2 0 field of the TM2UDICH register TMOUDIE Timer 0 underflow interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75
162. 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R RW RW RW RW RW RW RW RW RW P7P8CNT Ports 7 and 8 forced pullup 1 Ports 7 and 8 are only available in the quad flat package 0 Pullup Always set bits 7 to 3 of PCNT2 1 Don t pull up 09 I2COFF IC function enable 0 Enable Disable a PWMOFF PWM function enable 0 Enable You cannot read from or write to the registers associated with a funetion that is qisabled Setting the I2COFF or PWMOFF bits to 1 shuts off the system clock sup ply to the associated block which reduces power dissipation 1 Disable OSDREGE OSD registers read write enable To read or write to the OSD registers you must first set this bit to 1 0 Disable 1 Enable MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 287 Panasonic ROM Correction Description 12 ROM Correction 12 1 Description The ROM correction function can correct the program data in any address within the 256 kilobyte ROM It cannot correct OSD ROM data maximum of sixteen addresses can be corrected Addresses are set as address match interrupts This function shortens time to market for large scale designs since changes can be implemented in the software after the mask ROM is complete The ROM correction function has numerous other applications For instance you can insert keywords into the functional routines then use the function to send internal status information to an
163. 00 to the value in 5 to 5 Whenever the binary counter reaches the value in TMSCB in either up or down counting a compare capture B interrupt occurs at the beginning of the next cycle example x 00FE98 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 15 14 CB13 12 CB11 CB10 9 CB8 CB7 CB6 5 CB4 2 CBO Setting 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 4 Set the TM5NLD bit of the TM5MD register to 1 and the TMSEN bit to 0 This enables 5 and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 5 Set TM5NLD and TMSEN to 1 This starts the timer Counting begins at the start of the next cycle To enable timer 5 capture B interrupts Cancel all existing interrupt requests Next set the interrupt priority level in the TMSCBLV 2 0 bits of the TM5CBICH register levels 0 to 6 set TMSBIE bit to 1 and set the TMSBIR bit of TMSCBICL to 0 From this point on an interrupt request is generated whenever a timer 5 capture B event occurs 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 121 Panasonic Timers 16 Bi
164. 0000 0001 0002 0003 0000 soso fy yi pl yl el el pl piel el el DON x U Pe C 55 k k R5 TM50A Figure 4 48 One Shot Pulse Output Timing Timer 5 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 119 Panasonic Timers 16 Bit Timer Setup Examples 4 11 9 Setting Up an External Count Direction Controller Using Timer 5 In this example timer 5 counts 4 and the TMSIA pin controls the count direction up or down An interrupt occurs when the counter reaches a preset value P2 CORE ROM RAM P3 P6 Interrupts Bus Controller P5 Timers 0 3 Serial 5 4 gt Timers 4 5 ADC A Chip Level Timer 5 Bosc 4 gt TM5BC TM5CA E R c s Q Interrupt B rr TM5CB Block Level Figure 4 49 Block Diagram of External Count Direction Control Using Timer 5 TM5BC contents 0 x1000 x 1FFF Interrupt Figure 4 50 Configuration Example of External Count Direction Control Using Timer 5 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 120 Panasonic Timers 16 Bit Timer Setup Examples Use the MOV instruction for this s
165. 007E1C STAPW x 007E3C Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SFT SFT SFT SFT SFT SFT SFT SFT SFT SFT SFT STAP STAP STAP STAP STAP STAP STAP STAP STAP STAP STAP 10 9 8 Z 6 4 2 1 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R W R R R R R RW RW RW RW RW RW RW RW RW RW RW SFTSTAP 10 0 Software setting for sampling start position in clock units FCPNUM Sampling Start Position Register Hardware Calculation x 007E1E FCPNUMW x 007E3E Bit 15 14 13 12 11 10 9 8 7 6 a 4 3 2 1 0 FOP FCP FCP FCP FCP FCP NUM NUM NUM NUM NUM NUM NUM NUM NUM NUM NUM 10 9 8 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R FCPNUM 10 0 Sampling start position calculated by the hardware NFSEL Noise Filter Select Register x 007ECO NFSELW x 007EE0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MING rw TON Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R W R R R R R R R W R W This register selects the low pass filter which eliminates noise and high frequency signals that are unnecessary to the sync separator and the clamp ing controller The recommended setting for NFSEL is x 000
166. 07E2E Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPRT3 STC38 STC37 STC36 STC35 STC34 STC33 STC32 STC30 STC30 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R RW RW RW RW RW RW RW RW RW SPRT3 Cursor 3 color palette select 0 Graphics color palette 1 1 Graphics color palette 2 STC3 8 0 Cursor 3 Tile Code Use the same ROM data as that used for the graphics SHP Cursor Horizontal Position Register x 007F12 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 1 1 0 SHSZI SHSZO SHP9 SHP8 SHP7 SHP6 SHP5 SHP4 SHP3 SHP2 SHPI SHPO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R RW RW R RW RW RW RW RW RW RW RW RW RW SHSZ 1 0 Cursor horizontal size 00 1 dot 1 VCLK period 01 1 dot 2 VCLK periods 10 1 dot 3 periods 11 1 dot 4 periods SHP 9 0 Cursor horizontal position SVP Cursor Vertical Position Register x 007F14 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SVSZI SVSZO SVP9 SVP8 SVP7 SVP6 SVP5 SVP4 SVP3 SVP2 SVPI SVPO Rest 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R RW RW R RW RW RW RW RW RW RW RW RW SVSZ 1 0 Cursor vertical size Table 7 16 Cursor Vertical Size Settings SVSZ 1 0 1 Dot Size Settin
167. 07E30 FCPNUMW STAPW DATAEW DATASW CRI2EW CRI2SW CRITEW CRHSW 007E40 I2CBSTS I2CBRST 2 I2CMYAD 12 I2CDTRM C interface registers 007E50 007E60 007E70 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWMO PWM registers 007E80 007E90 007 0 RML BMI BMS RMG RMT RMIR RMIS Remote signal receiver registers D R R S C 007EBO HCD1 HCDO UNE ONG H counter registers 007ECO HSEP1 CLAMP SYN BPPST SCMING FQSEL NFSEL CLPCND Sync separator 1 registers 007EDO 1 HVCOND VCNT HDISTW HLOCKLV FIELD HSEP2 BPLV SYNC SCMING 007 0 HSEP1W CLAMPW SPLVW yw www BPPSTW W FQSELW NFSELW HDIS Sync separator 2 registers 007EFO CLPCND1W HVCONDW VCNTW HLOCK FIELDW HSEP2W TWW NW GROMEN CROMEN D D 007F10 CIVP CIHP GIVP GIHP SVP SHP STCO OSD control registers 007 00 EVOD OSD3 OSD2 OSD1 RAMEND 007F20 STC3 STC2 STC1 SHTG HSHT1 HSHT0 VSHT1 VSHT0 007F30 TESTA SBFNUM 007F40 test register test register VBI 1 test registers 007F50 TESTAW SBFNUMW 007F60 test register test register VBI 2 test registers 007F70 007F80 CPT7 CPT6 CPT5 4 2 1 OSD text color palette 007F90 CPTF CPTE CPTD CPTG CPTB CPTA CPT9 CPT8 007FA0 WBSHD BBSHD FRAME COLB OSD text effects registers 007FB0 007FCO GPT17 GPT16 GPT15 GPT14 G
168. 08 Panasonic 5 Display OSD Registers OSD2 OSD Register 2 x 007F08 Bit 15 13 10 9 8 7 6 5 4 3 2 1 0 GTHT GEXTE PRYM 27 COLB EE o CGPR SOUT GOUT COUT Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SPEXT Cursor extended mode select 0 Standard mode 16 x 16 pixels 1 Extended mode 32 x 32 pixels GTHT Graphic tile height select 0 16 pixels high 1 18 pixels high GEXTE Graphics maximum tiles per line select 0 Maximum 18 tiles 1 Maximum 28 tiles PRYM Translucent color control YM YS 1 0 Normal YS output 1 Don t output YS during YM output when the YM color code is not 0 Setting the YSPLT bit of OSD1 TRPTF Translucency control all layers to 1 disables the PRYM bit With Specifies translucency for color 15 in all palettes this setting you must also set the TRPT and TRPTF bits to 1 You can specify transparency for individual color palettes if TRPT Transparency control all layers needed Specifies transparency for color 0 in all palettes 0 Make color 15 on all palettes translucent 1 Output color 15 as specified 0 Make color 0 on all palettes transparent 1 Output color 0 as specified GCOL 1 0 Graphics color mode 00 16 color mode 10 4 color mode 01 8 color mode 11 2 color mode COLB Color bac
169. 1 1 1 1 output 9 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 181 Panasonic 5 Display Setting Up the OSD Graphics layer Color palette 2 YM3 0 YM2 0 YM1 0 YM0 0 Color palette 0 YM3 0 YM2 0 YM1 0 YM0 1 Color palette 1 YM3 1 YM2 0 YM1 0 YM0 1 RGB YM and YS signals are displayed at this line Color palette F YM3 1 YM2 0 YM1 0 YM0 1 Signal specified in color palette 0 is output diio T f RgB 011 2 F Ho ofl 2 10 YS RGB RGB YM YM YS YS _ 9 RGB _ YM Li YS RGB YS s Figure 7 21 OSD Signal Waveform Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 182 Panasonic 5 Display Setting Up the OSD Color palette 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 Digital input Internal DAC B G Analog output RGBCNT X007FO06 bit 1 Output YSto entire OSD display area PCB except transparert CNT and semitransparent areas CNT O O o YCNT x007F06 bit 3 x007F06 bit 0 YS YM B G R Figure 7 22 OSD Signal Output Switches MN102H75K F75K 85K F85K LSI User Manual Panasonic Semico
170. 10 International Trade Tower Nehru Place New Delhi_110019 INDIA Tel 91 11 629 2870 91 11 629 2877 Indonesia Sales Office P T MET amp Gobel M amp G JL Dewi Sartika Cawang 2 Jakarta 13630 INDONESIA Tel 62 21 801 5666 Fax 62 21 801 5675 e Taiwan Sales Office Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6F 550 Sec 4 Chung Hsiao E RD Taipei 110 TAIWAN Tel 886 2 2757 1900 886 2 2757 1906 Kaohsiung Office 6th Floor Hsin Kong Bldg No 251 Chi Hsien 1st Road Kaohsiung 800 TAIWAN Tel 886 7 346 3815 886 7 236 8362 Sales Office Panasonic Industrial Shanghai Co Ltd PI SH Floor 6 Zhong Bao Mansion 166 East Road Lujian Zui PU Dong New District Shanghai 200120 CHINA Tel 86 21 5866 6114 86 21 5866 8000 Panasonic Industrial Tianjin Co Ltd PI TJ Room No 1001 Tianjin International Building 75 Nanjin Road Tianjin 300050 CHINA Tel 86 22 2313 9771 Fax 86 22 2313 9770 Panasonic SH Industrial Sales Shenzhen Ltd PSI SZ 74 107 International Bussiness amp Exhibition Centre Futian Free Trade Zone Shenzhen 518048 CHINA Tel 86 755 359 8500 86 755 359 8516 Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11th Floor Great Eagle Center 23 Harbour Road Wanchai HONG KONG Tel 852 2529 7322 Fax 852 2865 3697 Korea Sales Office Panasonic Industrial Korea Co Ltd PIKL Kukje Center Bldg 11th 1
171. 12 CB11 CB10 9 CB8 CB7 6 CBS 4 2 CBO Setting 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 4 Set the TM5NLD bit of the TM5MD register to 1 and the TMSEN bit to 0 This enables 5 and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not change any other operating modes during this step 5 Set TM5NLD and TMSEN to 1 This starts the timer Counting begins at the start of the next cycle To enable timer 5 capture B interrupts Cancel all existing interrupt requests Next set the interrupt priority level in the TMSCBLV 2 0 bits of the 5 register levels 0 to 6 set the TMSBIE bit to 1 and set the TMSBIR bit of TMSCBICL to 0 From this point on an interrupt request is generated whenever a timer 5 capture B event occurs Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 112 Panasonic Timers 16 Bit Timer Setup Examples B service the interrupts Run the interrupt service routine The routine must determine the interrupt group then clear the interrupt request flag Timer 5 can input a two phase encoder signal Timer 5 does not operate in STOP mode when Bosc is off If you use an external clock it must be synchronized to Bosc Table 4 4 shows the count direction for the timing diagram in f
172. 2 Write the intended looping value for timer 5 TM5CA valid settings x 0001 to For TM5BC to count from x 0000 to x 1FFF for instance write x IFFF to TM5CA TM5CA example x 00FE94 Bit 15 14 13 12 11 10 9 8 Z 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 15 14 CAI3 CAI2 10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO Setting 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 Write the timer 5 interrupt value valid settings 0000 to the value in 5 to TM5CB Whenever the binary counter reaches the value in TMSCB in either up or down counting a compare capture B interrupt occurs at the beginning of the next cycle example x 00FE98 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 15 CB14 CBI3 12 CB11 CB10 9 CB8 CB7 6 CBS 4 2 CBO Setting 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 4 Set the TM5NLD bit of the TM5MD register to 1 and the TMSEN bit to 0 This enables 5 and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the
173. 2 1 multiple of 3 03 04 2 ROMEND 180 0 ROMEND 160 NM NM ROMEND 140 Y Lea 09 02 22255 ROMEND 120 9 04 lt 2 225 ROMEND 100 M DRE ROMEND EO LS RN 03 EDS Sete ROMEND C0 060 01 ROMEND A0 o5 E ROMEND 80 0 sa pi ee s E ere ROMEND 60 01 ROMEND 40 o2 00 128 bytes ROMEND 20 NEM 00 MeL ENS ROMEND 01Lk 1 06 p 0p 0 0 32 bytes 64 96 bytes 128 bytes 4 9 4 See fig 7 15 See fig 7 14 See fig 7 13 See fig 7 12 Figure 7 11 Graphics ROM in the Four Color Modes 16W x 16H Tiles Panasonic Semiconductor Development Company 174 Panasonic 102 75 75 85 85 LSI User Manual 5 Display ROM ROMEND 90xN 1 ROMEND 1B0 ROMEND 18C ROMEND 168 ROMEND 144 ROMEND 120 ROMEND FC ROMEND D8 ROMEND B4 ROMEND 90 ROMEND 6C ROMEND 48 ROMEND 24 ROMEND Required bytes per tile Graphic Tile Codes Nisa multiple of 3 2 colors 4 colors 8 colors 16 colors Nx4 1 N x4 3 1 N 1 Nx2 1 03 04 06 R m 0 0B S Say 05 uy Ga ce Ge eda eed 0 03 PEE E SEEE G a 02 09 04 qawa le
174. 38 lt P36 DAGOUT G P31 CVBSO 28 37 4 gt P35 DAROUT R vss 29 36 lt VREF P34 P32 CVBS1 30 35 4 IREF VREFLS 31 34 COMP P33 CLL 32 33 AVDD Notes 1 Pins marked with an asterisk are N channel open drain pins 2 Pin 25 is Vpp in the MN102H85K and Vpp in the MN102HF85K Figure 1 9 MN102H85K Pin Configuration in Single Chip Mode Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 30 Panasonic General Description Pin Descriptions 1 6 2 MNI02HT75K Pin Description 8 a amp seg s 22522222 m soo 0 4 4 nn O0 o oW CNN lt lt lt lt lt D d wx G SG c G o O10 Q Q Q O O O O gt O gt QN Q OO r st r o ORG do do do P55 SBOO 4 1 63 P54 IRQ5 VSYNC lt 2 62 P71 P84 lt 3 61 lt P10 ADIN5 IRQ1 NC 4 60 gt P11 ADIN6 IRQ2 P53 RST lt lt 5 59 gt P12 ADIN7 IRQ3 P52 IRQ4 VIO lt 6 58 e P72 TEST gt 7 57 gt ADIN8 WDOUT P51 YS 4 8 56 gt P14 9 STOP P83 4 gt 9 55 P73 P50 SYSCLK 4 gt 10 54 gt P15 ADIN10 PWMO 84 Pin QFP P82 11 Top Vi 53 gt P16
175. 4 3 2 1 0 SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD YM3 2 B3 B2 0 G3 G2 Gl GO R3 R2 RI RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w w w w w w w w w w w w w w w w This register contains the color used as black in box shadowing When dig ital output is selected BBSHDYMO is output as YM BBSHDBO as B BBSHDOGO as and BBSHDRO as When the YS color palette is selected BBSHDY 3 is output as YS BBSHDYM 3 0 YM color code BBSHDBJ3 0 Blue color code BBSHDG 3 0 Green color code BBSHDR S 0 Red color code WBSHD White Box Shadowing Register x 007FA6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WB WB WB WB WB WB WB WB WB WB WB WB WB WB WB WB SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD SHD YMI YMO B3 B2 0 G3 G2 Gl GO R3 R2 RI RO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w w w w w w w w w w w w w w w w This register contains the color used as white in box shadowing When dig ital output is selected WBSHDYMO is output as YM WBSHDBO as WBSHDOGO as G and WBSHDRO as R When the YS color palette is selected WBSHDYM3 is output as YS WBSHDYW 3 0 YM color code WBSHDBJ3 0 Blue color code WBSHDG 3 0 Green color code WBSHDR S 0 Red color code GPT10 GPT1F Gr
176. 4 Flash ROM Address Space in Serial Programming Mode 323 B 5 RAM Address Space in Serial Programming 324 B 6 Microcontroller Clock Frequencies during Serial Programming 324 B 7 Programming Times for PROM and Serial Writers 0 00 eee cece eee 328 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 10 Panasonic List of Figures List of Figures 1 1 Conventional vs MN102H Series Code Assignments 19 1 2 Three Stage REN EME ER idet reiten 19 1 3 MN102H Series Interrupt Servicing 20 1 4 Internal Registers Memory and Special Function Registers 23 1 5 Address Space pornstars duc Cutie d tr ob bate RUBLE Sg Sle bale bah gue dee bif rg 24 1 6 Interrupt Controller Configuration 12 25 1 7 Interr pt Servicing Sequence or csp age eae CA Ree ee e at o Y e eH 25 1 8 Functional Block Diagram 222222222252 a ER 28 1 9 MN102H85K Pin Configuration in Single Chip 30 1 10 MN102H75K Pin Configuration in Single Chip
177. 5 kHz Bosc 256 93 75 kHz Bosc 512 48 875 kHz Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 78 Panasonic Timers 8 Bit Timer Block Diagrams 4 3 8 Bit Timer Block Diagrams Data bus X FE10 Timer 0 base register TMOBR Load Reload 8 FE00 3 5 0 binary counter 4 Timer 0 m TMOBC Underflow underflow Y 1 2 gt TM0O pin Y Reset 2 Bosc 4 0 Bosc 64 1 P2MD7 P2DIR7 setting 412 2 TMOI pin gt 3 Multiplexer Figure 4 3 Timer 0 Block Diagram Data bus Y 8 Ae 8 FE11 Timer 1 base register TM1BR Load ai Reload 21 FE01 Timer 1 binary counter mi TM1BC gt Timer 1 Underflow underflow m interrupt Y 1 2 gt TM1O pin Y Reset Bosc 4 0 P4MD1 P4DIR1 setting Bosc 64 1 Cascade from timer 0 2 TM1I pin 3 Multiplexer Figure 4 4 Timer 1 Block Diagram MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 79 Panasonic lt 8 Bit Timer Block Diagrams Data bus Ew 8 FE12 Timer 2 base register
178. 5K 64 pin SDIL MN102H85K F85K 102 75 75 85 85 LSI User Manual Panasonic Panasonic Semiconductor Development Company Descriptions 1 6 1 MN102H85K Pin Description Poo AMIN IRQO Pol SDM 2 1 2 Pos ADINO gt Pos anit gt os ADIN2 ADING ADIN4 P10 ADINS IRQ1 P11 ADING G2 P12 ADIN7 IROS P13 ADINe WDOUT gt P14 ADING STOP ADINIO PWMO P16 ADIN11 PWM yop ver P30 CLH VREFHS Pat evaso vss Paz cvest VREFLS P33 CLL 64 Pin SDIP Top View DAYMOUT YM DABOUT B DAGOUT G P35 DAROUT R VREF IREF come AVDD Notes 1 Pins marked with an asterisk are N channel open drain pins 2 Pin 25 is Vpp in the MN102H85K and Vpp in the MN102HF85K Figure 1 9 MN102H85K Pin Configuration in Single Chip Mode T o Pin Descriptions 1 6 1 MN102H75K Pin Description Pi ADINS IRQ2 P12 ADIN ROS P13 WOOUT ADING STOP Pra PIS PMO Top View S811 sept Notes 1 Pins marked with an asterisk are N channel open drain pins 2 Pin 41 is Vpp in the MN102H75K and Vpp in the MN102HF75K Figure 1 9 MN102H75K Pin Configuration in Single Chip Mode 1 6 2 MN102H75K Pin Description paa TMSIC Hit Paa TMSIOB HO 84 Pin QFP Top View s L wc 2 Le
179. 5K F85K LSI User Manual Panasonic Semiconductor Development Company 163 Panasonic 5 Display Display Setup Examples The text display starts one dot to the right of the HP setting VP HSZ 2 x 20 Y SZ 2 3 Wa oer SSS Seca a S gt i Line 1 CC x 000 CC x 001 CC x 002 _ No shadow No shadow No shadow VSZ 3 gt l 6 outline Outline Outline Background col 2 Background col 5 Background col 5 i Text color 1 Text color A Text color A VP x 40 Line 2 HSZ 0 1 006 007 007 007 CC 007 CC 007 008 CC 010 HP x 4 Box shad 1 Box shad 1 Box shad 1 Sameas Sameas Sameas shad 2 Box shad 2 lab Char shad Char shad Char shad lleft left left Outline Blank Blank Blank Blank Back col 6 Back col 6 Back col 6 Back col 7 Back col 7 VSZ 1 Text col 9 Text col 9 Text col 9 Text col 8 Text col 8 2x VP x70 Hes HSZ 3 4x HP x 10 CC x 300 CC x 310 Vates cm gt No shadow no outline No shadow no outline Background col 2 Background col 2 VSZ 1 Text color 1 Text color 1 2x Display end Figure 7 5 Text Display Example Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User
180. 6 The two LSBs of the leader are always 0 RMCS Remote Signal Clock Status Register x 007EA6 Bit T 6 4 3 2 1 0 LONG SHORT TSCNT5 TSCNT4 TSCNT3 TSCNT2 TSCNTI TSCNTO DF DF Reset 0 0 0 0 0 0 0 0 R W R W R W R R R R R R RMCS indicates the result of the short long data detection It is a 16 bit access register LONGDF Long data format detection Set to 1 when long data is detected SHORTDF Short data format detection Set to 1 when short data is detected TSCNT 5 0 6 bit counter value RMSR Remote Signal Reception Data Shift Register x 007EA8 Bit 7 6 5 4 3 2 1 0 RMSR7 RMSR6 RMSR5 RMSR4 RMSR3 RMSR2 RMSRI RMSRO Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R RMTR Remote Signal Reception Data Transfer Register X 007EAA Bit 7 6 5 4 3 2 1 0 RMTR7 RMTR6 RMTR5 RMTR4 RMTR3 RMTR2 RMTRI RMTRO Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R microcontroller shifts received data into RMSR converting it to paral lel data After it shifts in 8 bits it loads the data byte to RMTR The CPU reads the data from RMTR The data shifts from LSB to MSB RMSR and RMTR are 8 or 16 bit access registers Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 226 Panasonic Closed Caption Decoder Description 9 Closed Caption Decod
181. 6W x 18H Tiles MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 177 Panasonic On Screen Display Setting Up the OSD 7 10 7 10 1 Setting the OSD Setting Up the OSD Display Colors This section describes how to set up the display colors for the OSD To set up the color palettes Write your settings to the color palette registers shown in table 7 8 Table 7 8 Color Palette Registers Layer Palette Address Applications Text CPTO CPTF x 007F80 Text foreground and background colors x 007F9E All layers COLB x 007FAO0 Color background Text FRAME x 007FA2 Outlining and character shadowing colors BBSHD 007 4 Box shadowing color black WBSHD x 007FA6 Box shadowing color white Graphics GPT10 x 007FCO0 Tile color palette 1 cursor 1 x 007FDE GPT20 007 0 Tile color palette 2 GPT2F x 007FFE To set up the cursor display colors Write to the fields described below GCOLI1 0 x 007F08 bits 9 and 8 sets the number of colors 2 4 8 or 16 STC 8 0 007 10 bits 8 to 0 specifies the code of the to be displayed SPRT x 007F10 bit 9 selects tile color palette 1 or 2 x 007FC0 007FDE or GPT2n x 007FE0 x 007FFE speci fies the colors on the palettes corresponding to the tile data stored in the ROM Tosetup the graphics display colors
182. 7 2 Cursor Tiles in Standard and Extended Modes MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 159 Panasonic 5 Display Standard Extended Display Modes You cannot use the tiles created for graphics layer extended mode as cursor tiles Table 7 4 Associated Tiles for Cursor Tile Code Registers Graphic Tile Register Register Address 1 Upper left STCO x 007F10 2 Upper right STC1 x 007F2A 3 Lower left STC2 x 007F2C 4 Lower right STC3 x 007F2E In standard mode STCO is the only cursor tile code register that is enabled Use the cursor horizontal position register SHP 00 127 and the cursor vertical position register SVP x 007F14 in both modes to program the display start position In extended mode this position refers to the upper left corner of tile 1 Set the color palette for each tile individually 7 6 2 Graphics Layer Display Modes The size of the tiles in the graphics layer is programmable to 16W x 16H pixels in standard mode and 16W x 18H pixels in extended mode Select the mode for this layer in the GTHT bit of the OSD2 register 007 08 In extended mode the tiles are the same size as the characters in the text layer This allows for a cleaner display when text and graphics appear side by side Display start position Display start position set in GHP and GVP 16 pixel set in GHP 16
183. 7 36 Field Detection Circuit Block Diagram 7 14 2 Description The 7 bit field counter in this block resets every HSYNC interval to count the system clock At each VSYNC interval the 4 MSBs of the 7 bit counter are alter nately loaded made readable to bits 7 to 4 N2 and 3 to 0 N1 of the EVOD register x 007FOE The comparator compares the N1 and N2 values and outputs the results to EOMON bit of EVOD The OSD identifies the field that sets EOMON to 1 as the display start field Table 7 15 shows the criteria that the comparator uses By reading the FRMON bit of EVOD the OSD can determine which register the 4 MSBs will load to on the next VSYNC input To ensure that the display starts at the right field you must also set the EOSEL bit of EVOD so that EOMON becomes 1 at the display start field 1 I TTT Field counter value Load value to FREG2 Load value to FREG1 Figure 7 37 Field Detection Timing MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 201 Panasonic 5 Display Field Detection Circuit Table 7 15 EOMON Output Criteria EOMON Output FRMON N1 N2 Relationship EOSEL 0 EOSEL 1 0 N1 gt 0 1 Load to 2 next N1 lt 1 0 N1 N2 Complement previous Complement previous 1 N1 gt N2 1 0 Load to 1 next N1 lt 0 1 N1 N2 Compleme
184. 7EE8 bits 6 0 Reference Level Clamping Type CCD0 CCD1 Sync tip 16 dec 16 dec clamping Pedestal Value in Value in clamping PCLV PCLVW 007 x 007EEC Value SYNCMIN 007 8 bits 14 8 Value in SYNCMINW x 007EE8 bits 14 8 102 75 75 85 85 1 81 User Manual Panasonic Semiconductor Development Company 229 Panasonic Closed Caption Decoder Functional Description Table 9 4 Current Level Control Current Source Control Low Current Medium Current High Current Conditions 1 2 3 4 5 6 10 lt Off On Off On 4 lt A lt 9 Off On Off On Off Off 1 lt A lt 3 Off On Off Off Off Off A 0 Off Off Off Off Off Off 3 lt lt 1 Off Off Off Off Off 9 lt lt 4 Off On Off Off Off lt 10 Off On Off On Off Notes 1 compare level reference level 2 The numbers 1 to 6 correspond to the same number in figure 9 5 Table 9 5 provides the registers used to control and monitor the clamping circuit See the page number indicated for register and bit descriptions Table 9 5 Control Registers for Clamping Circuit CCDO CCD1 Register Page Address Address Description Register for selecting the low pass filter NFSEL 242 x 007ECO x007EEO Noise filter select register Registers for controlling clamping SCMING 243
185. 8 2 VRAM Organization Graphics RAM Addresses When GEXTE 1 GRAMEND 40xN 5 Line N data GRAMEND 40x N 1 Program ER Data and Stack Area Graphics VRAM GRAMEND 3F x 008000 GRAMEND 3c Unused area GRAMEND 3D GRAMEND 3c Unused area GRAMEND 3B GRAMEND 40xn 5 Code 30 Line n data GRAMEND 2F Code 29 GRAMEND 40x n 1 GRAMEND 2E GRAMEND 7B Line 2 data GRAMEND 40 GRAMEND 3 Low order 8 bits GRAMEND 2 of graphics code GRAMEND 3B 7 Line 1 data 64 bytes GRAMEND 1 High order 8 bits 2125506 GRAMEND i n ________ GRAMEND of graphics code GRAMEND 40xN 5 GRAMEND CRAMEND 50xM 1 Text RAM Addresses CRAMEND 50xM 1 Line M data CRAMEND 50x M 1 CRAMEND 50xm 1 dE Line m data CRAMEND 4D Code ag CRAMEND 50x m 1 CRAMEND 4C i CRAMEND 4B CRAMEND 9F Line 2 data CRAMEND 50 CRAMEND 4F CRAMEND 3 Line 1 data CRAMEND 2 of text code bod CRAMEND COC CRAMEND of text code Notes 1 addresses are expressed in hex notation Other values are decimal 2 GRAMEND Graphics RAM end address programmable to any address 3 CRAMEND Text RAM end address programmable to any address 4 M Number of lines in the text layer 5 m 1 and up 6 N Number of lines in the graphics layer 7 n 1 and up Figure 7 6 VRAM Organization When GEXTE 0 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Compa
186. 85 85 LSI User Manual 60 Panasonic Interrupts Interrupt Control Registers RMCICL Remote Signal Receive Interrupt Control Register Low x 00FC76 Bit 7 6 5 4 3 2 1 0 RMC RMC z 2 IR lt uM ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R RMCICL detects and requests remote signal receive interrupts It is an 8 bit access register Use the MOVB instruction to access it RMCIR Remote signal receive interrupt request flag 0 No interrupt requested 1 Interrupt requested RMCID Remote signal receive interrupt detect flag 0 Interrupt undetected 1 Interrupt detected RMCICH Remote Signal Receive Interrupt Control Register High x 00FC77 Bit T 6 5 4 3 2 1 0 RMC IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W RMCICH enables remote signal receive interrupts It is an 8 bit access regis ter Use the MOVB instruction to access it The priority level for remote signal receive interrupts is written to the TM2UDLYV 2 0 field of the TM2UDICH register RMCIE Remote signal receive interrupt enable flag 0 Disable 1 Enable ADM3ICL Address Match Interrupt Control Register Low x 00FC78 Bit 7 6 5 4 3 2 1 0 X p ADM3 ADM3 IR ID Reset 0 0 0 0 0 0 R W R R R R W R R R R ADMS3ICL detects and requests address match 3 interrupts It is an 8 bit access register Use the MOVB instructi
187. 89 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 158 Panasonic 5 Display Standard Extended Display Modes 7 6 Standard and Extended Display Modes Two modes are available for the graphics and cursor layers standard and extended In extended mode the cursor layer can display four grouped graphic tiles rather than one The graphics layer can display tiles that are two pixels taller than those used in standard mode giving the graphic tiles the same dimensions as the characters in the text layer 7 6 1 Cursor Layer Display Modes The size of the cursor in the cursor layer is programmable to 16W x 16H pixels in standard mode and 32W x 32H pixels in extended mode Select the mode for this layer in the SPEXT bit of OSD2 register 007 08 To create a graphic for the cursor layer in extended mode combine four 16 x 16 tiles They are ordered as follows 1 upper left 2 upper right 3 lower left and 4 lower right Set the pointers to these tiles in cursor tile code registers 0 to 3 5 0 3 where STCO corresponds to tile 1 Table 7 4 shows the associated tiles and registers Display start position Display start position set in SHP and SVP set SHP SVP n 16 pixels Z 16 pixels 16 pixels 16 pixels 1 2 A Standard Mode 16W x 16 B Extended Mode 32W x 32H Figure
188. 91 Hangangro 2ga Youngsan ku Seoul 140 702 KOREA Tel 82 2 795 9600 Fax 82 2 795 1542 280901 Printed in JAPAN
189. A Tel 1 201 348 5257 1 201 392 4652 Chicago Office 1707 Randall Road Elgin Illinois 60123 7847 U S A Tel 1 847 468 5720 1 847 468 5725 Milpitas Office 1600 McCandless Drive Milpitas California 95035 U S A Tel 1 408 942 2912 1 408 946 9063 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee GA 30024 U S A Tel 1 770 338 6953 1 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 U S A Tel 1 619 503 2903 1 858 715 5545 e Canada Sales Office Panasonic Canada Inc PCI 5770 Ambler Drive 27 Mississauga Ontario LAW 2T3 CANADA Tel 1 905 238 2101 1 905 238 2414 E LATIN AMERICA e Mexico Sales Office Panasonic de Mexico S A de C V PANAMEX Amores 1120 Col Del Valle Delegacion Benito Juarez C P 03100 Mexico D F MEXICO Tel 52 5 488 1000 Fax 52 5 488 1073 Guadalajara Office SUCURSAL GUADALAJARA Av Lazaro Cardenas 2305 Local G 102 Plaza Comercial Abastos Col Las Torres Guadalajara Jal 44920 MEXICO Tel 52 3 671 1205 OG Brazil Sales Office Panasonic do Brasil Ltda PANABRAS Caixa Postal 1641 Sao Jose dos Campos Estado de Sao Paulo Tel 55 12 335 9000 55 12 331 3789 B EUROPE U K Sales Office Panasonic Industrial Europe Ltd PIEL Willoughby Road Bracknell Berks RG12 8FP THE UNITED KINGDOM Tel 44 1344 85 3671 44 1344 85 3853 Ge Germany Sales Office Panasonic Industrial E
190. AE 9469 COL BSHAD 2 CSHAD 1 FRAME 0 BCOL x 6 CCOL x 9 9FAC 0006 CC Character code x 006 9FAA 0007 CC Character code x 007 9FA8 4012 CCB Repeat character code CCB x 2 9FA6 9A78 COL BSHAD 3 CSHAD 0 FRAME 1 BCOL x 7 CCOL x 8 9FA4 0008 CC Character code x 008 9FA2 4002 CCB Blank CCB x 2 9 0 0010 CC Character code x 010 9F9E D810 CHP CHSZ x 3 CSHT 0 CHP x10 9F9G C870 CVP CLAST 0 CVSZ x1 CINT 0 CVP x 70 3 9F5E 0300 CC Character code x 300 9F5C 0310 CC Character code x 310 9F5A C044 CHP CHSZ x 0 0 CHP x 44 9F58 E030 CVP CLAST 1 CVSZ x 0 CINT 0 CVP x 30 Notes 1 Always specify the color code COL or character code CC at the beginning of each line If CC is the first code no COL the foreground text color will be color 1 on the palette and the background will be color 2 2 Always specify CHP and in that order at the end of each line A CC code must immediately follow a COL code 4 If you repeat a character with the CCB code precede CCB code with a CC code and follow it with a COL or CC code Set CINT to 1 in the CVP setting to generate an OSD text interrupt Set CLAST to 1 in the CVP setting for the last line in the text display Also set the CVP value to a smaller value than the position of the current line In the example in table 7 6 x 30 is smaller than v 70 MNI02H75K F75K 8
191. B R W Serial 1 reception end interrupt control register high I2CICL x 00FC9C R W PC interrupt control register low I2CICH x 0O0FC9D R W 12 interrupt control register high Note The interrupt error interrupt control register does not exist in the hardware but if no matching interrupt vector is found for an interrupt that occurs the CPU writes a C to IAGR to indicate that it detected an abnormality MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 47 Panasonic Interrupts Interrupt Control Registers The watchdog timer interrupt is provided for detecting and handling racing Normal operation is not guaranteed if the program returns after a watchdog interrupt For actions requiring returns use a timer interrupt IAGR Accepted Interrupt Group Number Register x 00FC0E Bit 15 14 13 12 11 10 9 8 7 6 2 4 3 2 1 0 GN5 GN4 GN3 GN2 GN1 GN0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IAGR returns the group number of an accepted interrupt indicated in the 6 bit GN field When the interrupt handler has to calculates the header address for the interrupt service routine it merely needs to add the contents of IAGR to the header address for the table in which are registered the vec tor addresses for servicing all interrupts 15 16 bit access register GN 5 0 Group Number
192. B interrupts It is an 8 bit access register Use the MOVB instruction to access it 5 2 0 Timer 5 compare capture B interrupt priority level Sets the priority from 0 to 6 TMSCBIE Timer 5 compare capture B interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 56 Panasonic Interrupts Interrupt Control Registers TM5CAICL Timer 5 Compare Capture Interrupt Control Register Low x O0FC6A Bit 7 6 5 4 3 2 1 0 5 5 z 7 m ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R TMSCAICL detects and requests timer 5 compare capture interrupts It is an 8 bit access register Use the MOVB instruction to access it TM5CAIR Timer 5 compare capture A interrupt request flag 0 No interrupt requested Interrupt requested TM5CAID Timer 5 compare capture A interrupt detect flag 0 Interrupt undetected Interrupt detected TMSCAICH Timer 5 Compare Capture A Interrupt Control Register High x 00FC6B Bit 7 6 5 4 3 2 1 0 5 IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W TMSCAICH enables timer 5 compare capture interrupts It is 8 bit access register Use the MOVB instruction to access it The priority level for timer 5 compare capture interrupts is written to the TMSCBLV 2 0 field of the TMSCBICH regist
193. C2 Crystal PLL 48 2 with 4 2 osc 0 1 OSDXI LC blocking fx OSDXO oscillator 1 0 OSDXI Crystal LC fx OSDXO oscillator or other excitation 1 1 Reserved If your design uses the OSDX clock set the XIO bit x 007F06 bit 7 for the appropriate frequency 0 Less 20 MHz 1 Greater than 20 MHz Selecting the divide by ratio There are five divide by settings available for any of the clocks described above Table 7 11 shows the register settings for each ratio Table 7 11 OSD Dot Clock Division Settings 6 5 cod Divide py Ratio 0 0 0 1 4 12 MHz 0 0 0 1 1 3 16 MHz 0 1 0 1 2 24 MHz 7 0 1 1 2 3 32 MHz 1 0 0 1 1 48 MHz 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Notes 1 Thisis the frequency with a 48 MHz clock source MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 193 Panasonic 5 Display Controlling the Shuttering Effect 7 13 Controlling the Shuttering Effect The MN102H75K 85K OSD achieves a shuttering effect using four pro grammable shutters two vertical and two horizontal With this feature you can shutter any portion of the OSD display or you can combine shuttering with a wipe out effect to create a smooth appearing and disappearing effect To prevent flickering and shadows on the display only write to the registers du
194. CA and TMnCB operating mode select 00 Compare register single buffer 01 Compare register double buffer 10 Capture register TMnIOA high capture A TMnIOA low capture B 11 Capture register TMnIOA high capture A TMnIOB high captureB TMnECLR Timer n BC external clear 0 Don t clear 1 Clear TMnBC asynchronously when the TMnIC signal goes high TMnLP Timer n BC loop select 0 0000 FFFF 1 0000 value in TMnCA TMnASEL TMnIOA output select 0 S R flip flop output single phase PWM 1 T flip flop output two phase PWM TMnS 2 0 Timer n clock source select 000 Timer 0 underflow 001 Timer 1 underflow 010 TMnIB signal 011 Bosc 4 100 4x two phase encoder 101 1x two phase encoder 110 111 Reserved Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 126 Panasonic Serial Interfaces Description 5 Serial Interfaces 5 1 Description The MN102H75K 85K contains two general purpose serial interfaces with syn chronous serial UART and I C modes The maximum baud rate in synchronous serial mode is 12 Mbps In UART mode the maximum baud rate is 375 000 bps when Bosc 24 MHz Signal from 8 bit timers TMOIR Tx end interrupt TXD gt SBOO Transmitter SBTO Rx end interrupt RXG lt D y Receiver SBI0 TXD 2 SBO1 Tx end interrupt Transmitter I Rx end interrupt Recei
195. Company 165 Panasonic 5 Display BLINK Specifies character blinking 0 Disable 1 Enable BCOL 3 0 Specifies the background color 1 of 16 colors CCOL 3 0 Specifies the foreground character color 1 of 16 colors COL Color Control Code Closed Caption Mode ID Code 10 CUNDL Specifies underlining 0 Disable 1 Enable ITALIC Specifies italicization 0 Disable 1 Enable FRAME Specifies character outlining black 0 Disable 1 Enable BLINK Specifies character blinking 0 Disable 1 Enable BCOL 3 0 Specifies the background color 1 of 16 colors CCOL 3 0 Specifies the foreground character color 1 of 16 colors CCB Repeat Blank Character Code ID Code 01 CCBF Repeat blank repeat character select 0 Repeat blank Repeat character CCB 3 0 Specifies the number of times up to 16 a blank space or character is repeated This function saves RAM space by preventing the VRAM address from incrementing The program redisplays the preceding charac ter code the specified number of times This increases the limit beyond 38 characters per line Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 166 Panasonic 5 Display VRAM a In closed caption mode only the b 00 b 01 and b 11 settings are available for CVSZ 1 0 The b 10 setting is reserved CHP Character Horizontal Position
196. D 59 ROMEND 54 Line 2 data ROMEND 53 ROMEND 4E Line 3 data ROMEND 4D 96 bytes ROMEND 1C ROMEND 1B ROMEND 06 Line 15 data ROMEND 05 ROMEND Line 16 data Line 1 ine heet 3 lt Line 2 li heet 2 mee heet 1 Graphics tile 16 bits 8 color mode A 1 dot 3 bits 8 colors ROMEND 5 ROMEND 4 ROMEND 3 ROMEND 2 ROMEND 1 ROMEND Line 16 Bit 0 Bit 15 Sheet 3 bits 7100 Sheet 3 bits 15 to 8 Figure 7 14 Graphics ROM Organization in 8 Color Mode 16W x 16H Tiles ROMEND 3F ROMEND 3C Line 1 data ROMEND 3B ROMEND 38 ROMEND 37 ROMEND 34 Line 2 data Line 3 data ROMEND 33 64 bytes ROMEND 08 ROMEND 07 ROMEND 04 Line 15 data ROMEND 03 ROMEND Line 16 data Graphics tile 4 color mode 1 dot 2 bits 4 colors 16bts i ia Line 1 heet 214 Line 2 Line 3 heet 1 Line 16 Sheet 1 bits 7 to 0 Sheet 1 bits 15 to 8 ROMEND 3 ROMEND 2 ROMEND 1 ROMEND Bit 0 Bit 15 Figure 7 15 Graphics ROM Organization in 4 Color Mode 16W x 16H Tiles ROMEND 1F ROMEND 1E ROMEND 1D ROMEND 1C ROMEND 1B ROMEND 1A ROMEND 19 32 bytes ROMEND 04 ROMEND 03 ROMEND 02 ROMEND 01 ROMEND Line 1 data Line 2 data Line 3 data Line 15 data Line 16 data Graphics tile 2 color
197. DIN8 conversion data buffer AN9BUF x 0OFF1A R 9 conversion data buffer AN10BUF XOOFF1C R ADIN10 conversion data buffer AN11BUF 00 1 R ADIN11 conversion data buffer ANOBUF AN11BUF ADINO ADIN11 Conversion Data Buffers 00 00 00 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ANn ANn ANn ANn ANn ANn ANn BUF6 5 BUF4 BUF3 BUF2 BUFI BUFO Reset 0 0 0 0 0 0 0 0 These buffers hold 8 bit A D conversion data Their value is unknown after reset Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 150 Panasonic Analog to Digital Converter ADC Control Registers ANCTR ADC Control Register x 00FF00 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 NCH3 NCH2 1CH3 2 ICH0 CKO 1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW R W RW RW RW RW RW RW RW R R RW RW RW RW ANNCH 3 0 Channel select for multiple channel conversion 0000 Convert ADINO 0111 Convert ADINO ADIN7 0001 Convert ADINO ADINI 1000 Convert ADINO ADINS 0010 Convert ADINO ADIN2 1001 Convert ADINO ADIN9 0011 Convert ADINO ADIN3 1010 Conver
198. Development Company 87 Panasonic Timers 16 Bit Timer Description 4 7 16 Bit Timer Description The MN102H75K 85K contains two 16 bit up down timers timers 5 and 6 Associated with each timer are two compare capture registers that can capture and compare the up down counter values generate PWM signals and generate interrupts The PWM function has a double buffering mode that causes cycle and transition changes to occur at the beginning of the next clock cycle This prevents PWM signal losses and minimizes waveform distortion during timing changes Timers 5 and 6 can serve as interval timers event counters in clock oscillation Y mode one or two phase PWMs dual capture inputs dual two phase encoders one shot pulse generators and external count direction controllers The clock Underflow interrupts can only source can be the internal clock the external clock or the TMOUDIR or occur during down counting TMIUDIR signals from the 8 bit timers TMnIC TMOUDIR TM1UDIR CLR Bosc 4 Up down counter encoding Match TMnIB 7 16 bit compare capture A gt TMnOA Capture TMnIA R S Q 16 bit compare capture A Capture T0 gt TMnOB Match Note Bosc 24 MHz Figure 4 14 Block Diagram of 16 Bit Timers Panasonic Semiconductor Development Company 102 75 75 85 85
199. Diagram uere em ED RU E quei ed e bnt 250 10 3 PWM Data Registers etre pe pb ER nre ie Seed 250 Panasonic Semiconductor Development Company 102 75 75 LSI User Manual Panasonic Contents 11 munti u u eI reise ERI kata ga iud 251 11 1 Description ii hu ai hu DU ERU E EIE EE L d n si t p ERES 251 11 2 Port Circuit Diagrams 2 1 252 11 3 Port Control Registers senne nn b tee peeeP Ode pRB eS a sasi COE SS 277 12 ROM Correction Een 288 12 1 D sciptOn a sp qa CERRAR UR PRN Bee RAE RA AR As He RARUS ee 288 12 2 Block Diagram ione pm dex Ever i bu Er HE IO DUE pe Reg 289 12 3 Programming 2 2 1 289 12 4 ROM Correction Control 1 290 13 C Bus 293 13 1 Description en e eb eR do o E ES d enis idit qi ti 293 13 2 Block Diagram cis durer RIT nrw RW es ER Pi piss e pap pee tus 206 13 3 Functional Description ger RR Rp RR ERREUR ET NR EE 296 13 4 Setting Up the YC B s Connections edad am atin teachin E 298 13 5 SDA and SCL Waveform Characteristics 299 13 6 Interface Setup Examples 2225 Sekiya
200. E eee Ree e 129 5 5 1 Synchronous Serial Mode 129 5 5 2 UART Mode TIMIN ort ne det et ee utei 130 5 6 Serial Interface Setup Examples 1 131 5 6 1 Setting Up UART Transmission Using Serial Interface 0 131 5 6 2 Setting Up Synchronous Serial Reception Using Serial Interface 0 134 5 6 3 Setting Up the Serial Interface 135 5 6 4 Setting Up Transmission Using Serial Interface 0 137 5 6 5 Setting Up Pc Reception Using Serial Interface 0 139 5 7 Serial Interface Control Registers 140 6 Analog to Digital 143 6 1 Descriptionz usce een s E e E EN E Ea eeiam Een 143 6 2 Features be e deo tod e e e M eot eg 143 6 3 Block Diagram E DEDI du tS EH E decreti dai E 144 6 4 A D Conversion Timing 22252522 pt EE esr pelo qma t pat eee dae ins 144 6 4 1 Selecting the ADC Clock 144 Panasonic Semiconductor Development Company 102 75 75 LSI User Manual Panasonic Contents 6 4 2 Single Channel Single Conversion Timing
201. EM Matsushita Electric Indus trial Co Ltd Third party PROM writer Gang writer DELLI 0000000 Model 1930 Electronics 4105 Yamada cho Tsuzuki ku Yokohama Japan Tel 045 591 5605 Single unit writer Model LabSite DIP 48 1 OEM DATA I O Osaki Building 2F 5 10 10 Osaki Shinagawa ku Tokyo Japan Tel 03 3779 2040 Check the following web page of our microcomputer division for the writer matching information http www mec panasonic co jp sc division micom Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 318 Panasonic MN102HF75K Flash Version Using the Onboard Serial Programming Mode B 4 Using the Onboard Serial Programming Mode The serial programming mode is primarily used to program the flash ROM in devices that are already installed on a PCB board Panasonic provides the ded icated hardware and software for this mode This section describes the microcon troller hardware system configuration software register map and protocol for this type of programming operation Onboard serial writer Television set Serial communication ll D Program pu for TV 16 bit microcontroller with flash EEPROM Figure B 4 Serial Writer Programmin
202. External Reset Control Timing Timer 5 Panasonic Semiconductor Development Company 124 Panasonic MN102H75K F75K 85K F85K LSI User Manual Timers 16 Bit Timer Control Registers 4 12 16 Bit Timer Control Registers Table 4 6 shows the registers used to control the 16 bit timers A binary counter TMnBO a compare capture register TMnCA a compare capture register B TMnCB and a timer mode register TMnMD is associated with each 16 bit timer Table 4 6 16 Bit Timer Control Registers Register Address R W Description Timer 4 TM4MD x 00FE80 Timer 4 mode register TM4BC x 00FE82 R Timer 4 binary counter TM4CA 00 84 Timer 4 compare capture register A TM4CAX x 00FE86 Timer 4 compare capture register set AX TM4CB 00 88 Timer 4 compare capture register TM4CBX x 00FE8A Timer 4 compare capture register set BX Timer 5 TM5MD x 00FE90 Timer 5 mode register 5 x 00FE92 R Timer 5 binary counter 5 x 00FE94 Timer 5 compare capture register A TMSCAX x 00FE96 Timer 5 compare capture register set AX 5 x OOFE98 Timer 5 compare capture register 5 x 00FE9A Timer 5 compare capture register set BX Note TM4CBX 5 and 5 are
203. F AN4BUF OOFF20 OOFF30 OOFF40 OOFF50 OOFF60 FAR Flash memory write control OOFF70 FBEWER EGEX FAREG FDREG FCREG registers External memory wait control 00FF80 MEMMD1 EXWMD registers 00FF90 2 PCNT1 OOFFAO test register P8 P7 Pe P5 P2 PO 00 0 PUP PUP PUP PUP PUP PUP PUP PUP PUP P8 P7 Pe P5 2 PI PO i our our our our our our our port control registers P8 7 Pe P5 2 PO OOFFDO IN IN IN IN IN N IN IN IN P8 P7 Pe 5 2 PI PO 00 0 DIR DIR DIR DIR DIR DIR DIR DIR DIR P6 P5 P4 P3 OOFFFO MD MD MD mp P2MD MD Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 314 Panasonic Register 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 315 Panasonic MN102HF75K Flash EEPROM Version Description Appendix BMN102HF75K Flash EEPROM Version A cycle of erasing to programing is counted as one time no matter how many blocks are rewritten Even when the multi block is rewritten separately or the same block is rewritten each block rewrite is counted For example rewriting Block1 Block2 and Block3 respec tively is counted as 3 times There fore to program efficiently rewrite all blocks in the lump B 1 Description
204. I frequency width 1 This field indicates the width in clock units from the first to the second rising edge after the CRI CRIFB CRI Frequency Width Register B x 007E0E CRIFBW x 007E2E Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRI4 CRB CRB CRIB CRB CRB CRB CRB CRB FQW7 FQW6 5 FQW4 FQW3 FQW2 FQWI FQWO FQW7 FQW6 5 FQW4 FQW3 FQW2 FQW1 FQWO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R CRI4FQW 7 0 CRI frequency width 4 This field indicates the width in clock units from the fourth to the fifth ris ing edge after the CRI CRISFQW 7 0 CRI frequency width This field indicates the width in clock units from the third to the fourth rising edge after the CRI CRI1S CRI Capture Start Timing Control Register 1 x 007E10 CRI1SW x 007E30 Bit 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 CRIIS CRIIS CRIIS CRIIS CRIIS CRIIS CRIIS CRIIS CRIS CRIIS CRIIS 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R R RW RW RW RW RW RW RW RW RW RW CRI1S 10 0 Start position for CRI capture 1 Valid range x 000 to x 7FF Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manu
205. IGOJA Joyesaueb es nd peo dn ou s 13Sd3SA o g AIGO4 0 2 1IN1d3SA d3SA es nd o g LnO4d1 to i wsaN Jojeredes ou S Io msan Joyesedas ONASA lo 9 unor4d1 dWVSd3SA 0 1 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 231 Panasonic Closed Caption Decoder Functional Description Table 9 6 Control Registers for Sync Separator Circuit CCDO CCD1 Register Page Address Address Description Register for setting the sync separator level SPLV 244 x007ECA x 007EEA Sync separator level set register Register for controlling the sync separator clock FQSEL 243 x 007EC2 007 2 Frequency select register Registers for controlling the HSYNC separator HSEP1 246 x007ECE x007EEE HSYNC separator control register 1 HSEP2 246 x007EDO x 007EFO HSYNC separator control register 2 HLOCKLV 246 x 007ED4 x O07EF4 Sync separator detection control register 1 HDISTW 247 007 06 x 007EF6 Sync separator detection control register 2 Register for controlling the VSYNC separator VONT 247 x007EDS8 007 8 VSYNC separator control register Register for controlling the field detection FIELD 246 x 007ED2 x 007EF2 Field detection control register Register for monitoring the sync separator status
206. IMD x OOFE2I Timer 1 mode register Timer 2 TM2BC 00 02 R Timer 2 binary counter TM2BR x 00FE12 Timer 2 base register TM2MD x O0FE22 Timer 2 mode register Timer 3 TM3BC 00 03 R Timer 3 binary counter TM3BR x 00FE13 Timer base register TM3MD x 00FE23 Timer 3 mode register TMOBC TM3BC Timer n Binary Counter x 00FE00 x 00FE03 Bit 7 6 5 4 3 2 1 0 TMn TMn TMn TMn TMn TMn TMn TMn BC7 BC6 5 BC4 BC3 BC2 BCO Reset 0 0 0 0 0 0 R W R R R R R R R R TMOBR TM3BR Timer n Base Register x 00FE10 x 00FE13 Bit 7 6 5 4 3 2 1 0 TMn TMn TMn TMn TMn TMn TMn TMn BR7 BR6 BR5 BR4 BR3 BR2 BRI BRO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W TMOMD TM3MD Timer n Mode Register x 00FE20 x 00FE23 Bit 7 6 5 4 3 2 1 0 TMn TMn TMn EN LD 51 50 Reset 0 0 0 0 0 0 0 0 R W R W R W R R R R R W R W TMnEN TMnBC count enable 0 Disable 1 Enable TMnLD TMnBR value load to TMnBC 0 Do not load value 1 Load value TMnS 1 0 Timer n clock source select See table 4 1 on page 78 for clock sources 00 clock source 0 01 clock source 1 10 clock source 2 and 11 clock source 3 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor
207. IN1 lt Figure 11 23 P51 YS Port 5 MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 273 Panasonic Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on c P5PUP2 0 52 1 IRQ4 VI0 70 a N LL 0 Port input 1 Port output P5DIR2 0 Port low output Pin 1 Port high output w 4 P5OUT2 2 P52 IRQ4 VI0 Schmidt trigger P5IN2 lt ff IRQ4 VIO lt Figure 11 24 P52 IRQ4 VIO Port 5 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 274 Panasonic Ports 1 0 Port Circuit Diagrams 1 Pullup on 0 Pullup off P5PUPS 0 Port low output 1 Port high output P5OUT3 p 0 Port input 1 Port output lt gt P5DIR3 r vd P53 RST TIT NTGTRST 4 Schmidt trigger Figure 11 25 P53 RST Port 5 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 275 Panasonic Ports I O Port Circuit Diagrams 0 Pullup off 1 Pullup on lt P5PUP4
208. INS 10 WDOUT 11 Reserved P1MD4 P12 function switch 0 2 1 ADIN7 P1MD2 P11 function switch 0 11 2 1 ADIN6 P1MD0 P10 function switch Control the IRQ3 2 and IRQI interrupt enable settings in the inter rupt control registers 0 PIO IRQI 1 ADINS Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 280 Panasonic Ports I O Port Control Registers P2MD Port 2 Output Mode Register x O0FFF4 Bit 15 14 13 12 11 10 9 8 6 4 2 1 0 P2MD P2MD P2MD P2MD P2MD P2MD P2MD P2MD P2MD P2MD P2MD d 14 13 12 11 10 9 8 6 4 2 7 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R RW RW RW RW RW RW R W R W R W R R W P2MD 13 12 P26 output and function switch P2MD 11 10 P25 output and function switch P2MD 9 8 P24 output and function switch 2 is a 16 bit access register P2MD14 P27 function switch To use TMOIO an output pin set this bit to 1 and set the P2DIR7 bit to 1 0 P27 1 TMOIO To use TMAIOA as an output pin set this field to b 01 and set the P2DIR6 bit to 1 00 P26 01 TM4IOA 10 SBOI 11 Reserved If you set this field to b 10 select SBI1 or SBDI in bit 11 of PCNTO To use TM4IOB as an output pin set this field to b 01 and set the P2DIRS bit to 1 00 P25 01 TM4IOB 10 SBI or SBD1 11 Reserved To use SBTI as an input
209. IR remote signal receiver the H counter that use PWM waveforms The OSD cannot display in SLOW mode For information on invoking SLOW mode from NORMAL mode see MN102H Series LSI User Manual MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 73 Panasonic Low Power Modes CPU Modes 1 Using OSDX clock both LG blocking oscillator and external source OSDXI and OSDXO must be set to port P46 P45 and output H before invoking STOP mode 3 1 3 Notes Invoking Exiting STOP and HALT Modes When invoking STOP and HALT modes To reduce power consumption before invoking the STOP or HALT mode stop current flow from output pins and stabilize the input level of input pins For output pins either match the output level to the external level or set the pin to input For input pins ensure that the external level is fixed To further reduce power consumption shut down unnecessary functions through the control reg isters See section 3 2 Turning Individual Functions On and Off on page 75 Before entering the STOP mode set all of the bits shown in table 3 1 to disable all of these functions Disable all functions in the NORMAL mode except the PLL circuit which you can only shut down once you have entered the SLOW mode To allow the MCU to exit the STOP or HALT mode on reset or interrupt you must set the interrupt registers before you invoke the standby mod
210. K F75K 85K F85K LSI User Manual 104 Panasonic Timers 16 Bit Timer Setup Examples With PWM output the duty cycle can change dynamically which can cause the PWM waveform to skip a pulse see the single buffering section of figure 4 34 below To prevent these misses timers 4 and 5 provide a double buffer mode In this mode no matter what the timing of a TMnCB the duty change does not occur until the beginning of the next cycle and no signals are lost Per formance is assured even when the output switches from all 18 to all 0s see the double buffering section of figure 4 34 below For this reason you must always use double buffer mode for PWM waveform output Use single buffer mode only in applications that are unaffected by this issues TM4EN Write to 4 TM4CB TM4BC Bosc 4 CLRBC4 1 Double buffering TM4CB TM4CBX B4 A4 TM40A TM40B Interrupts 2 Single buffering 171174 No PWM ot intetrupt errors TM4CB B4 A4 TM40A TM40B Interrupts
211. LOSE E9 E8 E7 E6 E5 E4 E3 E2 El E0 Reset 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 R RW RW RW RW RW RW RW RW RW RW HCLOSEE 9 0 Start position for HSYNC detection Set the position in HSYNC separator sampling clock units The valid range is X 000 to x 3FF and the recommended setting is x 00E4 FIELD Field Detection Control Register x 007ED2 FIELDW x 007EF2 Bit 15 14 13 12 11 10 9 8 7 6 3 4 2 2 1 0 ODD V V V V V V EVEN PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE PHASE 9 8 7 6 9 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 RW R R R R R R RW RW RW RW RW RW RW RW RW RW ODDEVEN Field detection signal 0 Odd field 1 Even field VPHASE 9 0 Phase difference setting for VSYNC and HSYNC Set the phase difference in HSYNC separator sampling clock units The valid range is x 000 to x 3FF HLOCKLV Sync Separator Detection Control Register 1 x 007ED4 HLOCKLVW x 007EF4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H H H H H H H H H LOCK LOCK LOCK LOCK LOCK LOCK LOCK LOCK LOCK LV8 LV7 LV6 LV5 LV4 LV2 LVI LVO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R R R R R R RW RW RW RW RW RW RW RW RW HLOCKLV 8 0 Sync separator detection threshold This va
212. LV 2 0 VBIVSYNC 1 interrupt priority level Sets the priority from 0 to 6 VBIVIE VBIVSYNC 1 interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 66 Panasonic Interrupts Interrupt Control Registers VBIVWICL VBIVSYNC 2 Interrupt Control Register Low x O0FC8A Bit 7 6 4 3 2 1 0 _ MS VBIVW _ _ En VBIVW IR ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R VBIVWICL detects and requests VBIVSYNC 2 interrupts It is an 8 bit access register Use the MOVB instruction to access it VBIVWIR VBIVSYNC 2 interrupt request flag 0 No interrupt requested Interrupt requested VBIVWID VBIVSYNC 2 interrupt detect flag 0 Interrupt undetected Interrupt detected VBIVWICH VBIVSYNC 2 Interrupt Control Register High x O0FC8B Bit 7 6 5 4 3 2 1 0 VBIVW IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W VBIVWICH enables VBIVSYNC 2 interrupts It is an 8 bit access register Use the MOVB instruction to access it The priority level for VBIVSYNC 2 interrupts is written to the VBIVLV 2 0 field of the VBIVICH register VBIVWIE VBIVSYNC 2 interrupt enable flag 0 Disable 1 Enable TM3UDICL Timer 3 Underflow Interrupt Control Register Low x 00FC8C Bit 7 6 5 4 3 2 1 0 TM3UD _ _ TM3UD ID
213. M Correction Control Registers AMCHIHO AMCHIHF ROM Correction Address Match Register n High Bit 7 6 5 4 3 2 1 0 CHAD CHAD CHAD CHAD CHAD CHAD CHAD CHAD 23 22 21 20 19 18 17 16 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W AMCHIHn is an 8 bit access register CHAD 23 16 Correction address bits A23 to A16 A23 MSB AMCHILO AMCHILF ROM Correction Address Match Register n Low Bit 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 CHAD CHAD CHAD CHAD CHAD CHAD CHAD CHAD CHAD CHAD CHAD CHAD CHAD CHAD CHAD CHAD 15 14 13 12 11 10 9 8 Hi 6 5 4 3 2 1 0 Rs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW R W RW RW RW RW RW RW RW RW AMCHILn is a 16 bit access register CHAD 15 0 Correction address bits A15 to AO CHDATO CHDAT15 ROM Correction Data Register Bit 7 6 5 4 3 2 1 0 CHD CHD CHD CHD CHD CHD CHD CHD 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W CHDATn is an 8 bit access register CHD7 Correction data bit D15 or D7 for address n CHD6 Correction data bit D14 or D6 for address n CHD5 Correction data bit D13 or D5 for address n CHD4 Correction data bit D112 or D4 for address n CHD3 Correction data bit D11 or D3 for address n CHD2 Correction data bit D10 or D2 for address CHD1 Correcti
214. Manual 164 Panasonic 5 Display 7 88 VRAM 7 8 1 Operation Table 7 7 VRAM Bit Allocation in Internal RAM Text layer 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 9 CCH8 CCH7 CCH6 CCH5 4 CCH3 2 CCHI CCH0 Character code ID code Character address 1024 characters COL normal mode 1 0 BSHADI BSHADO CSHAD FRAME BLINK BCOL3 BCOL2 BCOLI BCOL0 CCOL3 CCOL2 CCOL1 CCOLO Color control code ID code Box shadow Outline Blink Background color 16 colors Character color 16 colors COL closed caption mode 1 0 CUNDLIITALIC BLINK BCOL3 BCOL2 BCOLI BCOL0 CCOL3 CCOL2 CCOLI CCOLO Color control code ID code Underline Italics Outline Blink Background color 16 colors Character color 16 colors CCB 0 1 v es CCB3 CCB2 CCB0 Repeat character blank code ID code Senn Number of blank char repetitions CHP 1 1 CHSZ1 570 CSHT 9 CHP8 CHP7 CHP6 5 CHP4 CHP3 CHP2 CHPO Character H position control ID code H size Shutter H display start position 1 dot resolution 1024 steps 1 1 CLAST CVSZI CVSZO CINT 9 CVP8 CVP7 CVP6 5 CVP4 CVP3 CVP2
215. OMD register to 1 This loads the value in the Y base register to the binary counter At the same time select the clock source as the TMOIO signal input by writing b 11 to TMOS 1 0 Do not change the clock source once you select it Selecting the TMOMD example x 00FE20 clock source while you set up Bit 7 6 5 4 3 2 1 0 the count operation control will THO EMO mo corrupt the value in the binary EN LD S1 50 Setting 0 1 0 0 0 0 1 1 In the bank and linear address 6 Set TMOLD to 0 and TMOEN to 1 This starts the timer Counting begins at ing versions of the MN102 Series it was necessary to set TMOEN and TMOLD to 0 between steps 5 and 6 to underflow interrupt request is sent to the CPU the start of the next cycle When the binary counter reaches 0 and loads the value x 03 from the base register in preparation for the next count a timer 0 ensure stable operation This is unnecessary in the high speed linear addressing version Interrupt enable TMOBR 00 03 TMOBC 00 03 2 01 Timer 0 underflow i i I 4 f 4 TM0IO Sequence 2 3 5 6 TMOUDICH B TMOMD B TMOMD B TMOBR B Figure 4 10 Event Counter Timing Timer 0 MNI02H75K F75K 85K F85K LSI User
216. PT13 GPT12 11 GPT10 OSD graphics color palette 1 007FDO GPT1F GPT1E GPT1D 1 GPT1B GPT1A GPT19 GPT18 007 0 GPT27 26 GPT25 GPT24 GPT23 GPT22 GPT21 GPT20 OSD graphics color palette 2 007 0 GPT2F GPT2E GPT2D GPT2C GPT2B GPT2A GPT29 GPT28 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 312 Panasonic Register Table 2 Register Map 00 00 to x 00FDFF ieee 9 ied 6 5 4 3 2 110 Descripueh 00FC00 IAGR CPUM Special function registers 00FC10 00FC20 00FC30 00FG40 00FC50 OOFCEO Ce 00FC70 ADMO ADMG ADM ADMI De AD AMO TMOUD TM0UD TMIUD TMIUD TM2UD TM2UD Interrupt controller registers ooFc80 w or ee e e 00FC90 52 00FCAO 00FCBO 00FCCO 00FCDO O0FCEO OOFCFO et resist EXTMD ROMCEN interrupt mode register 00 00 AMC AMCHIL3 AMCHIL2 AMCHIL1 AMC AMCHILO 00FD10 His AMCHIL7 He AMCHIL6 HIME AMCHILS Hd AMCHIL4 ROM correction address match 00 020 AMC AMCHILB
217. Pana Series The One toWatch for Constant Innovation Making the Future Come Alive MICROCOMPUTER MN102H MN102H75K F75K 85K F85K LSI User s Manual Pub No 22385 011E Panasonic PanaXSeries is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations Request for your special attention and precautions in using the technical information 1 Q 3 4 5 semiconductors described in this book export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan The contents of this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party No part of this book may be reprinted or reproduced by any means without written permission from our company This book deals with standard specification Ask for the latest individual Product Standards or Specifications in advance fo
218. Pro aps nat 7 ee Pra aoina woour P14 apie STOP Jee pro Lee Pis Dito wna sa ace Pss apis ew 2 jac P17 lee P20 Pwus Lam Pes puns 19 bee P22 pws P23 fem Pat Turc sari Notes 1 Pins marked with an asterisk are N channel open drain pins 2 Pin 41 is Vpp in the MN102H75K and Vpp in the MNIO2HF75K Figure 1 10 MN102H75K Pin Configuration in Single Chip Mode Table 1 3 Pin Function Continued Pin Name 00 07 10 17 20 27 P30 P37 ports P40 P47 P50 P57 P60 P61 P70 P77 P80 P87 Table 1 3 Pin Function Continued Block Pin Name P00 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P61 only P70 P77 4N102H75K HF75K P80 P87 Note If the circuit uses the same power supply for digital and analog supplies connect the pins in the location closest to the power supply Figure 1 11 Power Supply Wring Y 102 75 MN102H85K Vss AVss PR Note If the circuit uses the same power supply for digital and analog supplies connect the pins in the location closest to the power supply Figure 1 12 Power Supply Wring Panasonic Semiconductor Development Company Panasonic 2 102 75 75 85 85 LSI User Manual The MN102H75K contains an internal PLL circuit To use this circui
219. R W A D conversion end interrupt control register low ANICH x 00FC81 R W A D conversion end interrupt control register high SCTOICL x 00FC82 R W Serial 0 transmission end interrupt control register low SCTOICH x 00FC83 R W Serial 0 transmission end interrupt control register high SCROICL x 00FC84 R W Serial 0 reception end interrupt control register low SCROICH x 00FC85 R W Serial 0 reception end interrupt control register high VBIVICL x 00FC88 R W VBIVSYNC 1 interrupt control register low VBIVICH x 00FC89 R W VBIVSYNC 1 interrupt control register high VBIVWICL x 00FC8A R W VBIVSYNC 2 interrupt control register low VBIVWICH x 00FC8B R W VBIVSYNC 2 interrupt control register high TM3UDICL x 00FC8C R W Timer 3 underflow interrupt control register low TM3UDICH x 0O0FC8D R W Timer 3 underflow interrupt control register high OSDGICL x 00FC90 R W OSD graphics interrupt control register low OSDGICH x 00FC91 R W OSD graphics interrupt control register high OSDCICL x 00FC92 R W OSD text interrupt control register low OSDCICH x 00FC93 R W OSD text interrupt control register high SCT1ICL x 00FC98 R W Serial 1 transmission end interrupt control register low SCT1ICH x 00FC99 R W Serial 1 transmission end interrupt control register high SCR1ICL x 00FC9A R W Serial 1 reception end interrupt control register low SCR1ICH x 00FC9
220. R W Group 10 Group 11 External interrupt 4 00FC58 R W p External interrupt 5 00FC5A R W Timer 4 compare capture B 00FC60 R W Timer 4 compare capture A 00 62 R W Timer 4 underflow interrupt 00 64 R W interrupt 1 00 66 R W Timer 5 compare capture B 00 68 R W m Group 21 Timer 5 compare capture 00FC6A R W Group 22 Timer 5 underflow interrupt 00FC6C R W Group 23 VBI interrupt 2 00FC6E R W Timer 2 underflow interrupt 00FC70 R W P Timer 1 underflow interrupt 00FC72 R W Timer 0 underflow interrupt 00 74 R W Remote signal receive int 00 76 R W Group 28 Address match interrupt 00FC78 R W Group 29 Address 2 match interrupt OOFC7A R W Group 30 Address 1 match interrupt 00FC7C R W Group 31 Address 0 match interrupt OOFC7E R W Group 32 A D conversion end int 00 80 R W Group 33 Serial 0 transmission end 00FC82 R W Group 34 Serial 0 reception end 00FC84 R W Group 35 VBIVSYNC interrupt 1 00FC88 R W VBIVSYNC interrupt 2 00FC8A R W Timer 3 underflow interrupt 00 8 R W Group 40 OSD interrupt graphics OOFC90 R W Group 41 OSD interrupt text 00FC92 R W Group 42 Group 43 Serial 1 transmission end 00 98 R W p Serial 1 reception end 00FC9A R W 12C interrupt O0FC9C R W Figure 2 2 Interrupt Vector Group and Class Assignments Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 38 Panasoni
221. R bit of TMACBICL to 0 From this point on an interrupt request is generated whenever a timer 4 capture B event occurs start of the next cycle To service the interrupts and calculate the signal width 1 Run the interrupt service routine The routine must determine the interrupt group then clear the interrupt request flag Ignore the flags when calculat 2 Calculate the number of cycles the TMAIA signal stays high Save the con ing the signal widthi even wien tents of TM4CA to the data registers then subtract the contents L s of TM4CA from the contents of TM4CB Since TM4LP is set to 0 the dif ference will be the correct value even if TM4CA is greater than TM4CB Timer 4 can input a single phase capture signal You must select up counting Timer 4 does not operate in STOP mode when Bosc is off If you use an external clock it must be synchronized to Bosc TM4CA captures the count on the rising edge of TM4IA and TM4CB captures the count on the falling edge of TM4IA A timer 4 capture B interrupt occurs when TM4CB captures the count and the contents of TM4CA and TM4CB are read during the interrupt service routine In the example timing chart shown in figure 4 36 x 000A x 0007 x 0003 or 3 cycles The calculation is correct even when is the larger value The flags are ignored so for instance x 0003 x FFFE x 0005
222. Reset 0 0 0 0 0 0 R W R R R R W R R R R TM3UDICL detects and requests timer 3 underflow interrupts It is an 8 bit access register Use the MOVB instruction to access it TM3UDIR Timer 3 underflow interrupt request flag 0 No interrupt requested Interrupt requested TM3UDID Timer underflow interrupt detect flag 0 Interrupt undetected Interrupt detected 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 67 Panasonic Interrupts Interrupt Control Registers TM3UDICH Timer 3 Underflow Interrupt Control Register High x 00FC8D Bit 7 6 5 4 3 2 1 0 TM3UD IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W TM3UDICH enables timer 3 underflow interrupts It is an 8 bit access reg ister Use the MOVB instruction to access it The priority level for timer 3 underflow interrupts is written to the 2 0 field of the VBIVICH register TM3UDIE Timer 3 underflow interrupt enable flag 0 Disable 1 Enable OSDGICL OSD Graphics Interrupt Control Register Low x 00FC90 Bit 7 6 5 4 3 2 1 0 _ _ OSDG _ _ _ OSDG ID Reset 0 0 0 0 0 0 0 R W R R R R W R R R R OSDGICL detects and requests OSD graphics interrupts It is an 8 bit access register Use the MOVB instruction to access it OSDGIR OSD graphics interrupt request flag 0 No interrupt requested 1 Interrupt requested
223. SPO Reset 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 R W R R RW RW RW RW RW RW R R R W RW RW RW RW RW The sync separator uses the value set in this register to separate the com posite sync signal from the composite video signal Video signal HSYNC Setting for sync separator level Composite sync processing Figure 9 14 Sync Separator Level Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 244 Panasonic Closed Caption Decoder Closed Caption Decoder Registers Composite signal from ADC Compare PSP MUX BSP CLMODE Figure 9 15 BSP and PSP Multiplexing BSP 5 0 Sync separator level for pedestal clamping Sync separator level sync tip level 2 BSP 5 0 The valid range is x 00 to PSP 5 0 Sync separator level for sync tip clamping Valid range x 00 to x 3F CLAMP Clamping Control Register x 007ECC CLAMPW x 007EEC Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VBI CL CL PCLV6 PCLV5 PCLVA PCLV3 PCLV2 PCLVI PCLVO SAFE ON MODE MODB 1 0 Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R RW RW RW RW RW RW RW R R R W R R R W R W Use this register to set the clamping mode sync tip or pedestal clamping PCLV 6 0 Pedestal clamping level setting Set the reference level for pedestal clamping in this field The v
224. Setup time for a repeated start condition tSU STA 4 7 Data hold time tHD DAT 300 ns Data setup time sU DAT 250 SDA and SCL rise time tR 1000 SDA and SCL fall time tp 300 Stop condition setup time tsu sto 4 0 us MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 299 Panasonic Bus Controller PC Interface Setup Examples 13 6 I2C Interface Setup Examples 13 6 1 Setting Up a Transition from Master Transmitter to Mas ter Receiver This example demonstrates how to set up a data transfer when changing from master transmitter to master receiver Figure 13 7 shows an example waveform 13 6 1 1Pre configuring set up the I O port Set port control register 0 PCNTO x 00FF90 to x 0100 enabling the SDAO and SCLO pins and set the port 6 output mode register P6MD x O0OFFFC to x 0003 selecting the SDAO and SCLO functions To enable 2 interrupts Set the interrupt control register pair I2COICH and I2COICL x 00FC9C to x 0100 To set up the C registers 1 Set the I2CCLK register 007 46 to x 0041 selecting a clock frequency of 80 kHz 2 Set the I2CDTRM register x 007E40 to x OSFD This sets STA to 1 STP to 0 and ACK to 0 Bits 7 to 1 of the transmission data setting x FD indi cate the address b 1111110 of the slave device from which the microcon troller will request the data and bit O indicates the
225. T 0 GTC x 012 97 0 4C13 GTC Graphic GCB x 3 GPRT 0 GTC x 013 97DE 4214 GTC Graphic GCB x 0 GPRT 1 GTC 014 97DC 0815 GTC Blank tile GCB x 2 0 GTC x 015 97DA 4216 GTC Graphic GCB x 0 GPRT 1 GTC x 016 97D8 D810 GHP GHSZ x 3 GSHT 0 GHP x 10 97D6 C858 GVP GLAST 0 GVSZ x 1 GINT 0 GVP x 58 3 97BE 4181 GTC Graphic GCB x 0 GPRT 0 GTC x 181 97BC 4382 GTC Graphic GCB x 0 GPRT 1 GTC x 182 97BA C044 GHP GHSZ 0 GSHT 0 GHP x 44 97B8 E020 GVP GLAST 1 GVSZ x0 GINT 0 GVP x 20 Notes 1 Always specify GHP and GVP in that order at the end of each line 2 Set GINT to 1 in the setting to generate an OSD graphics interrupt Set GLAST to 1 in the GVP setting for the last line in the graphics display Also set the GVP value to a smaller value than the position of the current line In the example in table 7 5 x 20 is smaller than v 58 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 161 Panasonic 5 Display Display Setup Examples E 4 A N HP x 22 Y maps ETE gt 1 1 Line 1 VSZ 3 GTC x000 GTC x 055 Blank GTC
226. TM1BR to TMIBC and simultaneously generates timer 1 underflow interrupt After each timer 1 underflow the ADC converts each of the ADIN 2 0 inputs a single time MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 149 Panasonic Analog to Digital Converter ADC Control Registers Timer 1 underflow Conversion Channel 0 Channel 1 Channel 2 Channel 0 Channel 1 Channel 2 Interrupts Figure 6 11 Timing of Hardware Controlled Intermittent Three Channel A D Conversion 6 6 ADC Control Registers The ADC contains thirteen registers one control register ANCTR and twelve data buffers each associated with one of the ADIN pins ANCTR controls the operating conditions and the read only data buffers hold the results of the A D conversions Table 6 2 ADC Control Registers Register Address R W Description ANCTR 00 00 R W ADC control register ANOBUF x 00FF08 R ADINO conversion data buffer AN1BUF x 00FF0A R ADIN1 conversion data buffer AN2BUF 00 R ADIN2 conversion data buffer AN3BUF x 00FF0E R conversion data buffer AN4BUF x OOFF10 R ADIN4 conversion data buffer ANSBUF x OO0FF12 R ADINS conversion data buffer AN6BUF x OOFF14 R ADING conversion data buffer AN7BUF x OOFF16 R ADIN7 conversion data buffer AN8BUF x OO0FF18 R A
227. Table2 1Comparison of MN102H75K and MN102L35G Interrupt Features 4 vectors per group Separated by interrupt service routine MN102H75K 1 vector per group Group number gener ated for each interrupt interrupt level settings 4 vectors per level 4 vectors per level The MN102H75K has six external interrupt pins Set the interrupt con dition positive edge negative edge either edge or active low in the EXTMD register interrupt groups IAGR group numbers The most important factor in real time control is an MCU S speed in servicing interrupts The MN102H75K 85K has an extremely fast interrupt response time due to its ability to abort instructions such as multiply or divide that require multiple clock cycles The MN102H75K 85K re executes an aborted instruction after returning from the interrupt service routine This section describes the interrupt system in the MN102H75K 85K The MN102H75K 85K contains 36 interrupt group controllers Each controls a single interrupt group Because each group contains only one interrupt vector the MN102H75K 85K can handle interrupts much quicker than previously possible Each interrupt group belongs to one of twelve classes which defines its interrupt priority level With the exception of reset interrupts all interrupts from timers other peripheral circuits and external pins must be registered in an interrupt group controller Once they are registered interrupt requests are sent to the CP
228. The program then looks up and branches to the entry address of the interrupt service routine for the interrupt that occurred Interrupt preprocessing Push registers branch to entry address etc Main program 080008 Hardware processing Push PC PSW Interrupt 6 machine cycles 7 machine cycles Figure 1 7 Interrupt Servicing Sequence JMP etc Interrupt service routine Header resets interrupt vector 102 75 75 85 85 LSI User Manual 25 Panasonic Panasonic Semiconductor Development Company General Description General Specifications 1 4 General Specifications Table 1 1 General Specifications Parameter Specification Structure Internal multiplier 16 bit x 16 bit 32 bit and saturate calculator Load store architecture Eight registers Four 24 bit data registers Four 24 bit address registers Other 24 bit program counter 16 bit processor status word 16 bit multiply divide register Instruction set 41 instructions 6 addressing modes 9 9 9 9 9 1 byte basic instruction length Code assignment 1 byte basic 0 to 6 bytes extension Performance 12 MHz internal operating frequency with a 4 MHz external oscilla tor Instruction execution clock cycles Minimum 1 clock cycle 83 3 ns for register to register operations Minimum 1 clock cycle 83 3 ns for load store operations Minimum 2 clo
229. Tx interrupt SBI RXBUSY Rx interrupt RXA 1 when Rx data in Data read Figure 5 7 UART Transmission Timing ST b0 b1 b2 b3 b4 b5 b6 b7 SP SP Figure 5 8 UART Reception Timing Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 130 Panasonic Serial Interfaces Serial Interface Setup Examples You must use 8 bit timer to set the transfer clock See sec tion 5 6 3 Setting Up the Serial Interface Clock on page 135 for an example setup 5 6 Serial Interface Setup Examples 5 6 1 Setting Up UART Transmission Using Serial Interface 0 This example illustrates serial transmission in the UART mode with the fol lowing settings Bosc 24MHz Baud rate 9600 bps transfer clock set up with timer 0 8 bit character length Two stop bits 9 9 Odd parity When transmission end interrupt occurs the next data byte is loaded Po Rom Ram pi P2 Interrupts Bus Controller P3 P4 Timers 01 Serial I Fs P5 SBOO P6 Timers 2 3 ADC Figure 5 9 Block Diagram of UART Transmission Using Serial Interface 0 Data transmission starts when the CPU writes data to the SCOTRB register The transmission start is synchronized to timer 0 underfl
230. U in accordance with the interrupt mask level 0 to 6 set in the interrupt group controller Groups 1 to 3 are dedicated to system inter rupts Table 2 1 compares the interrupt parameters of the MN102H75K 85K to those of the MN102L35G the comparable MCU in the previous generation of the 16 bit series Table2 1Comparison of MN102H75K 85K and MN102L35G Interrupt Features 4 vectors per group Separated by interrupt service routine MN102H75K 85K 1 vector per group Group number gener ated for each interrupt interrupt level settings 4 vectors per level 4 vectors per level The MN102H75K 85K has six external interrupt pins Set the interrupt condition positive edge negative edge either edge or active low in the EXTMD register interrupt groups IAGR group numbers The 102 75 provides two ways to reduce power consumption controlling CPU operating and standby modes to cut overall consumption and shutting down unused functions by stopping the system clock supplied to them 3 1 CPU Modes 3 1 1 Description The MN102H75K has two CPU operating modes NORMAL and SLOW and two CPU standby modes HALT and STOP Effective use of these modes can signifi cantly reduce power consumption Figure 3 1 shows the CPU states in the different modes The MN102H75K 85K provides two ways to reduce power consumption con trolling CPU operating and standby modes to cut overall consumption and shutting down unused functions by stopping
231. UDICL x 00FC70 R W Timer 2 underflow interrupt control register low TM2UDICH x 00FC71 R W Timer 2 underflow interrupt control register high TM1UDICL x 00FC72 R W Timer 1 underflow interrupt control register low TM1UDICH x 00FC73 R W Timer 1 underflow interrupt control register high TMOUDICL x 00FC74 R W Timer 0 underflow interrupt control register low TMOUDICH x 00FC75 R W Timer 0 underflow interrupt control register high RMCICL x 00FC76 R W Remote signal receive interrupt control register low RMCICH x 00FC77 R W Remote signal receive interrupt control register high Panasonic Semiconductor Development Company 46 Panasonic 102 75 75 85 85 LSI User Manual Interrupts Interrupt Control Registers Table 2 4 Interrupt Control Registers Register Address R W Description ADM3ICL x 00FC78 R W Address 3 match interrupt control register low ADM3ICH x 00FC79 R W Address 3 match interrupt control register high ADM2ICL x 00FC7A R W Address 2 match interrupt control register low ADM2ICH x 00FC7B R W Address 2 match interrupt control register high ADM1ICL x 00FC7C R W Address 1 match interrupt control register low ADM1ICH x 00FC7D R W Address 1 match interrupt control register high ADM0ICL x 00FC7E R W Address 0 match interrupt control register low ADMOICH x 00FC7F R W Address 0 match interrupt control register high ANICL x 00FC80
232. When Bosc is 24 MBz you must set the reference clock to lt 8 conversion rate 4 us or higher VDD ADINO ANOBUF ADINI AN1BUF 2 gt AN2BUF ADINS M AN3BUF ADIN4 8 bit AN4BUF successive AN5BUF approximation AN6BUF ADING and ADIN X hold ADC AN7BUF ADIN8 ANSBUF ADIN9 AN9BUF ADIN0 gt AN10BUF ADIN11 AN11BUF Vss Figure 6 1 ADC Architecture 6 2 Features Table 6 1 ADC Functions and Features Function Feature Description Sample and hold Embedded Conversion time 4 us per channel when Bosc 24 MHz Clock sources Programmable to Bosc divided by 8 or 16 Operating modes 46 operating modes four types 1 Single conversion of one input channel 0 1 2 3 4 5 6 7 8 9 10 or 11 Single conversion of multiple inputs channels 0 n where n 1 11 Continuous conversion of one input channel 0 1 2 3 4 5 6 7 8 9 10 0r 11 Continuous conversion of multiple inputs channels 0 where n 1 11 Conversion start Timer 1 underflow or register setting Interrupts An interrupt is generated each time a single or continuous conversion sequence ends Note 1 Channels correspond to the ADIN pin having the same number For instance channel 3 or ch3 corresponds to ADIN3
233. a wipe out effect to create a smooth appearing and disappearing effect The MN102H75K contains a remote signal receiver that processes sig nals in two formats Household Electrical Appliance Manufacturers Association HEAMA format and 5 6 bit format This chapter pro vides an overview of each block in the circuit and describes the opera tion of the receiver The MN102H75K 85K contains a remote signal receiver that processes signals in two formats Household Electrical Appliance Manufacturers Association HEAMA format and 5 6 bit format This chapter pro vides an overview of each block in the circuit and describes the opera tion of the receiver The MN102H75K contains two identical closed caption decoder cir cuits CCDO and CCD1 The MN102H75K 85K contains two identical closed caption decoder circuits CCDO and CCD1 The clamping circuit internal to the MN102H75K provides three current sources high medium and low The clamping circuit internal to the MN102H75K 85K provides three current sources high medium and low The MN102H75K contains seven 8 bit pulse width modulators PWMs with a minimum pulse width of 16 fsysc and an output waveform cycle of 2 ffevsck With a 4 MHz oscillator 16 fsyscik 1 33 us 8 us for SLOW mode and 2126 341 3 us 2 ms for SLOW mode The MN102H75K 85K contains seven 8 bit pulse width modulators PWMs with a minimum pulse width of 16 fsyscrk and an output wavefor
234. access registers 0 Pullup resistor off 1 Pullup resistor on Note that by default the P7P8CNT bit of the PCNT2 register forces the pullup resistors on for ports 7 and 8 P7PUP and P8PUP are only valid when P7P8CNT is 1 POOUT P5OUT Ports 0 5 Output Control Registers x O0FFCO x O0FFC5 Ports 7 8 Output Control Registers x O0FFC8 x 00FFCA Bit 7 6 5 4 3 2 1 0 PnOUT7 PnOUT6 PnOUTS5 PnOUTA PnOUT3 PnOUT2 PnOUTI PhOUTO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W P6OUT Port 6 Output Control Register x 00FFC6 Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 P6OUT 1 PGOUTO Reset 0 0 0 0 0 0 0 0 R W R R R R R R R W R W The PnOUT registers contain the port output data The bit number corre sponds to the associated pin number For instance POOUT7 applies to the P07 pin These are 8 bit access registers MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 277 Panasonic Ports I O Port Control Registers When using P57 as a port set SIFSELO PCNTO x FF90 bp12 to O POIN P5IN Ports 0 5 Input Registers x 00FFDO x 00FFD5 P7IN P8IN Ports 7 8 Input Registers x 00FFD8 x 00FFDA Bit Z 6 5 4 3 2 1 0 PnIN7 PnIN6 PnIN5 PnIN4 PnIN3 PnIN2 PnINI PnINO Reset Pin P
235. al 240 Panasonic Closed Caption Decoder Closed Caption Decoder Registers CRI1E CRI Capture Stop Timing Control Register 1 x 007E12 CRHEW x 007E32 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRIIE CRIIE CRUE CRIIE CRHE CRIIE CRIIE 10 9 8 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 R R R R RW RW RW RW RW RW R W RW RW RW RW CRI1E 10 0 Stop position for CRI capture 1 Valid range x 000 to x 7FF CRI2S CRI Capture Start Timing Control Register 2 x 007E14 CRI2SW x 007E34 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRDS CRDS CRDS CRI2S CRI2S CRI2S CRDS CRDS CRDS CRI2S CRI2S 10 9 8 7 6 5 4 3 2 1 0 Rest 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 RW R R R R RW RW RW RW RW RW RW RW RW RW RW CRI2S 10 0 Start position for CRI capture 2 Valid range x 000 to x 7FF CRI2E CRI Capture Stop Timing Control Register 2 x 007E16 CRI2EW x 007E36 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRDE 2 2 CRDE CRDE CRDE CRDE CRDE CRDE CRDE CRDE 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 t 1 1 1 1 1 1 1 1 1 1 R R RW RW RW RW RW RW RW RW RW CRI2E 10 0 Stop position for CRI capture 2 Set thi
236. alid range is x 00 to x 7F VBION VBI setting 0 VBIoff 1 VBlon SAFE Clamping current source select This bit is the capacity switch for 5 and 6 in figure 9 5 on page 229 0 High current source 5 and 6 capacity high 1 Medium current source 5 and 6 capacity low CLMODE 1 0 Clamping mode setting 00 Automatic switching depends on the cycle state 01 Sync tip clamping only 10 Pedestal clamping only 11 Clamping off MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 245 Panasonic Closed Caption Decoder Closed Caption Decoder Registers HSEP1 HSYNC Separator Control Register 1 x 007ECE HSEP1W x 007EEE Bit 15 14 13 12 11 10 9 8 7 6 5 4 9 2 1 0 us us us us us ns us Hs HS Hs HS FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ FREQ 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 R R R RW RW RW RW RW RW RW RW RW RW HSFREQ 10 0 Correction HSYNC frequency Set the correction HSYNC cycle in this field in HSYNC separator sam pling clock units The valid range is x 000 to x 7FF and the recom mended setting is x O10C HSEP2 HSYNC Separator Control Register 2 x 007EDO HSEP2E x 007EF0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H H H H H H H H H H CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE CLOSE C
237. ample sics ae eg upas pe ERR ERR RR ERE eR ER 185 7 26 Italicizing and Underlining 1 186 7 27 Graphic Tile Size Combinations 2 1 02 187 7 28 Character Size Combinations 2 32 uu pes Te ee e dp ane te ha wee DECRE 188 7 29 of Horizontal Display 189 7 30 DMA and Interrupt Timing for the 5 192 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 13 Panasonic List of Figures 7 31 Shuttered Area Setup Examples 195 7 32 Shutter Movement Setup 4 197 7 33 Text Layer Shuttering Setup 199 7 34 Shutter Blanking Setup 2 1 200 7 35 Line Shuttering Setup 2 2122 200 7 36 Field Detection Circuit Block 201 7 37 Field Detection Timing UR exe bum weber Bahan 201 8 1 IR Remote Signal Receiver Block Diagram
238. anasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 138 Panasonic Serial Interfaces Serial Interface Setup Examples You do not need to enable reception if it is already enabled by the initial settings You can also omit any settings already in place from the transmission sequence The parity bits serve as the ACK signal To output an ACK 1 sig nal select a fixed parity of 1 To output an ACK 0 signal select a fixed parity of 0 Select a parity of none if there is no ACK signal 5 6 5 Setting Up Pc Reception Using Serial Interface 0 This example illustrates the microcontroller as a master receiver in the PC mode using the SBO0 and SBTO pins When initiating master receiver mode your program must always first transmit a byte of data The master reception occurs during the interrupt service routine that runs after the data is transmitted For an example setup of master transmission see section 5 6 4 Setting Up C Transmission Using Serial Interface 0 on page 137 To set up the interface 1 During the interrupt service routine for the serial transmission end enable reception by setting the SCOREN bit of SCOCTR to 1 2 Select ACK output of 1 To set up data reception 1 Write a dummy data bit x to the serial port 0 transmit receive buffer This sets the SBOO signal high and initiates the master receiver mode 2 During the service routine for the ser
239. any 23 Panasonic General Description MN102H Series Description Address space The memory in the MN102H series is configured as linear address space The instruction and data areas are not separated so the basic segments are internal ROM internal RAM and special function registers Figure 1 5 shows the address space for the MN102H75K 85K The internal ROM contains the instructions and the font data for the on screen display OSD in any location The internal RAM contains the MCU data and the VRAM for the OSD in any location X007 ED0 Special Function x 007FFF Registers x 008000 Internal RAM Data 8 KB OSD Text VRAM Graphics VRAM x 009FFF Y x 00FC00 Special Function Registers x 00FFFF Program start address x 080000 099090 i Interrupt handler start address x 080000 Internal ROM Program 256 KB OSD Text fonts Graphic tiles x OBFFFF Figure 1 5 Address Space Note In writing do not use MOVB instruction to access Special Function Registers x OOFCOO x OOFFFF access by word In reading access by byte is possible Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 24 Panasonic General Description MN102H Series Description Interrupt controller An interrupt controller external to the core controls all nonmaskable and maskable interrupts except reset There are a maximum of sixteen interrupt cl
240. aphics Palette 1 Colors 0 15 Registers x 007FC0 x 007FDE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn GPTIn 2 YM0 B3 2 Bl BO G3 G2 GI GO R3 R2 RI RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W w w w w w w w w w w w w w w w w These registers contain one of two sets of colors used in the graphics layer When digital output is selected GPTInYMO is output as YM GPTInB0 as B GPTInGO as and GPTInRO as When the YS color palette is selected GPTInYMG is output as YS GPT1nYN 3 0 YM color code GPT1nB 3 0 Blue color code GPT1nG 3 0 Green color code GPT1nR 3 0 Red color code Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 214 Panasonic 5 Display OSD Registers GPT20 GPT2F Graphics Palette 2 Colors 0 15 Registers x 007FE0 x 007FFE Bit 15 14 13 12 11 10 9 8 7 6 9 4 3 2 1 0 GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n 2 2 Bl BO G3 G2 GI GO R3 R2 RI RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 These registers contain one of two sets of colors used in the graphics layer When digital output is se
241. aphics Vertical Size Settings GIVSZ 1 0 1 Dot Size Setting Interlaced Displays Progressive Displays 00 1 H scan line Reserved 01 2 H scan lines 1 H scan line 10 4 H scan lines 2 H scan lines 11 6 H scan lines 3 H scan lines Bit Reset R W GIVP 9 0 Graphics initial vertical position CIHP Text Initial Horizontal Position Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 x 007F1A 1 0 HSZ1 570 SHT CIHP9 CIHP8 CIHP7 CIHP6 5 4 CIHP3 CIHP2 CIHPI CIHPO 0 R 0 R 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW CIHSZ 1 0 Text initial horizontal size 00 1 dot 1 VCLK period 01 1 dot 2 VCLK periods 10 1 dot 3 periods 11 1 dot 4 periods CISHT Graphics initial shutter control 0 Shutter control on 1 Shutter control off CIHP 9 0 Graphics initial horizontal position CIVP Text Initial Vertical Position Register x 007F1C Bit 15 14 13 10 9 8 7 6 5 4 3 2 1 0 c CIVP7 CIVP6 CIVP5 4 CIVP3 CIVP2 CIVPO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R RW RW R RW RW RW RW RW
242. are calculation or software setting DATAG Data window for capturing the caption data CRI2G CRI window 2 for detecting the sampling cycle position CRI1G CRI window 1 for calculating the maximum and minimum values ACQG ACQ window for setting the H interval for data detection SLDSAMP Caption data sampling pulse FCPIN Start position for start bit detection software setting FCP Start position for start bit detection hardware calculation SLD Sliced data from the CVBS input signal Panasonic Semiconductor Development Company 248 Panasonic 102 75 75 85 85 LSI User Manual Pulse Width Modulator Description 10 Pulse Width Modulator 10 1 Description The MN102H75K 85K contains seven 8 bit pulse width modulators PWMs with a minimum pulse width of 16 fsyscrk and an output waveform cycle of For information on the SLOW 2 With a 4 MHz oscillator 16 fsyscy k 1 33 us 8 us for SLOW mode see section 3 1 CPU mode and 22 341 3 us 2 ms for SLOW mode Modes The PWM ports are 3 3 volt open drain outputs To enable the PWM ports either turn the pullup registers on using the pullup control registers for the asso ciated ports P15 P17 and P20 P23 see table 10 1 or connect external pullup resistors to these ports Table 10 1 Register Settings for Internal PWM Pullup PWM Block Register Bit No Setting P1PUP M 0
243. asses class 0 to 15 Each class can have up to four interrupt factors and any of seven priority levels Maskable Interrupt Receive Nonmaskable Interrupt Reset Receive Reset ry Interrupt Enable m Interrupt Controller a Nonmaskable interrupts Groups 0 3 4 External NMI pin input Interrupt Masking Nonmaskable Interrupt Controllers ke Watchdog timer 1 Nonmaskable Interrupt i Undefined instruction 6 5 4 3 2 1 0 Control Registers NMICR T nterrupt occurred WDICR fs UNICR but no vector exists EIICR 4 ra Group 4 4 lt Maskable Interrupt Controllers m Maskable Interrupt ai Control Registers xx ICR Maskable interrupts Max 240 vectors 4 External pin interrupts TET Group 63 Peripheral interupts ini Maskable Interrupt Controllers Maskable Interrupt Pen Control Registers xx ICR Note Interrupt control hardware configuration varies between products Figure 1 6 Interrupt Controller Configuration The CPU checks the processor status word to determine whether or not to accept an interrupt request If it accepts the request automatic hardware servicing begins and the contents of the program counter and other necessary registers are pushed to the stack
244. ata with No Leader When BCEDGS is 1 the counter resets at the second remote signal edge after each trailer detection By ignoring the leader this mode allows the microcon troller to receive 8 bit data that contains a leader See figure 8 4 8 bit data Trailer Ignored 8 bit data Remote signal input Edge detection 8 bit data 8 bit data reception detection 4 Trailer detection A A Leader detection reception A 5 X 6 7 0 Kiko counter 4 Counter reset Figure 8 4 Reception of 8 Bit Data with Leader MNI02H75K F75K 85K F85K LSI User Manual 219 Panasonic Panasonic Semiconductor Development Company Remote Signal Receiver IR Remote Signal Receiver Operation 8 3 4 Identifying the Data Format The microcontroller determines the logic levels of the data by testing the interval between remote signal edges Table 8 1 shows the intervals that the microcon troller interprets as 0 and 1 for both HEAMA and 5 6 bit formats Table 8 2 shows the conditions for identifying long and short data Table 8 1 Logic Level Conditions for Data Formats Logic Level Conditions Operating Mode Data 0 Data 1 HEAMA format lt 6 Ts cycles gt 6 Ts cycles 5 6 bit format lt 12 Ts cycles gt 12 Ts cycles Table 8 2 Long and Short Data Ide
245. atches the count value in the 10 bit register then clears the counter HCCNTO and HCCNT1 provide six interval settings 1024 us fixed interval obtained by dividing the system clock 12 MHz 2048 us fixed interval obtained by dividing the system clock 12 MHz 4098 us fixed interval obtained by dividing the system clock 12 MHz 8096 us fixed interval obtained by dividing the system clock 12 MHz Interval from active edge to active edge input of VIO pin Interval from active edge to active edge input of VSYNC pin If your application uses one of the fixed clocks based on divided PWM output 1024 2048 4098 or 8096 us you must also set up the PWM circuit See section 10 Pulse Width Modulator on page 249 When the count overflows is greater than x 3FF the counter stops counting and stores the value x 3FF in the 10 bit register At any time the CPU can obtain the count value stored in the latch by reading HCDO x 007EB4 or x 007EB6 register To enable or disable the H counter function set the HCNTOFF bit of the PCNTO register X OOFF90 see page 286 Disabling this circuit when it is unused can reduce power consumption Because the H counter uses the system clock it does not operate in STOP mode 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 309 Panasonic H Counter H Counter Control Registers 14 4 H Counter Control Regist
246. ating tiles allows you to use more than 18 or 28 tiles per line 7 For the OSD block to operate correctly always set bit 7of the PCNT2 register x 00FF92 to 0 Cursor layer Notes 1 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 153 Panasonic 5 Display Y29019 GSO 1 2 e1nBrJ4 Block Diagram 992 play 10 4q sejeoipur C 2 TOES 8499 3 170095 8100 ETID CED 077005 eldsIp XIN Josino pue solude6 1 181sI6 1 YUS EED Cann Jejo1uoo pue 15 1xo L aN GHB 215 3 ejep Jepooep CONSE 3a soiudej6 spray 49014 VIG erep appe 8 WVd pue u04 A sjaysibal aso seinquine dA dH 800 102 aso SA E lt 2 co N WA s n ed 20109 49 04 U00 Jeunus CY Jejunoo uonisod jeuozuoH 10d 3490 9 1 24 6 4901
247. bit during transmission or reception 0 Output stop sequence upon 1 to 0 transition 1 Output start sequence upon 0 to 1 transition SCnPTL Serial port n protocol select 0 UART 1 Synchronous serial or C SCnOD Serial port n bit order This bit must be set to 0 during 7 bit transmission 0 LSB first 1 MSB first Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 140 Panasonic Serial Interfaces Serial Interface Control Registers SCnICM Serial port n 12 mode select 0 PC mode off 1 PC mode on SCnLN Serial port n character length 0 7 bit 8 bit SCnPTY 2 0 Serial port n parity bit select 000 None 001 Reserved 010 Reserved 011 Reserved 100 0 output low 101 1 output high 110 Even 1s are even 111 Odd 1s are odd SCnSB Serial port n stop bit select UART mode only 0 1 bit 2 bit SCnS 1 0 Serial port n clock source select The 00 and 10 settings are reserved in UART and modes 00 SBTn pin 01 Timer 0 underflow x 1 8 10 Timer 1 underflow x 1 2 11 Timer 1 underflow x 1 8 SCOTRB SC1TRB Serial Port n Transmit Receive Buffer x 00FD82 x 00FD88 Bit 7 6 5 4 3 2 1 0 SCn SCn SCn SCn SCn SCn SCn SCn TRB7 TRB6 TRB5 4 TRB3 TRB2 TRBO Reset R W R W R W R W R W R W R W R W R W Data transmission begins when the CPU writes data to SCnTRB The CPU retrieves the data b
248. bitration function Internal peripheral functions MN102H series devices contain a wide range of internal periph eral devices such as timers serial interfaces ADCs and DACs MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 29 Panasonic General Description Pin Descriptions 1 6 Pin Descriptions 1 6 1 102 85 Pin Description N Z P00 RMIN IRQ0 1 64 vss P01 SDA 2 63 gt 5 2 P02 SCL 3 62 OSC1 ADIN0 4 61 VDD 04 ADIN 5 60 lt P61 SCLO P05 ADIN2 6 59 4 gt P60 SDAO P06 ADIN3 7 58 lt P57 SBTO P07 ADIN4 8 57 lt P56 SBIO SBDO P10 ADIN5 IRQ 9 56 lt P55 SBOO P11 6 IRQ2 0 55 lt 54 IRQ5 VSYNC P12 ADIN7 IRQ3 q 64 PinSDIP 4 ps3 RST P13 ADIN8 WDOUT 2 View 53 lt 52 IRQ4 VIO P14 ADIN9 STOP 3 52 4 TEST P15 ADIN10 PWMO 4 51 gt P51 YS P16 ADIN11 PWM 5 50 lt P50 SYSCLK P17 PWM2 6 49 4 gt 47 5 P20 PWM3 7 48 4 gt P46 OSDXI P21 PWM4 8 47 4 gt P45 OSDXO P22 PWM5 9 46 lt P44 TMBIC HI P23 PWM6 20 45 lt P43 5 HIO P24 TM4IC SBT1 21 44 gt 42 P25 TM4IOB SBI1 SBD1 22 43 lt P41 1 26 TM4IOA SBO1 23 42 4 P27 TM0IO 24 41 gt PDO VDD VPP 25 40 lt P40 DAYMOUT P30 CLH 26 39 gt gt P37 DABOUT VREFHS 27
249. ble flag 0 Disable 1 Enable TM4CAICL Timer 4 Compare Capture A Interrupt Control Register Low x 00FC62 Bit 7 6 5 4 3 2 1 0 ix TM CA _ _ TM4CA IR ID Reset 0 0 0 0 0 0 0 0 RW R R R R W R R R R TM4CAICL detects and requests timer 4 compare capture interrupts It is an 8 bit access register Use the MOVB instruction to access it TM4CAIR Timer 4 compare capture A interrupt request flag 0 No interrupt requested 1 Interrupt requested TM4CAID Timer 4 compare capture A interrupt detect flag 0 Interrupt undetected 1 Interrupt detected TM4CAICH Timer 4 Compare Capture A Interrupt Control Register High x O0FC63 Bit 7 6 5 4 3 2 1 0 IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W TM4CAICH enables timer 4 compare capture interrupts It is an 8 bit access register Use the MOVB instruction to access it The priority level for timer 4 compare capture interrupts is written to the TMACBLV 2 0 field of the TM4CBICH register Timer 4 compare capture A interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 54 Interrupts Interrupt Control Registers TM4UDICL Timer 4 Underflow Interrupt Control Register Low x 00FC64 Bit 7 6 4 3 2 1 0 TM4UD TM4UD
250. bus controller converts the data in the IDCCDTRM register to the PC protocol Transfer modes changes A write to the I2CDTRM register indicates the transfer mode master transmitter receiver or slave transmitter receiver for a new transfer To minimize software control the hardware generates an interrupt each time a transfer ends During interrupt servicing the SCL line stays low then clears to high on a write to I2CDTRM When the microcontroller is a slave transmitter and the transfer ends SCL goes high on a read to the I2CDREC register after an 1 negative acknowledge interrupt Multimaster support The hardware performs bus arbitration for a multimaster system When it loses an arbitration the hardware immediately stops the data transfer and generates an interrupt Address decoding The bus controller decodes the microcontroller s address set in the I2CMYAD register when the microcontroller is a slave device It also decodes the general code address 0 Forced bus reset Through software control by a write to the I2ZCBRST register the bus con troller can force the SCL line to reset to low when a bus error occurs This resets the entire 2 bus controller circuit leaving the microcontroller in slave receiver mode It does not change the contents of the 2 and I2CCLK registers Clock frequency adjustment The I2CCLK register sets the serial clock frequency allowing synchronization with
251. c Interrupts Description P 2 rogram Address 80008 Interrupt Handler preprocessing les Max 6 cycles st 5 The interrupt request is Interrupt service deleted in the header routine Included in the cycle count shown to the left Handler postprocessing Registers popped Figure 2 3 Interrupt Servicing Time Table 2 2 Handler Preprocessing Sequence Assembler Bytes Cycles Push registers add 8 A3 2 1 mov 0 2 2 DO 4 A3 3 3 Interrupt ACK mov FCOE DO 3 1 Generate header address mov BASE AO 3 1 for interrupt service routine mov D0 A0 A0 2 2 Branch jsr A0 2 5 Total 17 15 Table 2 3 Handler Postprocessing Sequence Assembler Bytes Cycles Pop registers mov A3 A0 2 2 movx 4 A3 DO 3 3 add 8 A3 2 1 Total 7 6 MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 39 Panasonic Interrupts Interrupt Setup Examples 2 2 Interrupt Setup Examples 2 2 1 Setting Up an External Pin Interrupt In this example an interrupt occurs on a falling edge signal from the IRQ0 P00 external interrupt pin and the interrupt priority level is 5 On reset the external edge setting in the EXTMD register is low b 00 active low interrupt and the IQOIR bit of the IQOICL register is 0
252. c Interrupts Interrupt Control Registers Bit XnICL System Interrupt 7 6 5 4 3 2 1 0 IR ID IR Interrupt request flag 0 interrupt requested 1 Interrupt requested ID Interrupt detect flag 0 Interrupt undetected 1 Interrupt detected The following is an example program setting an interrupt group s priority level LV field and enabling the interrupt group IE in the interrupt control register XnICH Note that interrupts must be disabled during this routine Example 2 1 Setting the Interrupt Priority Level Oxf7ff psw Clear the IE bit of the PSW nop inserted to ensure that IE clears nop completely so XnICH is accessible mov 0 XnICH Write to LV IE mov XnICH d0 Synchronize with the store buffer or 0x0800 psw Set the IE bit of the PSW r The program does not need to clear the IE bit of the PSW to disable interrupts during interrupt servicing since the interrupt service routine has already cleared it You can replace the NOP instructions in the example above with any instruction except for those that modify the PSW IE bit or the LV or IE bits of an XnICH register Inserting any of these instructions would cause interrupt error to occur The example includes two NOP instructions to ensure that the minimum number of cycles required for a write to IE have passed However you can also insert more than two NOPs
253. c Interrupts Interrupt Control Registers SCROICH Serial 0 Reception End Interrupt Control Register High x 00FC85 Bit 7 6 5 4 3 2 1 0 SCRO IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W SCROICH enables serial 0 reception end interrupts It is an 8 bit access register Use the MOVB instruction to access it The priority level for serial 0 reception end interrupts is written to the 2 0 field of the ANICH register SCROIE Serial 0 reception end interrupt enable flag 0 Disable 1 Enable VBIVICL VBIVSYNC 1 Interrupt Control Register Low x 00FC88 Bit 7 6 5 4 3 2 1 0 VBIVIR VBIVID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R VBIVICL detects and requests VBIVSYNC 1 interrupts It is an 8 bit access register Use the MOVB instruction to access it VBIVIR VBIVSYNC 1 interrupt request flag 0 No interrupt requested Interrupt requested VBIVID VBIVSYNC 1 interrupt detect flag 0 Interrupt undetected Interrupt detected VBIVICH VBIVSYNC 1 Interrupt Control Register High x 00FC89 Bit 7 6 5 4 3 2 1 0 _ VBIV vBIV _ VBIV LV2 LVO IE Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R R R R W VBIVICH sets the priority level for and enables VBIVSYNC 1 inter rupts It is an 8 bit access register Use the MOVB instruction to access it VBIV
254. cess register Use the MOVB instruction to access it SCTOIR Serial 0 transmission end interrupt request flag 0 No interrupt requested Interrupt requested SCTOID Serial 0 transmission end interrupt detect flag 0 Interrupt undetected Interrupt detected SCTOICH Serial 0 Transmission End Interrupt Control Register High x 00FC83 Bit 7 6 5 4 3 2 1 0 SCTO IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W SCTOICH enables serial 0 transmission end interrupts It is an 8 bit access reg ister Use the MOVB instruction to access it The priority level for serial 0 transmission end interrupts is written to the 2 0 field of the ANICH register SCTOIE Serial 0 transmission end interrupt enable flag 0 Disable 1 Enable SCROICL Serial 0 Reception End Interrupt Control Register Low x 00FC84 Bit 7 6 5 4 3 2 1 0 SCRO SCRO m IR m ID Reset 0 0 0 0 0 0 R W R R R R W R R R R SCROICL detects and requests serial 0 reception end interrupts It is an 8 bit access register Use the MOVB instruction to access it SCTOIR Serial 0 reception end interrupt request flag 0 No interrupt requested 1 Interrupt requested SCTOID Serial 0 reception end interrupt detect flag 0 Interrupt undetected 1 Interrupt detected 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 65 Panasoni
255. ch Register ROM Address Data Register High Order Low Order Address 0 AMCHIH0 x 00FD02 AMCHILO x 00FD00 CHDATO x 00FD40 Address 1 AMCHIH1 x 00FD06 AMCHIL1 x 00FD04 CHDAT1 x 00FD44 Address 2 AMCHIH2 x 00FD0A AMCHIL2 x 00FD08 CHDAT2 x 00FD48 Address 3 AMCHIH3 x 00FD0E AMCHIL3 x 00FD0C CHDAT3 x 00FD4C Address 4 AMCHIH4 x 00FD12 AMCHIL4 x 00FD10 CHDAT4 x 00FD50 Address 5 AMCHIH5 x 00FD16 AMCHIL5 x 00FD14 CHDAT5 x 00FD54 Address 6 AMCHIH6 x 00FD1A AMCHIL6 x 00FD18 CHDAT6 x 00FD58 Address 7 AMCHIH7 x 00FD1E AMCHIL7 x 00FD1C CHDAT7 x 00FD5C Address 8 AMCHIH8 x 00FD22 AMCHIL8 x 00FD20 CHDAT8 x 00FD60 Address 9 AMCHIH9 x 00FD26 AMCHIL9 x 00FD24 CHDAT9 x 00FD64 Address 10 AMCHIHA x 00FD2A AMCHILA x 00FD28 CHDAT10 x 00FD68 Address 11 AMCHIHB x 00FD2E AMCHILB x 00FD2C CHDAT11 x O0FD6C Address 12 AMCHIHC x 00FD32 AMCHILC x 00FD30 CHDAT12 x 00FD70 Address 13 AMCHIHD x 00FD36 AMCHILD x 00FD34 CHDAT13 x 00FD74 Address 14 AMCHIHE x 00FD3A AMCHILE x 00FD38 CHDAT14 x 00FD78 Address 15 AMCHIHF x 00FD3E AMCHILF x 00FD3C CHDAT15 x 00FD7C Note All registers reset to 0 ROMCEN ROM Correction Enable Register x 00FCFO Bit 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 ROMC ROMC ROMC ROMC ROMC ROMC ROMC ROMC ROMC ROMC ROMC ROMC ROMC ROMC ROMC ROMC EN15 4 ENI2 EN10 EN9 EN7 EN6 ENS EN3 EN2 ENO
256. ck cycles 167 ns for branch operations Pipeline 3 stage fetch decode execute Address space Linear address space Shared instruction data space Interrupts 6 external 30 internal 7 priority level settings Low power modes STOP HALT SLOW Oscillation fre 4 MHz 48 MHz with internal PLL quency Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 26 Panasonic General Description General Specifications Table 1 1 General Specifications Parameter Specification Timer counters Four 8 bit timers Cascading function forming 16 or 32 bit timers Timer output Selectable clock source internal or external Serial interface clock generation 9 9 9 Start timing generation for analog to digital converter Two 16 bit timers Compare capture registers Selectable clock source internal or external PWM and one shot pulse output Two phase encoder input 4x or 1x formats 16 bit watchdog timer ROM correction 16 bytes 8 bit x 16 SYSCLK output SYSCLK or SYSCLK 2 4 732 42 Hz Serial interfaces Two UART synchronous serial I2C master only interfaces One interface multimaster 2 channel with 1 internal circuit Analog to digital converter 8 bit with 12 channels Automatic scanning IR remote signal receiver 9 9 Automatic 5 6 bit detecti
257. ck source ANCK 1 0 b 10 Set the conversion start busy bit to 0 Set ANTC to 1 enabling conversion start at timer 1 underflow Set the ANICH 3 0 field to the first channel channel 0 and set the ANNCH 3 0 to the last channel channel 2 ANCTR example x 00FDAO Bit 15 14 13 12 11 10 9 8 6 3 4 3 2 1 0 c AN AN AN AN NCH3 NCH2 NCHO ICH3 ICH2 1CHO EN TC CKO MDI Setting 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 1 To set up the conversion cycle 1 Set the divide by ratio for timer 1 To divide Bosc 4 by 256 write 255 x FP to the timer 1 base register TM1BR The valid range for TMIBR is 1 to 255 TM1BR example x O0FE11 Bit 7 6 5 4 3 2 1 0 TMI TMI TMI TMI TMI TMI TMI TMI BR7 BR6 BR5 BR4 BR3 BR2 BRI BRO Setting 1 1 1 1 1 1 1 1 2 Set the TMILD bit of the TMIMD register to 1 and the TMIEN bit to 0 This loads the value in the base register to the binary counter TM1MD example x 00FE21 Bit 7 6 5 4 3 2 1 0 TMI TMI TMI TMI EN LD 51 50 Setting 0 1 0 0 0 0 1 0 3 Set TMILD to 0 and TMIEN to 1 This starts the timer Counting begins at the start of the next cycle When the binary counter TM1BC reaches 0 the microcontroller reloads the value in the base register
258. corrected data to the CPU Data bus ROM address Correction I address Correction match 8 registers 9 Correction Correction address data Match ROM correction detection MUX selector enable circuit registers Figure 12 3 ROM Correction Block Diagram 12 3 Programming Considerations At reset the ROM correction address match and data registers contain all 0s Since a reset also disables ROM correction in ROMCEN the ROM will still operate normally Only read from or write to the address match registers while ROM correction is disabled in ROMCEN Otherwise an error may occur in the match detection circuit Note that the address match and data registers only allow full register access 8 bit or 16 bit depending on the register You cannot write to individual bits MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 289 Panasonic ROM Correction ROM Correction Control Registers 12 4 ROM Correction Control Registers Table 12 1 shows the organization of the address match and data registers for ROM correction Write a ROM address to be corrected to an AMCHIHn and AMCHILn register pair and write the corrected data to the associated CHDATn register Enable ROM correction for the associated address in the ROMCEN register Table 12 1 ROM Correction Address Match and Data Registers Address Mat
259. cts to DATA I O s LabSite PROM writer When the microcontroller connects to the adaptor socket it auto matically enters PROM writer mode The adaptor socket ties the microcontroller pin states to PROM writer mode and programming occurs without any reference to the microcontroller pin states eee MN102HF85K Adaptor socket for MN102HF85K Third party PROM writer MN102HF75K Adaptor socket for MN102HF75K Figure B 2 PROM Writer Hardware Setup VPP 3 M 42 A17 NCE 2 41 NWE 015 3 40 MODE 014 4 39 15 013 5 38 14 012 6 37 A13 011 7 36 A12 010 8 35 11 09 9 34 10 VO8 10 33 9 ERASE 11 32 VSS VO7 12 31 A8 VO6 13 30 A7 VO5 14 29 A6 104 15 28 5 103 16 27 A4 102 17 26 101 18 25 2 00 19 24 A1 20 23 0 16 21 22 VDD Figure 3 Pin Configuration for Socket Adaptor MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 317 Panasonic MN102HF75K Flash EEPROM Version Using the PROM Writer Mode Table B 2 PROM Writer Hardware Device Hardware Part MN102HF75KBF MN102HF85KDP Package external view Installed 84 64 SDIP Installed sO Ordering information Part no FLS84F18 102HF57 OEM Matsushita Electric Indus trial Co Ltd Set this switch to the right o fa Ordering information Part no FLS64SD 102HF51 O
260. cursor to the SHP 9 0 field x 007F12 Valid range SHP gt x 0C Graphics Write the horizontal position of the first line in the display to the GIHP 9 0 field x 007F16 Write the position of the second and all following lines in the GHP 9 0 field of the graphics display RAM data for the preceding line Valid ranges lt GHP lt HP and x OC lt GIHP lt HP nax Text Write the horizontal position of the first line in the display to the CIHP 9 0 field x 007F1A Write the position of the second and all following lines in the CHP 9 0 field of the text display RAM data for the preceding line Valid ranges x OC lt CHP lt HP nax and x OC lt CIHP lt HP max To set HP max equations write max Thsyne Thw 0 8 Ls T dot T Nehar x 16 x 1024 Nou X 16 x Hy Thsync 18 the HSYNC cycle Thy is the HSYNC pulse width Ncnar is the number of characters in the line including repeated characters and blank spaces Ty is the dot clock cycle and H is the horizontal size The HP nax limit ensures that there is at least 0 8 us between the end of a line and the leading edge of HS YNC heyne gt Thw 10 8 js gt HSYNC LI RGB YM YS Figure 7 29 HP max of Horizontal Display Position About the horizontal start position on the screen The horizontal position or HP set
261. d graphics layers so that they will be displayed on both shuttered and non shuttered regions disable shuttering on the next line Set the GSHT bit bit 10 of GHP in the RAM data and or the CSHT bit bit 10 of CHP in the RAM data to 1 disable shuttering on the first line Set the GISHT bit of the GIHP register x 007F16 and or the CISHT bit of the CIHP register x 007F14 to 1 Figure 7 35 shows a setup example for the text layer Line 1 CISHT 1 C ABCDEFG m Shuttering effect Line 2 5 0 5 EFG Line 3 CSHT 0 Line 4 CSHT 1 gt ABCDEFG Television screen Figure 7 35 Line Shuttering Setup Example Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 200 Panasonic 5 Display Field Detection Circuit 7 14 Field Detection Circuit 7 14 1 Block Diagram HSYNC Database System Divide y R Upper 4 bits 4 x pog by 3 7 bit counter x 007F0E EVOD FREG 13 10 VSYNC Do leading p T FF LOADN1 4 edge detection D FF x 4 N1 l Y x 007F0E EVOD FREG 23 20 D FF x 4 2 4 4 N2CNT N1CNT Vertical display Y Y controller EOMON p Comparator EOSEL FRMON Figure
262. dth register A CRIFB 007 x 007E2E CRI frequency width register CRI1S x 007E10 x 007E30 R W CRI capture start timing control register 1 CRHE 007 12 x 007E32 R W CRI capture stop timing control register 1 CRI2S 007 14 x 007E34 R W CRI capture start timing control register 2 CRI2E x 007E16 x 007E36 R W CRI capture stop timing control register 2 DATAS 007 18 x 007E38 R W Data capture start timing control register DATAE 007 x 007E3A R W Data capture stop timing control register STAP 007 1 x007E3C R W Sampling start position register software setting FCPNUM x007E1E 007 R Sampling start position register hardware calculation NFSEL x 007ECO x 007EEO R W Noise filter select register FQSEL x 007EC2 x 007EE2 R W Frequency select register SCMING x 007EC4 x 007EE4 R W Minimum sync level detection interval set register BPPST x 007EC6 007 6 R W Backporch position register SYNCMIN x 007EC8 x007EE8 R Sync and pedestal level register SPLV x 007ECA 007 R W Sync separator level set register CLAMP x 007ECC x 007EEC R W Clamping control register HSEP1 x 007ECE x 007EEE R W HSYNC separator control register 1 HSEP2 x 007EDO x 007EFO R W HSYNC separator control register 2 FIELD x 007ED2 x 007EF2 R W Field detection control registe
263. e remote signal RMCOFF PONTO x 00FF90 bit 0 signal receiver receiver function control 2 1 IR remote signal receiver block enabled pit 0 C block enabled 2 2 function control s Se 0 2 1 1 block off 0 PLL block enabled PWM PWM function control 0 1 1 PLL block off 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 75 Panasonic Low Power Modes CPU Control Register 3 3 CPU Control Register CPUM CPU Mode Control Register x 00FCOO Bit 15 14 13 12 1 10 9 8 7 6 3 4 3 2 1 0 NW OSC DEN ID STOP HALT 1 Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R R R R R R R R R R R RW RW RW This register controls the invoking of all of the CPU modes NWDEN Watchdog timer reset 0 Enable watchdog timer 1 Disable and clear watchdog timer Setting the watchdog timer to 1 then setting it to 0 clears and restarts the watchdog timer OSCID Oscillator select System clock monitor 0 Fast 1 Slow STOP STOP mode request CPU operating state control See table 3 2 HALT HALT mode request CPU operating state control See table 3 2 OSC 1 0 Oscillator control See table 3 2 Table 3 2 CPU Mode Bit Settings Clock System STOP HALT OSC1 OSCO CPU Mode to CPU Clock PLL CPU 0 0 0 0 NORMAL 24MHz
264. e To specify a particular interrupt vector as the signal for waking up enable that vector in the interrupt registers For more information on controlling interrupts see section 2 Interrupts on page 37 When exiting STOP and HALT modes The MCU exits STOP and HALT modes on reset or interrupt For information on exiting on interrupt see Figure 3 1 CPU State Changes on page 72 When the MCU exits on reset it always exits to SLOW mode Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 74 Panasonic Low Power Modes Turning Individual Functions On and Off 3 2 You cannot set the PLL function control bit during NORMAL mode Turning Individual Functions On and Off The MN102H75K 85K allows you to turn each peripheral function on or off through writing to the registers You can significantly reduce power consumption by turning off unused functions Table 3 1 shows the register bits controlling on You must set it from the SLOW mode disabled Turning on the function enables register reads and writes and off for each function block The ADC used for the OSD and CCD functions is turned off on reset Write a 1 to the function to enable it when necessary You cannot read from or write to the registers associated with a function that is See the sections on each of these peripheral functions for more information To turn off the OSD block to save pow
265. e MN102H75K 1 bus interface Figure 13 6 and table 13 5 provide the timing definitions and specifica tions for the for the MN102H75K 85K bus interface Note circled areas are signals output from the MN102H75K Note The circled areas are signals output from the MN102H75K 85K Note circled areas are signals output from the MN102H75K Note The circled areas are signals output from the MN102H75K 85K Panasonic Semiconductor Development Company Panasonic 4 102 75 75 85 85 LSI User Manual The MN102H75K contains two H counter circuits that can be used to count the HSYNC signal Each H counter consists of a 10 bit counter and 10 bit register The MN102H75K 85K contains two H counter circuits that can be used to count the HSYNC signal Each H counter consists of a 10 bit counter and 10 bit register Table 14 1 H Counter Pins Description Alternative Functions Count source P43 TM5IOB Count source P44 TMSIC Count reset pin P52 IRQ4 Count reset pin P54 IRQ5 Table 14 1 H Counter Pins Description Alternative Functions Count source P43 TM5IOB Count source P44 TMSIC Count reset pin P52 IRQ4 Count reset 54 5 The MN102HE75K is electrically programmable 256 kilobyte flash ROM versions of the MN102H75K It is programmed in one of two modes
266. e a 0 to ANEN Start Stop requests State Channel n Channel n Channel n Channel n Channel n lconversion conversion conversion conversion conversion ANEN Figure 6 6 Single Channel Continuous Conversion Timing 6 4 5 Multiple Channel Continuous Conversion Timing When ANMD 1 0 611 the ADC converts multiple consecutive ADIN input signals continuously An interrupt occurs each time the conversion sequence ends Load Os to the ANICH 3 0 field of the ADC control register ANCTR then load the number of the final channel in the sequence to the ANNCH 3 0 field The sequence always begins with channel 0 When the software starts the conversion write a 0 to the ANTC bit disabling conversion start at timer 1 underflow then write a 1 to ANEN If ANTC 1 ANEN goes high upon a timer 1 underflow ANEN remains high during the con version To end the A D conversion write a 0 to ANEN Note that the ANICH 3 0 field holds the number of the channel being converted It clears to 0 when the sequence ends Start Stop requests State Channel 0 Channel 1 Channel 2 Channel 0 Channel 1 Channel 2 Channel 0 conversion conversion conversion conversion conversion conversion conversion ANEN Figure 6 7 Multiple Channel Continuous Conversion Timing Panasonic Semiconductor Development C
267. e core hardware MN10200 Series Linear Addressing High Speed Version Instruction Manual Describes the instruction set MN10200 Series Linear Addressing High Speed Version C Compiler User Manual Usage Guide Describes the installation commands and options for the C compiler MN10200 Series Linear Addressing High Speed Version C Compiler User Manual Language Description Describes the syntax for the C compiler MN10200 Series Linear Addressing High Speed Version C Compiler User Manual Library Reference Describes the standard libraries for the C compiler MN10200 Series Linear Addressing High Speed Version Cross Assembler User Manual Describes the assembler syntax and notation MN10200 Series Linear Addressing Version C Source Code Debugger User Manual Describes the use of the C source code debugger m MN10200 Series Linear Addressing Version PanaX Series Installation Manual Describes the installation of the C compiler cross assembler and C source code debugger and the procedures for using the in circuit emulator Questions and Comments e welcome your questions comments and suggestions Please contact the semicon uctor design center closest to you See the last page of this manual for a list of addresses and telephone numbers You can also find contact and product information pn the World Wide Web at http www psdc com MNTUZH Series LST User Manual Describes the
268. e encoder as the clock source TM5MD example x 00FE90 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 NLD UDI UDO TGE ONE MDI LP ASEL S2 81 50 Setting 0 0 0 0 0 0 0 0 0 0 0 1 lor 0 1 0 0 2 Write the intended looping value for timer 5 to TM5CA valid settings x 0001 to For TM5BC to count from x 0000 to x 1FFF for instance write x IFFF to TM5CA TM5CA example x 00FE94 Bit 15 14 13 12 11 10 9 8 Z 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 15 14 CAI3 CAI2 10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO Setting 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 Write the timer 5 interrupt value valid settings 0000 to the value in 5 to TM5CB Whenever the binary counter reaches the value in TMSCB in either up or down counting a compare capture B interrupt occurs at the beginning of the next cycle example x 00FE98 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 TM5 15 CB14 CBI3
269. eceiver Operation 6 3 5 Generating Interrupts The IR remote signal receiver has four interrupt vectors leader detection trailer detection 8 bit data reception detection and pin edge detection This section describes the operation for each of them 6 3 5 1 Leader Detection An interrupt occurs when the circuit detects a data leader It detects leaders by testing the interval between remote signal edges Table 8 3 shows the conditions Table 8 3 Leader Detection Conditions Format Edge Interval HEAMA data leader n 4 Tg lt interval lt n 4 Tg 5 6 bit data leader 28Ts x interval lt 36Ts Note 1 n the leader value set in LD 3 0 of the RMLD register 6 3 5 2 Trailer Detection An interrupt occurs when the 6 bit counter overflows 6 3 5 3 6 Bit Data Reception Detection An interrupt occurs when the microcontroller loads 8 bit received data to the reception data transfer register RMTR 6 3 5 4 Pin Edge Detection An interrupt occurs when the remote signal input pin RMIN is asserted The POLSEL bit of RMIR sets the polarity of RMIN RMIN input positive edge triggered POLSEL 0 RMIN input EE negative edge triggered POLSEL 1 Edge detection output 1 1 1 1 1 5 1 fsYSCLK P Note l fsyscik 1 12 MHz 0 083 Us Figure 8 6 Pin Edge Detection The detection output for all four interrupt vectors is an active high pulse asserted at intervals of 1 fgysc_
270. ed 0 Normal position 1 Add 1 to V position of even fields EONL and BFLD Closed caption scrolling control Use when required for smoother scrolling 00 Normal display 01 Fix to characters in odd fields during scrolling 10 Fix to characters in even fields during scrolling 11 Normal display UNDF Underline blinking control 0 Don t blink 1 Blink CAPM Closed caption mode setting 0 Normal display mode 1 Closed caption mode VSHTO Vertical Shutter 0 Register x 007F20 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VSON VSMP VSTO VST0 VST0 VST0 VST0 VST0 VST0 VST0 VST0 VST0 m EE 0 VSEO 0 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R RW RW RW RW RW RW RW RW RW RW RW RW VSONO Vertical shutter 0 on off 0 Off 1 On VSPO Vertical shutter 0 shuttering direction 0 Shutter below 1 Shutter above VSMP0 Vertical shutter 0 movement direction 0 Top to bottom 1 Bottom to top VSMO Vertical shutter 0 movement control 0 Don t move 1 Move VSTO 9 0 Vertical shutter O position Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 210 Panasonic 5 Display OSD Registers VSHT1 Vertical Shutter 1 Register x 007F22 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VSON VSMP VSTI VSTI VSTI VSTI VST1 VSTI
271. ed Intermittent Three Channel A D Conversion This example illustrates multiple channel conversion controlled by the hardware The ADIN2 ADIN1 and ADINO pins input analog voltage signals 0 0 V 3 3 V and the ADC converts the voltages to 8 bit digital values It writes the results to the registers periodically each time timer 1 underflows Slider 1 Slider 2 Slider 3 10 10 10 5 5 5 U T MN102H75t 0 ch1 ch2 A D converter data registers MN102 Jundertow CPU core Timer 1 Figure 6 10 Multiple Channel A D Conversion Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 148 Panasonic Analog to Digital Converter ADC Setup Examples Do not change the clock source once you have selected it Selecting the clock source while you set up the count operation control will corrupt the value in the binary counter To set up the input port Set the PODIR 5 3 bits of the port 0 I O control register PODIR to 0 This sets the ADIN2 P05 ADIN1 P04 and ADINO pins P11 to general purpose input To set up the ADC Set the operating conditions in the ADC control register ANCTR Select multiple channel single conversion mode ANMD 1 0 b 01 and 8 as the clo
272. ed instruction interrupt detect flag 0 Interrupt undetected Interrupt detected EIICR Interrupt error Interrupt Control Register x 00FC46 Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R does not exist in the hardware but if the CPU finds no matching interrupt vector for an interrupt that occurs it writes a C to IAGR to indi cate that it detected an abnormality EIICR is an 8 bit access register IQOICL External Interrupt 0 Interrupt Control Register Low x 00FC48 Bit 7 6 5 4 3 2 1 0 IQR 100 Reset 0 0 0 0 0 0 R W R R R R W R R R R IQOICL requests and verifies interrupt requests for external interrupt 0 It is an 8 bit access register Use the MOVB instruction to access it IQOIR External interrupt 0 interrupt request flag 0 No interrupt requested Interrupt requested IQOID External interrupt 0 interrupt detect flag 0 Interrupt undetected Interrupt detected MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 49 Panasonic Interrupts Interrupt Control Registers IQ0ICH External Interrupt 0 Interrupt Control Register High x 00FC49 Bit 7 6 4 3 2 1 0 IQOLV1 00 kes IQOIE Reset 0 0 0 0 0 0 0 0 R W R R W R W R R R R W IQOICH sets the priority level for and enables
273. el for external interrupt 5 is written to the IQ4LV 2 0 field of the IQ4ICH register External interrupt 5 interrupt enable flag 0 Disable 1 Enable TM4CBICL Timer 4 Compare Capture B Interrupt Control Register Low x 00FC60 Bit 7 6 5 4 3 2 1 0 TM4CB m IR ID Reset 0 0 0 0 0 0 R W R R R R W R R R R TM4CBICL detects and requests timer 4 compare capture B interrupts It is 8 bit access register Use the MOVB instruction to access it Timer 4 compare capture B interrupt request flag 0 No interrupt requested Interrupt requested TMA4CBID Timer 4 compare capture B interrupt detect flag 0 Interrupt undetected Interrupt detected 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 53 Panasonic Interrupts Interrupt Control Registers TM4CBICH Timer 4 Compare Capture B Interrupt Control Register High x O0FC61 Bit 7 6 5 4 3 2 1 0 TM4CB TM4CB TM4CB LV2 LVO E m IE Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R R R R W TMACBICH sets the priority level for and enables timer 4 compare capture B interrupts It is an 8 bit access register Use the MOVB instruction to access it TM4CBLV 2 0 Timer 4 compare capture B interrupt priority level Sets the priority from 0 to 6 TMACBIE Timer 4 compare capture B interrupt ena
274. em clock supply to the OSD The OSDPOFF bit enables or disables the system clock supply to the OSD block When the OSD is unused setting this bit to 0 stops the clock supply to the OSD reducing power dissipation Setting OSDPOFF to 0 not only disables the OSD display it disables reads from and writes to the OSD registers To operate the OSD set this bit to 1 then set up the OSD registers Using OSDREGE to control read write access to the OSD registers The OSDREGE bit enables or disables read write operations to the OSD reg isters Once you have set the OSD registers you can write a 0 to this bit to disable furthers reads and writes to them reducing power dissipation This bit resets to 0 Note that when OSDPOFF is 0 you cannot read or write to the OSD registers even if OSDREGE is 1 Table 7 3 shows the combinations of OSDPOFF and OSDREGE Note also that when OSDREGE is 0 the OSD display runs but the shuttering motion does not work If your application requires shutter movement you must enable OSDREGE Table 7 3 OSDPOFF and OSDREGE Settings OSDPOFF OSDREGE OSD Register R W Power Dissipation 0 Don t care Off Disabled Less 1 0 On Disabled 1 1 On Enabled Greater MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 155 Panasonic 5 Display OSD Operation See section 7 11 Selecting the OSD Dot Clock on page 186 for informat
275. emiconductor Development Company 243 Panasonic Closed Caption Decoder Closed Caption Decoder Registers Use this register to specify the position for capturing the pedestal level value used during pedestal clamping Specify a number of ADC clocks after the leading edge of HSYNC The valid range is 000 to x 1FF and the recommended setting is x 003C Video signal HSYNC _ Set this interval in BPPST Pedestal level for BPLV register Figure 9 13 Backporch Position Setting SYNCMIN Sync and Pedestal Level Register x 007EC8 SYNCMINW x 007EE8 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BPLV6 BPLV5 BPLVA BPLV3 BPLV2 BPLVI BPLVO 1 E EPA une n paa MA Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R BPLV 6 0 Pedestal level This register stores the pedestal level captured from the position specified in BPPST SYNOMIN 6 0 Minimum sync level This field stores the minimum level the sync tip level detected during the interval set in the SCMING register For sync tip clamping you should control clamping so as to make this value 16 dec SPLV Sync Separator Level Set Register x 007ECA SPLVW x 007EEA Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 5 BSP4 BSP3 BSP2 BSPO 5 5 PSP4 PSP3 PSP2 PSP1 P
276. er 1 Write a 0 to OSD 0501 bit10 2 Wait for the next VSYNC input 3 Write a0to OSDPOFF PCNTO bit 7 turning the clock off If you turn the clock off before the VSYNC input power usage may not drop or the microcontroller may halt Table 3 1 Peripheral Function On Off Switches Block Name Description Bit Name Address Operation Reset Value PONTO x 00FF90 bi 0 OSD block off OSD block control PONTO 00 bit 0 7 1 05 block enabled i 0 OSD function off OSD OSD function control OSD 0 10 1 OSD function on DRE 2 x 00FF92 bi 0 OSD register R W off OSD register R W control ps e X 00FF925 Dit g 0 E 0 1 OSD register R W enabled bi 0 ADC for CCD1 off ADC control for CCD1 apcron PONTO x00FF90 bit 0 5 1 ADC for CCD1 enabled 0 ADC for CCD0 off controforCCDO apcoon PONTO 00 90 bit 0 CCD 4 1 ADC for CCDO enabled bi 0 CCD1 block off CCD1 function control 0 1 1 CCD1 block enabled j 0 CCD0 block off CCD0 function control PONTO x 00FF90 bit 0 0 1 CCD0 block enabled 0 PLL block enabled PLL PLL function control PLLPOFF PONTO Dit 0 6 1 PLL block off 3 bi 0 H counter block enabled H counter H counter function control HCNTOFF ENO bit 0 3 1 H counter block off 0 IR remote signal receiver i block off n remot
277. er TMSCAIE Timer 5 compare capture A interrupt enable flag 0 Disable 1 Enable TM5UDICL Timer 5 Underflow Interrupt Control Register Low x 00FC6C Bit 7 6 5 4 3 2 1 0 E TMSUD _ UN 22 TMSUD IR ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R TMSUDICL detects and requests timer 5 underflow interrupts It is an 8 bit access register Use the MOVB instruction to access it TMBUDIR Timer 5 underflow interrupt request flag 0 No interrupt requested Interrupt requested TM5UDID Timer 5 underflow interrupt detect flag 0 Interrupt undetected 1 Interrupt detected 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 57 Panasonic Interrupts Interrupt Control Registers TM5UDICH Timer 5 Underflow Interrupt Control Register High x 00FC6D Bit 7 6 5 4 3 2 1 0 TMSUD IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W TMSUDICH enables timer 5 underflow interrupts It is an 8 bit access reg ister Use the MOVB instruction to access it The priority level for timer 5 underflow interrupts is written to the TMSCBLV 2 0 field of the TMSCBICH register TM5UDIE Timer 5 underflow interrupt enable flag 0 Disable 1 Enable VBIWICL VBI 2 Interrupt Control Register Low x 00FC6E Bit 7 6 5 4 3 2 1 0 _ _ VBIW _ _ VBIW IR ID Reset 0 0 0 0 0 0 0 0 R W R
278. er 9 1 Description The MN102H75K 85K contains two identical closed caption decoder circuits CCD0 and CCD1 The decoders extract encoded captions from composite video signals Figure 9 1 provides a block diagram of the decoders and section 9 3 Functional Description page 228 describes the circuit s main blocks the analog to digital converter clamping circuit sync separator circuit data slicer controller and sampling circuit Note that this section describes CCDO but all descriptions apply to CCD1 Table 9 1 provides the pin names for each decoder Table 9 1 Pins Used for CCDO and CCD1 Closed Caption Decoder Pin Name CCDO CVBSO VREFHS CLHO CLLO CCD1 CVBS1 VREFLS CLHO CLLO 9 2 Block Diagram Controller CRI Data extraction frequency Quse Slicing Data extractor circuit sampling circuit Slice level detector Max min detector HSYNC separator 724 VSYNC separator RAM Low pass filter Clamping P controller CPU Figure 9 1 Closed Caption Decoder Block Diagram MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 227 Panasonic Closed Caption Decoder Functional Description constants shown in figures 9 2 to 9 4 are recommended values only Operation at these values is not guaranteed 9 3 Functional Description 9 3 1 Analog to Digital Converter The analog to digital converter ADC co
279. er blank code CCB and a color control code COL or character code CC must follow it To indicate the last line of a display make the CHP and CVP values for the last line smaller than those in the currently displayed line In addition write a to the last line flag of the text layer CLAST Two text lines but no more can overlap on the screen The lower line takes priority appearing to lie on top of the higher line If the horizontal sync signal is asserted while the microcontroller is access ing CHP and that line and the next line may not display properly For details see section 7 10 4 Setting Up the OSD Display Position on page 189 Graphics layer 1 Place each line s horizontal and vertical position data GHP in that order at the end of the preceding line Do not place GHP and GVP at the start of a line To indicate the last line of a display make the GHP and GVP values for the last line smaller than those in the currently displayed line In addition write a 1 to the last line flag of the graphics layer GLAST Two graphic lines but no more can overlap on the screen The lower line takes priority appearing to on top of the higher line If the horizontal sync signal is asserted while the microcontroller is access ing GHP and that line and the next line may not display properly For details see section 7 10 4 Setting Up the OSD Display Position on page 1
280. er group 1 vector per group IAGR group numbers Separated by interrupt Group number gener service routine ated for each interrupt Interrupt response time Good Excellent Interrupt level settings 4 vectors per level 4 vectors per level Software compatibility Easily modified The MN102H75K 85K has six external interrupt pins Set the interrupt condition positive edge negative edge either edge or active low in the EXTMD register Internal Interrupt to CPU interrupts EXTMD Interrupt arbitration IRQO 4 Edge level H IRQ1 Edge level IRQ2 Edgellevel IRQ3 Edge level IRQ4 Edge level IRQ5 U Edge level Figure 2 1 Interrupt Controller Block Diagram MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 37 Panasonic Interrupts Description Priority Register Group Interrupt Vector Level Address NMIs z MN102H Watchdog timer 00FC42 R W CPU Core Undefined instruction 00FC44 R W Error interrupt 00 46 R W External interrupt 0 00FC48 R W Levels 0 6 External interrupt 1 00FC4A R W Group 8 External interrupt 2 00 50 R W Group 9 External interrupt 3 00FC52
281. er x 007F26 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 HSMP HSTI HSTI HST1 HST1 HSTI HSTI HSTI HST1 HSTI ze d 1 1 9 8 7 6 5 4 2 2 1 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW R W RW RW RW RW RW RW RW RW HSON Horizontal shutter 1 on off 0 Off 1 On HSP1 Horizontal shutter 1 shuttering direction 0 Shutter to the right 1 Shutter to the left HSMP1 Horizontal shutter 1 movement direction 0 Left to right 1 Rightto left HSM1 Horizontal shutter 1 movement control 0 Don t move 1 Move HST1 9 0 Horizontal shutter 1 position SHTC Shutter Control Register 2 x 007F28 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 SHT COLB SHT SHT SHT GSHT BLK SHT 1 SPO RAD The shuttering function does not BC SHT 5 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 work in the cursor layer SHTBLK Shutter blanking on off 0 Off 1 On COLBSHT Color background shutter control 0 Disable 1 Enable SHTSPT 1 0 Shutter speed control 00 Move every VSYNC 10 Move every 3 VSYNCs 01 Move every 2 VS YNCs 11 Move every 4 VSYNCs SHTRAD Shutter mode control 0 AND mode 1 OR mode GSHT Graphics shutter control 0 Disable 1 Enable BCSHT Text background shutter control 0 Disable 1 Enable CCSHT Text shutter control 0 Disable 1 Enable 0 0
282. ers All registers in H Counter block cannot be written by byte by word only Read by byte is possible HCCNTO Counter Control Register 0 x 007EBO Bit 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 SED RED SELR SELR SELR G0 G0 20 10 00 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDG0 Polarity select for count source signal HIO 0 Active low 1 Active high SEDGO Polarity select for reset signal 0 Active low 1 Active high SELR20 00 Reset signal select 000 1024 us 001 2048 us 010 4096 us 011 8192 us 100 VIO 101 VSYNC All other settings default to 1024 us RW RW RW RW RW HCCNT1 H Counter Control Register 1 x 007EB2 Bit 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 SED RED SELR SELR SELR G1 Gl 21 11 01 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEDG1 Polarity select for count source signal HI1 0 Active low 1 Active high SEDG1 Polarity select for reset signal 0 Active low 1 Active high SELR 21 01 Reset signal select 000 1024 us 001 2048 us 010 4096 us 011 8192 us 100 VIO 101 VSYNC All other settings default to 1024 us R W RW RW RW RW Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 310 Panasonic H Counter Control Registers HCD0 H
283. es If the graphics line you are positioning displays at 2x the base height the number of H scan lines is 16x2232 x20 H scan lines The valid range of settings for GVP is X 3F0 x 20 x 3D0 gt GVP gt x 03 About the vertical start position on the screen The vertical position or VP settings SVP GVP and CVP determine where the upper edge of cursor graphics and text lines start on the screen You can set this value for all of the layers in H scan line units Using the same VP settings for all the layers makes them all start at the same vertical position Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 190 Panasonic 5 Display DMA Interrupt Timing 1 If you use the OSD function the function executes for both the text and graphics layers even if your program does not use one of these layers To prevent error program data for the unused layer to meet the restrictions outlined in section 7 1 Description on page 153 7 11 DMA and Interrupt Timing This section describes how the MN102H75K 85K handles the timing of direct memory access DMA transfers of OSD data and OSD interrupts DMA On both the text and graphics layers the microcontroller reads the line 1 data from the RAM as it scans line 1 onto the display For line 2 and following lines it reads the data as it scans the display start for the preceding line The RAM
284. es can significantly reduce power consumption Figure 3 1 shows the CPU states in the different modes Program Write to CPUM register Clock to CPU 24 MHz NORMAL Mode Systemclook 12 MHz foo p NS THE CPU st d PLL lock to H 2 Lopsnasss kapas KON interrupt System clock 12 MHz CPU and PLL on Program Write to CPUM register STOP Mode Clock to CPU off System clock off H HALT Mode ME Program CPU and PLL off VR System clock Write to CPUM register Program Write to CPUM register Program Program Write to CPUM Write to CPUM register register mu Clock to CPU 4 MHz Interrupt System clock 2 MHz Interrupt CPU on PLL on Clock to CPU 4 MHz System clock 2 MHz CPU and PLL off Figure 3 1 CPU State Changes The CPU mode control register CPUM controls transitions between NORMAL and SLOW modes and from NORMAL and SLOW modes to the standby modes A normal reset or an interrupt wakes the MCU from a standby mode Note that you cannot invoke the STOP mode from NORMAL mode You can only enter STOP from the SLOW mode Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 72 Panasonic Low Power Modes CPU Modes 1 MN102H75K 85K recovers from power up and reset in SLOW mode For normal opera tion the program must switch
285. ess x 0x80008 but the soft branch instruction in the serial writer load program branches to x 0x82018 This address must hold a JMP instruction pointing to the real start address for the interrupt service routine B User program area This area stores the user program B 4 4 2 RAM Address Space Table B 5 RAM Address Space in Serial Programming Mode Address Size Description x 0x8000 3 KB Serial writer work area Ox8BFF x 0x8C00 1 KB Reserved area x OxdFEF Serial writer work area The 3 kilobytes of RAM area starting at address x Ox08000 are used for the serial writer work area The load program downloads programs to this area that it needs to operate the serial writer and program the EEPROM No other memory area be used for this purpose You do not need to know about RAM allo cation to program the EEPROM Reserved area Do not write to this area B 4 5 Microcontroller Clock on the Target Board For the clock supply to the microcontroller on the target board use the existing target board clock The OSC oscillator clock for the microcontroller is 4 MHz Using the internal PLL circuit the microcontroller switches to NORMAL mode and operates with a 12 MHz system clock Table B 6 shows the clock fre quencies for the microcontroller during serial programming Table B 6 Microcontroller Clock Frequencies during Serial Programming Oscillator Clock Frequency I
286. essed by a master Multimaster More than one device capable of controlling the bus can be connected to it More than one master can attempt to control the bus at the same time without corrupting the message The system is not dependent on any single master Arbitration Procedure to ensure that if more than one master simultaneously tries to control the bus only one is allowed to do so and the message is not corrupted The device that loses arbitration becomes the slave of the device that wins Synchronization Procedure to synchronize the clock signals of two or more devices MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 293 Panasonic I C Bus Controller Description Figure 13 2 shows an example of an bus configuration using two microcon trollers Both C bus lines SDA and SCL are bidirectional lines connected to a positive supply voltage via a pullup resistor The open drain output pins of the microcontrollers perform the wired AND function on the bus The software controls when each microcontroller operates as a transmitter or receiver or whether is in master or slave mode Vpp Pullup resistors Data line SDA Clock line SCL p a en rm I I IClock output Clock output Data output Clock input Clock input r Data input Device 1 Device 2 Figure 13 2 Connection of Two Microc
287. etup and only use 16 bit write operations This step stops the TM5BC count and clears both TM5BC and the S R flip flop to 0 To set up timer 5 1 Set the operating mode in the timer 5 mode register TMSMD Disable timer 5 counting and interrupts Set the TMSUD 1 0 bits to b 10 so that the count direction is up when the TMSIA signal is high and down when the TMSIA sig nal is low Select Bosc 4 as the clock source TM5MD example x 00FE90 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 NLD UDI UDO ONE MDI ASEL S2 81 50 Setting 0 0 0 0 1 0 0 0 0 0 0 1 lor 0 0 1 1 2 Write the intended looping value for timer 5 TM5CA valid settings x 0001 to x FFFF For TM5BC to count from x 0000 to x 1FFF for instance write x IFFF to TM5CA TM5CA example x 00FE94 Bit 15 14 13 12 11 10 9 8 Z 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 15 14 CA13 12 10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO Setting 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 Write the timer 5 interrupt value valid settings 00
288. external interrupt It is an 8 bit access register Use the MOVB instruction to access it IQOLV 2 0 External interrupt 0 interrupt priority level Sets the priority from 0 to 6 IQOIE External interrupt O interrupt enable flag 0 Disable 1 Enable IQ1ICL External Interrupt 1 Interrupt Control Register Low x 00FC4A Bit T 6 5 4 3 2 1 0 IQHR gt IQUD Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R IQIICL requests and verifies interrupt requests for external interrupt 1 It is an 8 bit access register Use the MOVB instruction to access it IQ1IR External interrupt 1 interrupt request flag 0 No interrupt requested 1 Interrupt requested IQ1ID External interrupt 1 interrupt detect flag 0 Interrupt undetected 1 Interrupt detected IQ1ICH External Interrupt 1 Interrupt Control Register High x 00FC4B Bit 7 6 5 4 3 2 1 0 IQUE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W enables external interrupt 1 It is an 8 bit access register Use the MOVB instruction to access it The priority level for external interrupt is written to the IQOLV 2 0 field of the IQOICH register IQ1IE External interrupt 1 interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 50 Panasonic Interrupts Interrupt Control Registers
289. g Configuration B Hardware requirements Onboard serial writer model AF200 provisional Add on circuit for target board Flash programming connectors or pins for target board Software requirements Serial writer load program installed in first kilobyte of MN102HF75K 85K EEPROM Programming algorithm for operating the onboard serial writer 102 75 75 85 85 1 81 User Manual Panasonic Semiconductor Development Company 319 Panasonic 102 5 Flash Version Using the Onboard Serial Programming Mode B 4 1 Configuring the System for Onboard Serial Programming Target board AC adaptor power source Vpp Target board UT c E sanee Serial writer AF200 flash microcontroller programmer provisional Figure B 5 Serial Writer Hardware Setup The workstation containing the program data sends the program to the serial writer through an IC card Through serial communication the serial writer programs the flash memory inside the microcontroller on the target board You must supply an external Vpp source to the target board The serial writer supplies the Vpp source You must provide the personal computer that holds the IC card To order the serial writer contact Provisional Yokoga
290. g Interlaced Displays Progressive Displays 00 1 H scan line Reserved 01 2 H scan lines 1H scan line 10 4 H scan lines 2H scan lines 11 6 H scan lines 3 H scan lines SVP 9 0 Cursor vertical position GIHP Graphics Initial Horizontal Position Register x 007F16 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GI GI GI uszi uszo sat GIHP9 GIHP8 GIHP7 GIHP6 GIHP5 GIHP4 GIHP3 GIHP2 GIHP1 GIHPO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R RW RW RW RW RW RW RW RW RW RW RW RW RW GIHSZ 1 0 Graphics initial horizontal size MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 205 Panasonic 5 Display OSD Registers Bit Reset R W 00 1 dot 1 VCLK period 01 1 dot 2 VCLK periods 10 1 dot 3 VCLK periods 11 1 dot 4 periods GISHT Graphics initial shutter control 0 Shutter control on 1 Shutter control off GIHP 9 0 Graphics initial horizontal position GIVP Graphics Initial Vertical Position Register x 007F18 15 14 13 12 11 10 9 8 7 6 5 4 3 1 1 0 GI GI GIVP9 GIVP8 GIVP7 GIVP6 5 GIVP4 GIVP3 GIVP2 GIVP1 GIVPO VSZ1 VSZ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R W R W R R W RW RW RW RW RW RW RW RW RW GIVSZ 1 0 Graphics initial vertical size Table 7 17 Gr
291. gister x 007E42 to determine the PC bus controller status 2 Since the communication will end when the microcontroller receives the next data byte set the I2CDTRM register x 007E40 to x 0100 This sets STA to 0 STP to 0 ACK to 1 and the transmission data to x 00 With this setting the microcontroller returns an ACK 1 signal on the ninth clock 13 6 1 4Setting Up the Third Interrupt When the microcontroller receives the data x 33 from the slave device it returns ACK 1 signal and the C bus controller generates an interrupt At this point implement the following settings To set up the interrupt Set the I2COICH and I2COICL register pair x OOFC9C to x 0100 This enables interrupts and clears the previous interrupt request Tosetup the C registers 1 Read the IZ2CDREC register x 007E42 to determine the PC bus controller status 2 Since the transfer has ended set the I2CDTRM register x 007E40 to x 0300 This sets STA to 0 STP to 1 ACK to 1 and the transmission data to x 00 With this setting the microcontroller issues a stop condition and frees the bus CULL AH Note The circled areas are signals output from the MN102H75K 85K Figure 13 7 Waveform for Master Transmitter Trans
292. gle Phase Capture Input Using Timer 4 106 4 11 5 Setting Up a Two Phase Capture Input Using 4 108 4 11 6 Setting Up a 4x Two Phase Encoder Input Using Timer5 111 4 11 7 Setting Up a 1x Two Phase Encoder Input Using Timer 5 114 4 11 8 Setting Up a One Shot Pulse Output Using Timer 5 117 4 11 9 Setting Up an External Count Direction Controller Using Timer 5 120 4 11 10 Setting Up External Reset Control Using Timer 5 123 4 12 16 Bit Timer Control 125 5 Serial Interfaces 522 ua dcr ia ox oaa OR ds 127 5 1 Description bere beer eer 127 5 2 Inu T CC 127 5 3 Connecting the Serial Interfaces 2 128 5 3 1 Synchronous Serial Mode 128 5 3 2 UART Mode Connections pte ad acp 128 5 3 3 Mode Connection 128 5 4 UART Mode Batd Rates cc TR ER ER 129 5 5 Serial Interface Timing pe Rede NES etas es ed
293. gram area 248 KB x 0x80000 1KB x 0x80400 Load program area 7KB x 0x81FFE Fixed user program area Test area 1 word 248 KB User program area x 0xBFFFC x 0xBFFFF Test area 1 word Note shaded regions are write protected in this mode Cross hatched regions test areas not for use in user programs Figure B 1 Memory Map for Onboard Serial Programming Mode Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 316 Panasonic MN102HF75K Flash EEPROM Version Benefits B 2 Benefits Because you can maintain and upgrade the program in the MN102HF75K 85K up to and immediately following product release this version of the device shortens time to market by as much as one month This device is ideal for appli cations in quickly changing markets since it allows you to revise the microcon troller program in an existing product B 3 Using the PROM Writer Mode In this mode the MN102HF75K allows a PROM writer to program the internal flash memory as if it was a standalone memory chip The microcontroller is inserted into a dedicated adaptor socket which conne
294. he OSD Selecting YS palette output by setting the YSPLT bit of OSD1 x 007F06 to 1 disables the PRYM bit With this setting you must also set the TRPT and TRPTF bits to 1 You can specify transparency for individual color palettes if needed Translucency The TRPTF bit allows you to make the color 15 translucent in all the palettes and GPT2F RGB and YS are output at low levels for that color and YM is output at the level specified for the palette This dims the color on the display See figure 7 21 007 08 bit 10 0 Make color 15 all palettes translucent 1 Output color 15 as specified The PRYM bit allows you to make specific regions of the OSD display trans lucent This bit is disabled when the YSPLT bit is 1 x 007F08 bit 12 0 Output YS high on all OSD display areas 1 Output YS low on OSD display areas that do not have low YM output YS palette output The YSPLT bit allows you to control the YS output See figure 7 22 YSPLT x 007F06 bit 3 0 Output YS to entire display area except transparent and translucent areas 1 Output the MSB bit 15 of all the color palettes from YS Analog digital output The YCNT and RGBC bits allow you to select 16 bit gradient analog or digital output through the four OSD output pins R G B and YM x 007F06 bit 1 0 Analog YM output 1 Digital YM output outpu
295. ial reception interrupt the CPU reads the transmit receive buffer to retrieve the reception data A transmission interrupt can serve as a reception interrupt To set up the stop sequence 1 Setthe SCOIIC bit of SCOCTR to 0 to signal the stop sequence 2 When you signal the stop sequence the data reception is still in progress After the stop sequence is output you must disable reception and reinitialize reception for succeeding bytes Figure 5 14 shows an example timing chart 12C sequence output bit Write to SCOTRB Dummy data transmission for reception 7 SBOO0 output 5 bz Tbe b5 b4Tb3 b2 bo AC b7 b6 b5 b4 b3 b2 b1 f Tx interrupt request Tx interrupt request SBTO output x y i Start detection bit 1 Stop detection bit 1 Rx settings Data rx Stop sequence Figure 5 14 Master Receiver Timing 2 Mode with ACK 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 139 Panasonic Serial Interfaces Serial Interface Control Registers Bit Reset R W 5 7 Serial Interface Control Registers Three registers control each of the serial interfaces the serial port control regis
296. iconductor Development Company 55 Panasonic Interrupts Interrupt Control Registers VBIICH VBI 1 Interrupt Control Register High x 00FC67 Bit 7 6 4 3 2 1 0 VBI IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W VBIICH enables VBI 1 interrupts It is an 8 bit access register Use the MOVB instruction to access it The priority level for VBI 1 interrupts is written to the TMACBLV 2 0 field of the TMACBICH register VBIIE VBI 1 interrupt enable flag 0 Disable 1 Enable TM5CBICL Timer 5 Compare Capture B Interrupt Control Register Low x 00FC68 Bit 7 6 5 4 3 2 1 0 5 5 m mH mi ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R TMSCBICL detects and requests timer 5 compare capture B interrupts It is an 8 bit access register Use the MOVB instruction to access it TM5CBIR Timer 5 compare capture B interrupt request flag 0 No interrupt requested Interrupt requested TM5CBID Timer 5 compare capture B interrupt detect flag 0 Interrupt undetected Interrupt detected TM5CBICH Timer 5 Compare Capture B Interrupt Control Register High x O0FC69 Bit 7 6 5 4 3 2 1 0 TMSCB 5 5 5 Lv2 LVO IE Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R R R R W TMSCBICH sets the priority level for and enables timer 5 compare capture
297. ided for detecting and handling racing Normal operation is not guaranteed if the program returns after a watchdog interrupt For actions requiring returns use a timer interrupt If WDM 1 0 00 a watchdog interrupt occurs when the watch dog timer counts 218 cycles 5 4613 ms at 4 MHz fosc 12 MHz fsysci k The WDM set tings have the following mean ings 00 216 5 46 ms 01 24 1 33 us 10 212 0 34 ms 11 214 1 37 ms The main program normally clears the watchdog timer prior to a watchdog interrupt 2 2 2 Setting Up a Watchdog Timer Interrupt In this example a watchdog timer reset occurs The watchdog timer starts running after a reset when the NWDEN flag in the CPU mode register CPUM is enabled set to 0 When the watchdog timer overflows a nonmaskable interrupt occurs This means that the watchdog timer must be cleared in the main program PO CORE ROM RAM P5 Le Interrupts Bus Controller P2 Timers 0 5 Serial I Fs ADC P1 Figure 2 6 Block Diagram of Watchdog Timer Interrupt Enabling watchdog timer interrupts 1 Enable interrupts by writing a 1 to the interrupt enable flag IE in the PSW and setting the interrupt masking level IM 2 0 to 7 b 111 2 Activate the watchdog timer by clearing the NWDEN bit of the CPUM regis ter Set the time limit for the racing detection function in the WDM 1 0
298. ield to the right 16 dots a 16 dots 16 dots Figure 7 24 Character Shadowing Example Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 184 Panasonic On Screen Display Setting Up the OSD shadowing normal mode writing a 1 to bit 12 BSHAD1 of COL setting in the VRAM causes a box shadow to appear around all characters following that COL If COL bit 11 BSHADO is 0 the color specified in the WBSHD register x 007FA6 appears on the top and left sides of the box and the color specified in the BBSHD register x 007FA4 appears on the bottom and right sides of the box These positions are reversed if BSHADO is 1 Figure 7 25 shows an example of box shadowing As shown in the figure the right hand border of the shadow box appears in the character field to the right of the shadowed text a To output a box shadow to
299. igure 4 42 In down counting when the binary counter reaches 0 it loops to the value in 5 interrupt B occurs when the contents of TM5BC match those of TM5CB Table 4 4 Count Direction for 4x Two Phase Encoder Timing Example Up Counting Down Counting TM5IA t 1 L 0 7 0 1 5 0 7 1 1 T 0 iM 5 N TM5CB T LY 1000 J TM5BC 0000 1FFF 1 1FFD 1FFE 1FFF 0000 0001 JJorrr 1000 1001 TMSIA TMSIB Interrupt Figure 4 42 4x Two Phase Encoder Input Timing Timer 5 102 75 75 85 85 LSI User Manual 113 Panasonic Panasonic Semiconductor Development Company Timers 16 Bit Timer Setup Examples 4 11 7 Setting Up a 1x Two Phase Encoder Input Using Timer 5 In this example timer 5 inputs a 1x two phase encoded signal that makes it count up and down An interrupt occurs when the counter reaches a preset value P2 CORE ROM RAM P3 P6 Interrupts lt Bus Controller P5 Timers 0 3 Serial 1 TMBIA gt i F TMBIB P4 Timers 4 5 ADC A Chip Level Timer 5 TM5BC Interrupt B TM5CA 5 R c Y S Q
300. iles and the VRAM space that contains the text and graphics programs This allows you to adjust the memory space to fit your application unused layer to meet the restric T 2 Features tions outlined here Table 7 1 OSD Functions and Features Function Feature Text Layer Graphics Layer Characters or tiles per line 38 characters per line 2 18 or 28 tiles per line RAM usage 80 bytes per line Line by line basis Maximum 64 lines 40 or 64 bytes per line Line by line basis Maximum 64 lines ROM usage 36 bytes per character 16 colors 128 bytes per tile 4 8colors 96 bytes per tile 4colors 64 bytes per tile 2 colors 32 bytes per tile Max characters or tiles 1024 characters 512 tiles in all color modes Resolution 16 wide x 18 high pixels 16 W x 16 H pixels or In closed caption mode 16 W x 18 H pixels 16 W x 26 H underlining is in the hardware Color depth One 16 color palette out of 4096 colors Two 16 color palettes out of 4096 colors Total 32 colors in one display Display start position H 1 dot resolution 1024 steps V 1 H scan line resolution 1024 steps H 1 dot resolution 1024 steps V 1 H scan line resolution 1024 steps Character or tile size 16 character sizes line by line basis H 1x 2x 3x 4x V 1x 2x 4x 6x 16 character sizes line by line basis H 1x 2x 3x 4x V 1x 2x 4x 6x Display functions Shutter
301. ilize 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 325 Panasonic 102 5 Flash Version Using the Onboard Serial Programming Mode Start routine for the load program Reset start SBT pin high amp amp SDB pin low Wait twAIT1 SBT pin high amp amp SDB pin low Has twaite passed SBT pin high amp amp SDB pin high Start serial writer Execute user load program program Figure B 9 Load Program Start Flow Conditions 1 After the load program initiates a reset start SBD must be low and SBT high 2 Afterthe program waits twarri 10 milliseconds SBD must still be low and SBT high 3 Within twarr2 100 milliseconds both SBD and SBT must be high If any of these conditions is not met control returns to the user program Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 326 Panasonic MN102HF75K Flash Version Using the Onboard Serial Programming Mode B 4 7 Branching to the User Program 4 7 1 Branching to the Reset Start Routine Reset start Serial writer Start serial writer Branch to address load program x 82010 Execute user program Generate 10 cycle delay Figure B 10 Flow of Branch to Reset Start Routine When the reset starts the serial writer load program initializes only if SBD is low Otherwise the
302. imer 5 is reset by an external signal while counting up Setting P2 CORE ROM RAM P3 P6 Interrupts Bus Controller P5 Timers 0 3 Serial 1 P4 Timers 4 5 ADC A Chip Level Timer 5 Bosc 4 gt TM5BC ve TM5CA 5 2 5 Y s TM5IC 5 Block Level Figure 4 52 Block Diagram of External Reset Control Using Timer 5 Set the operating mode in the timer 5 mode register TM5MD Disable To set up timer 5 timer 5 counting and interrupts Select up counting Since the TMSIC signal will reset the counter asynchronously set the TM5ECLR bit to 1 Select 4 as the clock source TM5MD example x 00FE90 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 NLD m m UDI UDO ONE MD1 LP ASEL S2 81 50 0 2 1 1 Set the value to which timer 5 will loop valid settings x 0001 to x FFFF For TMSBC to count from x 0000 to x 1FFF for instance write x 1 FFF to 5 102 75 75 85 85 LSI User Manual 123 Panasonic Semiconductor Develo
303. imer Block Diagrams 4 9 16 Bit Timer Block Diagrams TM4IC pin Timer 0 underflow gt 4 5 Timer 1 underflow 5 amp CLR ASEL TMAR pin 8 2 5 TM4BC T s OSC 0 a LOAD n eco pin t UD Match Capture P2MD6 P2DIR6 setting TM4CAX 5 s TM4CB T Q gt TM4IOB pin TM4IA 9 TM4CBX u P2MD5 P2DIRS setting MD LD meg J TM4MD lt one Figure 4 15 Timer 4 Block Diagram pin Timer 0 underflow m i 8 Timer 1 underflow gt CLR H ASEL pin 8 EN gt gt 5 E Bosc 4 gt N R LOAD 4 gt gt TMSIOA pin t UD Match Capture 5 a P4MD2 P4DIR2 setting TM5CAX SR i Match it Capture 5 gt TM5IOB TMBIA gt TM5CBX R P4MD3 P4DIR3 setting MD LD reg D TM5MD one Figure 4 16 5 Block Diagram 4 10 16 Bit Timing
304. in Pin Pin Pin Pin Pin Pin R W R R R R R R R R P6IN Port 6 Input Register x 00FFD6 Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 P6IN1 P6INO Reset 0 0 0 0 0 0 Pin Pin R W R R R R R R R R The PnIN registers contain the port input data The bit number corresponds to the associated pin number For instance POIN7 applies to the P07 pin These are 8 bit access registers PODIR P5DIR Ports 0 5 I O Control Registers x O0FFEO x O0FFE5 P7DIR P8DIR Ports 7 8 I O Control Registers x 00FFE8 x 00FFEA Bit 7 6 5 4 3 2 1 0 PnDIR7 PnDIR6 PnDIRS PnDIR4 PnDIR3 PnDIR2 PnDIR1 PnDIRO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W P6DIR Port 6 I O Control Register x 00FFE6 Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 P6DIRI P6DIRO Reset 0 0 0 0 0 0 0 0 R W R R R R R R R W R W The PnDIR registers control the I O direction of the ports The bit number corresponds to the associated pin number For instance PODIR7 applies to the P07 pin These are 8 bit access registers 0 Input 1 Output Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 278 Panasonic Ports I O Port Control Registers POMD Port 0 Output Mode Register Bit 7 6 5 4 3 2 1 0 POMD7 POMD6 POMDS POMD4 POMD3 POMD2 POMDI POMDO Reset 0 0 0 0 0 R W R W R W
305. ion on setting the OSD clock frequency a Do not layer any graphic or cur sor tiles over italicized charac ters in closed caption mode 7 5 OSD Operation This section describes the basic operation of the OSD block The remainder of section 7 provides more detailed specifications 7 5 1 OSD Clock The OSD clock source is programmable to either the microcontroller system clock OSC1 OSC2 pins or a dedicated OSD clock OSDXI OSDXO pins OSC clock source An internal phase locked loop PLL multiplies the external 4 MHz frequency to generate an OSD clock that is synchronized to the trailing edge of the horizontal sync signal HSYNC This dramatically reduces EMI and character distortion The output frequency is programmable to 12 16 24 32 or 48 MHz OSDX clock source An LC blocking oscillator allows HSYNC to serve as the clock source You can also input an external clock through the OSDXI pin and synchronize it internally Frequency range 12 48 MHz 7 5 2 External Input Sync Signals Input the horizontal sync signal through the HSYNC pin and the vertical sync signal through the VSYNC pin The pullup resistors and polarity are pro grammable interrupt must occur so that the microcontroller can detect each VSYNC start field Set the interrupt edge in the IQI TG 1 0 bits of the EXTMD registers and the OSD input polarity in the VPOL bit of the OSDI register Note that you must these parameters separately 7 5 3 Mu
306. itioning to Master Receiver MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 301 Panasonic I C Bus Controller PC Interface Setup Examples 13 6 2 Setting Up a Transition from Slave Receiver to Slave Transmitter This example demonstrates how to set up a data transfer when changing from slave receiver to slave transmitter Figure 13 8 shows an example waveform 13 6 2 1 Pre configuring set up the I O port Set port control register 0 PCNTO 00 90 to x 0300 enabling the SDA1 and SCL pins and set the port 0 output mode register POMD x 00FFFO to x 0006 selecting the SDA1 and SCL1 functions To enable 2 interrupts Set the PC interrupt control register pair 12 1 and I2COICL x 00FC9C to x 0100 To setup the C registers 1 Set the I2CMYAD register x 007E44 to x 0024 This sets the slave address of the microcontroller 2 Set the I2CDTRM register x 007E40 to x 0000 This sets STA STP and the transmission data to Os With this setting the microcontroller returns an ACK 0 signal when an address match occurs The master sends data the slave address to the slave microcontroller in sync with the master clock When the R W bit 1 the microcontroller changes from a slave receiver to a slave transmitter 13 6 2 2Setting Up the First Interrupt Once the microcontroller becomes a slave transmitter set
307. kground control 0 Don t output color background 1 Output color background VCLK 2 0 clock select a Divide by ratio select The values in parentheses are applicable when the oscillator in the OSDI register is set to the OSC clock OSCSEL 1 0 00 You cannot set VCLK 2 0 to 100 000 Divide by 4 12 MHz 100 Don t divide 48 MHz don t divide when the OSC 001 Divide by 3 16 MHz 101 Reserved clock is selected Only select it 010 Divide by 2 24 MHz 110 Reserved when the clock source is 32 011 2 3 division 32 MHz 111 Reserved MHz or less CGPR Graphics text layer priority 0 Graphics layer takes priority Text layer takes priority SOUT GOUT COUT Layer output on off SOUT cursor layer GOUT graphics layer COUT text layer 0 Don t output layer 1 Output layer MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 209 Panasonic 5 Display OSD Registers OSD3 OSD Register 3 x 007F0A Bit 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 PEN CANH BFLD UNDF CAPM Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R RW RW RW RW RW RW BLINK Character blinking control Controls blinking for text layer characters with BLINK set in the COL code 0 Don t blink 1 Blink CANH Vertical position control for closed captions Active when interlacing is select
308. l Description 9 3 3 2 VSYNC Separator The VSYNC separator extracts the VSYNC signal from the composite signal Like the HSYNC separator it contains programmable methods for eliminating noise The VCNT register contains these settings Masking the to 127H range by setting the VSEPSEL bit of VCNT to 0 prevents VS YNC errors due to noise See figure 9 8 VSYNC 127H Masked signal Figure 9 8 VSYNC Masking 9 3 3 3 Field Detection Circuit The field detection circuit detects the phase difference between VSYNC and HSYNC based on the setting in the VPHASE 9 0 field of the FIELD register This setting is in units of the sampling clock for the HSYNC separator The results of the field detection are stored in the ODDEVEN bit of FIELD 9 3 4 Data Slicer The data slicer contains the maximum and minimum detection circuits the slice level calculator and the slicer The circuit compares the 8 bit digital values output from the ADC to the slice level which can be calculated by the hardware or set in the software It then outputs the results in serial Os and 1s The data slicer calculates the slice level the level above which a signal is 1 and below which is 0 from the maximum and minimum clock run in CRI pulses occurring in the interval between the settings in the CRIIS and registers CRI Data HSYNC X X X LI T gt
309. lected GPT2nYMO is output as YM GPT2nBO as GPT2nGO as and GPT2nRO as When the YS color palette is selected GPT2nY is output as YS GPT2nYN 3 0 YM color code GPT2nB 3 0 Blue color code GPT2nG 3 0 Green color code GPT2nR 3 0 Red color code MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 215 Panasonic Remote Signal Receiver Description 8 IR Remote Signal Receiver fSYSCLK 12 MHz in all of the examples and descriptions in this section In addition fPWM1 fSYSCLK 23 fPWMS fSYSCLK 25 fPWM5 fSYSCLK 27 fPWM6 fSYSCLK 28 and fPWM8 fSYSCLK 210 8 1 Description The MN102H75K 85K contains a remote signal receiver that processes signals in two formats Household Electrical Appliance Manufacturers Association HEAMA format and 5 6 bit format This chapter provides an overview of each block in the circuit and describes the operation of the receiver The remote signal is input through the RMIN pin Each time the edge detection circuit detects the active edge of the signal the 6 bit counter resets and the sampling clock Ts starts counting Ts is formed by dividing PWM3 by the value in the frequency division control register RMTC The clock status register RMCS which can be read at any time holds the current value of the 6 bit counter The remote signal contains a leader data and a trailer in that order The micro controller shifts received
310. ler This block controls the operation of every block within the CPU using the results from the instruction decoder and interrupt requests ALU Arithmetic and logic unit This block calculates the operand addresses for arithmetic operations logic operations shift opera tions relative indirect register addressing indexed addressing and indirect register addressing Multiplier This block multiplies 16 bits x 16 bits 32 bits Internal ROM and RAM These memory blocks contain the program data and stack areas Address registers An The address registers store the addresses in memory to be accessed in data transfers In relative indirect indexed and indi rect addressing modes they store the base address Operation registers The data registers store data to be transferred to memory and Dn MDR results of operations In indexed and indirect addressing modes they store the offset address The multiplication division register stores data for multiplication and division operations PSW The processor status word contains flags that indicate the status of the CPU interrupt controller and provide information about oper ation results Interrupt controller This block detects interrupt requests from peripheral function blocks and requests the CPU to service the interrupt Bus controller This block controls the connection between the CPU s internal and external buses It also contains a bus ar
311. losed Caption Decoder Closed Caption Decoder Registers MAXMIN CRI Interval Maximum and Minimum Register x 007E02 MAXMINW x 007E22 Bit 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 7 6 5 2 MIN7 MIN6 MINS MIN3 MIN2 MINI MINO Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 7 0 Maximum value during the CRI interval Valid range x 00 to x FF MIN 7 0 Minimum value during the CRI interval Valid range x 00 to x FF SLICE VBI Data Slice Level Register x 007E04 SLICEW x 007E24 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLSF SLSF SLSF SLSF SLSF SLSF SLSF SLSF SLHD SLHD SLHD SLHD SLHD SLHD SLHD SLHD 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Reset R W RW RW RW RW RW RW RW R R R R R R R R SLSF 7 0 VBI data slice level software setting Valid range x 00 to x FF SLHD 7 0 VBI data slice level hardware calculation Valid range x 00 to x FF Composite signal from ADC Compare 0 1 data SLHD MUX SLSF SLICESEL Figure 9 12 SLSF and SLHD Multiplexing Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 238 Panasonic Closed Caption Decoder Closed Caption Decoder Registers
312. lti Layer Format Multi layer technology enables the microcontroller to display text graphics and hardware cursor as different display layers with different color depths You can stack the layers in any order When the layers contain overlapping images the cursor always takes highest priority The priority of the text and graphics layers is programmable in the registers Text layer Each character in the text layer contains a foreground character color and a background color Outlining and shadowing are separate options In closed caption mode the OSD can only display the text in the encoded captions The graphics and cursor layers can be displayed in this mode but note that if any tiles from either layer overlaps italicized text the pixels in the graphic will be dis placed distorting the image Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 156 Panasonic 5 Display OSD Operation When you not using the DAC set the COMP and IREF pins for the DAC to H 1 After a reset clears the system clock supply to the OSD stops To operate the OSD you must first set the OSDPOFF bit of x 00FF90 to 1 Graphics layer The graphics layer contains tiled images In the 16 color mode each 4 bit dot on a tile can display one of 16 colors Each tile can use either of two available color palettes allowing a total of 32 colors in o
313. lue is compared to the count of the corrected HSYNC The valid range is x 000 to x 1FF and the recommended setting is x 0008 HLOCKLV lt HSYNC count asynchronous HLOCKLV gt HSYNC count synchronous Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 246 Panasonic Closed Caption Decoder Closed Caption Decoder Registers HDISTW Sync Separator Detection Control Register 2 x 007ED6 HDISTWW x 007EF6 Bit 15 14 13 12 11 10 9 8 6 5 4 9 2 1 0 HDIST HDIST HDIST HDIST HDIST HDIST HDIST HDIST HDIST W8 WT W6 WS WA 2 WI WO Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 RW R R R R RW RW RW RW RW RW RW RW RW HDISTW 8 0 HSYNC count setting the interval for sync separation detection In this register set the interval during which sync separation occurs The valid range is x 000 to x 1FF and the recommended setting is x 0100 For NTSC format set the register to 525 dec indicating an HSYNC count of 525 VSYNC cycles The recommended setting is x 0100 VCNT VSYNC Separator Control Register 007 08 VCNTW x 007EF8 Bit 15 14 13 12 11 10 9 8 7 6 5 4 z 2 1 0 VSEP VSEP VSEP VSEP SEL LMT2 LMTO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 R W R R R R R R R R W R R R R R R W R W RW VSEPSEL VSYNC signal
314. lup off 1 Pullup on c POPUPO 0 Poo IRQO 1 RMIN IRQO U lt LX 0 Port input 1 Port output PODIRO 0 Port low output 1 Port high output tn X POOUTO POINO lt f Schmidt trigger RMIN IRQO lt Figure 11 1 P00 RMIN IRQO0 Port 0 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 252 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on c POPUPn 0 P04 P05 06 P07 1 ADINO ADIN1 ADIN2 ADIN3 ADIN4 POMDn D L 0 Port input 1 Port output PODIRn 0 Port low output Pin 1 Port high output dj aan ADINO ADIN1 4 AAA ADIN2 ADIN3 ADIN4 Figure 11 2 P03 ADIN0 to P07 ADIN4 Port 0 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 253 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on c P1PUPn 0 P10 IRQ1 P11 IRQ2 P12 IRQ3 1 ADIN5 ADIN6 ADIN7 P1MD 2n 15 0 Port input 1 Port output P1DIRn 0 Port low output Pin 1
315. m accepting any other maskable interrupts by setting the IM 2 0 and IE bits of the PSW to 0 To accept the same interrupt during the interrupt service rou tine clear IR flag at the begin ning of it Enable interrupts by writing a 1 to the interrupt enable flag IE in the PSW and setting the interrupt masking level IM 2 0 to 7 b 111 Now if a falling edge occurs on IRQO 00 an interrupt will occur If the CPU accepts the interrupt the program branches to address x 080008 Servicing the interrupt 4 Interrupt servicing During interrupt preprocessing read the accepted interrupt group number register LAGR to determine the interrupt group group 4 in this case Branch to the interrupt service routine At the beginning of the interrupt service routine clear the IQOIR bit in IQOICL to 0 After the service routine ends return to the main program with the RTI instruction IRQO EXTMD Low level Falling edge IQ0IE if ft IQ0IR Registers R W EXTMD W IQ0ICH B IQ0ICL B IQ0ICL B IQOICL B Sequence 1 2 3 4 5 6 7 4 5 6 7 Figure 2 5 Timing for External Pin Interrupt Setup Example MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 41 Interrupts Interrupt Setup Examples watchdog timer interrupt is prov
316. m cycle of 2 fe vscrk With a 4 MHz oscillator 16 fsyscy x 1 33 us 8 us for SLOW mode and 2 fcvsck 341 3 us 2 ms for SLOW mode The 102 75 contains 50 pins that form general purpose I O ports Ports 0 1 2 3 4 and 5 are 8 bit ports and port 6 is a 2 bit port of these pins have alternate functions Ports 7 and 8 are only available with the quad flat package The MN102H75K 85K contains 50 pins that form general purpose I O ports Ports 0 1 2 3 4 and 5 are 8 bit ports and port 6 is a 2 bit port of these pins have alternate functions Ports 7 and 8 are only avail able with the quad flat package The MN102H75K contains one IC bus controller fully compliant with the 2 specification that can control one of two bus connections The MN102H75K 85K contains one C bus controller fully compliant with the specification that can control one of two bus connec tions Figure 13 3 shows the MN102H75K operation sequence in each of these modes In all modes the C bus controller generates an interrupt after each data byte transfer then the software loads the next data byte Figure 13 3 shows the MN102H75K 85K operation sequence in each of these modes In all modes the I2C bus controller generates an inter rupt after each data byte transfer then the software loads the next data byte Figure 13 6 and table 13 5 provide the timing definitions and specifica tions for the for th
317. ming chart TCO underflow 1 8 4 4 Rn SCOTRB write U SBOO st b0 bt b2 b3 b2 b3 b4 Interrupt request Interrupt service routine SCOTBSY S Figure 5 10 UART Transmission Timing Serial Interface 0 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 133 Panasonic Serial Interfaces Serial Interface Setup Examples 5 6 2 Setting Up Synchronous Serial Reception Using Serial Interface 0 This example illustrates serial reception in the synchronous serial mode with the following settings LSB first 8 bit character length Odd parity When a reception end interrupt occurs the CPU reads the data byte To set up the input port Set the PSDIR7 bit of the port 5 I O control register PSDIR to 0 This sets the SBTO pin to input To set up serial interface 0 Configure the reception settings in the serial port 0 control register SCOCTR Select timer 0 underflow x 1 8 as the serial port 0 clock source Select timer 0 underflow x 1 8 as the serial port 0 clock source Select synchronous serial mode odd parity 8 bit data length and LSB first output SCOCTR example x 00FD80 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sco SCO SCO SCO Sco Sco Sco SCO 5 0 Sco Sco SCO
318. n Bosc is off If you use an external clock it must be synchronized to Bosc TMACA captures the count on the rising edge of TMAIA and TMACB captures the count on the rising edge of TMAIB A timer 4 capture B interrupt occurs when TMACB captures the count and the contents of and TMACB are read during the interrupt service routine In the example timing chart shown in figure 4 38 x 000A x 0007 x 0003 or 3 cycles The calculation is correct even when TMACA is the larger value The flags are ignored so for instance x 0003 x FFFE x 0005 TMEN 0 011 21 314 5 6 7 8 9 CIDI EI F 10 11 12 BOSC 4 YY Y Y Y Y iY Y Y Y TM4CA 0 7 TM4CB 0 A el ae mak TMAIB mewt 0 Pd i bPidjig4 diii Figure 4 38 Two Phase Capture Input Timing Timer 4 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 110 Panasonic Timers 16 Bit Timer Setup Examples 4 11 6 Setting Up 4x Two Phase Encoder Input Using Timer 5 In this example timer 5 inputs a 4x two phase encoded signal that makes it count up and down An interrupt occurs when the counter reaches a preset value
319. nasonic Timers 16 Bit Timer Timing BC value FFFF Time r TMnIB i TMnIA 1 i 0033 Example 5 7 Figure 4 24 Two Phase Capture Input Timing 16 Bit BC value A Time TMnIA i f 1 TMnIB Figure 4 25 Two Phase 4x Encoder Timing 16 Bit Timers BC value Time TMnIA TMnIB Figure 4 26 Two Phase 1x Encoder Timing 16 Bit Timers MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 93 Panasonic Timers 16 Bit Timer Setup Examples 4 11 16 Bit Timer Setup Examples 4 11 1 Setting Up an Event Counter Using Timer 4 In this example timer 4 counts the TMAIB input signal Bosc 4 6 MHz or less and generates an interrupt on the second and fifth cycles TM4IB P2 CORE ROM RAM Interrupts Bus Controller P5 Timers 0 3 Serial I Fs gt Timers 4 5 ADC A Chip Level Timer 4 Bosc 4 TM4BC 4 TM4CAX ke TMAIB R a TM4OA TM4CB TM4CBX B Block Level Figure 4 27 Block Diagram of Event Counter Usi
320. nductor Development Company a TM2UDICH TMOUDICL and TMOUDICH are 8 bit access registers Use the MOVB instruction to access them Bit Setting Timers 6 Bit Timer Setup Examples 4 5 8 Bit Timer Setup Examples 4 5 1 Setting Up an Event Counter Using Timer 0 In this example timer 0 generates an underflow interrupt on the fourth rising edge of the TMOIO signal The event counter continues to operate during STOP mode In all modes but STOP the TMnIO signal input is synchronized to Bosc In STOP mode the timer counts TMnIO signal directly When an interrupt occurs the CPU returns to NORMAL mode after the oscillator stabilization wait The event counter con tinues to count the TMnIO signal during stabilization wait and at the same time that the CPU returns to NORMAL mode the event counter begins counting the signal resulting from the Bosc sampling of the TMnIO signal input TMol P2 CORE ROM RAM P4 P6 Interrupts K lt Bus Controller P5 gt Timers 0 3 Serial I Fs Timers 4 5 ADC Figure 4 9 Block Diagram of Event Counter Using Timer 0 1 Set the interrupt enable flag IE of the processor status word PSW to 1 2 Disable timer 0 counting in the timer 0 mode register TMOMD This step is unnecessary immediately after a reset since TMOMD resets to 0 TMOMD example x 00FE20 7 6 5 4 3 2 1 0 TMO TMO
321. nductor Development Company 183 Panasonic 5 Display Setting Up the OSD Z 10 2 Text Layer Functions This section describes the character enhancement functions available in the text layer Outlining In both normal and closed caption modes writing a 1 to bit 9 of the COL setting in the VRAM causes an outline to appear around all characters fol lowing that COL You can specify the color of the outline in the FRAME register x 007FA2 Figure 7 23 shows an example of character outlining As shown the figure if a character contains dots in the left or right borders of its field the outlining for those dots appear in the adjacent character field 16 dots 16 dots 16 dots gt Figure 7 23 Character Outlining Example Character shadowing In normal mode writing a 1 to bit 10 CSHAD of the COL setting in VRAM causes a drop shadow to appear behind all characters following that COL You can specify the color of the shadow in the FRAME register x 007FA2 Figure 7 24 shows an example of character shadowing As shown in the figure if a character contains dots in right border of its field the shadowing for those dots appear in the character f
322. ne display The graphics layer also supports 2 4 and 8 color modes the tiles in a single display screen must be in the same color mode For instance an 8 color mode tile cannot be displayed at the same time as a 16 color mode tile The size of one tile is 16W x 16H pixels in standard mode and 16W x 18H pixels in extended mode Cursor layer The cursor layer displays an icon indicating the position of the next entry One display screen displays only one cursor tile The ROM data and color palettes for the tile are the same as those of the graphics layer The size of one tile is 16W x 16H pixels in standard mode and 32W x 32H pixels in extended mode 7 5 4 Output Pin Setup To set up the output pins enable the OSD output pins in the I O registers Select DAC or digital output for RGB and YM Set the YS polarity 7 5 5 Microcontroller Interface The microcontroller writes display data to be sent to the OSD control registers and the VRAM which is assigned to internal RAM space The control registers CRAMEND and GRAMEND hold the end address of the data in the 7 5 6 VRAM Display data stored in the VRAM transfers automatically through a DMA transfer from the internal RAM to the OSD as the display approaches its specified position The microcontroller is suspended while the data is transferred on the bus See section 7 10 and Interrupt Timing on page 185 for more information on this timing The two MSBs
323. nes blink on underlined blinking characters Set bit 0 UNDF of the OSD3 register to O to disable underline blinking and set it to 1 to enable underline blinking The blink cycle lasts for 128 VSYNC pulses about 2 seconds The characters display for 96 VSYNCS about 1 5 seconds and turn off for 32 VSYNCS about 0 5 seconds Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 186 Panasonic On Screen Display Setting Up the OSD 7 10 3 Display Sizes B Graphic tile sizes x4 x3 x2 x1 GHSZ 1 0 41 b b 10 01 b O0 b 16 b 00 x1 b 10 x4 b 11 T x6 GVSZ 1 0 2x and 11 3x The 00 setting is reserved The settings shown are for interlaced displays In progressive displays the vertical size settings GVSZ 1 0 are as follows 01 1 10 102 75 75 85 85 LSI User Manual Figure 7 27 Graphic Tile Size Combinations Panasonic Semiconductor Development Company 187 Panasonic 5 Display Setting Up the OSD Character sizes 1 x2 x3 x4
324. ng Select 4 as the clock source Select double buffer operating mode Use the MOV instruction for this setup and only use 16 bit write TMAND example x 00FE80 operations Bit 15 14 1 2 1 10 9 8 7 6 5 4 3 2 1 0 4 TM4 4 4 4 4 4 4 4 4 4 4 4 4 NLD UDI UDO TGE ONE MD1 ECLR LP S2 81 50 This step stops the TM4BC count and clears both TM4BC see NL 16 7 29 S Q 9 0 387 LEO mco 70 97 c9 Wo d and the S R flip flop to 0 2 Set the divide by ratio for timer 4 To divide 4 by 5 write x 0004 to timer 4 compare capture register The valid range for TM4CA is x 0001 to x FFFE TMACA example x 00FE84 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM4 4 4 4 4 4 4 4 4 TM4 4 4 4 4 4 TM4 15 14 CAI3 CAI2 10 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 Set the timer 4 duty cycle For a 2 5 Bosc 4 duty cycle write x 0001 to timer 4 compare capture register B The valid range is 1 lt TMACB the TMACA value TM4CB example x 00FE88 Bit 15 14 13 12 11 10 9 8 7 6 5
325. ng Timer 4 To set up timer 4 1 Set the operating mode in the timer 4 mode register TM4MD Disable 1 timer 4 counting and interrupts Select up counting Select TM4IB as the clock source Use the MOV instruction for this setup and only use 16 bit write TMAND example x 00FE80 operations Bit 15 14 10 9 8 7 6 5 4 3 2 1 0 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 EN ND TGE ONE MD ECLR LP ASEL S2 si SO This step stops the TM4BG 0 0 0 0 0 0 0 0 1 0 0 1 0 count clears both 4 eset ed and the S R flip flop to 0 2 Set the divide by ratio for timer 4 To divide the TM4IB input signal by 5 write x 0004 to timer 4 compare capture register The valid range for is x 0001 to x FFFE Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 94 Panasonic Timers 16 Bit Timer Setup Examples TM4CA example x 00FE84 Bit 15 14 13 12 11 10 9 8 7 6 2 4 3 2 1 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 15 14 CAI3 12 CAII 0 CA9 CA7 CA6 CAS CA4 CA2 CAI CAO
326. nstruction for this setup and only use 16 bit write TMAND example x 00FE80 operations Bit 15 14 10 9 8 7 6 5 4 3 2 1 0 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 TM4 EN ND TGE ONE MD ECLR ASEL S2 si SO This step stops the TM4BG 1 0 0 0 0 1 1 count and clears both 4 entire ds ese roS ug and the S R flip flop to 0 2 Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0 This enables and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle Do not Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 106 Panasonic Timers 16 Bit Timer Setup Examples change any other operating modes during this step When TM4MD 1 0 b 10 dur 3 Set TMANLD TM4EN to 1 This starts the timer Counting begins at the ing capture TMACA and become read only regis ters To write to or must first set To enable timer 4 capture interrupts TM4MD 1 0 b 00 Cancel all existing interrupt requests Next set the interrupt priority level in the TMACBLV 2 0 bits of the TM4CBICH register levels 0 to 6 set the TMABIE bit to 1 and set the TMABI
327. nsumption The devices in this series contain up to 16 megabytes of linear address space and enable highly efficient program development In addition the optimized hardware structure allows for low system wide power consumption even in large systems 1 2 102 Series Features Designed for embedded applications the MN102H series contains a flexible and optimized hardware architecture as well as a simple and efficient instruction set It provides both economy and speed This section provides the features of the MN102H series CPU B High speed signal processing An internal multiplier multiplies two 16 bit registers for a 32 bit product in a single cycle In addition the hardware contains a saturation calculator to ensure that no signal processing is missed and to increase signal processing speed Linear addressing for large systems The MN102H series provides up to 16 megabytes of linear address space With linear addressing the CPU does not detect any borders between memory banks which provides an effective development environment The hardware architecture is also optimized for large scale designs The memory is not divided into instruction and data areas so operations can share instructions Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 18 Panasonic General Description MN102H Series Features B Single byte basic instruction length The MN102H series has replaced general
328. nt previous Complement previous 7 14 3 Considerations for Interlaced Displays Switching the display start field OSD is constructed so the display start position is the field field 1 where the EOMON bit is 1 However interlaced displays may require that the start position be a field field 2 where the EOMON bit is O In this case merely com plementing the EOSEL bit will not result in a correct display You must set the following two bits to have the display start at field 2 CANH 007 bit 4 Set to 1 0 Normal display 1 Slide the field 1 display position down 1 line EOSEL 007 bit 10 Complement the value EOSEL has for field 1 in a normal display Scrolling in the closed caption mode To implement text layer scrolling in the closed caption mode the program must constantly switch the text display fields This can cause the text lines to display incorrectly To prevent this set the following bits to fix the text lines to the even or odd field characters while scrolling BFLD x 007F0A bit 2 Set to 1 to enable scrolling 0 Normal display 1 Display the same characters in fields 1 and 2 EONL x 007F0A bit 3 Set to O or 1 0 Fix to characters in field 1 1 Fix to characters in field 2 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 202 Panasonic 5 Display OSD Registers
329. nternal System Clock Frequency 4MHz 12 MHz Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 324 Panasonic MN102HF75K Flash Version Using the Onboard Serial Programming Mode B 4 6 Setting Up the Onboard Serial Programming Mode enter serial programming mode the microcontroller must be in write mode This section describes the pin setup for the serial writer interface Normal timing waveform A B D I I l VPP RST E SeT SBD A Timing waveform during serial programming Vpp 1 1 1 1 Vpp da 1 l 1 BST do SE i Z SBD gt gt 4 H to t5 Figure B 8 Timing for the Serial Writer Interface set up the serial writer interface 1 Turn on the external Vpp supply 2 Attime in figure B 8 turn Vpp on At this point output RST SBD low 3 Through the serial writer drive the RST pin from time B in figure B 8 when SBT goes high on microcontroller power up for t5 cycles The microcontrol ler initializes 4 Through the serial writer drive the SBD pin low from time C in figure B 8 when RST goes high on microcontroller power up for t4 cycles This tells the microcontroller that it is connected to the serial writer 5 ts long enough to allow the microcontroller oscillator to stab
330. ntification Operating Mode Long Data Short Data HEAMA format gt 10 Ts cycles lt 2 Ts cycles 5 6 bit format gt 20 Ts cycles lt 4 Ts cycles The 6 bit counter regulates data format detection When the microcontroller detects a data leader it sets the LONGDF bit of the clock status register RMCS to indicate long data Figure 8 5 is a graphic representation of all the conditions for identifying the data format When the microcontroller detects a data trailer the hardware automatically shuts off the supply to sampling clock Ts which the 6 bit counter counts The counter resets and the clock supply restarts at the next edge detection 0 2 4 6 8 10 t2 16 20 24 28 32 36 40 64 Ts MEE Leader NE Leader 24 Pod i i When RMLD 3 0 6 i i o I Data Data 0 476 5 ormai z detection Data 1 8 5 tu Short I Short long 5 detection Long e Oh 8 Leader Leader 32 Ts E i Data Data 0 8 Ts I Q format o detection Data 1 16 Ts i Short long Short 4 detection Long 1 0 4 8 12 16 20 24 28 32 36 40 64 Ts Figure 8 5 Conditions for Detecting Data Formats Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 220 Panasonic Remote Signal Receiver IR Remote Signal R
331. nverts the clamped video signal to 8 bit digital data using a 12 MHz sampling clock Figure 9 2 shows an example con figuration using the recommended external pin connections In this example both caption decoders are used Figure 9 3 shows the recommended connection when neither decoder is used and figure 9 4 shows that when only CCDO is used PONTO x 00FF90 bit 4 8 2kQ Power Down VREFH OUT A D VIDEO 0 VREFL ADDATA 0 VBIOOFF PCNTO x 00FF90 bit 0 Low pass filter Clamping circuit ADC1ON PCNTO x 00FF90 bit 5 VIDEO IN 1 IN Power Down VREFH OUT A D VREFL 12 Miz Low pass filter _ x 00FF90 bit 1 Figure 9 2 Recommended ADC Configuration O CLH Used as P30 2308 VREFHS VREFHS 50 nu Used as P31 ViGEG IN External PM CVBS1 Used as P32 Used as P32 VREFLS Fy VREFLS 6 8 kQ CLL O Used as P33 Figure 9 3 External Connection with Figure 9 4 External Connection with Both CCD0 and CCD1 Unused Only CCD1 Unused CLL Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 228 Panasonic Closed Caption Decoder Functional Description Table 9 2 Caption decoder register setting VBI control ADC control Clamp control Use two cap caption 0 ON PCNTO bp0 0 ON PCNTO bp4 1 P3MD bp3 2 1 0
332. ny 169 Panasonic 5 Display GRAMEND 40xN 5 Line N data GRAMEND 40x N 1 x GRAMEND 40xn 5 GRAMEND 40x n 1 Line 2 data Line 1 data GRAMEND 7B GRAMEND 40 GRAMEND 3B GRAMEND GRAMEND 3F GRAMEND 3E GRAMEND 3D GRAMEND 3C GRAMEND 3B GRAMEND 3A GRAMEND 2F GRAMEND 2E GRAMEND 3 Low order 8 bits GRAMEND 2 of graphics code GRAMEND 1 High order 8 bits GRAMEND of graphics code A GEXTE 1 GRAMEND 28xN 1 Line N data EN GRAMEND 28x N 1 GRAMEND 27 25 Code 20 GRAMEND 25 GRAMEND 24 GRAMEND 23 GRAMEND 28xn 1 GRAMEND 28x n 1 Line 2 data Line 1 data GRAMEND 4F GRAMEND 28 GRAMEND 27 GRAMEND GRAMEND 22 GRAMEND 5 GRAMEND 4 GRAMEND 2 of graphics code GRAMEND 1 High order 8 bits of graphics code B 0 Figure 7 7 Graphics Organization for Two Modes Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 170 Panasonic 5 Display VRAM 7 8 3 Cautions about the number of display code set to VRAM When the display lines are adjoined or overlapped and the number of the above display code is extremely fewer than that of the below one first line of the display line may not be output correctly In OSD circuit font data to display are read from ROM and stored to the buffer The data in the buffer are overwritten after the present display c
333. ock Timing Determination 9 3 5 2 Data Capture Control The DATAS and DATAE registers control the data capture timing and the CAPDATA register stores the caption data captured on the sampling clock gen erated through CRI detection The HNUM register controls interrupt timing CRI Data ms n DATAS Sampling clock CRI2S DATAE Figure 9 11 Caption Data Capture Timing 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 235 Panasonic Closed Caption Decoder Closed Caption Decoder Registers 9 4 Closed Caption Decoder Registers Allregisters in Closed caption Decoder block cannot be written by byte by word only Read by byte 15 possible Table 9 9 Closed Caption Decoder Register CCD0 CCD1 Register Address Address R W Description FCCNT x 007E00 007 20 R W VBI decoding format select register MAXMIN x007E02 x 007E22 R CRI interval maximum and minimum register SLICE x 007E04 x 007E24 R W VBI data slice level register HNUM x007E06 x007E26 R HSYNC count register ACQ1 x 007E08 x 007E28 R W ACQ capture timing control register 1 CAPDATA 007 x 007E2A Caption data capture register CRIFA x 007EOC x 007E2C CRI frequency wi
334. ock source once you select it Selecting the clock source while you set up the count operation control will corrupt the value in the binary counter In the bank and linear address ing versions of the MN102 series it was necessary to set TM1EN and TM1LD to 0 between steps 3 and 4 to ensure stable operation This is unnecessary in the high speed linear addressing version 3 TMILD bit of the TMIMD register to 1 This loads the value in the base register to the binary counter At the same time select the clock source as Bosc 4 by writing b 00 to TM1S 1 0 TM1MD example x O0FE21 Bit T 6 5 4 3 2 1 0 TMI TMI TMI TMI EN LD 51 50 Setting 0 1 0 0 0 0 0 0 4 Set TMILD to 0 and TMIEN to 1 This starts the timer Counting begins at the start of the next cycle When the binary counter reaches 0 and loads the value x 26 from the base register in preparation for the next count a timer 1 underflow occurs The serial interface operates in sync with this underflow output Figure 5 12 shows an example timing chart Bosc 4 TMiBR 00 126 Y Y Y Y y y y y y 1 00 26 90 26 00 26 00 26 00 26 00 26 00 26 00 26 00 26 00 26 00 26
335. ode is output to the display data of the next line Show the example when the display lines are adjoined The number of the display code in the above line line M is reffered to n and that of the below one line M 1 is refferred N The buffer holds n display data of the last line of line M at the time of A see figure below and the data in the buffer are overwritten to the display data of the first line of line M 1 as time goes by At the time of B the buffer holds n display data of the first line of line M 1 In case n is smaller than N N n display data are needed to display the first line of line M 1 and to be written to the buffer before it is shown on the display Especially when n is extremely smaller than N a large amount of the display data is needed to be written to the buffer before display And in case writing is not done in time it shows wrong data on the screen HSYNC line M last line line M 1 last line i he number of displa the number of t display code n display code N Buffer line M 1 first line line M 1 first line line M 1 second line data write n data write N n data write N Figure 7 8 Timing for OSD data To prevent the wrong display written above the first line of the below line is to be shown later enough after the last line of the above line is displayed The time Td needed for the correct display is caluculated as below Td 0 8 N n x0 5 us n the number of display code
336. odify the ROM space that con tains the text characters and the graphic tiles and the VRAM space that contains the text and graphics programs This allows you to adjust the memory space to fit your application The MN102H75K 85K contains an on screen display OSD function composed of three layers a text layer a graphics layer and a cursor layer You can control each layer individually which gives you great freedom in positioning displays You can also modify the ROM space that contains the text characters and the graphic tiles and the VRAM space that contains the text and graphics programs This allows you to adjust the memory space to fit your application This section describes how the MN102H75K handles the timing of direct memory access transfers of OSD data and OSD inter rupts This section describes how the MN102H75K 85K handles the timing of direct memory access DMA transfers of OSD data and OSD inter rupts The MN102H75K OSD achieves a shuttering effect using four pro grammable shutters two vertical and two horizontal With this fea ture you can shutter any portion of the OSD display or you can combine shuttering with a wipe out effect to create a smooth appearing and disappearing effect The MN102H75K 85K OSD achieves a shuttering effect using four programmable shutters two vertical and two horizontal With this fea ture you can shutter any portion of the OSD display or you can com bine shuttering with
337. of the transferred data contain one or more of the following ID codes Text layer 1 Character code CC 2 Color control code normal mode COL 3 Color control code closed caption mode COL 4 Repeat character blank code CCB 5 Character horizontal position code CHP 6 Character vertical position code CVP Graphics layer 1 Graphic tile code GTC 2 Graphics horizontal position code GHP 3 Graphics vertical position code GVP MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 157 Panasonic 5 Display OSD Operation Set CHP GHP GVP for every line in the VRAM If you do not a software processing error may occur 7 5 7 Conditions for VRAM Writes B Textlayer The lead data for each line must be the color control code COL or the char acter code CC Never place the horizontal position CHP vertical position CVP or repeat CCB codes at the beginning of a line If the lead data is CC with no COL specification the character will be text palette color 1 and the background will be color 2 Place each line s horizontal and vertical position data CHP and CVP in that order at the end of the preceding line Insert the color control code COL before the character code CC You do not need to meet condition 3 in the closed caption mode since COL can carry over in that mode A character code CC must immediately precede a repeat charact
338. ompany 102 75 75 85 85 LSI User Manual 146 Panasonic Analog to Digital Converter ADC Setup Examples 6 5 ADC Setup Examples 6 5 1 Setting Up Software Controlled Single Channel A D Conversion This example illustrates single channel conversion controlled by the software The ADIN6 pin inputs an analog voltage signal 0 0 3 3 V and the ADC converts it to 8 bit digital values MN102H75K Queue eere doce s P11 ADIN6 Figure 6 8 Single Channel A D Conversion To set up the input port Set the PIMD2 bit of the port 1 output mode register PIMD to 1 This sets the ADING pin P11 to analog input To set up the ADC 1 Set the operating conditions in the ADC control register ANCTR Select single channel single conversion mode ANMD 1 0 b 00 Bosc 8 as the clock source ANCK 1 0 b 10 and channel 6 as the conversion channel AN1CH 3 0 b 011 Set the conversion start busy bit ANEN to 0 ANCTR example x O0FFO00 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NCH3 2 ICH3 2 1CHO m gt CKO MDI Setting 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 When the software controls the 2 Set ANEN to 1 to start conversion Conversion starts on the first rising edge S itmust setthe of the ADC
339. ompany 33 Panasonic General Description Pin Descriptions Considerations for power supply clock and reset pins O lt AVpp Power MN102H75K Supply MN102H85K Vss AVss Vss O lt Note Ifthe circuit uses the same power supply for digital and analog supplies connect the pins in the location closest to the power supply Figure 1 11 Power Supply Wiring OSC1 Osc2 OSC1 osc2 4 MHz 0 1 uF t 1 Co 4 MHz N Oscillation 7117 7 7 Circuit 77 Note capacitance values vary depending the oscillator Figure 1 12 OSC1 and OSC2 Connection Examples 4 A 9 RST ue Y 10 uF 100 pF x 77 77 Figure 1 13 Reset Pin Connection Example 1 OSDXI OSDXO OSDXI OSDXO 16 2 48 2 a 16MHz 48MHz Oscillation Circuit ZZ Note The capacitance values vary depending on the oscillator Figure 1 14 OSDXI and OSDXO Connection Examples Connection the PLL circuit The MN102H75K 85K contains an internal PLL circuit To use this circuit you must connect it to an external lag lead filter Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 34 Panasonic General Description Bus Interface 1 7 Bus Interface 1 7 1 Description The bus interface operates in external e
340. on 1 bit interrupt PWM 8 bit with 7 channels 3 3 volt tolerance Closed caption decoder 2channels Internal sync separator On screen display Three layer format Textlayer 16 x 18 pixels 16 x 26 in closed caption mode blink ing outlining shadowing foreground and background shutter effect italics CC mode underlining CC mode Graphics layer 16 x 16 16 x 18 pixels Cursor layer 16 x 16 32 x 32 pixels 1 cursor displaying one graphic tile Color depth One 16 color palette out of 4096 colors Dot clock Internal PLL frequencies 12 16 24 32 and 48 MHz External clock 16 48 MHz LC blocking oscillator 16 48 MHz ports 66 MN102H75K F75K 50 MN102H85K F85k Package 84 pin QFP MN102H75K F75K 64 pin SDIL MN102H85K F85k MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 27 Panasonic General Description Block Diagram 1 5 Block Diagram Address registers Data registers A0 D0 1 Clock lt Clock 1 01 2 generator souca A2 D2 Multiplication Division Register A3 D3 MDR Multiplier Program Counter Instruction execution controller Instruction decoder Quick decoder Incrementer N Instruction Interrupt queue controller
341. on data bit D9 or D1 for address n CHDO Correction data bit D8 or DO for address n Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 292 Panasonic I C Bus Controller Description 13 2 Bus Controller 13 1 Description The MN102H75K 85K contains one C bus controller fully compliant with the Pc specification that can control one of two IC bus connections An bus is a simple two wire bus for transferring data between ICs Since it requires only two lines a serial data line SDA and a serial clock line SCL it minimizes interconnections so ICs have fewer pins and there are less PCB tracks The result is smaller and less expensive PCBs Figure 13 1 shows a typical PC bus application Data line SDA Clock line SCL Figure 13 1 Example of I C Bus Application In an PC bus system devices are considered as masters or slaves when performing data transfers A master is the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer At that time any device addressed is considered a slave Table 13 1 defines some IC bus terminology Table 13 1 I C Bus Terminology Term Description Transmitter The device that sends the data to the bus Receiver The device that receives the data from the bus Master The device that initiates a transfer generates clock signals and termi nates a transfer Slave The device addr
342. on to access it ADMSIR Address match 3 interrupt request flag 0 No interrupt requested 1 Interrupt requested ADMSID Address match interrupt detect flag 0 Interrupt undetected 1 Interrupt detected 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 61 Panasonic Interrupts Interrupt Control Registers ADM3ICH Address 3 Match Interrupt Control Register High x 00FC79 Bit 7 6 5 4 3 2 1 0 ADM3 ADM3 ADM3 ADM3 Lv2 LVO 7 E IE Reset 0 0 0 0 0 0 0 0 R W R R W R W R R R R W sets the priority level for and enables address match 3 inter rupts It is an 8 bit access register Use the MOVB instruction to access it ADM3LV 2 0 Address match 3 interrupt priority level Sets the priority from 0 to 6 ADMSIE Address match 3 interrupt enable flag 0 Disable 1 Enable ADM2ICL Address 2 Match Interrupt Control Register Low x 00FC7A Bit 7 6 5 4 3 2 1 0 _ _ 2 2 IR ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R ADM2ICL detects and requests address match 2 interrupts It is an 8 bit access register Use the MOVB instruction to access it ADM2IR Address match 2 interrupt request flag 0 No interrupt requested Interrupt requested ADM2ID Address match 2 interrupt detect flag 0 Interrupt undetected Interrupt detected
343. onfiguration Example 1 of 1x Two Phase Capture Input Using Timer 5 114 4 45 Configuration Example 2 of 1x Two Phase Capture Input Using 5 114 4 46 1x Two Phase Encoder Input Timing Timer 5 116 4 47 Block Diagram of One Shot Pulse Output Using Timer 5 117 4 48 One Shot Pulse Output Timing Timer 5 119 4 49 Block Diagram of External Count Direction Control Using Timer 5 120 4 50 Configuration Example of External Count Direction Control Using Timer 5 120 4 51 External Count Direction Control Timing Timer 5 122 4 52 Block Diagram of External Reset Control Using Timer 5 123 4 53 External Reset Control Timing Timer 5 2 2 1 124 5 1 Serial Interface Configuration Example 127 5 2 Synchronous Serial Mode 1 128 5 3 UART Mode Connections NUDO 128 5 4 IC Mode Connection 128 5 5 Synchronous Serial Transmission
344. ontrollers to the 12 Bus Table 13 2 describes the four possible operating modes for devices on the PC bus Table 13 2 Operating Modes for Devices on 2 Bus Operating Mode Description Master transmitter Device that generates the serial transfer clock SCL signal and transmits serial data to a slave device in sync with SCL Master receiver Device that generates the SCL signal and receives serial data from a slave device in sync with SCL Slave transmitter Device that transmits data in sync with the SCL signal from the mas ter Slave receiver Device that receives data in sync with the SCL signal from the master Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 294 Panasonic I C Bus Controller Description Figure 13 3 shows the MN102H75K 85K operation sequence in each of these modes In all modes the IC bus controller generates an interrupt after each data byte transfer then the software loads the next data byte Interrupt Interrupt Interrupt MN102H51K R W 0 A A Address Caster me w Data 8 bits Data 8 bits Slave ACK ACK ACK Normally ACK 0 A Master Transmitter ACK 1 signals transfer end to slave transmitter Interrupt Interrupt Interrupt MN102H51K R W 1 Address CMaster 7 bits RAN ack Slave ACK Da
345. operation has the value 1 this flag is set if that bit is 0 this flag is reset ZX Extension zero flag If all bits of the result of an operation have the value O this flag is set oth erwise it is reset VF Overflow flag If the operation causes the sign bit to change in a 16 bit signed number this flag is set otherwise it is reset CF Carry flag If the operation resulted in a carry into from addition or a borrow out of from subtraction or a comparison bit 15 this flag is set otherwise it is reset NF Negative flag If bit 15 of the result of an operation has the value 1 this flag is set if that bit is 0 this flag is reset ZF Zero flag If the least significant 16 bits of the result of an operation have the value 0 this flag is set otherwise it is reset Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 22 Panasonic General Description MN102H Series Description Internal registers memory and special function registers 2 3 O gt o o a o o U Oo N gt o o e o gt o gt gt gt gio Multiplication Division Register 15 0 MDR Processor Status Word 15 0 PSW Memory SFRs and Ports RAM CPUM EFCR IAGR NMICR
346. output H level before invoking STOP mode Reset OSD1 OSD Register 1 x 007F06 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 OSC OSC YS YS OSD SELI SELO HPOL VPOL POL PLT YCNT RGBC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R W RW RW RW RW RW RW RW R RW R W 0 Off 1 On OSCSEL 1 0 Oscillator select 00 OSC clock PLL internal synchronization 01 OSDX clock with LC blocking oscillator 10 OSDX clock external source internal synchronization 11 Reserved XIO OSDX frequency select Frequency range 12 to 48 MHz 0 Less than 20 MHz 1 Greater than 20 MHz HPOL HSYNC input polarity select 0 Active low 1 Active high VPOL VSYNC input polarity select 0 Active high 1 Active low YSPOL YS output polarity select 0 Active high 1 Active low YSPLT YS color palette select 0 Output YS to entire display area except transparent and translucent areas 1 Output the MSB bit 15 of all the color palettes from YS YCNT YM DAC digital output select 0 DAC output 1 Digital output Digital output is the LSB of YM bit 12 of the color palette RGBC RGB DAC digital output select 0 DAC output 1 Digital output Digital output is the LSB of each color R bit 0 of the color palette G bit 4 of the color palette B bit 8 of the color palette Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 2
347. ow An interrupt occurs when transmission ends and the next data byte is written to SCOTRB If the application does not use interrupts it must poll the SCOTBY flag of the SCOSTR register It can write the transmission data when SCOTBY is 0 Tosetup the output port Set the PSMDS bit of the port 5 output mode register PSMD to 1 This selects the SBOO pin as the serial interface output port P5MD example x O0FFFA Bit 7 6 5 4 3 2 1 0 P5 P5 P5 P5 P5 P5 P5 P5 MD7 MD6 MD5 MD4 MD3 MD2 MDI MDO Setting 0 1 0 0 0 0 0 0 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 131 Panasonic Serial Interfaces Serial Interface Setup Examples To set up serial interface 0 1 Configure the transmission settings in the serial port 0 control register 5 Since the transfer clock is timer 0 divided by 8 select timer 0 underflow x 1 8 as the serial port 0 clock source Select UART mode odd parity 2 bit stop bit 8 bit data length and LSB first output Also set the SCOREN and SCOTEN flags to 0 disabling transmission and reception SCOCTR example x 00FD80 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sco SCO SCO SCO SCO SCO SCO SCO Sco SCO Sco SCO _ Sco Sco TEN REN BRE DCS PTL OD DCM LN 2 PTYO SB 51 50 Setting 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 2 Setthe SCOTEN bit to 1
348. pment Company Panasonic Timers 16 Bit Timer Setup Examples TM5CA example x 00FE94 Bit 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 15 14 CA13 12 10 CA9 CA7 CA6 CA5 CA4 CA2 CAI CAO Setting 0 0 0 1 1 1 3 Set the TMSNLD bit of the TM5MD register to 1 and the TM5EN bit to 0 This enables TM5BC and the S R flip flop This step ensures stable opera tion If it is omitted the binary counter may not count the first cycle 4 Set TM5NLD and TMSEN to 1 This starts the timer Counting begins at the start of the next cycle From this point on whenever the 5 signal is high timer 5 will be reset asynchronously This is an easy way to synchronize the microcontroller operation with an external event You can use it to adjust motor speed or to initialize the timers through the hardware Timer 5 does not operate in STOP mode when Bosc is off If you use an external clock it must be synchronized to Bosc Figure 4 53 shows an example timing chart TM5BC 0000 0001 0002 0003 0004 0000 0001 0002 0003 4 Y Y Yl Y 1 Y TM5IC Figure 4 53
349. power modes timers and serial connections Chapters 6 to 10 describe the on screen display and other specialized functions available with the MN102H75K Chapter 11 provides the I O port specifications chapter 12 describes ROM correction feature chapter 13 describes the PC interface and chapter 14 describes the H scan line counter Appendix A provides a register map and Appendix B describes the flash EEPROM version This manual is intended for assembly language programming engineers It describes the internal configuration and hardware functions of the MN102H75K and MN102H85K microcontrollers Except when discusssiing differing specifications this manual refers to the two microcontrollers as a single device MN102H75K 85K Using This Manual The chapters in this manual deal with the internal blocks of the MN102H75K 85K Chapters 1 to 5 provide an overview of the MN102H75K 85K s general specifications interrupts power modes timers and serial connections Chapters 6 to 10 describe the on screen display and other specialized functions available with the MN102H75K 85K Chapter 11 provides the I O port specifications chapter 12 describes the ROM correction feature chapter 13 describes the interface and chapter 14 describes the H scan line counter Appendix A provides a register map and Appendix B describes the flash EEPROM version MNTO200 Series Linear Addressing High Speed Version LST User Manual Describes th
350. produced directly in assembly language This gives designers the advantage of short development time in a C language envi ronment without the trade off in code size expansion The PanaXSeries development tools support MN102H series devices Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 20 Panasonic General Description MN102H Series Description B Outstanding power savings The MNIO2H series contains separate buses for instructions data and peripheral functions which distributes and reduces load capacitance dra matically reducing overall power consumption The series also supports three HALT and STOP modes for even greater power savings The MN102H series is the flagship product for Panasonic s new high per formance architecture Panasonic will expand the series as it strives to improve the CPU core s performance and speed and as it develops devices incorporating ASSPs ASICs internal EPROM and other products to meet the needs of a wide array of embedded designs 1 3 MN102H Series Description This section describes the basic architecture and functions of MN102H series devices Processor status word PSW The PSW contains the operation status flags and interrupt mask levels flags Note that the PSW for the MN102H series contains flags for both 16 and 24 bit operation results Flags forA 1124 B its Bir 15 14 13 12 11
351. pture Input Using Timer 4 B To set up timer 0 1 Disable timer 0 counting in the timer 0 mode register TMOMD This step is unnecessary immediately after a reset since TMOMD resets to 0 TMOMD example x 00FE20 Bit 7 6 5 4 3 2 1 0 TMO TMO TMO TMO EN LD 51 50 Setting 0 0 0 0 0 0 2 Set the divide by ratio for timer 0 To divide Bosc 4 by two write x 01 to the timer 0 base register TMOBR The valid range for TMOBR is 0 to 255 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 108 Panasonic Timers 16 Bit Timer Setup Examples Do not change the clock source once you select it Selecting the clock source while you set up the count operation control will corrupt the value in the binary counter In the bank and linear address ing versions of the MN102 series it was necessary to set TMOEN and TMOLD to 0 between steps 3 and 4 to ensure stable operation This is unnecessary in the high speed linear addressing version Use the MOV instruction for this TMOBR example x 00FE10 Bit 7 6 5 4 3 2 1 0 TMO TMO TMO TMO TMO TMO TMO TMO BR7 BR6 BR5 BR4 BR3 BR2 BRI BRO Setting 0 0 0 0 0 0 0 1 3 Set the TMOLD bit of the TMOMD register to 1 This loads the value in the base register to the binary counter At the same time select the clock source as Bosc 4 by writing b 00
352. pture Register x 007E0A CAPDATAW x 007E2A Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP CAP DA15 14 DAI3 DAI2 DA11 DAIO DA9 DA8 DA7 DA6 DAS DA4 DA2 DAI DAO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R CAPDA 15 0 Caption data This register stores the 16 bit captured caption data MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 239 Panasonic Closed Caption Decoder Closed Caption Decoder Registers CRIFA CRI Frequency Width Register x 007E0C CRIFAW x 007E2C Bit 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 CRD CRI2 CRD FQW7 FQW6 5 FQW4 EQW3 FQW2 FQW1 FOW0 FQW7 FQW6 5 FQW4 FQW3 2 FQW1 FQWO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The CRIFA and CRIFB registers store the CRI cycles from rising edge to rising edge for monitoring whether the CRIs were detected correctly dur ing this period CRI2FQW 7 0 CRI frequency width 2 This field indicates the width in clock units from the second to the third rising edge after the CRI CRI1FQW 7 0 CR
353. r HLOCKLV x 007ED4 x 007EF4 R W Sync separator detection control register 1 HDISTW x 007ED6 x 007EF6 R W Sync separator detection control register 2 VONT x 007ED8 x 007EF8 R W VSYNC separator control register HVCOND 007 x007EFA R Sync separator status register CLPCND1 x007EDC x007EFC R Clamping control signal status register 1 SBFNUM x 007F4C x 007F6C R Sampling start position register TESTA x 007F4E x 007F6E R Test register Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 236 Panasonic Closed Caption Decoder Closed Caption Decoder Registers FCCNT VBI Decoding Format Select Register x 007E00 1 FCCNTW x 007E20 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLPU NCRI Pordestens usine thexlosedicau FCP SYNC HCNT HCNT SLICE SLICE SLICE SLICE 1 CRIC G CNT CNT CNT CNT CNT gns 8 p SEL SEL SELI SELO SEL LD2 LD1 LDO SEL STAP4 STAP3 STAP2 STAP1 STAPO SEL SEL tion decoder always tie the FCCNT Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 register to x 0008 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW This register contains the settings for selecting either a hardware or soft ware slice level and for setting the data capture format When you do not use a bit or
354. r Setup Examples 4 11 3 Setting Up Two Phase PWM Output Signal Using Timer 4 In this example timer 4 is used to divide timer 0 underflow by 5 and generate five cycle two phase PWM signal The phase difference of this signal is 2 cycles To accomplish this the program must load the divide by ratio of 5 actual setting 4 into compare capture register A and a cycle count of 2 actual setting 1 into compare capture register B P3 CORE ROM RAM P4 P6 Interrupts Bus Controller P5 Timers0 3 Serial l Fs 4 k Timers 4 5 ADC TM4OB A Chip Level Timer 4 Timer 0 TM4BC underflow t 4 TM4CAX R Y x TM4CB TM4CBX Q gt Controller T Q gt B Block Level Figure 4 32 Block Diagram of Two Phase PWM Output Using Timer 4 set up the output port Set the PZMD 13 12 bits of the port 2 output mode register P2MD to b 01 selecting the TM4IOA pin set the PAMD 11 10 bits to b 01 selecting the TMAIOB pin and set the P2DIR 6 5 bits of the port 2 I O control register P2DIR to b 11 selecting output direction This step selects the TM4OA P26 and TMAOB 25 pins as the timer output ports
355. r more detailed information required for your design purchasing and applications If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book Contents Contents About This 16 Using This Manual c eR PERMESSO EUR 16 Text Conventions reg bec e RE E E WE Ae abeam E 16 Register Conventions siis sno eoe eR Rn ete babe 16 Related Documents sess ac prm ac RD A La ale RC ORES Ta ee SRA 17 Questions and Comments 1 mee eos Wh eS die rec b ee 17 1 General Descriptlon 2er Re b a i ea ae 18 1 1 MN102H Series QV rvIeW u uy Rude ee eer UTAH ee Du enne 18 1 2 MN 102H Series Features ua d e ehe eee epe re eS ls 18 1 3 MN102H Series Description uha quypaq pee ee LPS EE aad 21 1 4 General Specifications oss Le pO Ce UPS eee o DEVE TER 26 1 5 Block Diagram a RU Eg d Rr quide BUR QA RE 28 1 6 Pin Descrptions a us su aaa bee de ESTRENO e x e rv epe ua eee et 30 1 6 1 MN102H85K Pin 30 1 6 2 MN102H75K Pin 2 2 2 2 31 1 7 Bus Interface cese rebos
356. r sampling cycles This eliminates any noise occurring during one or two sampling cycles Select the sampling clock PWM6 or PWMS with the SP bit of the RMLD register PWM6 is selected at reset ws j Noise filter m output em Noise eliminated Figure 8 2 IR Remote Signal Noise Filtering Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 218 Panasonic Remote Signal Receiver IR Remote Signal Receiver Operation 8 3 3 8 Bit Data Reception Resetting the 8 bit data reception counter allows the microcontroller to receive 8 bit data either with or without a leader The software can reset the counter using the BCRSTE and BCEDGS bits of the interrupt status register RMIS The counter can also be reset by an external reset or a hardware reset at leader detection Set BCRSTE to enable resets to the 8 bit data reception counter When the BCEDGS bit is 0 the counter resets at the first remote signal edge after each trailer detection This mode is for data containing no leader See figure 8 3 8 bit data Trailer 8 bit data Remote signal input Edge detection 8 bit data 8 bit data reception detection 4 Trailer detection reception X 5 X 6 X 7K 0 1 X 2 counter 4 Counter reset Figure 8 3 Reception of 8 Bit D
357. r the next VSYNC input 3 Write a 0 to OSDPOFF PONTO bit 7 turning the clock off If you turn the clock off before the VSYNC input power usage may not drop or the microcontroller may halt OSDPOFF OSD circuit enable Setting this bit to 0 shuts off the system clock supply to the OSD block reducing power dissipation The program must write a 1 to this bit before writing any values to the OSD registers 0 Disable 1 Enable PLLPOFF PLL circuit enable 0 Enable 1 Stop ADC1ON ADC circuit enable for closed caption decoder 1 0 Disable 1 Enable ADCOON ADC circuit enable for closed caption decoder 0 0 Disable 1 Enable HCNTOFF H counter circuit enable 0 Enable 1 Disable RMCOFF IR remote signal receiver circuit enable 0 Enable 1 Disable VBI1OFF Closed caption decoder 1 circuit enable 0 Enable 1 Disable VBIOOFF Closed caption decoder 0 circuit enable 0 Enable 1 Disable Setting the HCNTOFF RMCOFF VBIIOFF or VBIOOFF bits to 1 shuts off the system clock supply to the associated block which reduces power dissipation Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 286 Panasonic Ports I O Port Control Registers 2 Port Control Register 2 00 92 Bit 15 10 9 8 7 6 5 4 3 2 1 0 P7P8 PWM OSD CNT Test Bits OFF OFF REGE Reset 0 0 0 0
358. r what the timing of a TMnCB change the duty change does occur until the beginning of the next cycle and no signals are lost Performance is assured even when the output switches from all 1s to all Os see the double buffering section of figure 4 31 below For this reason you must always use double buffer mode for PWM waveform output Use single buffer mode only in applications that are unaffected by these issues TM4EN Write to TM4CB TM4CB 1 18 o ee t TM4BC 010111213 4011121314012 131410111213 5 4 CLRBC4 1 Double buffering TM4CB Dor 18 1 13 0 f o ol p 1 TM4CBX 54 R4 BA Interrupts Li 2 Single buffering No PWM ol intetrupt errors TM4CB 1981 toto odo too o dH S4 R4 TM4OA r 3B oi Interrupts i Li 412 Lost interrupt causing a PWM output error Figure 4 31 Single Phase PWM Output Timing with Dynamic Duty Changes Timer 4 Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 100 Panasonic Timers 16 Bit Time
359. ransfer transfer timer timer clock clock Figure 4 1 Timer Configuration Examples TM0UDIR To 16 bit timer serial I F TM1UDIR To 16 bit timer serial I F A D conversion start Bosc 4 TM2UDIR Bosc 256 TMSUDIR Bosc 512 Note Bosc 24 MHz Figure 4 2 Block Diagram of 8 Bit Timers MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 77 Panasonic Timers 8 Bit Timer Features 4 2 8 Bit Timer Features Table 4 1 8 Bit Timer Functions and Features Function Feature Timer 0 Timer 1 Timer 2 Timer 3 Interrupt request flag s TMOUDICL register TM1UDICL register TM2UDICL register TMSUDICL register TMOUDIR bit TM1UDIR bit TM2UDIR bit TM3UDIR bit Interrupt source s Timer 0 underflow Timer 1 underflow Timer 2 underflow Timer 3 underflow Interval timer function v v v Event counter function v v Clock source for 16 bit timer v v Timer output function v v TMOO signal signal Serial interface transfer clock v v source conversion trigger function v Clock sources 0 4 Bosc 4 Bosc 4 Bosc 4 1 Bosc 64 Bosc 64 Bosc 256 Bosc 256 2 Bosc 512 Cascade connection Cascade connection Cascade connection 3 TM0I signal signal Bosc 512 Bosc 512 Cascade connection v v v Note When Bosc 24 MHz Bosc 4 6 MHz Bosc 64 37
360. raphics ROM Setup Example fora Single 173 7 11 Graphics ROM in the Four Color Modes 16W x 16H 174 7 12 Graphics ROM in the Four Color Modes 16W x 18H 175 7 13 Graphics ROM Organization in 16 Color Mode 16W x 16H Tiles 176 7 14 Graphics ROM Organization in 8 Color Mode 16W x 16H Tiles 176 7 15 Graphics ROM Organization in 4 Color Mode 16W x 16H Tiles 176 7 16 Graphics ROM Organization in 2 Color Mode 16W x 16H Tiles 176 7 17 Graphics ROM Organization in 16 Color Mode 16W x 18H Tiles 177 7 18 Graphics ROM Organization in 8 Color Mode 16W x 18H 177 7 19 Graphics ROM Organization in 4 Color Mode 16W x 18H Tiles 177 7 20 Graphics ROM Organization in 2 Color Mode 16W x 18H Tiles 177 7 21 Signal Waveform d Tct TOR vebeetepequbbeque pet spese 182 7 22 OSD Signal Output Switches 183 7 23 Character Outlining Example seeria sr ina EEA ok PEEL Wee PLE Ub Rb i ERU 184 7 24 Character Shadowing 212 1 184 7 25 Box Shadowing Ex
361. re 10 2 PWM Block Diagram 10 3 PWM Data Registers registers in PWM function cannot be written by byte be word only Read by byte is possible Bits 7 to 0 of each of the seven PWM data registers PWMO to PWM6 hold the 8 bit pulsewidth modulated data to be written to the PWMs The registers reset to 0 and they set to 1 when PWM output is high PWMO PWMe PWMn Data Registers Xx 007E70 x 007E7C Bit 7 6 5 4 3 2 1 0 PWMn7 PVMn6 PWMn5 PWMn4 PWMn3 PWMn2 PWMn1 PWMn0 Reset 0 0 0 0 0 0 0 0 RW R R R R R R R R Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 250 Panasonic Ports Description 11 Ports 11 1 Description MN102H75K 85K contains 50 pins that form general purpose 1 ports Ports 0 1 2 3 4 and 5 are 8 bit ports and port 6 is a 2 bit port of these pins have alternate functions Ports 7 and 8 are only available with the quad flat package Table 11 1 1 Port Pins Port Associated Pins Port 0 07 00 Port 1 17 10 Port 2 27 20 Port 3 P37 P30 Port 4 47 40 Port 5 57 50 Port 6 61 60 Port 7 77 70 Port 8 87 80 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 251 Panasonic Ports 1 0 Port Circuit Diagrams 11 2 I O Port Circuit Diagrams 0 Pul
362. registers in the following format REGISTER Register Name x 000000 Bit 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Name Name Name Name Name Name Name Name Name Name Name Name Name Reset 0 R W R 0 R 0 R 0 oOo 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW The hexadecimal value 000000 indicates the register address top row of the register diagram holds the bit numbers Bit 15 is the most significant bit MSB The second row holds the bit or field names A dash indicates reserved bit The third row shows the reset values and the fourth row shows the accessibility R read only W write only and R W readable writable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 16 Panasonic About This Manual Related Documents Related Documents MNIO2H Series LSI User Manual Describes the core hardware MNIO2H Series Instruction Manual Describes the instruction set B MNIO2H Series C Compiler User Manual Usage Guide Describes the installation commands and options for the C compiler B MNIO2H Series C Compiler User Manual Language Description Describes the syntax for the C compiler B 2 Series C Compiler User Manual Library Reference Describes the standard
363. required for PROM and serial programming and repro Rewriting the data to the address where data has already set is forbid gramming erasing and programming Table B 7 Programming Times for PROM and Serial Writers Programming Time Reprogramming Writer User Program Only Time den DATA I O LabSite DIP48 1 YDC AF200 provisional TBA TBA lt 3 5 4 minutes Note Times indicated are minimum time requirements Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 328 Panasonic MN102H75K F75K 85K F85K LSI User s Manual Description Record of Changes Ver 1 0 to 1 1 Description of Changes Former version New version 22385 011E October 2001 1st Edition 1st Printing Latest version 22385 010E September 2001 1st Edition Sales office Definition A add D delete C modify change MN102H75K F75K 85K F85K LSI User s Manual Modified Points From MN102H75K F75K To MN102H75K F75K 85K F85K Before Modify After Modify This manual is intended for assembly language programming engineers It describes the internal configuration and hardware functions of the MN102H75K microcontrollers Using This Manual The chapters in this manual deal with the internal blocks of the MN102H75K Chapters 1 to 5 provide an overview of the MN102H75K s general specifications interrupts
364. res 06 20 ee tank uuu k ae ie da on be 78 4 3 8 Bit Timer Block 1 79 4 4 8 Bit Timer Timing suo RI RR RR RE a ag eR 81 4 5 8 Bit Timer Setup Examples sees me ree eR e er E Rr eee ERR 82 MN102H75K F75K LSI User Manual Panasonic Semiconductor Development Company 3 Panasonic Contents 4 5 1 Setting Up an Event Counter Using Timer 0 82 4 5 2 Setting Up an Interval Timer Using Timers 1 2 84 4 6 8 Bit Timer Control Registers 4 87 4 7 16 Bit Timer Description i a RR ELE ERE AREE a eR 88 4 8 16 Bit DImer Eeat tes spei e Ven detegit sea abe nt E a ge notte pue rige igne ed 89 4 9 16 Bit Timer Block Diagrams 90 4 10 16 Bit Timer Timings e oce O SAE EUR 90 4 11 16 Bit Timer Setup Examples 94 4111 Setting Up an Event Counter Using 4 94 4 11 2 Setting Up a Single Phase PWM Output Signal Using 4 96 4 11 3 Setting Up a Two Phase PWM Output Signal Using 4 101 4 11 4 Setting Up a Sin
365. ring the VS YNC cycle 7 13 1 Controlling the Shuttered Area The register settings for the two vertical shutters VSHTO and VSHT1 and the two horizontal shutters HSHTO and HSHT1 control which area of the screen is shuttered Table 7 12 shows the register settings required for this function and figure 7 31 shows four setup examples Table 7 12 Bit Settings for Controlling the Shuttered Area Function VSHTO Bit VSHT1 Bit HSHTO Bit HSHT1 Bit Description Shutter enable disable VSONO VSON1 HSONO HSON1 0 Disable shutter Acts as though there are no shutter lines 1 Enable shutter Shutter position VST00 VST10 HST00 HST10 For vertical shutters this is the number of scan VSTO9 VST19 HST09 HST19 lines from the top of the screen For horizontal shutters it is the number of pixels from the left of the screen Shuttering direction VSP0 VSP1 HSP0 5 1 0 Shutter below vertical shutters or to the right horizontal shutters 1 Shutter above vertical shutters or to the left horizontal shutters Shuttering mode control SHTRAD 0 AND the shuttered areas of all the shutters shared bit 1 OR the shuttered areas of all the shutters Determining the vertical shutter positions VSTO and VST1 The top edge of the television screen is x 000 Each integer higher brings the shutter position down one H scan line Determining the horizontal shutter positions HSTO and HST1 The left edge of the tele
366. rs 0 3 Serial I Fs TM4OA lt 2 Timers 4 5 ADC A Chip Level Timer 4 Bosc 4 24 2 REN R z s gt 4 V4 TM4CBX B Block Level Figure 4 29 Block Diagram of Single Phase PWM Output Using Timer 4 set up the output port Set the PZMD 13 12 bits of the port 2 output mode register P2MD to b 01 selecting the TM4IOA pin and set the P2DIR6 bit of the port 2 I O control register P2DIR to 1 selecting output direction This step selects the TM4OA pin P26 as the timer output port P2MD example x Oo0FFF4 Bit 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 _ P P P P P P2 P P P P P P P P2 MD14 MD13 MD12 MD10 MDs MD6 MD5 MD2 MDI Setting 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 96 Panasonic Timers 16 Bit Timer Setup Examples P2DIR example x 00FFE2 Bit 7 6 5 4 3 2 1 0 P2 P2 P2 P2 P2 P2 P2 P2 DIR7 DIR6 DIRS DIR4 DIR3 DIR2 DIRI DIRO Setting 0 1 0 0 0 0 0 0 To set up timer 4 1 Set the operating mode in the timer 4 mode register TM4MD Disable 1 timer 4 counting and interrupts Select up counti
367. rs LRB AAS LAB BB lt Y Bus busy logic Register control Arbitration logic sequence controller Clock prescaler q Figure 13 4 2 Bus Controller Block Diagram 13 3 Functional Description The bus controller contains the registers shown in table 13 3 See the page number indicated for register and bit descriptions Table 13 3 Control Registers for Clamping Circuit Register Page Address Description I2CDTRM 304 x007E40 PC transmission data register I2CDREC 305 007 42 C reception data register I2CMYAD 305 007 44 self address register I2CCLK 306 007 46 12C clock control register l2CBRST 306 007 48 I C bus reset register I2CBSTS 306 x 007E4A bus status register Arbitration and bus busy control The bus controller allows software control but implements communication timing and bus arbitration completely in the hardware Arbitration Controlled by the software but implemented completely in the hardware Bus busy Checked by the hardware This eliminates the need for the software to check whether the bus is busy The program can request a transfer to the bus at any time Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 296 Panasonic I C Bus Controller Functional Description Register settings conversions to 12 protocol The 2
368. rts MN102H75K HF75K 20 27 8 General purpose port 2 I O total 66 pins P30 P37 8 General purpose port 3 I O MN102H85K HF85K 40 47 y o 8 General purpose port 4 I O total 50 pins 50 57 8 General purpose port 5 I O 60 61 2 General purpose port 6 I O I O ports only in 70 77 8 General purpose port 7 I O MN102H75K F75K P80 P87 y o 8 General purpose port 8 I O CVBSO CBVS1 2 Composite video signal input CLH 1 level high input Closed caption decoders 2 CLL 1 level low input VREFHS 1 CCD reference voltage input VREFLS 1 reference voltage input A D converter 12 channel ADINO ADIN 1 1 12 Analog signal input DAROUT 2 1 DAC output red DAGOUT 1 1 DAC output green DABOUT 7 1 DAC output blue D A converter 1 DAYMOUT 7 1 DAC output 4 bit 4 channel IREF 1 Resistance connection for DAC bias current setting VREF 1 DAC reference voltage connection COMP 1 DAC phase compensator connection VCOI 1 Internal VCO input external LPF input PLL PDO 1 Internal phase compare output external LPF output STOP 1 STOP mode status signal Mode WDOUT 1 Watchdog timer overflow signal Test TEST 1 Test Connect to ground Notes 1 When DAROUT DAGOUT DABOUT and DAYMOUT used for digital output their names R G B and YM respectively MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development C
369. s field so that the last CRI rising edge is included The valid range is x 000 to x 7FF DATAS Data Capture Start Timing Control Register x 007E18 DATASW x 007E38 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA S S S S S S S S S S S 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 i 1 1 1 R W R R R R R RW RW RW RW RW RW RW RW RW RW RW DATAS 10 0 Start position for data capture Set this field to the same start position as that for CRI detection set in 25 The valid range is x 000 to x 7FF MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 241 Panasonic Closed Caption Decoder Closed Caption Decoder Registers DATAE Data Capture Stop Timing Control Register x 007E1A DATAEW x 007E3A Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA 10 9 8 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 R W R R R R R RW RW RW R VW RW RW RW RW DATAE 10 0 Stop position for data capture Set this value high enough to allow the last data to be captured The valid range is x 000 to x 7FF STAP Sampling Start Position Register Software Setting x
370. s repeated GPRT Specifies graphics color palette 1 or 2 0 Palette 1 1 Palette 2 GTC 8 0 Specifies the address of one of 512 graphic tiles stored in the ROM GHP Graphics Horizontal Position Control Code ID Code 11 GHSZ 1 0 Specifies the H size of the characters on the next line 00 1 dot 1 VCLK period 01 1 dot 2 VCLK periods 10 1 dot 3 periods 11 1 dot 4 VCLK periods GSHT Specifies shutter operation for the next line Setting this bit to 1 disables the shuttering function You can disable and enable shuttering on a line by line basis 0 Enable 1 Disable GHP 9 0 Specifies a VCLK indicating the horizontal start position for the next line 1024 steps are available GVP Graphics Vertical Position Control Code ID Code 11 GLAST Specifies the last line in the internal RAM graphics layer This resets the line pointer for graphic tile reads from the internal RAM to the first line 0 Disable 1 Enable GVSZ 1 0 Specifies the V size of the tiles on the next line 00 1 dot 1 H scan line 01 1 dot 2 H scan lines 10 1 dot 4 H scan lines 11 1 dot 6 H scan lines GINT Specifies an OSD interrupt 0 Disable 1 Enable GVP 9 0 Specifies an H scan line indicating the vertical start position for the next line 1024 steps are available Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 168 Panasonic 5 Display VRAM 7
371. signal Each H counter consists of a 10 bit counter and 10 bit register 14 2 Block Diagram Selected in SELR 20 00 SELR 21 01 fields of HCCNTO HCONT 1 registers I I VSYNC Selected in REDGO REDG1 bits of HCCNTO HCONT 1 registers 1024 us M U Polarity waveform ivider 4096 us 341 us signal from PWM block i Count source Polarity gt 4 HIO HI1 switch HIO for H counter 0 and Selected in SEDGO SEDGI bits Latch HI1 for H counter 1 of HCCNTO HCCNT1 registers 10 bit counter 10 bit register Data bus Figure 14 1 H Counter Block Diagram 14 3 H Counter Operation Figure 14 2 provides a schematic diagram of an example counter operation HI0rising edge count H a _ d NL C N z gt s a setting I n Note In this example HIO is active high and VSYNC is active low Figure 14 2 H Counter Operation Example 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 307 Panasonic H Counter H Counter Operation Figure 14 3 shows the input timing for the count source and reset signals Never input a count source signal in less than 245 ns tj after the reset signal input Otherwise the signal may be counted as part of the previous count cycle HIO courted on the rising edge HIO I I pH 1 I 114 gt 245 5 1
372. signal falls The 5 bit serves as the busy flag for the one shot pulse Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 118 Panasonic Timers 16 Bit Timer Setup Examples Timer 5 can output a one shot pulse Timer 5 does not operate in STOP mode when Bosc 18 off If you use an external clock it must be synchronized to Bosc Figure 4 48 shows an example timing diagram for one shot pulse output On the falling edge of TMSIB the TM5EN flag is set and counting begins at the start of the next cycle Before the count starts 5 is 0 initial TM5OA output value is 0 and the R5 reset and S5 set signals are not asserted After the count starts when it changes from 0 to 1 the S5 signal is asserted This sets the TMSOA signal high and it outputs the one shot pulse When the count reaches 3 TMSBC resets changing from 3 to 0 and the R5 signal is asserted causing the TMSOA signal to go low Because the TM5ONE bit of the TM5MD register is 1 and the TMSEN bit is reset the count stops The circuit state is now the same as it was before the TMSIB signal went low When the TMSIB signal falls again the hardware once again sets the TMSEN bit and the one shot pulse sequence repeats 5 0003 5 0001 5 0000 0001 0002 0003
373. sion 146 6 7 Multiple Channel Continuous Conversion 146 6 8 Single Channel A D 1 42 22 2 147 6 9 Timing of Software Controlled Single Channel A D 148 6 10 Multiple Channel A D Conversion 2 148 6 11 Timing of Hardware Controlled Intermittent Three Channel A D Conversion 150 6 12 Cautions on Analog to Digital 152 7 1 OSD Block Diagram or REESE Ree RN en aa RE Reg 154 7 2 Cursor Tiles in Standard and Extended 159 7 3 Graphic Tiles in Standard and Extended 160 7 4 Graphics Display Example aus ue e sep de en pee CES 162 7 5 Text Display Ex i ple aeta oer EI ERE PIS RC RR RR TR eet 164 7 6 Organization When GEXTE 0 124 4 169 7 1 Graphics VRAM Organization for Two 170 7 8 Timing for OSD Re RSA RE REL p ER eg Ee 171 7 9 ROM Organization order eRED gb abite bie Wee ea enia 172 7 10 G
374. sonic Remote Signal Receiver IR Remote Signal Receiver Control Registers The edge detection circuit samples the remote signal with fSYSCLK Set the frequency divide by ratio to meet this condition If you do not the microcontroller may interpret the data 1s and 05 incorrectly 8 4 IR Remote Signal Receiver Control Regis ters registers in block cannot be written by byte by word only Read by byte is possible Table 8 5 IR Remote Signal Receiver Registers Register Address R W Function RMTC x 007EA4 R W Remote signal frequency division control register RMIR x 007EA2 R W Remote signal interrupt control register RMIS x 007EA0 R W Remote signal interrupt status register RMLD x 007EAC R W Remote signal leader value set register RMCS x 007EA6 R Remote signal clock status register RMSR x 007EA8 Remote signal reception data shift register RMTR x 007EAA R Remote signal reception data transfer register RMTC Remote Signal Frequency Division Control Register Bit 7 6 5 4 3 2 1 0 RMTC7 RMTC6 5 RMTC4 RMTC3 RMTC2 RMTCI RMTCO Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W x 007EA4 After the program sets the divide by ratio for the frequency in the read values may be incorrect until the circuit detects the next active edge of the remote signal To identify
375. sun ETE 1 Text interrupt raphics interrupt I Graphics interrupt Line GI gt Line C1 gt 1 Text DMA Text Text Text Text interrupt display display display display Graphic display 41 Horizontal sync pulse Figure 7 30 DMA and Interrupt Timing for the OSD Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 192 Panasonic 5 Display Selecting the OSD Dot Clock 7 12 Selecting the OSD Dot Clock This section describes how to set up the OSD dot clock Selecting the clock source The source for the OSD dot clock is programmable to either the 4 MHz clock supplied through the OSC1 and OSC2 pins then multiplied by the PLL circuit to 48 MHz or a dedicated clock supplied through the OSDXI and OSDXO pins The dedicated OSDX clock can be a crystal LC oscillator or other form of 1 tation that is input through the OSDXI pin and synchronized internally to the HSYNC pulse or it can be an LC blocking oscillator synchronized to the HSYNC pulse Table 7 10 OSD Dot Clock Source Settings OSCSEL1 OSCSELO i illator pin illator Fr n x 007FO6 bit 9 x 007F06 bit Oscillator pins Oscillator type Frequency 0 0 OSC1 OS
376. syn chronous serial transfers SBO SBO 9 SBO SBO LX E SBI SBI SBI SBI S SBT sBr S S a A Simplex Connection B Full Duplex Connection Figure 5 2 Synchronous Serial Mode Connections 5 3 2 UART Mode Connections Figure 5 3 shows serial port connections for either simplex or full duplex UART transfers SBO SBO SBO SBO X SBI SBI SBI SBI 2 E E 2 o 2 2 c S S S A Simplex Connection B Full Duplex Connection Figure 5 3 UART Mode Connections 5 3 3 Mode Connection The serial interfaces can connect to C slave transmitters or receivers For this mode always pull up SBO and SBT pins to V pp Either connect a pullup resistor externally or turn on the internal one by setting the PPLU register SBO i SBT Master transmitter receiver MN102H75K Y Y Slave Slave transmitter transmitter receiver receiver Figure 5 4 Mode Connection Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 128 Panasonic Serial Interfaces UART Mode Baud Rates 5 4 UART Mode Baud Rates In UART mode the serial interface transfer clock is set to 16 times the baud rate clock The expression below is the formula for
377. synchronize with external clock Transmission bit LSB first Maximum clock speed 2 10 MHz Positive I O logic Two I O pins SBTI and SBDI pins with alternate I O port functions B 4 3 2 Serial Writer Interface Block Diagram P25 TM4IOB SBD1 RXC TXC lt P24 TMAIC SBT1 RST RST 8 bit serial interface use serial interface 1 Figure B 7 Serial Writer Interface Block Diagram When programming the memory you need not be aware of these microcontroller hardware connections However it is vital that you take these connections into account when designing your target board so that the serial writer can program the device correctly and so that SBD1 and SBTI are dedicated pins for the serial writer preventing other user circuits from communicating with the device Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User Manual 322 Panasonic MN102HF75K Flash Version Using the Onboard Serial Programming Mode B 4 4 Microcontroller Memory Map Used During Onboard Serial Programming B 4 4 1 Flash ROM Address Space Table B 4 Flash ROM Address Space in Serial Programming Mode Address Size Description x Ox80000 1KB Serial writer load program area x 0x803FF 0 80400 7 Fixed user program area 0 81 x 0x82000 8 bytes Security code 0 82007 0 82008 8 bytes Reserved area x 0x8200F
378. t you must connect it to an external lag lead filter The MN102H75K 85K contains an internal PLL circuit To use this circuit you must connect it to an external lag lead filter The most important factor in real time control is an MCU s speed in servicing interrupts The MN102H75K has an extremely fast interrupt response time due to its ability to abort instructions such as multiply or divide that require multiple clock cycles The MN102H75K re executes an aborted instruction after returning from the interrupt service routine This section describes the interrupt system in the MN102H75K The MN102H75K contains 36 interrupt group controllers Each controls a single interrupt group Because each group contains only one interrupt vector the MN102H75K can handle interrupts much quicker than pre viously possible Each interrupt group belongs to one of twelve classes which defines its interrupt priority level With the exception of reset interrupts all interrupts from timers other peripheral circuits and external pins must be registered in an interrupt group controller Once they are registered interrupt requests are sent to the CPU in accordance with the interrupt mask level 0 to 6 set in the interrupt group controller Groups 1 to 3 are dedicated to system inter rupts Table 2 1 compares the interrupt parameters of the MN102H75K to those of the MN102L35G the comparable MCU in the previous gen eration of the 16 bit series
379. t ADINO ADIN10 0100 Convert ADINO ADIN4 1011 Convert ADINO ADINI11 0101 Convert ADINO ADIN5 1100 1111 Reserved 0110 Convert ADINO ADIN6 AN1CH 3 0 Channel select for single channel conversion 0000 Convert ADINO 0111 Convert ADIN7 0001 Convert ADIN1 1000 Convert ADIN8 0010 Convert ADIN2 1001 Convert ADIN9 0011 Convert ADIN3 1010 Convert ADIN10 0100 Convert ADIN4 1011 Convert ADIN11 0101 Convert ADIN5 1100 1111 Reserved 0110 Convert ADIN6 ANEN Conversion start busy flag 0 No conversion in progress 1 Conversion in progress ANTC Conversion start at timer 1 underflow 0 Disable 1 Enable 5 Always set this bit to 0 1 0 Clock source select 00 Reserved 01 Reserved 10 Bosc 8 11 Bosc 16 ANMD 1 0 Operating mode select 00 Single channel single conversion 01 Multiple channels single conversion 10 Single channel continuous conversion 11 Multiple channels continuous conversion 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 151 Panasonic Analog to Digital Converter Cautions about Analog to Digital Converter 6 7 Cautions about Analog to Digital Converter The type of this Analog to Digital Converter is a sample hold one and so the current temporarily flows in conversion to charge the condenser of the sample hold circuit For this reasons the following settings are needed to get the accurancy of convension
380. t OSDREGE 1 or the shutters will not move PCNT2 register bit 0 Vertical shutter 0 stops x 3FF HSYNC lines from the top of the screen Figure 7 32 Shutter Movement Setup Examples 102 75 75 85 85 LSI User Manual 197 Panasonic Panasonic Semiconductor Development Company 5 Display Controlling the Shuttering Effect Do not allow the horizontal shut tering boundaries to overlap any italicized portion of a closed caption display This distorts the italicized characters 7 13 3 Controlling Shuttering Effects Through register settings you can independently control shuttering for text text background graphics and color background You can also output blanks to the shuttered area You cannot shutter the cursor layer Table 7 13 shows the register settings required for these effects There are three types of shuttering shuttering of text text background and graphics shuttering of the color background and shutter blanking The sections below describe how to control each of these Table 7 14 Bit Settings for Controlling Shuttering Effects Function Bit Name Description Text shuttering CCSHT 0 Shutter text layer characters 1 Don t shutter text layer characters Text background BCSHT 0 Shutter text layer background shuttering 1 Don t shutter text layer background Graphics shuttering GSHT 0 Shutter graphics layer 1 Don t shutter graphics layer
381. t This Manual Using This Manual About This Manual This manual is intended for assembly language programming engineers It describes the internal configuration and hardware functions of the MN102H75K and MN102H85K microcontrollers Except when discusssiing differing specifi cations this manual refers to the two microcontrollers as a single device MN102H75K 85K Using This Manual The chapters in this manual deal with the internal blocks of the MN102H75K 85K Chapters 1 to 5 provide an overview of the MN102H75K 85K s general specifications interrupts power modes timers and serial connections Chapters 6 to 10 describe the on screen display and other specialized functions available with the MN102H75K 85K Chapter 11 provides the I O port specifications chapter 12 describes the ROM correction feature chapter 13 describes the Pc interface and chapter 14 describes the H scan line counter Appendix provides a register map and Appendix B describes the flash EEPROM version Text Conventions Where applicable this manual provides special notes and warnings Helpful or supplementary comments appear in the sidebar In addition the following symbols indicate key information and warnings Key information These notes summarize key points relating to an operation Warning Please read and follow these instructions to prevent damage or reduced performance Register Conventions This manual presents 8 and 16 bit
382. t Timer Setup Examples To service the interrupts Run the interrupt service routine The routine must determine the interrupt group then clear the interrupt request flag Either the TM5IA or TMSIB signal can control the timer 5 count direction The count direction is determined at the opposite edge from the count edge at the source clock transition occurring in the middle of the count cycle Timer 5 does not operate in STOP mode when Bosc is off If you use an external clock it must be synchronized to Bosc Figure 4 51 shows an example timing chart In this example an interrupt occurs when the timer switches from down to up counting TM5CA 1FFF TM5CB 1000 TM5BC 0000 1FFD 1FFE 1FFF 0000 0001 0002 OFFF 1000 1001 IULII gt bap Td lt 4 B Interrupt Figure 4 51 External Count Direction Control Timing 5 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 122 Panasonic Timers 16 Bit Timer Setup Examples 1 Use the instruction to set this data and only use 16 bit write operations This step stops the TM5BG count and clears both TM5BG and the S R flip flop to 0 4 11 10Setting Up External Reset Control Using Timer 5 In this example t
383. t causes cycle and transition changes to occur at the beginning of the next clock cycle This prevents PWM signal losses and minimizes waveform distortion during timing changes The MN102H75K contains two general purpose serial interfaces with synchronous serial and modes The maximum baud rate in synchronous serial mode is 12 Mbps In UART mode the maximum baud rate is 375 000 bps when Bosc 24 MHz The MN102H75K 85K contains two general purpose serial interfaces with synchronous serial UART and modes The maximum baud rate in synchronous serial mode is 12 Mbps In UART mode the maxi mum baud rate is 375 000 bps when Bosc 24 MHz The MN102H75K contains an 8 bit charge redistribution A D converter ADO that can process up to 12 channels The reference clock is select able to Bosc x 1 8 or 1 16 When Bosc is 24 MHz you must set the reference clock to Bosc 8 conversion rate 4 us or higher The MN102H75K 85K contains an 8 bit charge redistribution A D con verter ADC that can process up to 12 channels The reference clock is selectable to Bosc x 1 8 or 1 16 When Bosc is 24 MHz you must set the reference clock to Bosc 8 conversion rate 4 us or higher The MN102H75K contains an on screen display OSD function com posed of three layers a text layer a graphics layer and a cursor layer You can control each layer individually which gives you great freedom in positioning displays You can also m
384. t on HEAMA leader detection 0 No request 1 Request M56BITD Interrupt request on 5 6 bit leader detection 0 Norequest Request TRAILRD Interrupt request on trailer detection 0 Norequest Request Interrupt request on 8 bit reception detection 0 Norequest Request EDGED Interrupt request on RMIN pin edge detection 0 Norequest Request 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 225 Panasonic Remote Signal Receiver IR Remote Signal Receiver Control Registers fPWM1 fSYSCLK 23 fPWMS fSYSCLK 25 fPWM5 fSYSCLK 27 fPWM6 fSYSCLK 28 and fPWM8 fSYSCLK 210 Do not set the leader value too small Leader detection and data detection may occur simultaneously RMLD Remote Signal Leader Value Set Register X 007EAC Bit 7 6 4 3 2 1 0 SP SPSLW LD3 LD2 LD0 Reset 0 0 0 0 0 1 1 0 R W R W R W R R R W R W R W R W RMLD is a 16 bit access register SP and SPSLW Switch clock frequencies 00 Filter sampling cycle fpwwe clock PWM3 01 Filter sampling cycle fpwy3 clock PWMI 10 Filter sampling cycle clock PWM3 11 Filter sampling cycle fpywys clock PWMI LD 3 0 HEAMA data leader value Set the four MSBs of the 6 bit leader value for HEAMA data in LD 3 0 This 4 bit setting must be between 0 and 60 Ts cycles The default value is x
385. t output P3DIRn P4DIRn 0 Port low output 1 Port high output 9 P3OUTn 0 P4OUTn M U ROUT GOUT BOUT YMOUT Digital output T P3INn P4INn lt DAROUT DAGOUT DABOUT DAYMOUT DAC output Figure 11 9 P35 DAROUT R P36 DAGOUT G P37 DABOUT B Port 3 and P40 DAYMOUT YM Port 4 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 260 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on lt P2PUP5 00 P25 01 SBI1 SBD1 C 10 TM4IOB P2MD10 11 Reserved P2MD11 0 Port input 00 1 Port output 10 c P2DIR5 E M 0 3 line 5 1 5 01 5 1 U PCNTO bit 11 4 2 line SBD1 SBT1 oil x SIFSEL1 0 Port low output Pin 1 Port high output LOA iru 2 5 80 U P25 L 01 SBI1 SBO1 10 SBD1 TM4IOB output P2IN5 1 0 Push pull PCNTO bit 13 1 Open drain Schmidt trigger ODASCI1 For 2 mode SB lt 0 Pullup off 1 Pullup on lt gt P2PUP6 00 25 01 SBI1 SBD1 3
386. ta 8 bits Data 8 bits B Master Receiver R W 1 _ Ack 0 Ack 1 Address Master s 7 bits R W ACK ACK Clave ACK Data 8 bits Data 8 bits MN102H51K T T Interrupt Interrupt Interrupt Master MN102H51K When the microcontroller is addressed it outputs ACK 0 and sets the AAS bit of the IPCDREC register to 1 1 signals transfer end to slave transmitter C Slave Transmitter Address i 7 bits Data 8 bits Data 8 bits P ACK ACK Y Y Interrupt Interrupt Interrupt When the microcontroller is addressed Y it outputs ACK 0 and sets the AAS bit Interrup of the 2 register to 1 STS sets to 1 D Slave Receiver Figure 13 3 2 Bus Interface Operation MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 295 Panasonic I C Bus Controller Block Diagram 13 2 Block Diagram SDA Digital filter D 14 0 Bus buffer SS P Parallel to serial ae lt lt MSB Transmission data register LSB Data bus converter B g controller Serial to parallel um E no convener Msg Reception data register 15 Address comparator SCL Digital mr filter X Address register l T T T T T Clock register m Clock f controller Control register 5 8 gt Status register MODE le
387. ta to x AA The microcontroller does not need to issue an ACK signal in this transfer so the ACK bit should be 1 3 Begin transmitting data in sync with the clock from the master 13 6 2 4Setting Up the Third Interrupt The master send an 1 signal then issues a stop condition ending the communication Data slave address ACK AOR c 0 0 0 1 0 0 1102010 1 0 10 15 0 51 0 1 0 1 O 1 MEE Esp eee oe T PLE Note areas signals output from the MN102H75K 85K Figure 13 8 Waveform for Slave Receiver Transitioning to Slave Transmitter MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 303 Panasonic Bus Controller PC Bus Interface Registers 13 7 12 Bus Interface Registers All registers in IC blook cannot be written by byte by word only Read by byte is possible I2CDTRM 2 Transmission Data Register x 007E40 Bit 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 STA STO ACK DT7 DT6 DT5 DT4 DT3 DT2 DTI DTO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R RW RW RW RW RW RW RW RW RW RW RW STA 12 start control Y STO stop control Writing to
388. tal output is selected COLBYMO is output as YM COLBBO as B COLBOO as and COLBRO as When the YS color palette is selected COLBYN3O is output as YS COLBYW S 0 YM color code COLBBJ3 0 Blue color code COLBG 3 0 Green color code COLBR S3 0 Red color code FRAME Outlining and Character Shadowing Color Register x 007FA2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FRAM FRAM FRAM FRAM FRAM FRAM FRAM FRAM FRAM FRAM YMI YMO B3 B2 0 G3 G2 Gl GO R3 R2 RI RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W w w w w w w w w w w w w w w w w This register contains the color used for text outlining and shadowing When digital output is selected FRAMEYMO is output as YM FRAMEBO as B FRAMEGO as FRAMERO as R When the YS color palette is selected FRAMEYM 3 is output as YS FRAMEYN 3 0 YM color code FRAMEBJ3 0 Blue color code FRAMEG 3 0 Green color code FRAMER 3 0 Red color code MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 213 Panasonic 5 Display OSD Registers Bit Reset R W Bit Reset R W BBSHD Black Box Shadowing Register x 007FA4 15 14 13 12 11 10 9 8 7 6 5
389. ter SCnCTR the serial transmit receive buffer SCnTRB and the serial port status register SCnS TR Table 5 3 Serial Interface Control Registers Register Address R W Description Serial I F SCOCTR x 00FD80 R W Serial port 0 control register 0 SCOTRB x 00FD82 R W Serial port 0 transmit receive buffer SCOSTR x 00FD83 Serial port 0 status register Serial I F SC1CTR x 00FD88 R W Serial port 1 control register 1 SC1TRB x 00FD8A R W Serial port 1 transmit receive buffer SC1STR x0O0FD8B R Serial port 1 status register SCOCTR SC1CTR Serial Port n Control Register x 00FD80 x 00FD88 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCn SCn SCn SCn SCn m SCn SCn SCn SCn SCn SCn SCn En SCn SCn TEN REN BRE PTL OD ICM LN 2 SB 51 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW R RW RW SCOCTR controls the operating conditions for the serial interface includ ing the clock source the parity bit the protocol and transmit receive enabling SCnTEN Serial port n transmit enable 0 Disable 1 Enable SCnREN Serial port n receive enable 0 Disable 1 Enable SCnBRE Serial port n break transmission 0 Don t break 1 Break Force SBOn to 0 SCnllC Serial port n 2 start stop sequence output Do not this
390. the STA and STO bits allows you to change the state of the SCL is held low during interrupt transmission or reception operation Table 13 6 shows the settings for dif servicing and is cleared high by ferent start and stop conditions a write to 2 Table 13 6 STA and STO Settings STA STO Mode Function Description 0 0 All state change 1 1 All NOP No state change 1 0 Slave receiver Start Change to mode indicated by R W bit Master transmitter start R W 0 Change to master transmitter R W 1 Change to master receiver 0 1 Slave receiver Stop read Change to slave receiver after stop Master transmitter Stop write condition ACK Acknowledge signal output control The acknowledge signal is output after every byte transfer on the ninth clock pulse is normally 1 and transitions to 0 to output an acknowl edge for instance if the master or slave receiver has received a data byte DT 7 0 Data to be transmitted The parallel data in this field is converted to serial data for transmission to the C bus It is shifted MSB first to the interface Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 304 Panasonic 2 Bus Controller Bus Interface Registers I2CDREC 2 Reception Data Register x 007E42 Bit 15 14 13 12 11
391. the User 327 B 4 7 1 Branching to the Reset Start 327 B 4 7 2 Branching to the Interrupt Start Routine 327 B 5 Reprogramming FIOW sie SiN ke ea er he ca by ee Reg 328 B 6 Programming TIMES u 20022226 etd eee dete E eve od ack dt eda erede 328 Panasonic Semiconductor Development Company MN102H75K F75K LSI User Manual Panasonic List of Tables List of Tables 1 1 General Specifications s seis V EE EROR ERR E REN LER ER rd 26 1 2 Block Diagram Explanation 2 2 2 29 1 3 Pin F nctions o bp R ECKE eg e ARR RR RE t Ge 32 1 4 Wait Count Settings u ie Ae vee ee Se SPUR th ata E eee ees 36 2 1 Comparison of MN102H75K and MN102L35G Interrupt 37 2 2 Handler Preprocessing uu s puhu espe Pede eU viv RUE Qu rap det queue 39 2 3 Handler POStproCessIng n ies ee Oe Ree RAT ah RES RE de See A ee HUGE 39 2 4 Interrupt Control Registers sasana e 46 3 1 Peripheral Function On Off Switches 75 3 2 CPU Mode Bit Settings zii uia e ERRARE
392. the a 16 dots 16 dots right output a space to the right e of the text BSHAD0 0 2 8 5 BSHAD0 1 gt Box shadowing black Box shadowing white Specify the color in BBSHD x 7FA4 Specify the color in WBSHD x 7FA6 Figure 7 25 Box Shadowing Example MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 185 Panasonic 5 Display Setting Up the OSD Italicizing In closed caption mode writing a 1 to bit 10 ITALIC of the COL setting in the VRAM italicizes all characters following that COL Figure 7 26 shows an example of an italicized character Underlining In closed caption mode writing a 1 to bit 11 CUNDL of the COL setting in the VRAM underlines all characters following that COL Figure 7 26 shows an example of an underlined character 4 5 2 Italics 5 o e N Y Caption mode Figure 7 26 Italicizing and Underlining Example B Blinking In both normal and closed caption modes writing a 1 to bit 8 BLINK of the COL setting in the VRAM causes all characters following that COL to blink To use this function you must enable blinking by writing a 1 to bit 5 BLINK of the OSD3 register x 007FOA In closed caption mode you can specify whether or not the underli
393. the clock source as Bosc 4 by writing b 00 to TMOS 1 0 Do not change the clock source once you select it Selecting the TMOMD example x 00FE20 clock source while you set up Bit 7 6 5 4 3 2 1 0 the count operation control will THO TMG mo rata corrupt the value in the binary EN LD S1 SO counter Setting 0 1 0 0 0 0 0 0 In the bank and linear address 4 Set TMOLD to 0 and TMOEN to 1 This starts the timer Counting begins at ing versions of the MN102 series it was necessary to set TMOEN and TMOLD to 0 between steps 3 and 4 to underflow interrupt request is sent to the CPU ensure stable operation This is unnecessary in the high speed linear addressing version the start of the next cycle When the binary counter reaches 0 and loads the value x 01 from the base register in preparation for the next count a timer 0 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 102 Panasonic Timers 16 Bit Timer Setup Examples To set up timer 4 1 Setthe operating mode in the timer 4 mode register TM4MD Disable 1 timer 4 counting interrupts Select up counting Select timer 0 under flows clock source Use the MOV instruction for this setup and only use 16 bit write TMAND example x 00FE80 operations Bit 15 14 13012010 10 9 8 7 6 5 4 3 2 1 0 4 4 TM4 4 4 4 4 4 4 4
394. the microcontroller program in an existing product B 3 Using the PROM Writer Mode In this mode the MN102HF75K allows a PROM writer to program the internal flash memory as if it was a standalone memory chip The microcontroller is inserted into a dedicated adaptor socket which con nects to DATA I O s LabSite PROM writer When the microcontroller connects to the adaptor socket it automatically enters PROM writer mode The adaptor socket ties the microcontroller pin states to PROM writer mode and programming occurs without any reference to the microcontroller pin states Third party PROM writer MN102HF75K Adaptor socket for 102 75 Device MN102HF75KBF lt MN102HF75KBF Nso2HFBSKDR 102 75 75 85 85 LSI User Manual 5 Panasonic Panasonic Semiconductor Development Company MN102H75K F75K 85K F85K LSI User s Manual October 2001 Ist Edition 1st Printing Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd Semiconductor Company Matsushita Electric Industrial Co Ltd Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http www panasonic co jp semicon SALES OFFICES NORTH AMERICA U S A Sales Office Panasonic Industrial Company PIC New Jersey Office Two Panasonic Way Secaucus New Jersey 07094 U S
395. the remote signal the IR signal receiver generates a sampling clock Ts by dividing the PWM3 pulse by the value set in 7 0 fpwM3 15 divided by 25 375 kHz 2 7 us with a 4 MHz oscilla tor The Ts cycle is the contents of RMTC 1 so load a value from 1 to 255 for a division ratio from 2 to 256 The microcontroller reads the value in the frequency division counter as a ones complement number each digit is complemented Set the RMTC value so that Ts T 2 where T is the pulse width of the remote input signal Table 8 6 shows how to define T for the different formats Table 8 6 HEAMA and 5 6 Bit Data Pulse Widths H L HEAMA formar Data 0 tLe 1 T 3T Data 0 2T 2T 5 6 bit format Data 1 2T 6T RMTC is an 8 or 16 bit access register MN102H75K F75K 85K F85K LSI User Manual 223 Panasonic Panasonic Semiconductor Development Company Remote Signal Receiver IR Remote Signal Receiver Control Registers All registers in RMC block cannot be written by byte by word only Read by byte 1s possible RMIR Remote Signal Interrupt Control Register x 007EA2 Bit 7 6 5 4 3 2 1 0 MOD MOD FILTR POL LEADER TRAILR DAT8 AUTO SEL E SEL E E E E Reset 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W RMIR controls the operating modes and interrupt operations for the receiver circuit It is
396. ti Layer Format a id aV as eR RU Cont CENE bed vei 156 7 5 4 Output Pin Set p ck I See eee TERCER e RE ERES un as FATUR Ue 157 7 5 5 Microcontroller Interface isse ae Re eR ER EQ C RE 157 7 5 6 VRAM bp sie eie e eee 157 7 57 Conditions for Writes 158 7 6 Standard and Extended Display 159 7 6 1 Cursor Layer Display 1 159 7 6 2 Graphics Layer Display 160 77 Display Setup Examples us repre oo eee Sh bee Meech Ame Laas 161 7 7 1 Setting Up the Graphics 161 7 1 2 Setting Up the Text Layer i eee en ex hoe bea GE bes 163 7 8 ere REVERSUS VoU Ee de PT st us 165 7 8 1 VRAM Operation PRESE RO EDU A eau d mS ungues 165 7 8 2 VRAM Organization e e p OR RO RASS RR P RR REOR 169 7 8 3 Cautions about the number of display code set to 171 7 9 ROM uapa OEC E AE een 172 7 9 1 ROM Organiz tion 630 pes pct a ese YG SIA CERERI RE ERE 172 7 9 2 Graphics ROM Organization in Different Color Modes
397. tings SHP GHP and CHP determine where the left side of cursor graphics and text lines start on the screen You can set this value for all of the layers in 1 pixel units MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 189 Panasonic On Screen Display Setting Up the OSD set up the vertical position Cursor Write the vertical position of the cursor to the SVP 9 0 field x 007F14 Valid range x 3F0 no of scan lines gt SHP gt x 03 Graphics a Write the vertical position of the first line in the display to the GIVP 9 0 field x 007F18 When you write new values to the GIVP and CIVP fields the T Write the position of the second and all following lines in the GVP 9 0 settings take effect on the next field of the graphics display RAM data for the preceding line VSYNC pulse This means that changes are reflected in the next Valid range x 3F0 no of H scan lines GIVP GVP gt x 03 display screen rather than the current one Text Write the vertical position of the first line in the display to the CIVP 9 0 field x 007F1C Write the position of the second and all following lines in the CVP 9 0 field of the text display RAM data for the preceding line Valid ranges x 3F0 no of scan lines gt CIVP CVP gt x 03 VP range calculation example The base graphics line height is 16 dots or H scan lin
398. to x 3FF RAMEND Text and Graphics RAM End Address Register Bit 15 14 13 12 11 10 9 8 7 6 2 4 3 2 1 0 GRAM CRAM CRAM CRAM CRAM CRAM END END END END END END END END END END END END END END END END 11 10 9 8 7 6 5 4 AIO A9 8 7 5 4 0 oO 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW x 007F04 Reset 0 0 0 0 0 GRAMENDA 11 4 holds the programmable portion of the graphics RAM end address and CRAMENDA 11 4 holds the programmable portion of the text RAM end address The low order 4 bits of the address are always and the high order 4 bits are always x 9 The available address range 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 203 Panasonic 5 Display OSD Registers is x 900F to x OFFF with a programmable range from x 00 to x FF A11 A4 1001 XXXX XXXX 1111 Fixed Programmable Fixed x 900F 1001 0000 000011111 x 9FFF 100111111 111111111 5 0 Cursor Tile Code Register 0 x 007F10 Bit 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 SPRTO 5 08 STCO7 STCO6 STCOS STC04 STCO3 STC02 STC01 STC00
399. tor Development Company 43 Panasonic Interrupts Interrupt Control Registers 2 3 Interrupt Control Registers A control register is assigned to each interrupt vector group Except for the class 0 registers WDICR PIICR and EIICR the control registers allow you to enable and set the priority level for interrupt groups Below is the general format of the registers in class 0 and classes 1 to 11 Class 0 X WD watchdog overflow interrupts PI undefined instruction interrupts EI interrupt error interrupts XICR System Interrupt Bit 7 6 5 4 3 2 1 0 ID Interrupt detect flag 0 Interrupt undetected Interrupt detected Classes 1 11 X IQ external interrupts TM timer interrupts SC serial interrupts I2C I2C interrupts OSD OSD interrupts AN A D conversion end interrupts RMC remote signal receive interrupts VBI VBI interrupts ADM address match interrupts XnICH System Interrupt Bit 7 6 5 4 3 2 1 0 Lv2 Lvl Lvo IE LV 2 0 Interrupt priority level Sets the priority from 0 to 6 000 0 001 1 etc When LV 7 inter rupts are not serviced Note that some registers do not contain the LV field In this case these bits always read 0 IE Interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 44 Panasoni
400. trol Register Low x 00FC80 Bit 7 6 5 4 3 2 1 0 ANID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R ANICL detects and requests A D conversion end interrupts It is an 8 bit access register Use the MOVB instruction to access it ANIR A D conversion end interrupt request flag 0 No interrupt requested Interrupt requested ANID A D conversion end interrupt detect flag 0 Interrupt undetected Interrupt detected ANICH A D Conversion End Interrupt Control Register High x 00FC81 Bit 7 6 5 4 3 2 1 0 ANLV2 ANLV0 ANIE Reset 0 0 0 0 0 0 0 0 R W R R W R W R W R R R R W ANICH sets the priority level for and enables A D conversion end inter rupts It is an 8 bit access register Use the MOVB instruction to access it ANLV 2 0 A D conversion end interrupt priority level Sets the priority from 0 to 6 ANIE A D conversion end interrupt enable flag 0 Disable 1 Enable Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 64 Panasonic Interrupts Interrupt Control Registers SCTOICL Serial 0 Transmission End Interrupt Control Register Low x 00FC82 Bit 7 6 5 4 3 2 1 0 SCTO SCTO z lt 7 Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R SCTOICL detects and requests serial 0 transmission end interrupts It is an 8 bit ac
401. truction to access it The priority level for address match 1 interrupts is written to the ADM3LV 2 0 field of the ADM3ICH register Address match 1 interrupt enable flag 0 Disable 1 Enable ADMOICL Address 0 Match Interrupt Control Register Low x 00FC7E Bit 7 6 5 4 3 2 1 0 e ADMO _ ADMO IR ID Reset 0 0 0 0 0 0 R W R R R R W R R R R ADMOICL detects and requests address match 0 interrupts It is an 8 bit access register Use the MOVB instruction to access it ADMOIR Address match 0 interrupt request flag 0 No interrupt requested Interrupt requested ADMOID Address match 0 interrupt detect flag 0 Interrupt undetected 1 Interrupt detected 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Company 63 Panasonic Interrupts Interrupt Control Registers ADMOICH Address 0 Match Interrupt Control Register High x 00FC7F Bit 7 6 5 4 3 2 1 0 ADM0 IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W ADMOICH enables address match 0 interrupts It is 8 bit access regis ter Use the MOVB instruction to access it The priority level for address match 0 interrupts is written to the ADM3LV 2 0 field of the ADM3ICH register ADMOIE Address match 0 interrupt enable flag 0 Disable 1 Enable ANICL A D Conversion End Interrupt Con
402. ts bit 12 of color palette RGBC x007F06 bit 0 0 Analog R G B output 1 Digital R G B output outputs bits 0 R 4 G and 8 B of color palette Table 7 9 summarizes the controls for RGM YM and YS output Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 180 Panasonic 5 Display Setting Up the OSD Table 7 9 RGB YM and YS Output Control Settings Waveform in YSPLT PRYM TPRT TRPTF RGB YM YS figure 7 21 0 0 0 0 Color palettes 0 and F Color palettes 0 and F Color palettes 0 and F output low output low output low 0 0 0 1 Color 0 output low Color palette 0 output low Color palette 0 output low Q 0 0 1 0 Color palette F output low Color palette F output low Color palette F output low 0 0 1 1 0 1 0 0 Color palettes 0 F Color palettes 0 and F Color palettes 0 and F output low output low output low when YM low 0 1 0 1 Color palette 0 output low Color palette 0 output low Color palettes 0 output low when YM z low 0 1 1 0 Color palette F output low Color palette F output low Color palettes F output low when z low 0 1 1 1 Output low when z low 1 0 0 0 Reserved 1 0 0 1 Reserved 1 0 1 0 Reserved output 1 0 1 1 1 1 0 0 Reserved ES 1 1 0 1 Reserved 1 1 1 0 Reserved
403. tting 0 1 0 1 1 1 1 1 TM2BR example x 00FE12 Bit i 6 5 4 3 2 1 0 TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 BR7 BR6 BR5 BR4 BR3 BR2 BRI BRO Setting 1 1 1 0 1 0 1 0 4 Set the TMILD bit of the TMIMD register and theTM2LD bit of the 1 TM2MD register to 1 This loads value the base register to binary counter At the same time select the clock source as the BOSC A for timer 1 Do not change the clock source and cascade to timer 1 for timer 2 Write to TMnS 1 0 once you select it Selecting the clock source while you set up TM1MD example x 00FE21 the count operation control will Bit 7 6 5 4 3 2 1 0 corrupt the value in the binary TMI TMI TMI counter EN LD 51 50 Setting 0 1 0 0 0 0 0 0 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 85 Panasonic Timers 6 Bit Timer Setup Examples In the bank and linear address ing versions of the MN102 series it was necessary to set TMOEN and TMOLD to 0 between steps 4 and 5 to ensure stable operation This is unnecessary in the high speed linear addressing version Access TM2MD and TM1MD with a 16 bit write using the MOV instruction or set the two registers consecutively begin ning with TM2MD Bit Setting TM2MD example 7 6 5 4 3 1 0 TM2 TM2 TM2 TM2 EN LD 51 50 0 1 0
404. upt Control Register Low x 00FC9C Bit 7 6 5 4 3 2 1 0 Dc Dc zm E g ID Reset 0 0 0 0 0 0 0 0 R W R R R R W R R R R I2CICL detects and requests PC interrupts It is an 8 bit access register Use the MOVB instruction to access it 2 interrupt request flag 0 No interrupt requested 1 Interrupt requested I2CID 2 interrupt detect flag 0 Interrupt undetected 1 Interrupt detected I2CICH 2 Interrupt Control Register High x 00FC9D Bit 7 6 5 4 3 2 1 0 Dc IE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R W I2CICH enables interrupts It is an 8 bit access register Use the MOVB instruction to access it The priority level for Pc interrupts is written to the SCTILV 2 0 field of the SCTIICH register I2CIE 2 interrupt enable flag 0 Disable 1 Enable MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 71 Panasonic Low Power Modes CPU Modes 3 Low Power Modes You cannot enter STOP mode from NORMAL mode The MN102H75K 85K provides two ways to reduce power consumption con trolling CPU operating and standby modes to cut overall consumption and shutting down unused functions by stopping the system clock supplied to them 3 1 CPU Modes 3 1 1 Description The MN102H75K 85K has two CPU operating modes NORMAL and SLOW and two CPU standby modes HALT and STOP Effective use of these mod
405. upt response MN102H series devices can stop executing instructions even those with long execution cycles to service interrupts immediately After an interrupt occurs the program branches to the interrupt service routine within six cycles or less The architecture also includes a programmable interrupt handler which allows you to adjust interrupt servicing speed within the software when necessary improving real time control performance Main Program Instruction 1 Interrupt Request Instruction 2 Instruction 3 Instruction 4 Figure 1 3 MN102H Series Interrupt Servicing Interrupt Service Routine Flexible interrupt control structure The interrupt controller supports a maximum of 64 interrupt vectors Vectors 0 to 3 are nonmaskable interrupts Groups of up to four vectors are assigned to classes and each class can be set to one of seven priority levels This gives the software designer great flexibility and fine control The core is also backwards compatible with software from previous Panasonic peripheral modules B High speed high functionality external interface The MN102H series provides DMA handshaking bus arbitration and other functions that ensure a fast efficient Interface with other devices Optimal C Language development environment The MN102H series combines hardware optimized for C language pro gramming with a highly efficient C compiler resulting in assembly codes the same size as that
406. upts 2 1 Description The most important factor in real time control is an MCU s speed in servicing interrupts The MN102H75K 85K has an extremely fast interrupt response time due to its ability to abort instructions such as multiply or divide that require multiple clock cycles The MN102H75K 85K re executes an aborted instruction after returning from the interrupt service routine This section describes the interrupt system in the MN102H75K 85K The MN102H75K 85K contains 36 interrupt group controllers Each controls a single interrupt group Because each group contains only one interrupt vector the MN102H75K 85K can handle interrupts much quicker than previously possible Each interrupt group belongs to one of twelve classes which defines its interrupt priority level With the exception of reset interrupts all interrupts from timers other peripheral circuits and external pins must be registered in an interrupt group controller Once they are registered interrupt requests are sent to the CPU in accordance with the interrupt mask level 0 to 6 set in the interrupt group controller Groups 1 to 3 are dedicated to system interrupts Table 2 1 compares the interrupt parameters of the MN102H75K 85K to those of the MN102L35G the com parable MCU in the previous generation of the 16 bit series Table 2 1 Comparison of MN102H75K 85K and MN102L35G Interrupt Features Parameter MN102L35G MN102H75K 85K Interrupt groups 4 vectors p
407. urope GmbH PIEG Hans Pinsel Strasse 2 85540 Haar GERMANY Tel 49 89 46159 119 49 89 46159 195 ASIA e Singapore Sales Office Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 The Concourse Singapore 199555 THE REPUBLIC OF SINGAPORE Tel 65 390 3688 Fax 65 390 3689 e Malaysia Sales Office Panasonic Industrial Company M Sdn Bhd Head Office Tingkat 16B Menara PKNS Petaling Jaya No 17 Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan MALAYSIA Tel 60 3 7951 6601 60 3 7954 5968 Fax 52 3 671 1256 Matsushita Electric Industrial Co Ltd 2001 Penang Office Suite 20 07 20th Floor MWE Plaza No 8 Lebuh Farquhar 10200 Penang Malaysia Tel 60 4 201 5113 Fax 60 4 261 9989 Johore Sales Office Menara Pelangi Suite8 3A Level8 No 2 Jalan Kuning Taman Pelangi 80400 Johor Bahru Johor MALAYSIA Tel 60 7 331 3822 Fax 60 7 355 3996 Oe Thailand Sales Office Panasonic Industrial THAILAND Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st FI Rachadaphisek Rd Huaykwang Bangkok 10320 THAILAND Tel 66 2 693 3428 Fax 66 2 693 3422 Philippines Sales Office PISP Panasonic Indsutrial Sales Philippines Division of Matsushita Electric Philippines Corporation 102 Laguna Boulevard Bo Don Jose Laguna Technopark Santa Rosa Laguna 4026 PHILIPPINES Tel 63 2 520 8615 Fax 63 2 520 8629 lndia Sales Office National Panasonic India Ltd NPI E Block 5
408. ut Using 4 96 4 30 Single Phase PWM Output Timing Timer 4 1 99 4 31 Single Phase PWM Output Timing with Dynamic Duty Changes Timer 4 100 4 32 Block Diagram of Two Phase PWM Output Using 4 101 4 33 Two Phase PWM Output Timing Timer 4 104 4 34 Two Phase PWM Output Timing with Dynamic Duty Changes Timer 4 105 4 35 Block Diagram of Single Phase Capture Input Using 4 106 4 36 Single Phase Capture Input Timing Timer 4 2 107 4 37 Block Diagram of Two Phase Capture Input Using 4 108 4 38 Two Phase Capture Input Timing Timer 4 110 4 39 Block Diagram of 4x Two Phase Capture Input Using 5 111 4 40 Configuration Example 1 of 4x Two Phase Capture Input Using 5 111 4 41 Configuration Example 2 of 4x Two Phase Capture Input Using 5 111 4 42 4x Two Phase Encoder Input Timing Timer 5 113 4 43 Block Diagram of 1x Two Phase Capture Input Using 5 114 4 44 C
409. ver RXC RXD SBI VV Figure 5 1 Serial Interface Configuration Example 5 2 Features Table 5 1 Serial Interface Functions and Features bit only Clock source 1 2 of timer 0 underflow 1 8 of timer 0 or 1 underflow External clock 1 8 of timer 0 or 1 underflow Maximum baud rate 12 Mbps when Bosc 24 MHz 375 000 bps when Bosc 24 MHz Error detection Parity error Overrun error Parity error Overrun error Framing error Buffers Independent transmit receive buffers single transmit buffer double receive buffers Interrupts Transmission or reception complete interrupts Function Feature Synchronous Serial Mode UART Mode 2 Mode Parity None 0 1 even or odd Can be master trans Character length 7 bit or 8 bit mitter or receiver No Transfer bit order LSB or MSB first programmable 8 LSB first detection start sequence MNI02H75K F75K 85K F85K LSI User Manual 127 Panasonic Panasonic Semiconductor Development Company Serial Interfaces Connecting the Serial Interfaces See section 11 I O Ports for details on setting up the SBT port 5 3 Connecting the Serial Interfaces Figures 5 2 5 3 and 5 4 illustrate six different methods of connecting the serial interface 5 3 1 Synchronous Serial Mode Connections Figure 5 2 shows serial port connections for either simplex or full duplex
410. vision screen is x 000 Each integer higher brings the shutter position right one pixel One pixel or one dot is the smallest display unit in the OSD Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 194 Panasonic 5 Display Controlling the Shuttering Effect Television screen HSHT1 Television screen HSHT0 HSHT1 HSHT1 Television screen VSONO VSON1 1 V shutters 0 and 1 on HSONO 5 1 1 H shutters 0 and 1 on VSP0 0 V shutter 0 shutters below VSHTO VSP1 1 V shutter 1 shutters above HSPO 0 shutter 0 shutters to the right 1 shutter 1 shutters to the left SHTRAD 0 All shutters ANDed VSHT1 Shuttered region VSONO VSON1 1 V shutters 0 and 1 on HSONO HSON1 1 shutters 0 and 1 on VSPO 0 V shutter 0 shutters below VSP1 1 V shutter 1 shutters above HSPO 0 H shutter 0 shutters to the right 1 shutter 1 shutters to the left SHTRAD 1 All shutters ORed VSHTO VSHT1 VSONO VSON1 1 V shutters 0 and 1 on HSONO HSON1 1 H shutters 0 and 1 on VSPO 1 V shutter 0 shutters above VSP1 0 V shutter 1 shutters below HSPO 1 H shutter 0 shutters to the left 0 shutter 1 shutters to the right SHTRAD 1 All shutters ORed VSHT1 VSONO 0 V shutter 0 off VSON1 1 V shutter 1 on HSONO HSON1 1 H shutters 0 and 1 on VSPO
411. w output Pin 1 Port high output 0 lt gt POOUT2 9 P02 U SCL1 x SCL output er POIN2 lt Gl Schmidt trigger SCL input gt I2CSEL1 lt gt e I2CSELO 0 Pullup off 1 Pullup on c P6PUP1 0 P61 1 SCLO gt P6MD1 0 Port input 1 Port output c P6DIR1 JJ 0 Port low output Pin 1 Port high output 0 lt gt P6OUT1 M P61 U SCL0 X 777 P6IN1 lt I Schmidt trigger Figure 11 13 P02 SCL1 Port 0 and P61 SCLO Port 6 Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 264 Panasonic Ports 1 0 Port Circuit Diagrams 0 Pullup off 1 Pullup on c POPUP1 0 PO1 1 SDA1 c POMD1 ee 0 Port input 1 Port output c PODIR1 E 0 Port low outpu Pin 1 Port high output 0 c e POOUT1 M P01 IH 5 SDA1 x SDA output 1 e POIN1 lt I Schmidt trigger SDA input e gt I CSEL1 lt gt e 120580 4
412. wa Digital Computer Co Ltd Microcontroller System Joint Headquarters Equipment Business Center Keio Fuchu 1 chome Building 7F 1 9 Fuchu cho Fuchu shi Tokyo Japan Model AF200 flash microcontroller programmer Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 320 Panasonic MN102HF75K Flash Version Using the Onboard Serial Programming Mode B 4 2 Circuit Requirements for the Target Board Target board Vpp 5 V Vpp for level detection DD x 10 9 e Serial m D UST Ue writer SET gt SBT1 MCU G D SED 4 gt SBD1 External GND power source 3 0V 33V a GND Figure B 6 Target Board Serial Writer Connection Table B 3 Pin Descriptions for Target Board Serial Writer Connection Pin Name Description Vpp 5 V power supply Vpp 3 0 3 3 external power supply Vpp for level detection Vpp level detection pin for target board RST Reset SBT Serial interface clock supply SBD Serial interface data supply GND Ground Note 1 During normal microcontroller operation Vpp should always be equal to Vpp 3 3 0 3 V Apply 5 V to the Vpp supply only when programming the flash memory During programming the serial writer supplies Vpp to the microcontroller Install a switch on the target board to toggle bet
413. ween V pp supplied by the serial writer and Vpp for normal operation Inserial programing a large scale of current flows through Vpp See to it that 5V is supplied to Vpp by checking the connection and reducing the impedance of switches You must supply a Vpp source of 3 0 V 3 3 V externally Vpp for level detection informs the serial writer of the actual Vpp level of the target board If the Vpp level is too low the serial writer generates an error message Connect pullup resistors on the target board to the RST SBT and SBD pins Use a pullup resistor value of 10 10 Install a switch on the target board to toggle between RST for serial programming and RST for normal operation Alternatively install a wired OR connection For a wired OR connection disable RST for normal operation during serial programming RST SBT and SBD are output from the serial writer through an open nection MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 321 Panasonic 102 5 Flash Version Using the Onboard Serial Programming Mode B 4 3 Microcontroller Hardware Used in Onboard Serial Pro gramming B 4 3 1 Serial Writer Interface Description The microcontroller contains the following interface hardware for serial pro gramming of the flash ROM One 8 bit serial interface use serial interface 1 Data transmission and reception
414. x Bits 3 to 0 of the RMIR register control the interrupt vectors individually A 0 disables the interrupt vector and a 1 enables it A remote signal interrupt sets the RMCIR flag of the RMCICL interrupt register 00 76 MNI02H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 221 Panasonic Remote Signal Receiver IR Remote Signal Receiver Operation 8 3 6 Controlling the SLOW Mode Use bit 7 SP in the RMLD reg The MN102H series microcontrollers have two operating modes NORMAL and ister to toggle thenoise filter SLOW See section 3 1 CPU Modes on page 72 In SLOW mode sampling frequency between PWM6 PWM8 and PWM3 2 MHz which affects the frequencies of the PWM3 clock and noise filter PWM5 sampling PWM6 PWM8 Use the SPSLW bit bit 6 of the RMLD register to change which clocks and noise filter sampling that you use Table 8 4 Differences between SLOW and NORMAL Modes SPSLW Normal Mode SLOW Mode f 12 MHz f 2 MHz RMLD bit 6 Noise filter sampling Clock Noise filter sampling Clock 0 PWM6 PWM8 PWM3 PWM6 PWM8 PWM3 21 3 85 5us 2 7us 128 us 512 us 16 us 1 PWM3 PWM5 PWM1 PWM3 PWM5 PWM1 2 7 us 10 7 us 0 67 us 16 us 64 us 4 0 lt Panasonic Semiconductor Development Company 102 75 75 85 85 LSI User Manual 222 Pana
415. xtension mode Figure 1 15 provides the memory space for the MCU in this mode External Expansion Mod x 000000 c External devices 008000 i Internal RAM x00AO00 8192 bytes x 00FC00 Peripheral registers x 010000 External devices External memory space 0 CS0 signal notera 2090000 a IR remote signal receive Internal masked ROM 256 Kbytes 7 OSD 5 CCD0 x 0C0000 CCD1 x 200000 PWM 400000 External devices __ External memory space 1 x 800000 CS1 signal L External memory space 2 _ cannot be accessed x C00000 CS2 signal __ External memory space CS3 signal XFFFFFF Expandable up to 16 MB gt jJ MN102H75K 256 Kbytes xocoooo 8192 bytes xooAo00 Figure 1 15 Memory Space External Extension Mode MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 35 Panasonic General Description Bus Interface 1 7 2 Bus Interface Control Registers The external memory wait register EXWMD and memory mode register 1 control the bus interface EXWMD External Memory Wait Register x O0FF80 Bi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 id 0 EW 33 EW 32 EW 31 EW 30 EW 23 EW 22 EW 21 EW 20 EW 13 EW 12 EW 11 EW 10 EW 03 EW 02 EW 01 EW 00
416. xxICR SCCTRn TRXBUFn SCSTRn ANCTR ANnBUF TMn BCn BRn MEMMD PnOUT PnIN PnDIR Note 1 on the product The program counter specifies the 24 bit address of the program instruction being executed The four address registers specify the location of the data in the memory A3 is assigned as the stack pointer The four data registers handle all arithmetic and logic operations When byte length 8 bit or word length 16 bit data is to be transferred to memory or to another register an instruction adds a zero or sign extension The dedicated multiplication division register stores the high order 16 bits of the 32 bit product of multiplication operations In division operations before execution it stores the high order 16 bits of the 32 bit dividend and after execution it stores the 16 bit remainder of the quotient Memory ROM and RAM special function registers for controlling peripheral functions and I O ports can all be assigned to the same address space Internal control registers Interrupt control registers Serial interface registers A D converter registers Timer counter registers Memory control registers port registers This allocation is a representative example Actual memory peripheral SFR and I O port configuration depends Figure 1 4 Internal Registers Memory and Special Function Registers 102 75 75 85 85 LSI User Manual Panasonic Semiconductor Development Comp
417. y of 1 To _ 2 2 2 n output 0 signal select SCLN 1 protocol SCOPTL 1 I C mode SC0ICM 1 and MSB a fixed parity of 0 Select a parity first bit order SC0OD 1 Enable both transmission and reception SCOTEN of none if there is no ACK signal and SCOREN 1 and disable transmission breaks 5 0 Select the timer 0 underflow rate divided by 8 as the clock source SC0CTR example x 00FD80 Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 SCO Sco Sco Sco Sco Sco SCO SCO 5 Sco Sco Sco EN Sco Sco TEN REN BRE DCS PTL OD DCM LN 2 SB 51 50 Setting 1 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 To set up the start sequence Reception must be enabled for Write a 1 to the SCOIIC bit of the SCOCTR register to signal the start sequence ihecireuht to derecta start SBOO output immediately goes low Read SCOSTR to verify that the start sequence occurred correctly SC0IST 1 At this point even if another start exists on the bus an arbitration lost will not be detected Totransmit the first data byte 1 Load the data to the serial port 0 transmit receive buffer which initiates data output The SBOO pin begins data output to the C bus when the SBTO clock signal goes low with a 1 8 clock cycle delay 2 After transmission both the SBOO and SBTO signals stay low To transmit a second data
418. y reading SCnTRB SCnTRB has two respec tive buffers for transmission and for reception The buffers for reception is consist of two buffers and the received data is set to SCnTRB after the reception ends and held until that of the next data ends Over run error occurs if SCnTRB is not read before the reception of the next data ends See 5 5 When the received data is set to SCnTRB reception end interrupt occurs and SCnRXA flag of SCnTRB register is set to 1 During 7 bit transfers the most significant bit bit 7 of SCnTRB is always 0 The reset value of SCOTRB is undefined MN102H75K F75K 85K F85K LSI User Manual Panasonic Semiconductor Development Company 141 Panasonic Serial Interfaces Serial Interface Control Registers SCOSTR SC1STR Serial Port n Status Register x 00FD83 x 00FD8B Bit 7 6 5 4 3 2 1 0 SCn SCn SCn SCn SCn SCn SCn SCn TBY RBY ISP RXA IST FE PE OE Reset 0 0 0 0 0 0 0 0 R W R R R R R R R R SCnSTR contains the error detection and status flags for the serial inter faces SCnTBY Serial port n transmission busy flag 0 OK to transmit 1 Transmission in progress SCnRBY Serial port n reception busy flag 0 OK to receive 1 Reception in progress SCnISP Serial port n 2 stop sequence detect A read or write to SCnTRB clears this bit 0 No stop sequence 1 Stop sequence detected SCnRXA Serial port n received data flag 0 Not received 1 Received

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