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Intel BX80646I54670K Computer Hardware User Manual

1. Status 26 MSR_PERF_STATUS May Report an Incorrect Core Voltage The core operating voltage can be determined by dividing MSR_PERF_STATUS MSR 198H bits 47 32 by 2 13 However due to this erratum this calculation may report half the actual core voltage The core operating voltage may be reported incorrectly It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes PCIe Atomic Transactions From Two or More PCIe Controllers May Cause Starvation On a Processor PCIe controller configuration in which two or more controllers receive concurrent atomic transactions a PCIe controller may experience starvation which eventually can lead to a completion timeout Atomic transactions from two or more PCIe controllers may lead to a completion timeout Atomic transactions from only one controller will not be affected by this erratum Intel has not observed this erratum with any commercially available device None identified For the steppings affected see the Summary Table of Changes The Corrected Error Count Overflow Bit in IA32_ MCO_STATUS is Not Updated After a UC Error is Logged When a UC uncorrected error is logged in the IA32_MCO_STATUS MSR 401H corrected errors will continue to update the lower 14 bits bits 51 38 of the Corrected Error Count Due to this erratum the sticky count overflow bit bit 52 of the Corrected Error Count will not get updated a
2. Workaround Status HSD55 Problem Implication Workaround Status HSD56 Problem Implication Workaround Status HSD57 Problem Implication Workaround Status The From IP for Branch Tracing May be Incorrect BTM Branch Trace Message and BTS Branch Trace Store report the From IP indicating the source address of the branch instruction Due to this erratum BTM and BTS may repeat the From IP value previously reported The To IP value is not affected Using BTM or BTS reports to reconstruct program execution may be unreliable It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes TM1 Throttling May Continue indefinitely TM1 Thermal Monitor 1 throttling may continue when the processor s temperature decreases below the throttling point while the processor is in Package C3 or deeper The processor will continue thermal throttling but does not indicate it is hot It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Internal Parity Errors May Incorrectly Report Overflow in The IA32_MCi_STATUS MSR Due to this erratum uncorrectable internal parity error reports with an IA32_MCi_STATUS MCACOD bits 15 0 value of 0005H and an IA32_MCi_STATUS MSCOD bits 31 16 value of 0004H may incorrectly set the IA32_MCi_STATU
3. HSD10 Problem Implication Workaround Status intel FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM In general a PEBS record should be generated on the first count of the event after the counter has overflowed However IA32_DEBUGCTL_MSR FREEZE_WHILE_SMM MSR 1D9H bit 14 prevents performance counters from counting during SMM System Management Mode Due to this erratum if 1 A performance counter overflowed before an SMI 2 A PEBS record has not yet been generated because another count of the event has not occurred 3 The monitored event occurs during SMM then a PEBS record will be saved after the next RSM instruction When FREEZE_WHILE_SMM is set a PEBS should not be generated until the event occurs outside of SMM A PEBS record may be saved after an RSM instruction due to the associated performance counter detecting the monitored event during SMM even when FREEZE_WHILE_SMM is set None identified For the steppings affected see the Summary Table of Changes APIC Error Received Illegal Vector May be Lost APIC Advanced Programmable Interrupt Controller may not update the ESR Error Status Register flag Received Illegal Vector bit 6 properly when an illegal vector error is received on the same internal clock that the ESR is being written as part of the write read ESR access flow The corresponding error interrupt will also not be generated for this case Due to this e
4. Manual volumes 1 2A 2B 3A and 3B will be posted in a separate document Intel 64 and IA 32 Architecture Software Developer s Manual Documentation Changes Use the following link to become familiar with this file http developer intel com products processor manuals index htm There are no new Documentation Changes in this Specification Update revision On Demand Clock Modulation Feature Clarification Software Controlled Clock Modulation section of the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide will be modified to differentiate On demand clock modulation feature on different processors The clarification will state For Hyper Threading Technology enabled processors the IA32_CLOCK_MODULATION register is duplicated for each logical processor In order for the On demand clock modulation feature to work properly the feature must be enabled on all the logical processors within a physical processor If the programmed duty cycle is not identical for all the logical processors the processor clock will modulate to the highest duty cycle programmed for processors if the CPUID DisplayFamily_DisplayModel signatures is listed in Table 14 2 For all other processors if the programmed duty cycle is not identical for all logical processors in the same core the processor will modulate at the lowest programmed duty cycle For multiple processor cores in a physical package each core can modulate to
5. Products are differentiated by their unique characteristics such as core speed L2 cache size package type etc as described in the processor identification information table Read all notes associated with each S Spec number Specification Changes are modifications to the current published specifications These changes will be incorporated in any new release of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorporated in any new release of the specification Documentation Changes include typos errors or omissions from the current published specifications These will be incorporated in any new release of the specification Errata remain in the specification update throughout the product s lifecycle or until a particular stepping is no longer commercially available Under these circumstances errata removed from the specification update are archived and available upon request Specification changes specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation datasheets manuals and so on intel Summary Tables of Changes The following tables indicate the errata specification changes specification clarifications or documentation changes whic
6. causing the VMM to walk incorrect or non existent tables Intel has not observed this erratum with any commercially available software Privileged software should not execute a MWAIT because it can trigger a package C7 entry exit between writing to RTA_REG IRTA_REG and GCMD_REG SRTP GCMD_REG SIRTP registers For the steppings affected see the Summary Table of Changes General Purpose Performance Counters Can Unexpectedly Increment A performance monitor event programmed in a general purpose performance counter should count the number of occurrences of the event selected in IA32_PERFEVTSEL 0 7 MSR 186H 18DH If INV invert bit 23 is set to 1 and a non zero CMASK Counter Mask bits 31 24 value is used due to this erratum the event may over count in the case that either of OS Operating System mode bit 17 or USR User mode bit 16 is selected Over counting will occur for the cycles spent in the non matching CPL General purpose performance counters may reflect counts higher than the actual number of events when the INV bit is set CMASK is a non zero value and either the OS or USR bit is set None identified Specification Update 35 intel Status HSD74 Problem Implication Workaround Status HSD75 Problem Implication Workaround Status HSD76 Problem Implication Workaround Status HSD77 Problem Implication Workaround Status 36 For the ste
7. Last Branch Record is not correctly reported Due to this erratum an incorrect From IP on the LBR stack may be observed None identified For the steppings affected see the Summary Table of Changes SMRAM State Save Area Above the 4GB Boundary May Cause Unpredictable System Behavior If BIOS uses the RSM instruction to load the SMBASE register with a value that would cause any part of the SMRAM state save area to have an address above 4 GBytes subsequent transitions into and out of SMM system management mode might save and restore processor state from incorrect addresses This erratum may cause unpredictable system behavior Intel has not observed this erratum with any commercially available system Ensure that the SMRAM state save area is located entirely below the 4GB address boundary For the steppings affected see the Summary Table of Changes DMA Remapping Faults for the Graphics VT d Unit May Not Properly Report Type of Faulted Request When a fault occurs during DMA remapping of Graphics accesses at the Graphics VT d unit the type of faulted request read or write should be reported in bit 126 of the FRCD_REG register in the remapping hardware memory map register set Due to this erratum the request type may not be reported correctly Software processing the DMA remapping faults may not be able to determine the type of faulting graphics device DMA request None identified For the steppings affected see the Summary T
8. Not HSD34 x Noi Fix Update Previous Elements HSD35 X No Fix PLATFORM_POWER_LIMIT MSR Not Visible HSD36 X No Fix LPDDR Memory May Report Incorrect Temperature HSD37 X No Fix PCle Host Bridge DID May Be Incorrect HSD38 X No Fix TSC May be Incorrect After a Deep C State Exit PCle Controller May Initiate Speed Change While in DL_Init State HSP39 x N F x Causing Certain PCle Devices to Fail to Train HSD40 X No Fix Spurious VT d Interrupts May Occur When the PFO Bit is Set HSD41 X No Fix N A Erratum has been removed AVX Gather Instruction That Causes a Fault or VM Exit May Incorrectly HSD42 x No Fix Modify Its Destination Register Inconsistent NaN Propagation May Occur When Executing V DPPS HSD43 X No Fix Instruction HSD44 X No Fix Display May Flicker When Package C States Are Enabled HSD45 x No Fix Certain Combinations of AVX Instructions May Cause Unpredictable System Behavior HSD46 X No Fix Processor May Incorrectly Estimate Peak Power Delivery Requirements HSD47 X No Fix IA32_PERF_CTL MSR is Incorrectly Reset HSD48 X No Fix Processor May Hang During a Function Level Reset of the Display AVX Gather Instruction That Should Result in DF May Cause HSD49 x Neen Unexpected System Behavior HSD50 x No Fix raii and Refresh Rate Maybe be Incorrect After Exiting Package C HSD51 X No Fix Processor May Livelock During On Demand Clock Modulation HSD52 x No Fix IA32_DEBUGCTL FREEZE_PERFMON_ON_PM1 is Incorrectly Cleared by SM
9. OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or go to http www intel com design literature htm Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release Customers licensees and other third parties are not authorized by Intel to use code names in advertising promotion or marketing of any product or servi
10. Updates Revision number added to Revision History to maintain N A consistency with NDA Specification Update numbering Errata Moved previous HSD99 to HSD108 005 Added HSD99 107 and HSD109 115 November 2013 Updated Identification Information Identification Information 006 Updated Desktop Processor Identification table December 2013 007 Errata December 2013 Added HSD116 118 Specification Update intel Preface This document is an update to the specifications contained in the Affected Documents table below This document is a compilation of device and documentation errata specification clarifications and changes It is intended for hardware system manufacturers and software developers of applications operating systems or tools Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents This document may also contain information that was not previously published Affected Documents Document Title Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 Document Number 328897 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 2 of 2 328898 Related Documents Docu
11. Volume 1 Basic Architecture e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide There are no new Specification Changes in this Specification Update revision 48 Specification Update intel Documentation Changes Note HSD1 The Documentation Changes listed in this section apply to the following documents e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation Documentation changes for Intel 64 and IA 32 Architecture Software Developer s
12. a programmed duty cycle independently For the P6 family processors on demand clock modulation was implemented through the chipset which controlled clock modulation through the processor s STPCLK pin Table 14 2 CPUID Signatures for Legacy Processors That Resolve to Higher Performance Setting of Conflicting Duty Cycle Requests Specification Update 49 50 Display Family Display Display Family Display Display Family Display Display Family Display Model Model Model Model OF_xx 06_1C 06_1A 06_1E 06_1F 06_25 06_26 06_27 06_2C 06_2E 06_2F 06_35 06_36 Specification Update
13. aperture may result in a failure for writes to complete or reads to return incorrect results A hang or functional failure may occur during graphics operation such as OGL or OCL conformance tests 2D 3D games and graphics intensive application It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update HSD21 Problem Implication Workaround Status HSD22 Problem Implication Workaround Status HSD23 Problem Implication Workaround Status PCIe Root Port May Not Initiate Link Speed Change The PCle Base specification requires the upstream component to maintain the PCle link at the target link speed or the highest speed supported by both components on the link whichever is lower PCle root port will not initiate the link speed change without being triggered by the software when the root port maximum link speed is configured to be 5 0 GT s System BIOS will trigger the link speed change under normal boot scenarios However BIOS is not involved in some scenarios such as link disable re enable or secondary bus reset and therefore the speed change may not occur unless initiated by the downstream component This erratum does not affect the ability of the downstream component to initiate a link speed change All known 5 0Gb s capable PCIe downstream components have been observed to initiate the link speed change
14. before software invalidates any TLB entries for the linear region Due to this erratum an unexpected machine check with error code 0150H may occur possibly resulting in a shutdown Intel has not observed this erratum with any commercially available software Software should not write to a paging structure entry in a way that would change for any linear address both the page size and the memory type It can instead use the following algorithm first clear the P flag in the relevant paging structure entry e g PDE then invalidate any translations for the affected linear addresses and then modify the relevant paging structure entry to set the P flag and establish the new page size and memory type For the steppings affected see the Summary Table of Changes Specification Update HSD14 Problem Implication Workaround Status HSD15 Problem Implication Workaround Status HSD16 Problem Implication Workaround Status intel Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX vvvv May Produce a NM Exception The VAESIMC and VAESKEYGENASSIST instructions should produce a UD Invalid Opcode exception if the value of the vvvv field in the VEX prefix is not 1111b Due to this erratum if CRO TS is 1 the processor may instead produce a NM Device Not Available exception Due to this erratum some undefined instruction encodings may produce a NM instead of a
15. by VM entry event injection may use an incorrect value for the B flag default stack pointer size and upper bound for the stack segment SS An affected stack access may use an incorrect address or an incorrect segment upper bound This may result in unpredictable system behavior It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes A Fault in SMM May Result in Unpredictable System Behavior The value of the SS register as well as the current privilege level CPL may be incorrect following a fault in SMM system management mode The erratum can occur only if a fault occurs following an SMI system management interrupt and before software has loaded the SS register e g with the MOV SS instruction This erratum may cause unpredictable system behavior Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Table of Changes Processor Frequency is Unexpectedly Limited Below Nominal P1 When cTDP Down is Enabled When cTDP Configurable Thermal Design Power Down is enabled on a processor branded as Core i3 or Pentium the processor frequency will be limited to cTDP Down P1 frequency Max Non Turbo Frequency when it should be able to operate between the cTDP Down frequency P1 and the nominal P1 frequency When cTDP is enabled the processor cannot achieve expected frequenc
16. intel Desktop 4th Generation Intel Core PA Processor Family Desktop Intel Pentium Processor Family ane Desktop Intel Celeron Processor Family Specification Update December 2013 Revision 007 Reference Number 328899 007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER
17. or FXRSTOR with the VEX prefix For the steppings affected see the Summary Table of Changes RDRAND Execution in a Transactional Region May Cause a System Hang Execution of the RDRAND Random number generator instruction inside an Intel TSX transactional region may cause the logical processor to hang A system hang may occur as a result of this erratum It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Uncore Clock Frequency Changes May Cause Audio Video Glitches On some processors the time required to change the uncore clock frequency may be large enough to significantly lengthen the latency of I O Requests to memory possibly resulting in audio or video glitches Audio Video glitches may occur during uncore ratio changes It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Processor May Experience a Spurious LLC Related Machine Check During Periods of High Activity Due to certain internal conditions while running core and memory intensive operations some processors may incorrectly report an LLC last level cache related machine check with a IA32_MCi_STATUS MCACOD value of 110AH Due to this erratum the processor may experience a machine check It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of
18. returned in bits 9 1 although there is a VMCS field whose encoding uses the index value 23 Software that uses the value reported in IA32_VMX_VMCS_ENUM 9 1 to read and write all VMCS fields may omit one field None identified For the steppings affected see the Summary Table of Changes Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be Observed During RTM Restricted Transactional Memory operation when branch tracing is enabled using BTM Branch Trace Message or BTS Branch Trace Store the incorrect EIP value From_IP pointer may be observed for an RTM abort Due to this erratum the From_IP pointer may be the same as that of the immediately preceding taken branch None identified For the steppings affected see the Summary Table of Changes VT d Hardware May Perform STRP And SIRTP Operations on a Package C7 Exit On a package C7 exit VT d hardware may spuriously perform SRTP Set Root Table Pointer and SIRTP Set Interrupt Remapping Table Pointer operations A package C7 exit can cause the value programmed by software in the RTA_REG IRTA_REG to be visible to hardware before software executes a GCMD SRTP command This will result in hardware using the new values for the DMA and interrupt translation page walks possibly before they are intended to be used by software If software has updated the root table pointer but has not executed the SRTP command then the root table pointer update will happen unexpectedly
19. 0T C 0 3 2 2 2 9 1600 2 9 35 SR1NP 13 4130 C 0 3 2 2 3 4 1600 3 4 65 SR1CN pe C 0 2 2 1 2 7 1333 2 7 65 SR1CP wen C 0 2 2 1 2 4 1333 2 4 35 SRINC ae C 0 2 2 1 2 8 1333 2 8 65 16 Specification Update intel Errata HSD1 Problem Implication Workaround Status HSD2 Problem Implication Workaround Status HSD3 Problem Implication Workaround Status LBR BTS BTM May Report a Wrong Address when an Exception Interrupt Occurs in 64 bit Mode An exception interrupt event should be transparent to the LBR Last Branch Record BTS Branch Trace Store and BTM Branch Trace Message mechanisms However during a specific boundary condition where the exception interrupt occurs right after the execution of an instruction at the lower canonical boundary OxO0007FFFFFFFFFFF in 64 bit mode the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to all 1 s Subsequent BTS and BTM operations which report the LBR will also be incorrect LBR BTS and BTM may report incorrect information in the event of an exception interrupt None identified For the steppings affected see the Summary Table of Changes EFLAGS Discrepancy on Page Faults and on EPT Induced VM Exits after a Translation Change This erratum is regarding the case where paging structures are modified to change a linear address from writable to non wri
20. Are Not Available Feature flags BMI1 and BMI2 CPUID leaf 7 sub leaf 0 EBX bits 3 and 8 report these two groups of bit manipulation instructions are not present for the Intel Core i3 4330TE but these instruction groups should be available An attempt to execute any of these instructions will generate a UD fault Software attempting to use any of instructions in the BMI1 and BMI2 groups will result in a UD fault It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Virtual APIC Page Accesses With 32 Bit PAE Paging May Cause a System Crash If a logical processor has EPT Extended Page Tables enabled is using 32 bit PAE paging and accesses the virtual APIC page then a complex sequence of internal processor micro architectural events may cause an incorrect address translation or machine check on either logical processor This erratum may result in unexpected faults an uncorrectable TLB error logged in IA32_MCi_STATUS MCACOD bits 15 0 with a value of 0000_0000_0001_xxxxb where x stands for 0 or 1 a guest or hypervisor crash or other unpredictable system behavior It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update 43 intel HSD109 Problem Implication Workaround Status HSD110 Problem Implication Workaround Sta
21. Changes The Processor May Not Enter Package C7 When Using a PSR Display The processor datasheet specifies that entering package C7 requires enabling PSR Panel Self Refresh for certain display resolutions along with other conditions Due to this erratum the processor may not enter package C7 when connected to a PSR enabled display even if all of the required conditions are met Due to this erratum the processor may not enter package C7 It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update HSD97 Problem Implication Workaround Status HSD98 Problem Implication Workaround Status HSD99 Problem Implication Workaround Status HSD100 Problem Implication Workaround Status Video Audio Distortion May Occur Due to this erratum internal processor operations can occasionally delay the completion of memory read requests enough to cause video or audio streaming underrun Visible artifacts such as flickering on a video device or glitches on audio may occur It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes System May Hang When Audio is Enabled During Package C3 When audio is enabled while in package C3 state or deeper audio memory traffic continues to be generated Due to this erratum the processo
22. ERR Pin Assertion is Not Cleared on a Warm Reset HSD118 x No Fix rae a Machine Check Error During Core C6 Entry May Not be Specification Changes Number SPECIFICATION CHANGES None for this revision of this specification update Specification Clarifications Number SPECIFICATION CLARIFICATIONS None for this revision of this specification update Documentation Changes Number DOCUMENTATION CHANGES HSD1 On Demand Clock Modulation Feature Clarification Specification Update 13 intel Identification Information Component Identification using Programming Interface The processor stepping can be identified by the following register contents Table 1 Desktop 4th Generation Intel Core Processor Family Component Identification Extended Extended Processor Family Model Stepping Reserved Family Model Reserved Type Code Number ID 31 28 27 20 19 16 15 14 13 12 11 8 7 4 3 0 00000000b 0011b 00b 0110b 1100b xxxxb Notes 1 The Extended Family Bits 27 20 are used in conjunction with the Family Code specified in Bits 11 8 to indicate whether the processor belongs to the Intel386 Intel486 Pentium Pentium 4 or Intel Core processor family 2 The Extended Model Bits 19 16 in conjunction with the Model Number specified in Bits 7 4 are used to identify the model of the processor wit
23. I HSD53 X No Fix The From IP for Branch Tracing May be Incorrect HSD54 X No Fix TM1 Throttling May Continue indefinitely 10 Specification Update Errata Sheet 3 of 5 Specification Update Steppings Number Status ERRATA C 0 Internal Parity Errors May Incorrectly Report Overflow in The ER X No Fix 1432 MCi_STATUS MSR e Performance Monitor Events OTHER_ASSISTS AVX_TO_SSE And HSD56 X No Fix d ka OTHER_ASSISTS SSE_TO_AVX May Over Count HSD57 X No Fix Processor May Run at Incorrect P State HSD58 x No Fix Performance Monitor Event DSB2MITE_SWITCHES COUNT May Over Count Performance Monitor Register UNC_PERF_GLOBAL_STATUS Not HSDS9 x er rie Restored on Package C7 Exit Processor May Not Enter Package C6 or Deeper C states When PCle HSDG x No Fix Links Are Disabled n Performance Monitor Event For Outstanding Offcore Requests And MSDEL x NoFix Snoop Requests May Over Count HSD62 x No Fix nina Performance Monitor Event Counts May be Inaccurate During SMT HSD63 X No Fix Timed MWAIT May Use Deadline of a Previous Execution HSD64 x No Fix The Upper 32 Bits of CR3 May be Incorrectly Used With 32 Bit Paging HSD65 x No Fix Performance Monitor Events HLE_RETIRED ABORTED_MISC4 And RTM_RETIRED ABORTED_MISC4 May Over Count HSD66 X No Fix A PCle LTR Update Message May Cause The Processor to Hang HSD67 x No Fix GETSEC Does Not Repor
24. IOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes TSC May be Incorrect After a Deep C State Exit On exiting from Package C6 or deeper the processor may incorrectly restore the TSC Time Stamp Counter Software using the TSC may produce incorrect result and or may not behave as expected It is possible for BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes PCIe Controller May Initiate Speed Change While in DL_Init State Causing Certain PCIe Devices to Fail to Train The PCIe controller supports hardware autonomous speed change capabilities Due to this erratum the PCIe controller may initiate speed change while in the DL_Init state which may prevent link training for certain PCIe devices Certain PCIe devices may fail to complete DL_Init causing the PCIe link to fail to train It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update 27 intel HSD40 Problem Implication Workaround Status HSD41 HSD42 Problem Implication Workaround Status HSD43 Problem Implication Workaround Status 28 Spurious VT d Interrupts May Occur When the PFO Bit is Set When the PFO Primary Fault Overflow field bit 0 in the VT d FSTS Fault Status register is set to 1 further faults sho
25. RETIRED LOCK MEM_UOP_RETIRED SPLIT MEM_UOP_RETIRED STLB_MISS MEM_LOAD_UOPS_RETIRED HIT_LFB MEM_LOAD_UOPS_RETIRED L1_HIT MEM_LOAD_UOPS_RETIRED L2_HIT MEM_LOAD_UOPS_RETIRED LLC_HIT MEM_LOAD_UOPS_MISC_RETIRED LLC_MISS MEM_LOAD_UOPS_LLC_HIT_RETIRED XSNP_HIT MEM_LOAD_UOPS_LLC_HIT_RETIRED XSNP_HITM MEM_LOAD_UOPS_LLC_HIT_RETIRED XSNP_MISS MEM_LOAD_UOPS_LLC_HIT_RETIRED XSNP_NONE MEM_LOAD_UOPS_RETIRED LLC_MISS MEM_LOAD_UOPS_LLC_MISS_RETIRED LOCAL_DRAM MEM_LOAD_UOPS_LLC_MISS_RETIRED REMOTE_DRAM MEM_LOAD_UOPS_RETIRED L2_MISS Due to this erratum certain performance monitoring event will produce unreliable results during hyper threaded operation None identified For the steppings affected see the Summary Table of Changes Performance Monitor UOPS_EXECUTED Event May Undercount The performance monitor event UOPS_EXECUTED Event BiH any Unmask should count the number of UOPs executed each cycle However due to this erratum when eight UOPs execute in one cycle these UOPs will not be counted The performance monitor event UOPS_EXECUTED may reflect a count lower than the actual number of events None identified For the steppings affected see the Summary Table of Changes Specification Update 25 intel HSD31 Problem Implication Workaround Status HSD32 Problem Implication Workaround Status HSD33 Problem Implication Workaround Status HSD34 Problem Implication Workaround
26. S OVER flag bit 62 indicating an overflow even when only a single error has been observed IA32_MCi_STATUS OVER may not accurately indicate multiple occurrences of uncorrectable internal parity errors There is no other impact to normal processor functionality None identified For the steppings affected see the Summary Table of Changes Performance Monitor Events OTHER_ASSISTS AVX_TO_SSE And OTHER_ASSISTS SSE_TO_AVX May Over Count The Performance Monitor events OTHER_ASSISTS AVX_TO_SSE Event C1H Umask 08H and OTHER_ASSISTS SSE_TO_AVX Event CiH Umask 10H incorrectly increment and over count when an HLE Hardware Lock Elision abort occurs The Performance Monitor Events OTHER_ASSISTS AVX_TO_SSE And OTHER_ASSISTS SSE_TO_AVX may over count None identified For the steppings affected see the Summary Table of Changes Processor May Run at Incorrect P State The processor package may use stale software P State performance state requests when one or more logical processors are idle The processor package may run at a higher or lower than expected P State This issue may persist as long as any logical processor is idle It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update 31 HSD58 Problem Implication Workaround Status HSD59 Problem Implication Workaround Status HSD60 Problem Impl
27. Status HSD114 Problem Implication Workaround Status HSD115 Problem Implication Workaround Status HSD1i16 Problem Processor May Hang During Package C7 Exit Under certain internal timing conditions the processor might not properly exit package C7 leading to a hang Due to this erratum the package C7 state may not be reliable Intel has not observed this erratum with any commercially available system It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Intel TSX Instructions May Cause Unpredictable System behavior Under a complex set of internal timing conditions and system events software using the Intel TSX Transactional Synchronization Extensions instructions may observe unpredictable system behavior This erratum may result in unpredictable system behavior Intel has not observed this erratum with any commercially available system It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Spurious LLC Machine Check May Occur Under certain stressful conditions while running at ring ratios higher than 30 the processor may experience a spurious LLC machine check as indicated by IA32_MCi_STATUS MCACOD bits 15 0 with value 000x 0001 0000 1010 where x is 0 or 1 When this erratum occurs an uncorrectable LLC error will be logged an
28. The PLATFORM_POWER_LIMIT MSR 615H is used to control the PL3 power limit 3 mechanism of the processor Due to this erratum this MSR is not visible to software Software is unable to read or write the PLATFORM_POWER_LIMIT MSR If software attempts to access this MSR a general protection fault will occur It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes LPDDR Memory May Report Incorrect Temperature When any of the four possible LPDDR ranks are not populated the unpopulated ranks will report a default temperature of 85C as a three bit value of 011b If the system has unpopulated ranks the temperature of memory will be reported as 85C in PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE MCHBAR Bus 0 Device 0 Function 0 offset 58B8H in bits 5 7 until any of the populated ranks report a higher temperature than this When the memory temperature is less than or equal to 85C it may be reported as 85C This erratum does not affect DDR3 and DDR3L memory types It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes PCIe Host Bridge DID May Be Incorrect The PCIe Host Bridge DID register Bus 0 Device 0 Offset 2H contents may be incorrect after a Package C7 exit Software that depends on the Host Bridge DID value may not behave as expected after a Package C7 exit It is possible for the B
29. UD exception Software should always set the vvvv field of the VEX prefix to 1111b for instances of the VAESIMC and VAESKEYGENASSIST instructions For the steppings affected see the Summary Table of Changes Processor May Fail to Acknowledge a TLP Request When a PCIe root port s receiver is in Receiver LOs power state and the port initiates a Recovery event it will issue Training Sets to the link partner The link partner will respond by initiating an LOs exit sequence Prior to transmitting its own Training Sets the link partner may transmit a TLP Transaction Layer Packet request Due to this erratum the root port may not acknowledge the TLP request After completing the Recovery event the PCIe link partner will replay the TLP request The link partner may set a Correctable Error status bit which has no functional effect None identified For the steppings affected see the Summary Table of Changes Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered If the local APIC timer s CCR current count register is 0 software should be able to determine whether a previously generated timer interrupt is being delivered by first reading the delivery status bit in the LVT timer register and then reading the bit in the IRR interrupt request register corresponding to the vector in the LVT timer register If both values are read as 0 no timer interrupt should be in the process of being delivered Due to this erratu
30. able of Changes AVX Gather Instructions Page Faults May Report an Incorrect Faulting Address If software modifies a paging structure entry to relax the access rights for a linear address and does not perform a TLB invalidation a subsequent execution of an AVX gather instruction that accesses that address may generate a page fault that loads CR2 which should containing the faulting linear address with an incorrect value Software handling an affected page fault may not operate correctly It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update HSD87 Problem Implication Workaround Status HSD88s Problem Implication Workaround Status HSD89 Problem Implication Workaround Status HSD9O Problem Implication Workaround Status HSD91 Problem Implication Workaround Status Intel TSX Instructions May Cause Unpredictable System behavior Under certain system conditions Intel TSX Transactional Synchronization Extensions instructions may result in unpredictable system behavior Due to this erratum use of Intel TSX may result in unpredictable behavior It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Event Injection by VM Entry May Use an Incorrect B Flag for SS The stack accesses made
31. are may observe different NaN encodings in the destination elements Inconsistent NaN encodings in the destination elements for the V DPPS instruction may be observed It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update HSD44 Problem Implication Workaround Status HSD45 Problem Implication Workaround Status HSD46 Problem Implication Workaround Status HSD47 Problem Implication Workaround Status HSD48 Problem Implication Workaround Status Display May Flicker When Package C States Are Enabled When package C States are enabled the display may not be refreshed at the correct rate When this erratum occurs the user may observe flickering on the display It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Certain Combinations of AVX Instructions May Cause Unpredictable System Behavior Execution of certain combinations of AVX instructions may lead to unpredictable system behavior When this erratum occurs unpredictable system behaviors including system hang or incorrect results can occur It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Processor May Incorrectly Estimate Peak Power Delive
32. capture processor state in a PEBS record following the execution of the next instruction that causes the counter to increment a triggering instruction Due to this erratum the capture of processor state may occur at an instruction after the first triggering instruction following the skid but not beyond the second triggering instruction after the skid A PEBS record may contain processor state including instruction pointer not associated with the triggering instruction None identified For the steppings affected see the Summary Table of Changes MSR_PP1_ENERGY_STATUS Reports Incorrect Energy Data The MSR_PP1_ENERGY_STATUS MSR 641H bits 31 0 reports incorrect energy data Due to this erratum reported Intel Integrated Graphics domain energy consumption may not be accurate It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes x87 FPU DP May be Incorrect After Instructions That Save FP State to Memory Under certain conditions the value of the x87 FPU DP Floating Point Unit Data Pointer saved by the FSAVE FNSAVE FSTENV FNSTENV FXSAVE XSAVE or XSAVEOPT instructions may be incorrect Due to this erratum the x87 FPU DP may be incorrect It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update HSD113 Problem Implication Workaround
33. ces and any such use of Intel s internal code names is at the sole risk of the user Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM Functionality performance or other benefits will vary depending on hardware and software configurations Software applications may not be compatible with all operating systems Consult your PC manufacturer For more information visit http Awww intel com go virtualization Intel Turbo Boost Technology requires a system with Intel Turbo Boost Technology Intel Turbo Boost Technology and Intel Turbo Boost Technology 2 0 are only available on select Intel processors Consult your PC manufacturer Performance varies depending on hardware software and system configuration For more information visit http www intel com go turbo Intel Hyper Threading Technology requires an Intel HT Technology enabled system check with your PC manufacturer Performance will vary depending on the specific hardware and software used Not available on Intel Core i5 750 For more information including details on which processors support HT Technology visit http www intel com info hyperthreading Intel 64 architecture requires a system with a 64 bit enabled processor chipset BIOS and software Performance will vary depending on the specific hardware and software you use Consult your PC manufacturer for more information For more informati
34. count Due to this erratum the Local Memory Read Load Retired PerfMon events listed below may undercount MEM_LOAD_RETIRED L3_HIT MEM_LOAD_RETIRED L3_MISS MEM_LOAD_L3_HIT_RETIRED XSNP_MISS MEM_LOAD_L3_HIT_RETIRED XSNP_HIT MEM_LOAD_L3_HIT_RETIRED XSNP_HITM MEM_LOAD_L3_HIT_RETIRED XSNP_NONE MEM_LOAD_L3_MISS_RETIRED LOCAL_DRAM MEM_LOAD_L4_RETIRED LOCAL_HIT MEM_TRANS_RETIRED LOAD_LATENCY The affected events may undercount resulting in inaccurate memory profiles Intel has observed undercounts as much as 40 None identified For the steppings affected see the Summary Table of Changes Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior Specific source copy blitter instructions in Intel HD Graphics 4600 Processor may result in unpredictable behavior when a blit source and destination overlap Due to this erratum the processor may exhibit unpredictable graphics controller behavior Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Table of Changes Processor May Enter Shutdown Unexpectedly on a Second Uncorrectable Error If an IA32_MCi_STATUS MSR contains an uncorrectable error with MCACOD 0x406 and a second uncorrectable error occurs after warm reset but before the first error is cleared by zeroing the IA32_MCi_STATUS MSR a shutdown will occur When this erratum occurs the processor will unex
35. d EPT violation This erratum applies only if software enters 64 bit mode loads CR3 with a 64 bit value and then returns to 32 bit paging without changing CR3 Intel has not observed this erratum with any commercially available software Software that has executed in 64 bit mode should reload CR3 with a 32 bit value before returning to 32 bit paging For the steppings affected see the Summary Table of Changes Performance Monitor Events HLE_RETIRED ABORTED_MISC4 And RTM_RETIRED ABORTED_MISC4 May Over Count The Performance Monitor Events HLE_RETIRED ABORTED_MISC4 Event C8H Umask 40H and RTM_RETIRED ABORTED_MISC4 Event C9H Umask 40H are defined to count the number of transactional aborts due to incompatible memory types Due to this erratum they may count additional unrelated transactional aborts The Performance Monitor Events HLE_RETIRED ABORTED_MISC4 and RTM_RETIRED ABORTED_MISC4 counts may be greater than the number of aborts due to incompatible memory types This can result in nonzero counts when all memory types are compatible None identified For the steppings affected see the Summary Table of Changes Specification Update 33 HSD66 Problem Implication Workaround Status HSD67 Problem Implication Workaround Status HSD68 Problem Implication Workaround Status HSD69 Problem Implication Workaround Status 34 A PCIe LTR Update Message May Cause The Process
36. d the system may hang or restart It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Page Fault May Report Incorrect Fault Information Under the following conditions 1 Aread modify write instruction s memory source destination e g ADD memory reg crossing a cache line boundary 2 That instruction executing without fault 3 While the read modify write instruction is executing one or more of the following page table attributes associated with its memory operand are modified a the D dirty flag was 0 when the instruction was initiated but was concurrently set to 1 and or b one of the relevant R W flags was 0 when the instruction was initiated but was concurrently set to 1 and or c if the read modify write instruction executes at CPL 3 and one of the relevant U S flags was 0 when the instruction was initiated but was concurrently set to 1 4 A subsequent instruction executing within a narrow timing window that experiences a page fault 5 There is no serializing instruction between the read modify write instruction and the faulting instruction Specification Update 45 intel Implication Workaround Status HSD117 Problem Implication Workaround Status HSD118 Problem Implication Workaround Status 46 The page fault in 4 may report an incorrect error code and faulting linear addres
37. e HSD5 x No Fix MONITOR or CLFLUSH on the Local XAPIC s Address Space Results in Hang HSD6 x No Fix An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang HSD7 x No Fix GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code FREEZE _WHILE_SMM Does Not Prevent Event From Pending HERS x No Fix EBS During SMM HSD9 X No Fix APIC Error Received Illegal Vector May be Lost Changing the Memory Type for an In Use Page Translation May Lead to FSD 0 x No Fix Memory Ordering Violations Performance Monitor Precise Instruction Retired Event May Present FISBT1 x No Fix Wrong Indications HSD12 x No Fix CRO CD Is Ignored in VMX Operation i Instruction Fetch May Cause Machine Check if Page Size and Memory meets x Nene Type Was Changed Without Invalidation P Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value FSD14 x Nek for VEX vvvv May Produce a NM Exception HSD15 X No Fix Processor May Fail to Acknowledge a TLP Request HSD16 x No Fix Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered HSD17 x No Fix PCle Root port Initiated Compliance State Transmitter Equalization Settings May be Incorrect HSD18 X No Fix PCle Controller May Incorrectly Log Errors on Transition to RxLOs HSD19 X No Fix Unused PCle Lanes May Report Correctable Errors e Accessing Physical Memory Space 0 640K through the Graphics HSD20 x No Fix Apert
38. egister A DTLB error is indicated by MCA error code bits 15 0 appearing as binary value 000x 0000 0001 0100 in the MCi_Status register Due to this erratum the Overflow bit in the MCi_Status register may not be an accurate indication of multiple occurrences of DTLB errors There is no other impact to normal processor functionality None identified For the steppings affected see the Summary Table of Changes Specification Update 17 HSD4 Problem Implication Workaround Status HSD5 Problem Implication Workaround Status HSD6 Problem Implication Workaround Status HSD7 Problem Implication Workaround Status 18 LER MSRs May Be Unreliable Due to certain internal processor events updates to the LER Last Exception Record MSRs MSR_LER_FROM_LIP 1DDH and MSR_LER_TO_LIP 1DEH may happen when no update was expected The values of the LER MSRs may be unreliable None identified For the steppings affected see the Summary Table of Changes MONITOR or CLFLUSH on the Local XAPIC s Address Space Results in Hang If the target linear address range for a MONITOR or CLFLUSH is mapped to the local xAPIC s address space the processor will hang When this erratum occurs the processor will hang The local xAPIC s address space must be uncached The MONITOR instruction only functions correctly if the specified linear address range is of the type write back CLFLUSH
39. es Specification Update HSD105 Problem Implication Workaround Status HSD106 Problem Implication Workaround Status HSD107 Problem Implication Workaround Status HSD108 Problem Implication Workaround Status Warm Reset Does Not Stop GT Power Draw Due to this erratum if GT is enabled prior to a warm reset it will remain powered after the warm reset The processor will make incorrect power management decisions because it assumes the GT is not drawing power after a warm reset The processor may draw more current than expected from an external VR Voltage Regulator The processor may also put the external VR into a low power state where it will be unable to supply the sufficient power resulting in unpredictable system behavior It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Unused PCIe Lanes May Remain Powered After Package C7 If a PCle controller is enabled and either has unused lanes or no PCle device is present the link and or unused lanes should enter a low power state Due to this erratum after exiting Package C7 the unused link and or unused lanes may remain powered Power consumption may be greater than expected It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes BMI1 And BMI2 Instruction Groups
40. etcher and over count OFFCORE_REQUESTS_OUTSTANDING DEMAND_DATA Event 60H Umask 01H OFFCORE_REQUESTS DEMAND_DATA Event BOH Umask 01H CYCLE_ACTIVITY L2_Pending Event A3H Umask 01H L2_HIT_MISS LOAD Event 24H Umask 01H The listed performance monitoring events may reflect a count higher than the actual number of events None identified For the steppings affected see the Summary Table of Changes Accessing Nonexistent Uncore Performance Monitoring MSRs May Not Signal a GP An access to an uncore Performance Monitor MSR beyond the number reported in the MSR_UNC_CBO_CONFIG MSR 396H bits 3 0 should signal a GP general protection exception due to this erratum the processor may hang instead of signaling GP When software accesses nonexistent uncore performance monitoring MSRs the logical processor may hang instead of signaling a GP It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Call Stack Profiling May Produce Extra Call Records The performance monitoring Call Stack Profiling function should not generate call records for zero length calls call instructions targeting the location following the instruction However due to this erratum the processor will produce call records for zero length calls The performance monitoring LBR call stack MSRs are incorrect in the presence of zero length calls because calls and return
41. f Changes Uncorrectable Machine Check Error During Core C6 Entry May Not be Signaled Machine Check exceptions occurring during core C6 entry may be ignored When this erratum occurs incorrect state may be saved during core C6 entry and subsequently restored during core C6 exit resulting in unpredictable system behavior It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update intel Specification Changes The Specification Changes listed in this section apply to the following documents Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide There are no new Specification Changes in this Specification Update revision Specification Update 47 intel Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents e Intel 64 and IA 32 Architectures Software Developer s Manual
42. flushes data from the cache Intel has not observed this erratum with any commercially available software Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space For the steppings affected see the Summary Table of Changes An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR 409H may also result in a system hang causing an Internal Timer Error MCACOD 0x0400h to be logged in another machine check bank IA32_MCi_STATUS Uncorrectable errors logged in IA32_CR_MC2_STATUS can further cause a system hang and an Internal Timer Error to be logged None identified For the steppings affected see the Summary Table of Changes GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code During a GP General Protection Exception the processor pushes an error code on to the exception handler s stack If the segment selector descriptor straddles the canonical boundary the error code pushed onto the stack may be incorrect An incorrect error code may be pushed onto the stack Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Table of Changes Specification Update HSD8 Problem Implication Workaround Status HSD9 Problem Implication Workaround Status
43. following instruction Due to this erratum DR6 BO B3 bits may not contain information about data breakpoints matched during the MOV POP SS when the following instruction is either an MMX instruction that uses a memory addressing mode with an index or a store instruction When this erratum occurs DR6 may not contain information about all breakpoints matched This erratum will not be observed under the recommended usage of the MOV SS r m or POP SS instructions i e following them only with an instruction that writes E R SP None identified For the steppings affected see the Summary Table of Changes Specification Update 23 HSD24 Problem Implication Workaround Status HSD25 Problem Implication Workaround Status HSD26 Problem Implication Workaround Status HSD27 Problem Implication Workaround Status 24 VEX L is Not Ignored with VCVT 2SI Instructions The VEX L bit should be ignored for the VCVTSS2SI VCVTSD2SI VCVTTSS2SI and VCVTTSD2SI instructions however due to this erratum the VEX L bit is not ignored and will cause a UD Unexpected UDs will be seen when the VEX L bit is set to 1 with VCVTSS2SI VCVTSD2SI VCVTTSS2SI and VCVTTSD2SI instructions Software should ensure that the VEX L bit is set to 0 for all scalar instructions For the steppings affected see the Summary Table of Changes Certain Local Memory Read Load Retired PerfMon Events May Under
44. fter a UC error is logged The Corrected Error Count Overflow indication will be lost if the overflow occurs after an uncorrectable error has been logged None identified For the steppings affected see the Summary Table of Changes An AVX Gather Instruction That Causes an EPT Violation May Not Update Previous Elements When execution of an AVX gather instruction causes an EPT extended page table violation due to a specific element all previous elements should be complete Due to this erratum such an execution may fail to complete previous elements In addition the instruction s mask operand is not updated This erratum applies only if the EPT violation occurs while updating an accessed or dirty flag in a paging structure entry Instructions impacted by this erratum are VGATHERDPS VGATHERDPD VGATHERQPS VGATHERQPD VPGATHERDD VPGATHERDQ VPGATHERQD and VPGATHERQQ This erratum may prevent a gather instruction from making forward progress It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update HSD35 Problem Implication Workaround Status HSD36 Problem Implication Workaround Status HSD37 Problem Implication Workaround Status HSD38 Problem Implication Workaround Status HSD39 Problem Implication Workaround Status PLATFORM_POWER_LIMIT MSR Not Visible
45. ftware programs in MSR IA32_PMC1 47 0 in order to control interrupt frequency Due to this erratum when using low SAV values the program may get incorrect PEBS or PMI interrupts and or an invalid counter state The sampling driver should avoid using SAV lt 100 For the steppings affected see the Summary Table of Changes CRO CD Is Ignored in VMX Operation If CRO CD 1 the MTRRs and PAT should be ignored and the UC memory type should be used for all memory accesses Due to this erratum a logical processor in VMX operation will operate as if CRO CD 0 even if that bit is set to 1 Algorithms that rely on cache disabling may not function properly in VMX operation Algorithms that rely on cache disabling should not be executed in VMX root operation For the steppings affected see the Summary Table of Changes Instruction Fetch May Cause Machine Check if Page Size and Memory Type Was Changed Without Invalidation This erratum may cause a machine check error IA32_MCi_STATUS MCACOD 0150H on the fetch of an instruction that crosses a 4 KByte address boundary It applies only if 1 the 4 KByte linear region on which the instruction begins is originally translated using a 4 KByte page with the WB memory type 2 the paging structures are later modified so that linear region is translated using a large page 2 MByte 4 MByte or 1 GByte with the UC memory type and 3 the instruction fetch occurs after the paging structure modification but
46. g Size tional Graphics Freq MHz Freq Power MB Core Cores Rate GHz W GHz SR147 17 4770K C 0 8 4 2 3 9 1600 3 5 95 SR149 17 4770 C 0 8 4 2 3 9 1600 3 4 95 SR14A 15 4670K C 0 6 4 2 3 8 1600 3 4 95 SR14D 15 4670 C 0 6 4 2 3 8 1600 3 4 95 SR14E 15 4570 C 0 6 4 2 3 6 1600 3 2 95 SR14F 15 4440 C 0 6 4 2 3 3 1600 3 1 95 SR14G 15 4430 C 0 6 4 2 3 2 1600 3 95 SR14H 17 4770S C 0 8 4 2 3 9 1600 3 1 65 SR14J 15 4570S C 0 6 4 2 3 6 1600 2 9 65 SR14K 15 4670S c 0 6 4 2 3 8 1600 3 1 65 SR14L 15 4440S C 0 6 4 2 3 3 1600 2 8 65 SR14M 15 4430S C 0 6 4 2 3 2 1600 2 7 65 SR14N 17 4770T c 0 8 4 2 3 7 1600 2 5 45 SR14P 15 4670T c 0 6 4 2 3 3 1600 2 3 45 SR14Q 17 4765T C 0 8 4 2 3 1600 2 35 Specification Update 15 intel Table 2 Desktop Processor Identification Sheet 2 of 2 max Thermal S Spec Processor Stepping Size tional Graphics Freq Memory Freq Design MB Core Cores Rate GHz W GHz SR18K 17 4770R C 0 6 4 3 3 9 1600 3 2 65 SR18M 15 4670R C 0 4 4 3 3 7 1600 3 65 SR18Q 15 4570R C 0 4 4 3 3 2 1600 2 7 65 SR1BW 17 4771 C 0 8 4 2 3 9 1600 3 5 95 SR1CA 15 4570T C 0 4 2 2 3 6 1600 2 9 35 SR1CE G3430 C 0 3 2 1 3 3 1600 3 3 65 SR1CG G3220 C 0 3 2 1 3 1333 3 65 SR1CL G3220T C 0 3 2 1 2 6 1333 2 6 35 SR1NB G3420 C 0 3 2 1 3 2 1333 3 2 65 SRINK 13 4330T C 0 4 2 2 3 1600 3 35 SR1NL 13 4340 C 0 4 2 2 3 6 1600 3 6 65 SR1NM 13 4330 C 0 4 2 2 3 5 1600 3 5 65 SR1NN 13 413
47. h apply to the processor Intel may fix some of the errata in a future stepping of the component and account for the other outstanding issues through documentation or specification changes as noted These tables uses the following notations Codes Used in Summary Tables Stepping X Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping No mark or Blank box This erratum is fixed in listed stepping or specification change does not apply to listed stepping Page Page Page location of item in this document Status Doc Document change or update will be implemented Plan Fix This erratum may be fixed in a future stepping of the product Fixed This erratum has been previously fixed No Fix There are no plans to fix this erratum Row Change bar to left of a table row indicates this erratum is either new or modified from the previous version of the document 8 Specification Update Errata Sheet 1 of 5 Steppings Number Status ERRATA c 0 n LBR BTS BTM May Report a Wrong Address when an Exception HSDI x none Interrupt Occurs in 64 bit Mode EFLAGS Discrepancy on Page Faults and on EPT Induced VM Exits after HSD No EIK a Translation Change n MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a HSD3 x No Fix DTLB Error HSD4 x No Fix LER MSRs May Be Unreliabl
48. he guest physical address field in the VMCS Software may not be easily able to determine the page offset of the original memory access that caused the EPT violation Intel has not observed this erratum to impact the operation of any commercially available software Software requiring the page offset of the original memory access address can derive it by simulating the effective address computation of the instruction that caused the EPT violation For the steppings affected see the Summary Table of Changes APIC Timer Might Not Signal an Interrupt While in TSC Deadline Mode If the APIC timer is in TSC deadline mode and is armed when a timed MWAIT instruction is executed the timer expiration might not cause an interrupt Software depending on APIC timer TSC deadline mode interrupts may not behave as expected It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update HSD70 Problem Implication Workaround Status HSD71 Problem Implication Workaround Status HSD72 Problem Implication Workaround Status HSD73 Problem Implication Workaround IA32_VMX_VMCS_ENUM MSR 48AH Does Not Properly Report The Highest Index Value Used For VMCS Encoding IA32_VMX_VMCS_ENUM MSR 48AH bits 9 1 report the highest index value used for any VMCS encoding Due to this erratum the value 21 is
49. he BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update 29 HSD49 Problem Implication Workaround Status HSD50 Problem Implication Workaround Status HSD51 Problem Implication Workaround Status HSD52 Problem Implication Workaround Status 30 AVX Gather Instruction That Should Result in DF May Cause Unexpected System Behavior Due to this erratum an execution of a 128 bit AVX gather instruction may fail to generate a DF double fault when expected Instructions impacted by this erratum are VGATHERDPS VGATHERDPD VGATHERQPS VGATHERQPD VPGATHERDD VPGATHERDQ VPGATHERQD and VPGATHERQQ When this erratum occurs an operation which should cause a DF may result in unexpected system behavior It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Throttling and Refresh Rate Maybe be Incorrect After Exiting Package C State When the OLTM Open Loop Thermal Management feature is enabled the DIMM thermal status reported in DDR_THERM_PERDIMM_STATUS MCHBAR Offset 588CH may be incorrect following an exit from Package C3 or deeper The incorrect DIMM thermal status may result in degraded performance from unneeded memory throttling and excessive DIMM refresh rates It is possible for BIOS to contain a workaround for
50. he PCIe controller is enabled Bus 0 Device 0 Function 0 Offset 54h bits 2 1 11 then the processor will be unable to enter Package C6 or deeper C states Due to this erratum the process will not enter Package C6 or deeper C states It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Performance Monitor Event For Outstanding Offcore Requests And Snoop Requests May Over Count The performance monitor event OFFCORE_REQUESTS_OUTSTANDING Event 60H any Umask Value should count the number of offcore outstanding transactions each cycle Due to this erratum the counts may be higher than actual number of events The performance monitor events OFFCORE_REQUESTS_OUTSTANDING may reflect counts higher than the actual number of events None identified For the steppings affected see the Summary Table of Changes Specification Update HSD62 Problem Implication Workaround Status HSD63 Problem Implication Workaround Status HSD64 Problem Implication Workaround Status HSD65 Problem Implication Workaround Status Some Performance Monitor Event Counts May be Inaccurate During SMT Mode The performance monitor event OFFCORE_REQUESTS_OUTSTANDING Event 60H any Umask Value should count the number of occurrences that loads or stores stay in the super queue each cycle The performance monitor even
51. hin the processor s family 3 The Family Code corresponds to Bits 11 8 of the EDX register after RESET Bits 11 8 of the EAX register after the CPUID instruction is executed with a 1 in the EAX register and the generation field of the Device ID register accessible through Boundary Scan 4 The Model Number corresponds to Bits 7 4 of the EDX register after RESET Bits 7 4 of the EAX register after the CPUID instruction is executed with a 1 in the EAX register and the model field of the Device ID register accessible through Boundary Scan 5 The Stepping ID in Bits 3 0 indicates the revision number of that model See the processor Identification table for the processor stepping ID number in the CPUID information When EAX is initialized to a value of 1 the CPUID instruction returns the Extended Family Extended Model Processor Type Family Code Model Number and Stepping ID value in the EAX register Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register Cache and TLB descriptor parameters are provided in the EAX EBX ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register The processor can be identified by the following register contents Stepping Vendor ID dar pass i rir ss Revision ID CRID C 0 8086h 0C04h GT2 0416h 06h 06h Notes 1 The Vendor ID corresponds to bits 15 0 of
52. ication Workaround Status HSD61 Problem Implication Workaround Status 32 Performance Monitor Event DSB2MITE_SWITCHES COUNT May Over Count The Performance Monitor Event DSB2MITE_SWITCHES COUNT Event ABH Umask 01H should count the number of DSB Decode Stream Buffer to MITE Macro Instruction Translation Engine switches Due to this erratum the DSB2MITE_SWITCHES COUNT event will count speculative switches and cause the count to be higher than expected The Performance Monitor Event DSB2MITE_SWITCHES COUNT may report count higher than expected None identified For the steppings affected see the Summary Table of Changes Performance Monitor Register UNC_PERF_GLOBAL_STATUS Not Restored on Package C7 Exit MSR_UNC_PERF_GLOBAL_STATUS 392H is a global status register which indicates the overflow of uncore performance monitor counters The content of this register is lost in package C7 state If any uncore performance monitor counter has overflowed before entering the package C7 state the MSR_UNC_PERF_GLOBAL_STATUS register will no longer reflect the overflow after exiting C7 state It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Processor May Not Enter Package C6 or Deeper C states When PCIe Links Are Disabled If the PCIe links are disabled via Link Disable Bus 0 Device 1 Functions 2 1 Offset BOh bit 4 and t
53. ies None identified For the steppings affected see the Summary Table of Changes PMI May be Signaled More Than Once For Performance Monitor Counter Overflow Due to this erratum PMI Performance Monitoring Interrupt may be repeatedly issued until the counter overflow bit is cleared in the overflowing counter Multiple PMIs may be received when a performance monitor counter overflows None identified If the PMI is programmed to generate an NMI software may delay the EOI end of Interrupt register write for the interrupt until after the overflow indications have been cleared For the steppings affected see the Summary Table of Changes Specification Update 39 HSD92 Problem Implication Workaround Status HSD93 Problem Implication Workaround Status HSD94 Problem Implication Workaround Status HSD95 Problem Implication Workaround Status HSD96 Problem Implication Workaround Status 40 Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a NM Exception Attempt to use FXSAVE or FXRSTOR with a VEX prefix should produce a UD Invalid Opcode exception If either the TS or EM flag bits in CRO are set a NM device not available exception will be raised instead of UD exception Due to this erratum a NM exception may be signaled instead of a UD exception on an FXSAVE or an FXRSTOR with a VEX prefix Software should not use FXSAVE
54. ld GP at PFAT launch Due to this erratum a GP fault may not be generated A PFAT module that does not follow the PFAT module base address requirements may result in unpredictable system behavior It is possible for the BIOS to contain a workaround for this issue For the steppings affected see the Summary Table of Changes Specification Update 41 HSD101 Problem Implication Workaround Status HSD102 Problem Implication Workaround Status HSD103 Problem Implication Workaround Status HSD104 Problem Implication Workaround Status 42 Incorrect LBR Source Address May be Reported For a Transactional Abort If the fetch of an instruction in a transactional region causes a fault a transactional abort occurs If LBRs are enabled the source address recorded for such a transactional abort is the address of the instruction being fetched If that instruction was itself the target of an earlier branch instruction this erratum may erroneously record the address of the branch instruction as the source address for the transactional abort Trace reconstruction software that uses LBR information may fail when this erratum occurs None identified For the steppings affected see the Summary Table of Changes Address Translation Faults for Intel VT d May Not be Reported for Display Engine Memory Accesses The Intel VT d Intel Virtualization Technology for Directed I O hard
55. m a timer interrupt may be delivered even if the CCR is 0 and the LVT and IRR bits are read as 0 This can occur only if the DCR Divide Configuration Register is greater than or equal to 4 The erratum does not occur if software writes zero to the Initial Count Register before reading the LVT and IRR bits Software that relies on reads of the LVT and IRR bits to determine whether a timer interrupt is being delivered may not operate properly Software that uses the local APIC timer must be prepared to handle the timer interrupts even those that would not be expected based on reading CCR and the LVT and IRR bits alternatively software can avoid the problem by writing zero to the Initial Count Register before reading the LVT and IRR bits For the steppings affected see the Summary Table of Changes Specification Update 21 HSD17 Problem Implication Workaround Status HSD1i8 Problem Implication Workaround Status HSD19 Problem Implication Workaround Status HSD20 Problem Implication Workaround Status 22 PCIe Root port Initiated Compliance State Transmitter Equalization Settings May be Incorrect If the processor is directed to enter PCIe Polling Compliance at 5 0 GT s or 8 0 GT s transfer rates it should use the Link Control 2 Compliance Preset De emphasis field bits 15 12 to determine the correct de emphasis level Due to this erratum when the processor is directed
56. ment Title Document Number Location AP 485 Intel Processor Identification and the CPUID Instruction http www intel com design processor appInots 241618 htm Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference Manual A M Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide Intel 64 and IA 32 Intel Architecture Optimization Reference Manual http www intel com products processor manuals index htm Intel 64 and IA 32 Architectures Software Developer s Manual Documentation Changes http www intel com design processor specupdt 252046 htm ACPI Specifications www acpi info Specification Update intel Nomenclature Note Specification Update Errata are design defects or errors These may cause the processor behavior to deviate from published specifications Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices S Spec Number is a five digit code used to identify products
57. mpliant PFAT Module Base Address May Cause Unpredictable System Behavior HSD101 x No Fix Incorrect LBR Source Address May be Reported For a Transactional Abort HSD102 x No Fix Address Translation Faults for Intel VT d May Not be Reported for Display Engine Memory Accesses HSD103 x No Fix ao Corrected Error Count May be Inaccurate After Package C7 HSD104 X No Fix PCle Device s SVID is Not Preserved Across The Package C7 C State HSD105 X No Fix Warm Reset Does Not Stop GT Power Draw HSD106 X No Fix Unused PCle Lanes May Remain Powered After Package C7 HSD107 X No Fix BMI1 And BMI2 Instruction Groups Are Not Available HSD108 x No Fix Virtual APIC Page Accesses With 32 Bit PAE Paging May Cause a System Crash HSD109 X No Fix Processor Energy Policy Selection May Not Work as Expected 12 Specification Update Errata Sheet 5 of 5 Steppings Number Status ERRATA C 0 HSD110 x No Fix A PEBS Record May Contain Processor State for an Unexpected Instruction HSD111 X No Fix MSR_PP1_ENERGY_STATUS Reports Incorrect Energy Data HSD112 x No Fix x87 FPU DP May be Incorrect After Instructions That Save FP State to Memory HSD113 X No Fix Processor May Hang During Package C7 Exit HSD114 X No Fix Intel TSX Instructions May Cause Unpredictable System behavior HSD115 X No Fix Spurious LLC Machine Check May Occur HSD116 X No Fix Page Fault May Report Incorrect Fault Information HSD117 X No Fix CAT
58. ncorrect HSD83 X No Fix Transactional Abort May Produce an Incorrect Branch Record A SMRAM State Save Area Above the 4GB Boundary May Cause ad x Mo BIK Unpredictable System Behavior A DMA Remapping Faults for the Graphics VT d Unit May Not Properly HEDES No ED Report Type of Faulted Request HSD86 x No Fix AVX Gather Instructions Page Faults May Report an Incorrect Faulting Address HSD87 X No Fix Intel TSX Instructions May Cause Unpredictable System behavior HSD88 X No Fix Event Injection by VM Entry May Use an Incorrect B Flag for SS HSD89 X No Fix A Fault in SMM May Result in Unpredictable System Behavior F Processor Frequency is Unexpectedly Limited Below Nominal P1 When AN j No Fix STDP Down is Enabled HSD91 x No Fix PMI May be Signaled More Than Once For Performance Monitor Counter Overflow Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a HSD92 X No Fix NM Exception HSD93 x No Fix n Execution in a Transactional Region May Cause a System HSD94 X No Fix Uncore Clock Frequency Changes May Cause Audio Video Glitches Processor May Experience a Spurious LLC Related Machine Check HSD95 A No Fix During Periods of High Activity HSD96 X No Fix The Processor May Not Enter Package C7 When Using a PSR Display HSD97 X No Fix Video Audio Distortion May Occur HSD98 X No Fix System May Hang When Audio is Enabled During Package C3 HSD99 X No Fix INVPCID May Not Cause UD in VMX Non Root Operation HSD100 x No Fix Non Co
59. on visit http www intel com info em64t Intel Intel Core Intel386 Intel486 Pentium and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2013 Intel Corporation All rights reserved 2 Specification Update Contents i n t el j Contents Revision Misto ili y dann ka kin E ea dun d k nek di kaka bek ii dea piesa kak 5 PROTAGG ci ix 3040515 ey x e ber n e hakan k H ne dra n bu an had Pkk wa kek a aA deka Pek wa y e Ki RR test 6 Summary Tables of Changes i EEE kk kk kek Ek kk KEK KAKA KAK KAKA KA AA 8 Identification Information LL EEE EEE kk kk kk KE KAK kk KA KAKA KA 14 DL Rene Pe rrr rr r rrr 17 Specification Chan ges EEE kk kak kek kk K k KA KAK kK KAK AKA KRA KAKA KIRA 47 Specification Clarifications c lcl danka iiaia deku lk d k kal ulan ene anaa 48 Documentation Changes L Ek kk kk kek kk KA Kek KK KAK KK KA KA KA A KIR 49 Specification Update 3 Contents Specification Update Revision History Revision Description Date 001 Initial Release June 2013 002 No Updates Revision number added to Revision History to maintain N A consistency with NDA Specification Update numbering Errata 003 Added HSD59 99 August 2013 Updated Identification Information 004 No
60. or to Hang If a PCIe device sends an LTR Latency Tolerance Report update message while the processor is in a package C6 or deeper the processor may hang Due to this Erratum the processor may hang if a PCIe LTR update message is received while in a Package C6 or deeper It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes GETSEC Does Not Report Support For S CRTM Processors with Intel Boot Guard Technology that has GETSEC PARAMETERS leaf 5 EAX bit 5 set indicates support for processor rooted S CTRM Static Core Root of Trust for Measurement Due to this erratum that bit will not be set even though processor rooted S CRTM is supported Software may be unaware of support for processor rooted S CTRM It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes EPT Violations May Report Bits 11 0 of Guest Linear Address Incorrectly If a memory access to a linear address requires the processor to update an accessed or dirty flag in a paging structure entry and if that update causes an EPT violation the processor should store the linear address into the guest linear address field in the VMCS Due to this erratum the processor may store an incorrect value into bits 11 0 of this field The processor correctly stores the guest physical address of the paging structure entry into t
61. oring events MEM_TRANS_RETIRED LOAD_LATENCY Event CDH Umask 01H MEM_LOAD_RETIRED L2_HIT Event D1H Umask 02H and MEM_UOPS_RETIRED LOCKED Event DOH Umask 20H should count the number of locked loads Due to this erratum these events may under count for locked transactions that hit the L2 cache The above event count will under count on locked loads hitting the L2 cache None identified For the steppings affected see the Summary Table of Changes Graphics Processor Ratio And C State Transitions May Cause a System Hang If ratio or C state changes involving the processor core and processor graphics occur at the same time or while processor graphics are active under certain internal conditions the ratio change may not complete The system may hang during C state or ratio changes It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update HSD78 Problem Implication Workaround Status HSD79 Problem Implication Workaround Status HSD80O Problem Implication Workaround Status HSD81 Problem Implication Workaround Status intel Certain Performance Monitoring Events May Over Count Software Demand Loads The following performance monitor events should count the number of software demand loads However due to this erratum they may also include requests from the Next Page Pref
62. pectedly shut down instead of executing the machine check handler None identified Software should clear IA32_MCi_STATUS MSRs as early as possible to minimize the possibility of this erratum occurring For the steppings affected see the Summary Table of Changes Specification Update HSD28 Problem Implication Workaround Status HSD29 Problem Implication Workaround Status HSD30 Problem Implication Workaround Status intel Modified Compliance Patterns for 2 5 GT s and 5 GT s Transfer Rates Do Not Follow PCIe Specification The PCIe controller does not produce the PCIe specification defined sequence for the Modified Compliance Pattern at 2 5 GT s and 5 GT s transfer rates This erratum is not seen at 8 GT s transfer rates Normal PCIe operation is unaffected by this erratum None identified For the steppings affected see the Summary Table of Changes Performance Monitor Counters May Produce Incorrect Results When operating with SMT enabled a memory at retirement performance monitoring event from the list below may be dropped or may increment an enabled event on the corresponding counter with the same number on the physical core s other thread rather than the thread experiencing the event Processors with SMT disabled in BIOS are not affected by this erratum The list of affected memory at retirement events is as follows MEM_UOP_RETIRED LOADS MEM_UOP_RETIRED STORES MEM_UOP_
63. ppings affected see the Summary Table of Changes Performance Monitoring Events May Report Incorrect Number of Load Hits or Misses to LLC The following performance monitor events should count the numbers of loads hitting or missing LLC However due to this erratum The L3_hit related events may over count and the L3_miss related events may undercount MEM_LOAD_RETIRED L3_HIT Event D1H Umask 40H MEM_LOAD_RETIRED L3_MISS Event D1H Umask 20H MEM_LOAD_L3_HIT_RETIRED XSNP_NONE Event D2H Umask 08H MEM_LOAD_LLC_MISS_RETIRED LOCAL_DRAM Event D3H Umask 01H The listed performance monitoring events may be inaccurate None identified For the steppings affected see the Summary Table of Changes Performance Monitoring Event INSTR_RETIRED ALL May Generate Redundant PEBS Records For an Overflow Due to this erratum the performance monitoring feature PDIR Precise Distribution of Instructions Retired for INSTR_RETIRED ALL Event COH Umask 01H will generate redundant PEBS Precise Event Based Sample records for a counter overflow This can occur if the lower 6 bits of the performance monitoring counter are not initialized or reset to 0 in the PEBS counter reset field of the DS Buffer Management Area The above event count will under count on locked loads hitting the L2 cache None identified For the steppings affected see the Summary Table of Changes Locked Load Performance Monitoring Events May Under Count The performance monit
64. r logic required for memory traffic may be powered down When this erratum occurs the processor logic required for audio memory traffic may not be operational resulting in a system hang It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes INVPCID May Not Cause UD in VMX Non Root Operation The INVPCID instruction should cause an invalid opcode exception UD in VMX non root operation if either bit 31 of the primary processor based VM execution controls activate secondary controls or bit 12 of the secondary processor based VM execution controls enable INVPCID is 0 Due to this erratum the INVPCID instruction will not cause UD if activate secondary controls is 0 and enable INVPCID is 1 Instead the instruction will either execute normally or cause a VM exit if the INVLPG exiting VM execution control is 1 The processor may cause a VM exit that software does not expect Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Table of Changes Non Compliant PFAT Module Base Address May Cause Unpredictable System Behavior PFAT Platform Firmware Armoring Technology requires the PFAT module base address be 256KB aligned and reside in the first 4GB of memory If BIOS does not comply with these requirements when setting up the PFAT module the processor shou
65. rratum an incoming illegal vector error may not be logged into ESR properly and may not generate an error interrupt None identified For the steppings affected see the Summary Table of Changes Changing the Memory Type for an In Use Page Translation May Lead to Memory Ordering Violations Under complex microarchitectural conditions if software changes the memory type for data being actively used and shared by multiple threads without the use of semaphores or barriers software may see load operations execute out of order Memory ordering may be violated Intel has not observed this erratum with any commercially available software Software should ensure pages are not being actively used before requesting their memory type be changed For the steppings affected see the Summary Table of Changes Specification Update 19 HSD11 Problem Implication Workaround Status HSD12 Problem Implication Workaround Status HSD13 Problem Implication Workaround Status 20 Performance Monitor Precise Instruction Retired Event May Present Wrong Indications When the PDIR Precise Distribution for Instructions Retired mechanism is activated INST_RETIRED ALL event COH umask value 00H on Counter 1 programmed in PEBS mode the processor may return wrong PEBS PMI interrupts and or incorrect counter values if the counter is reset with a SAV below 100 Sample After Value is the counter reset value so
66. ry Requirements Under certain conditions the processor may incorrectly calculate the frequency at which the cores and graphics engine can operate while still meeting voltage regulator and power supply peak power delivery capabilities When this occurs combined with high power workloads system shutdown may be observed When this erratum occurs system shutdown may be observed under high power workloads It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes IA32_PERF_CTL MSR is Incorrectly Reset The IA32_PERF_CTL MSR 199H is not initialized correctly after a processor reset If software reads the IA32_PERF_CTL MSR before writing it software can observe an incorrect reset value Although incorrect values are reported to software the correct default values for this register are still used by the processor No performance or power impact occurs due to this erratum It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Processor May Hang During a Function Level Reset of the Display When package C States are enabled it is possible that the processor may hang when software performs a Function Level Reset of the display via bit 1 of the Advanced Features Control Register Bus 0 Device 2 Function 0 Offset OA8H When this erratum occurs the processor may hang It is possible for t
67. s these would describe the read modify write instruction s memory access instead of that of the faulting instruction The address of the faulting instruction is reported correctly The erratum makes it appear that the page fault resulted from an access that occurred prior to the faulting instruction Because the earlier access completed without faulting a page fault handler may identify the page fault as transient or spurious and re execute the faulting instruction e g by executing IRET In such cases the erratum will not recur the page fault on the later access will recur and will be reported correctly If the page fault handler does not re execute the faulting instruction this erratum may result in unpredictable system behavior Intel has not observed this erratum with any commercially available software None identified For the steppings affected see the Summary Table of Changes CATERR Pin Assertion is Not Cleared on a Warm Reset If the CATERR pin is held asserted to indicate a fatal error a subsequent warm reset event will not cause the CATERR pin to de assert When this erratum occurs platforms that monitor the CATERR pin may be unable to detect a fatal error after a warm reset or may incorrectly respond to a CATERR pin assertion although an error may not have occurred subsequent to the warm reset event The CATERR pin can be de asserted by a cold reset event For the steppings affected see the Summary Table o
68. s do not match None identified For the steppings affected see the Summary Table of Changes Warm Reset May Fail or Lead to Incorrect Power Regulation Due to this erratum after a warm reset the processor may fail to boot properly or may cause power to be regulated to an incorrect level The processor may not be able to control the VR Voltage Regulator to advertised specifications leading to in a system hang a machine check or improper power regulation It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Specification Update 37 HSD82 Problem Implication Workaround Status HSD83 Problem Implication Workaround Status HSD84 Problem Implication Workaround Status HSD85 Problem Implication Workaround Status HSD86 Problem Implication Workaround Status 38 PCIe Host Bridge DID May Be Incorrect The PCIe Host Bridge DID register Bus 0 Device 0 Function 0 Offset 2H contents may be incorrect Software that depends on the Host Bridge DID value may not behave as expected It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Transactional Abort May Produce an Incorrect Branch Record If an Intel TSX transactional abort event occurs during a string instruction the From IP in the LBR
69. t CYCLE_ACTIVITY CYCLES_L2_ PENDING Event A3H Umask 01H should count the number of cycles that demand loads stay in the super queue However due to this erratum these events may count inaccurately during SMT mode The performance monitor events OFFCORE_REQUESTS_OUTSTANDING and CYCLE_ACTIVITY L2_ PENDING may be unreliable during SMT Mode None identified For the steppings affected see the Summary Table of Changes Timed MWAIT May Use Deadline of a Previous Execution A timed MWAIT instruction specifies a TSC deadline for execution resumption If a wake event causes execution to resume before the deadline is reached a subsequent timed MWAIT instruction may incorrectly use the deadline of the previous timed MWAIT when that previous deadline is earlier than the new one A timed MWAIT may end earlier than expected It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes The Upper 32 Bits of CR3 May be Incorrectly Used With 32 Bit Paging When 32 bit paging is in use the processor should use a page directory located at the 32 bit physical address specified in bits 31 12 of CR3 the upper 32 bits of CR3 should be ignored Due to this erratum the processor will use a page directory located at the 64 bit physical address specified in bits 63 12 of CR3 The processor may use an unexpected page directory or if EPT Extended Page Tables is in use cause an unexpecte
70. t Support For S CRTM HSD68 x No Fix EPT Violations May Report Bits 11 0 of Guest Linear Address Incorrectly HSD69 x No Fix APIC Timer Might Not Signal an Interrupt While in TSC Deadline Mode IA32_VMX_VMCS_ENUM MSR 48AH Does Not Properly Report The JER x No Fix Highest Index Value Used For VMCS Encoding Incorrect FROM_IP Value For an RTM Abort in BTM or BTS May be HSD71 X No Fix Obsened HSD72 x No Fix VT d Hardware May Perform STRP And SIRTP Operations on a Package C7 Exit HSD73 X No Fix General Purpose Performance Counters Can Unexpectedly Increment HSD74 x No Fix Performance Monitoring Events May Report Incorrect Number of Load Hits or Misses to LLC Performance Monitoring Event INSTR_RETIRED ALL May Generate FSDZ9 a Noti Redundant PEBS Records For an Overflow HSD76 X No Fix Locked Load Performance Monitoring Events May Under Count HSD77 x No Fix el Processor Ratio And C State Transitions May Cause a System Certain Performance Monitoring Events May Over Count Software HSD78 x No Fix Mamand leads 3 Accessing Nonexistent Uncore Performance Monitoring MSRs May Not HSD79 x No Fix Signal a GP HSD80 X No Fix Call Stack Profiling May Produce Extra Call Records HSD81 x No Fix Warm Reset May Fail or Lead to Incorrect Power Regulation 11 intel Errata Sheet 4 of 5 Steppings Number Status ERRATA C 0 HSD82 X No Fix PCle Host Bridge DID May Be I
71. table without software performing an appropriate TLB invalidation When a subsequent access to that address by a specific instruction ADD AND BTC BTR BTS CMPXCHG DEC INC NEG NOT OR ROL ROR SAL SAR SHL SHR SHLD SHRD SUB XOR and XADD causes a page fault or an EPT induced VM exit the value saved for EFLAGS may incorrectly contain the arithmetic flag values that the EFLAGS register would have held had the instruction completed without fault or VM exit For page faults this can occur even if the fault causes a VM exit or if its delivery causes a nested fault None identified Although the EFLAGS value saved by an affected event a page fault or an EPT induced VM exit may contain incorrect arithmetic flag values Intel has not identified software that is affected by this erratum This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit If the handler of the affected events inspects the arithmetic portion of the saved EFLAGS value then system software should perform a synchronized paging structure modification and TLB invalidation For the steppings affected see the Summary Table of Changes MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error A single Data Translation Look Aside Buffer DTLB error can incorrectly set the Overflow bit 62 in the MCi_Status r
72. the Vendor ID Register located at offset 00h 01h in the PCI function 0 configuration space 2 The Host Device ID corresponds to bits 15 0 of the Device ID Register located at Device 0 offset 02h 03h in the PCI function 0 configuration space 3 The Processor Graphics Device ID DID2 corresponds to bits 15 0 of the Device ID Register located at Device 2 offset 02h 03h in the PCI function 0 configuration space 4 The Revision Number corresponds to bits 7 0 of the Revision ID Register located at offset 08h in the PCI function 0 configuration space 14 Specification Update Component Marking Information intel The processor stepping can be identified by the following component markings Figure 1 Desktop 4th Generation Intel Core Processor Family Top Side Markings Sample QDF GRP1LINE1 i M C YY GRP1LINE2 INTEL CONFIDENTIAL GRP1LINE1 GRP1LINE3 QDF ES SPEED GRP 1LINEZ EST GRP1LINE4 XXXXX GRP 1LINE4 GRP1LINES5 FPO e4 GRP 1LINES Production SSPEC GRP1LINE1 i M C YY GRP1LINE2 SUB BRAND PROC GRP1LINE3 SSPEC SPEED Pkg Size 37 5mm x 37 5mm GRP1LINE4 XXXXX Pin Count 1150 GRP1LINES5 FPO e4 FOL Mark 2D Matrix and Human Readable Serial 4 characters XXXXX Country of Origin Table 2 Desktop Processor Identification Sheet 1 of 2 Max S Spec Processer Cache Func Integrated Turbo Memory Core eae rain cial Number Steppin
73. this erratum For the steppings affected see the Summary Table of Changes Processor May Livelock During On Demand Clock Modulation The processor may livelock when 1 a processor thread has enabled on demand clock modulation via bit 4 of the IA32_CLOCK_MODULATION MSR 19AH and the clock modulation duty cycle is set to 12 5 02H in bits 3 0 of the same MSR and 2 the other processor thread does not have on demand clock modulation enabled and that thread is executing a stream of instructions with the lock prefix that either split a cacheline or access UC memory Program execution may stall on both threads of the core subject to this erratum This erratum will not occur if clock modulation is enabled on all threads when using on demand clock modulation or if the duty cycle programmed in the IA32_CLOCK_MODULATION MSR is 18 75 or higher For the steppings affected see the Summary Table of Changes IA32_DEBUGCTL FREEZE_PERFMON_ON_PMLis Incorrectly Cleared by SMI FREEZE_PERFMON_ON_PMI bit 12 in the IA32_DEBUGCTL MSR 1D9H is erroneously cleared during delivery of an SMI system management interrupt As a result of this erratum the performance monitoring counters will continue to count after a PMI occurs in SMM system management Mode None identified For the steppings affected see the Summary Table of Changes Specification Update HSD53 Problem Implication Workaround Status HSD54 Problem Implication
74. to enter Polling Compliance from 2 5 GT s transfer rate it retains 2 5 GT s de emphasis values The processor may operate in Polling Compliance mode with an incorrect transmitter de emphasis level None identified For the steppings affected see the Summary Table of Changes PCIe Controller May Incorrectly Log Errors on Transition to RxLOs Due to this erratum if a link partner transitions to RxLOs state within 20 ns of entering LO state the PCIe controller may incorrectly log an error in Correctable Error Status Receiver Error Status field Bus 0 Device 2 Function 0 1 2 and Device 6 Function 0 offset 1DOH bit 0 Correctable receiver errors may be incorrectly logged Intel has not observed any functional impact due to this erratum with any commercially available add in cards None identified For the steppings affected see the Summary Table of Changes Unused PCIe Lanes May Report Correctable Errors Due to this erratum during PCIe link down configuration unused lanes may report a Correctable Error Detected in Bus 0 Device 1 Function 0 2 and Device 6 Function 0 Offset 158H Bit 0 Correctable Errors may be reported by a PCIe controller for unused lanes None identified For the steppings affected see the Summary Table of Changes Accessing Physical Memory Space 0 640K through the Graphics Aperture May Cause Unpredictable System Behavior The physical memory space 0 640K when accessed through the graphics
75. tus HSD111 Problem Implication Workaround Status HSD112 Problem Implication Workaround Status 44 Processor Energy Policy Selection May Not Work as Expected When the IA32_ENERGY_PERF_BIAS MSR 1BOH is set to a value of 4 or more the processor will try to increase the energy efficiency of Turbo mode However this functionality is effectively disabled if the software requested P state exceeds the maximum P state supported by the processer This has the effect of decreasing the energy efficiency of the processor while in Turbo mode When this erratum occurs reduced battery life and reduced energy efficiency may occur BIOS should set the max ACPI _PST object to the max supported turbo ratio ensuring that the software P state request does not exceed the maximum ratio supported by the processor Note that this workaround will disable Core Ratio Overclocking For the steppings affected see the Summary Table of Changes A PEBS Record May Contain Processor State for an Unexpected Instruction If a performance counter has overflowed and is configured for PEBS precise event based sampling the processor will arm the PEBS hardware within a bounded number of cycles called the skid see the discussion of skid and related topics in the Precise Distribution of Instructions Retired section of the Intel 64 and IA 32 Architectures Software Developer Manual Once the PEBS hardware is armed the processor should
76. uld not generate an interrupt Due to this erratum further interrupts may still occur Unexpected Invalidation Queue Error interrupts may occur Intel has not observed this erratum with any commercially available software Software should be written to handle spurious VT d fault interrupts For the steppings affected see the Summary Table of Changes N A Erratum has been removed AVX Gather Instruction That Causes a Fault or VM Exit May Incorrectly Modify Its Destination Register An execution of a 128 bit AVX gather instruction zeroes the upper 128 bits of the instruction s destination register unless access to the first unmasked element causes a fault or VM exit Due to this erratum these bits may be cleared even when accessing the first unmasked element causes a fault or VM exit Instructions impacted by this erratum are VGATHERDPS VGATHERDPD VGATHERQPS VGATHERQPD VPGATHERDD VPGATHERDQ VPGATHERQD and VPGATHERQQ Software that depends on the destination register of a 128 bit AVX gather instruction to remain unchanged after access of the first unmasked element results in fault or VM exit may not behave as expected It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Changes Inconsistent NaN Propagation May Occur When Executing V DPPS Instruction Upon completion of the V DPPS instruction with multiple different NaN encodings in the input elements softw
77. ure May Cause Unpredictable System Behavior HSD21 x No Fix PCle Root Port May Not Initiate Link Speed Change HSD22 x No Fix Pending x87 FPU Exceptions MF May be Signaled Earlier Than Expected DR6 B0 B3 May Not Report All Breakpoints Matched When a MOV POP MSDE No Fix SS is Followed by a Store or an MMX Instruction HSD24 X No Fix VEX L is Not Ignored with VCVT 2SI Instructions Certain Local Memory Read Load Retired PerfMon Events May HSD25 X No Fix Undercount Specification Update intel Errata Sheet 2 of 5 Steppings Number Status ERRATA C 0 a Specific Graphics Blitter Instructions May Result in Unpredictable MSD26 X Awak Graphics Controller Behavior HSD27 x No Fix Processor May Enter Shutdown Unexpectedly on a Second Uncorrectable Error Modified Compliance Patterns for 2 5 GT s and 5 GT s Transfer Rates Do HSD2 X No Fix Not Follow PCle Specification HSD29 X No Fix Performance Monitor Counters May Produce Incorrect Results HSD30 X No Fix Performance Monitor UOPS_EXECUTED Event May Undercount HSD31 X No Fix MSR_PERF_STATUS May Report an Incorrect Core Voltage PCle Atomic Transactions From Two or More PCle Controllers May HSD32 x Nori Cause Starvation The Corrected Error Count Overflow Bit in IA32_ MCO_STATUS is Not HSD33 x No Fix Updated After a UC Error is Logged An AVX Gather Instruction That Causes an EPT Violation May
78. ware unit supporting the Processor Graphics device Bus 0 Device 2 Function 0 may not report address translation faults detected on Display Engine memory accesses when the Context Cache is disabled or during time periods when Context Cache is being invalidated Due to this erratum Display Engine accesses that fault are correctly aborted but may not be reported in the FSTS_REG fault reporting register GFXVTDBAR offset 034H None identified For the steppings affected see the Summary Table of Changes L3 Cache Corrected Error Count May be Inaccurate After Package C7 Exit The corrected error count for L3 cache errors reported in I A32_MCi_STATUS Corrected Error Count bits 52 38 with an MCACOD of 0001 0001 xxxx xxxx x can be 0 or 1 may be incorrectly restored to a smaller value during exit from Package C7 The corrected error count for L3 cache errors in IA32_MCi_STATUS may be inaccurate after Package C7 exit None identified For the steppings affected see the Summary Table of Changes PCIe Device s SVID is Not Preserved Across The Package C7 C State Bus 0 Device 7 Function 0 s SVID register Subsystem Vendor Identification Offset 2CH is not preserved across package C7 C State transitions This may cause the operating system to think the device has been replaced with a different device It is possible for the BIOS to contain a workaround for this erratum For the steppings affected see the Summary Table of Chang
79. without relying on the root port to do so Due to this erratum the PCIe root port may not initiate a link speed change during some hardware scenarios causing the PCle link to operate at a lower than expected speed Intel has not observed this erratum with any commercially available platform None identified For the steppings affected see the Summary Table of Changes Pending x87 FPU Exceptions MF May be Signaled Earlier Than Expected x87 instructions that trigger MF normally service interrupts before the MF Due to this erratum if an instruction that triggers MF is executed while Enhanced Intel SpeedStep Technology transitions Intel Turbo Boost Technology transitions or Thermal Monitor events occur the pending MF may be signaled before pending interrupts are serviced Software may observe MF being signaled before pending interrupts are serviced None identified For the steppings affected see the Summary Table of Changes DR6 B0 B3 May Not Report All Breakpoints Matched When a MOV POP SS is Followed by a Store or an MMX Instruction Normally data breakpoints matches that occur on a MOV SS r m or POP SS will not cause a debug exception immediately after MOV POP SS but will be delayed until the instruction boundary following the next instruction is reached After the debug exception occurs DR6 BO0 B3 bits will contain information about data breakpoints matched during the MOV POP SS as well as breakpoints detected by the

Intel BX80646I54670K Computer Hardware User Manual

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