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Intel 8XC196NT Computer Hardware User Manual

1. 7 6 CAN Control CAN CON 7 7 CAN Bit Timing 0 BTIMEO 7 8 CAN Bit Timing 1 BTIME1 7 9 CAN Standard Global Mask SGMSK Register 7 10 CAN Extended Global Mask EGMSK Register 7 11 CAN Message 15 Mask MSK15 7 12 CAN Message Object x Configuration CAN MSGxCFG Register 7 13 CAN Message Object x Identifier MSGxIDO0 3 Register 7 14 CAN Message Object x Control 0 CAN MSGxCONO Register 7 15 CAN Message Object x Control 1 MSGxCON1 Register 7 16 CAN Message Object Data CAN MSGxDATAO 7 Registers 7 17 CAN Control CAN CON Register men nenea nenea 7 18 CAN Message Object x Control 0 CAN MSGxCONO Register 7 19 CAN Interrupt Pending INT 7 20 CAN Status STAT Register 2 7 21 CAN Message Object x Control 0 MSGxCONO Register 7 22 Receiving a Message for Message Objects 1 14 CPU Flow 7 23 Receiving a Message for Message Object 15 CPU Flow 7 24 Receiving a Message CAN Controller
2. 7 25 Transmitting a Message CPU 1 7 26 Transmitting a Message CAN Controller Flow ees 8 1 Clock GIFCUIT acia tene eii dei e ee 9 1 Modes 0 and Tirriings crier ertet 9 2 Chip Configuration 1 CCR1 10 1 Auto Programming Circuit essen A 1 87C196CB 84 PLCC 5 8XC196CB SUPPLEMENT Figure A 2 vi FIGURES 87C196CB 100 pin QFP Package intel CONTENTS TABLES Table Page 1 1 Related Documents inire ios 1 2 2 1 Features of the 8XC196NT and 87C196CB nenea nenea nenea ne 2 1 2 2 State Times at Various Frequencies 2 3 Relationships Between Input Frequency Clock Multiplier and State Times 2 5 3 1 Register File Memory 00 3 1 3 2 976196CB Memory Map hee a Rai 3 2 3 3 876196 Peripheral SFRs een 3 3 3 4 CAN Peripheral SERS 22 22 een 3 4 3 5 Selecting a Window of Peripheral 5 3 6 3 6 Selecting a Window of the Upper Register 3 7 3 7 Selecting a Window of Upper Register 3 8 3 8 WINDOWS 2 ra rl nn oh rer 3 9 3 9 WSR Sett
3. Hex Address Contents 1Ex7 1ExE Data Bytes 0 7 1Ex6 Message Configuration 1 2 1 5 Message Identifier 0 3 1Ex0 1Ex1 Message Control 0 1 x message object number in hexadecimal 7 3 2 1 Receive and Transmit Priorities The lowest numbered message object always has the highest priority regardless of the message identifier When multiple messages are ready to transmit the CAN controller transmits the mes sage from the lowest numbered message object first When multiple message objects are capable of receiving the same message the lowest numbered message object receives it For example if all identifier bits are masked message object 1 receives all messages 7 3 2 2 Message Acceptance Filtering The mask registers provide a method for developing an acceptance filtering strategy for a specific system Software can program the mask registers to require an exact match on specific identifier bits while masking don t care the remaining bits Without a masking strategy a message ob ject could accept only those messages with an identical message identifier With a masking strat egy in place a message object can accept messages whose identifiers are not identical The CAN controller filters messages by comparing an incoming message s identifier with that of an enabled internal message object The standard global mask register applies to messages with standard 11 610 identifiers while the extended gl
4. sese 7 23 7 5 3 2 Message Object Control Register 1 7 23 7 5 4 Programming the Message Object Data 7 23 7 6 ENABLING THE CAN INTERRUPTS nenea nenea nana 7 29 7 7 DETERMINING THE CAN CONTROLLER S INTERRUPT STATUS 7 32 7 8 FLOW DIAGRAMS 2 RC RED n eam a e bans 7 35 7 9 DESIGN CONSIDERATIONS curiosidad see al 7 41 7 9 1 Hardware Reset razi eR RT d mt eee co E IO ua aa 7 41 7 92 Software lnitialization ite a a aaa a a a e n a aa 7 41 7 9 3 BUSTO State 2 ohana ds ei 7 41 CHAPTER 8 SPECIAL OPERATING MODES 8 1 CLOCK GCIBGULTRY ee BE 8 1 CHAPTER 9 INTERFACING WITH EXTERNAL MEMORY 9 1 ADDRESS PINS iia a 9 1 9 2 BUS TIMING MODES uscar li data 9 1 CHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY 10 1 SIGNATURE WORD AND PROGRAMMING VOLTAGES eee 10 1 10 2 MEMORY MAP FOR SLAVE PROGRAMMING 10 1 10 3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMING 10 2 10 4 MEMORY MAP FOR SERIAL PORT 10 3 10 4 1 Selecting Bank 0 FF2000 FF7FFFH enma n 10 4 10 4 2 Selecting Bank 1 FF8000 FFFFFFH mmm aan n 10 4 APPENDIX A SIGNAL DESCRIPTIONS A 1 FUNCTIONAL GROUPINGS OF 6 A 1 A2 SIGNALE DESCRIPTIONS cuui etc ia e tu ett eos pecia A 3 DEFAU
5. 30 AD1 P3 1 SLP1 PBUS1 EJ 31 A18 EPORT 2 E 32 RESET 34 P2 5 HOLD 45 amp 48 Vss1 E 49 P0 0 ACHO 50 P0 1 ACH1 51 P0 2 ACH2 52 P0 3 ACH3 53 P2 3 BREQ 43 P2 6 HLDA CPVER ONCE 46 P2 0 TXD PVER 40 P2 4 INTOUT AINC EJ 44 ADO P3 0 SLPO PBUSO 33 P2 1 RXD PALE 41 2 2 EXTINT PROG 42 P2 7 CLKOUT PACT 47 P6 1 EPA9 COMP1 P6 0 EPA8 COMPO P1 0 EPAO T2CLK P1 1 EPA1 P1 2 EPA2 T2DIR P1 3 EPA3 P1 4 EPA4 P1 5 EPA5 P1 6 EPA6 P1 7 EPA7 Vss1 VREF ANGND P0 7 ACH7 PMODE3 P0 6 ACH6 PMODE2 P0 5 ACH5 PMODE1 P0 4 ACH4 PMODEO A2847 01 Figure A 1 87C196CB 84 pin PLCC Package A 2 intel SIGNAL DESCRIPTIONS 99 1 P3 1 PBUS1 98 FI AD2 P3 2 SLP2 PBUS2 97 E AD3 P3 3 SLP3 PBUS3 96 ADA P3 4 SLP4 PBUS4 95 AD5 P3 5 SLP5 PBUS5 94 FI AD6 P3 6 SLP6 PBUS6 93 FI AD7 P3 7 SLP7 PBUS7 100 A18 EPORT 2 90 El AD8 P4 0 PBUS8 89 EI AD9 P4 1 PBUS9 88 FI AD10 P4 2 PBUS10 87 AD11 P4 3 PBUS11 86 FI AD12 P4 4 PBUS12 85 FI AD13 P4 5 PBUS13 84 AD14 P4 6 PBUS14 83 015 P4 7 PBUS15 82 EI A16 EPORT O 81 EI A17 EPORT 1 NC P5 7 BUSWIDTH ADO P3 0 SLPO PBUSO P5 2 WR WRL SLPWR RESET P5
6. 5 5 7 8 7 3 CAN CONTROLLER OPERATION nenea nenea manea emana 7 4 7 3 1 Address ach ee ees EE TR e AAA 7 5 13 27 Message Objects eue A Se aa ta ee et 7 5 7 3 2 1 Receive and Transmit Priorities 7 6 7 3 2 2 Message Acceptance Filtering 2 7 6 7 3 3 Message Frames us A Ei 7 7 7 3 4 Error Detection and Management Logic 7 9 73 5 Bit Timing ciere ile atte 7 10 7 3 5 1 Bit Timing EQuations edet Dee oi RP HD e etude aped 7 12 7 4 CONFIGURING THE CAN CONTROLLER nenea nenne 7 13 7 4 1 Programming the CAN Control CAN CON Register 7 13 7 4 2 Programming the Bit Timing 0 CAN BTIMEO Register 7 15 7 4 8 Programming the Bit Timing 1 CAN 1 Register 7 16 87C196CB SUPPLEMENT intel 7 4 4 Programming a Message Acceptance Filter 7 17 7 5 CONFIGURING MESSAGE OBJECTS nenea nenea nennen 7 20 7 5 1 Specifying a Message Object s Configuration 7 21 7 5 2 Programming the Message Object Identifier 7 22 7 5 8 Programming the Message Object Control Registers 7 23 7 5 3 1 Message Object Control Register 0
7. 0 disable interrupts 1 enable interrupts When the IE bit is set an interrupt is generated only if the corresponding interrupt source s enable bit EIE or SIE in CAN_CON TXIE or RXIE in CAN_MSGx_CONO is also set If the IE bit is clear an interrupt request updates the CAN interrupt pending register but does not generate an interrupt 0 INIT Software Initialization Enable Figure 7 17 CAN Control CAN_CON Register Continued 7 30 intel CAN SERIAL COMMUNICATIONS CONTROLLER CAN MSGxCONO Address 1Ex0H x 1 F x 1 15 87C196CB Reset State Unchanged Program the CAN message object x control 0 CAN MSGxCONO register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt The least significant bit pair indicates whether an interrupt is pending This register consists of four bit pairs the most significant bit of each pair is in true form and the least significant bit is in complement form This format allows software to set or clear any bit with a single write operation without affecting the remaining bits 7 0 87C196CB MSGVAL MSGVAL TXIE TXIE RXIE RXIE INT PND INT Bit Bit Number Mnemonic Function 7 6 MSGVAL Message Object Valid 5 4 TXIE Transmit Interrupt Enable Receive message objects do not use this bit pair For transmit message
8. Locations 00E0 00FFH 00C0 00FFH 0080 00FFH ODEO ODFFH 6FH ODCO ODDFH 6EH PM ODAO ODBFH 6DH Pt 0D80 0D9FH 6CH 0D60 0D7FH 6BH 0D40 0D5FH 6AH SM 0D20 0D3FH 69H 0000 001 68H is OCEO 0CFFH 67H 0CCO 0CDFH 66H e 0 0 0 65H dl 0C80 0C9FH 64H 0C60 0C7FH 63H 0C40 0C5FH 62H Hil 0C20 0C3FH 61H i 0C00 0C1FH 60H i 87C196CB SUPPLEMENT Table 3 8 Windows intel WSR Value WSR Value WSR Value for Base Address for 32 byte Window for 64 byte Window 128 byte Window 00 0 00 0 0 0080 00FFH Peripheral SFRs 1FEOH f 1FCOH 7EH 1 7DH 1F80H 7CH 3EH 1FHt 1F60H 7BH 1F40H 7AH 3DH 1F20H 79H 1F00H 78H 3CH 1EH CAN Peripheral SFRs 1 77H 1ECOH 76H 3BH 1 75H 1E80H 74H 3AH 1DH 1E60H 73H 1E40H 72H 39H 1E20H 71H 1E00H 70H 38H 1CH Register RAM 1DEOH 6FH 1DCOH 6EH 37H 1DAOH 6DH 1D80H 6CH 36H 1BH 1D60H 6BH 1D40H 6AH 35H 1D20H 69H 1D00H 68H 34H 1AH 1 67 1CCOH 66H 33H 1 65H 1C80H 64H 32H 19H 1C60H 63H 1C40H 62H 31H 1C20H 61H 1C00H 60H 30H 18H Locations 1FE0 1FFFH contain memory mapped SFRs that cannot be accessed through a window Reading these locations through a window returns FFH writing these locations through a window has no effect intel Ta
9. Register arithmetic logic unit A part of the CPU that consists of the ALU the PSW the master PC the microcode engine a loop counter and six registers The difference between corresponding code transitions from different actual characteristics taken from the same converter on the same channel with the same temperature voltage and frequency conditions The amount of repeatability error depends on the comparator s ability to resolve very similar voltages and the extent to which random noise contributes to the error A memory location that is reserved for factory use or for future expansion Do not use a reserved memory location except to initialize it with FFH The number of input voltage levels that an A D converter can unambiguously distinguish between The number of useful bits of information that the converter can return A small 2 3 pF capacitor used in the A D converter circuitry to store the input voltage on the selected input channel intel sample delay sample delay uncertainty sample time sample time uncertainty sample window sampled inputs SAR set SFR SHORT INTEGER sign extension sink current GLOSSARY The time period between the time that A D converter receives the start conversion signal and the time that the sample capacitor is connected to the selected channel The variation in the sample delay The period of time that the sample window is open That is the length o
10. Yes TX REQ 1 A2594 01 Figure 7 22 Receiving a Message for Message Objects 1 14 CPU Flow 7 36 intel CAN SERIAL COMMUNICATIONS CONTROLLER Power Up All bits undefined MSGVAL 1 INT PND 0 RXIE Application specific Initialization NEWDAT 0 RMTPND 0 MSGLST 0 DIR 0 receive XTD Application specific ID Application specific MASK Application specific Process message contents INT PND 0 NEWDAT 0 and RMTPND 0 Process Restart Process A2597 02 Figure 7 23 Receiving a Message for Message Object 15 CPU Flow 7 37 87C196CB SUPPLEMENT intel Bus idle Yes No TX REQ 1 MSGLST 0 Received frame with same identifer as this message object Yes NEWDAT 0 Load identifer and control into buffer Send remote frame MSGLST 1 No Nm Transmission Store message successful 9 NEWDAT 1 TX REQ 0 RMTPND 0 Yes TX REQ 0 RMTPND 0 ue Yes Yes INT PND 1 INT PND 1 A2598 01 Figure 7 24 Receiving a Message CAN Controller Flow 7 38 intel CAN SERIAL COMMUNICATIONS CONTROLLER Power Up All bits undefined MSGVAL 1 INT PND 0 TXIE Application specific Initializati RXIE Application specific nittalization NEWDAT 0 RMTPND 0 TX_REQ 0 MSGLST 0 DLC Application specific DIR 1 transmit
11. indicating that a receive or transmit interrupt request is pending 7 0 87C196CB Pending Interrupt Bit Number Function 7 0 Pending Interrupt This field indicates the source of the highest priority pending interrupt Value Pending Interrupt Priority 15 is highest 0 is lowest 00H none 01H status register 15 02H message object 15 14 03H message object 1 13 04H message object 2 12 05H message object 3 11 06H message object 4 10 07H message object 5 9 08H message object 6 8 09H message object 7 7 OAH message object 8 6 OBH message object 9 5 OCH message object 10 4 message object 11 3 OEH message object 12 2 OFH message object 13 1 10H message object 14 0 Figure 7 19 CAN Interrupt Pending CAN_INT Register If a status change generated the interrupt CAN_INT 01H software can read the CAN status register Figure 7 20 to determine the source of the interrupt request 7 32 intel CAN SERIAL COMMUNICATIONS CONTROLLER CAN STAT Address 1E01H 87C196CB Reset State XXH The CAN status CAN STAT register reflects the current status of the CAN peripheral 7 0 87C196CB BUSOFF WARN RXOK TXOK LEC2 LEC1 LECO Bit Bit Function Number Mnemonic 7 BUSOFF Bus off Status The CAN peripheral sets this read only bit to indicate that it has isolated itself from the CAN bus floated the TX pin because an error counter has reached 256 A bus off r
12. intel MEMORY PARTITIONS Table 3 3 87C196CB Peripheral SFRs Must be addressed as a word Ports 0 1 2 and 6 SFRs Timer 1 Timer 2 and EPA SFRs Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1FDEH Reserved Reserved F9EH TIMER2 H TIMER2 L 1FDCH Reserved Reserved 1F9CH Reserved T2CONTROL 1FDAH Reserved PO_PIN F9AH TIMER TIMER1 L 1FD8H Reserved Reserved 1F98H Reserved T1CONTROL 1FD6H P6 PIN P1 PIN 1F96H Reserved Reserved 1FD4H P6 REG P1 REG 1F94H Reserved Reserved 1FD2H P6 DIR P1 DIR 1F92H Reserved Reserved 1FDOH P6 MODE P1 MODE 1F90H Reserved Reserved 1FCEH P2 PIN Reserved EPA SFRs 1FCCH P2 REG Reserved Address High Odd Byte Low Even Byte 1FCAH P2 DIR Reserved F8bH COMP1 TIME COMP1 TIME L 1FC8H P2 MODE Reserved 1F8CH Reserved COMP1 CON 1FC6H Reserved Reserved 1F8AH COMPO TIME COMPO TIME L 1FC4H Reserved Reserved 1F88H Reserved COMPO CON 1FC2H Reserved Reserved 1F86H 9 TIME 9 TIME 1 1FCOH Reserved Reserved 1F84H Reserved EPA9_CON SIO and SSIO SFRs 1F82H EPA8_ TIME EPA8_TIME L Address High Odd Byte Low Even Byte 1F80H Reserved EPA8_CON 1FBEH Reserved Reserved 1F7EH EPA7_TIME H EPA7_TIME L 1FBCH SP_BAUD H SP_BAUD L 1F
13. nonvolatile memory npn transistor off isolation OTPROM p channel FET p type material PC PCCBs PIC Glossary 6 intel The maximum deviation of code transitions of the terminal based characteristic from the corre sponding code transitions of the ideal characteristic Interrupts that cannot be masked disabled and cannot be assigned to the PTS for processing The nonmaskable interrupts are unimplemented opcode software trap and NMI Read only memory that retains its contents when power is removed Many MCS 96 microcontrollers are available with either masked ROM EPROM or OTPROM Consult the Automotive Products Embedded Microcontrollers databook to determine which type of memory is available for a specific device A transistor consisting of one part p type material and two parts n type material The ability of an A D converter to reject isolate the signal on a deselected off output One time programmable read only memory Similar to EPROM but it comes in an unwindowed package and cannot be erased A field effect transistor with a p type conducting path Semiconductor material with introduced impurities doping causing it to have an excess of positively charged carriers Program counter Programming chip configuration bytes which are loaded into the chip configuration registers CCRs when the device is entering programming modes otherwise the CCBs are used Programmable interr
14. one bit of each pair is in true form and one is in complement form This format allows software to set or clear any bit with a single write operation without affecting the remaining bits Table 7 12 shows how to interpret the bit pair values Table 7 12 Control Register Bit pair Interpretation Access Type MSB LSB Definition 0 0 Not allowed indeterminate 0 1 Clear 0 Write 1 0 Set 1 1 1 No change 0 1 Clear 0 Read 1 Set 1 7 5 3 1 Message Object Control Register 0 Message object control register 0 Figure 7 14 indicates whether an interrupt is pending controls whether a successful transmission or reception generates an interrupt and indicates whether a message object is ready to transmit 7 5 3 2 Message Object Control Register 1 Message object control register 1 Figure 7 15 indicates whether the message object contains new data whether a message has been overwritten whether the message is being updated and whether a transmission or reception is pending Message objects 1 14 have only a single buffer so if a second message is received before the CPU reads the first the first message is overwritten Message object 15 has two alternating buffers so it can receive a second message while the first is being processed However if a third message is received while the CPU is reading the first the second message is overwritten 7 5 4 Programming the Message Object Da
15. 00C8H CAN_MSG5DATA1 1E58H 72H 00F8H 39H 00D8H 1CH 00D8H CAN_MSG6DATA1 1E68H 73H 00E8H 39H 00E8H 1CH 00E8H CAN_MSG7DATA1 1E78H 73H 00F8H 39H 00F8H 1CH 00F8H CAN_MSG8DATA1 1E88H 74H 00E8H 3AH 00C8H 1DH 0088H CAN MSG9DATA1 1E98H 74H 00F8H 3AH 00D8H 1DH 0098H CAN_MSG10DATA1 1EA8H 75H 00E8H 3AH 00E8H 1DH 00A8H MSG11DATA1 1EB8H 75H 00F8H 3AH 00F8H 1DH 00B8H CAN_MSG12DATA1 1EC8H 76H 00E8H 3BH 00C8H 1DH 00C8H CAN_MSG13DATA1 1ED8H 76H 00F8H 3BH 00D8H 1DH 00D8H CAN_MSG14DATA1 1EE8H 77H 00E8H 3BH 00E8H 1DH 00E8H CAN_MSG15DATA1 1EF8H 77H 00F8H 3BH 00F8H 1DH 00F8H CAN_MSG1DATA2 1E19H 70H 00F9H 38H 00D9H 1CH 0099H CAN_MSG2DATA2 1E29H 71H 00E9H 38H 00E9H 1CH 00A9H CAN MSG3DATA2 1E39H 71H 00F9H 38H 00F9H 1CH 00B9H CAN_MSG4DATA2 1E49H 72H 00E9H 39H 00C9H 1CH 00C9H CAN MSG5DATA2 1E59H 72H 00F9H 39H 00D9H 1CH 00D9H CAN MSG6DATA2 1E69H 73H 00E9H 39H 00E9H 1CH 00E9H CAN_MSG7DATA2 1E79H 73H 00F9H 39H 00F9H 1CH 00F9H CAN_MSG8DATA2 1E89H 74H 00E9H 3AH 00C9H 1DH 0089H CAN MSG9DATA2 1E99H 74H 00F9H 3AH 00D9H 1DH 0099H CAN_MSG10DATA2 1EA9H 75H 00E9H 3AH 00E9H 1DH 00A9H Must be addressed as a word 3 14 intel MEMORY PARTITIONS Table 3 9 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows Memory OOE0 00FFH 00CO O0FFH 0080 00FFH Register Mnemonic A L
16. 16 are multiplexed with EPORT 3 0 7 0 Analog Channels 0 7 These pins are analog inputs to the A D converter These pins may individually be used as analog inputs ACH or digital inputs PO x While it is possible for the pins to function simultaneously as analog and digital inputs this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results The ANGND and Vagr pins must be connected for the A D converter and port 0 to function ACH7 4 are multiplexed with 0 7 4 and PMODE 3 0 ACH3 0 are multiplexed with PO 3 0 AD15 0 Address Data Lines These pins provide a multiplexed address and data bus During the address phase of the bus cycle address bits 0 15 are presented on the bus and can be latched using ALE or ADV During the data phase 8 or 16 bit data is trans ferred AD7 0 are multiplexed with SLP7 0 P3 7 0 and PBUS 7 0 AD15 8 are multiplexed with P4 7 0 and PBUS 15 8 SIGNAL DESCRIPTIONS Table A 3 Signal Descriptions Continued Name Type Description ADV O Address Valid This active low output signal is asserted only during external memory accesses ADV indicates that valid address information is available on the system address data bus The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes An external latch can use this signal to demultiplex the
17. 38H 00E4H 1CH 00A4H CAN_MSG3ID2 1E34H 71H 00F4H 38H 00F4H 1CH 00B4H CAN_MSG4ID2 1E44H 72H 00E4H 39H 00C4H 1CH 00C4H CAN_MSG5ID2 1E54H 72H 00F4H 39H 00D4H 1CH 00D4H 5 6 2 1E64H 73H 00E4H 39H 00E4H 1CH 00E4H CAN_MSG7ID2 1E74H 73H 00F4H 39H 00F4H 1CH 00F4H CAN_MSG8ID2 1E84H 74H 00E4H 3AH 00C4H 1DH 0084H CAN_MSG9ID2 1E94H 74H 00F4H 3AH 00D4H 1DH 0094H CAN_MSG10ID2 1EA4H 75H 00E4H 3AH 00E4H 1DH 00A4H CAN_MSG11ID2 1EB4H 75H 00F4H 3AH 00F4H 1DH 00B4H CAN_MSG12ID2 1EC4H 76H 00E4H 3BH 00C4H 1DH 00C4H CAN_MSG13ID2 1ED4H 76H 00F4H 3BH 00D4H 1DH 00D4H MSG14ID2 1EE4H 77H 00E4H 3BH 00E4H 1DH 00E4H CAN_MSG15ID2 1EF4H 77H 00F4H 3BH 00F4H 1DH 00F4H CAN_MSG1ID3 1E15H 70H 00F5H 38H 00D5H 1CH 0095H CAN_MSG2ID3 1E25H 71H 00E5H 38H 00E5H 1CH 00A5H CAN_MSG3ID3 1E35H 71H 00F5H 38H 00F5H 1CH 00B5H Must be addressed as a word 3 18 intel MEMORY PARTITIONS Table 3 9 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows Memory OOE0 00FFH 00CO O0FFH 0080 00FFH Register Mnemonic Location WSR Direct WSR Direct WSR Direct Address Address Address CAN MSGAIDS 1E45H 72H 00E5H 39H 00C5H 1CH 00C5H CAN_MSG5ID3 1E55H 72H 00F5H 39H 00D5H 1CH 00D5H CAN_MSG6ID3 1E65H 73H 00E5H 39H 00E5H 1CH 00E5H CAN_MSG7ID3 1E75H 73H 00F5H 39H 00F5H 1CH 00F5H
18. 64 byte Windows 128 byte Windows Memor 00E0 00FFH 00C0 00FFH 0080 00FFH Register Mnemonic Location WSR Direct WSR Direct WSR Direct Address Address Address CAN_MSG7CONO 1E70H 73H 00FOH 39H 00FOH 1CH 00FOH CAN_MSG8CONO 1E80H 74H OOEOH 3AH 00COH 1DH 0080H CAN_MSG9CONO 1E90H 74H 00FOH 3AH 00DOH 1DH 0090H CAN_MSG10CONO 1 75 00 00 1DH 00A0H CAN MSG11CONO 1EBOH 75H OOFOH 3AH 00FOH 1DH 00BOH CAN_MSG12CONO 1ECOH 76H 00 3BH 00COH 1DH 00COH CAN_MSG13CONO 1EDOH 76H 00FOH 3BH 00DOH 1DH 00DOH CAN_MSG14CONO 1 77H 00 3BH 00 1DH OOEOH CAN_MSG15CONO 1EFOH 77H 00FOH 3BH 00FOH 1DH 00FOH CAN_MSG1CON1 1E11H 70H 00F1H 38H 00D1H 1CH 0091H CAN_MSG2CON1 1E21H 71H 00E1H 38H 00E1H 1CH 00A1H CAN_MSG3CON1 1E31H 71H 00 38H 00 1CH 00B1H CAN_MSG4CON1 1E41H 72H 00E1H 39H 00C1H 1CH 00C1H CAN_MSG5CON1 1E51H 72H 00F1H 39H 00D1H 1CH 00D1H CAN_MSG6CON1 1E61H 73H 00E1H 39H 00E1H 1CH 00E1H CAN_MSG7CON1 1E71H 73H 00F1H 39H 00F1H 1CH 00F1H CAN_MSG8CON1 1E81H 74H 00E1H 3AH 00C1H 1DH 0081H CAN_MSG9CON1 1E91H 74H 00F1H 3AH 00D1H 1DH 0091H CAN_MSG10CON1 1EA1H 75H 00E1H 3AH 00E1H 1DH 00A1H CAN_MSG11CON1 1EB1H 75H 00 00 1DH 00B1H CAN_MSG12CON1 1EC1H 76H 00E1H 3BH 00C1H 1DH 00C1H CAN_MSG13CON1 1ED1H 76H 00 3BH 00D1H 1DH 00D1H CAN_MSG14CON1 1EE1H 77H 00E1H 3BH 00E1H 1DH 00E1H CAN_MSG15
19. CAN_MSG8ID3 1E85H 74H 00E5H 3AH 00C5H 1DH 0085H CAN_MSG3ID3 1E95H 74H 00F5H 3AH 00D5H 1DH 0095H CAN_MSG10ID3 1EA5H 75H 00E5H 3AH 00E5H 1DH 00A5H CAN MSG11ID3 1EB5H 75H 00F5H 3AH 00F5H 1DH 00B5H CAN_MSG12ID3 1EC5H 76H 00E5H 3BH 00C5H 1DH 00C5H CAN_MSG13ID3 1ED5H 76H 00F5H 3BH 00D5H 1DH 00D5H CAN_MSG14ID3 1EE5H 77H 00E5H 3BH 00E5H 1DH 00E5H CAN_MSG15ID3 1EF5H 77H 00F5H 3BH 00F5H 1DH 00F5H CAN_MSK15 1E0CH 70H 00 38H 00CCH 1CH 008CH CAN SGMSK 1E06H 70H 00 6 38 00C6H 1CH 0086H CAN_STAT 1E01H 70H 00E1H 38H 00C1H 1CH 0081H COMPO CON 1F88H 7CH 00E8H 3EH 00C8H 1FH 0088H COMP1_CON 1F8CH 7CH 00 00CCH 1FH 008CH COMPO TIME 1F8AH 7CH 00 00 1 008 COMP1 TIME 1F8EH 7CH 00 00 1 008 EPA MASK 1FAOH 7DH 00 00 1 00A0H EPA MASK1 1FA4H 7DH 00E4H 3EH 00E4H 1FH 00A4H EPA_PEND 1FA2H 7DH 00E2H 3EH 00E2H 1FH 00A2H EPA_PEND1 1FA6H 7DH 00 6 00 6 1 00 6 0 1F60H 7BH 00 3DH 00E0H 1EH 00E0H EPA1_CON 1F64H 7BH 00E4H 3DH 00E4H 1EH 00E4H EPA2_CON 1F68H 7BH 00E8H 3DH 00E8H 1EH 00E8H EPA3 CON 1F6CH 7BH 00 3DH 00 00 EPA8 1F80H 7CH 00 00COH 1FH 0080H EPA9 CON 1F84H 7CH 00E4H 3EH 00C4H 1FH 0084H EPA9_TIME 1F86H 7CH 00 6 00C6H 1FH 0086H EPAO TIME 1F62H 7BH 00E2H 3DH 00E2H 1EH 00E2H EPA1 TIME 1F66H 7BH 00 6 3DH 00 6 00 6 Must be addressed as
20. CCR2 is loaded 7 0 MSEL1 MSELO 0 1 WDE BW1 IRC2 2 Bit Bit Number Mnemonic Function 7 6 MSEL1 0 External Access Timing Mode Select These bits control the bus timing modes MSEL1 MSELO 0 0 standard mode plus one wait state 0 1 reserved 1 0 reserved 1 1 standard mode 0 To guarantee proper operation write zero to this bit 1 To guarantee proper operation write one to this bit WDE Watchdog Timer Enable Selects whether the watchdog timer is always enabled or enabled the first time it is cleared 0 always enabled 1 enabled first time it is cleared 2 BW1 Buswidth Control This bit along with the BWO bit CCRO 1 selects the bus width BW1 BWO 0 0 illegal 0 1 16 bit only 1 0 8 bit only 1 1 BUSWIDTH pin controlled The CCRs are loaded with the contents of the chip configuration bytes CCBs after reset unless the microcontroller is entering programming modes in which case the programming chip configuration bytes PCCBs are used The CCBs reside in internal nonvolatile memory at addresses FF2018H CCBO FF201AH CCB1 and FF201CH CCB2 Figure 9 2 Chip Configuration 1 CCR1 Register 87C196CB SUPPLEMENT intel CCR1 Continued no direct access The chip configuration 1 CCR1 register enables the watchdog timer and selects the bus timing mode Two of its bits combine with three bits of CCRO to control wait states and bus width Another bit controls w
21. CONTROLLER CAN_EGMSK 87C196CB Address Reset State 1 1E0AH 1E09H 1E08H Unchanged Program the CAN extended global mask CAN_EGMSK register to mask don t care specific message identifier bits for extended message objects 31 24 87C196CB MSK4 MSK3 MSK2 MSK1 MSKO 23 16 MSK12 MSK11 MSK10 MSK9 MSK8 MSK7 MSK6 MSK5 15 8 MSK20 MSK19 MSK18 MSK17 MSK16 MSK15 MSK14 MSK13 7 0 MSK28 MSK27 MSK26 MSK25 MSK24 MSK23 MSK22 MSK21 ea iam Fonction 31 27 MSK4 0 ID Mask These bits individually mask incoming message identifier ID bits 0 mask the ID bit accept either 0 or 1 1 accept only an exact match 26 24 Reserved for compatibility with future devices write zeros to these bits 23 16 MSK12 5 ID Mask 5d ae ab These bits individually mask incoming message identifier ID bits 0 mask the ID bit accept either 0 or 1 1 accept only an exact match Figure 7 10 CAN Extended Global Mask CAN_EGMSK Register 87C196CB SUPPLEMENT intel CAN MSK15 Address 1EOFH 1E0EH 87C196CB 1E0DH 1 Reset State Unchanged Program the CAN message 15 mask CAN MSK15 register to mask don t care specific message identifier bits for message 15 in addition to those bits masked by a global mask CAN_EGMSK or CAN SGMSK 31 24 87C196CB MSK4 MSK3
22. Code Description 1F DATA High byte of address to DATA register F9 DATA Low byte of address to DATA register 0A DATA TO ADDR Move address from DATA register to ADDR register 00 SET DLE FLAG The next data byte is 1FH 00 DATA Data to clear the most significant bit 07 WRITE BYTE Move data from the DATA register to memory location 1FF9H 10 4 2 Selecting Bank 1 FF8000 FFFFFFH Send the following RISM command sequence to select bank 1 Code Description 1F DATA High byte of address to DATA register F9 DATA Low byte of address to DATA register 0A DATA TO ADDR Move address from DATA register to ADDR register 80 DATA Data to set the most significant bit 07 WRITE BYTE Move data from the DATA register to memory location 1FF9H 10 4 intel A Signal Descriptions APPENDIX A SIGNAL DESCRIPTIONS A 1 FUNCTIONAL GROUPINGS OF SIGNALS Table A 1 lists the signals for the 87C196CB grouped by function A diagram of each package that is currently available shows the pin location of each signal NOTE As new packages are supported they will be added to the datasheets first If your package type is not shown in this appendix refer to the latest datasheet to find the pin locations Table A 1 87C196CB Signals Arranged by Functional Categories Input Output Processor Control Bus Control amp Status EPORT 7 0 100 pin CB EA ALE
23. D CONVERTER AD_RESULT Read Address 1FAAH Reset State 7F80H The A D result AD_RESULT register consists of two bytes The high byte contains the eight most significant bits from the A D converter The low byte contains the two least significant bits from a ten bit A D conversion indicates the A D channel number that was used for the conversion and indicates whether a conversion is currently in progress 15 8 ADRLT9 ADRLT8 ADRLT7 ADRLT6 ADRLT5 ADRLT4 ADRLT3 ADRLT2 7 0 ADRLT1 ADRLTO STATUS ACH2 ACH1 ACHO Nano Function 15 6 ADRLT9 0 A D Result These bits contain the A D conversion result 5 4 Reserved These bits are undefined STATUS A D Status Indicates the status of the A D converter Up to 8 state times are required to set this bit following a start command When testing this bit wait at least the 8 state times 0 A D is idle 1 A D conversion is in progress 2 0 ACH2 0 A D Channel Number These bits indicate the A D channel number that was used for the conversion The 87C196CB has eight A D channel inputs numbered 0 7 Figure 6 2 A D Result AD_RESULT Register Read Format intel CAN Serial Communications Controller intel CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLER The 87C196CB has a peripheral not found in the 8XC196NT the CAN controller area net work peripheral The CAN serial communicatio
24. MSK2 MSK1 MSKO 23 16 MSK12 MSK11 MSK10 MSK9 MSK8 MSK7 MSK6 MSK5 15 8 MSK20 MSK19 MSK18 MSK17 MSK16 MSK15 MSK14 MSK13 7 0 MSK28 MSK27 MSK26 MSK25 MSK24 MSK23 MSK22 MSK21 Bit 3 Number Function 31 27 MSK4 0 ID Mask These bits individually mask incoming message identifier ID bits 0 mask the ID bit accept either O or 1 1 accept only an exact match 26 24 Reserved These bits are undefined for compatibility with future devices do not modify these bits 23 16 MSK12 5 ID Mask bd M GRON These bits individually mask incoming message identifier ID bits i 0 mask the ID bit accept either 0 or 1 1 accept only an exact match t Setting a CAN MSK15 bit in any position that is cleared in the global mask register has no effect The message 15 mask is ANDed with the global mask so any don t care bits defined in a global mask are also don t care bits for message 15 Figure 7 11 CAN Message 15 Mask CAN MSK15 Register 7 5 CONFIGURING MESSAGE OBJECTS Each message object consists of a configuration register a message identifier control registers and data registers from zero to eight bytes of data This section explains how to configure mes sage objects and determine their status 7 20 intel CAN SERIAL COMMUNICATIONS CONTROLLER 7 5 4 Specifying a Message Object s Configuration Each message object c
25. Programming Voltages esee 10 1 10 2 Slave Programming Mode Memory 2 220400440 0 10 2 10 3 Auto Programming Memory emere nennen 10 2 10 4 Serial Port Programming Mode Memory 10 4 A 1 87C196CB Signals Arranged by Functional A 1 A 2 Description of Columns of Table 3 A 4 A 3 Signal DeScriptiols ad ida A 4 A 4 Definition of Status Symbols 44 14 5 8 C196CB Pin Status sana Heeres et A 14 vii intel Guide to This Manual intel CHAPTER 1 GUIDE TO THIS MANUAL This document is a supplement to the 8XC196NT Microcontroller User s Manual It describes the differences between the 87C196CB and the 8XC196NT For information not found in this supplement please consult the 5XC 96NT Microcontroller User s Manual order number 272317 or the 87C196CB datasheet 87C196CA 87C196CB 20 MHz Advanced 16 Bit CHMOS Microcontroller with Integrated CAN 2 0 order number 272405 1 1 MANUAL CONTENTS This supplement contains several chapters an appendix a glossary and an index This chapter Chapter 1 provides an overview of the supplement This section summarizes the contents of the remaining chapters and appendixes The remainder of this chapter provides references to related documentation Chapter 2 Archi
26. This signal carries messages from other nodes on the CAN bus to the integrated CAN controller RXD 1 0 Receive Serial Data In modes 1 2 and 3 RXD receives serial port input data In mode 0 it functions as either an input or an open drain output for data is multiplexed with P2 1 and PALE SC1 0 1 0 Clock Pins for SSIOO and 1 For handshaking mode configure SC1 0 as open drain outputs This pin carries a signal only during receptions and transmissions When the SSIO port is idle the pin remains either high with handshaking or low without handshaking SCO is multiplexed with P6 4 and SC1 is multiplexed with P6 6 87C196CB Supplement Table A 3 Signal Descriptions Continued Name Type Description SD1 0 1 0 Data Pins for SSIOO and 1 SDO is multiplexed with P6 5 and SD1 is multiplexed with P6 7 SLP7 0 VO Slave Port Address Data bus Slave port address data bus in multiplexed mode and slave port data bus in demultiplexed mode In multiplexed mode is the source of the internal control signal SLP_ADDR SLP7 0 are multiplexed with AD7 0 P3 7 0 and PBUS 7 0 SLPALE Slave Port Address Latch Enable Functions as either a latch enable input to latch the value on SLP1 witha multiplexed address data bus or as the source of the internal control signal SLP_ADDR with a demultiplexed address data bus SLPALE is multiplexed with P5 0 ADV and ALE SLPCS Slave Port Ch
27. a standard I O port pin or as an extended address signal Setting a bit configures a pin as an extended address signal clearing a bit configures a pin as a standard I O port pin 7 0 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PINO Bit Bit s Number Mnemonic Function 7 0 PIN7 0 Extended Address Port Pin x Mode This bit determines the mode of EPORT x 0 standard l O port pin 1 extended address signal Figure 5 3 Extended Port Mode EP_MODE Register intel PORTS Address 1FE7H Reset State XXH Each bit of the extended port input EP_PIN register reflects the current state of the corresponding pin regardless of the pin configuration 7 0 PIN7 PING PINS PIN4 PINS PIN2 PIN1 PINO Bit Bit F ion Number Mnemonic Functio 7 0 PIN7 0 Extended Address Port Pin x Input This bit contains the current state of EPORT x Figure 5 4 Extended Port Input EP_PIN Register EP_REG Address 1FE5H Reset State 00H Each bit of the extended port data output EP_REG register contains data to be driven out by the corresponding pin When a pin is configured as standard l O EP_MODE x 0 the result of a CPU write to EP_REG is immediately visible on the pin During nonextended data accesses EP_REG contains the value of the memory page that is to be accessed For compatibility with software tools clear the EP_REG bit for any EPORT pin that
28. address from the address data bus A decoder can also use this signal to generate chip selects for external memory ADV is multiplexed with P5 0 SLPALE and ALE AINC Auto Increment During slave programming this active low input enables the auto increment feature Auto increment allows reading or writing of sequential OTPROM locations without requiring address transactions across the PBUS for each read or write AINC is sampled after each location is programmed or dumped If AINC is asserted the address is incremented and the next data word is programmed or dumped AINC is multiplexed with P2 4 and INTOUT ALE O Address Latch Enable This active high output signal is asserted only during external memory cycles ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address data bus ALE differs from ADV in that it does not remain active during the entire bus cycle An external latch can use this signal to demultiplex address from the address data bus ALE is multiplexed with P5 0 SLPALE and ADV ANGND GND Analog Ground ANGND must be connected for A D converter and port 0 operation ANGND and Vss should be nominally at the same potential BHE O Byte High Enable During 16 bit bus cycles this active low output signal is asserted for word reads and writes and high byte reads and writes to external memory BHE indicates that valid data is being transferred
29. converter and the logic used to read port 0 Digital Circuit Ground Core Ground Port Ground Connect each Vss and Vas pin to ground through the lowest possible impedance path Vas pins are connected to the core ground region of the micro controller while Vas pins are connected to the port ground region ANGND is connected to the analog ground region Separating the ground regions provides noise isolation Write This active low output indicates that an external write is occurring This signal is asserted only during external memory writes WR is multiplexed with P5 2 SLPWR and WRL The chip configuration register 0 CCRO determines whether this pin functions as WR or WRL CCRO 2 1 selects WR CCRO 2 0 selects WRL WRH Write High During 16 bit bus cycles this active low output signal is asserted for high byte writes and word writes to external memory During 8 bit bus cycles WRH is asserted for all write operations WRH is multiplexed with P5 5 and BHE t The chip configuration register 0 CCRO determines whether this pin functions as BHE WRH CCRO 2 1 selects BHE CCRO 2 0 selects WRH 87C196CB Supplement intel Table A 3 Signal Descriptions Continued Name Type Description WRL Write Lowt During 16 bit bus cycles this active low output signal is asserted for low byte writes and word writes During 8 bit bus cycles WRL is asserted for a
30. future devices write zeros to these bits EIE Error Interrupt Enable This bit enables and disables the bus off and warn interrupts 0 disable bus off and warn interrupts 1 enable bus off and warn interrupts 2 SIE Status change Interrupt Enable This bit enables and disables the successful reception RXOK successful transmission TXOK and error code change LEC2 0 interrupts 0 disable status change interrupt 1 enable status change interrupt When the SIE bit is set the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message even if no message object accepts it Figure 7 6 CAN Control CAN_CON Register 87C196CB SUPPLEMENT intel CAN CON Continued Address 1E00H 87C196CB Reset State 01H Program the CAN control CAN_CON register to control write access to the bit timing registers to enable and disable CAN interrupts and to control access to the CAN bus 7 0 87C196CB CCE EIE SIE IE INIT Bit Bit Function Number Mnemonic unctio 1 IE Interrupt Enable This bit globally enables and disables interrupts error status change and message object transmit and receive interrupts 0 disable interrupts 1 enable interrupts When the IE bit is set an interrupt is generated only if the corresponding interrupt source s enable bit EIE or SIE in CAN_CON TXIE or RXIE in CA
31. integrity through error management logic The CAN controller Figure 7 2 has one input pin one output pin control and status registers and error detection and management logic Bit Timing Registers Control Register Status Register Interrupt Register Global Message Mask Objects 1 14 Registers Message Mask 15 Object 15 Register Bus Bus Driver Driver Error Management Logic A2590 02 Figure 7 2 CAN Controller Block Diagram 7 2 intel CAN SERIAL COMMUNICATIONS CONTROLLER 7 2 CAN CONTROLLER SIGNALS AND REGISTERS Table 7 1 describes the CAN controller s pins and Table 7 2 describes the control and status reg isters Table 7 1 CAN Controller Signals Signal Type Description RXCAN Receive This signal carries messages from other nodes on the CAN bus to the CAN controller TXCAN Transmit This signal carries messages from the CAN controller to other nodes on the CAN bus Table 7 2 Control and Status Registers Register Register Mnemonic Address Description CAN_BTIMEO 1E3FH Bit Timing 0 Program this register to define the length of one time quantum and the maximum number of time quanta by which a bit time can be modified for resynchronization CAN_BTIME1 1E4FH Bit Timing 1 Program this register to define the sample time and mode 1E00H Control Program this register
32. is configured as an extended address signal EP_MODE x set 7 0 PIN7 PING PIN5 PIN4 PIN3 PIN2 PIN1 PINO Bit Bit Number Mnemonic Function 7 0 PIN7 0 Extended Address Port Pin x Output If EPORT x is to be used as an output write the data that it is to drive out If EPORT x is to be used as an input set this bit If EPORT x is to be used as an address line write the correct value for the memory page to be accessed by nonextended instructions Figure 5 5 Extended Port Data Output EP REG Register intel Analog to digital A D Converter intel CHAPTER 6 ANALOG TO DIGITAL A D CONVERTER 6 1 ADDITIONAL A D INPUT CHANNELS The 87C196CB s A D converter is functionally identical to that of the 8XC196NT but it has eight analog input channels instead of four Table 6 1 lists the A D signals Figure 6 1 describes the command register and Figure 6 2 describes the result register Table 6 1 A D Converter Pins PortPin A D Signal T Description P0 7 0 ACH7 0 Analog inputs See the Voltage on Analog Input Pin specification in the datasheet ANGND GND Reference Ground Must be connected for A D converter and port operation VREF PWR Reference Voltage Must be connected for A D converter and port operation 6 1 87C196CB SUPPLEMENT intel AD COMMAND Address 1FACH i Reset State COH The A D command AD COMMAND reg
33. n is the number of bits to be converted For a 10 bit converter with a reference voltage of 5 12 volts one LSB is equal to 5 0 millivolts 5 12 219 All interrupts except unimplemented opcode software trap and NMI Maskable interrupts can be disabled masked by the individual mask bits in the interrupt mask registers and their servicing can be disabled by the global interrupt enable bit Each maskable interrupt can be assigned to the PTS for processing The property of successive approximation converters which guarantees that increasing input voltages produce adjacent codes of increasing value and that decreasing input voltages produce adjacent codes of decreasing value In other words a converter is monotonic if every code change represents an input voltage change in the same direction Large differ ential nonlinearity errors can cause the converter to exhibit nonmonotonic behavior Most significant bit of a byte or most significant byte of a word A field effect transistor with an n type conducting path channel Semiconductor material with introduced impurities doping causing it to have an excess of negatively charged carriers An A D converter has no missing codes if for every output code there is a unique input voltage range which produces that code only Large differential nonlinearity errors can cause the converter to miss codes Glossary 5 87C196CB SUPPLEMENT nonlinearity nonmaskable interrupts
34. objects set this bit pair to enable the CAN peripheral to initiate a transmit TX interrupt after a successful trans mission You must also set the interrupt enable bit CAN_CON 1 to enable the interrupt bit5 bit 4 0 1 no interrupt 1 0 generate an interrupt 3 2 RXIE Receive Interrupt Enable Transmit message objects do not use this bit pair For receive message objects set this bit pair to enable the CAN peripheral to initiate a receive RX interrupt after a successful reception You must also set the interrupt enable bit CAN_CON 1 to enable the interrupt bit3 bit 2 0 1 no interrupt 1 0 generate an interrupt 1 0 INT_PND Interrupt Pending Figure 7 18 CAN Message Object x Control 0 CAN_MSGxCONO Register When the SIE bit in the CAN control register is set the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message even if no message ob ject accepts it If you set both the SIE bit Figure 7 17 and an individual message object s RXIE bit Figure 7 18 the CAN controller generates two interrupt requests each time a message object receives a message The status change interrupt is useful during development to detect bus errors caused by noise or other hardware problems However you should disable this interrupt during normal operation in most applications If the status change interrupt is enabled each status change generates an interrupt
35. recovery sequence which clears the error counters The CAN peripheral waits for 128 bus idle states 128 packets of 11 consecutive recessive bits then resumes normal operation See Bus off State on page 7 41 Figure 7 6 CAN Control CAN_CON Register Continued intel CAN SERIAL COMMUNICATIONS CONTROLLER 7 4 2 Programming the Bit Timing 0 BTIMEO Register Bit timing register O Figure 7 7 defines the length of one time quantum and the maximum amount by which the sample point can be moved or trspg2 can be shortened and the other lengthened to compensate for resynchronization CAN BTIMEO Address 1E3FH 87C196CB Reset State Unchanged Program the CAN bit timing 0 CAN_BTIMEO register to define the length of one time quantum and the maximum number of time quanta by which a bit time can be modified for resynchronization 7 0 87C196CB SJW1 SJWO BRP5 BRP4 BRP3 BRP2 BRP1 BRPO Bit Bit Number Mnemonic Function 7 6 SJW1 0 Synchronization Jump Width This field defines the maximum number of time quanta by which a resyn chronization can modify trseq1 and trsee2 Valid programmed values are 0 3 The hardware adds 1 to the programmed value so a 1 value causes the CAN peripheral to add or subtract 2 time quanta for example This adjustment has no effect on the total bit time if t4 increased by 2 tq trsee2 is decreased by 2 tq and
36. rising edge of RESET places the device into on circuit emulation ONCE mode This mode puts all pins into a high impedance state thereby isolating the device from other components in the system The value of ONCE is latched when the RESET pin goes inactive While the device is in ONCE mode you can debug the system using a clip on emulator To exit ONCE mode reset the device by pulling the RESET signal low To prevent inadvertent entry into ONCE mode either configure this pin as an output or hold it high during reset and ensure that your system meets the Vj specification see datasheet ONCE is multiplexed with P2 6 SIGNAL DESCRIPTIONS Table A 3 Signal Descriptions Continued Name Type Description P0 7 0 Port 0 This is a high impedance input only port Port 0 pins should not be left floating These pins may individually be used as analog inputs or digital inputs While it is possible for the pins to function simultaneously as analog and digital inputs this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results ANGND and Vaz must be connected for port 0 to function 7 4 are multiplexed with ACH7 4 and PMODE 3 0 P0 3 0 are multiplexed with ACH3 0 P1 7 0 I O Port 1 This is a standard bidirectional port that is multiplexed with individually selectable special function signals Port 1 is multiple
37. that supports CAN specification 2 0 Chip configuration bytes The chip configuration registers CCRs are loaded with the contents of the CCBs after a device reset unless the device is entering programming modes in which case the PCCBs are used Chip configuration registers Registers that specify the environment in which the device will be operating The chip configuration registers are loaded with the contents of the CCBs after a device reset unless the device is entering programming modes in which case the PCCBs are used The difference between corresponding code transitions of actual characteristics taken from different A D converter channels under the same temperature voltage and frequency conditions This error is caused by differences in DC input leakage and on channel resistance from one multiplexer channel to another A graph of output code versus input voltage the transfer function of an A D converter The 0 value of a bit or the act of giving it a 0 value See also set 1 A set of instructions that perform a specific function a program 2 The digital value output by the A D converter The voltage corresponding to the midpoint between two adjacent code transitions on the A D converter The point at which the A D converter s output code changes from Q to Q 1 The input voltage corre sponding to a code transition is defined as the voltage that is equally likely to produce either of t
38. to set or clear any bit with a single write operation without affecting the remaining bits 7 0 87C196CB MSGVAL MSGVAL TXIE TXIE RXIE RXIE INT PND INT PND Bit Bit Number Mnemonic Function 3 2 RXIE Receive Interrupt Enable Transmit message objects do not use this bit pair For a receive message object set this bit pair to enable this message object to initiate a receive RX interrupt after a successful reception You must also set the interrupt enable bit CAN_CON 1 to enable the interrupt bit3 bit 2 0 1 no interrupt 1 0 generate an interrupt 1 0 INT_PND Interrupt Pending This bit pair indicates that this message object has initiated a transmit TX or receive RX interrupt Software must clear this bit when it services the interrupt bit1 bitO 0 1 no interrupt 1 0 an interrupt was generated Figure 7 14 CAN Message Object x Control 0 CAN MSGxCONO Register Continued 7 25 87C196CB SUPPLEMENT intel CAN MSGxCON1 Address 1Ex1H x 1 F x 1 15 87C196CB Reset State Unchanged The CAN message object x control 1 MSGxCON 1 register indicates whether a message object has been updated whether a message has been overwritten whether the CPU is updating the message and whether a transmission or reception is pending This register consists of four bit pairs the most significant bit of each pair is in true form and the least signific
39. use ports 3 and 4 for O Systems with EA tied active cannot use ports 3 and 4 as standard I O when is active these ports will function only as the address data bus EA is sampled and latched only on the rising edge of RESET Changing the level of EA after reset has no effect On devices with no internal nonvolatile memory always connect EA to Vss EPA9 0 VO Event Processor Array EPA Input Output pins These are the high speed input output pins for the EPA capture compare channels For high speed PWM applications the outputs of two EPA channels either EPAO and EPA1 or EPA2 and EPA3 can be remapped to produce a PWM waveform on a shared output pin EPA9 0 are multiplexed as follows EPAO P1 0 T2CLK EPA1 P1 1 EPA2 P1 2 T2DIR EPA3 P 1 3 EPA4 P1 4 EPA5 P1 5 6 1 6 EPA7 P1 7 EPA8 P6 0 COMPO and EPA9 P6 1 COMP1 EPORT 7 0 VO Extended Addressing Port 100 pin CB This is a 4 bit bidirectional memory mapped I O port EPORT 7 0 are multiplexed with A23 16 EPORT 3 0 VO Extended Addressing Port 84 pin CB This is a 4 bit bidirectional memory mapped I O port EPORT 3 0 are multiplexed with A19 16 EXTINT External Interrupt In normal operating mode a rising edge on EXTINT sets the EXTINT interrupt pending bit EXTINT is sampled during phase 2 CLKOUT high The minimum high time is one state time In powerdown mode asserting the EXTINT signal for at least 50 ns causes the device to resume normal operation T
40. valid values are 0 3 tprop The portion of 1 that is equivalent to PROP SEG as defined by the CAN protocol Twice the maximum sum of the physical bus delay input comparator delay and output driver delay rounded up to the nearest multiple of tq intel CAN SERIAL COMMUNICATIONS CONTROLLER 7 4 CONFIGURING THE CAN CONTROLLER This section explains how to configure the CAN controller Several registers combine to control the configuration the CAN control register the two bit timing registers and the three mask reg isters 7 4 1 Programming the CAN Control CAN_CON Register The CAN control register Figure 7 6 controls write access to the bit timing registers enables and disables global interrupt sources error status change and individual message object and controls access to the CAN bus CAN_CON Address 1E00H 87C196CB Reset State 01H Program the CAN control CAN_CON register to control write access to the bit timing registers to enable and disable CAN interrupts and to control access to the CAN bus 7 0 87C196CB CCE EIE SIE IE INIT Bit Bit Function Number Mnemonic ABEND Reserved for compatibility with future devices write zero to this bit CCE Change Configuration Enable This bit controls whether software can write to the bit timing registers 0 prohibit write access 1 allow write access 5 4 Reserved for compatibility with
41. vice versa 5 0 BRP5 0 Baud rate Prescaler This field defines the length of one time quantum tq using the following formula where tyra is the input clock period on XTAL1 Valid programmed values are 0 63 tq 2 X BRP 1 For example at 20 MHz operation the system clock period is 50 ns Writing 3 to BRP achieves a time quanta of 400 ns writing 1 to BRP achieves a time quanta of 200 ns tq 2x50 x 3 1 400 ns tq 2x50 x 1 1 200 ns The CCE bit CAN_CON 6 must be set to enable write access to this register Figure 7 7 CAN Bit Timing 0 CAN_BTIMEO Register 87C196CB SUPPLEMENT intel 7 4 3 Programming the Bit Timing 1 CAN BTIME1 Register Bit timing register 1 Figure 7 8 controls the time at which the bus is sampled and the number of samples taken In single sample mode the bus is sampled once and the value of that sample is considered valid In three sample mode the bus is sampled three times and the value of the ma jority of those samples is considered valid Single sample mode may achieve a faster transmis sion rate but it is more susceptible to errors caused by noise on the CAN bus Three sample mode is less susceptible to noise related errors but it may be slower If you specify three sample mode the hardware adds two time quanta to the TSEG1 value to allow time for two additional samples during CAN BTIME1 Address 1E4FH 87C196CB Reset Stat
42. 0 through DT Event processor array An integrated peripheral that provides high speed input output capability Erasable programmable read only memory Electrostatic discharge The attenuation from an input voltage on the selected channel to the A D output after the sample window closes The ability of the A D converter to reject an input on its selected channel after the sample window closes Glossary 3 87C196CB SUPPLEMENT FET frequency generator full scale error hold latency ideal characteristic input leakage input series resistance integer INTEGER interrupt controller interrupt latency interrupt service routine interrupt vector Glossary 4 intel Field effect transistor The 8XC196MD peripheral that generates outputs with a fixed 50 duty cycle and a programmable frequency The frequency generator can be used for infrared transmission The difference between the ideal and actual input voltage corresponding to the final full scale code transition of an A D converter The time it takes the microcontroller to assert HLDA after an external device asserts HOLD The characteristic of an ideal A D converter An ideal characteristic is unique its first code transition occurs when the input voltage is 0 5 LSB its full scale final code transition occurs when the input voltage is 1 5 LSB less than the full scale reference and its code widths are all exactly 1 0 LSB These properties re
43. 0 1 not ready 1 0 message object is valid For receive message objects the CAN peripheral sets this bit pair when it stores new data into the message object For transmit message objects set this bit pair and clear the CPUUPD bit pair to indicate that the message contents have been updated Clearing CPUUPD prevents a remote frame from triggering a transmission that would contain invalid data During initialization clear this bit for any unused message objects Figure 7 15 CAN Message Object x Control 1 CAN MSGxCON 1 Register Continued 7 27 87C196CB SUPPLEMENT intel CAN MSGxDATAO 7 Address 1ExEH 1ExDH X 1 15 87C196CB 1ExCH 1ExBH 1ExAH 1Ex9H 1Ex8H 1Ex7H x 1 F Reset State Unchanged The CAN message object data CAN MSGxDATAO 7 registers contain data to be transmitted or data received Any unused data bytes have random values that change during operation 87C196CB 7 0 CAN MSGxDATA7 Data 7 7 0 CAN MSGXxDATA6 Data 6 7 0 CAN MSGXxDATAS5 Data 5 7 0 CAN MSGxDATA4 Data 4 7 0 CAN MSGXxDATAS3 Data 3 7 0 CAN MSGXxDATA2 Data 2 7 0 CAN MSGXxDATA1 Data 1 7 0 CAN MSGXxDATAO Data 0 Function 7 0 Data Each message object can use from zero to eight data registers to hold data to be transmitted or data received For receive message objects these registers accept data during a reception For transmit message obje
44. 00 CAN_MSG11DATA5 1EBCH 75H OOFCH 3AH 00FCH 1DH 00BCH CAN_MSG12DATA5 1ECCH 76H 00ECH 3BH 00CCH 1DH 00CCH MSG13DATA5 1EDCH 76H OOFCH 3BH 00DCH 1DH 00DCH CAN MSG14DATA5 1EECH 77H 00 3BH 00 1DH 00 CAN_MSG15DATA5 1EFCH 77H OOFCH 3BH 00FCH 1DH 00FCH CAN_MSG1DATA6 1E1DH 70H 00FDH 38H 00DDH 1CH 009DH CAN_MSG2DATA6 1E2DH 71H 00EDH 38H 00EDH 1CH 00ADH CAN_MSG3DATA6 1E3DH 71H 00FDH 38H 00FDH 1CH 00BDH CAN_MSG4DATA6 1E4DH 72H 00EDH 39H 00CDH 1CH 00CDH CAN_MSGS5DATA6 1E5DH 72H 00FDH 39H 00DDH 1CH 00DDH CAN_MSG6DATA6 1E6DH 73H 00EDH 39H 00EDH 1CH 00EDH CAN_MSG7DATA6 1E7DH 73H 00FDH 39H 00FDH 1CH 00FDH CAN_MSG8DATA6 1E8DH 74H 00EDH 3AH 00CDH 1DH 008DH CAN MSG9DATA6 1E9DH 74H 00FDH 3AH 00DDH 1DH 009DH CAN_MSG10DATA6 1EADH 75H 00EDH 3AH 00EDH 1DH 00ADH CAN_MSG11DATA6 1EBDH 75H 00FDH 3AH 00FDH 1DH 00BDH CAN_MSG12DATA6 1ECDH 76H 00EDH 3BH 00CDH 1DH 00CDH MSG13DATA6 1EDDH 76H 00FDH 3BH 00DDH 1DH 00DDH CAN_MSG14DATA6 1EEDH 77H 00EDH 3BH 00EDH 1DH 00EDH Must be addressed as a word 3 16 intel MEMORY PARTITIONS Table 3 9 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows Memor OOE0 00FFH 00CO O0FFH 0080 00FFH Register Mnemonic Location WSR Direct WSR Direct WSR Direct Address Address Address CAN_MSG15DATA6 1EFDH 77H 0
45. 0FDH 3BH 00FDH 1DH 00FDH CAN_MSG1DATA7 1E1EH 70H 00 38H 00DEH 1CH 009EH CAN_MSG2DATA7 1E2EH 71H 00 38H 00 1CH 00 CAN_MSG3DATA7 1E3EH 71H 00 38H 00 1CH 00 CAN_MSG4DATA7 1E4EH 72H 00 39H 00 1 00 CAN MSG5DATA 7 1E5EH 72H 00 39H 00DEH 1CH 00DEH CAN_MSG6DATA7 1E6EH 73H OOEEH 39H 00 1 00 CAN_MSG7DATA7 1E7EH 73H 00 39H 00 1CH 00 CAN_MSG8DATA7 1E8EH 74H 00 00 1DH 008EH CAN MSG9DATA7 1E9EH 74H 00 00DEH 1DH 009EH CAN_MSG10DATA7 1EAEH 75H 00 00 1DH 00 CAN_MSG11DATA7 1EBEH 75H 00 00 1DH 00BEH CAN_MSG12DATA7 1ECEH 76H 00 3BH 00 1DH 00 CAN_MSG13DATA7 1EDEH 76H 00 3BH 00DEH 1DH 00DEH CAN_MSG14DATA7 1EEEH 77H 00 00 1DH 00 CAN_MSG15DATA7 1EFEH 77H 00 00 1DH OOFEH CAN_MSG1IDO 1E12H 70H 00F2H 38H 00D2H 1CH 0092H CAN MSG2IDO 1E22H 71H 00E2H 38H 00E2H 1CH 00A2H CAN_MSG3IDO 1E32H 71H 00F2H 38H 00F2H 1CH 00B2H CAN_MSG4IDO 1E42H 72H 00E2H 39H 00C2H 1CH 00C2H CAN_MSG5IDO 1E52H 72H 00F2H 39H 00D2H 1CH 00D2H CAN_MSG6IDO 1E62H 73H 00E2H 39H 00E2H 1CH 00E2H CAN_MSG7IDO 1E72H 73H 00F2H 39H 00F2H 1CH 00F2H CAN_MSG8IDO 1E82H 74H 00E2H 3AH 00C2H 1DH 0082H CAN_MSG9IDO 1E92H 74H 00F2H 3AH 00D2H 1DH 0092H CAN_MSG10IDO 1EA2H 75H 00E2H 3AH 00E2H 1DH 00A2H CAN_MSG11IDO 1EB2H 75H 00F2H 3AH 00F2H 1DH 00B2H CAN MSG12IDO 1EC2H 76H 00E2H 3BH 00C2H 1
46. 1H OOFFH 38H OOFFH 1CH 00BFH CAN_BTIME1 1E4FH 72H 00 39H 00 1CH 00CFH CAN_CON 1E00H 70H 00 38H 00COH 1CH 0080H CAN_EGMSK 1E08H 70H 00E8H 38H 00C8H 1CH 0088H CAN_INT 1E5FH 72H OOFFH 39H 00DFH 1CH 00DFH CAN_MSGICFG 1E16H 70H OOF6H 38H 00D6H 1CH 0096H CAN_MSG2CFG 1E26H 71H 00E6H 38H 00E6H 1CH 00A6H MSGS3CFG 1E36H 71H OOF6H 38H OOF6H 1CH 00B6H CAN_MSG4CFG 1E46H 72H 00 6 39H 00C6H 1CH 00C6H CAN_MSG5CFG 1E56H 72H OOF6H 39H 00D6H 1CH 00D6H CAN_MSG6CFG 1E66H 73H 00 6 39H 00E6H 1CH 00E6H CAN_MSG7CFG 1E76H 73H 00F6H 39H 00F6H 1CH 00F6H CAN_MSG8CFG 1E86H 74H 00 6 00C6H 1DH 0086H CAN_MSG9CFG 1E96H 74H OOF6H 3AH 00D6H 1DH 0096H CAN_MSG10CFG 1EA6H 75H 00E6H 3AH 00E6H 1DH 00A6H CAN MSG11CFG 1EB6H 75H 00F6H 3AH 00F6H 1DH 00B6H CAN_MSG12CFG 1EC6H 76H 00E6H 3BH 00C6H 1DH 00C6H CAN_MSG13CFG 1ED6H 76H OOF6H 3BH 00D6H 1DH 00D6H CAN_MSG14CFG 1EE6H 77H 00E6H 3BH 00 6 1DH 00E6H CAN_MSG15CFG 1EF6H 77H 00F6H 3BH 00F6H 1DH 00F6H CAN_MSG1CONO 1E10H 70H 00FOH 38H 00DOH 1CH 0090H CAN_MSG2CONO 1E20H 71H 00 38H 00 1CH 00A0H CAN 1E30H 71H 00FOH 38H 00FOH 1CH 00BOH CAN_MSG4CONO 1E40H 72H 00 39H 00COH 1CH 00COH CAN_MSG5CONO 1E50H 72H 00FOH 39H 00DOH 1CH 00DOH CAN_MSG6CONO 1E60H 73H 00E0H 39H 00 1CH 00 t Must be addressed as a word intel MEMORY PARTITIONS Table 3 9 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows
47. 25 ns 250 ns 12 MHz 0 1 12 MHz 83 5 ns 167 ns 16 MHz 0 1 16 MHz 62 5 ns 125 ns 20 MHz 0 i 20 MHz 50 ns 100 ns 4 MHz 1 4 16 MHz 62 5 ns 125 ns 5 MHz 1 4 20 MHz 50 ns 100 ns intel Memory Partitions intel CHAPTER 3 MEMORY PARTITIONS This chapter describes the differences in the address space of the 87C196CB from that of the 8XC196NT The 87C196CB has 56 Kbytes of one time programmable read only memory OT PROM while the 8XC196NT is available with 32 Kbytes The 87C196CB also has an additional 512 bytes of register RAM The 87C196CB is available in either an 84 pin or a 100 pin package The 84 pin 87C196CB like the 8XC196NT has up to 20 external address lines enabling access to 1 Mbyte of linear address space The 100 pin 87C196CB has four additional pins available for external address lines With all 24 external address lines connected A23 16 and AD15 0 the 100 pin 87C196CB can access 16 Mbytes of linear address space 3 1 MEMORY MAP SPECIAL FUNCTION REGISTERS AND WINDOWING Table 3 1 compares the register file addresses of the 8XC196NT and 87C196CB Table 3 2 is a memory map of the 87C196CB Table 3 3 lists the 87C196CB s peripheral SFRs these are the same as those of the 8XC196NT Table 3 4 lists the CAN peripheral SFRs which are unique to the 87C196CB Tables 3 5 through 3 9 provide the information necessary to window higher memory into the lower register file for direct access Table 3 1 Registe
48. 3DATA5 1E7AH CAN MSG7DATA4 CAN MSG7DATAS3 1E3AH CAN MSG3DATA4 MSG3DATAS3 1E78H CAN MSG7DATA2 MSG7DATA1 1E38H CAN MSG3DATA2 CAN MSGS3DATA1 1E76H CAN MSG7DATAO CAN MSG7CFG 1E36H CAN MSG3DATAO MSG3CFG 1E74H CAN_MSG7ID3 CAN_MSG7ID2 1E34H CAN_MSG3ID3 CAN_MSG3ID2 1E72H CAN_MSG7ID1 CAN_MSG7IDO 1E32H CAN MSGSID1 CAN MSGS3IDO 1E70H MSG7CON1 MSG7CONO 1E30H CAN_MSG3CON1 CAN MSG3CONO Message 6 Message 2 Addr High Odd Byte Low Even Byte Addr High Odd Byte Low Even Byte 1E6EH Reserved CAN_MSG6DATA7 1E2EH Reserved CAN_MSG2DATA7 1E6CH CAN_MSG6DATA6 CAN MSG6DATA5 1E2CH MSG2DATA6 CAN MSG2DATA5 1E6AH CAN MSG6DATA4 CAN MSG6DATAS3 1E2AH MSG2DATA4 MSG2DATAS3 1E68H CAN MSG6DATA2 CAN MSG6DATA1 1E28H CAN MSG2DATA2 CAN MSG2DATA1 1E66H CAN MSG6DATAO CAN MSG6CFG 1E26H CAN MSG2DATAO CAN MSG2CFG 1E64H CAN MSG6IDS3 CAN MSG6ID2 1E24H CAN MSG2ID3 MSG2ID2 1E62H CAN MSG6ID1 CAN MSG6IDO 1E22H CAN_MSG2ID1 CAN MSG2IDO 1E60H CAN MSG6CON 1 CAN MSG6CONO 1E20H CAN MSG2CON 1 CAN MSG2CONO Message 5 and Interrupts Message 1 Addr High Odd Byte Low Even Byte Addr High Odd Byte Low Even Byte 1EBEH INT CAN MSGB5DATA7 1E1EH Reserved CAN MSG1DATA 7 1E5CH CAN_MSG5DATA6 CAN_MSG5DATA5 1E1CH CAN_MSG1DATA6 CAN MSG1DATA5 1E5AH MSG5DATA4 CAN MSGB5DATAS3 1E1AH CAN MSG1DATA4 CAN MSG1DATAS3 1E58H CAN MSG5DATA2 MSG5DATA1 1E18H CAN MSG1DATA2 CAN M
49. 5 BHE WRH NMI P5 3 RD SLPRD EA A20 EPORT 4 Vest A21 EPORT 5 NC A22 EPORT 6 Voc Vpp NC A23 EPORT 7 Vss P5 0 ADV ALE SLPALE NC P5 1 INST SLPCS NC xx87C196CB P5 6 READY P5 4 SLPINT A19 EPORT 3 NC NC NC P2 0 TXD PVER P2 1 RXD PALE Voc P2 2 EXTINT PROG NC 2 3 Er View of component as Vest 55 P2 4 INTOUT AINC mounted on PC board NC P2 5 HOLD E 21 RXCAN P2 6 HLDA CPVER ONCE E 22 TXCAN P2 7 CLKOUT PACT E 23 XTAL1 Q 24 XTAL2 Vss1 E125 NC P0 0 ACHO E 26 P0 1 ACH1 CJ 27 P0 2 ACH2 28 P0 3 ACH3 29 P0 4 PMODE 0 30 P6 7 SD1 P6 6 SC1 P6 5 SDO P6 4 SCO Vec ANGND K 34 P1 1 EPA1 E 44 P6 3 T1DIR E 49 PLLEN 50 P1 3 EPA3 42 P1 0 EPAO T2CLK r3 45 P0 5 ACH5 PMODE 1 31 P0 6 ACH6 PMODE 2 EJ 32 P0 7 ACH7 PMODE 3 33 P1 7 EPA7 E 38 P1 6 6 39 P1 5 EPA5 40 P1 4 EPA4 41 P1 2 EPA2 T2DIR E 43 P6 0 EPA8 COMPO 46 P6 1 EPA9 COMP1 47 P6 2 T1CLK 48 A3171 02 Figure A 2 87C196CB 100 pin QFP Package A 2 SIGNAL DESCRIPTIONS Table A 2 defines the columns used in Table A 3 which describes the signals A 3 87C196CB Supplement intel Table A 2 Description of Columns of Table A 3 Column Heading Description Name Lists the signals arranged alphabetically Many pins have two functions so the
50. 7 18 CAN STAT 7 4 7 33 CCRI 9 3 DIR 5 2 EP MODE 5 2 EP PIN 5 3 EP REG 5 3 INT MASKI 4 2 INT PENDI 4 2 PO PIN 5 1 Reset status I O and control pins A 14 S Serial port programming mode 10 4 SFRs windowed direct addresses 3 11 Signal descriptions A 4 A 14 State time defined 2 4 T Timing internal 2 2 2 4 Index 2 intel selectable bus timing 8 1 W Windows and memory mapped SFRs 3 9 locations that cannot be windowed 3 9 table of 3 11 WSR values and direct addresses 3 9
51. 7CH Reserved EPA7_CON 1FBAH SP_CON SBUF_TX 1F7AH EPA6_TIME EPA6_TIME L 1FB8H SP_STATUS SBUF_RX 1F78H Reserved EPA6_CON 1FB6H Reserved Reserved 1F76H 5 TIME H EPAS5 TIME L 1FB4H Reserved SSIO_BAUD 1F74H Reserved EPA5 CON 1FB2H SSIO1 SSIO1 BUF 1F72H 4 TIME H EPA4 TIME L 1FBOH 55100 CON 55100 BUF 1F70H Reserved 4 CON A D SFRs 1F6EH TIME H TIME L Address High Odd Byte Low Even Byte 1F6CH EPA3_CON H EPAS3 CON L 1FAEH AD TIME AD TEST F6AH EPA2 TIME EPA2 TIME L 1FACH Reserved AD COMMAND 1F68H Reserved EPA2 CON 1FAAH AD RESULT H AD RESULT L 1F66H 1 TIME H EPA1 TIME L EPA Interrupt SFRs 1F64H EPA1 CON H EPA1 CON L Address High Odd Byte Low Even Byte 1F62H TIME H EPAO TIME L 1FA8H Reserved EPAIPV 1F60H Reserved CON 1FA6H Reserved EPA PEND1 1FA4H Reserved EPA MASK1 HFA2H EPA PEND H EPA PEND L HFAOH EPA H EPA MASK L 87C196CB SUPPLEMENT Table 3 4 CAN Peripheral SFRs intel Message 15 Message 11 Addr High Odd Byte Low Even Byte Addr High Odd Byte Low Even Byte 1EFEH Reserved CAN_MSG15DATA7 1EBEH Reserved CAN_MSG11DATA7 1EFCH CAN MSG15DATA6 CAN_MSG15DATA5 1EBCH CAN_MSG11DATA6 MSG11DATA5 1EFAH CA
52. 87C196CB Supplement to 8XC196NT User s Manual 87C196CB Supplement to 8XC196NT User s Manual August 2004 Order Number 272787 003 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The 87C196CB and 8XC196NT microprocessors may contain design defects or errors known as errata which may cause the products to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or you
53. ADV EPORT 3 0 84 pin CB EXTINT BHE WRH P0 7 0 ACH7 0 NMI BREQ P1 0 EPA0 T2CLK ONCE BUSWIDTH P1 1 EPA1 RESET CLKOUT P1 2 EPA2 T2DIR SLPINT HOLD P1 7 3 EPA7 3 XTAL1 HLDA P2 0 TXD XTAL2 INST P2 1 RXD PLLEN INTOUT P2 7 2 Address amp Data READY P3 7 0 A23 16 100 pin CB RD P4 7 0 A19 16 84 pin CB SLPALE P5 7 0 AD15 0 SLPCS P6 0 EPA8 COMPO SLP7 0 SLPWR P6 1 EPA9 COMP1 Programming Control SLPRD P6 2 T1CLK AINC Power amp Ground P6 3 T1DIR CPVER ANGND P6 4 SCO PACT Voc P6 5 SDO PALE Vop P6 6 SC1 PBUS15 0 VREE P6 7 SD1 PMODE 3 0 Vas Vas RXCAN PROG TXCAN PVER Slave port signal 87C196CB Supplement amp gt n lt 2 ud Eo 90 Jee wa rz ad 5 lg 037 55255 fro 9 lt 2r0 fj zz 99000 NOE pe ESPEP EEES EE DIDA AG O 0 0 0 Oo 014920 aaa gt anan lt gt gt gt gt nnunnnnnnnnnunmnnnnmnunnrmr P5 7 BUSWIDTH PLLEN A17 EPORT 1 P6 3 T1DIR A16 EPORT O P6 2 TICLK AD15 P4 7 PBUS15 AD14 P4 6 PBUS14 AD13 P4 5 PBUS13 AD12 P4 4 PBUS12 AD11 P4 3 PBUS11 AD10 P4 2 PBUS10 xx87C196CB View of component as AD7 P3 7 SLP7 PBUS7 25 mounted on PC board AD6 P3 6 SLP6 PBUS6 26 AD5 P3 5 SLP5 PBUS5 r 27 ADA P3 4 SLP4 PBUS4 EJ 28 AD3 P3 3 SLP3 PBUS3 EF 29 AD2 P3 2 SLP2 PBUS2
54. B4H 7DH 00F4H 3EH 00F4H 1FH 00B4H SSIOO_BUF 1FBOH 7DH 00FOH 3EH 00FOH 1FH 00BOH SSIO1_BUF 1FB2H 7DH 00F2H 3EH 00F2H 1FH 00B2H 55100 CON 1FB1H 7DH 00F1H 3EH 00F1H 1FH 00B1H SSIO1_CON 1FB3H 7DH 00F3H 3EH 00F3H 1FH 00B3H TICONTROL 1F98H 7CH 00F8H 3EH 00D8H 1FH 0098H T2CONTROL 1F9CH 7CH OOFCH 3EH 00DCH 1FH 009CH TIMER17 1F9AH 7CH OOFAH 3EH 00DAH 1FH 009AH 2 1F9EH 7CH 00 00DEH 1FH 009 Must be addressed as a word intel Standard and PTS Interrupts intel 4 1 INTERRUPT SOURCES VECTORS AND PRIORITIES CHAPTER 4 STANDARD AND PTS INTERRUPTS The interrupt structure of the 87C196CB is the same as that of the 8XC196NT The only differ ence is that INT13 which was reserved on the 8XC196NT supports the CAN peripheral Table 4 1 lists the 87C196CB s interrupts sources default priorities 30 is highest and 0 is low est and vector addresses Figures 4 1 and 4 2 illustrate the interrupt mask and pending registers Table 4 1 Interrupt Sources Vectors and Priorities ee PTS Service Interrupt Source Mnemonic o 5 E o 5 E 5 8 5 8 5 2 gt 2 gt Es Nonmaskable Interrupt NMI INT15 FF203EH 30 EXTINT Pin EXTINT INT14 FF203CH 14 PTS14 FF205CH 29 CAN CAN INT13 FF203AH 13 PTS13 7 FF205AH 28 SIO Receive RI INT12 FF2038H 12 PTS12 FF2058H 27 SIO Transmit Tl INT11 FF2036H 11 P
55. CAN MSG13DATA2 MSG13DATA1 1E98H CAN MSG9DATA2 CAN MSG9DATA1 1ED6H CAN MSG13DATAO CAN MSG13CFG 1E96H CAN MSG9DATAO CAN MSG9CFG 1ED4H CAN_MSG13ID3 CAN_MSG13ID2 1E94H CAN_MSG9ID3 CAN MSGS9ID2 1ED2H CAN_MSG13ID1 CAN MSG13IDO 1E92H CAN MSGSID1 CAN MSGS9IDO 1EDOH CAN _MSG13CON1 CAN MSG13CONO 1E90H CAN MSG9CON1 CAN MSG9CONO Message 12 Message 8 Addr High Odd Byte Low Even Byte Addr High Odd Byte Low Even Byte 1ECEH Reserved CAN MSG12DATA7 1E8EH Reserved CAN MSG8DATA 7 1ECCH MSG12DATA6 CAN MSG12DATA5 1E8CH CAN MSG8DATA6 CAN MSG8DATA5 1ECAH MSG12DATA4 CAN MSG12DATAS3 1E8AH CAN MSG8DATA4 CAN MSG8DATA3 1EC8H CAN MSG12DATA2 CAN MSG12DATA1 1E88H CAN MSG8DATA2 CAN MSG8DATA1 1EC6H CAN MSG12DATAO CAN MSG12CFG 1E86H CAN MSG8DATAO CAN MSG8CFG 1EC4H MSG12ID3 CAN MSG12ID2 1E84H CAN MSGS8ID3 CAN MSGS8ID2 1EC2H MSG12ID1 CAN MSG12IDO 1E82H CAN MSG8ID1 CAN MSGS8IDO 1ECOH MSG12CON1 CAN MSG12CONO 1E80H MSG8CON1 CAN MSG8CONO 3 4 intel MEMORY PARTITIONS Table 3 4 CAN Peripheral SFRs Continued Message 7 Message 3 and Bit Timing 0 Addr High Odd Byte Low Even Byte Addr High Odd Byte Low Even Byte 1E7EH Reserved CAN_MSG7DATA7 1E3EH CAN_BTIMEO CAN_MSG3DATA7 1E7CH CAN_MSG7DATA6 MSG7DATA5 1E3CH CAN MSG3DATA6 CAN MSGS
56. CON1 1EF1H 77H 00 00 1DH 00 CAN_MSG1DATAO 1E17H 70H 00F7H 38H 00D7H 1CH 0097H CAN_MSG2DATAO 1E27H 71H 00E7H 38H 00E7H 1CH 00A7H CAN_MSG3DATAO 1E37H 71H 00F7H 38H 00F7H 1CH 00B7H CAN MSGA4DATAO 1E47H 72H 00E7H 39H 00C7H 1CH 00C7H CAN_MSG5DATAO 1E57H 72H 00F7H 39H 00D7H 1CH 00D7H CAN_MSG6DATAO 1E67H 73H 00 7 39H 00E7H 1CH 00E7H CAN_MSG7DATAO 1E77H 73H 00F7H 39H 00F7H 1CH 00F7H CAN_MSG8DATAO 1E87H 74H 00E7H 3AH 00C7H 1DH 0087H Must be addressed as a word 87C196CB SUPPLEMENT intel Table 3 9 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows M OOE0 00FFH 00CO O0FFH 0080 00FFH Register Mnemonic poda WSR Direct WSR Direct WSR Direct Address Address Address CAN MSG9DATAO 1E97H 74H 00F7H 3AH 00D7H 1DH 0097H CAN MSG10DATAO 1EA7H 75H 00E7H 3AH 00E7H 1DH 00A7H CAN_MSG11DATAO 1EB7H 75H 00F7H 3AH 00F7H 1DH 00B7H CAN_MSG12DATAO 1EC7H 76H 00E7H 3BH 00C7H 1DH 00C7H CAN_MSG13DATAO 1ED7H 76H 00F7H 3BH 00D7H 1DH 00D7H CAN MSG14DATAO 1EE7H 77H 00E7H 3BH 00E7H 1DH 00E7H CAN_MSG15DATAO 1EF7H 77H 00F7H 3BH 00F7H 1DH 00F7H CAN MSG1DATA1 1E18H 70H 00F8H 38H 00D8H 1CH 0098H CAN_MSG2DATA1 1E28H 71H 00E8H 38H 00E8H 1CH 00A8H CAN MSG3DATA1 1E38H 71H 00F8H 38H 00F8H 1CH 00B8H CAN MSGA4DATA1 1E48H 72H 00E8H 39H 00C8H 1CH
57. DH 00C2H CAN_MSG13IDO 1ED2H 76H 00F2H 3BH 00D2H 1DH 00D2H CAN_MSG14IDO 1EE2H 77H 00E2H 3BH 00E2H 1DH 00E2H CAN_MSG15IDO 1EF2H 77H 00F2H 3BH 00F2H 1DH 00F2H CAN_MSG1ID1 1E13H 70H 00F3H 38H 00D3H 1CH 0093H Must be addressed as a word 87C196CB SUPPLEMENT intel Table 3 9 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows Memory OOE0 00FFH 00CO O0FFH 0080 00FFH Register Mnemonic Location WSR Direct WSR Direct WSR Direct Address Address Address CAN MSG2ID1 1E23H 71H 00E3H 38H 00 1CH 00 CAN_MSG3ID1 1E33H 71H 00F3H 38H 00F3H 1CH 00B3H CAN_MSG4ID1 1E43H 72H 00 39H 00C3H 1CH 00C3H CAN_MSGSID1 1E53H 72H 00F3H 39H 00D3H 1CH 00D3H CAN_MSG6ID1 1E63H 73H 00E3H 39H 00 1CH 00E3H CAN_MSG7ID1 1E73H 73H 00F3H 39H 00F3H 1CH 00F3H CAN_MSG8ID1 1E83H 74H 00 00C3H 1DH 0083H CAN_MSG9ID1 1E93H 74H 00F3H 3AH 00D3H 1DH 0093H CAN_MSG10ID1 1EA3H 75H 00 00 1DH 00 CAN_MSG11ID1 1EB3H 75H 00F3H 3AH 00F3H 1DH 00B3H CAN_MSG12ID1 1EC3H 76H 00 3BH 00C3H 1DH 00C3H MSG 13ID1 1ED3H 76H 00F3H 3BH 00D3H 1DH 00D3H CAN_MSG14ID1 1EE3H 77H 00 3BH 00 1DH 00 CAN_MSG15ID1 1EF3H 77H 00F3H 3BH 00F3H 1DH 00F3H CAN_MSG1ID2 1E14H 70H 00F4H 38H 00D4H 1CH 0094H CAN_MSG2ID2 1E24H 71H 00E4H
58. FBH 1CH 00FBH CAN_MSG8DATA4 1E8BH 74H 00 00CBH 1DH 008BH CAN_MSG9DATA4 1E9BH 74H 00FBH 3AH 00DBH 1DH 009BH CAN_MSG10DATA4 1EABH 75H 00 00 1DH 00ABH CAN MSG11DATA4 1EBBH 75H 00FBH 3AH 00FBH 1DH 00BBH CAN_MSG12DATA4 1ECBH 76H 00 3BH 00CBH 1DH 00CBH Must be addressed as a word 87C196CB SUPPLEMENT intel Table 3 9 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows M OOE0 00FFH 00CO O0FFH 0080 00FFH Register Mnemonic poda WSR Direct WSR Direct WSR Direct Address Address Address CAN MSG13DATA4 1EDBH 76H 00FBH 3BH 00DBH 1DH 00DBH CAN_MSG14DATA4 1EEBH 77H 00 00 1DH 00 CAN_MSG15DATA4 1EFBH 77H 00FBH 3BH 00FBH 1DH 00FBH CAN_MSG1DATAS5 1E1CH 70H OOFCH 38H 00DCH 1CH 009CH CAN MSG2DATAS5 1E2CH 71H 00 38H 00 1 00 CAN_MSG3DATA5 1E3CH 71H 00FCH 38H 00FCH 1CH 00BCH CAN_MSG4DATA5 1E4CH 72H 00 39H 00CCH 1CH 00CCH CAN MSGS5DATAS5 1E5CH 72H OOFCH 39H 00DCH 1CH 00DCH CAN MSG6DATAS5 1E6CH 73H 00 39H 00 1 00 CAN_MSG7DATA5 1E7CH 73H 00FCH 39H 00FCH 1CH OOFCH CAN_MSG8DATA5 1E8CH 74H 00ECH 3AH 00CCH 1DH 008CH CAN MSG9DATAS5 1E9CH 74H OOFCH 3AH 00DCH 1DH 009CH CAN MSG10DATAS5 1EACH 75H 00 00 1DH
59. L COMMUNICATIONS CONTROLLER 7 3 4 Error Detection and Management Logic The CAN controller has several error detection mechanisms including cyclical redundancy checking CRC and bit coding rules stuffing and destuffing The CAN controller generates a CRC code for transmitted messages and checks the CRC code of incoming messages The CRC polynomial has been optimized for control applications with short messages After five consecutive bits of equal value are transmitted a bit with the opposite polarity is added to the bit stream This bit is called a stuff bit by adding a transition a stuff bit aids in synchroni zation All message fields are stuffed except the CRC delimiter the acknowledgment field and the end of frame field Receiving nodes reject data from any message that is corrupted during transmission and send an error message via the CAN bus Transmitting nodes monitor the CAN bus for error messages and automatically repeat a transmission if an error occurs The following error types are detected stuff error more than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed form error the fixed format part of a received frame has the wrong format for example a reserved bit has the wrong value acknowledgment error this device transmitted a message but it was not acknowledged by another node on the CAN bus The transmit error counter stops incrementing after 128 ac
60. L OVERVIEW Disable PLL Powerdown Phase XTAL1 Q Comparator Phase locked XTAL2 7 Oscillator Disable Oscillator Powerdown Disable Clock Input Powerdown Phase locked Loop Clock Multiplier Divide by two Circuit Disable Clocks PLLEN Q Powerdown Peripheral Clocks PH1 PH2 Clock CLKOUT Generators CPU Clocks PH1 PH2 Disable Clocks Idle Powerdown A3168 01 Figure 2 2 Clock Circuitry The rising edges of PH1 and PH2 generate the internal CLKOUT signal Figure 2 3 The clock circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibil ity in power management It also outputs the CLKOUT signal on the CLKOUT pin Because of the complex logic in the clock circuitry the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal This delay varies with temperature and voltage 2 3 87C196CB SUPPLEMENT intel lt _ lt LE 1 State Time gt 1 State Time gt PH1 PH2 j A E CLKOUT A e e d Ph Phase 1 Phase 2 Phase 1 Phase 2 1 A0805 01 Figure 2 3 Internal Clock Phases The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state Table 2 2 lists state time durations at various frequencies Table 2 2 State Times at Various Frequencies f Frequency I
61. LT CONDITIONS eee nn nnne nnne nennt rennen neret A 14 GLOSSARY INDEX intel FIGURES Figure 2 1 87C196CB Block Diagram sse 2 2 eere Ser ePi EE 2 3 Internal Clock Phases 2 4 Effect of Clock Mode on CLKOUT 4 1 Interrupt Mask 1 INT MASK1 4 2 interrupt Pending 1 INT PEND1 5 1 Port x Pin Input PIN 1 5 2 Extended Port I O Direction DIR 5 8 Extended Port Mode EP MODE 5 4 Extended Port Input EP PIN 5 5 Extended Port Data Output REG 6 1 A D Command AD COMMAND 6 2 A D Result AD RESULT Register Read Format 7 1 A System Using CAN Controllers eene 7 2 CAN Controller Block 7 8 ANTES nee 7 4 A Bit Time as Specified by the CAN 7 5 A Bit Time as Implemented in the CAN Controller
62. N_MSG15DATA4 CAN_MSG15DATA3 1EBAH CAN MSG11DATA4 CAN_MSG11DATA3 1EF8H CAN MSG15DATA2 CAN MSG15DATA1 1EB8H CAN MSG11DATA2 MSG11DATA1 1EF6H CAN MSG15DATAO CAN MSG15CFG 1EB6H CAN MSG11DATAO MSG11CFG 1EF4H CAN MSG15ID3 CAN MSG15ID2 1EB4H MSG111ID3 CAN MSG11ID2 1EF2H CAN_MSG15ID1 CAN MSG15IDO 1EB2H CAN_MSG11ID1 MSG111DO 1EFOH CAN MSG15CON1 CAN MSG15CONO 1EBOH CAN MSG11CON1 CAN MSG11CONO Message 14 Message 10 Addr High Odd Byte Low Even Byte Addr High Odd Byte Low Even Byte 1EEEH Reserved MSG14DATA7 1EAEH Reserved CAN MSG10DATA7 1EECH CAN MSG14DATA6 CAN MSG14DATA5 1EACH MSG10DATA6 CAN MSG10DATA5 1EEAH CAN MSG14DATA4 CAN MSG14DATA3 1EAAH CAN MSG10DATA4 CAN MSG10DATA3 1EE8H CAN MSG14DATA2 _MSG14DATA1 1EA8H CAN MSG10DATA2 MSG10DATA1 1EE6H MSG14DATAO MSG14CFG 1EA6H CAN_MSG10DATAO MSG10CFG 1EE4H CAN_MSG14ID3 CAN_MSG14ID2 1EA4H CAN_MSG10ID3 CAN_MSG10ID2 1EE2H CAN_MSG14ID1 CAN_MSG14IDO 1EA2H CAN_MSG10ID1 CAN_MSG10IDO 1EEOH CAN_MSG14CON1 CAN_MSG14CONO 1EAOH CAN_MSG10CON1 CAN_MSG10CONO Message 13 Message 9 Addr High Odd Byte Low Even Byte Addr High Odd Byte Low Even Byte 1EDEH Reserved CAN_MSG13DATA7 1E9EH Reserved CAN_MSG9DATA7 1EDCH CAN_MSG13DATA6 CAN_MSG13DATA5 1E9CH CAN MSG9DATA6 CAN MSG9DATA5 1EDAH CAN MSG13DATA4 MSG13DATAS3 1E9AH MSG9DATA4 CAN MSG9DATAS3 1ED8H
63. N_MSGx_COND is also set If the IE bit is clear an interrupt request updates the CAN interrupt pending register but does not generate an interrupt 0 INIT Software Initialization Enable Setting this bit isolates the CAN bus from the system If a transfer is in progress it completes but no additional transfers are allowed 0 software initialization disabled 1 software initialization enabled A hardware reset sets this bit enabling you to configure the RAM without allowing any CAN bus activity After a hardware reset or software initial ization clearing this bit completes the initialization The CAN peripheral waits for a bus idle state 11 consecutive recessive bits before partici pating in bus activities Software can set this bit to stop all receptions and transmissions on the CAN bus To prevent transmission of a specific message object while its contents are being updated set the CPUUPD bit in the individual message object s control register 1 See Configuring Message Objects on page 7 20 Entering powerdown mode stops an in progress CAN transmission immediately To avoid stopping a CAN transmission while it is sending a dominant bit on the CAN bus set the INIT bit before executing the IDLPD instruction The CAN peripheral also sets this bit to isolate the CAN bus when an error counter reaches 256 This isolation is called a bus off condition After a bus off condition clearing this bit initiates a bus off
64. OG is active During a word dump a falling edge causes the contents of an OTPROM location to be output on the PBUS while a rising edge ends the data transfer PROG is multiplexed with P2 2 and EXTINT PVER Program Verification During slave or auto programming PVER is updated after each programming pulse A high output signal indicates successful programming of a location while a low signal indicates a detected error PVER is multiplexed with P2 0 and TXD RD O Read Read signal output to external memory RD is asserted only during external memory reads RD is multiplexed with P5 3 and SLPRD READY Ready Input This active high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally When READY is high CPU operation continues in a normal manner with wait states inserted as programmed in the chip configuration registers READY is ignored for all internal memory accesses READY is multiplexed with P5 6 RESET 1 0 Reset A level sensitive reset input to and open drain system reset output from the microcontroller Either a falling edge on RESET or an internal reset turns on a pull down transistor connected to the RESET pin for 16 state times In the powerdown and idle modes asserting RESET causes the chip to reset and return to normal operating mode After a device reset the first instruction fetch is from FF2080H RXCAN Receive
65. P6 7 SD1 WK1 Note 3 Note 3 EA HiZ HiZ HiZ NMI HiZ HiZ HiZ RXCAN WK1 WK1 WK1 TXCAN LoZ1 LoZ1 LoZ1 Vop HiZ LoZ1 LoZ1 XTAL1 Osc input HiZ Osc input HiZ Osc input HiZ XTAL2 Osc output LoZO 1 Osc output LoZO 1 Note 5 NOTES 1 If PS5_MODE y 0 port is as programmed If PS_MODE y 1 and HLDA 1 P5 0 and P5 1 1070 P5 5 is LoZ1 If P5 MODE y 1 and HLDA 0 port is on NO gut If P5 MODE y 0 port is as programmed If P5 MODE y 1 port is If Px MODE y 0 port is as programmed If Px MODE y 1 pin is as specified by DIR and the associated peripheral If P2 MODE 7 0 pin is as programmed If P2_MODE 7 1 pin is 040 If XTAL1 0 pin is LoZ1 If XTAL1 1 pin is LoZO If EA 0 port is If EA 1 port is open drain I O ODIO Pins configured as address are high impedance pins configured as I O remain unchanged intel Glossary intel GLOSSARY This glossary defines acronyms abbreviations and terms that have special meaning in this man ual Chapter discusses notational conventions and general terminology absolute error accumulator actual characteristic A D converter ALU assert attenuation bit BIT break before make byte BYTE The maximum difference between corresponding actual and ideal code transitions Absolute error accounts for all deviations of an actual A D converter from an ideal conver
66. SG1DATA1 1E56H CAN MSG5DATAO CAN MSGS5CFG 1E16H MSG1DATAO CAN MSG1CFG 1E54H CAN_MSG5ID3 CAN MSGBSID2 1E14H CAN_MSG1ID3 CAN MSG1ID2 1E52H CAN_MSG5ID1 CAN MSGBSIDO 1E12H CAN_MSG1ID1 CAN MSG1IDO 1E50H CAN_MSG5CON1 CAN MSG5CONO 1E10H CAN MSG1CON 1 CAN MSG1CONO Message 4 and Bit Timing 1 Mask Control and Status Addr High Odd Byte Low Even Byte Addr High Odd Byte Low Even Byte 1E4EH 1 MSGA4DATA7 1E0EH CAN MSK15 CAN MSK15 1E4CH CAN_MSG4DATA6 CAN_MSG4DATA5 1E0CH CAN_MSK15 CAN_MSK15 1E4AH CAN_MSG4DATA4 CAN_MSG4DATA3 1 EGMSK CAN_EGMSK 1E48H CAN MSG4DATA2 CAN MSG4DATA1 1E08H CAN EGMSK CAN EGMSK 1E46H CAN MSG4DATAO CAN MSG4CFG 1E06H CAN SGMSK CAN SGMSK 1E44H CAN MSGAID3 MSGAID2 1E04H Reserved Reserved 1E42H CAN MSGAID1 MSGAIDO 1E02H Reserved Reserved 1E40H MSG4CON1 MSG4CONO 1E00H CAN STAT CAN The CCE bit in the control register CAN CON must be set to enable write access to the bit timing registers BTIMEO and CAN BTIME1 3 5 87C196CB SUPPLEMENT Table 3 5 Selecting a Window of Peripheral SFRs intel Peripheral WSR Value for 32 byte Window WSR Value for 64 byte Window WSR Value for 128 byte Window 00 0 00 0 0 0080 00FFH Ports 0 1 2 6 7EH 3FH A D converter EPA interrupts 7DH 3EH 1FH EPA com
67. TS11 FF2056H 26 SSIO Channel 1 Transfer SSIO1 INT10 FF2034H 10 PTS10 FF2054H 25 SSIO Channel 0 Transfer SSIOO INTO9 FF2032H 09 509 FF2052H 24 Slave Port Command Buff Full CBF INTO8 FF2030H 08 508 FF2050H 23 Unimplemented Opcode FF2012H Software TRAP Instruction FF2010H Slave Port Input Buff Full IBF INTO7 FF200EH 07 PTSO7 FF204EH 22 Slave Port Output Buff Empty OBE INTO6 FF200CH 06 506 FF204CH 21 A D Conversion Complete AD DONE INTO5 FF200AH 05 505 204 20 0 INTO4 FF2008H 04 PTS04 FF2048H 19 EPA Capture Compare 1 EPA1 INTOS FF2006H 03 PTS03 FF2046H 18 EPA Capture Compare 2 EPA2 INTO2 FF2004H 02 502 FF2044H 17 EPA Capture Compare 3 EPA3 INTO1 FF2002H 01 501 2042 16 EPA Capture Compare 4 9 EPAx INTOO FF2000H 00 5001 FF2040H 15 EPA 0 9 Overrun EPA Compare 0 1 Timer 1 Overflow Timer 2 Overflow PTS service is not recommended because the PTS cannot determine the source of shared interrupts 87C196CB SUPPLEMENT intel INT MASK1 Address 0013H i Reset State 00H The interrupt mask 1 INT MASK1 register enables or disables masks individual interrupt requests The El and DI instructions enable and disable servicing of all maskable interrupts INT MASK1 can be read from or written to as a byte register PUSHA saves this register on the stack and POPA rest
68. Transmit FF2036H SSIO1 SSIO 1 Transfer FF2034H SSIOO SSIO 0 Transfer FF2032H CBF Slave Port Command Buffer Full FF2030H Figure 4 2 interrupt Pending 1 INT_PEND1 Register intel I O Ports intel 5 1 PORT 0 AND EPORT CHAPTER 5 I O PORTS The I O ports of the 87C196C B are functionally identically to those of the 8XC196NT However the 87C196CB implements all eight pins of port 0 and the 100 pin 87C196CB also implements all eight pins of the EPORT The associated registers have been modified to include bits corre sponding to the upper nibble of the ports Table 5 1 provides an overview of the 8XC196CB s I O ports Figure 5 1 illustrates the port O pin state register and Figures 5 2 through 5 5 illustrate the EPORT registers Table 5 1 87C196CB Input Output Ports Port Bits Type Direction Associated Peripheral s Port 0 8 Standard Input only A D converter Port 1 8 Standard Bidirectional EPA and timers Port 2 8 Standard Bidirectional SIO interrupts bus control clock gen Port 3 8 Memory mapped Bidirectional Address data bus Port 4 8 Memory mapped Bidirectional Address data bus Port 5 8 Memory mapped Bidirectional Bus control slave port Port 6 8 Standard Bidirectional EPA SSIO 4 84 pin CB UE EPORT 8 100 pin CB Memory mapped Bidirectional Extended address lines PO_PIN Address 1FDAH Each bit of the port 0 pin input PO_PIN register re
69. XTD Application specific ID Application specific CPUUPD 1 NEWDAT 1 Update Write calculate message contents CPUUPD 0 Want to send Update message TX REQ 1 A2596 01 Figure 7 25 Transmitting a Message CPU Flow 7 39 87C196CB SUPPLEMENT intel Bus free TX REQ 1 CPUUPD 0 Received remote frame with same identifer as this message object NEWDAT 0 Load message into buffer Yes TX REQ 1 RMTPND 1 No No 724 Transmission successful Yes INT_PND 1 Ho TX REQ 0 Yes RMTPND 0 Yes INT_PND 1 A2595 02 Figure 7 26 Transmitting a Message CAN Controller Flow 7 40 intel CAN SERIAL COMMUNICATIONS CONTROLLER 7 9 DESIGN CONSIDERATIONS This section outlines design considerations for the CAN controller 7 9 1 Hardware Reset A hardware reset clears the error management counters and the bus off state and leaves the reg isters with the values listed in Table 7 14 Table 7 14 Register Values Following Reset Register Hex Address Reset Value Control 1E00 01H Status 1E01 undefined Standard Global Mask 1E06 1E07 unchanged undefined at power up Extended Global Mask 1E08 1E0B unchanged undefined at power up Message 15 Mask 1E0C 1E0F unchanged undefined at power up Bit Timing O 1E3F unchanged undefined at power up Bit Timing 1 1E4F unchanged
70. a word Table 3 9 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows M OOE0 00FFH 00CO O0FFH 0080 00FFH Register Mnemonic emory Location WSR Direct WSR Direct WSR Direct Address Address Address EPA2 TIME 1F6AH 7BH 00 3DH 00 1EH OOEAH EPA3_TIMEt 1F6EH 7BH 00 3DH 00 1EH 00 EPA8_TIMEt 1F82H 7CH 00E2H 3EH 00C2H 1FH 0082H EPA9_TIME 1F86H 7CH 00 6 00C6H 1FH 0086H EPAIPV 1FA8H 7DH 00E8H 3EH 00E8H 1FH 00A8H P1 DIR 1FD2H 7EH 00F2H 3FH 00D2H 1FH 00D2H P2_DIR 1FCBH 7EH 00 00CBH 1FH 00CBH P6 DIR 1FD3H 7EH 00F3H 3FH 00D3H 1FH 00D3H P1_MODE 1FDOH 7EH OOFOH 3FH 00DOH 1FH 00DOH P2_MODE 1FC9H 7EH 00E9H 3FH 00C9H 1FH 00C9H P6 MODE 1FD1H 7EH 00F1H 3FH 00D1H 1FH 00D1H PO_PIN 1FDAH 7EH 00 00DAH 1FH 00DAH P1 PIN 1FD6H 7EH 00F6H 3FH 00D6H 1FH 00D6H P2_PIN 1FCFH 7EH 00EFH 3FH 00 1 00 P6 1FD7H 7EH 00F7H 3FH 00D7H 1FH 00D7H P1_REG 1FD4H 7EH 00F4H 3FH 00D4H 1FH 00D4H P2_REG 1FCDH 7EH 00EDH 3FH 00CDH 1FH 00CDH 6 REG 1FD5H 7EH 00F5H 3FH 00D5H 1FH 00D5H SBUF_RX 1FB8H 7DH 00F8H 3EH 00F8H 1FH 00B8H SBUF_TX 1FBAH 7DH 00 00 1 00BAH SP_BAUD 1FBCH 7DH OOFCH 3EH 00FCH 1FH 00BCH SP_CON 1FBBH 7DH 00FBH 3EH 00FBH 1FH 00BBH SP_STATUS 1FB9H 7DH 00F9H 3EH 00F9H 1FH 00B9H SSIO_BAUD 1F
71. age object only if this bit pair indicates that the message is valid If multiple message objects have the same identifier only one can be valid at any given time During initialization software should clear this bit for any unused message objects Software can clear this bit if a message is no longer needed or if you need to change a message object s contents or identifier 5 4 TXIE Transmit Interrupt Enable Receive message objects do not use this bit pair For transmit message objects set this bit pair to enable the CAN peripheral to initiate a transmit TX interrupt after a successful trans mission You must also set the interrupt enable bit CAN_CON 1 to enable the interrupt bit5 bit 4 0 1 no interrupt 1 0 generate an interrupt Figure 7 14 CAN Message Object x Control 0 CAN_MSGxCONO Register 7 24 intel CAN SERIAL COMMUNICATIONS CONTROLLER CAN MSGxCONO Continued Address 1Ex0H x 1 F x 1 15 87C196CB Reset State Unchanged Program the CAN message object x control 0 CAN MSGxCONO register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt The least significant bit pair indicates whether an interrupt is pending This register consists of four bit pairs the most significant bit of each pair is in true form and the least significant bit is in complement form This format allows software
72. al pull up resistors During auto programming and ROM dump ports 3 and 4 serve as a regular system bus to access external memory P4 6 and P4 7 are left unconnected P1 1 and P1 2 serve as the upper address lines Slave programming PBUS 7 0 are multiplexed with AD7 0 SLP7 0 and P3 7 0 PBUS 15 8 are multiplexed with AD15 8 and P4 7 0 Auto programming PBUS 7 0 are multiplexed with AD7 0 SLP7 0 and P3 7 0 PBUS 13 8 are multiplexed with AD13 8 and P4 5 0 PBUS15 14 are multiplexed with P1 2 1 PMODE 3 0 Programming Mode Select The value on the PMODE pins determines the programming mode OH serial port programming 5H slave programming 6H ROM dump CH auto programming PMODE is sampled after a device reset and must be static while the part is operating PMODE 3 0 are multiplexed with 0 7 4 and ACH7 4 PLLEN Phase locked Loop Enable This input pin enables and disables the on chip clock multiplier feature 0 standard mode internal frequency is equal to Fyz 1 1 quadruple mode internal frequency is equal to 4Fyc4 4 SIGNAL DESCRIPTIONS Table A 3 Signal Descriptions Continued Name Type Description PROG Programming Start During programming a falling edge latches data on the PBUS and begins programming while a rising edge ends programming The current location is programmed with the same data as long as PROG remains asserted so the data on the PBUS must remain stable while PR
73. and chip configuration byte reads INST is low during internal memory fetches INST is multiplexed with P5 1 and SLPCS Interrupt Output This active low output indicates that a pending interrupt requires use of the external bus How quickly the microcontroller asserts INTOUT depends upon the status of HOLD and HLDA and whether the microcontroller is executing from internal or external program memory If the microcontroller is executing from internal memory and receives an interrupt request while in hold it asserts INTOUT immediately However if the microcontroller is executing code from external memory and receives an interrupt request while in hold it asserts BREQ and waits until the external device deasserts HOLD to assert INTOUT If the microcontroller is executing code from external memory and receives an interrupt request as it is going into hold between the time that an external device asserts HOLD and the time that the microcontroller responds with HLDA the microcontroller asserts both HLDA and INTOUT and keeps them asserted until the external device deasserts HOLD INTOUT is multiplexed with P2 4 and AINC Nonmaskable Interrupt In normal operating mode a rising edge on NMI generates a nonmaskable interrupt NMI has the highest priority of all prioritized interrupts Assert NMI for greater than one state time to guarantee that it is recognized ONCE On circuit Emulation Holding ONCE low during the
74. ant bit is in complement form This format allows software to set or clear any bit with a single write operation without affecting the remaining bits 7 0 MSGLST MSGLST CPUUPD CPUUPD 87C196CB RMTPND RMTPND TX TX REQ NEWDAT NEWDAT Bit Bit Number Mnemonic Function 7 6 RMTPND Remote Request Pending Receive message objects do not use this bit pair The CAN controller sets this bit pair to indicate that a remote frame has requested the transmission of a transmit message object If the CPUUPD bit pair is clear the CAN controller transmits the message object then clears RMTPND Setting RMTPND does not cause a transmission it only indicates that a transmission is pending bit7 bit6 0 1 no pending request 1 0 a remote request is pending 5 4 TX_REQ Transmission Request Set this bit pair to cause a receive message object to transmit a remote frame a request for transmission or to cause a transmit object to transmit a data frame Read this bit pair to determine whether a transmission is in progress bit5 bit 4 0 1 no pending request no transmission in progress 1 0 transmission request transmission in progress Figure 7 15 CAN Message Object x Control 1 CAN_MSGxCON1 Register 7 26 intel CAN SERIAL COMMUNICATIONS CONTROLLER CAN_MSGxCON1 Continued Address 1Ex1H x 1 F x 1 15 87C196CB Reset State Unchanged CAN message
75. ate nonoverlapping time segments a synchro nization delay segment a propagation delay segment and two phase delay segments Figure 7 4 and Table 7 8 The CAN controller implements a bit time as three segments combining PROP SEG and PHASE SEGI into trsgg Figure 7 5 and Table 7 9 This implementation is identical to that of the 82527 CAN peripheral 4 Nominal Bit Time 5 SYNC SEG PROP SEG PHASE SEG PHASE SEG2 Sample Transmit A2603 01 Figure 7 4 A Bit Time as Specified by the CAN Protocol Table 7 8 CAN Protocol Bit Time Segments Symbol Definition SYNC SEG The synchronization delay segment allows for synchronization of the various nodes on the bus An edge is expected to lie within this segment PROP SEG The propagation delay segment compensates for the physical delay times within the network It is twice the sum of the signal s propagation time on the bus line the input comparator delay and the output driver delay The factor of two accounts for the requirement that all nodes monitor all bus transmissions for errors PHASE SEG This segment compensates for edge phase errors It can be lengthened or shortened by resynchronization PHASE SEG2 This segment compensates for edge phase errors It can be lengthened or shortened by resynchronization intel CAN SERIAL COMMUNICATIONS CONTROLLER Bit Time TSEG1 1 tq A TSEG2 1
76. available in either an 84 pin or a 100 pin package The 84 pin 87C196CB like the 8XC196NT has up to 20 external address lines enabling access to 1 Mbyte of linear address space The 100 pin 87C196CB has four additional pins available for external address lines With all 24 external address lines connected the 100 pin 87C196CB can access 16 Mbytes of linear address space 2 1 DEVICE FEATURES Table 2 1 lists the features of the 8XC196NT and the 87C196CB The 87C196CB implements more OTPROM more register RAM four additional A D channels and the CAN peripheral The 100 pin 87C196CB also implements four additional EPORT pins Table 2 1 Features of the 8XC196NT and 87C196CB E S a 2 12185 a glei lsg 18 5 2 tc a 3 e E Bl BE o e 5 a a 62 2 lt O 8XC196NT 68 Oor32K 1K 512 56 10 2 4 1 4 0 87C196CB 84 56K 15 512 56 10 2 8 1 4 2 87C196CB 100 56K 15K 512 60 10 2 8 1 8 2 Register RAM amount includes the 24 bytes allocated to the core SFRs and stack pointer 2 1 87C196CB SUPPLEMENT intel 2 2 BLOCK DIAGRAM Figure 2 1 shows the major blocks within the device The 8XC196NT and 87C196CB have the same peripheral set with the exception of the CAN controller area network peripheral which is unique to the 87C196CB The CAN peripheral manages communications be
77. ble 3 8 Windows Continued MEMORY PARTITIONS WSR Value WSR Value WSR Value for Base Address for 32 byte Window for 64 byte Window 128 byte Window 00 0 00 0 0 0080 00FFH Upper Register File 03E0H 5FH 03C0H 5EH 2FH 03A0H 5DH 0380H 5CH 2EH 17H 0360H 5BH 0340H 5AH 2DH 0320H 59H 0300H 58H 2CH 16H 02E0H 57H 02C0H 56H 2BH 02A0H 55H 0280H 54H 2AH 15H 0260H 53H 0240H 52H 29H 0220H 51H 0200H 50H 28H 14H 01E0H 4FH 01C0H 4EH 27H 01A0H 4DH 0180H 4CH 26H 13H 0160H 4BH 0140H 4AH 25H 0120H 49H 0100H 48H 24H 12H Locations 1FE0 1FFFH contain memory mapped SFRs that cannot be accessed through a window Reading these locations through a window returns FFH writing these locations through a window has no effect 87C196CB SUPPLEMENT intel Table 3 9 WSR Settings and Direct Addresses for Windowable SFRs 32 byte Windows 00 0 64 byte Windows 00C0 00FFH 128 byte Windows 0080 00FFH Register Mnemonic pure WSR address WSR address WER Address AD_COMMAND 1FACH 7DH 00 00 1 00 AD_RESULT 1FAAH 7DH 00EAH 3EH 00EAH 1FH 00AAH AD_TEST 1FAEH 7DH 00EEH 3EH 00 1 00 AD TIME 1FAFH 7DH 00 00 1 OOAFH CAN_BTIMEO 1E3FH 7
78. cts write the data that is to be transmitted to these registers The number of data bytes must match the DLC field in the CAN MSGXxCFG register For example if CAN_MSG1DATAO CAN MSG1DATA1 CAN MSG1DATA2 and MSG1DATAS contain data the DLC field in MSG1CFG must contain 04H Figure 7 16 CAN Message Object Data CAN MSGxDATAO 7 Registers 7 28 intel CAN SERIAL COMMUNICATIONS CONTROLLER 7 6 ENABLING THE CAN INTERRUPTS The CAN controller has a single interrupt input INT13 to the interrupt controller Generally PTS interrupt service is not useful for the CAN controller because the PTS cannot readily deter mine the source of the CAN controller s multiplexed interrupts To enable the CAN controller s interrupts you must enable the interrupt source by setting the CAN bit in INT MASKI see Ta ble 7 2 on page 7 3 and globally enable interrupt servicing by executing the EI instruction In addition you must set bits in the CAN control register Figure 7 17 and the individual message objects control register 0 Figure 7 18 to enable the individual interrupt sources within the CAN controller CAN_CON Address 1E00H 87C196CB Reset State 01H Program the CAN control CAN_CON register to control write access to the bit timing registers to enable and disable CAN interrupts and to control access to the CAN bus 7 0 87C196CB CCE EIE SIE IE INIT Bit B
79. direct indexed extenceg ERR External device memory or I O connected to address data bus Indirect indexed extended OOFFFF External devi d OTPROM tt Indirect indexed ded 002000 xternal device or remappe ndirect indexed extende 001FFF a 001FEO Memory mapped SFRs Indirect indexed extended 001FDF Indirect indexed extended 001 00 ORAS windowed direct 001EFF 001E00 CAN SFRs Indirect indexed extended 001DFF Indirect indexed 001C00 memalregister RAM windowed direct 001BFF External device memory or I O connected to address data bus i 000600 future SFR expansion Indirect indexed extended 0005 Internal code and data RAM 000400 mapped identically into pages OOH Indirect indexed extended 0003FF T i Indirect indexed 000100 Upper register file register RAM windowed direct 0000FF 2 oe 000000 Lower register file register RAM stack pointer CPU SFRs Direct indirect indexed For the 87C196CB the program and special purpose memory locations FF2000 FFFFFFH can reside either in external memory or in internal OTPROM Locations xF0000 xFOOFFH are reserved for in circuit emulators Do not use these locations except to initialize them Except as otherwise noted initialize unused program memory locations and reserved memory locations to FFH tit These locations can be either external memory CCB2 2 0 or a copy of the OTPROM CCB2 2 1
80. e Unchanged Program the CAN bit timing 1 CAN BTIME 1 register to define the sample time and the sample mode The CAN controller samples the bus during the last one in single sample mode or three in three sample mode time quanta of trsec1 and initiates a transmission at the end of tisego Therefore specifying the lengths of 1 and defines both the sample point and the trans mission point 7 0 87C196CB SPL TSEG2 TSEG1 Bit Bit 2 Number Mnemonic Function 7 SPL Sampling Mode This bit determines how many samples are taken to determine a valid bit value 0 1 sample 1 3 samples using majority logic 6 4 TSEG2 Time Segment 2 This field determines the length of time that follows the sample point within a bit time Valid programmed values 1 7 the hardware adds 1 to this value 3 0 TSEG1 Time Segment 1 This field defines the length of time that precedes the sample point within a bit time Valid programmed values are 2 15 the hardware adds 1 to this value In three sample mode the hardware adds 2 time quanta to allow time for the two additional samples The CCE bit CAN_CON 6 must be set to enable write access to this register For correct operation according to the CAN protocol the total bit time must be at least 8 time quanta so the sum of the programmed values of TSEG1 and TSEG2 must be at least 5 The total bit time is the sum Of tsync sea trsee1 trsee2 The length of tsy
81. ecovery sequence clears this bit and clears the error counters See Bus off State on page 7 41 6 WARN Warning Status The CAN peripheral sets this read only bit to indicate that an error counter has reached 96 indicating an abnormal rate of errors on the CAN bus Reserved This bit is undefined 4 RXOK Reception Successful The CAN peripheral sets this bit to indicate that a message has been successfully received error free regardless of acknowledgment since the bit was last cleared Software must clear this bit when it services the interrupt 3 TXOK Transmission Successful The CAN peripheral sets this bit to indicate that a message has been successfully transmitted error free and acknowledged by at least one other node since the bit was last cleared Software must clear this bit when it services the interrupt 2 0 LEC2 0 Last Error Code This field indicates the error type of the first error that occurs in a message frame on the CAN bus Error Detection and Management Logic on page 7 9 describes the error types LEC2 LEC1 LECO Error Type 0 0 0 no error 0 0 1 stuff error 0 1 0 form error 0 1 1 acknowledgment error 1 0 0 bit 1 error 1 0 1 bit O error 1 1 0 CRC error 1 1 1 unused Figure 7 20 CAN Status CAN_STAT Register If an individual message object caused the interrupt request CAN INT 02 10H software can read the associated message object control 0 reg
82. egister 7 3 7 21 MSGxCONO register 7 3 7 24 7 31 7 34 MSGxCONI register 7 4 7 26 INDEX MSGxDATAO 7 register 7 28 CAN MSGxDATAx register 7 4 CAN MSQGxID register 7 4 CAN MSGxIDO 3 register 7 22 CAN MSKIS register 7 4 7 20 CAN SGMSK register 7 4 7 18 STAT register 7 4 7 33 register 9 3 CLKOUT and internal timing 2 2 2 4 Clock circuitry 2 3 Clock phases internal 2 4 D Documents related 1 2 E DIR register 5 2 EP MODE register 5 2 EPORT 5 1 register 5 3 EP REG register 5 3 F Formulas clock period t 2 4 PH1 and PH2 frequency 2 4 state time 2 4 Frequency f 2 4 2 4 Idle mode pin status A 14 Interrupts 4 1 INT MASKI register 4 2 INT PENDI register 4 2 Manual contents summary 1 1 Memory mapping auto programming mode 10 2 serial port programming mode 10 3 Index 1 87C196CB SUPPLEMENT P PIN register 5 1 Period t 2 4 Pin diagrams A 1 Pins reset status A 14 A 15 Port 0 5 1 Powerdown mode pin status A 14 R Registers COMMAND 6 2 AD RESULT 6 3 CAN BTIMEO 7 3 7 15 CAN BTIMEI 7 3 7 16 CAN CON 7 3 7 13 7 29 CAN EGMSK 7 3 7 19 CAN INT 7 3 7 32 CAN MSGxCFG 7 3 7 21 CAN MSGxCONO 7 3 7 24 7 31 7 34 CAN MSGxCONI 7 4 7 26 CAN MSGxDATAO 7 7 28 CAN MSGxDATAx 7 4 CAN MSGAXID 7 4 CAN MSGxIDO 3 7 22 CAN MSKIS 7 4 7 20 CAN SGMSK 7 4
83. el Chapter 9 Interfacing with External Memory discusses differences in the bus timing modes supported by the 8XC196NT and the 87C196CB Chapter 10 Programming the Nonvolatile Memory describes the memory maps and rec ommended circuits to support programming of the 87C196CB s 56 Kbytes of OTPROM Appendix A Signal Descriptions describes the additional signals implemented on the 87C196CB Glossary defines terms with special meaning used throughout this supplement Index lists key topics with page number references 1 2 RELATED DOCUMENTS Table 1 1 lists additional documents that you may find useful in designing systems incorporating the 87C196CB microcontroller Table 1 1 Related Documents Title and Description Order Number 8XC196NT Microcontroller User s Manual 272317 Automotive Products handbook 231792 87C196CB 20 MHz Advanced 16 Bit CHMOS Microcontroller with 272405 Integrated CAN 2 0 datasheet 1 2 intel Architectural Overview intel CHAPTER 2 ARCHITECTURAL OVERVIEW This chapter describes architectural differences between the 87C196CB and the 8XC196NT Both the 8XC196NT and the 87C196CB are designed for high speed calculations and fast I O With the addition of the CAN controller area network peripheral the 87C 196CB reduces point to point wiring requirements making it well suited to automotive and factory automation appli cations The 87C196CB is
84. er 0 87C196CB SUPPLEMENT intel 7 3 5 1 Bit Timing Equations The bit timing equations of the integrated CAN controller are equivalent to those for the 82527 CAN peripheral with the DSC bit in the CPU interface register set system clock divided by two The following equations show the timing calculations for the integrated CAN controller and the 82527 CAN peripheral respectively Fosc CAN Controller CAN bus frequency 2x BRP 1 3 TSEG1 TSEG2 Fosc 82527 CAN bus frequency gt DSC 1 x BRP 1 x 3 TSEG1 TSEG2 where Fosc the input clock frequency on the XTAL1 pin in MHz BRP the value of the BRP bit in bit timing register 0 TSEG1 the value of the TSEG1 field in bit timing register 0 TSEG2 the value of the TSEG1 field in bit timing register 1 Table 7 10 defines the bit timing relationships of the CAN controller Table 7 10 Bit Timing Relationships I Definition terre tsync_sea rsea1 trsec2 bari input clock period on XTAL1 50 ns at 20 MHz operation tq 2tyrau X BRP 1 where BRP is a field in bit timing register 0 valid values are 0 63 tsync_seG 114 trseat TSEG1 1 x tq where TSEG1 is a field in bit timing register 1 valid values are 2 15 trseg2 TSEG2 1 x tq where TSEG2 is a field in bit timing register 1 valid values are 1 7 1 x tq where SJW is a field in bit timing register O
85. er for message object 15 to allow it to accept a greater range of message identifiers than mes sage objects 1 14 can Clear a mask bit to accept either a zero or a one in that position The CAN controller applies the appropriate global mask to each incoming message identifier and checks for an acceptance match on message objects 1 14 If no match exists it then applies the message 15 mask and checks for a match on message object 15 7 17 87C196CB SUPPLEMENT intel CAN SGMSK Address 1E07H 1E06H 87C196CB Reset State Unchanged Program the CAN standard global mask SGMSK register to mask don t care specific message identifier bits for standard message objects 15 8 87C196CB MSK20 MSK19 MSK18 7 0 MSK28 MSK27 MSK26 msk25 MSK24 MSK23 MSK22 MSK21 Bit Bit Number Mnemonic Function 15 13 MSK20 18 ID Mask These bits individually mask incoming message identifier ID bits 0 mask the ID bit accept either O or 1 1 accept only an exact match 12 8 Reserved for compatibility with future devices write zeros to these bits 7 0 MSK28 21 ID Mask These bits individually mask incoming message identifier ID bits 0 mask the ID bit accept either 0 or 1 1 accept only an exact match Figure 7 9 CAN Standard Global Mask CAN_SGMSK Register intel CAN SERIAL COMMUNICATIONS
86. f this pin is held low during reset the device will enter a reserved test mode so exercise caution if you use this pin for input If you choose to configure this pin as an input always hold it high during reset and ensure that your system meets the specification see datasheet to prevent inadvertent entry into a test mode Port 5 is multiplexed as follows P5 0 ALE ADV SLPALE P5 1 INST SLPCS P5 2 WR WRL SLPWR P5 3 RD SLPRD SLPINT P5 5 BHE WRH P5 6 READY and P5 7 BUSWIDTH 87C196CB Supplement intel Table A 3 Signal Descriptions Continued Name Type Description P6 7 0 1 0 Port 6 This is a standard 8 bit bidirectional port Port 6 is multiplexed as follows P6 0 EPA8 COMPO P6 1 EPA9 COMP1 P6 2 T1CLK P6 3 T1DIR 6 4 5 0 P6 5 SDO P6 6 SC1 and P6 7 SD1 PACT O Programming Active During auto programming or ROM dump a low signal indicates that programming or dumping is in progress while a high signal indicates that the operation is complete PACT is multiplexed with P2 7 and CLKOUT PALE Programming ALE During slave programming a falling edge causes the device to read a command and address from the PBUS PALE is multiplexed with P2 1 and RXD PBUS15 0 1 0 Address Command Data Bus During slave programming ports 3 and 4 serve as a bidirectional port with open drain outputs to pass commands addresses and data to or from the device Slave programming requires extern
87. f time that the input channel is actually connected to the sample capacitor The variation in the sample time The period of time that begins when the sample capacitor is attached to a selected channel of an A D converter and ends when the sample capacitor is disconnected from the selected channel All input pins with the exception of are sampled inputs The input pin is sampled one state time before the read buffer is enabled Sampling occurs during PH1 while CLKOUT is low and resolves the value high or low of the pin before it is presented to the internal bus If the pin value changes during the sample time the new value may or may not be recorded during the read RESET is a level sensitive input EXTINT is normally a sampled input however the powerdown circuitry uses EXTINT as a level sensitive input during powerdown mode Successive approximation register A component of the A D converter The 1 value of a bit or the act of giving it a 1 value See also clear Special function register An 8 bit signed variable with values from E through 27 1 A method for converting data to a larger format by filling the upper bit positions with the value of the sign This conversion preserves the positive or negative value of signed integers Current flowing into a device to ground Always a positive value Glossary 9 87C196CB SUPPLEMENT source current SP special interrupt special purp
88. flects the current state of the corresponding pin regardless of the pin configuration Reset State XXH 7 0 PIN7 PING PIN5 PIN4 PIN3 PIN2 PIN1 PINO Bit Bit Number Mnemonic Function 7 0 PIN7 0 Port 0 Pin x Input Value This bit contains the current state of PO x Figure 5 1 Port x Pin Input Px_PIN Register 87C196CB SUPPLEMENT intel EP DIR Address 1FE3H zi Reset State FFH In I O mode each bit of the extended port I O direction register controls the direction of the corresponding pin Clearing a bit configures a pin as a complementary output setting a bit configures a pin as either an input or an open drain output Open drain outputs require external pull ups Any pin that is configured for its extended address function is forced to the complementary output mode except during reset hold idle and powerdown 7 0 PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PINO Bit Bit Number Mnemonic Function 7 0 PIN7 0 Extended Address Port Pin x Direction This bit configures EPORT x as a complementary output or an input open drain output 0 complementary output 1 input or an open drain output Figure 5 2 Extended Port I O Direction DIR Register EP MODE Address 1FE1H Reset State FFH Each bit of the extended port mode register controls whether the corresponding pin functions as
89. has only 32 Kbytes FF2000 FF9FFFH The 87C196CB s programming signals registers and proce dures are the same as those of the 8XC196NT This chapter describes the differences in memory mapping and programming circuits for the 87C196CB 10 1 SIGNATURE WORD AND PROGRAMMING VOLTAGES The 87C196CB s programming voltages are the same of those of the 8XC196NT however the signature word differs Table 10 1 lists the signature word and programming voltages Table 10 1 Signature Word and Programming Voltages Signature Word Programming V Programming Vpp Device Location Value Location Value Location Value 87C196CB 0070H 87CBH 0072H 40H 0073H OAOH 10 2 MEMORY MAP FOR SLAVE PROGRAMMING MODE Because the 87C196CB has an additional 24 Kbytes of OTPROM its memory map Table 10 2 differs from that of the 8XC196NT The remaining information on slave programming is correct for the 87C196CB 10 1 87C196CB SUPPLEMENT intel Table 10 2 Slave Programming Mode Memory Map Description Address Comments OTPROM FF2000 FFFFFFH OTPROM Cells OFD 0778H OTPROM Cell DED 0758H UPROM Cell DEI 0718H UPROM Cell PCCB 0218H Test EPROM Programming Voc 0072H Read Only Programming Vpp 0073H Read Only Signature word 0070H Read Only tThese bits program the UPROM cells Once these bits are programmed they cannot be erased and dynamic fail
90. he interrupt need not be enabled but the pin must be configured as a special function input If the EXTINT interrupt is enabled the CPU executes the interrupt service routine Otherwise the CPU executes the instruction that immediately follows the command that invoked the power saving mode In idle mode asserting any enabled interrupt causes the device to resume normal operation EXTINT is multiplexed with P2 2 and PROG 87C196CB Supplement intel Table A 3 Signal Descriptions Continued Name Type Description HLDA Bus Hold Acknowledge This active low output indicates that the CPU has released the bus as the result of an external device asserting HOLD HLDA is multiplexed with P2 6 and CPVER HOLD Bus Hold Request An external device uses this active low input signal to request control of the bus This pin functions as HOLD only if the pin is configured for its special function and the bus hold protocol is enabled Setting bit 7 of the window selection register WSR enables the bus hold protocol HOLD is multiplexed with P2 5 INST INTOUT NMI Instruction Fetch This active high output signal is valid only during external memory bus cycles When high INST indicates that an instruction is being fetched from external memory The signal remains high during the entire bus cycle of an external instruction fetch INST is low for data accesses including interrupt vector fetches
91. hether CCR2 is loaded 7 0 MSEL1 MSELO 0 1 WDE BW1 IRC2 LDCCB2 Bit Bit Function Number Mnemonic 1 IRC2 Ready Control This bit along with IRCO CCRO 4 and IRC1 CCRO 5 limits the number of wait states that can be inserted while the READY pin is held low Wait states are inserted into the bus cycle either until the READY pin is pulled high or until this internal number is reached IRC2 IRC1 IRCO zero wait states illegal illegal one wait state two wait states three wait states READY pin controlled If you choose the READY pin controlled option you must keep P5 6 configured as a special function input and add external hardware to count wait states and release READY within a specified time 0 LDCCB2 Load CCB2 Setting this bit causes CCB2 to be read an 2200 00 xo 20 a0Xx 0 The CCRs are loaded with the contents of the chip configuration bytes CCBs after reset unless the microcontroller is entering programming modes in which case the programming chip configuration bytes PCCBs are used The CCBs reside in internal nonvolatile memory at addresses FF2018H CCBO FF201AH CCB1 and FF201CH CCB2 Figure 9 2 Chip Configuration 1 CCR1 Register Continued intel 10 Programming the Nonvolatile Memory intel CHAPTER 10 PROGRAMMING THE NONVOLATILE MEMORY The 87C196CB has 56 Kbytes of OTPROM FF2000 FFFFFFH while the 8XC196NT
92. ing 3 phase AC induction motors brushless DC motors and other devices requiring multiple PWM outputs See watchdog timer Any 16 bit unit of data An unsigned 16 bit variable with values from 0 through DIT A method for converting data to a larger format by filling the upper bit positions with zeros An ideal A D converter s first code transition occurs when the input voltage is 0 5 LSB Zero offset error is the difference between 0 5 LSB and the actual input voltage that triggers an A D converter s first code transition Glossary 11 intel Index intel A A D converter signals 6 1 AD COMMAND register 6 2 AD RESULT register 6 3 Auto programming mode circuit 10 3 memory map 10 2 B Block diagram CAN peripheral 7 2 clock circuitry 2 2 core and peripherals 2 2 Bus timing modes 9 1 9 2 comparison 9 1 9 2 C CAN serial communications controller 7 1 7 42 address map 7 5 bit timing 7 10 7 12 block diagram 7 2 bus off state 7 41 error detection and management logic 7 9 message acceptance filtering 7 6 frames 7 7 extended 7 8 standard 7 8 identifiers effect of masking on 7 7 objects 7 5 7 6 overview 7 1 7 2 programming 7 4 7 31 receive and transmit priorities 7 6 registers 7 3 7 4 signals 7 3 CAN BTIMEO register 7 3 7 15 CAN BTIMEI register 7 3 7 16 CON register 7 3 7 13 7 29 CAN EGMSK register 7 3 7 19 CAN INT register 7 3 7 32 MSGxaCFG r
93. ings and Direct Addresses for Windowable 5 3 11 4 1 Interrupt Sources Vectors and 4 1 5 1 87C196CB Input Output Ports nennen nnne nnns 5 1 6 1 A DiGonverter Piris it D RR CRI ERU er MP 6 1 7 1 GAN Eontroller Signals eu ea 7 3 7 2 Control and Status Registers 4 8 0184084 7 3 7 3 CAN Controller Address Map mmm nene nenea nenea 7 5 7 4 Message Object 7 6 7 5 Effect of Masking on Message 7 7 7 6 Standard Message Frame anne 7 8 7 7 Extended Message 2 422242441 aaa e 7 8 7 8 CAN Protocol Bit Time Segments nenea nana nana nana 7 10 7 9 CAN Controller Bit Time 40040 00 7 11 7 10 Bit Timing 7 12 7 11 Bit Timing Requirements for Synchronization men nenea nana ana 7 17 7 12 Control Register Bit pair 7 23 7 13 Cross reference for Register Bits Shown in 7 35 7 14 Register Values Following 7 41 9 1 Modes 0 and Timing 9 1 10 1 Signature Word and
94. interrupt request INT_PEND1 0012H Interrupt Pending 1 The CAN bit in this register when set indicates a pending CAN interrupt request The CCE bit in CON must be set to enable write access to the bit timing registers In register names x 1 15 in addresses y 1 F 7 3 CAN CONTROLLER OPERATION This section describes the address map message objects message frames which contain mes sage objects error detection and management logic and bit timing for CAN transmissions and receptions intel CAN SERIAL COMMUNICATIONS CONTROLLER 7 39 4 Address Map The CAN controller has 256 bytes of RAM containing 15 message objects and control and status registers at fixed addresses Each message object occupies 15 consecutive bytes beginning at a base address that is a multiple of 16 bytes The byte above each message object is reserved indi cated by a dash character or occupied by a control register The lowest 16 bytes of RAM contain the remaining control and status registers Table 7 3 This 256 byte section of memory can be windowed for register direct access Table 7 3 CAN Controller Address Map Hex Address Description Hex Address Description 1EFF 1E6F 1EFO 1EFE Message Object 15 1E60 1E6E Message Object 6 1EEF 1E5F Interrupt Register 1EEO 1EEE Message Object 14 1E50 1E5E Mes
95. ion describe the steps that your software shown as CPU and the CAN controller execute to receive and transmit messages Table 7 13 lists the register bits shown in the diagrams along with their associated registers and a cross reference to the figure that de scribes them Table 7 13 Cross reference for Register Bits Shown in Flowcharts Bit Mnemonic Register Mnemonic Figure and Page CPUUPD CAN_MSGxCON1 Figure 7 15 on page 7 26 DIR CAN_MSGxCFG Figure 7 12 on page 7 21 DLC CAN_MSGxCFG Figure 7 12 on page 7 21 ID CAN_MSGxID Figure 7 13 on page 7 22 INT_PND CAN_MSGxCONO Figure 7 14 on page 7 24 MSGLST CAN_MSGxCON1 Figure 7 15 on page 7 26 MSGVAL CAN_MSGxCONO Figure 7 14 on page 7 24 NEWDAT CAN_MSGxCON1 Figure 7 15 on page 7 26 RMTPND CAN_MSGxCON1 Figure 7 15 on page 7 26 RXIE CAN_MSGxCONO Figure 7 14 on page 7 24 TXIE CAN_MSGxCONO Figure 7 14 on page 7 24 TX_REG CAN_MSGxCON1 Figure 7 15 on page 7 26 XTD CAN_MSGxCFG Figure 7 12 on page 7 21 7 35 87C196CB SUPPLEMENT intel Power Up All bits undefined MSGVAL 1 0 Application specific j RXIE Application specific Initialization NEWDAT 0 RMTPND 0 TX 0 MSGLST 0 DLC don t care DIR 0 receive XTD Application specific ID Application specific NEWDAT 0 Process message contents Process Restart Process Request update
96. ip Select SLPCS must be held low to enable slave port operation SLPCS is multiplexed with P5 1 and INST SLPINT O Slave Port Interrupt This active high slave port output signal can be used to interrupt the master processor SLPINT is multiplexed with P5 4 and a special test mode entry pin See P5 7 0 for special considerations SLPRD l Slave Port Read Control Input This active low signal is an input to the slave Data from the P3_REG or SLP_STAT register is valid after the falling edge of SLPRD SLPRD is multiplexed with P5 3 and RD SLPWR Slave Port Write Control Input This active low signal is an input to the slave The rising edge of SLPWR latches data on port 3 into the P3_PIN or SLP_CMD register SLPWR is multiplexed with P5 2 WR WRL T1CLK Timer 1 External Clock External clock for timer 1 Timer 1 increments or decrements on both rising and falling edges of T1CLK Also used in conjunction with T1DIR for quadrature counting mode and External clock for the serial I O baud rate generator input program selectable T1CLK is multiplexed with P6 2 T2CLK Timer 2 External Clock External clock for timer 2 Timer 2 increments or decrements on both rising and falling edges of T2CLK Also used in conjunction with T2DIR for quadrature counting mode T2CLK is multiplexed with P1 0 and EPAO T1DIR Timer 1 External Direction External direction up down for timer 1 Timer 1 increments when T1DIR is high and decrements whe
97. ister Figure 7 21 The INT PND bit pair will be set indicating that a receive or transmit interrupt request is pending 7 83 87C196CB SUPPLEMENT intel CAN MSGxCONO Address 1 x 1 F n 1 15 Reset State Unchanged Program the CAN message object x control O register CAN MSGxCONO to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt The most significant bit pair indicates whether an interrupt is pending This register consists of four bit pairs the most significant bit of each pair is in true form and the least significant bit is in complement form This format allows software to set or clear any bit with a single write operation without affecting the remaining bits 7 0 MSGVAL MSGVAL TXIE TXIE RXIE RXIE INT PND INT PND Nube LM Function 7 6 MSGVAL Message Object Valid 5 4 TXIE Transmit Interrupt Enable 3 2 RXIE Receive Interrupt Enable 1 0 INT_PND Interrupt Pending This bit pair indicates that the CAN peripheral has initiated a transmit TX or receive RX interrupt Software must clear this bit when it services the interrupt 01 no interrupt 10 an interrupt was generated Figure 7 21 CAN Message Object x Control 0 CAN _MSGxCONO Register 7 34 intel 7 8 FLOW DIAGRAMS CAN SERIAL COMMUNICATIONS CONTROLLER The flow diagrams in this sect
98. ister selects the A D channel number to be converted controls whether the A D converter starts immediately or with an EPA command and selects the conversion mode 0 1 0 GO ACH2 ACH1 ACHO Bit Bit f Number Mnemonic Function 7 6 Reserved for compatibility with future devices write zeros to these bits 5 4 M1 0 A D These bits determine the A D mode M1 MO Mode 10 bit conversion 8 bit conversion threshold detect high threshold detect low 3 GO A D Conversion Trigger Writing this bit arms the A D converter The value that you write to it determines at what point a conversion is to start 0 EPA initiates conversion 1 start immediately 2 0 ACH2 0 A D Channel Selection Write the A D conversion channel number to these bits The 87C196CB has eight A D channel inputs numbered 0 7 00 While a threshold detection mode is selected for an analog input pin no other conversion be started If another value is loaded into AD COMMAND the threshold detection mode is disabled and the new command is executed tt Itis the act of writing to the GO bit rather than its value that starts a conversion Even if the GO bit has the desired value you must set it again to start a conversion immediately or clear it again to arm it for an EPA initiated conversion Figure 6 1 A D Command AD_COMMAND Register intel ANALOG TO DIGITAL A
99. it 2 Function Number Mnemonic unco Reserved for compatibility with future devices write zero to this bit CCE Change Configuration Enable 5 4 Reserved for compatibility with future devices write zeros to these bits EIE Error Interrupt Enable This bit enables and disables the bus off and warn interrupts 0 disable bus off and warn interrupts 1 enable bus off and warn interrupts 2 SIE Status change Interrupt Enable This bit enables and disables the successful reception RXOK successful transmission TXOK and error code change LEC2 0 interrupts 0 disable status change interrupt 1 enable status change interrupt When the SIE bit is set the CAN controller generates a successful reception RXOK interrupt request each time it receives a valid message even if no message object accepts it Figure 7 17 CAN Control CAN_CON Register 7 29 87C196CB SUPPLEMENT intel CAN CON Continued Address 1E00H 87C196CB Reset State 01H Program the CAN control CAN_CON register to control write access to the bit timing registers to enable and disable CAN interrupts and to control access to the CAN bus 7 0 87C196CB CCE EIE SIE IE INIT Bit Bit i Function Number Mnemonic 1 IE Interrupt Enable This bit globally enables and disables interrupts error status change and message object transmit and receive interrupts
100. ith a standard identifier If you accidentally clear the XTD bit for a message that has an extended iden tifier the CAN controller will clear the extended bits in the identification register If you set the XTD bit for a message object that message object cannot receive message objects with standard identifiers For a transmit message set the DIR bit and write the number of programmed data bytes 0 8 to the DLC field For a receive message clear the DIR bit The CAN controller stores the data length from the received message in the DLC field 7 21 87C196CB SUPPLEMENT intel 7 5 2 Programming the Message Object Identifier Each message identifier register Figure 7 13 specifies the message s identifier For messages with extended identifiers write the identifier to bits ID28 0 For messages with standard identi fiers write the identifier to bits ID28 18 Software can change the identifier during normal oper ation without requiring a subsequent device reset Clear the MSGVAL bit in the corresponding message control register 0 to prevent the CAN controller from accessing the message object while the modification takes place then set the bit to allow access CAN MSGxID0 3 Address 1Ex5H 1EX4H x 1 15 87C196CB 1Ex3H 1EX2H x 1 F Reset State Unchanged Write the message object s identifier to the CAN message object x identifier MSGxID0 3 register Software can change the identifier during normal operation Clea
101. knowledgment errors so this error type does not cause a bus off state bit 1 error the CAN controller tried to send a recessive logic 1 bit as part of a transmitted message with the exception of the arbitration field but the monitored CAN bus value was dominant logic 0 bit 0 error the CAN controller tried to send a dominant logic 0 bit as part of a transmitted message with the exception of the arbitration field but the monitored CAN bus value was recessive logic 1 CRC error the CRC checksum received for an incoming message does not match the CRC value that the CAN controller calculated for the received data The CAN status register indicates the type of the first transmission error that occurred on the CAN bus and whether an abnormal number of errors have occurred Two counters a receive error counter and a transmit error counter track the number of errors The status register s warning bit is set when the receive or transmit error counter reaches 96 the bus off bit is set when either counter reaches 256 If this occurs the CAN controller isolates itself from the CAN bus floats the TX pin Software must clear the INIT bit in the control register Figure 7 6 on page 7 13 to begin a bus off recovery sequence 7 9 87C196CB SUPPLEMENT intel 7 3 5 Bit Timing A message object consists of a series of bits transmitted in consecutive bit times The CAN pro tocol specifies a bit time composed of four separ
102. ll down LoZO Low impedance strongly driven low WK1 Weak pull up LoZ1 Low impedance strongly driven high ODIO Open drain I O Table A 5 87C196CB Pin Status Port Pins Multiplexed Status During Status During Status During With Reset Idle Powerdown P0 7 4 ACH7 4 HiZ HiZ HiZ P1 7 0 EPA7 0 WK1 Note 3 Note 3 P2 0 TXD WK1 Note 3 Note 3 P2 1 RXD WK1 Note 3 Note 3 A 14 intel Table A 5 87C196CB Pin Status Continued SIGNAL DESCRIPTIONS Port Pins Multiplexed Status During Status During Status During With Reset Idle Powerdown P2 2 EXTINT WK1 Note 3 Note 3 P2 3 BREQ WK1 Note 3 Note 3 P2 4 INTOUT WK1 Note 3 Note 3 P2 5 HOLD WK1 Note 3 Note 3 P2 6 HLDA WK1 Note 3 Note 3 P2 7 CLKOUT Note 3 Note 4 P3 7 0 AD7 0 WKi Note 6 Note 6 P4 7 0 AD15 8 WK1 Note 6 Note 6 EPORT 3 0 AD19 17 WK1 Note 7 Note 7 P5 0 ALE WK1 Note 1 Note 1 P5 1 INST WKO Note 1 Note 1 P5 2 WR WRL WK1 Note 3 Note 3 P5 3 RD WK1 Note 3 Note 3 P5 4 SLPINT WK1 Note 3 Note 3 P5 5 BHE WRH WK1 Note 1 Note 1 P5 6 READY WK1 Note 2 Note 2 P5 7 BUSWIDTH WK1 Note 2 Note 2 P6 1 0 EPA9 8 WK1 Note 3 Note 3 P6 2 T1CLK WK1 Note 3 Note 3 P6 3 T1DIR WK1 Note 3 Note 3 P6 4 SCO WK1 Note 3 Note 3 P6 5 SDO WK1 Note 3 Note 3 P6 6 SC1 WK1 Note 3 Note 3
103. ll write operations WRL is multiplexed with P5 2 SLPWR and WR4 t The chip configuration register 0 CCRO determines whether this pin functions as WR or WRL CCRO 2 1 selects WR CCRO 2 0 selects WRL XTAL1 Input Crystal Resonator or External Clock Input Input to the on chip oscillator and the internal clock generators The internal clock generators provide the peripheral clocks CPU clock and CLKOUT signal When using an external clock or crystal instead of the on chip oscillator connect the clock input to XTAL1 The external clock signal must meet the V specification for XTAL1 see datasheet XTAL2 Inverted Output for the Crystal Resonator Output of the on chip oscillator inverter Leave XTAL2 floating when the design uses a external clock source instead of the on chip oscillator A 3 DEFAULT CONDITIONS Table A 5 lists the default functions of the I O and control pins of the microcontroller with their values during various operating conditions Table A 4 defines the symbols used to represent the pin status Refer to the DC Characteristics table in the datasheet for actual specifications for Vog Vi Vow and Table A 4 Definition of Status Symbols Symbol Definition Symbol Definition 0 Voltage less than or equal to Vo Vu MDO Medium pull down 1 Voltage greater than or equal to Von Vi MD1 Medium pull up HiZ High impedance WKO Weak pu
104. n it is low Also used in conjunction with T1CLK for quadrature counting mode T1DIR is multiplexed with P6 3 SIGNAL DESCRIPTIONS Table A 3 Signal Descriptions Continued Name Type Description T2DIR Timer 2 External Direction External direction up down for timer 2 Timer 2 increments when T2DIR is high and decrements when it is low Also used in conjunction with T2CLK for quadrature counting mode T2DIR is multiplexed with P1 2 and EPA2 TXCAN Transmit This signal carries messages from the integrated CAN controller to other nodes on the CAN bus TXD Transmit Serial Data In serial l O modes 1 2 and 3 TXD transmits serial port output data In mode O it is the serial clock output TXD is multiplexed with P2 0 and PVER PWR Digital Supply Voltage Connect each Vec pin to the digital supply voltage PWR Programming Voltage During programming the V pin is typically at 12 5 V voltage Exceeding the maximum Vpp voltage specification can damage the device Vpp also causes the device to exit powerdown mode when it is driven low for at least 50 ns Use this method to exit powerdown only when using an external clock source because it enables the internal phase clocks but not the internal oscillator VREF Vss Vss1 WR PWR GND Reference Voltage for the A D Converter This pin also supplies operating voltage to both the analog portion of the A D
105. nc sec is 1 time quanta and the hardware adds 1 to both TSEG1 and TSEG2 Therefore if TSEG1 TSEG2 5 the total bit length will be equal to 8 1 5 1 1 Table 7 11 lists additional conditions that must be met to maintain synchronization Figure 7 8 CAN Bit Timing 1 CAN_BTIME1 Register intel CAN SERIAL COMMUNICATIONS CONTROLLER Table 7 11 Bit Timing Requirements for Synchronization Bit Time Segment Requirement Comments gt 3tq minimum tolerance with 1tq propagation delay allowance trsect 2 tsuw terop for single sample mode gt pnop 2tq for three sample mode gt 2tq minimum tolerance trsec2 5 em gt toyw if tsjw gt trsee2 sampling may occur after the bit time 7 4 4 Programming a Message Acceptance Filter The mask registers provide a method for developing an acceptance filtering strategy Without a filtering strategy a message object could accept an incoming message only if their identifiers were identical The mask registers allow a message object to ignore one or more bits of incoming message identifiers so it can accept a range of message identifiers The standard global mask register Figure 7 9 applies to messages with standard 11 bit mes sage identifiers while the extended global mask register Figure 7 10 applies to messages with extended 29 bit identifiers The message 15 mask register Figure 7 11 provides an additional filt
106. nput to the State Time Divide by two Circuit 8 MHz 250 ns 12 MHz 167 ns 16 MHz 125 ns 20 MHz 100 ns The following formulas calculate the frequency of PH1 and PH2 the duration of a state time and the duration of a clock period t PH1 in MHz PH2 State Time in us t lo Because the device can operate at many frequencies this manual defines time requirements such as instruction execution times in terms of state times rather than specific measurements Datasheets list AC characteristics in terms of clock periods t sometimes called Toso Figure 2 4 illustrates the timing relationships between the input frequency Fra the operating frequency f and the CLKOUT signal with each PLLEN pin configuration Table 2 3 details the relationships between the input frequency Fx 1 1 the PLLEN pin the operating frequency f the clock period t and state times intel ARCHITECTURAL OVERVIEW PLLEN 0 XTAL1 5 MHz i a A CLKOUT Ge ES excu PLLEN 1 XTAL1 5 MHz gt t 20ns DERIO NEIRA H Tica A3170 01 Figure 2 4 Effect of Clock Mode on CLKOUT Frequency Table 2 3 Relationships Between Input Frequency Clock Multiplier and State Times F Frequency PLLEN Multiplier Input mM to Geek State Time on XTAL1 the Divide by two Circuit Period 4 MHz 0 1 4 MHz 250 ns 500 ns 5 MHz 0 1 5 MHz 200 ns 400 ns 8 MHz 0 1 8 MHz 1
107. ns controller manages communications between multiple network nodes This integrated peripheral is similar to Intel s standalone 82527 CAN serial communications controller It supports both the standard and the extended message frames specified by CAN 2 0 protocol parts A and B developed by Robert Bosch GmbH This chapter describes the integrated CAN controller and explains how to configure it Consult Appendix A Signal Descriptions for detailed descriptions of the signals discussed in this chapter 7 1 CAN FUNCTIONAL OVERVIEW The integrated CAN controller transfers messages between network nodes according to the CAN protocol The CAN protocol uses a multiple master contention based bus configuration which is also called CSMA CR carrier sense multiple access with collision resolution Each CAN controller s input and output pins are connected to a two line CAN bus through which all com munication takes place Figure 7 1 Dashboard 196Cx device 196Cx device Transmission 196Cx device RXCAN CAN Bus EM Driver 2588 02 Figure 7 1 A System Using CAN Controllers 7 1 87C196CB SUPPLEMENT intel This bus configuration reduces point to point wiring requirements making the CAN controller well suited to automotive and factory automation applications In addition it relieves the CPU of much of the communications burden while providing a high level of data
108. obal mask register applies to those with extend ed 29 bit identifiers The CAN controller applies the appropriate global mask to each incoming message identifier and checks for an acceptance match in message objects 1 14 If no match ex ists it then applies the message 15 mask and checks for a match on message object 15 The mes sage 15 mask is ANDed with the global mask so any bit that is masked by the global mask is automatically masked for message 15 The CAN controller accepts an incoming data message if the message s identifier matches that of any enabled receive message object It accepts an incoming remote message request for data transmission if the message s identifier matches that of any enabled transmit message object The remote message s identifier is stored in the transmit message object overwriting any masked bits Table 7 5 shows an example 7 6 intel CAN SERIAL COMMUNICATIONS CONTROLLER Table 7 5 Effect of Masking on Message Identifiers Transmit message object ID 11000000000 Mask 0 don t care 1 must match 00000000011 Received remote message object ID 00111111100 Resulting message object ID 00111111100 7 3 3 Message Frames A message object is contained within a message frame that adds control and error detection bits to the content of the message object The frame for an extended message differs slightly from that for a standard message but they contain similar informati
109. object x control 1 CAN_MSGxCON1 register indicates whether a message object has been updated whether a message has been overwritten whether the CPU is updating the message and whether a transmission or reception is pending This register consists of four bit pairs the most significant bit of each pair is in true form and the least significant bit is in complement form This format allows software to set or clear any bit with a single write operation without affecting the remaining bits 7 0 MSGLST MSGLST CPUUPD CPUUPD 87C196CB RMTPND RMTPND TX TX REQ NEWDAT NEWDAT Bit Bit Function Number Mnemonic unco 3 2 MSGLST or Message Lost Receive CPUUPD For a receive message object the CAN controller sets this bit pair to indicate that it stored a new message while the NEWDAT bit pair was still set overwriting the previous message bit3 bit2 0 1 no overwrite occurred 1 0 a message was lost overwritten CPU Updating Transmit For a transmit message object software should set this bit pair to indicate that it is in the process of updating the message contents This prevents a remote frame from triggering a transmission that would contain invalid data bit3 bit 2 0 1 the message is valid 1 0 software is updating data 1 0 NEWDAT New Data This bit pair indicates whether a message object is valid configured and ready for transmission bit1 bit 2
110. ocation WSR Direct WSR Direct WSR Direct Address Address Address CAN_MSG11DATA2 1EB9H 75H 00F9H 3AH 00F9H 1DH 00B9H CAN_MSG12DATA2 1EC9H 76H 00E9H 3BH 00C9H 1DH 00C9H CAN MSG13DATA2 1ED9H 76H 00F9H 3BH 00D9H 1DH 00D9H CAN_MSG14DATA2 1EE9H 77H 00E9H 3BH 00E9H 1DH 00E9H CAN_MSG15DATA2 1EF9H 77H 00F9H 3BH 00F9H 1DH 00F9H CAN_MSG1DATA3 1E1AH 70H 00FAH 38H 00DAH 1CH 009AH CAN_MSG2DATA3 1E2AH 71H 00 38H 00 1CH 00AAH CAN MSGS3DATAS 1E3AH 71H 00FAH 38H OOFAH 1CH 00 CAN_MSG4DATA3 1E4AH 72H 00EAH 39H 00 1CH 00 CAN_MSG5DATA3 1E5AH 72H 00FAH 39H 00DAH 1CH 00DAH CAN MSG6DATAS3 1E6AH 73H 00EAH 39H 00EAH 1CH 00EAH CAN_MSG7DATA3 1E7AH 73H 00FAH 39H 00FAH 1CH OOFAH CAN_MSG8DATA3 1E8AH 74H 00EAH 3AH 00 1DH 008AH CAN_MSG9DATA3 1E9AH 74H 00FAH 3AH 00DAH 1DH 009AH CAN_MSG10DATA3 1EAAH 75H 00 00 1DH 00AAH CAN MSG11DATA3 1EBAH 75H OOFAH 3AH OOFAH 1DH 00 CAN_MSG12DATA3 1ECAH 76H 00EAH 3BH 00CAH 1DH 00CAH CAN MSG13DATA3 1EDAH 76H 00 3BH 00DAH 1DH 00DAH CAN MSG14DATA3 1EEAH 77H 00 00 1DH 00 CAN_MSG15DATA3 1EFAH 77H OOFAH 3BH OOFAH 1DH OOFAH CAN_MSG1DATA4 1E1BH 70H 00FBH 38H 00DBH 1CH 009BH CAN_MSG2DATA4 1E2BH 71H 00EBH 38H 00EBH 1CH 00ABH CAN_MSG3DATA4 1E3BH 71H 00FBH 38H 00FBH 1CH 00BBH CAN_MSG4DATA4 1E4BH 72H 00 39H 00CBH 1CH 00CBH CAN_MSG5DATA4 1E5BH 72H 00FBH 39H 00DBH 1CH 00DBH CAN_MSG6DATA4 1E6BH 73H 00 39H 00 1CH 00 CAN_MSG7DATA4 1E7BH 73H 00FBH 39H 00
111. on A data frame contains a message object with data to be transmitted a remote frame is a request for another node to transmit a data frame so it contains no data Figure 7 3 illustrates standard and extended message frames Table 7 6 and Table 7 7 describe their contents and summarize the minimum message lengths Actual message lengths may differ because the CAN controller adds bits during transmission see Error Detection and Management Logic on page 7 9 After each message frame an intermission field consisting of three recessive 1 bits separates messages This intermission may be followed by a bus idle time Standard Frame End of Frame Arbitration Control CRC Ack Field Field Data pieta Field F 11 bit 15 bit Identifier 0 8 Bytes CRC Extended Frame End of Frame Arbitration Control CRC Field Field Data Field Field F 11 bit 18 bit 15 bit Identifier Identifier 0 8 Bytes CRC A2599 01 Figure 7 3 CAN Message Frames 7 7 87C196CB SUPPLEMENT Table 7 6 Standard Message Frame intel Field Description Bit Count SOF Start of frame A dominant 0 bit marks the beginning of a message frame 1 11 bit message identifier Arbitration RTR Remote transmission request Dominant 0 for data frames recessive 1 12 for remote frames IDE Identifier extension bit always dominant 0 Control r0 Reserved bi
112. on the 100 pin 87C196CB has four additional address pins A23 20 91 ADDRESS PINS The 100 pin 87C196CB has 24 available address pins A23 16 and AD15 0 The A23 20 timings are identical to those of A19 16 During the CCB fetch the 100 pin 87C196CB strongly drives OFFH on A23 16 The 84 pin 87C196CB strongly drives OFH on A19 16 as does the 8XC196NT 9 2 BUS TIMING MODES The 87C196CB implements only modes 3 and 0 Table 9 1 and Figure 9 1 compare the timings of these two modes Figure 9 2 illustrates the CCB1 register which selects the mode Table 9 1 Modes 0 and 3 Timing Comparisons Timing Specifications Mode Teiu Tav Tavov Taan Taupz TaLov Mode 3 0 1t 3t 1t 1t 1t Mode 0 0 1t 5t 3t it 3t t These are ideal timing values for purposes of comparison only They do not include internal device delays Consult the datasheet for current device specifications 9 1 87C196CB SUPPLEMENT lt TaLov 1t Taupz 1t 1 I e Tavov 3t MODE 0 ALE RD 1 jee a g Tanoz t Data Address m AVDV 5t A0809 01 Figure 9 1 Modes 0 and 3 Timings 9 2 intel INTERFACING WITH EXTERNAL MEMORY CCR1 no direct access The chip configuration 1 CCR1 register enables the watchdog timer and selects the bus timing mode Two of its bits combine with three bits of CCRO to control wait states and bus width Another bit controls whether
113. onfiguration register Figure 7 12 specifies a message identifier type standard or extended transfer direction transmit or receive and data length in bytes CAN MSGxCFG Address 1Ex6H x 1 F x 1 15 87C196CB Reset State Unchanged Program the CAN message object x configuration MSGxCFQG register to specify a message object s data length transfer direction and identifier type 7 0 87C196CB DLC3 DLC2 DIR XTD Bit Bit Function Number Mnemonic 7 4 DLC3 0 Data Length Code Specify the number of data bytes this message object contains Valid values are 0 8 The CAN controller updates a receive message object s data length code after each reception to reflect the number of data bytes in the current message 3 DIR Direction Specify whether this message object is to be transmitted or is to receive a message object from a remote node 0 receive 1 transmit 2 XTD Extended Identifier Used Specify whether this message object s identification registers contain an extended 29 bit or a standard 11 bit identifier 0 standard identifier 1 extended identifier 1 0 Reserved for compatibility with future devices write zeros to these bits Figure 7 12 CAN Message Object x Configuration CAN MSGxCFG Register Set the XTD bit for a message object with an extended identifier clear it for a message w
114. ores it 7 0 NMI EXTINT CAN RI TI SSIO1 SSIOO CBF 7 0 Setting a bit enables the corresponding interrupt The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt FF203EH EXTINT EXTINT Pin FF203CH CAN CAN Peripheral FF203AH RI SIO Receive FF2038H TI SIO Transmit FF2036H SSIO1 SSIO 1 Transfer FF2034H 55100 SSIO 0 Transfer FF2032H CBF Slave Port Command Buffer Full FF2030H NMI is always enabled This nonfunctional mask bit exists for design symmetry with the INT_PEND1 register Always write zero to this bit Figure 4 1 Interrupt Mask 1 INT MASK1 Register INT_PEND1 Address 0012H B Reset State 00H When hardware detects a pending interrupt it sets the corresponding bit in the interrupt pending INT PEND or INT PEND1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit 7 0 NMI EXTINT CAN RI TI SSIO1 55100 CBF 7 0 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is cleared when processing transfers to the corresponding interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt FF203EH EXTINT EXTINT Pin FF203CH CAN CAN Peripheral FF203AH RI SIO Receive FF2038H TI SIO
115. ose memory standard interrupt state time or state successive approximation temperature coefficient temperature drift terminal based characteristic transfer function Glossary 10 intel Current flowing out of a device from Vcc Always a negative value Stack pointer Any of the three nonmaskable interrupts unimple mented opcode software trap or NMI A partition of memory used for storing the interrupt vectors PTS vectors chip configuration bytes and several reserved locations Any maskable interrupt that is assigned to the interrupt controller for processing by an interrupt service routine The basic time unit of the device the combined period of the two internal timing signals PH1 and 2 The internal clock generator produces PH1 and PH2 by halving the frequency of the signal on XTAL1 The rising edges of the active high and PH2 signals generate CLKOUT the output of the internal clock generator Because the device can operate at many frequencies this manual defines time requirements in terms of state times rather than in specific units of time An A D conversion method that uses a binary search to arrive at the best digital representation of an analog input Change in the stated variable for each degree Centigrade of temperature change The change in a specification due to a change in temperature Temperature drift can be calculated by using the temperature coefficient for the s
116. over the upper half of the system data bus Use BHE in conjunction with ADO to determine which memory byte is being transferred over the system bus BHE ADO Byte s Accessed 0 0 both bytes 0 1 high byte only 1 0 low byte only BHE is multiplexed with P5 5 and WRH t The chip configuration register 0 CCRO determines whether this pin functions as BHE or WRH CCRO 2 1 selects BHE CCRO 2 0 selects WRHA 87C196CB Supplement intel Table A 3 Signal Descriptions Continued Name Type Description BREQ O Bus Request This active low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle The device can assert BREQ at the same time as or after it asserts HLDAH Once it is asserted BREQ remains asserted until HOLD is removed You must enable the bus hold protocol before using this signal BREQ is multiplexed with P2 3 BUSWIDTH Bus Width The chip configuration register bits CCRO 1 and CCR1 2 along with the BUSWIDTH pin control the data bus width When both CCR bits are set the BUSWIDTH signal selects the external data bus width When only one CCR bit is set the bus width is fixed at either 16 or 8 bits and the BUSWIDTH signal has no effect CCRO 1 CCR1 2 BUSWIDTH 0 1 N A fixed 8 bit data bus 1 0 N A fixed 16 bit data bus 1 1 high 16 bit data bus 1 1 low 8 bit data bus BUSWIDTH is multiplexed with P5 7 CLKOUT O Clock Output Outp
117. pare 0 1 capture compare 8 9 timers 7CH EPA capture compare 0 7 7BH 3DH 1EH CAN messages 14 15 77H CAN messages 12 13 76H 1DH CAN messages 10 11 75H CAN messages 8 9 74H CAN messages 6 7 73H 39H CAN messages 4 5 bit timing 1 interrupts 72H ICH CAN messages 2 3 bit timing 0 71H 38H CAN message 1 control status mask 70H intel Table 3 6 Selecting a Window of the Upper Register File MEMORY PARTITIONS Register RAM WSR Value for 32 byte Window WSR Value for 64 byte Window WSR Value for 128 byte Window Locations 00E0 00FFH 00C0 00FFH 0080 00FFH 03E0 03FFH 2 03C0 03DFH 5EH 17H 03A0 03BFH 5DH 2EH 0380 039 5CH 0360 037FH 5BH 2DH 0340 035 SAH 0320 033FH 59H 0300 031FH 58H Eu 02 0 02 57 02C0 02DFH 56H 2BH 02A0 02BFH 55H 0280 029FH 54H 2AH 15H 0260 027FH 53H 0240 025FH 52H 29H 0220 023FH 51H 0200 021 50H 28H 14H 01E0 01FFH 4FH 01C0 01DFH 4EH 27H 01A0 01BFH 4DH 0180 019 4CH 26H 13H 0160 017FH 4BH 0140 015 4 25H 0120 013FH 49H 0100 011 48 24H 12H 87C196CB SUPPLEMENT 3 8 intel Table 3 7 Selecting a Window of Upper Register RAM MEMORY PARTITIONS Register RAM WSR Value for 32 byte Window WSR Value for 64 byte Window WSR Value for 128 byte Window
118. pecification An actual characteristic that has been translated and scaled to remove zero offset error and full scale error A terminal based characteristic resembles an actual characteristic with zero offset error and full scale error removed A graph of output code versus input voltage the characteristic of the A D converter intel transfer function errors UART Vcc rejection watchdog timer waveform generator WDT word WORD zero extension zero offset error GLOSSARY Errors inherent in an analog to digital conversion process quantizing error zero offset error full scale error differential nonlinearity and nonlinearity Errors that are hardware dependent rather than being inherent in the process itself include feedthrough repeatability channel to channel matching off isolation and rejection errors Universal asynchronous receiver and transmitter A part of the serial I O port The property of an A D converter that causes it to ignore reject changes in Vcc so that the actual characteristic is unaffected by those changes The effectiveness of Vcc rejection is measured by the ratio of the change in Vec to the change in the actual characteristic An internal timer that resets the device if software fails to respond before the timer overflows One of the 8XC196Mx peripherals that can be used to produce pulse width modulated PWM outputs The waveform generator is optimized for controll
119. r File Memory Addresses Device and Hex Address Range Description Addressing Modes CB NT 1DFF 1C00 Register RAM Indirect indexed or windowed direct 03FF O3FF i i i 0100 0100 Upper register file register RAM Indirect indexed or windowed direct OOFF OOFF 5 mex 001A 001A Lower register file register RAM Direct indirect or indexed 0019 0019 s 7 y A 0018 0018 Lower register file stack pointer Direct indirect or indexed 0017 0017 F S 0000 0000 Lower register file CPU SFRs Direct indirect or indexed 3 1 87C196CB SUPPLEMENT Table 3 2 87C196CB Memory Map intel Hex Lo e Address Description Addressing Modes FFFFFF Program memory After a device reset the first instruction fetch FF2080 is from FF2080H Indirect indexed extended FF207F y FF2000 Special purpose memory Indirect indexed extended 85 External device memory or I O connected to address data bus Indirect indexed extended FFO5FF Internal code and data RAM FF0400 mapped identically into pages FFH and 00H Indirect indexed extended iid External device memory or I O connected to address data bus Indirect indexed extended FFOOFF 2 FF0000 Reserved Indirect indexed extended FEFFFF 100 pin 87C196CB External device memory or I O 5 0 0000 84 pin 87C196CB _ Overlaid memory 1 In
120. r distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright Intel Corporation 1998 2004 Third party brands and names are the property of their respective owners intel CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1 1 MANUAL CONTEN IS treatise teer ne rte ce vA eis D la a rna Pav 1 1 1 2 RELATED DOGCUMENTS emet us ad i cando t 1 2 CHAPTER 2 ARCHITECTURAL OVERVIEW 2 1 DEVIGE FEATURES e de recta Piet tei er ic Ue eda i pt Da 2 1 2 2 BLOCK DIAGRAM iei db tret eee ea c He nein gin see Da a 2 2 2 3 INTERNAL TIMING cits ci Lire engen 2 2 CHAPTER 3 MEMORY PARTITIONS 3 1 MEMORY SPECIAL FUNCTION REGISTERS AND WINDOWING 3 1 CHAPTER 4 STANDARD AND PTS INTERRUPTS 4 1 INTERRUPT SOURCES VECTORS AND PRIORITIES 4 1 CHAPTER 5 PORTS 5 1 PORTO AND EPORT c e RU ot tet le 5 1 CHAPTER 6 ANALOG TO DIGITAL A D CONVERTER 6 1 ADDITIONAL A D INPUT CHANNELS nenea nennen nnne nene 6 1 CHAPTER 7 CAN SERIAL COMMUNICATIONS CONTROLLER 7 1 CAN FUNCTIONAL 0102042 2 10000000000000 nennen nennen enne nenne 7 1 7 2 CAN CONTROLLER SIGNALS AND
121. r the MSGVAL bit in the corresponding MSGxCONO register to prevent the CPU from accessing the message object change the identifier in MSGxID0 3 then set the MSGVAL bit to allow access 87C196CB 31 24 MSGxID3 ID4 IDS ID2 ID1 IDO 23 16 CAN MSGXxID2 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 15 8 CAN_MSGxID1 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 7 0 MSGxIDO ID28 1D27 ID26 ID25 1D24 1D23 ID22 ID21 MCN SA Function 31 27 ID4 0 Message Identifier 17 0 23 16 ID12 5 These bits hold the 18 least significant bits of an extended identifier If 12 8 ID17 13 you write an extended identifier to these bits but specify a standard identifier XTD 0 in the corresponding message object s configuration register CAN 5 the CPU clears these bits ID17 0 26 24 Reserved for compatibility with future devices write zeros to these bits 15 13 1D20 18 Message Identifier 28 18 7 0 ID28 21 These bits hold either an entire standard identifier or the 11 most significant bits of an extended identifier This register is the same as the arbitration register in the standalone 82527 CAN peripheral Figure 7 13 CAN Message Object x Identifier CAN_MSGxIDO 3 Register 7 22 intel CAN SERIAL COMMUNICATIONS CONTROLLER 7 5 3 Programming the Message Object Control Registers Each message object control register consists of four bit pairs
122. re are more entries in this column than there are pins Every signal is listed in this column Type Identifies the pin function listed in the Name column as an input 1 output O bidirectional I O power PWR or ground GND Note that all inputs except RESET are sampled inputs RESET is a level sensitive input During powerdown mode the powerdown circuitry uses EXTINT as a level sensitive input Description Briefly describes the function of the pin for the specific signal listed in the Name column Also lists the alternate fuction that are multiplexed with the signal if applicable Table A 3 Signal Descriptions Name Type Description A23 16 VO Address Lines 16 23 100 pin CB These address lines provide address bits 20 23 during the entire external memory cycle supporting extended addressing of the 16 Mbyte address space A23 20 are multiplexed with EPORT 7 0 A19 16 Address Lines 16 19 84 pin CB These address lines provide address bits 16 19 during the entire external memory cycle supporting extended addressing of the 1 Mbyte address space NOTE Internally there are 24 address bits however only 20 address lines A19 16 and AD15 0 are implemented as external pins on the 84 pin 87C196CB The internal address space is 16 Mbytes 000000 FFFFFFH and the external address space is 1 Mbyte 00000 FFFFFH The device resets to FF2080H in internal OTPROM or F2080H in external memory A19
123. rences of 11 consecutive recessive bits before participating in bus activities During this sequence the CAN controller writes a bit 0 error code to the LEC2 0 bits of the status register each time it receives a recessive bit Software can check the status register to determine whether the CAN bus is stuck in a dominant state Once the CAN controller is resynchronized with the CAN bus it clears the BUSOFF bit and starts transferring messages again 7 42 intel Special Operating Modes intel CHAPTER 8 SPECIAL OPERATING MODES 8 1 CLOCK CIRCUITRY The 87C196CB s idle powerdown and ONCE modes are the same as those of the 8XC196NT The only difference is in the way that the power saving modes disable the clock circuitry Figure 8 1 Disable PLL Powerdown Phase Phase locked Oscillator Disable Clock Input Powerdown Divide by two Circuit Disable Clocks Powerdown Disable Oscillator Powerdown Phase locked Loop Clock Multiplier PLLEN Peripheral Clocks PH1 PH2 Clock CLKOUT Generators CPU Clocks PH1 PH2 Disable Clocks Idle Powerdown A3168 01 Figure 8 1 Clock Circuitry 8 1 intel Interfacing with External Memory intel CHAPTER 9 INTERFACING WITH EXTERNAL MEMORY The 87C196CB s external memory interface is similar to that of the 8XC196NT However the 87C196CB supports only two of the bus timing modes modes 3 and 0 In additi
124. request placing an unnecessary burden on the CPU To prevent re dundant interrupt requests enable the error interrupt sources with the EIE bit and enable the re ceive and transmit interrupts in the individual message objects 7 31 87C196CB SUPPLEMENT intel 7 7 DETERMINING THE CAN CONTROLLER S INTERRUPT STATUS A successful reception or transmission or a change in the status register can cause the CAN con troller to generate an interrupt request The INT PENDI register see Table 7 2 on page 7 3 in dicates whether a CAN interrupt request is pending The CAN interrupt pending register Figure 7 19 indicates the source of the request either the status register or a specific message object Your interrupt service routine should read the CAN INT register to ensure that no additional in terrupts are pending before executing the return instruction CAN INT Address 1E5FH read only 87C196CB Reset State 00H The CAN interrupt pending CAN INT register indicates the source of the highest priority pending interrupt If a status change generated the interrupt request software can read the status register CAN STAT to determine whether the interrupt request was caused by an abnormal error rate a successful reception a successful transmission or a new error If an individual message object generated the interrupt request software can read the associated message object control 0 register CAN MSGxCONO The INT PND bit pair will be set
125. rogramming Circuit 10 4 MEMORY MAP FOR SERIAL PORT PROGRAMMING The 87C196CB s memory map Table 10 4 for serial port programming differs from that of the 8XC196NT The remaining information on serial port programming is correct for the 87C196CB 10 3 87C196CB SUPPLEMENT intel Table 10 4 Serial Port Programming Mode Memory Map Address Range Description Normal Operation Serial Port Programming Mode FF2000 FF7FFFH A000 FFFFH bank 0 1FF9H 00H mena ORCI FF8000 FFFFFFH 8000 FFFFH bank 1 1FF9H 80H External memory 4000 7FFFH Do not address 2400 3FFFH Test ROM and RISM 2000 23FFH The lower 24 Kbytes of OTPROM FF2000 FF7FFFH are remapped to A000 FFFFH and the upper 32 Kbytes FF8000 FFFFFFH are mapped to 8000 FFFFH A bank switching mecha nism differentiates between the two address ranges The most significant bit of an otherwise re served byte register location 1FF9H selects the bank Bank 0 is the lower 24 Kbytes and bank 1 is the upper 32 Kbytes To program the lower 24 Kbytes you must write to location 1FF9H To program the upper 32 Kbytes you must write 80H to location 1FF9H See page 10 4 for the required command sequences WARNING Writing any value other than 00H or 80H to location 1FF9H will cause the microcontroller to enter an unsupported test mode 10 4 1 Selecting Bank 0 FF2000 FF7FFFH Send the following RISM command sequence to select bank 0
126. s of the PTS control block The microcoded response to a single PTS interrupt request Any maskable interrupt that is assigned to the PTS for interrupt processing A microcoded response that enables the PTS to complete a specific task quickly These tasks include transferring a single byte or word transferring a block of bytes or words managing multiple A D conver sions and generating PWM outputs The entire microcoded response to multiple PTS interrupt requests The PTS routine is controlled by the contents of the PTS control block Glossary 7 87C196CB SUPPLEMENT PTS transfer PTS vector PWM quantizing error RALU repeatability error reserved memory resolution sample capacitor Glossary 8 intel The movement of a single byte or word from the source memory location to the destination memory location A location in special purpose memory that holds the starting address of a PTS control block Pulse width modulated outputs The 8XC196Mx devices have several options for producing PWM outputs the generic pulse width modulator modules the waveform generator and the EPA with or without the PTS The 8XC196MD also has a frequency generator that produces PWM outputs An unavoidable A D conversion error that results simply from the conversion of a continuous voltage to its integer digital representation Quantizing error is always 0 5 LSB and is the only error present in an ideal A D converter
127. sage Object 5 1EDF 1E4F Bit Timing Register 1 1EDO 1EDE Message Object 13 1E40 1E4E Message Object 4 1ECF 1E3F Bit Timing Register 0 1ECO 1ECE Message Object 12 1E30 1E3E Message Object 3 1EBF 1E2F 1EBO 1EBE Message Object 11 1E20 1E2E Message Object 2 1EAF 1E1F 1EAO 1EAE Message Object 10 1E10 1E1E Message Object 1 1E9F 1E0C 1E0F Message 15 Mask Register 1E90 1E9E Message Object 9 1 08 1 Extended Global Mask Register 1E8F 1E06 1E07 Standard Global Mask Register 1E80 1E8E Message Object 8 1E02 1E05 1E7F 1E01 Status Register 1E70 1E7E Message Object 7 1E00 Control Register The control register s CCE bit must be set to enable write access to the bit timing registers 7 3 2 Message Objects The CAN controller includes 15 message objects each of which occupies 15 bytes of RAM Ta ble 7 4 Message objects 1 14 can be configured to either transmit or receive messages while message object 15 can only receive messages Message objects 1 14 have only a single buffer so if a second message is received before the CPU reads the first the first message is overwritten Message object 15 has two alternating buffers so it can receive a second message while the first is being processed However if a third message is received while the CPU is reading the first the second message is overwritten 2d a 87C196CB SUPPLEMENT intel Table 7 4 Message Object Structure
128. ssage has been overwritten whether software is updating the message and whether a transfer is pending CAN_MSGxDATAO 1Ey7H Message Object x Data 0 7 CAN MSCADATA 1Ey8H The data registers contain data to be transmitted or data received CAN_MSGxDATA2 1Ey9H CAN MSGxDATA3 1EyAH Do not use unused data bytes as scratch pad memory the CAN CAN MSGxDATA4 1EyBH controller writes random values to these registers during MSGxDATAS5 1EyCH Operation MSGXxDATA6 1EyDH CAN MSGXxDATA7 1EyEH MSGxIDO 1Ey2H Message Object x Identification 0 3 MSGXxID1 1Ey3H write the message object s ID to this register This register is the MSGxID2 1Ey4H same as the arbitration register of the 82527 MSGXxID3 1Ey5H CAN MSK15 1 1E0DH Message 15 Mask 1EOEH 1E0FH Program this register to mask don t care specific message identifier bits for message 15 in addition to those bits masked by a global mask The message 15 mask is ANDed with the standard or extended global mask so any don t care bits defined in a global mask are also don t care bits for message 15 CAN SGMSK 1E06H 1E07H Standard Global Mask Program this register to mask don t care specific message identifier bits for standard message objects CAN STAT 1E01H Status This register reflects the current status of the CAN controller INT MASK1 0013H Interrupt Mask 1 The CAN bit in this register enables and disables the CAN
129. sult in a conversion without zero offset full scale or linearity errors Quantizing error is the only error seen in an ideal A D converter Current leakage from an input pin to power or ground The effective series resistance from an analog input pin to the sample capacitor of an A D converter Any member of the set consisting of the positive and negative whole numbers and zero A 16 bit signed variable with values from 2 5 through 2 5 1 The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide Also called the programmable interrupt controller PIC The total delay between the time that an interrupt is generated not acknowledged and the time that the device begins executing the interrupt service routine or PTS routine A software routine that you provide to service a standard interrupt See also PTS routine A location in special purpose memory that holds the starting address of an interrupt service routine intel ISR linearity errors LONG INTEGER LSB maskable interrupts monotonic MSB n channel FET n type material no missing codes GLOSSARY See interrupt service routine See differential nonlinearity and nonlinearity A 32 bit signed variable with values from through 49 127 1 Least significant bit of a byte or least significant byte of a word 2 In an A D converter the reference voltage divided by 2 where
130. t always dominant 0 6 DLC Data length code A 4 bit code indicating the number of data bytes 0 8 Data Data 1 to 8 bytes for data frames 0 bytes for remote frames 0 64 CRC CRC code A 15 bit CRC code plus a recessive 1 delimiter bit 16 Ack Acknowledgment A dominant 0 bit sent by nodes receiving the frame plus a 2 recessive 1 delimiter bit End of frame 7 recessive 1 bits mark the end of a frame 7 Minimum standard message frame length bits 44 108 Table 7 7 Extended Message Frame Field Description Bit Count SOF Start of frame A dominant 0 bit marks the beginning of a message frame 1 11 bits of the 29 bit message identifier SRR Substitute remote transmission request always recessive 1 Arbitration IDE Identifier extension bit always recessive 1 32 18 bits of the 29 bit message identifier RTR Remote transmission request always recessive 1 r0 Reserved bit always dominant 0 Control r1 Reserved bit always dominant 0 6 DLC Data length code A 4 bit code indicating the number of data bytes 0 8 Data Data 1 to 8 bytes for data frames O bytes for remote frames 0 64 CRC CRC code A 15 bit CRC code plus a recessive 1 delimiter bit 16 Ack Acknowledgment A dominant 0 bit sent by nodes receiving the frame plus a 2 recessive 1 delimiter bit End of frame 7 recessive 1 bits mark the end of a frame 7 Minimum extended message frame length bits 64 128 intel CAN SERIA
131. ta Each message object can have from zero to eight bytes of data For transmit message objects write the message data to the data registers Figure 7 16 For receive message objects the CAN controller stores the received data in these registers The CAN controller writes random values to any unused data bytes during operation so you should not use unused data bytes as scratch pad memory 7 23 87C196CB SUPPLEMENT intel CAN MSGxCONO Address 1Ex0H x 1 F x 1 15 87C196CB Reset State Unchanged Program the CAN message object x control 0 CAN MSGxCONO register to indicate whether the message object is ready to transmit and to control whether a successful transmission or reception generates an interrupt The least significant bit pair indicates whether an interrupt is pending This register consists of four bit pairs the most significant bit of each pair is in true form and the least significant bit is in complement form This format allows software to set or clear any bit with a single write operation without affecting the remaining bits 7 0 87C196CB MSGVAL MSGVAL TXIE TXIE RXIE RXIE INT PND INT PND Bit Bit Function Number Mnemonic 7 6 MSGVAL Message Object Valid Set this bit pair to indicate that a message object is valid configured and ready for transmission or reception bit7 bit6 0 1 not ready 1 0 message object is valid The CAN peripheral will access a mess
132. tectural Overview compares the features of the 87C196CB with those of the 8XC196NT and describes the 87C196CB s internal clock circuitry Chapter 3 Memory Partitions describes the addressable memory space of the 84 pin and 100 pin 87C196CB lists the peripheral special function registers SFRs and provides tables of WSR values for windowing higher memory into the lower register file for direct access Chapter 4 Standard and PTS Interrupts describes the additional interrupts for the CAN controller area network peripheral and the SFRs that support those interrupts Chapter 5 I O Ports describes the port 0 and EPORT differences for the 100 pin 87C196CB Both port O and the EPORT are implemented as eight bit ports on the 100 pin 87C196CB but as four bit ports like the 8XC196NT on the 84 pin 87C196CB Chapter 6 Analog to digital A D Converter illustrates the SFRs that are affected by the implementation of port 0 as an eight bit port Chapter 7 CAN Serial Communications Controller describes the 87C196CB s integrat ed CAN controller and explains how to configure it This integrated peripheral is similar to Intel s standalone 82527 CAN serial communications controller supporting both the standard and ex tended message frames specified by the CAN 2 0 protocol parts A and B Chapter 8 Special Operating Modes illustrates the clock control circuitry of the 87C196CB 87C196CB SUPPLEMENT int
133. ter A register or storage location that forms the result of an arithmetic or logical operation A graph of output code versus input voltage of an actual A D converter An actual characteristic may vary with temperature supply voltage and frequency conditions Analog to digital converter Arithmetic logic unit The part of the RALU that processes arithmetic and logical operations The act of making a signal active enabled The polarity high or low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high A decrease in amplitude voltage decay A binary digit A single bit operand that can take on the Boolean values true and false The property of a multiplexer which guarantees that a previously selected channel is deselected before a new channel is selected That is break before make ensures that the A D converter will not short inputs together Any 8 bit unit of data An unsigned 8 bit variable with values from 0 through 28 1 Glossary 1 87C196CB SUPPLEMENT CAN CCBs CCRs channel to channel matching error characteristic clear code code center code transition Glossary 2 intel Controller area network The 87C196CB s integrated networking peripheral similar to Intel s standalone 82527 CAN serial communications controller
134. to prevent transfers to and from the bus to enable and disable CAN interrupts and to control write access to the bit timing registers CAN_EGMSK 1E08H 1E09H Extended Global Mask 1EOAH 1E0BH Program this register to mask don t care specific message identifier bits for extended message objects CAN INT 1E5FH CAN Interrupt Pending This read only register indicates the source of the highest priority pending interrupt CAN_MSGxCFG 1Ey6H Message Object x Configuration Program this register to specify a message object s data length transfer direction and identifier type CAN_MSGxCONO 1Ey0H Message Object x Control 0 Program this register to enable or disable the message object s successful transmission TX and reception RX interrupts Read this register to determine whether a message object is ready to transmit and whether an interrupt is pending CCE bit in must be set to enable write access to the bit timing registers In register names x 1 15 in addresses 1 87C196CB SUPPLEMENT intel Table 7 2 Conirol and Status Registers Continued Register Register Address Description CAN_MSGxCON1 1Ey1H Message Object x Control 1 Program this register to indicate that a message is ready to transmit or to initiate a transmission Read this register to determine whether the message object contains new data whether a me
135. tq Sample Transmit A2602 01 Figure 7 5 A Bit Time as Implemented in the CAN Controller Table 7 9 CAN Controller Bit Time Segments Symbol Definition ses This time segment is equivalent to SYNC_SEG in the CAN protocol Its length is one time E quantum trsect This time segment is equivalent to the sum of PROP SEG and PHASE SEG in the CAN protocol Its length is specified by the TSEG1 field in bit timing register 1 To allow for resyn chronization the sample point can be moved trsegs can be shortened and the other lengthened by 1 to 4 time quanta depending on the programmed value of the SJW field in bit timing register O The CAN controller samples the bus once or three times depending on the value of the sampling mode SPL bit in bit timing register 0 In three sample mode the hardware lengthens trsec by 2 time quanta to allow time for the additional two bus samples In this case the sample point shown in Figure 7 5 is the time of the third sample the first and second samples occur 2 and 1 time quanta earlier respectively 2 This time segment is equivalent to PHASE_SEG2 in the CAN protocol Its length is specified by the TSEG2 field in bit timing register 1 To allow for resynchronization the sample point be moved trsga OF trseez be shortened and the other lengthened by 1 to 4 time quanta depending on the programmed value of the SJW field in bit timing regist
136. tween multiple net work nodes This integrated peripheral is similar to Intel s standalone 82527 CAN serial commu nications controller supporting both the standard and extended message frames specified by the CAN 2 0 protocol parts A and B Interrupt Controller Clock and Code Data PTS Power Mgmt RAM A3179 01 Figure 2 1 87C196CB Block Diagram 2 3 INTERNAL TIMING The 87C196CB s clock circuitry Figure 2 2 implements phase locked loop and clock multiplier circuitry which can substantially increase the CPU clock rate while using a lower frequency in put clock The clock circuitry accepts an input clock signal on XTAL1 provided by an external crystal or oscillator Depending on the value of the PLLEN pin this frequency is routed either through the phase locked loop and multiplier or directly to the divide by two circuit The multi plier circuitry can quadruple the input frequency Fyra 1 before the frequency f reaches the di vide by two circuitry The clock generators accept the divided input frequency f 2 from the divide by two circuit and produce two nonoverlapping internal timing signals PH1 and PH2 These signals are active when high NOTE This manual uses lowercase f to represent the internal clock frequency For the 87C196CB f is equal to either Or AF depending on the clock multiplier mode which is controlled by the PLLEN input pin 2 2 intel ARCHITECTURA
137. undefined at power up Interrupt 1E5F 00H Message Object x 1Ex0 1ExE unchanged undefined at power up 7 9 2 Software Initialization The software initialization state allows software to configure the CAN controller s RAM without risk of messages being received or transmitted during this time Setting the INIT bit in the control register causes the CAN controller to enter the software initialization state Either a hardware re set or a software write can set the INIT bit While INIT is set all message transfers to and from the CAN controller are stopped and the error counters and bit timing registers are unchanged Your software should clear the INIT bit to cause the CAN controller to exit the software initial ization state At this time the CAN controller synchronizes itself to the CAN bus by waiting for a bus idle state 11 consecutive recessive bits before participating in bus activities 7 9 3 Bus off State If an error counter reaches 256 the CAN controller isolates itself from the CAN bus sets the BUSOFF bit in the status register and sets the INIT bit in the control register While INIT is set all message transfers to and from the CAN controller are stopped the error counters and bit tim ing registers are unchanged Software must clear the INIT bit to initiate the bus off recovery se quence 7 41 87C196CB SUPPLEMENT intel The CAN controller synchronizes itself to the CAN bus by waiting for 128 bus idle states 128 occur
138. upt controller The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide Also called simply the interrupt controller intel prioritized interrupt program memory protected instruction PSW PTS PTSCB PTS control block PTS cycle PTS interrupt PTS mode PTS routine GLOSSARY Any maskable interrupt or nonmaskable NMI Two of the nonmaskable interrupts unimplemented opcode and software trap are not prioritized they vector directly to the interrupt service routine when executed A partition of memory where instructions can be stored for fetching and execution An instruction that prevents an interrupt from being acknowledged until after the next instruction executes The protected instructions are DI EI DPTS EPTS POPA POPF PUSHA and PUSHF Processor status word The high byte of the PSW is the status byte which contains one bit that globally enables or disables servicing of all maskable interrupts one bit that enables or disables the PTS and six Boolean flags that reflect the state of the current program The low byte of the PSW is the INT_MASK register A push or pop instruction saves or restores both bytes PSW INT MASK Peripheral transaction server The microcoded hardware interrupt processor See PTS control block A block of data required for each PTS interrupt The microcode executes the proper PTS routine based on the content
139. ure analysis of the device is impossible 10 3 MEMORY MAP AND CIRCUIT FOR AUTO PROGRAMMING Because the 87C196CB has an additional 24 Kbytes of OTPROM its auto programming memory map Table 10 3 and circuit Figure 10 1 differ from those of the 8XC196NT Table 10 3 Auto Programming Memory Map Gut rom Internal Address Using Circuit m seisoa EE A15 0 4014 00014H Programming pulse width PPW LSB 4015H N A 00015H Programming pulse width PPW MSB 4020 402FH FF2020 FF202FH 00020 0002FH Security key for verification 4000 7FFFH FF2000 FF5FFFH 04000 07FFFH First 16 Kbytes of code and data 4000 7FFFH FF6000 FF9FFFH 08000 0BFFFH Second 16 Kbytes of code and data 4000 7FFFH FFA000 FFDFFFH 0 000 Third 16 Kbytes of code and data 4000 5FFFH FFE000 FFFFFFH 10000 11FFFH Last 8 Kbytes of code and data 10 2 intel PROGRAMMING THE NONVOLATILE MEMORY Voc 20 pF 20 pF I 100 kQ XTAL XTAL2 RESET oo 5 0V eT Voc 74HC14 1 0uF READY P5 6 104F 1 NMI BUSWIDTH P5 7 4 1 ES i Voc RD P5 3 VREF 7 P0 7 El PMODE 3 0 6 PMODE 2 P1 2 AlS P0 5 PMODE 1 AD13 8 A13 8 P0 4 Voc 0 ANGND 270k He CEE Pf DU 7415373 74HC14 5 ON Programming V 00 270kQ lt P2 0 PVER 74HC14 ON Error 87C196CB A3228 01 Figure 10 1 Auto P
140. ut of the internal clock generator The CLKOUT frequency is Ye the operating frequency f CLKOUT has a 50 duty cycle CLKOUT is multiplexed with P2 7 and PACT COMP1 0 O Event Processor Array EPA Compare Pins These signals are the output of the EPA compare only channels These pins are multiplexed with other signals and may be configured as standard I O COMP1 0 are multiplexed as follows COMPO P6 0 EPA8 and COMP1 P6 1 EPA9 CPVER O Cumulative Program Verification During slave programming a high signal indicates that all locations programmed correctly while a low signal indicates that an error occurred during one of the programming operations CPVER is multiplexed with P2 6 and HLDA SIGNAL DESCRIPTIONS Table A 3 Signal Descriptions Continued Name Type Description EA External Access This input determines whether memory accesses to special purpose and program memory partitions FF2000 FF9FFFH are directed to internal or external memory These accesses are directed to internal memory if EA is held high and to external memory if EA is held low For an access to any other memory location the value of EA is irrelevant EA also controls entry into programming mode If EA is at Vpp voltage typically 12 5 V on the rising edge of RESET the device enters programming mode NOTE Systems with EA tied inactive have idle time between external bus cycles When the address data bus is idle you can
141. wo adjacent codes intel code width crosstalk DC input leakage deassert differential nonlinearity doping double word DOUBLE WORD EPA EPROM ESD feedthrough GLOSSARY The voltage change corresponding to the difference between two adjacent code transitions Code width deviations cause differential nonlinearity and nonlin earity errors See off isolation Leakage current from an analog input pin to ground The act of making a signal inactive disabled The polarity high or low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To deassert RD is to drive it high to deassert ALE is to drive it low The difference between the actual code width and the ideal one LSB code width of the terminal based characteristic of an A D converter It provides a measure of how much the input voltage may have changed in order to produce a one count change in the conversion result Differential nonlinearity is a measure of local code width error nonlinearity is a measure of overall code transition error The process of introducing a periodic table Group III or Group V element into a Group IV element e g silicon A Group III impurity e g indium or gallium results in a p type material A Group V impurity e g arsenic or antimony results in an n type material Any 32 bit unit of data An unsigned 32 bit variable with values from
142. xed as follows P1 0 EPAO P1 1 EPA1 P1 2 EPA2 1 P1 4 T1CLK P1 5 T1DIR P1 6 T2CLK and P1 7 T2DIR P2 7 0 P3 7 0 P4 7 0 Vo VO I O Port 2 This is a standard bidirectional port that is multiplexed with individually selectable special function signals P2 6 is multiplexed with the ONCE function If this pin is held low during reset the device will enter ONCE mode so exercise caution if you use this pin for input If you choose to configure this pin as an input always hold it high during reset and ensure that your system meets the V specification see datasheet to prevent inadvertent entry into a test mode Port 2 is multiplexed as follows P2 0 TXD PVER P2 1 RXD PALE P2 2 EXTINT PROG P2 3 BREQ P2 4 INTOUT AINC P2 5 HOLD P2 6 HLDA ONCE CPVER P2 7 CLKOUT PACT Port 3 This is an 8 bit bidirectional memory mapped I O port with open drain outputs The pins are shared with the multiplexed address data bus which has comple mentary drivers P3 7 0 are multiplexed with AD7 0 SLP7 0 and PBUS 7 0 Port 4 This is an 8 bit bidirectional memory mapped I O port with open drain outputs The pins are shared with the multiplexed address data bus which has comple mentary drivers P4 7 0 are multiplexed with AD15 8 and PBUS15 8 P5 7 0 VO Port 5 This is an 8 bit bidirectional memory mapped I O port P5 4 is multiplexed with a special test mode entry function I

Intel 8XC196NT Computer Hardware User Manual

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