Connect Tech PCI-104 Network Card User Manual
Contents
1. MTGTXNO_114 Output c MTGTXP0_114 Output c 3 3V Power a 3 3V Power a 3 3V Power a 3 3V Power a MTGRXN1_114 Input c MTGRXP1_114 Input c MTGTXN1_114 Output c Notes MTGTXP1_114 Output a Pins have a different function from Revision B b The Rocket I O GTP are organized into tiles where each tile has two transceivers and shares a common PLL In this design tiles 112 and 114 are used c c Tile 112 has AC coupling capacitors on the TX pairs validated at PCI Express data rates 2 5 Gbps d Tile 114 has AC coupling capacitors on both the RX and TX pairs validated at SATA data rates 1 5 Gbps e HSS_USER_IO are flexible LVCMOS side band signals WARNING If connecting two FreeForm PCI 104 s together using the Rocket I O interface in a cross over fashion care must be taken Ensure that only cables provided by Connect Tech are used Cables ordered directly from Samtec or a third party could result in damage to the cable and or the FreeForm PCI 104 board itself Revision 0 02 12 Connect Tech FreeForm PCI 104 User Manual Top View High Speed Serial P4 RS 485 Headers P5 P6 Table 7 RS 485 Port 1 Pinout P5 Direction WO ONS DN BR Wl fe o Table 8 RS 485 Port 2 Pinout P6 Direction P62. Input Output GPIOP 23 Input Output GND Power GND Power GND Power GND Power GPION 8 Input Output GPION 24 Input Output GPIOP 8 Input Output GPIOP 24 Input Output GPION 9 Input Output GPION 25 Input Output GPIOP 9 Input Output GPIOP 25 Input Output GPION 10 Input Output GPION 26 Input Output GPIOP 10 Input Output GPIOP 26 Input Output GPION 11 Input Output GPION 27 Input Output GPIOP 11 Input Output GPIOP 27 Input Output GND Power GND Power GND Power GND Power GPION 12 Input Output GPION 28 Input Output GPIOP 12 Input Output GPIOP 28 Input Output GPION 13 Input Output GPION 29 Input Output GPIOP 13 Input Output GPIOP 29 Input Output GPION 14 Input Output GPION 30 Input Output GPIOP 14 Input Output GPIOP 30 Input Output GPION 15 Input Output GPION 31 Input Output GPIOP 15 Input Output GPIOPG1 Input Output GND Power GND Power Revision 0 02 GND Power GND Power 14 Connect Tech FreeForm PCI 104 User Manual Side View External Power Connector P8 The external connector provides 5V to the power regulation circuitry The external power connector should only be used when the Fr
3. MTGRXP1_114 26 MTGTXN1_114 26 MTGTXN1_114 28 MTGTXP1_114 28 MTGTXP1_114 RS 485 Headers P5 The orientation of the connector has changed The pinout remains the same Revision B 10 750 Revision 0 02 Revision C P5 485 Port 0 10 38 Connect Tech FreeForm PCI 104 User Manual External Power Connector P8 The connector no longer enables 3 3V regulation it is always enabled Revision B Revision C 1 5V 1 5V 2 3 3 enable connect to 5V 3 GND 3 GND 4 VIO connect to 5V 4 VIO connect to 5V Specifications Revision B Revision C Power Requirements 3 3V DC and 5V DC in PCI 104 stack 5V DC in PCI 104 stack 5V DC stand alone Current requirements are configuration dependant 5V DC stand alone Revision 0 02 39
4. bit generated at end FPGA implementation using ISE o PLX 9056 boundary scan definition file bdsl o Ethernet PHY boundary scan definition file To program the SPI flash a hex file must be generated mcs then written to the flash To generate the hex file the following is required FPGA Bitstream Setting PROM file format to MCS important since bits are swapped Setting SPI PROM density to 16M Setting SPI Flash type to M25P16 Oo Oo 0 For a complete procedure refer to Appendix A Revision 0 02 19 Connect Tech FreeForm PCI 104 User Manual Power and Thermal Considerations The FreeForm PCI 104 s Virtex 5 FPGA is a versatile flexible device with many built in features like termination PLLs and high speed gigabit transceivers The drawback of these on chip features is that they consume a lot of power and hence dissipate a lot of heat As a result Connect Tech is recommending the installation of a heatsink included with the product see section Heat Sink Installation As well the FPGA designer must perform power analysis on their design to determine that they are not stressing the Virtex 5 component i e exceeding the junction temperature Power analysis can be performed using the Xpower Analyzer part of the ISE design suite and the XPE spreadsheets Xilinx Power Estimator Spreadsheets http www xilinx com products design_resources power_central Reference Design FPGA power analysis Power analysis
5. 485 Port 1 4 OIII Mm BR JW JR a Revision 0 02 Connect Tech FreeForm PCI 104 User Manual GPIO Header P7 When in differential mode the GPIO header positive P and negative N signals are adjacent on a standard ribbon cable Note that the GPIO voltage level is set via hardware O O GPION 0 FCG001 L12 populated enabling 2 5V I O including LVDS FCG002 L13 populated enabling 3 3V I O Table 9 GPIO Header Pinout Input Output GPION 16 Input Output GPIOP 0 Input Output GPIOP 16 Input Output GPION 1 Input Output GPION 17 Input Output GPIOP 1 Input Output GPIOP 17 Input Output GPION 2 Input Output GPION 18 Input Output GPIOP 2 Input Output GPIOP 18 Input Output GPION 3 Input Output GPION 19 Input Output GPIOP 3 Input Output GPIOP 19 Input Output GND Power GND Power GND Power GND Power GPION 4 Input Output GPION 20 Input Output GPIOP 4 Input Output GPIOP 20 Input Output ra USES SES GPION 5 Input Output GPION 21 Input Output GPIOP 5 Input Output GPIOP 21 Input Output GPION 6 Input Output GPION 22 Input Output GPIOP 6 Input Output GPIOP 22 Input Output GPION 7 Input Output GPION 23 Input Output GPIOP 7
6. Physical memory allocation for bus mastering or DMA purposes Interrupt handling EEPROM read write by address oO000 0 The SDK is available for download from http www plxtech com products sdk In order to download the SDK you will need to register with PLX Reference Design amp Application Examples The FreeForm PCI 104 ships with a CD containing o Documentation and manuals o FPGA VHDL reference design o Software program examples The reference design and example programs help users quickly develop custom hardware and software applications Refer to the CD for installation instructions The latest reference design is always available from http devel connecttech com If a username and password have not already been provided please contact Connect Tech Support via email support connecttech com Revision 0 02 18 Connect Tech FreeForm PCI 104 User Manual FPGA Configuration The Virtex 5 FPGA can be configured via two methods o JTAG programming chain using P2 o SPI Flash read on power up by FPGA The configuration flash can be programmed loaded through three methods o JTAG programming chain through FPGA using P2 Direct with cable using P3 o Indirect programming through FPGA only possible after configuration is complete refer to reference design for more details O To configure the FPGA via the JTAG boundary scan programming chain three items are required o FPGA bitstream
7. If you experience difficulties after reading the manual and or using the product contact the Connect Tech reseller from which you purchased the product In most cases the reseller can help you with product installation and difficulties In the event that the reseller is unable to resolve your problem our highly qualified support staff can assist you Our support section is available 24 hours a day seven days a week on our website at www connecttech com support support asp See the contact information section below for more information on how to contact us directly Our technical support is always free Not listing all possible trademarks or copyright acknowledgments does not constitute a lack of acknowledgment to the rightful owners of the trademarks and copyrights mentioned in this document Contact Information We offer three ways for you to contact us Telephone Facsimile Technical Support representatives are ready to answer your call Monday through Friday from 8 30 a m to 5 00 p m Eastern Standard Time Our numbers for calls are Telephone 800 426 8979 North America only Telephone 519 836 1291 Live assistance available 8 30 a m to 5 00 p m EST Monday to Friday Facsimile 519 836 4878 on line 24 hours Email Internet You may contact us through the Internet Our email and URL addresses are sales connecttech com support connecttech com www connecttech com Mail Courier You may contact us by letter
8. and our mailing address for correspondence is Connect Tech Inc 42 Arrow Road Guelph Ontario Canada NIK 1S6 Revision 0 02 3 Connect Tech FreeForm PCI 104 User Manual Table of Contents Limited Lifetime War dle rats 2 Copyright o NT 2 Trademark Acknowledgment 0 ceeccecssecesececssecesneecaeceeneecsaeceeeecsaeceaeecsaeceaeecaeeeeaeecsaeeenees 2 Customer Support Overview 0 eee ceecescesecesecesecssecseecaeeeseeeeeeesescensecsecsaecsaecsaesseeeaeseneseeeennees 3 Contact Information AA este sch sete uscaeseevecochenscbepesnscssebuasssadesnecboononstne 3 Table of Contents geseet ENEE oti e o EEE O ei eE E oe sheesh ies datan tendons 4 Listof Tables c3 ccccastccscasheciiestieescescaoute eeina ea ee aoa E ah o a Eno E VE ee EEE EAEE 5 ListiOf Figures cocteles dci ai EA EE ae iii due 5 rie el ee EE 6 Product Features emanaciones ENEE SEENEN ENEE 6 About this manual ENEE EES EEN ENEE delos daras docena desidia 6 NANO cs ciius Ee bE SOEKE aeS K ENEE eE o ESEK CA Eo eere eaei 7 GI E E E E E E 9 Hardware DESCUIDO raros E E T E A E a 10 Jumpers and SwitChes aiii e 10 Slot Selection RS W 1 cs tie aee eege Eeer 10 FPGA Configuration Settings UI 10 Connector Pinot i n ita 11 PCETELO4 Header Plastilina 11 JTAG Programming Header D 11 SPI Flash Programming Header P3 oooooocccocccoconoconocononconnconoconocnoconoconorononaninnnonos 11 Eligh speed Serial Paita eiii 12 RS 483 Headers P5 PO EE 13 GPIO Hea
9. degr mbient degree tion Temp de Revision 0 02 33 Connect Tech FreeForm PCI 104 User Manual Scenario 2 No Heatsink 250 LFM Total Available Utilization Total Power Junction Temp Value Range Revision 0 02 34 Connect Tech FreeForm PCI 104 User Manual Scenario 3 No heatsink 0 LEM Used Total Available Ultilization Total Power Junction Temp Revision 0 02 35 Connect Tech FreeForm PCI 104 User Manual Appendix C Hardware Changes from Revision B This appendix lists the changes between hardware revision B and hardware revision C The following is a summary of changes PCB requires only 5V over PCI 104 it previously required 3 3V and 5V A dedicated local bus oscillator was added to generate 50Mhz A clock is no longer forwarded from FPGA to the PLX PCI 9056 The DDR2 FPGA pinout has been changed to increase timing margins The pinout of connector P4 high speed serial has changed The sideband signals have been relocated and 3 3V has been added The orientation of connector P5 RS 485 port 0 has rotated 180 degrees The Location of P8 external power connector has changed The 3 3V enable signal has also been removed Revision 0 02 36 Connect Tech FreeForm PCI 104 User Manual Reference Design The top level reference design contains a generic parameter which will correctly configure the FPGA for Revision B or Revision C A separate constraint file UCF is created for Revisi
10. was performed on the FCGOO1 when configured with the reference design The Virtex 5 XPE spreadsheet was used to determine an effective junction to ambient thermal resistance Oya effective The following parameters are entered into the spreadsheet to determine Dua eftective Part XCSVLX30T Package FF665 Grade Industrial Process Typical Speed Grade 1 Stepping Stepping 1 Thermal Information Ambient Temp C 50 Airflow LFM 250 Heat Sink Custom Custom OSA C W 8 Board Selection Small 4 x4 of Board Layers 12 to 15 Osa is the surface to ambient temperature for a heatsink with dimensions 27 mm x 27 mm x 6 4 mm and 250 LFM airflow The Osa improves decreases with a taller heatsink Three scenarios were developed and the XPE parameters Airflow and Custom OSA were varied The OjA effective Was entered into the Xpower Analyzer yielding a Juction Temperature 50 C anda maximum ambient temperature The following table summarizes the scenarios and the results For complete details of the scenarios see Appendix B Heatsink attached 250 LEM No Heatsink 250 LFM No heatsink 0 LFM Calculation details Tiunction Tambient PrrGA Oy effective 50 C 3 53W e 4 9 C IW 67 297 C EE T jonction max Ml PrrGA ES Dia effective 100 C T 3 53W S 4 9 SC W 82 7 C Note Tjunction_absolute_max 125 C is not
11. 16 3 KB L Desktop My Documents My Computer My Network File name y bsd y Places Files of type Boundary Scan Files bsd y Cancel Y Revision 0 02 Connect Tech FreeForm PCI 104 User Manual TDI xeSvix30t pei9056ba_r1 unknown init bit pci9056ba bsd file TDO 7 Again a prompt will ask for device number three National PHY Browse to the bsdl folder and select DP83849IVS bsd The device will be added to the JTAG chain TDI xc5wIx30t pci9056ba_r1 dp83849i init bit pcigs056ba bsd dp83849ivs bsd TDO 8 To test stream integrity right click on the FPGA and select Get Device ID The console will report IDCODE 82a6e093 TDI Program verify Get D D Get Device Signature Usercode TDO Add SPI Flash Add BPI Flash Assign New Configuration File f f BATCH CMD Readldcode p 1 Maximum TCK operating frequency for this device chain 10000000 Validating chain Boundary scan chain validated successfully 0 Device Temperature Current Reading 273 00 C 0 VCCINT Supply Current Reading 0 000 Y O VCCAUX Supply Current Reading 0 000 Y 11 IDCODE is 10000010101001101110000010010011 11 IDCODE is S2a6e093 in hex Li AU Manufacturer s ID Xilinx xc5vlx30t Version 8 Revision 0 02 24 Connect Tech FreeForm PCI 104 User Manual Programming the FPGA 1 Right click on device number one Virtex 5 FPG
12. A and select program The following diagram will appear Note that verification will only work if an msk file has been created g Programming Properties ogramming Properties Advanced PROM Programming Properties Revision Properties Verify General CPLD And PROM Properties Erase Before Programming Read Protect PROM CoolRunnerl Usercode 8 Hex Digits CPLD Specific Properties Write Protect Functional Test On The Fly Program PLA UES Enter up to 13 characters PROM Specific Properties Load FPGA Parallel Mode Use D4 for CF Spartan34N Programming Properties Data Protect Data Lockdown FPGA Device Specific Programming Properties C Pulse PROG 7 Program Key C Assert Cable INIT during programming 2 Select OK to begin programming After programming is complete the status window will report INFO iMPACT 2219 Status register values INFO iMPACT 0011 1111 1001 1110 0000 1010 1110 0000 INFO iMPACT 1 Checking done pin done 11 Programmed successfully 11 Verifying device INFO iMPACT 2502 Complete word count is 9363744 32 292617 INFO iMPACT 2495 Readback Size is 9363744 done 1 Verification completed successfully INFO iMPACT 579 1 Completed downloading bit file to device INFO iMPACT 1 Checking done pin done 11 Programmed successfully PROGRESS_END End Operation Elapsed time 8 sec Revision 0 02 25 Connect Tech FreeForm PCI 104 User Manu
13. AB7 _ ddr2_a lt 11 gt AF3 ddr2_dq lt 11 gt AB6 ddr2_a lt 12 gt AF4 ddr2_dq lt 12 gt AB6 ddr2_a lt 12 gt AF4 ddr2_dq lt 12 gt AC9 ddr2_a lt 13 gt AFI2 ddr2_dq lt 13 gt AF12 ddr2_dq lt 13 gt AE7 ddr2_ba lt 0 gt AFS ddr2_dq lt 14 gt AE7 __ ddr2_ba lt 0 gt AFS ddr2_dq lt 14 gt AAS ddr2_ba lt 1 gt AF9 ddr2_dq lt 15 gt AAS _ ddr2_ba lt 1 gt AF9 ddr2_dq lt 15 gt v9 ddr2_ba lt 2 gt AD24 ddr2_dq lt 16 gt v9 ddr2_ba lt 2 gt AE8 ddr2_cas_n AE25 ddr2_dq lt 17 gt AE11 _ ddr2_ck lt 0 gt AC26 ddr2_dq lt 18 gt AE11 ddr2 ck lt 0 gt AD11 ddr2 ck_n lt 0 gt AC23 ddr2_dq lt 19 gt AD11 ddr2_ck_n lt 0 gt AD18 _ ddr2_cke lt 0 gt AB22 ddr2_dq lt 20 gt AC _ ddr2_cs_n lt 0 gt AC24 ddr2_dq lt 21 gt AE16 ddr2_dm lt 0 gt AE26 ddr2_dq lt 22 gt AE16 ddr2_dm lt 0 gt AE6 ddr2_dm lt 1 gt AD26 ddr2_dq lt 23 gt AE6 ddr2_dm lt l gt AD25 ddr2 dm lt 2 gt AD23 ddr2_dq lt 24 gt AD23 Ddr2_dq lt 24 gt AE18 _ ddr2_dm lt 3 gt AEI5 ddr2_dq lt 25 gt ARIS ddr2_dm lt 3 gt AEIS Ddr2 dq lt 25 gt AD19 ddr2_dqs lt 0 gt AF24 ddr2_dq lt 26 gt AD19_ ddr2_dqs lt 0 gt AF7 ddr2_dqs lt 1 gt AF13 ddr2_dq lt 27 gt AF7 ddr2_dqs lt 1 gt AF13 ddr2_dq lt 27 gt AF20 ddr2_dqs lt 2 gt AF14 ddr2_dq lt 28 gt AF20 ddr2_dqs lt 2 gt AF14 ddr2_dq lt 28 gt AF22 ddr2_dqs lt 3 gt AF25 ddr2_dq lt 29 gt AF22 ddr2_dqs lt 3 gt AD20 ddr2_dqs_n lt 0 gt AF15 ddr2_dq lt 30 gt AD20 ddr2_dqs_n lt 0 gt AF15 ddr2_dq lt 30 gt AF8 d
14. Connect Tech Inc Industrial Strength Communications FreeForm PCI 104 User Manual Connect Tech Inc 42 Arrow Road Guelph Ontario Canada NIK 1S6 Tel 519 836 1291 800 426 8979 Fax 519 836 4878 Email sales Oconnecttech com supportO connecttech com URL http www comnecttech com CTIM 00040 Revision 0 02 September 19 2008 Connect Tech FreeForm PCI 104 User Manual Limited Lifetime Warranty Connect Tech Inc provides a Lifetime Warranty for all Connect Tech Inc products Should this product in Connect Tech Inc s opinion fail to be in good working order during the warranty period Connect Tech Inc will at its option repair or replace this product at no charge provided that the product has not been subjected to abuse misuse accident disaster or non Connect Tech Inc authorized modification or repair You may obtain warranty service by delivering this product to an authorized Connect Tech Inc business partner or to Connect Tech Inc along with proof of purchase Product returned to Connect Tech Inc must be pre authorized by Connect Tech Inc with an RMA Return Material Authorization number marked on the outside of the package and sent prepaid insured and packaged for safe shipment The Connect Tech Inc Lifetime Warranty is defined as the serviceable life of the product This 1s defined as the period during which all components are available Should the product prove to be irreparable Connect Tech Inc reserve
15. PGA configuration storage 8MB Flash for embedded code storage Designed for embedded processing using MicroBlaze 100MHz input clock 128MB DDR2 400 memory 2 x 10 100 Ethernet with modular jacks 2 x RS 485 serial interface High speed serial connector 4 x Rocket I O GTP channels 64 single ended or 32 LVDS general purpose I O External 5V power connection for programming and development JTAG test and programming chain Industrial temperature range of 40 C to 85 C Ships preconfigured with a reference design About this manual This manual will provide the user with the following information 000000 0 Revision 0 02 System overview Introduction to the reference design Description of jumpers switches and connector pinouts Hardware installation instructions Software installation instructions FPGA configuration details Specifications Connect Tech FreeForm PCI 104 User Manual System Overview The following conceptual block diagram provides a high level overview of the FreeForm PCI 104 and illustrates the general interconnection between components and connectors For the actual orientation and description of components refer to Figure 2 and Table respectively PCI 104 Bus 1x6 Header Local Bus 64 I O 32 LVDS Pairs pe 2x40 Header 2x5 Header 2x5 2 Header JTAG Connector 1x7 Header High Speed Serial Ext Power Conne
16. Tyco Tyco 5 104069 3 3 111196 3 0 050 x0 100 pitch 2x40 ribbon cable mate or Tyco 8 487937 0 discrete wire housing Tyco 1 487547 1 crimps for housing Samtec Samtec Connect Tech Inc IPL1 102 01 S D IPD1 02 D MSG037 0 100 pitch 2x2 discrete wire housing 5V power supply for Samtec development purposes CC79L 2024 01 S crimps for housing or Samtec MMSD 02 22 S 03 25 S pre assembled housing and wiring Note CBG027 and MSG037 are available as part of development kit DEV002 For more details on mating components visit o Samtec http www samtec com o Tyco Electronics http www tycoelectronics com Revision 0 02 16 Connect Tech FreeForm PCI 104 User Manual Hardware Installation Before installing the FreeForm PCI 104 into a PCI 104 stack ensure the following o Slot selection is properly set using the rotary switch RSW1 o FPGA configuration jumper J1 is set to read from flash Once installed in the system and power is applied the LED D1 will illuminate to indicate that FreeForm PCI 104 is functioning Heat Sink Installation Each FreeForm PCI 104 ships with a FPGA heat sink 27 mm x 27 mm to be installed by the user Simply peel of the sticker backing and press firmly onto the FPGA using proper ESD precautions If the heat sink size is not suitable for your application please contact Connect Tech Inc WARNING In many applications including high
17. al Generating a PROM MCS File 1 Double click Prom File Formatter in the Flows window E Z Boundam Scan SolSlaveSerial Ta SelectMAP a Desktop Configuration a Direct SPI Configuration E System CE PROM File Formatter Modes 2 The Prepare PROM Files dialog will appear Ensure that the following settings are selected 3 Party SPI PROM MSC PROM File Format 3 Give the file a name and click Next iMPACT Prepare PROM Files want to target a O Xilinx PROM Generic Parallel PROM 31d Party SPI PROM PROM Supporting Multiple Design Versions Spartan3E MultiBoot PROM File Format QM OTEK UFP C format Exo BIN SC HEX Swap Bits Checksum Fill Value 2 Hex Digits FF PROM File Name init_plx_GPIO25 cs Location C Data Projects FreeF ormPCI104 hardware logic init_pk_GPIO25 Revision 0 02 Connect Tech FreeForm PCI 104 User Manual 4 Select the PROM density 16M gt click Next gt click Finish E iMPACT Specify SPI PROM Device C EE v 5 A prompt will ask to add device to data stream 0 Click OK Select the bitstream from the project directory Revision 0 02 27 Connect Tech FreeForm PCI 104 User Manual Add Device Look in CE init_plx_GPIO25 e Ed Recent Documents Desktop My Documents My Network Places Sie templates xst Z File name init Files of type FPGA Bit Fil
18. ctor Connector Figure 1 FreeForm PCI 104 Block Diagram Revision 0 02 7 Connect Tech FreeForm PCI 104 User Manual P10 ETH 1 gt ER si o 2 pe EHO UNIVERSAL STANDALONE SA O di FreeForm PCI 104 P1 PCI 184 pewi Table 1 FreeForm PCI 104 Components Connectors P1 Description PCI 104 connector P2 JTAG programming header P3 SPI flash programming header P4 High speed serial connector RS 485 header P7 GPIO header P8 External power header P9 RJ 45 A P10 RJ 45 B Jumpers Switches Description RSW1 Slot selection J1 Components FPGA configuration settings Description not all on top side User LEDs D5 FPGA load complete LED U4 PLX PCElocal bus bridge US Virtex 5 FPGA U10 FPGA configuration flash U11 Embedded code flash U12 U13 DDR2 memory U14 Parameter EEPROM U15 U16 RS 485 transceiver U17 Dual 10 100 PHY 01 02 03 Revision 0 02 Oscillators Connect Tech FreeForm PCI 104 User Manual Reference Design The FreeForm PCI 104 ships with a pre installed reference design that is loaded into the FPGA s configuration flash This reference design demonstrates how to interface the FreeForm PCI 104 Virtex 5 FPGA with the PLX PCI 9056 PCI to Local Bus Bridge as well as the various peripheral
19. der Pierina RE 14 External Power Connector PS 15 Connector s Mating Components and Cables A 16 Hardware Install EE 17 Heat Smk Installation tias ios 17 Stand alone Operation ee ees EES een 17 software Install muii dis 18 FPGA Development Environment 18 PLX Software Development Kit GD 18 Reference Design amp Application Examples AA 18 EPGA Configuration EE 19 Power and Thermal Constderattons crac cnn nnnnonn nono cn nono neon nono no rnncnns 20 Reference Design FPGA power analysis ooonnononononnconcconccononononnnonnncnncnanonnn conc conc crec necnnos 20 e A ess Sec hes avai cige av ea ates deci bce i RUG ele eel 21 Appendix A iMPACT Instructions for FPGA Confeurapon 22 Launch Impact EE 22 Programming the PPOO A 25 Generating a PROM MCS bie 26 Configuring the FPGA with the SPI Flach 29 Configuring the FPGA SPI flash Association 29 Programming the Flash AA 31 Appendix B Power calculations oooonncnnncnoccnonnconoconccononnnono nono nono nnnn non nnnn cnn c nero nero nooo coca ncnnninns 33 Scenario 1 Heatsink attached 250 LFM ccccccccsssssscecececeessssececececeessntsaeeeeeens 33 Scenario 2 No Heatsink 250 LEM 34 Scenario 3 No heatsink OLEM a A N 35 Appendix C Hardware Changes from Revision B A 36 Reference Design icon nicootcin estaca orasa inca ni asta Ee eN RAE rebanada esa 37 Hardware Description G cocovecuinesianono ccassseesscudb esti sce tania andaba abans resina
20. dr2_dqs_n lt 1 gt AF23 ddr2_dq lt 31 gt AF8 ddr2_dqs_n lt 1 gt AF23 ddr2_dq lt 31 gt AE20 ddr2 dos n lt 2 gt AD13 _ ddr2_odt lt 0 gt AE20 ddr2_dqs_n lt 2 gt AE21 ddri dos mei AAT ddr2_ras_n AE21 ddr2_dqs_n lt 3 gt AAT ddr2_ras_n ABS ddr2_we_n ABS ddr2_we_n Revision 0 02 37 Connect Tech FreeForm PCI 104 User Manual Hardware Description Connector Pinouts High speed Serial P4 The sideband LVCMOS signals HSS have been rearranged so that when two FreeForm units are connected HSS_USER_IO 0 maps to HSS_USER_IO 2 HSS_USER_IO 1 maps to HSS_USER_IO 3 Also 3 3V pins replace the GND pins this is because the connector has embedded GND blades Revision B Revision C 1 MTGRXNO_112 1 MTGRXNO_112 3 MTGRXPO_112 3 MTGRXP0_112 2 MTGTXNO_112 2 MTGTXNO_112 4 MTGTXPO_112 4 MTGTXPO_112 5 GND HSS_US 7 GND 6 HSS_USER_IO 0 8 HSS_USER_IO 1 3 9 MTGRXN1_112 MTGRXN1_112 11 MTGRXP1_112 11 MTGRXP1_112 10 MTGTXNI_112 10 MTGTXN1_112 12 MTGTXPI_112 12 MTGTXPI_112 13 GND 15 GND 14 GND 16 GND 17 MTGRXNO_114 17 MTGRXNO_114 19 MTGRXPO_114 19 MTGRXPO_114 18 MTGTXNO_114 18 MTGTXNO_114 20 MTGTXP0_114 20 MTGTXPO_114 21 GND 23 GND 22 HSS_USER_IO 2 24 HSS_USER_IO 3 25 MTGRXNI_114 25 MTGRXNI_114 27 MTGRXP1_114 27
21. eeForm PCI 104 is being programmed outside of a PCI PCI 104 system Table 10 External Power Connector Pinout P8 5V P8 Standalone Power Input GND VIO connect to 5V It is recommended that a Connect Tech Inc FreeForm PCI 104 power supply is used for providing external power Orientation of the power supply connector is important Ensure that the clip on the cable aligns with the catch on P8 as shown below Figure 3 External Power Connection Revision 0 02 15 Connect Tech FreeForm PCI 104 User Manual Connector s Mating Components and Cables The following table lists the manufacturer and part number for connectors on the FreeForm PCI 104 as well as potential mating components Table 11 Connector Mate Listing Samtec Samtec Connect Tech Inc TSW 107 07 L S SSW 107 xx G S CBG027 0 100 pitch 1x7 Socket other options available JTAG programming cable Samtec Samtec Connect Tech Inc TSW 106 07 L S SSW 106 xx G S CBG027 0 100 pitch 1x6 Socket other options available JTAG programming cable Samtec Samtec Connect Tech QSE 014 01 L D DP A QTE 014 01 L D DP A Please contact sales for more 0 8mm pitch 2x14 5mm mated height other information arranged as 14 differentials heights available pairs Samtec Samtec Connect Tech Inc TSW 105 07 L D SSW 105 xx G D CAG104 0 100 pitch 2x5 Socket other options available Header to DB9
22. es bit Je 6 Click No when asked if another device is to be added Click OK to accept the setup 7 Double Click Generate File from the iMPACT processes menu The status will be reported in the console Available Operations are Generate File Operations BATCH BATCH BATCH BATCH BATCH BATCH Z ch BATCH CMD setMode pff CMD CMD setAttribute CMD setAttribute CMD setAttribute CMD setAttribute CMD setAttribute setSubmode pffparallel configdevice configdevice configdevice configdevice configdevice aber Seabee attr a TEE attr fillValue value FF swapBit value true fileFormat value mcs dir value UP path value a eee es ee GPIO25 CMD setAttribute configdevice attr name value init_plx_GPIO25 cs BATCH Total configuration bit size Total configuration byte size BATCH BATCH 9371136 bits 1171392 bytes CMD setCurrentDesign version 0 CMD generate spi Swap bit can only be disabled in Hex file format only OxlldfcO 1171392 bytes loaded up from 0x0 Using user specified prom size of 2048K Writing file C Data Projects FreeFormPC1I104 hardware logic init_plx_GP1I025 init_plx_GPI025 mcs Writing file C Data Projects FreeFormPC1I104 hardware logic init_plx_GP1I025 init_plx_GPI025 prm Revision 0 02 28 Connect Tech FreeFo
23. ference only They do not provide power to the configuration circuitry Table 5 SPI Flash Programming Header Pinout P3 SPI_CSN Input SPI_MOSI Input SPI_MISO Output SPI_CLK Input GND Reference 3 3V Reference SPI Flash Header P3 APA Top View Revision 0 02 11 Connect Tech FreeForm PCI 104 User Manual High speed Serial P4 The high speed serial connector carries four Rocket GTP I O channels each with a dedicated transmit and receive differential pair These channels are capable of operating up 3 125 Gbps depending on configuration For more information on Rocket I O capabilities visit the Xilinx website http www xilinx com products silicon_solutions fpgas virtex virtexS Table 6 Hi MTGRXNO_112 Input h Speed serial Connector Pinout P4 b MTGRXP0_112 Input b MTGTXNO_112 Output b MTGTXP0_112 Output b HSS_USER_IO 0 Input Output a d HSS_USER_IO 1 Input Output a d HSS_USER_IO 2 Input Output a d HSS_USER_IO 3 Input Output a d MTGRXN1_112 Input b MTGRXP1_112 Input b MTGTXN1_112 Output b MTGTXP1_112 Output b DIDlS ZL olaola 3 3V Power a 3 3V Power a 3 3V Power a 3 3V Power a MTGRXNO_114 Input c MTGRXP0_114 Input c
24. ibe the function of all switches jumpers and provide details on connector pinouts Jumpers and Switches Slot Selection RSW1 This rotary switch selects a slot position in the PCI 104 stack When mounting on a PCI adapter card ensure slot one is selected Table 2 Slot Selection RSW1 FPGA Configuration Settings J1 Jumper J1 is used to control FPGA configuration Table 3 FPGA Configuration Settings J1 FPGA waits for configuration over JTAG using P2 FPGA reads configuration from SPI flash FPGA is tri stated flash is isolated from FPGA and can be programmed directly Revision 0 02 10 Connect Tech FreeForm PCI 104 User Manual Connector Pinouts PCI 104 Header P1 Refer to PCI 104 specifications Note P1 must be connected to a PCI 104 stack supplying both 3 3V and 5V JTAG Programming Header P2 Use P2 to configure the FPGA via JTAG Refer to FPGA Configuration for more information Power pins are for voltage reference only they do not provide power to the configuration circuitry Note that the FPGA can always be programmed via JTAG regardless of the J1 configuration setting Input Input Input Output Input Reference Reference SPI Flash Programming Header P3 P3 may be used to directly program the SPI flash providing that J1 is set correctly to the tri state FPGA position The power pins are for voltage re
25. ked and verified Flash is erased Flash is programmed After completion of the flash programming the FPGA will attempt to configure itself from the flash If the SPI flash setting is not selected with J 1 this step will fail This does not mean the flash is not programmed but rather the verification of the programmed contents has failed rie SPI access core not detected SPI access core will be downloaded to the device to enable operations PROGRESS_START Starting Operation ER done 115 INFO INFO INFO INFO INFO INFO Downloading core Reading status register contents iMPACT 2219 Status register values iMPACT 0011 1111 1001 1110 0000 1010 1000 0000 iMPACT 2492 1 Completed downloading core to device iMPACT 1 Checking done pin done Core downloaded successfully IDCODE is 202015 in hex ID Check passed IDCODE is 202015 in hex ID Check passed Erasing Device Programming Device Reading device contents Verification completed iMPACT 1 Checking done pin done Programmed successfully iMPACT 1 Checking done pin done Programmed successfully PROGRESS_END End Operation Elapsed time 179 sec Revision 0 02 32 Connect Tech FreeForm PCI 104 User Manual Appendix B Power calculations Scenario 1 Heatsink attached 250 LFM Used Total Available Utilization Total Dynamic Total EE Junction Temp Ambient Temp
26. on B and Revision C which need to be added to the ISE project manually Revision B Local Clock Generation Local clock generated in Revision C Dedicated oscillator FPGA and forwarded to PLX generates local bus clock Y21 _ lb_lcikfb bridge Clock feedback to Y21 Tb_Iclkfb Clock is driven to FPGA on A20 lb_lclko_loop FPGA via pin Y21 pin Y21 which drives an B21 E ER internal global clock net DDR2 Pinout Pin SignalName Pin Signal Name AA9 ddr2_a lt 0 gt AD21 ddr2_dq lt 0 gt AA9 ddr2_a lt 0 gt Y8 ddr2_a lt 1 gt AD15 ddr2_dq lt 1 gt Y8 ddr2_a lt 1 gt AD15 ddr2_dq lt 1 gt AD8 ddr2_a lt 2 gt AC21 ddr2_dq lt 2 gt AD8 ddr2_a lt 2 gt Y7 ddr2_a lt 3 gt AD14 ddr2_dq lt 3 gt Y7 ddr2_a lt 3 gt AB9 ddr2_a lt 4 gt AE13 ddr2_dq lt 4 gt AB9 ddr2_a lt 4 gt WO ddr2_a lt 5 gt AE22 ddr2_dq lt 5 gt WO ddr2_a lt S gt AE22 ddr2_dq lt 5 gt AC8 ddr2_a lt 6 gt AD16 ddr2 dq lt 6 gt AD16 ddr2_dq lt 6 gt AD6 ddr2_a lt 7 gt AE17 ddr2_dq lt 7 gt AD6 ddr2_a lt 7 gt AA8 ddr2_a lt 8 gt AF10 ddr2_dq lt 8 gt AA8 ddr2_a lt 8 gt AF10 ddr2_dq lt 8 gt V8 ddr2_a lt 9 gt AES ddr2_dq lt 9 gt V8 ddr2_a lt 9 gt AES ddr2_dq lt 9 gt ACHT ddr2_a lt 10 gt AE12 ddr2_dq lt 10 gt AC7 _ ddr2_a lt 10 gt AE12 ddr2 dq lt 10 gt AB7 ddr2_a lt 11 gt AF3 ddr2_dq lt 11 gt
27. rm PCI 104 User Manual Configuring the FPGA with the SPI Flash In previous Xilinx FPGA configurations the SPI flash required programming via 3 party JTAG test software or through in system methods The following features are new to ISE 9 1 9 2 and are only available on select FPGAs including the Virtex 5 Your FreeForm PCI 104 card featuring the Xilinx Virtex 5 FPGA includes a standard core to enable programming of BPI and SPI flashes over JTAG Configuring the FPGA SPI flash Association 1 Select Boundary Scan from the Flows tab H SS Boundary Scan Sa SlaveSerial Ba SelectMAP alDesktop Configuration Ea Direct SPI Configuration E SystemACE E PROM File Formatter Modes 2 Right click on the FPGA and select Add SPI Flash TDI Program Verify CM Get Device ID int Get Device Signature Usercode TDO Add SPI Flash Add BPI Flash Assign New Configuration File Revision 0 02 Connect Tech FreeForm PCI 104 User Manual 3 Browse to the directory containing the previously generated MCS file Select and click Open Add PROM File BAR Look in E init_plx_GPI025 Eme ES EEN 5 _xmsgs My Recent templates Documents Ext E Blinit pk GP1O25 mes Desktop My Documents My Computer My Network File name fini_plx_GPI025 mes Places Files of type mes Files mes y Cancel Y 4 The FPGA SPI Flash Association windo
28. s Launch Impact 1 Open iMPACT and select create a new project E iMPACT Project want to 3 plx_full ipf Browse C Load most recent project file when iMPACT starts create a new project ipf default ipf Cancel 2 Select configure devices using boundary scan iMPACT will scan the JTAG chain and identify three devices The first device will be the FPGA TDI unknown file unknown file xcSvix30t file TDO Revision 0 02 22 Connect Tech FreeForm PCI 104 User Manual 3 A prompt will ask for a new configuration file Select the bitstream from the project directory g Assign New Configuration File PR Look in Eqpjects FreeFomPCI104 hardware logic init_plk_GPID25 v 4 DI Ek E a 3_ngo _xmsgs templates rst File name init bit File type All Design Files P bi rbt nky ise bsd E Cancel Cancel All Bypass None Enable Programming of SPI Flash Device Attached to this FPGA Enable Programming of BPI Flash Device Attached to this FPGA 4 A prompt will ask for a BSDL file for device number 2 PLX PCI9056 Click Yes Unknown Device File Query Do you have a BSDL or BIT file for this device 5 Browse to the bsdl folder and select PCI9056BA bsd Add Device Look in E bei DI e cy ES E E My Recent Type BSDL File Documents Date Modified 2007 10 26 4 31 PM Size
29. s The PLX 9056 provides a generic local bus that is capable of operating at up to 66MHz this design forwards a 50MHz clock to the PLX The PLX bridge has been set in the C Mode of operation The reference logic operates as a local bus slave as well as a local bus master The reference design contains examples demonstrating Loading of PLX 9056 s registers via the local bus Local bus slave transfers Local bus master transfers GPIO control Programming the SPI Flash Interfacing to the built in Virtex 5 TEMACs RS 485 serial data transfers Reading writing to the serial EEPROM Reading writing to DDR2 memory Interfacing to the Virtex 5 Rocket I O transceivers 000000000 0 Most of the example VHDL modules demonstrate how to interface with the various peripherals through a register set which is accessible by the host system over the PCI bus A set of software applications has been created to show how the host system can communicate with each FPGA sub module In most applications the host system will not directly control these peripherals In a custom application these modules can be easily modified to interconnect with each other through the FPGA fabric To obtain the source code refer to Software Installation For further details on the reference design refer to FreeForm PCI 104 Reference Design Guide CTIM 00042 Revision 0 02 9 Connect Tech FreeForm PCI 104 User Manual Hardware Description The following sections descr
30. s 38 Connector note ek ENER alain AEN ee 38 Specifications dias 39 Revision 0 02 4 Connect Tech FreeForm PCI 104 User Manual List of Tables Table 1 FreeForm PCI 104 Components ccoccnoccconcnonononcnnnonnnnnnnnnnonnnonnoco nono nocn conocio nn nono crac crncnnnns 8 Table 2 Slot Selection RS Witt Eege EE Ee Ee 10 Table 3 FPGA Configuration Settings OI 10 Table 4 JTAG Programming Header Pinout OD 11 Table 5 SPI Flash Programming Header Pinout D i 11 Table 6 High Speed serial Connector Pinout DA 12 Table 7 RS 485 Port 1 Pinout Pai 13 Table 8 RS 485 Port 2 Pinout Pei 13 Table 9 GPIO Header Pour 14 Table 10 External Power Connector Pinout OP 15 Table 11 Connector Mate Listing cnn cnn cn neon nooo arcano rancios 16 List of Figures Figure 1 FreeForm PCI 104 Block Diagramm 7 Figure 2 FreeForm PCI 104 Layout 8 Figure 3 External Power Connecton nono nnnnnnnncnnn nono co nono E a 15 Revision 0 02 5 Connect Tech FreeForm PCI 104 User Manual Introduction Connect Tech s FreeForm PCI 104 features Xilinx s Virtex 5 multi platform FPGA offering users a flexible reconfigurable computing platform that also takes advantage of the high bandwidth capabilities of the PCI bus while communicating with various I O interfaces Product Features ef et e ARa DE et e AR e O OOO O 0 0 0 PCI 104 form factor 32 Bit 33MHz Xilinx multi platform Virtex 5 FPGA with 3 million logic gates 2MB Flash for F
31. s the right to substitute an equivalent product if available or to retract Lifetime Warranty if no replacement is available The above warranty is the only warranty authorized by Connect Tech Inc Under no circumstances will Connect Tech Inc be liable in any way for any damages including any lost profits lost savings or other incidental or consequential damages arising out of the use of or inability to use such product Copyright Notice The information contained in this document is subject to change without notice Connect Tech Inc shall not be liable for errors contained herein or for incidental consequential damages in connection with the furnishing performance or use of this material This document contains proprietary information that is protected by copyright All rights are reserved No part of this document may be photocopied reproduced or translated to another language without the prior written consent of Connect Tech Inc Copyright O 2008 by Connect Tech Inc Trademark Acknowledgment Connect Tech Inc acknowledges all trademarks registered trademarks and or copyrights referred to in this document as the property of their respective owners Not listing all possible trademarks or copyright acknowledgments does not constitute a lack of acknowledgment to the rightful owners of the trademarks and copyrights mentioned in this document Revision 0 02 2 Connect Tech FreeForm PCI 104 User Manual Customer Support Overview
32. speed memory operations the FPGA dissipates a significant amount of power Failure to use any heat sinking will result in the product warranty being voided Stand alone Operation Operating the FreeForm PCI 104 outside of a PCI 104 stack or a PCI system for extended periods of time is not recommended The PCI to local bus bridge PCI PLX 9056 requires the pull up pull down resistors provided on a system s main board Configuring or programming the FreeForm PCI 104 in stand alone mode is acceptable providing that it is not left powered on in stand alone state for an extended period of time WARNING The power supply MSG037 included with the development kit DEV002 is intended for desktop programming only It is not intended or warranted to be used in any other situation Revision 0 02 17 Connect Tech FreeForm PCI 104 User Manual Software Installation FPGA Development Environment FreeForm PCI 104 has been developed with Xilinx WebPACK 9 2 available free of charge at http www xilinx com ise logic_design_prod webpack htm PLX Software Development Kit SDK PLX provides a software development kit SDK to aid in the creation of applications using the PLX 9056 bridge The SDK provides a generic driver for Windows 2000 XP and Linux A common API is also included which encapsulates functions like Configuration register read write Block read block write to local address space i e memory registers in the FPGA
33. used since this is the absolute point of failure Revision 0 02 20 Connect Tech FreeForm PCI 104 User Manual Specifications Programmable FPGA Virtex 5 FPGA LX30T Input Clock 100MHz Memory Flash 128MB DDR2 400 2MB Flash FPGA configuration 8MB Flash Embedded code 4K serial EEPROM parameter storage General Purpose User I O 64 single ended I O 32 LVDS I O Serial 2 x RS 485 Ethernet 2 x 10Base T 100Base TX High speed serial 4 x Rocket I O transceivers GTP Operating Environment Storage Temperature 65 C to 150 C Operating Temperature 0 C to 70 C commercial 40 C to 85 C industrial Power Requirements 5V DC in PCI 104 stack 5V DC standalone Current requirements are configuration dependant Dimensions PC 104 Plus 2 2 compliant PCI 104 1 0 compliant Connectors Two RJ 45 modular jacks Ethernet Two 2x5 0 100 headers serial One 2x40 0 050 x 0 100 header general I O One 1x6 0 100 header flash programming One 2x14 0 8 mm differential pair terminal high speed serial Revision 0 02 Connect Tech FreeForm PCI 104 User Manual Appendix A MPACT Instructions for FPGA Configuration To configure the FPGA via JTAG connect the JTAG programming cable to P2 ensuring that all JTAG signals align correctly It is important to note that P2 also has the TRST signal on pin 1 which is not part of Xilinx s Parallel or USB programming cable
34. w will appear select M25P16 this is the flash device connected to the FPGA L FPGA SPI Flash Association Select SPI Flash FPGA xcSvix30t TDI xeSvix30t pci9O56ba_r1 dp83849i init bit pci9056ba bsd dp83849ivs bsd TDO Revision 0 02 30 Connect Tech FreeForm PCI 104 User Manual Programming the Flash 1 Right click the previously associated flash device and select program Verify Erase Blank Check Readback TDI 3049ivs bsd Assign New Configuration File Delete TDO 2 The programming dialog will appear Select Verify and Erase Before Programming then click OK g Programming Properties Category E Programming Properties Advanced PROM Programming Properties Revision Properties Verify General CPLD And PROM Properties H j Read Protect PROM CoolRunnerl Usercode 8 Hex Digits EE CPLD Specific Properties Write Protect Functional Test On The Fly Program PLA UES Enter up to 13 characters PROM Specific Properties Load FPGA Parallel Mode Use D4 for CF Spartan3 N Programming Properties Data Protect Data Lockdown FPGA Device Specific Programming Properties Pulse PROG Program Key J Assert Cable INIT during programming Revision 0 02 31 Connect Tech FreeForm PCI 104 User Manual 3 Observe the results in the transcript window Dn gp The SPI core is first download to the FPGA device The IDCODE is chec
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