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Company X Accessories C1030-5510 Electronic Keyboard User Manual

1. Move currently selected entry on position up Move currently selected entry on position down Remove currently selected entry All buttons should be self explanatory but here s a more detailed look on the add entry it opens the following dialog Choose option to add Program design file to FPGA o mm Reset FPGA Write register value Sleep o Figure 16 Add new initializing task One of the four possible entries must be selected using the radio button in front of it Depending on the option one or two parameters must be set OK adds the new action to initializer list USBS6 C1030 5510 http www cesys com User Doc V0 3 56 preliminary Sequence start The button sitting below the list runs all actions from top to bottom In addition to this the remaining Ul components the content panel will be enabled as UDKLab expects a working communication at this point The sequence can be modified an started as often as wished Content panel The content panel can be a visual representation of the FPGA design loaded during initialization It consists of a list of registers and data areas which can be visit and modified using UDKLab The view is split into two columns while the left part contains the registers and the right part all data area block entries GPIO OE BankO gt 0x00100008 Block RAM gt 0x00000000 Hex 40000000 1073741824 Address Range 0x00000000 0x000007
2. IN OUT BANK 0 21 514 22 ADDO N IN OUT BANK 0 21 497 25 ADD 10 IN OUT BANK 0 24 381 26 ADD IO N IN OUT BANK 0 24 354 ADD IO IN OUT BANK 0 25 102 28 ADD IO N IN OUT BANK 0 25 137 29 ADDIO IN OUT BANK 0 25 150 30 ADD IO N IN OUT BANK 0 25 137 EN ADD IO IN OUT BANK 0 26 005 32 ADD IO N IN OUT BANK 0 25 980 35 ADD IO IN OUT BANK 0 40 687 36 ADD IO N IN OUT BANK 0 40 669 ADD IO IN OUT BANK 0 40 905 38 ADD IO IN OUT BANK 0 40 865 a wo em P wrour wes aan Fa moo ws n nour panko 43577 Fa aso ou e nor swo sam USBS6 C1030 5510 http www cesys com User Doc V0 3 66 preliminary CPN Wermame FPGAIO PIN Direction FPGABANK Etch Length mm a oio cw n wiour panko somo Fas 6 es P iow eko ao pas ao ws w wrour sanko ass USBS6 C1030 5510 http www cesys com User Doc VO 3 67 preliminary Mechanical dimensions 4 2 1 Sv v6 001 Figure 20 USBS6 mechanical dimensions in mm USBS6 C1030 5510 http www cesys com User Doc V0 3 68 preliminary Table of contents Table of Contents ERS ET LONE TET 2 External DT v QULA TRETEN 9 EE AR a uiii dl os tss ci Gral Duis i fi boo Up tUa M Quim a b ann 11 USBS6 C1030 5510 http www cesys com User Doc V0 3 69 preliminary
3. Register read and write either by value or bit wise using checkboxes Live update of register values Data areas like RAM or Flash can be filled from file or read out to file Live view of data areas More on these areas below LJ 01 ro Device Project Tools Info GPIO OE BankO gt 0x00100008 8 9 amp Hex 40000000 a l write Block RAM gt 0x00000000 t Address Range 0x00000000 0x000007ff 2kByte 0 MB Alignment 4 byte w HAAF wa DE Hi Lo GPIO BankO gt 0x00100000 Hex 40000000 J O 0O 0 0 Read __write ocam Q 38 gt 8 E EDH 2 Hi DMI to HAA IO OE Bank1 gt 0x0010000c Hex 00000000 88 Deantoni enes RENA 00000000 00 00 00 00 00 00 00 00 00000008 00 00 00 00 00 00 00 00 00000010 00 00 00 00 00 00 00 00 00000018 00 00 00 00 00 00 00 00 00000020 00 00 00 00 00 00 00 00 00000028 00 00 00 00 00 00 00 00 00000030 00 00 00 00 00 00 00 00 00000038 00 00 00 00 00 00 00 00 00000040 00 00 00 00 00 00 00 00 00000048 00 00 00 00 00 00 00 00 Flash Contents gt 0x00200000 E Read wie 2 Address Range 0x00200000 0x0027ffff 512 kByte 0 MB Alignment 4byte Hi DDD DODOD DE E Deve Toric Lem Lo II IE a PIO Bank1 gt 0x00100004 Hex 00
4. CESYS GmbH provides this documentation without warranty term or condition of any kind either express or implied including but not limited to express and implied warranties of merchantability fitness for a particular purpose and non infringement While the information contained herein is believed to be accurate such information is preliminary and no representations or warranties of accuracy or completeness are made In no event will CESYS GmbH be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document CESYS GmbH will make improvements or changes in the product s and or program s described in this documentation at any time CESYS GmbH retains the right to make changes to this product at any time without notice Products may have minor variations to this publication known as errata CESYS GmbH assumes no liability whatsoever including infringement of any patent or copyright for sale and use of CESYS GmbH products CESYS GmbH and the CESYS logo are registered trademarks All product names are trademarks registered trademarks or service marks of their respective owner Please check www cesys com to get the latest version of this document CESYS Gesellschaft f r angewandte Mikroelektronik mbH Zeppelinstrasse 6a D 91074 Herzogenaurach Germany USBS6 C1030 5510 http www cesys com User Doc V0 3 2 preliminary Overview Summary of USBS6
5. OUT ADR 1 0 b 00 and EP6 IN ADR 1 0 b 10 Switching FIFOADR 1 is enough to select data direction FIFOADR O has to be statically set to LOW FLAG A B C FX 2 outputs A gt EP2 empty flag B gt EP2 almost empty flag meaning one 16 bit data word is available C gt EP6 almost full flag meaning one 16 bit data word can still be transmitted to EP6 there is no real full flag for EP6 almost full could be used instead FD 15 0 bidirectional tristate data bus Introduction to example FPGA designs The CESYS USBS6 Card is shipped with some demonstration FPGA designs to give you an easy starting point for own development projects The whole source code is written in USBS6 C1030 5510 http www cesys com User Doc V0 3 18 preliminary VHDL Verilog and schematic entry design flows are not supported The design usbs6 soc demonstrates the implementation of a system on chip SoC with host software access to the peripherals like GPIOs external Flash Memory LPDDR Memory and internal BlockRAM over USB This design requires a protocol layer over the simple USB bulk transfer see CESYS application note Transfer Protocol for CESYS USB products for details which is already provided by CESYS software API The design usbs6 bram is a minimal example for data transfers from and to the FPGA over USB and can be used to get for familiar with UDK hardware software interface The Spartan 6 X
6. USBS6 is a low cost multilayer PCB with SPARTAN 6 FPGA and USB 2 0 Interface 34 I O balls of the FPGA are available on standard 2 54mm headers 81 I O balls can be reached through a industry standard VG 96 pin connector It offers multiple configuration options including USB and onboard SPI Flash and can also be used standalone without the need of a USB interface Feature list Form factor 120x100mm XILINX SPARTAN 6 XC6SLX16 2CSG324C USB2 0 Controller CYPRESS CY7C68013A FPGA configuration Using USB2 0 JTAG or SPI Flash Memory 16Mb SPI Flash Numonyx M25P 16 128Mb Quad SPI Flash Macronix MX25L12845EMI 10G 1Gb low power DDR SDRAM Micron Technology MT46H64M16LFCK 5 Peripherals USB TO SERIAL UART FTDI FT232R HEX rotary DIP switch 3 status 5 user LEDs Expansion connectors 2x25 Pin standard RM2 54mm header VG 96 pin connector Clock Onboard 48MHz clock signal up to two optional onboard clocks external clock sources possible Included in delivery The standard delivery order no 1030 5510 includes s One USBS6 One USB cable 1 5m One CD ROM containing the user s manual English drivers libraries tools and example source code All parts are ROHS compliant USBS6 C1030 5510 http www cesys com User Doc V0 3 3 preliminary Hardware Block Diagram wlas TT i os RE EM EE mo EE EM ol e Eme E B 3 status amp USB to HEX rotary
7. contents in the data area limited by the file size or data area size This button is not shown if the Read only flag is set Live View If this button is active the text view below shows the contents of the area updated every 100 ms the view can be scrolled so every piece can be visited USBS6 C1030 5510 http www cesys com User Doc V0 3 59 preliminary Additional information Using SPI Flash for configuration How to store configuration data in SPI Flash To allow configuration of the FPGA via onboard SPI Flash on power up first an appropriate configuration file has to be stored in the SPI Flash There are several ways to accomplish this Loading SPI Flash via USB The easiest way to get data into SPI Flash surely is to use CESYS software UDK Lab With the help of this easy to use tiny tool binary FPGA configuration bitstreams bin can be downloaded to onboard SPI Flash via USB SPI Flash Indirect Programming Using FPGA JTAG Chain Since XILINX ISE WebPACK version 10 1 it is possible to configure SPI Flashes attached to the FPGA via JTAG interface Before starting to download a design to SPI Flash with iMPACT programming software it is necessary to prepare the required mcs SPI PROM file With xapp951 XILINX provides an application note how to accomplish that using iMPACT or PROMGen software tools Select 16M SPI PROM Density when asked Thereafter connect JTAG adapter and power up USBS6 either by connecting
8. it must be at least of size uiDestSize GetDeviceName API Code C const char ceDevice GetDeviceName C CE RESULT GetDeviceName CE DEVICE HANDLE Handle char pszDest unsigned int uiDestSize NET string ceDevice GetDeviceName USBS6 C1030 5510 http www cesys com User Doc V0 3 43 preliminary Return device type name of given device pointer or handle Notice C API pszDest is the buffer were the value is stored to it must be at least of size uiDestSize GetBusType API Code C ceDevice ceBusType ceDevice GetBusType C CE RESULT GetBusType CE DEVICE HANDLE Handle unsigned int puiBusType NET ceDevice ceBusType ceDevice GetBusType Return type of bus a device is bound to can be any of the following Constant Bus ceBT PCI PCI bus ceBT USB USB bus GetMaxTransferSize API Code C unsigned int ceDevice GetMaxTransferSize C CE RESULT GetMaxTransferSize CE DEVICE HANDLE Handle unsigned int puiMaxTransferSize NET uint ceDevice GetMaxTransferSize Return count of bytes that represents the maximum in one transaction larger transfers must be split by the API user USBS6 C1030 5510 User Doc V0 3 44 http www cesys com preliminary Using devices After getting a device pointer or handle devices can be used Before transferring data
9. w Wo E E w w x ADI m w A 1 e m 1 O w 9 Us m wo e as oin e up o w m moor m x avion a m apoio z2 w ois m m m a USBS6 C1030 5510 http www cesys com User Doc V0 3 15 preliminary J4 IDC 2x25 Pin external expansion connector PIN FPGAIO Comment Ta eaa Gommon m em io as an Avo a su oim zm wz os a sw im ao au moon a ew iom ae we moos raf eo w ew cw woe 3 We ios w pu moos s cm amor m eo e ew a cu moos e ws uos pw 10x cu avion cw jo Ws o os nwe e c m vecoro fof eso aar OoOO yO GCLK Enable Disable optional pull up resistors during configuration Pulled HIGH via external 4 7 kOhm resistor Leave unconnected It is strongly recommended to check the appropriate data sheets of SPARTAN 6 devices about special functionality IO like GCLK HSWAPEN USBS6 C1030 5510 http www cesys com User Doc V0 3 16 preliminary FPGA design Cypress FX 2 LP and USB basics Several data transfer types are defined in USB 2 0 specification High speed bulk transfer is the one and only mode of interest to end users USB transfers are packet oriented and have a time framing scheme USB packets consist of USB protocol and user payload data Payload could hav
10. 00000 Dec Read wie Hi AB to DOE ish Command gt 0x00280000 Hex 00000 Read a gt Figure 11 UDKLab Main Screen Hi Lo 00200000 ff ff ff ff aa 99 55 66 00200008 30 00 80 O1 00 00 00 07 00200010 30 01 60 01 00 00 00 60 00200018 30 01 20 01 00 00 31 e5 00200020 30 01 cO 01 01 c2 20 93 00200028 30 00 cO 01 00 00 00 00 00200030 30 00 80 01 00 00 00 09 00200038 30 00 20 01 00 00 00 00 00200040 30 00 80 01 00 00 00 01 00200048 30 00 40 00 50 01 14 Sa USBS6 C1030 5510 User Doc V0 3 51 http www cesys com preliminary Using UDKLab After starting UDKLab most of the UI components are disabled They will be enabled at the point they make sense As no device is selected only device independent functions are available The FPGA design array creator The option to define USB Power On behavior Info menu contents All other actions require a device which can be chosen via the device selector which pops up as separate window a Choose device selector e Select device to work with g Confirm selection same as double click on 2 Oo Re Trigger device enumeration i e after device un plug Figure 12 Device selection flow If the device list is not up to date clicking Re Enum will search again A device can b
11. C API offers all functions from a dynamic link library Windows dll Linux so and uses standardized data types only so it is usable in a wide range of environments Adding it to the UDK build process is nearly identical to the C API description except that UDKAPIC LIBNAME must be used USBS6 C1030 5510 http www cesys com User Doc V0 3 37 preliminary NET API Include file Library file udkapinet dll resided in bin build Namespace cesys ceUDK The NET API as well as it example application is separated from the normal UDK build First of all CMake doesn t have native support NET as well as it is working on Windows systems only Building it has no dependency to the standard UDKAPI all required sources are part of the NET API project The Visual Studio solution is located in directory dotnet inside the UDK installation root It is a Visual Studio 8 2005 solution and should be convertible to newer releases The solution is split into two parts the NET API in mixed native managed C and an example written in C To use the NET API in own projects it s just needed to add the generated DLL udkapinet dll to the projects references API Functions in detail Notice To prevent overhead in most usual scenarios the API does not serialize calls in any way so the API user is responsible to serialize call if used in a multi threaded context Notice The examples for NET in the following chapter are in C
12. Ke ee en TER Re eo ozi oy eee ee e e e o e e D B 2959 CE S L Figure 2 USBS6 Top View USBS6 C1030 5510 http www cesys com User Doc V0 3 5 preliminary Powering USBS6 USBS6 may be used bus powered see SW2 below without the need of any external power supply other than USB In this mode VCCO IO on J3 PIN A3 B3 C3 sourcing capability is limited due to the fact that USB power supply current is limited depending on which system is used as host Typically USB hosts allow up to 500mA In bus powered mode at first only FX2 is enabled After successful connection to the operating system the further power on sequencing behavior depends on UDK configuration Until the release of UDK2 0 only the API could enable further power on sequencing therefore after plugging an USB cable it also was necessary to start an application like cesys Monitor before the FPGA and other devices turned on With v2 0 and upcoming releases of UDK framework the user now can decide which power on behavior fits best Power on sequencing through API or as soon as USB cable is plugged in Default mode is API controlled Modes of ee Commet Y O Commet Y O VCCO IO Bus powered m USB is used as power supply input 3 3V mA Connect 5V power supply to VG 96pin external 3 3V 3A expansion connector J3 PINS A1 B1 and C1 Self powered Minimum required supply current A The actual required supply curre
13. Length mm BANK 3 52 506 BANK 3 52 504 BANK 3 BANK 3 rast ves rz P nm N N A12 N N 60 987 60 972 D2 D1 N N BANK 3 BANK 3 50 233 50 221 VG96 1024 VG96 1025 A13 VG96 1027 C2 B13 VG96 1028 1 C13 C12 Zz N N BANK 3 BANK 3 48 317 48 315 VG96 1029 VG96 1026 A14 VG96 1030 L4 VG96 1031 3 L5 K5 G3 G1 N N BANK 3 BANK 3 62 860 62 840 N N BANK 3 BANK 3 61 467 61 456 VG96 1033 VG96 1034 N N BANK 3 BANK 3 62 236 62 210 E3 E1 N N BANK 3 BANK 3 65 015 65 008 C15 VG96 1035 C14 VG96 1032 A16 VG96 1036 L7 B16 VG96 1037 K6 s N N BANK 3 BANK 3 64 049 63 853 BANK 3 BANK 3 67 057 67 031 62 885 62 926 USBS6 C1030 5510 http www cesys com User Doc VO 3 63 preliminary Etch Length mm 63 426 64 103 64 144 VG96 1047 H7 P BANK 3 63 630 A20 IN m vosos amp e m Banks em vossos vs n n Banks VG96 1050 F5 N BANK 3 A24 VG96 1057 IN OUT BANK 0 63 585 VG96 1058 C6 N IN OUT BANK 0 63 540 VG96 1059 F7 c23 vGo6 1056 Eb A25 VG96 1060 E7 60 899 60 885 56 002 55 884 64 148 64 134 IN OUT IN OUT IN OUT BANK 0 BANK 0 BANK 0 60 224 N 60 128 71 834 B25 VG96 1061 E8 N IN OUT BANK 0 71 637 A26 VG96 1063 IN OUT BANK 0 69 596 B26 VG96 1064 C9 N IN OUT BANK 0 69 497 IN OUT IN O
14. Sink On Chip Bus Protocol Engine Slave FIFO idc d Connectors LEDs User Flash Deas Hex Enc B3 1 Multi l O Figure 8 WISHBONE system overview Files and modules src wishbone pkg vhd A package containing datatypes constants and components needed for the WISHBONE system There are VHDL subroutines for a WISHBONE master bus functional model USBS6 C1030 5510 http www cesys com User Doc V0 3 21 preliminary BFM too These can be used for behavioral simulation purposes src usbs6 soc top vhd This is the top level entity of the design The WISHBONE components are instantiated here src wb intercon vhd All WISHBONE devices are connected to this shared bus interconnection logic Some MSBs of the address are used to select the appropriate slave src wb ma fx2 vhd This is the entity of the WISHBONE master which converts the CESYS USB protocol into one or more 32 Bit single read write WISHBONE cycles The low level FX 2 slave FIFO controller fx2 slfifo ctrl vhd is used and 16 32 bit data width conversion is done by using special FIFOs sfifo hd a1Kx18b0K5x36 vhQq src wb sl bram vhd A internal BlockRAM is instantiated here and simply connected to the WISHBONE architecture It can be used for testing address oriented data transactions over USB src wb sl gpio vhd This entity provides up to 256 general purpose l Os to set and monitor non timin
15. coding style API Error handling Error handling is offered very different While both C and NET API use exception handling the C API uses a classical return code error inquiry scheme C and NET API UDK API code should be embedded inside a try branch and exceptions of type ceException must be caught If an exception is raised the generated exception object offers methods to get detailed information about the error C API All UDK C API functions return either CE SUCCESS or CE FAILED If the latter is returned the functions below should be invoked to get the details of the error USBS6 C1030 5510 http www cesys com User Doc V0 3 38 preliminary Methods Functions GetLastErrorCode API Code C unsigned int ceException GetErrorCode C unsigned int GetLastErrorCode NET uint ceException GetLastErrorCode Returns an error code which is intended to group the error into different kinds It can be one of the following constants Error code Kind of error ceE TIMEOUT Errors with any kind of timeout ceE IO ERROR IO errors of any kind file hardware etc ceE UNEXP HW BEH Unexpected behavior of underlying hardware no response wrong data ceE PARAM Errors related to wrong call parameters NULL pointers ceE RESOURCE Resource problem wrong file format missing dependency ceE API Undefined behavior of underlying API ceE ORDER Wrong ord
16. data transfers Maybe it is necessary to fill up endpoint buffer with dummy data if some kind of host timeout condition has to be met Another FX 2 data transfer mechanism is called GPIF General Programmable InterFace mode The GPIF engine inside the FX 2 acts as a master to endpoint buffers transferring data and presenting configurable handshake waveforms to external hardware CESYS USB card supports slave FIFO mode for data communication only GPIF mode is exclusively used for downloading configuration bitstreams to FPGA Clocking FPGA designs The 48 MHz SYSCLK oscillator is an onboard clock source for the FPGA It is used as interface clock IFCLK between FX 2 slave FIFO bus and FPGA l Os So this clock source must be used for data transfers to and from FPGA over USB Appropriate timing constraints can be found in ucf files of design examples included in delivery It is strictly recommended to use a single clock domain whenever possible Using a fully synchronous system architecture often results in smaller less complex and more performant FPGA designs compare Xilinx white paper WP331 Timing Closure Coding Guidelines USBS6 C1030 5510 http www cesys com User Doc V0 3 17 preliminary In FPGA designs with multiple clock domains asynchronous FIFOs have to be used for transferring data from one clock domain to the other and comprehensive control signals have to be resynchronized Other clock sources can b
17. disabled during power down and self refresh modes MCB1 RZQ N14 Input termination calibration pin used with the soft calibration module External 100 Ohm resistor to GND MCB1 ZIO No connect signal used with the soft calibration module to calibrate the input termination value MCB1 CK G16 Clock CK is the system clock input CK and CK are differential clock inputs All address and control input signals are sampled on the MCB1 CK n C18 crossing of the positive edge of CK and the negative edge of CK ndi Input and output data is referenced to the crossing of CK and CK both directions of the crossing MCB1 DQ3 L18 EUM Data input output Lower Byte Data bus MCB1 LDQS K17 Data strobe for Lower Byte Data bus Output with read data input with write data DQS is edge aligned with read data center aligned in write data It is used to capture data MCB1 LDM L16 Input data mask DM is an input mask signal for write data Input data is masked when DM is sampled HIGH along with that input data MCB1 UDM during a WRITE access DM is sampled on both edges of DQS MCB1 DQ8 Data input output Upper Byte Data bus MCB4 DQ10 MCB1 DQ11 USBS6 C1030 5510 http www cesys com User Doc V0 3 10 preliminary LPDDR SDRAM MT46H64M16LFCK 5 Somme FPGAIO Com U y O MCB1 DQ15 MCB1 UDQS N15 Data strobe for Upper Byte Data bus Output with read data input with write data DQS is edge aligned with read data center aligned in wri
18. given time The following sections will give you a brief introduction about the data transfer from and to the FPGA over the Cypress FX 2 USB peripheral controller s slave FIFO interface the WISHBONE interconnection architecture and the provided peripheral controllers CESYS USB cards use only slave FIFO mode for transferring data For further information about the FX 2 slave FIFO mode see Cypress FX 2 user manual and datasheet and about the WISHBONE architecture see specification B 3 wbspec b3 pdf FPGA source code copyright information This source code is copyrighted by CESYS GmbH GERMANY unless otherwise noted FPGA source code license THIS SOURCECODE IS NOT FREE IT IS FOR USE TOGETHER WITH THE CESYS PRODUCTS ONLY YOU ARE NOT ALLOWED TO MODIFY AND DISTRIBUTE OR USE IT WITH ANY OTHER HARDWARE SOFTWARE OR ANY OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC DESIGN WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT HOLDER Disclaimer of warranty THIS SOURCECODE IS DISTRIBUTED IN THE HOPE THAT IT WILL BE USEFUL BUT THERE IS NO WARRANTY OR SUPPORT FOR THIS SOURCECODE THE COPYRIGHT HOLDER PROVIDES THIS SOURCECODE AS IS WITHOUT WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THIS SOURCECODE I WITH YOU SHOULD THIS SOURCECODE PROVE DEFECTIVE YOU ASSUME THE COST OF ALL NECES
19. is build of a FPGA BlockRAM src flash ctrl vhd The low level FLASH controller for SPI FLASH memory It supports reading and writing of four bytes of data at one time as well as erasing the whole memory usbs6 soc xise Project file for Xilinx ISE usbs6 soc ucf User constraint file with timing and pinout constraints usbs6 soc fpga consts h C header file extracted from VHDL packages It contains address flag bitfield and value definitions for FPGA design access integration into host software application Software Pseudo Code Example include usbs6 soc fpga consts h address of UART status and configuration register uint32 t uiRegAddr UART BASEADR UART STACFG OFFSET read modify write register value for 9600 baud uint32 t uiRegVal ReadRegister uiRegAddr amp UART STACFG BDR FIELD uiRegVal UART STACFG BDR FIELD amp UART STACFG BDR VAL 9600 lt lt UART STACFG BDR FIELD POS setting UART baud rate WriteRegister uiRegAddr uiRegVal WISHBONE transactions The software API functions ReadRegister WriteRegister lead to one and ReadBlock WriteBlock to several consecutive WISHBONE single cycles Bursting is not allowed in the WISHBONE demo application The address can be USBS6 C1030 5510 http www cesys com User Doc V0 3 25 preliminary incremented automatically in block transfers You can find details on enabling disabling the burst mode and address a
20. just add new ones or does nothing even if a USB device is removed For a clean detection of a device removal calling Delnit Init and Enumerate in exactly that order will build a new clean device list but invalidates all previous created device pointers and handles To identify devices in a unique way each device gets a UID which is a combination of device type name and connection point so even after a complete cleanup and new enumeration devices can be exactly identified by this value Methods Functions Init API Code C static void ceDevice Init C CE RESULT Init NET static void ceDevice Init Prepare internal structures must be the first call to the UDK API Can be called after invoking Delnit again see top of this section Delnit API Code C static void ceDevice Delnit C CE RESULT Delnit NET static void ceDevice Delnit Free up all internal allocated data there must no subsequent call to the UDK API after this call except Init is called again All retrieved device pointers and handles are invalid after this point USBS6 C1030 5510 http www cesys com User Doc V0 3 40 preliminary Enumerate API Code C static void ceDevice Enumerate ceDevice ceDeviceType DeviceType C CE RESULT Enumerate unsigned int Device Type NET static void ceDevice Enumerate ceDevice ceDeviceType DeviceType Search for ne
21. levels Do not forget to also enable FPGA power up With XILINX parallel cable IV the led lights green if FPGA is powered on Before starting to download a design to SPI Flash with iMPACT programming software it is necessary to prepare the required mcs SPI PROM file With xapp951 XILINX provides an application note how to accomplish that using iMPACT or PROMGen software tools Select 16M SPI PROM Density when asked Now programming of the SPI Flash can be started by clicking Direct SPI Configuration from within IMPACT Follow the manual provided by XILINX in xapp951 Select M25P16 SPI Flash PROM Type when asked USBS6 C1030 5510 User Doc V0 3 61 http www cesys com preliminary IO pairing and etch length report J3 VG 96 pin connector Differential pairs 28 IN 12 IN OUT m vem uz P WN em Fm voir wi n W em Ca vem x 5 W eme Fes ve T w n em Ca vossos r e mw Banks Cr wem w e Fer vemgon w N Cw vex m n BANK Cw veers e e n Banks Bro vem m 60 667 60 664 57 362 57 362 59 397 59 394 BANK 3 BANK 3 59 131 59 129 BANK 3 BANK 3 59 244 59 232 58 301 58 299 58 238 58 236 BANK 3 BANK 3 59 802 59 761 BANK 3 BANK 3 55 682 55 680 IN IN IN IN NIE BN USBS6 C1030 5510 http www cesys com User Doc VO 3 62 preliminary PIN Netname FPGAIO FPGABANK Etch
22. like the PCIS3Base require the following driver sudo PLX SDK DIR pwd Bin Plx load 9056 PCle based boards like the PCleV4Base require the following sudo PLX SDK DIR pwd Bin Plx load 8311 Automation of this load process is out of the scope of this document Build UDK Prerequisites The whole UDK will be build using CMake a free cross platform build tool It creates dynamic Makefiles on unix compatible platforms The first thing should be editing the little configuration file linux cmake inside the installation root of the UDK It contains the following options BUILD UI TOOLS If 0 UDKLab isn t build if 7 UDKLab is part of the build but requires a compatible wxWidgets installation CMAKE BUILD TYPE Select build type can be one of Debug Release RelWithDebInfo MinSizeRel If there should be at least 2 builds in parallel remove this line and specify the type using command line option DCMAKE BUILD TYPE Makefile creation and build Best usage is to create an empty build directory and run cmake inside of it cd udkapi2 0 mkdir build cd build cmake If all external dependencies are met this will finish creating a Makefile To build the UDK just invoke make make Important The UDK C API must be build with the same toolchain and build flags like USBS6 C1030 5510 http www cesys com User Doc V0 3 35 preliminary the application that uses it Otherwise unw
23. to or from devices or catching interrupts PCI devices must be accessed which is done by calling Open All calls in this section require an open device which must be freed by calling Close after usage Either way after calling Open the device is ready for communication As of the fact that Cesys devices usually have an FPGA on the device side of the bus the FPGA must be made ready for usage If this isn t done by loading contents from the on board flash not all devices have one a design must be loaded by calling one of the ProgramFPGA calls These call internally reset the FPGA after design download From now on data can be transferred Important All data transfer is based on a 32 bit bus system which must be implemented inside the FPGA design PCI devices support this natively while USB devices use a protocol which is implemented by Cesys and sits on top of a stable bulk transfer implementation Methods Functions Open API Code C void ceDevice Open C CE RESULT Open CE DEVICE HANDLE Handle NET __ void ceDevice Open Gain access to the specific device Calling one of the other functions in this section require a successful call to Open Notice If two or more applications try to open one device PCI and USB devices behave a bit different For USB devices Open causes an error if the device is already in use PCI allows opening one device from multiple processes As PCI drivers are n
24. 30 00 80 01 00 00 00 01 00200048 30 00 40 00 50 01 14 Sa 00000000 Read ne F E Figure 17 Content panel USBS6 C1030 5510 http www cesys com User Doc V0 3 57 preliminary Register entry A register entry can be used to communicate with a 32 bit register inside the FPGA In UDKLab a register consists of the following values Address Name Info text The visual representation of one register can be seen in the following image GPIO BankO gt 0x00 100000 fe Hex 00000000 Dec O e D Read write Auto 2 P Hi Lo Figure 18 Register panel The left buttons are responsible for adding new entries move the entry up or down and removing the current entry all are self explanatory The header shows it s mapping name as well as the 32 bit address The question mark in the lower right will show a tooltip if the mouse is above it which is just a little help for users Both input fields can be used to write in a new value either hex or decimal or contain the values if they are read from FPGA design The checkboxes represent one bit of the current value Clicking the Read button will read the current value from FPGA and update both text boxes a
25. 7 je os veseioss ca Fr veseiosb ws re vess 1054 625 rs veseioss ozs es ean wap ew ew je oo as E vewiosr 621 vs vexios cm Fa ves1o8 ao Hr vesom 820 cs veseios c20 rs Tena mw vese 1045 eta Ha vos cio y vess 1047 mal He vese 042 616 Taan css e vess tom 17 vese 1036 ete s vessiosr fere ws vesslous ais 15 vess 1039 ers e vess 1084 Jers es ves 1035 mal 14 ves 1020 Jere 1s vase 10st ora er vess 1032 mal c2 vase 1027 era 61 vexom ers cs Tena aa 02 vese 024 Bia 01 veso fora 61 vees 1025 am re ves 021 mi Fi vesio Jen s vesiom ato ne vase iow Bio Ha ves ora fero v1 eae ho ke vemos eo Kr vase ore co iz vesio as uz ves 012 es ur aaas os m Yen USBS6 C1030 5510 http www cesys com User Doc VO 3 14 preliminary J3 VG 96 pin external expansion connector G ras P2 vemos ss er vemior ce w vese 108 L vemos ss m vemos Tal vastos m u2 vewio mew voso es Pe vee 102 m veco m we e eean 2 GND B2 cn cr cn m sover et sovext jei sovex tok o OS GCLK Figure 6 IDC 2x25 Pin external expansion connector J4 J4 IDC 2x25 Pin external expansion connector salma Comment Pm reGAIo Comment Gl v cio s ow sle oo a CDOT slo ox s
26. C6SLX16 Device is supported by the free Xilinx ISE Webpack development software You will have to change some options of the project properties for own applications A bitstream in the bin format is needed if you want to download your FPGA design with the CESYS software API functions LoadBIN and ProgramFPGA The generation of this file is disabled by default in the Xilinx ISE development environment Check create binary configuration file at right click generate programming file gt properties gt general options sd Process Properties E3 Category General Options Configuration Options Startup Options Readback Options Property Name Value Run Design Rules Checker DRC Create Bit File Create ASCII Configuration File L1 Create IEEE 1532 Configuration File L1 Enable BitStream Compression L1 Enable Debugging of Serial Mode BitStream Enable Cyclic Redundancy Checking CRC Property display level Standard w Figure 7 ISE Generate Programming File Properties Gen Opt USBS6 C1030 5510 http www cesys com User Doc V0 3 19 preliminary After ProgramFPGA is called and the FPGA design is completely downloaded the pin RESET note the prefix means that the signal is active low is automatically pulsed HIGH LOW HIGH This signal can be used for resetting the FPGA design The API function ResetFPGA can be called to initiate a pulse on RESET at a user
27. Example of a VHDL simulation testbench demonstrating BFM techniques for accessing BlockRAM as a WISHBONE slave device wb sl bram vhd src fx2 slfifo ctrl vhd See chapter Design usbs6 soc src sync fifo vhd See chapter Design usbs6 soc usbs6 bram xise Project file for Xilinx ISE usbs6 bram ucf User constraint file with timing and pinout constraints wb sl bram tb do ModelSim command macro file for BFM BlockRAM testbench wb sl bram tb vhd USBS6 C1030 5510 http www cesys com User Doc V0 3 28 preliminary wb sl bram tb cmd Win32 batch file automatically starting ModelSim with example testbench and appropriate simulation script wb sl bram tb do Just doubleclick for running the demo USBS6 C1030 5510 http www cesys com User Doc V0 3 29 preliminary Software Introduction The UDK Unified Development Kit is used to allow developers to communicate with Cesys s USB and PCl e devices Older releases were just a release of USB and PCI drivers plus API combined with some shared code components The latest UDK combines all components into one single C project and offers interfaces to C C and for NET Windows only The API has functions to mask able enumeration unique device identification runtime FPGA programming and 32bit bus based data communication PCI devices have additional support for interrupts Changes to previous versions Beginning with release 2 0 the UDK API is a truly combin
28. FT232R External expansion connectors On connectors J3 and J4 up to 115 general purpose FPGA IO are accessible Bank 0 and Bank 3 of the FPGA are configured for 3 3V signaling level Differential IO standards as for example LVDS are supported too Detail information about IO pairing is available in paragraph IO pairing and etch length report of chapter D 10 on connectors J3 and J4 are directly connected to FPGA IO and therefore are only 3 3 Volt tolerant NEVER apply voltages outside the interval 0 95V 4 1V as this may lead to severe damage of FPGA and attached components For more information regarding DC and switching characteristics of Spartan 6 FPGA please consult documentation DS160 on XILINXTM website USBS6 C1030 5510 http www cesys com User Doc VO 3 13 preliminary l ynunuebrubrbpuocpuudgococadaaadguadugaaucducd cducucuctc p que CE T M M Ka Ka M M ELEME E ELE E PE ELE GE map MK K MC MG QW QG MK G GM Md JJJ TN Figure 5 VG 96 pin external expansion connector J3 J3 VG 96 pin external expansion connector FPGA Comment FPGA Comment FPGA Comment IO E ES A32 GND O enD ex maol Fra voo iors emer voo ore eso Frt verior ass ort voorz ez on voe ors Tea En voeon nas ort vese 1089 eas Fio voos 1079 ez G8 Vena 26 09 vase 1060 826 co vees lost cze be vess 1065 wes Er vee 1050 625 Es veseios css Taa maa os vase 105
29. FileName Program the FPGA with the Xilinx tools bin file indicated by the filename parameter Calls ResetFPGA subsequently ProgramFPGAFromMemory API Code C void ceDevice ProgramFPGAFromMemory const unsigned char pszData unsigned int uiSize C CE RESULT ProgramFPGAFromMemory CE DEVICE HANDLE Handle const unsigned char pszData unsigned int uiSize NET void ceDevice ProgramFPGAFromMemory byte Data uint Size Program FPGA with a given array created with UDKLab This was previously done using fpgaconv ProgramFPGAFromMemoryZ API Code C void ceDevice ProgramFPGAFromMemoryZ const unsigned char pszData unsigned int uiSize C CE RESULT ProgramFPGAFromMemoryZ CE DEVICE HANDLE Handle const unsigned char pszData unsigned int uiSize NET void ceDevice ProgramFPGAFromMemoryZ byte Data uint Size Same as ProgramFPGAFromMemory except the design data is compressed SetTimeOut API Code C void ceDevice SetTimeOut unsigned int uiTimeOutMS C CE RESULT SetTimeOut CE DEVICE HANDLE Handle unsigned int uiTimeOutMS NET void ceDevice SetTimeOut uint uiTimeOutMS USBS6 C1030 5510 User Doc V0 3 48 http www cesys com preliminary Set the timeout in milliseconds for data transfers If a transfer is not completed inside this timeframe the API generates a timeout error EnableBurst API Code C v
30. Oscillators 5 user LEDs UART DIP switch Figure 1 USBS6 Block Diagram Spartan 6 FPGA XC6SLX16 2CSG324C FPGA features Logic cells 14 579 Configurable logic blocks Slices Flip Flops 2 278 18 224 Max distributed RAM kb 136 DSP Slices 136 Block RAM Blocks 18kB Max kb 32 576 CMTs 2 For details of the SPARTAN 6 FPGA device please look at the data sheet at http www xilinx com support documentation data_sheets ds160 pdf USBS6 C1030 5510 http www cesys com User Doc V0 3 4 preliminary 7eeeecceeceoeocoeocoecoeooococococcccocococoocococooo 5 6666666 6666666666666 66666 6666 6 6 5 6666666666666 666666666 666666 ee SI 6 6666666666666666 6 6 6 6 6 6 6 6 6 e 5 eeecccc c 0 000000000000000 Ea le o ek R E Eee le e D18 Gia le oe nl ws ER NN oe na ta F15 m 618 KIS 017 F16 EB XILINX FPGA H17 I6 br ua m mu TT SPARTAN 6 m PCPR mm Mm Mila L18 KT P16 M13 E 4 m we um ms a 2 R See oo au gue a My us Wi xd EERE RRR n HE LI am s N E wssssEENSSESESESEE 2 Wm NW sean O um 3 _ BR 05 0 80 08 8 02 08 0818 85 koo A uS a 7 turma s ana EDGE vT o Se m AM wm uw am me RRR TTT gl d ELE a l PENNE o EA wa E BREE B E EE xc 0 eee gu CYPRESS FX 2 A M a g E r3 e T1 Ras HHRHH mma 8 mii ii L t G oa Ipsi gp gru
31. SARY SERVICING REPAIR OR CORRECTION IN NO EVENT WILL THE COPYRIGHT HOLDER BE LIABLE TO YOU FOR DAMAGES INCLUDING ANY GENERAL SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THIS SOURCECODE INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THIS SOURCECODE TO OPERATE WITH ANY OTHER SOFTWARE PROGRAMS USBS6 C1030 5510 http www cesys com User Doc V0 3 20 preliminary HARDWARE CIRCUITS OR ANY OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC DESIGN EVEN IF THE COPYRIGHT HOLDER HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Design usbs6 soc An on chip bus system is implemented in this design The VHDL source code shows you how to build a 32 Bit WISHBONE based shared bus architecture All devices of the WISHBONE system support only SINGLE READ WRITE Cycles Files and modules having something to do with the WISHBONE system are labeled with the prefix wb The WISHBONE master is labeled with the additional prefix ma and the slaves are labeled with sl There is a package for each module with the additional postfix pkg It contains the appropriate VHDL component declaration interface description as well as public constants like register address offsets 32 Bit SoC UART BRAM Xilinx SIO Macros sr E INTERCONNECTION E GPIO Universal Data Source
32. USB cable or via external 5V power supply With XILINX parallel cable IV the led lights green if FPGA is powered on Now start XILINX iMPACT select Boundary Scan mode and follow the manual provided by XILINX in xapp951 Select M25P16 SPI Flash PROM Type when asked SPI Flash M25P16 Signal Name FPGA IO FPGA Direction Comment D MOSI T13 Output Master SPI Serial Data Output Q MISO R13 Input Master SPI Serial Data Input S CSO B V3 Output Master SPI Chip Select Output C CCLK R15 Output Configuration Clock W WP Externally pulled HIGH via 4 7kOhm resistor HOLD HOLD Externally pulled HIGH via 4 7kOhm resistor SPI Flash Direct Programming using iMPACT Out of the box Direct SPI Programming via XILINX download cable and iMPACT USBS6 C1030 5510 http www cesys com User Doc V0 3 60 preliminary programming software is not supported But with the help of some tiny FPGA design which only has to bypass SPI signals to external IO pins on connectors J3 or J4 it is possible to access all needed SPI Flash pins Connect JTAG adapter to external IO pins as described in the following chart SPI Flash Direct Programming necessary connections to JTAG cable M25P16 FPGA Connection JTAG Signal Name D MOSI TDI Q DIN TDO S CSO B TMS C CCLK TCK VCC VCCO_IO VREF GND GND GND Make sure that VCCO IO is configured for 3 3V signaling
33. USBS6 User Manual C1030 5510 CESYS V 0 3 June 29 2010 SPARTAN 6 FPGA board with USB2 0 SPI Flash and JTAG interface Order number C1030 5510 e 25 060622202222202222202222220222202295 5 6 6666 66 666 6 6 66 6 6 6 66 6 oo eo LU B sak LUR HH G LR cis ns 888 88 m ns G14 A ka r m us m FERRE cm Wis us nus B as mm m m EB ne XILINX FPGA wm J eu de Pia K SPARTAN 6 m ml POOR m gp lia L18 KIT P16 M13 E ma Ie iei Wii M ane a 2 SERRE es oe w MB a ow wy nm deg sssausssscrm LI e EE z E emm tal PUMA es s amp amp 8 8 8 8 8 688 8 8 8 8 8 ee RR N Tee Tes Elo Toe e j OOOO OCT ee E B Tuse e CER Hd 3 3V GND Ax sssHESSEEE S E E 8 F B l Wi EH o Q4 DOGMA ni cp E E ud RI Pa nd dl Er i 6 EE at e K n T REGS uw USB2 0 ET 2 eYPRESSFX 2 ld E am tae sd genis sp e puo mao ima d p su ay Te eu Zo u ee atc qo 0 e us em 8 oo 22 S Sie sle vBRHHR cos da e e 05 o L e s DH eee TAS USBS6 C1030 5510 User Doc V0 3 http www cesys com preliminary Copyright information Copyright O 2010 CESYS GmbH All Rights Reserved The information in this document is proprietary to CESYS GmbH No part of this document may be reproduced in any form or by any means or used to make derivative work such as translation transformation or adaptation without written permission from CESYS GmbH
34. UT IN OUT BANK 0 N IN OUT BANK 0 BANK 0 BANK 0 63 074 63 051 VG96 1065 C25 VG96 1062 C8 VG96 1066 G9 VG96 1067 F9 N 74 749 74 696 USBS6 C1030 5510 http www cesys com User Doc VO 3 64 preliminary PIN Netname FPGAIO PIN Direction FPGABANK Etch Length mm mas vemos on Pe nour mao C28 VG96 IO71 G8 C27 VG96 1068 F8 IN OUT A29 VG96 1072 IN OUT BANK 0 B29 VG96 1075 N IN OUT BANK 0 VG96 1075 IN OUT BANK 0 B30 VG96 1076 N IN OUT BANK 0 VG96 1077 IN OUT BANK 0 VG96 1074 N IN OUT BANK 0 VG96 1078 IN OUT BANK 0 B31 VG9 1079 N IN OUT BANK 0 J4 IDC 50 pin connector Differential pairs 17 IN OUT Direction FPGABANK Etch Length mm 73 791 73 594 IN OUT BANK 0 BANK 0 69 296 N 69 246 72 405 72 379 74 452 74 253 68 952 68 755 75 068 74 871 PIN Netname FPGAIO PIN s 0 cs P mour sako sose a o s w wrour sanko sous s we e P iow ako 2006 e o ar n wrour sanko 250 Ls 1o s e nor cao tem n mo s e wrour panko sam USBS6 C1030 5510 http www cesys com User Doc VO 3 65 preliminary ADDIO B4 P IN OUT BANK 0 19 754 ADD IO N IN OUT BANK 0 19 743 A16 e IN OUT BANK 0 20 143 ADD IO A6 N IN OUT BANK 0 20 131 19 ADDO IN OUT BANK 0 20 421 20 ADD IO N IN OUT BANK 0 20 394 21 ADDIO B9
35. above installation called in same directory sudo make remove The configuration file etc modprobe d ceusbuni conf offers two simple options Read the comments in the file Enable kernel module debugging Choose between firmware which automatically powers board peripherals or not Changing these options require a module reload to take affect PCI The PCI drivers are not created or maintained by Cesys they are offered by the manufacturer of the PCI bridges that were used on Cesys PCl e boards So problems regarding them can t be handled or supported by us Important If building PlxSdk components generate the following error warning bin sh not found Here s a workaround The problem is Ubuntu s default usage of dash as sh which can t handle command lL Replacing dash with bash is accomplished by the following commands that must be done as root sudo rm bin sh sudo ln s bin bash bin sh Installation explained in detail PIxSdk decompression cd udkapi2 0 drivers linux tar xvf PlxSdk tar USBS6 C1030 5510 http www cesys com User Doc V0 3 34 preliminary Build drivers cd PlxSdk Linux Driver PLX SDK DIR pwd buildalldrivers Loading the driver manually requires a successful build it is done using the following commands cd udkapi2 0 drivers linux PlxSdk sudo PLX SDK DIR pwd Bin Plx load Svc PCI based boards
36. alog USBS6 C1030 5510 http www cesys com User Doc V0 3 53 preliminary FPGA design flashing This option stores a design into the flash component on devices that have support for it The design is loaded to the FPGA after device power on without host intervention How and under which circumstances this is done can be found in the hardware description of the corresponding device The following screen shows the required actions for flashing Le Tenes a Choose device e Select flash device e Choose FPGA design for flashing o Close dialog after flashing has finished 9 O Alternatively the flash can be erased On USB4VF devices one of two areas can be chosen Stage Figure 14 Flash design to device Projects Device communication is placed into a small project management This reduces the actions from session to session and can be used for simple service tasks too A projects stores the following information Device type it is intended to Initializing sequence Register list Data area list Projects are handled like files in usual applications they can be loaded saved new USBS6 C1030 5510 http www cesys com User Doc V0 3 54 preliminary projects can be created Only one project can be active in one session Initializing sequence The initializing sequence is a list of actions that must be executed in order to work with the FPGA on the device T
37. anted side effects in exception handling will occur See example in Add project to UDK build USBS6 C1030 5510 http www cesys com User Doc V0 3 36 preliminary Use APIs in own projects C API Include file udkapi h Library file e Windows udkapi vc ver arch lib ver is 8 9 10 arch is x86 or amd64 resides in lib build Linux libusbapi so resides in ib Namespace ceUDK As this API uses exceptions for error handling it is really important to use the same compiler and build settings which are used to build the API itself Otherwise exception based stack unwinding may cause undefined side effects which are really hard to fix Add project to UDK build A simple example would be the following Let s assume there s a source file mytest mytest cpp inside UDK s root installation To build a mytestexe executable with UDK components those lines must be appended add executable mytestexe mytest mytest cpp target link libraries mytestexe UDKAPI LIBNAME Rebuilding the UDK with these entries in Visual Studio will create a new project inside the solution and request a solution reload On Linux calling make will just include mytestexe into the build process C API Include file udkapic h Library file e Windows udkapic voc ver arch lib ver is 8 9 10 arch is x86 or amd64 resides in lib build Linux libusbapic so resides in ib Namespace Not applicable The
38. apter for one port of Spartan 6 build in multiport memory controller block MCB src wb sl uart vhd This entity is a simple UART transceiver with 16 byte buffer for each direction connected to USB2UART interface Xilinx UART transceiver macros are used as physical layer Baudrate is adjustable up to 230400 default 9600 by writing appropriate timer prescaling values to the status and configuration register This register contains buffer level flags FULL and HALFFULL for each direction too Data format is fixed at 8 N 1 Reading from UART pipe is always non blocking A data present flag provided along with received bytes indicates if current RX value is valid Writing to UART pipe is blocking if TX buffer gets full So that loss of transmitted data can easily be avoided src xil uart macro This directory contains VHDL source code files of Xilinx UART transceiver macros Note that these source code files are copyrighted by Xilinx and are absolutely not supported by CESYS For details on these macros see the application note XAPP223 200 MHz UART with Internal 16 Byte Buffer provided by Xilinx src xil mcb mig This directory contains VHDL source code files generated by Xilinx memory interface generator tool to build the frontend for MCB File memc1 infrastructure vhd has been modified to fit example design requirements src fx2 slfifo ctrl vhd This controller handles 512 byte aligned raw USB bulk transfers with
39. are easier to meet USBS6 C1030 5510 http www cesys com User Doc V0 3 26 preliminary Basic WISHBONE cycle ck rii rir STB TT O WE ZX XUZ Master ADR ZIK X 7 77 DAT DA I DAT s VITIIFITETHITT AO X s ave ACK fh Figure 10 WISHBONE transactions with WriteRegister WriteBlock ReadRegister ReadBlock The WISHBONE signals in these illustrations and explanations are shown as simple bit types or bit vector types but in the VHDL code these signals could be encapsulated in extended data types like arrays or records Example port map ACK I gt intercon masters slave 2 ack Port ACK lis connected to signal ack of element 2 of array slave of record masters of record intercon Design usbs6 bram This design is intended to demonstrate behavior of UDK software API resulting in USBS6 C1030 5510 http www cesys com User Doc VO 3 27 preliminary WISHBONE cycles It is a reduced version of usbs6 soc example implementing a single BlockRAM slave Files and modules src wishbone pkg vhd See chapter Design usbs6 soc src usbs6 bram top vhd This is the top level module It instantiates FX 2 module as a WISHBONE master device wb ma fx2 vhd and a BIockRAM as a WISHBONE slave device wb sl bram vhd src wb ma fx2 vhd See chapter Design usbs6 soc src wb sl bram vhd See chapter Design usbs6 soc src sim tb wb sl bram tb vhd
40. ate FPGA IO to a HIGH level wm CO JO Figure 4 Bitte durch Orginalbild ersetzen LEDs Signal Name FPGAIO Comment SYS LEDO E Internal 5V power supply SYS LED1 E Power OK signal from onboard voltage regulator SYS LED2 V17 Illuminates to indicate the status of the DONE pin if FPGA is successfully configured USER LEDO User configurable LED USER LED1 User configurable LED USER LED2 User configurable LED USER LED3 User configurable LED USER LED4 User configurable LED The HEX rotary DIP switch is of binary coded type The four weighted terminals are externally pulled HIGH with 4 7 kOhm resistors the common terminals are connected to GND Therefore the four FPGA inputs behave like a complementary binary coded hexadecimal switch HEX rotary DIP switch DIAL FPGA Pin N8 FPGAPinM11 FPGA Pin M10 FPGA Pin N9 Poo 1 1 1 1 E E E ee o E E O RE NEN o Ee Ee a NEN ee a ae ee ee USBS6 C1030 5510 http www cesys com User Doc V0 3 12 preliminary HEX rotary DIP switch FPGA Pin N9 FT232R from FTDI is a USB to serial UART interface USB to serial UART interface EE FTDI TXD FPGAIN Transmit asynchronous data output for FT232R FTDI RTS n FTDI CTS n FTDI RESET n FPGAIN Request to send control output for FT232R FPGA OUT Clear to send control input for FT232R FPGA OUT Active low reset pin for FT232R FTDI RXD FPGA OUT Receiving asynchronous data input for
41. e selected by either double clicking on it or choosing OK Important Opening the device selector again will internally re initialize the underlying API So active communication is stopped and the right panel is disabled again more on the state of this panel below USBS6 C1030 5510 http www cesys com User Doc V0 3 52 preliminary After a device has been selected most UI components are available FPGA configuration FPGA design flashing if device has support Project controls Initializer controls Related to projects The last disabled component at this point is the content panel It is enabled if the initialization sequence has been run The complete flow to enable all Ul elements can be seen below Block RAM CD Select device t e Load project modify initialize sequence e Run the initialization sequence a x A o After completion this panel will be enabled 0x00000100 gt uxuuuu iuu a Hex 00000000 X e cO S pes Flash Contents gt 0x00200000 l e s GPIO BankO gt 0x00100000 00000000 t X e E 4 GPIO OE Bank1 gt 0x00 19000 IHE s s GPIO Bank1 gt 0x00100004 M Figure 13 Prepare to work with device FPGA configuration Choosing this will pop up a file selection dialog allowing to choose the design for download If the file choosing isn t canceled the design will be downloaded subsequent to closing the di
42. e a variable length of up to 512 bytes per packet Packet size is fixed to the maximum value of 512 bytes for data communication with CESYS USB cards to achieve highest possible data throughput USB peripherals could have several logical channels to the host The data source sink for each channel inside the USB peripheral is called the USB endpoint Each endpoint can be configured as IN channel direction peripheral gt host or OUT endpoint channel direction host gt peripheral from host side perspective CESYS USB cards support two endpoints one for each direction FX 2 has an integrated USB SIE Serial Interface Engine handling USB protocol and transferring user payload data to the appropriate endpoint So end users do not have to care about USB protocol in their own applications FX 2 endpoints are realized as 2 kB buffers These buffers can be accessed over a FIFO like interface with a 16 bit tristate data bus by external hardware External hardware acts as a master polling FIFO flags applying read and write strobes and transferring data Therefore this FX 2 data transfer mechanism is called slave FIFO mode As already mentioned all data is transferred in multiples of 512 bytes External hardware has to ensure that the data written to IN endpoint is aligned to this value so that data will be transmitted from endpoint buffer to host The 512 byte alignment normally causes no restrictions in data streaming applications with endless
43. e added internally by using Spartan 6 onchip digital clock managers DCMs or PLLs or externally by connecting clock sources to other FPGA global clock inputs A wide range of clock frequencies can be synthesized with DCMs and PLLs For further details on DCMs PLLs please see Spartan 6 FPGA Clocking Resources User Guide UG382 FX 2 FPGA slave FIFO connection Only the logical behavior of slave FIFO interface is discussed here For information about the timing behavior like setup and hold times please see FX 2 datasheet All flags and control signals are active low postfix The whole interface is synchronous to IFCLK The asynchronous FIFO transfer mode is not supported SLWR E FX 2 input FIFO write strobe SLRD FX 2 input FIFO read strobe SLOE FX 2 input output enable activates FX 2 data bus drivers PKTEND FX 2 input packet end control signal causes FX 2 to send data to host at once ignoring 512 byte alignment so called short packet Short packets sometimes lead to unpredictable behavior at host side So CESYS USB cards do not support short packets This signal has to be statically set to HIGH Dummy data should be added instead of creating short packets There is normally no lack of performance by doing this because transmission of USB packets is bound to a time framing scheme regardless of amount of payload data FIFOADR 1 0 FX 2 input endpoint buffer addresses CESYS USB cards use only two endpoints EP2
44. ed int puiRaised NET bool ceDevice WaitForlnterrupt uint uiTimeOutMS PCI only Check if the interrupt is raised by the FPGA design If this is done in the time specified by the timeout the function returns immediately flagging the interrupt is raised return code puiRaised Otherwise the function returns after the timeout without signaling Important If an interrupt is caught Enablelnterrupt must be called again before checking for the next Besides that the FPGA must be informed to lower the interrupt line in any Way Enablelnterrupt API Code C void ceDevice Enablelnterrupt C CE RESULT Enablelnterrupt CE DEVICE HANDLE Handle NET void ceDevice Enablelnterrupt PCI only Must be called in front of calling WaitForlnterrupt and every time an interrupt is caught and should be checked again ResetFPGA API Code C void ceDevice ResetFPGA C CE RESULT ResetFPGA CE DEVICE HANDLE Handle NET void ceDevice ResetFPGA USBS6 C1030 5510 User Doc V0 3 AT http www cesys com preliminary Pulses the FPGA reset line for a short time This should be used to sync the FPGA design with the host side peripherals ProgramFPGAFromBIN API Code C void ceDevice ProgramFPGAFromBIN const char pszFileName C CE RESULT ProgramFPGAFromBIN CE DEVICE HANDLE Handle const char pszFileName NET void ceDevice ProgramFPGAFromBIN string s
45. ed interface to Cesys s USB and PCI devices The class interface from the former USBUni and PClBase API s was saved at a large extend so porting applications from previous UDK releases can be done without much work Here are some notes about additional changes Complete rewrite Build system cleanup all UDK parts except NET are now part of one large project 64 bit operating system support UDK tools combined into one application UDKLab Updated to latest PLX SDK 6 31 Identical C C and NET API interface NET Windows only Different versions of components collapsed to one UDK version Windows only Microsoft Windows Vista Seven 7 support PCI drivers are not released for Seven at the moment Driver installation update is done by an installer now Switched to Microsoft s generic USB driver WinUSB Support moved to Visual Studio 2005 2008 and 2010 experimental older Visual Studio versions are not supported anymore Linux only Revisited USB driver tested on latest Ubuntu distributions 32 64 Simpler USB driver installation USBS6 C1030 5510 http www cesys com User Doc V0 3 30 preliminary Windows Requirements To use the UDK in own projects the following is required Installed drivers Microsoft Visual Studio 2005 or 2008 2010 is experimental e CMake 2 6 or higher gt http www cmake org e wxWidgets 2 8 10 or higher must be build separately http www wxwidgets org op
46. er calling a group of code i e deinit init ceE PROCESSING Occurred during internal processing of anything ceE INCOMPATIBLE _ Not supported by this device ceE OUTOFMEMORY Failure allocating enough memory GetLastErrorText API Code C const char ceException GetLastErrorText C const char GetLastErrorText NET string ceException GetLastErrorText Returns a text which describes the error readable by the user Most of the errors contain problems meant for the developer using the UDK and are rarely usable by end users In most cases unexpected behavior of the underlying operation system or in data transfer is reported All texts are in english USBS6 C1030 5510 http www cesys com User Doc V0 3 39 preliminary Device enumeration The complete device handling is done by the API internally It manages the resources of all enumerated devices and offers either a device pointer or handle to API users Calling Init prepares the API itself while Delnit does a complete cleanup and invalidates all device pointers and handles To find supported devices and work with them Enumerate must be called after Init Enumerate can be called multiple times for either finding devices of different types or to find newly plugged devices primary USB at the moment One important thing is the following Enumerate does never remove a device from the internal device list and so invalidate any pointer it
47. es the behavior of app fifo rd empty o and app fifo rd count o when there is no transaction at the slave FIFO controller side of the FIFO During simultaneous FIFO read and FIFO write transactions the signals do not change The signal app fifo rd empty o will be cleared and app fifo rd count o Willincrease if there are write transactions on the slave FIFO controller side but no read transactions at the application side Please note the one clock cycle delay between app fifo rd iandapp fifo rd data o The signals app usb h2p pktcount o 7 0 and app usb p2h pktcount o 7 0 not shown in figure 9 are useful to fit the 512 byte USB bulk packet alignment They are automatically incremented if the appropriate read app fifo rd i or write strobe app fifo wr i is asserted These signals count 16 bit data words not data bytes 512 byte alignment is turned into a 256 16 bit word alignment at this interface Please note that using raw USB bulk transfers and slave FIFO transactions directly is not recommended It is just for background information Use protocol based WISHBONE interface instead USBS6 C1030 5510 http www cesys com User Doc V0 3 24 preliminary src sync fifo vhd This entity is a general purpose synchronous FIFO buffer It is build of FPGA distributed RAM src sfifo hd a1Kx18b0K5x36 vhd This entity is a general purpose synchronous FIFO buffer with mismatched port widths It
48. ff 2kByte 0 MB Alignment 4 byte Read Paar aii ei Device To File FileToDevice tive view i A Lo IIi E 00000000 00 00 00 00 00 00 00 00 00000008 00 00 00 00 00 00 00 00 PIO BankO gt 0x00100000 00000010 00 00 00 00 00 00 00 00 00000018 00 00 00 00 00 00 00 00 00000020 00 00 00 00 00 00 00 00 00000028 00 00 00 00 00 00 00 00 Read 00000030 00 00 00 00 00 00 00 00 00000038 00 00 00 00 00 00 00 00 Hex 40000000 Hi PISE E E 00000040 00 00 00 00 00 00 00 00 to BODE D 00000048 00 00 00 00 00 00 00 00 GPIO OE Bank1 gt 0x0010000c A Address Range 0x00200000 0x0027fffF Read 512 kByte 0 MB Alignment 4byte PIBS i Device ToFie tive View n i to DODDE Hex 00000000 00200000 ff ff ff ff aa 99 55 66 GPIO Bank1 gt 0x00100004 00200008 30 00 80 01 00 00 00 07 00200010 30 01 60 01 00 00 00 60 Hex 00000000 00200018 30 01 20 01 00 00 31 eS 00200020 30 01 cO 01 O1 c2 20 93 00200028 30 00 cO 01 00 00 00 00 00200030 30 00 80 01 00 00 00 09 00200038 30 00 20 01 00 00 00 00 00200040
49. g critical internal and external FPGA signals The l Os can be accessed as eight ports with 32 bits each Every single I O can be configured as an in or output I O signals of VG96 connector VG96 IO 80 0 are at portO portz bits 80 0 I O signals of add on connector ADD 10 33 0 are at port3 port4 bits 129 96 user LEDs are at port5 bits 163 160 and hex encoder is at port6 bits 195 192 Port is used for monitoring MCB status signals bit 224 gt READ ERROR bit 225 gt READ OVERFLOW bit 226 gt WRITE ERROR bit 227 gt WRITE UNDERRUN and bit 228 gt CALIBRATION DONE src wb sl flash vhd The module encapsulates the low level FLASH controller flash ctrl vhd The integrated command register supports the BULK ERASE command which erases the whole memory by programming all bits to 1 In write cycles the bit values can only be changed from 1 to 0 That means that it is not allowed to have a write access to the same address twice without erasing the whole flash before The read access is as simple as reading from any other WISHBONE device Please see the SPI FLASH data sheet for details on programming and erasing There are two instances of this module One is used for USBS6 C1030 5510 http www cesys com User Doc V0 3 22 preliminary programming FPGA configuration bitstream to SPI FLASH and the other accesses QUAD SPI FLASH for storing nonvolatile application data src wb sl mcb vhd WISHBONE ad
50. he image shows an example initializing list of an EFMO1 loading our example design and let the LED blink for some seconds Prog C devel projects cesys udk trunk efm01_top bin Wirite GPIO OE Banko Figure 15 Initializing sequence Sequence contents UDKLab supports the following content for initialization FPGA programming FPGA reset Register write Sleep Without a design an FPGA does nothing so it must be loaded before usage This can be ensured in two ways USBS6 C1030 5510 http www cesys com User Doc V0 3 55 preliminary Download design from host Load design from flash supported on EFMO1 USBVAF and USBS6 So the first entry in the initialize list must be a program entry or if loaded from flash a reset entry To sync communication to the host side Subsequent to this a mix of register write and sleep commands can be placed which totally depends on the underlying FPGA design This can be a sequence of commands sent to a peripheral component or to fill data structures with predefined values If things get complexer i e return values must be checked this goes beyond the scope of the current UDKLab implementation and must be solved by a host process To control the sequence the buttons on the left side can be used In the order of appearance they do the following also indicated by tooltips Clear complete list Add new entry to the end of the list
51. ies to configure itself from the attached Flash using SPI Master mode If no valid design is stored in the SPI Flash the FPGA has to be configured via JTAG or USB JTAG configuration is supported at any time after the FPGA is properly powered on For downloading designs via JTAG ISE WebPACK from XILINX is recommended The tool can be downloaded from XILINX web page free of charge As JTAG connector USBS6 implements a standard 2x7 Pin header with 2mm pitch which is compatible to recent XILINX platform cables rm ET Figure 3 JTAG connector J2 J2 JTAG connector Signal Comment Signal Comment Name Name 14 GND Ground signal EN VCCAUX 3 3V auxiliary supply Ps eno muse ef TK Aw Test lok r ew oraso e mo bi Testa our Fs ow oraso 1 To bis Testa n ono feroase 1 Nocomecor Fw ew oroas 1 Noconmeston For further information on the different configuration solutions for XILINX SPARTAN 6 USBS6 C1030 5510 http www cesys com User Doc V0 3 7 preliminary FPGA the reader is encouraged to take a look at the user guide UG380 on XILINX web page USB2 0 controller CYPRESS FX2LP is a highly integrated low power USB2 0 microcontroller that integrates USB2 0 transceiver serial interface engine SIE enhanced 8051 micro cont
52. ion to use the right one refer to command substitution if not familiar with Drivers The driver installation on Linux systems is a bit more complicated than on Windows systems The drivers must be build against the installed kernel version Updating the kernel requires a rebuild USB As the USB driver is written by Cesys the installation procedure is designed to be as simple and automated as possible The sources and support files reside in directory lt udkroot gt drivers linux usb Just go there and invoke make cd udkapi2 0 drivers linux usb make If all external dependencies are met the build procedure should finish without errors Newer kernel releases may change things which prevent success but it is out of the scope of our possibilities to be always up to date with latest kernels To install the driver the USBS6 C1030 5510 http www cesys com User Doc V0 3 33 preliminary following command has to be done sudo make install This will do the following things Install the kernel module inside the module library path update module dependencies Install a new udev rule to give device nodes the correct access rights 0666 etc udev rules d 99 ceusbuni rules Install module configuration file etc dev modprobe d ceusbuni conf Start module If things work as intended there must be an entry proc ceusbuni after this procedure The following code will completely revert the
53. l conflict with the standard wxWidgets build configuration Solution creation and build The preferred way is to open a command prompt inside the installation root of the UDK USBS6 C1030 5510 http www cesys com User Doc V0 3 31 preliminary lets assume to use c udkapi C cd Nudkapi CMake allows the build directory separated to the source directory so it s a good idea to do it inside an empty sub directory mkdir build cd build The following code requires an installation of CMake and at least one supported Visual Studio version If CMake isn t included into the PATH environment variable the path must be specified as well cmake This searches the preferred Visual Studio installation and creates projects for it Visual Studio Express users may need to use the command prompt offered by their installation If multiple Visual Studio versions are installed CMake s command parameter G can be used to specify a special one see CMake s documentation in this case This process creates the solution files inside c udkapi build All subsequent tasks can be done in Visual Studio with the created solution another invocation of cmake isn t necessary under normal circumstances Important The UDK C API must be build with the same toolchain and build flags like the application that uses it Otherwise unwanted side effects in exception handling will occur See example in Add project
54. nt strongly depends on FGPA design and may exceed the minimum required n self powered mode the actual VCCO IO current limit depends on sourcing capability of external 5V power supply and may be less If the attached USB2 0 host interface should not be used as power supply it is possible to use USBS6 self powered see SW2 above In this mode an external 5V power supply must be connected to the external expansion connector J3 PINS A1 B1 and C1 All onboard voltages are enabled as soon as an external power supply is applied VCCO on BANKO and BANKS is tied together to VCCO IO but routed independent from other supply voltages Therefore in self powered mode maximum current available on J3 PIN A3 B3 C3 VCCO IO mainly depends on the external power supply to the limit of the onboard regulator which is about 3A As default VCCO IO is regulated to 3 3V to enable 3 3V signaling levels on the external expansion connectors Other signaling levels may be supported but require adjustment of the onboard synchronous buck regulator to the desired value USBS6 C1030 5510 http www cesys com User Doc V0 3 6 preliminary It is strongly recommended to check XILINX UG381 about Spartan 6 FPGA SelectlO Signal Standards on XILINX website Configuration Configuration of USBS6 can be accomplished in several ways JTAG SPI Flash or USB The default configuration mode is booting from SPI Flash After powering on the FPGA USBS6 always tr
55. oid ceDevice EnableBurst bool bEnable C CE RESULT EnableBurst CE DEVICE HANDLE Handle unsigned int uiEnable NET void ceDevice EnableBurst bool bEnable PCI only Enable bursting in transfer which frees the shared address data bus between PCl e chip and FPGA by putting addresses on the bus frequently only USBS6 C1030 5510 User Doc V0 3 49 http www cesys com preliminary UDKLab Introduction UDKLab is a replacement of the former cesys Monitor as well as cesys Lab and fpgaconv It is primary targeted to support FPGA designers by offering the possibility to read and write values from and to an active design It can further be used to write designs onto the device s flash so FPGA designs can load without host intervention Additionally designs can be converted to C C and C arrays which allows design embedding into an application USBS6 C1030 5510 http www cesys com User Doc V0 3 50 preliminary The main screen The following screen shows an active session with an EFMO1 device The base view is intended to work with a device while additional functionality can be found in the tools menu The left part of the screen contains the device initialization details needed to prepare the FPGA with a design or just a reset if loaded from flash plus optional register writes for preparation of peripheral components The right side contains elements for communication with the FPGA design
56. ot developed by Cesys it s not possible to us to prevent this as we see this as strange behavior The best way to share communication of more than one application with devices would be a client server approach Close API Code C void ceDevice Close C CE RESULT Close CE DEVICE HANDLE Handle NET void ceDevice Close USBS6 C1030 5510 http www cesys com User Doc V0 3 45 preliminary Finish working with the given device ReadRegister API Code C unsigned int ceDevice ReadRegister unsiged int uiRegister C CE RESULT ReadRegister CE DEVICE HANDLE Handle unsigned int uiRegister unsigned int puiValue NET uint ceDevice ReadRegister uint uiRegister Read 32 bit value from FPGA design address space internally just calling ReadBlock with size 4 WriteRegister API Code C void ceDevice WriteRegister unsiged int uiRegister unsigned int uiValue C CE RESULT WriteRegister CE DEVICE HANDLE Handle unsigned int uiRegister unsigned int uiValue NET void ceDevice WriteRegister uint uiRegister uint uiValue Write 32 bit value to FPGA design address space internally just calling WriteBlock with size 4 ReadBlock API Code C void ceDevice ReadBlock unsiged int uiAddress unsigned char pucData unsigned int uiSize bool bincAddress C CE RESULT ReadBlock CE DEVICE HANDLE Handle unsigned int uiAddress unsigned char p
57. out CESYS USB transfer protocol It checks FX 2 FIFO flags and copies data from FX 2 endpoints to internal FPGA buffers sync fifo vhd and vice versa So the USB data link looks like any other FPGA FIFO buffer to user logic Ports of x2 slfifo ctrl connected to FX 2 are labeled with prefix fx2 and ports connected to user logic are labeled with prefix app Sometimes the abbreviations h2p host to peripheral and p2h peripheral to host are used in signal names to indicate data flow direction USBS6 C1030 5510 http www cesys com User Doc V0 3 23 preliminary RD app fifo wr i h i l x i i i i A app fifo wr data i X DO XZZZ K 01 K D2 A D3 A nA KLZ P app fifo wr full o 2 app_fifo_wr_count_o ifclk lt app_fifo_rd_i 9 uL app fifo rd data o A app_fifo_rd_empty_o y is app_fifo_rd_count_o Figure 9 FIFO transactions of fx2 sl fi fo ctrl at user logic side The upper waveform demonstrates the behavior of app fifo wr full o and app fifo wr count o When there is no transaction on the slave FIFO controller side of the FIFO During simultaneous FIFO read and FIFO write transactions the signals do not change The signal app fifo wr full o willbe cleared and app fifo wr count o will decrease if there are read transactions at the slave FIFO controller side but no write transactions at the application side The lower waveform demonstrat
58. r than the device count returned by GetDeviceCount This pointer or handle is valid up to the point Delnit is called USBS6 C1030 5510 User Doc V0 3 42 http www cesys com preliminary Information gathering The functions in this chapter return valuable information All except GetUDKVersionString are bound to devices and can be used after getting a device pointer or handle from GetDevice only Methods Functions GetUDKVersionString API Code C static const char ceDevice GetUDKVersionString C const char GetUDKVersionString NET static string ceDevice GetUDKVersionString Return string which contains the UDK version in printable format GetDeviceUID API Code C const char ceDevice GetDeviceUID C CE RESULT GetDeviceUID CE DEVICE HANDLE Handle char pszDest unsigned int uiDestSize NET string ceDevice GetDeviceUID Return string formatted unique device identifier This identifier is in the form of type location while type is the type of the device i e EFMO1 and location is the position the device is plugged to For PCI devices this is a combination of bus slot and function PCI bus related values and for USB devices a path from device to root hub containing the port of all used hubs So after re enumeration or reboot devices on the same machine can be identified exactly Notice C API pszDest is the buffer were the value is stored to
59. roller Soft IP all on their own Some examples on how to implement LPDDR with Spartan 6 are available in chapter C LPDDR SDRAM MT46H64M16LFCK 5 SgmiName FPGAIO Come Address inputs Provide the row address for ACTIVE commands and the column address and auto precharge bit A10 for READ or WRITE commands to select one location out of the memory array in the respective bank During a PRECHARGE command A10 determines whether the PRECHARGE applies to one bank A10 LOW bank selected by BAO BA1 or all banks A10 HIGH The address inputs also provide the op code during a LOAD MODE REGISTER command MCB1 BAO H13 Bank address inputs BAO and BA1 define to which bank an ACTIVE READ WRITE or PRECHARGE command is being applied BAO and BA1 also determine which mode register is loaded during a Note LOAD MODE REGISTER command USBS6 C1030 5510 http www cesys com User Doc VO 3 9 preliminary LPDDR SDRAM MT46H64M16LFCK 5 signal Name FPGAIO Comme Command inputs RAS CASH and WE along with CS define the command being entered Puce css MCB1 CKE n D17 Clock enable CKE HIGH activates and CKE LOW deactivates the internal clock signals input buffers and output drivers Taking CKE LOW enables PRECHARGE power down and SELF REFRESH operations all banks idle or ACTIVE power down row active in any bank CKE is synchronous for all functions except SELF REFRESH exit All input buffers except CKE are
60. roller and a programmable peripheral interface More information on usage of FX2LP in conjunction with Spartan 6 can be found in chapter C USB2 0 FX2LP Microcontroller CYPRESS CY7C68013A FX2 IFCLK V9 Clock input for both FX2 and FPGA 48MHz clock is provided by an external oscillator FX2 SLWR FX2 input FIFO write strobe FX2 SLRD FX2 input FIFO read strobe FX2 SLOE FX2 input output enable activates FX2 data bus FX2 PKTEND V8 FX2 input packet end control signal causes FX2 to send data to host at once ignoring 512 byte alignment so called short packet Short packets sometimes lead to unpredictable behavior at host side wherefore short packets are not support FX2 input endpoint buffer addresses only two endpoints are used EP2 OUT ADR 1 0 b 00 and EP6 IN ADR 1 0 b 10 R TT 16 Bit bidirectional FIFO data bus FX2 FD10 USBS6 C1030 5510 http www cesys com User Doc VO 3 8 preliminary USB2 0 FX2LP Microcontroller CYPRESS CY7C68013A FX2 FD11 FX2 FD12 FX2 FD13 FX2 FD14 R8 FX2 FD15 External memory USBS6 offers the opportunity to use various external memory architectures in one s FPGA design With Micron Technology MT46H64M16LFCK 5 up to 1Gbit of high speed low power DDR SDRAM is available The integrated memory controller of Spartan 6 devices enables system designers to implement state of the art memory interfaces without the need to develop a whole memory cont
61. s well as the checkboxes which is automatically done every 100ms if the Auto button is active Setting register values inside the FPGA is done in a similar way clicking the Write button writes the current values to the device One thing needs a bit attention here Clicking on the checkboxes implicitly writes the value without the need to click on the Write button USBS6 C1030 5510 User Doc V0 3 58 http www cesys com preliminary Data area entry A data area entry can be used to communicate with a data block inside the FPGA examples are RAM or flash areas Data can be transfered from and to files as well as displayed in a live view An entry constits of the following data Address Name Data alignment Size Read only flag The visual representation is shown below Block RAM gt 0x00000000 ES Address Range 0x00000000 0x000007ff 4 2kByte 0 MB Alignment 4 byte t3 Device To File File To Device Live View L Figure 19 Data area panel Similar to the register visualization the buttons on the right side can be used to add move and remove data area panels The header shows the name and the address followed by the data area details Below are these buttons Device To File The complete area is read and stored to the file which is defined in the file dialog opening after clicking the button File To Device This reads the file selected in the upcoming file dialog and stores the
62. te data It is used to capture data As the memory device interface of Spartan 6 supports only one device CS signal is not supported by Spartan 6 MCB CS is pulled LOW via an external O Ohm resistor It is strongly recommended to check XILINX user guide UG388 about Spartan 6 FPGA Memory Controller on XILINX website It is strongly recommended to check XILINX user guide UG416 about Spartan 6 FPGA Memory Interface Solutions on XILINX website User specific data can be stored in up to 128Mb of non volatile Flash memory The SPI compliant interface guarantees ease of use and when speed matters Macronix MX25L 12845EMI 10G supports Q SPI with data rates up to 50 MByte s in fast read double transfer rate mode Some examples on how to implement a SPI compliant interface with Spartan 6 are available in chapter C Q SPI Flash MX25L12845EMI 10G MX CS n Active low Chip Select MX SCLK Clock Input Active low Write Protect SPI Serial Data IO Dual or Q SPI Peripherals USBS6 integrates several peripheral devices Three system and five user configurable LEDs one HEX rotary DIP switch and one USB to SERIAL UART are available Power supply status and FPGA configuration are observable through the system LEDs The user USBS6 C1030 5510 http www cesys com User Doc VO 3 11 preliminary configurable LEDs allow to make internal monitoring status signals visible by driving the appropri
63. tionally only if UDKLab should be build Driver installation The driver installation is part of the UDK installation but can run standalone on final customer machines without the need to install the UDK itself During installation a choice of drivers to install can be made so it is not necessary to install i e PCI drivers on machines that should run USB devices only or vice versa If USB drivers get installed on a machine that has a pre 2 0 UDK driver installation we prefer the option for USB driver cleanup offered by the installer this cleanly removes all dependencies of the old driver installation Note There are separate installers for 32 and 64 bit systems Important At least one device should be present when installing the drivers Build UDK Prerequisites The most components of the UDK are part of one large CMake project There are some options that need to be fixed in msvc cmake inside the UDK installation root BUILD UI TOOLS If 0 UDKLab will not be part of the subsequent build procedure if 7 it will This requires an installation of an already built wxWidgets WX WIDGETS BASE PATH Path to wxWidgets build root only needed if BUILD UI TOOLS is not O USE STATIC RTL If 0 all projects are build against the dynamic runtime libraries This requires the installation of the appropriate Visual Studio redistributable pack on every machine the UDK is used on Using a static build does not create such dependencies but wil
64. to UDK build Info It is easy to create different builds with different Visual Studio versions by creating different build directories and invoke CMake with different G options inside them C cd Nudkapi mkdir build2005 cd build2005 cmake G Visual Studio 8 2005 cdi a mkdir build2008 cd build2008 cmake G Visual Studio 9 2008 USBS6 C1030 5510 http www cesys com User Doc V0 3 32 preliminary Linux There are too many distributions and releases to offer a unique way to the UDK installation We ve chosen to work with the most recent Ubuntu release 9 10 at the moment All commands are tested on an up to date installation and may need some tweaking on other systems versions Requirements GNU C compiler toolchain zlib development libraries s CMake 2 6 or higher gt http www cmake org wxWidgets 2 8 10 or higher gt http www wxwidgets org optionally only if UDKLab should be build sudo apt get install build essential cmake zliblg dev libwxbase2 8 dev libwxgtk2 8 dev The Linux UDK comes as gzip ed tar archive as the Windows installer won t usually work The best way is to extract it to the home directory tar xzvf UDKAPI x x tgz This creates a directory home userj udkapi version which is subsequently called udkroot The following examples assume an installation root in udkapi2 0 Important Commands sometimes contain a symbol have attent
65. ucData unsigned int uiSize unsigned int uilncAddress NET void ceDevice ReadBlock uint uiAddess byte Data uint uiLen bool bIncAddress Read a block of data to the host buffer which must be large enough to hold it The size should never exceed the value retrieved by GetMaxTransferSize for the specific device bIncAddress is at the moment available for USB devices only It flags to read all data from the same address instead of starting at it WriteBlock API Code C void ceDevice WriteBlock unsiged int uiAddress unsigned char pucData unsigned int uiSize bool bincAddress C CE RESULT WriteBlock CE DEVICE HANDLE Handle unsigned int uiAddress http www cesys com preliminary USBS6 C1030 5510 User Doc V0 3 46 unsigned char pucData unsigned int uiSize unsigned int uilncAddress void ceDevice WriteBlock uint uiAddess byte Data uint uiLen bool bIncAddress NET Transfer a given block of data to the 32 bit bus system address uiAddress The size should never exceed the value retrieved by GetMaxTransferSize for the specific device bIncAddress is at the moment available for USB devices only It flags to write all data to the same address instead of starting at it WaitForlnterrupt API Code C bool ceDevice WaitForlnterrupt unsigned int uiTimeOutMS C CE RESULT WaitForlnterrupt CE DEVICE HANDLE Handle unsigned int uiTimeOutMS unsign
66. uto increment mode in the CESYS application note Transfer Protocol for CESYS USB products and software API documentation CESYS USB transfer protocol is converted into one or more WISHBONE data transaction cycles So the FX 2 becomes a master device in the internal WISHBONE architecture Input signals for the WISHBONE master are labeled with the postfix output signals with O WISHBONE signals driven by the master STB O strobe qualifier for the other output signals of the master indicates valid data and control signals WE O write enable indicates if a write or read cycle is in progress ADR O 31 2 32 Bit address bus the software uses BYTE addressing but all internal WISHBONE accesses are DWORD 32 Bit aligned So address LSBs 1 0 are discarded DAT O 31 0 32 Bit data out bus for data transportation from master to slaves WISHBONE signals driven by slaves s DAT 1 31 0 32 Bit data in bus for data transportation from slaves to master e ACK I handshake signal slave devices indicate a successful data transfer for writing and valid data on bus for reading by asserting this signal slaves can insert wait states by delaying this signal it is possible to assert ACK in first clock cycle of STB O assertion using a combinatorial handshake to transfer data in one clock cycle recommendation registered feedback handshake should be used in applications where maximum data throughput is not needed because timing specs
67. wly plugged devices of the given type and add them to the internal list Access to this list is given by GetDeviceCount GetDevice DeviceType can be one of the following DeviceType Description ceDT ALL All UDK supported devices ceDT PCI ALL All UDK supported devices on PCI bus ceDT PCI PCIS3BASE Cesys PCIS3Base ceDT PCI DOB DOB ceDT PCI PCIEVABASE Cesys PCleV4Base ceDT PCI RTC RTC ceDT PCI PSS PSS ceDT PCI DEFLECTOR Deflector ceDT USB ALL All UDK supported devices ceDT USB USBV4F Cesys USBV4F ceDT USB EFMO1 Cesys EFMO1 ceDT USB MISS2 MISS2 ceDT USB CID CID ceDT USB USBS6 Cesys USBS6 Customer specific devices GetDeviceCount API Code C static unsigned int ceDevice GetDeviceCount C CE RESULT GetDeviceCount unsigned int puiCount NET static uint ceDevice GetDeviceCount Return count of devices enumerated up to this point May be larger if rechecked after calling Enumerate in between USBS6 C1030 5510 User Doc V0 3 41 http www cesys com preliminary GetDevice API Code C static ceDevice ceDevice GetDevice unsigned int uildx C CE RESULT GetDevice unsigned int uildx CE DEVICE HANDLE pHandle NET static ceDevice ceDevice GetDevice uint uildx Get device pointer or handle to the device with the given index which must be smalle

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