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Analog Devices ADSP-TS201S Network Card User Manual

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1. REFERENCE SIGNAL MEASURED 015 MEASURED ENA tois tena Von MEASURED VoL MEASURED AV VoL MEASURED DECAY OUTPUT STOPS OUTPUT STARTS DRIVING DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1 25V Figure 35 Output Enable Disable December 2006 ADSP TS201S Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driv ing The time for the voltage on the bus to ramp by AV is dependent on the capacitive load C and the drive current Ip This ramp time can be approximated by the following eguation tramp C AV Ip The output enable time tgya is the difference between MEASURED ENA and tramp as shown in Figure 35 The time MEASURBD ENA 15 the interval from when the reference signal switches to when the output voltage ramps AV from the mea sured three stated output level tramp is calculated with test load C drive current Ip and with AV equal to 0 4 V Capacitive Loading Output valid and hold are based on standard capacitive loads 30 pF on all pins see Figure 36 The delay and hold specifica tions given should be derated by a drive strength related factor for loads other than the nominal value of 30 pF Figure 37 through Figure 44 show how output rise time varies with capac itance Figure 45 graphically shows how output valid varies with load capacitanc
2. LcLKOP 0V LxCLKOUT LxCLKOUT Von 0V LcLKOH LCLKOL Lpos LDoH tipos LpoH Figure 18 Link Ports Output Clock e a p LxDATO OV R 1000 C 0 1pF Figure 20 Link Ports Data Output Setup and Hold Ces 5pF Lp P VThese parameters are valid for both clock edges C yu 5pF treo treo lt gt Vop MIN ON Voo wm Figure 19 Link Ports Differential Output Signals Transition Time LxCLKOUT 0V LxDATO Vop 0V LACKID LxACKI BCMPOV LxBCMPO Figure 21 Link Ports Transmission Start Rev C Page 32 of48 December 2006 ADSP TS201S 2 FIRST EDGE OF 5TH SHORT VVORD IN A QUAD VVORD LAST EDGE IN A QUAD WORD LxCLKOUT 0V LxDATO Vop 0V LACKIS LACKIH LxACKI scmPoH LxBCMPO Figure 22 Link Ports Transmission End and Stops Bag EDGE IN A QUAD WORD LxCLKOUT 0V LxDATO Vop 0V li ackis LACKIH LxACKI Figure 23 Link Ports Back to Back Transmission Rev C Page 33 of48 December 2006 ADSP TS201 Link Port Data In Timing Table 33 with Figure 24 and Figure 25 provide the data in timing for the LVDS link ports Table 33 Link Port Data In Timing Parameter Description Min Max Unit Inputs LxCLKIN
3. E 10 Vpp 2 38V 105 C 5 E 15 2 20 25 lou 30 mi 04 08 12 16 2 0 24 2 8 OUTPUT PIN VOLTAGE V 3 z 2 5V 25 C 2 b LE Figure 27 Typical Drive Currents at Strength 1 2 Vpp 1o 2 38V 105 C 5 o 0 0 4 0 8 12 1 6 2 0 24 2 8 OUTPUT PIN VOLTAGE V Figure 30 Typical Drive Currents at Strength 4 Rev C Page360f48 December 2006 OUTPUT PIN CURRENT mA OUTPUT PIN CURRENT mA OUTPUT PIN CURRENT mA 100 90 80 70 60 50 40 30 10 10 20 30 40 50 60 70 80 90 100 STRENGTH 5 Vpp Io 2 5V 25 C 2 63V 40 C Von qo 2 53V 40 C Von 2 38V 105 C 2 5V 25 C Vpp 2 38V 105 C 0 4 0 8 1 2 1 OUTPUT PIN VOLTAGE V 6 20 2 4 Figure 31 Typical Drive Currents at Strength 5 2 8 STRENGTH 6 lo Vpp 2 63V 40 C I Vpp io 2 5V 25 C t Ven 1o 2 38V 105 C t Vpp yo 2 63V 40 C Vpp 2 5V 25 C Vpp io 2 38V 105 C lon 0 4 0 8 1 2 1 6 2 0 24 2 8 OUTPUT PIN VOLTAGE V Figure 32 Typical Drive Cur
4. Von A Vpp 10 Vpp pRAM Figure 12 Power Up Timing Table 26 Power Up Reset Timing Parameter Min Max Unit Timing Requirements RsT IN PWR RST IN Deasserted After Vpp Von a Von io DRAM SCLK and Static Strap Pins Stable 2 ms trrst_IN_PwR TRST Asserted During Power Up Reset 100 x Leck ns Switching Characteristic trast OUT pwr RST_OUT Deasserted After RST_IN Deasserted 1 5 ms Applies after Vpp Vpp 10 VDD DRAw and SCLK are stable and before RST_IN deasserted iN PWR our PwR RST OUT rRST IN PWR TRST SCLK Vpp Vpp A Vpp 10 VDD_DRAM STATIC STRAP PINS Figure 13 Power Up Reset Timing Rev C Page260f48 December 2006 Table 27 Normal Reset Timing ADSP TS201S Parameter Min Max Unit Timing Reguirements RsT IN RST_IN Asserted 2 ms STRAP RST_IN Deasserted After Strap Pins Stable 1 5 ms Switching Characteristic tast OUT RST_OUT Deasserted After RST_IN Deasserted 1 5 ms RST_IN trst_out RST OUT tstrap STRAP PINS Figure 14 Normal Reset Timing Table 28 On Chip DRAM Refresh Parameter Min Max Unit Timing Requirement ker On chip DRAM Refresh Period 1 56 Hs For more information on setting the refresh rate for the on chip DRAM refer to the ADSP TS201 TigerSHARC Processor Programming Reference Rev C Page 27 of48 December 2006 ADSP TS201S Table 29 AC Sig
5. input A asynchronous O output OD open drain output T three state P power supply G ground pd internal pull down 5 ko pu internal pull up 5 ko pd 0 internal pull down 5 ko on DSP ID internal pull up 5 kO on DSP ID 0 pu od 0 internal pull up 500 on DSP ID 0 pd m internal pull down 5 ko on DSP bus master pu m internal pull up 5 ko on DSP bus master pu ad internal pull up 40 ko For more pull down and pull up information see Electrical Characteristics on Page 22 Term termination of unused pins column symbols epd external pull down approximately 5 ko to Vss epu external pull up approx imately 5 to Von jo nc not connected na not applicable always used Vpp io connect directly to Vpp io Vss connect directly to Vss Table 4 SCLK Ratio SCLKRAT2 0 Ratio 000 default 4 001 5 010 6 011 7 100 8 101 10 110 12 111 Reserved Rev C Page 12 of48 December 2006 ADSP TS201S Table 5 Pin Definitions External Port Bus Controls Signal Type Term Description ADDR31 0 1 O T nc Address Bus The DSP issues addresses for accessing memory and peripherals on pu_ad these pins In a multiprocessor system the bus master drives addresses for accessing internal memory or I O processor registers of other ADSP TS201S processors The DSP inputs addresses when a host or another DSP accesses its internal memory or 1 O processor
6. Ground and Reference Signal Type Term Description Vpp P na Vpp pins for internal logic Von A P na Vpp pins for analog circuits Pay critical attention to bypassing this supply Von io P na Vbo pins for I O buffers Von DRAM P na Vpp pins for internal DRAM VREF Reference voltage defines the trip point for all input buffers except SCLK RST_IN POR IN IRQ3 0 FLAG3 0 DMAR3 0 ID2 0 CONTROLIMP1 0 LXDATO3 0P N LxCLKOUTP N LxDATI3 0P N LxCLKINP N TCK TDI TMS and TRST Ver can be connected to a power supply or set by a voltage divider circuit as shown in Figure 6 For more information see Filtering Reference Voltage and Clocks on Page 10 SCLK Ver System Clock Reference Connect this pin to a reference voltage as shovvn in Figure 7 For more information see Filtering Reference Voltage and Clocks on Page 10 Vss G na Ground pins NC nc No Connect Do notconnectthese pins to anything not to any supply signal or each other These pins are reserved and must be left unconnected I input A asynchronous O output OD open drain output T three state P power supply G ground pd internal pull down 5 ko pu internal pull up 5 ko pd internal pull down 5 ko on DSP ID 0 pu_0 internal pull up 5 k2on DSP ID 0 pu_od_0 internal pull up 500 2 on DSP ID 0 pd m internal pull down 5 ko on DSP bus master pu m internal pull up 5 ko on DSP bus master pu ad inter
7. R5 Vpn io T5 Vss N6 Voo P6 Vbo R6 Vbo T6 Vbo N7 Vip P7 Man R7 Vbo T7 EH N8 Vas P8 Vas R8 Vss T8 Vss N9 Vas P9 Vas R9 Vas T9 Vss Min Vs P10 Vss R10 Vss T10 Vss N11 Vss P11 Vss R11 Vss T11 Vss N12 Vss P12 Vss R12 Vss T12 Vss N13 Vss P13 Vss R13 Vss T13 Vss N14 Vss P14 Vss R14 Vss T14 Vss N15 Vss P15 Vss R15 Vss T15 Vss N16 Vss P16 Vss R16 Vss T16 Vss N17 Vss P17 Vss R17 Vss T17 Vss N18 Von P18 Von DRAM R18 VED DRAM T18 Von N19 Von P19 Vbp DRAM R19 VED DRAM T19 Von N20 P20 ND R20 Vooo T20 Vss N21 LODATO2_N P21 LODATO1_N R21 NC T21 L1DATIO_N N22 LODATO2_P P22 LODATO1_P R22 Vss T22 L1DATIO_P N23 LOCLKON P23 LODATOO_N R23 LOBCMPO T23 L1ACKO N24 LOCLKOP P24 LODATOO_P R24 LOACKI T24 L1BCMPI Rev C Page430f48 December 2006 ADSP TS201S Table 35 576 Ball 25 mm x 25 mm BGA_ED Ball Assignments Continued Ball No Signal Name Ball No Signal Name Ball No Signal Name Ball No Signal Name U1 MSSDO V1 MSSD2 W1 CONTROLIMPO Y1 EMU U2 RST_OUT V2 DS2 W2 ENEDREG Y2 TCK U3 ID2 V3 POR_IN W3 TDI Y3 TMROE U4 DS1 V4 CONTROLIMP1 WA TDO Y4 FLAG3 U5 Vom V5 Vss ws Vpp io Y5 Vss U6 Voo V6 Voo w6 Voo Y6 Vio U7 Vop V7 Vop W7 Vop Y7 Vss 8 Vss V8 Vis w8 Voo Y8 vee U9 Vss v9 Vop w9 Vop Y9 Vss U10 Vpp vio V W10 Vop Y10 V zi U11 VpD_DRAM V11 VpD_DRAM W11 Von DRAM Y11 Von io U12 Vss V12 Vpp_DRAM W12 Von pRAM Y12 Von io Ul3 Vg V13 Lyon VV13 Ion Y13 Nada Ul4 Vs V
8. as inputs they can provide the test for conditional branching RESET AND BOOTING The ADSP TS201S processor has three levels of reset Power up reset after power up of the system SCLK all static inputs and strap pins are stable the RST_IN pin must be asserted low Normal reset for any chip reset following the power up reset the RST_IN pin must be asserted low DSP core reset when setting the SWRST bit in EMUCTL the DSP core is reset but not the external port or I O For normal operations tie the RST_OUT pin to the POR_IN pin Rev C Page 9 of 48 ADSP TS201S After reset the ADSP TS201S processor has four boot options for beginning operation e Boot from EPROM Boot by an external master host or another ADSP TS201S processor e Boot by link port e No boot start running from memory address selected with one of the IRO3 0 interrupt signals See Table 2 Using the no boot option the ADSP TS201S processor must start running from memory when one of the interrupts is asserted Table 2 No Boot Run from Memory Addresses Interrupt Address IROO 0x3000 0000 External Memory IRO1 0x3800 0000 External Memory IRO2 0x8000 0000 External Memory IRO3 0x0000 0000 Internal Memory The ADSP TS201S processor core always exits from reset in the idle state and waits for an interrupt Some of the interrupts in the interrupt vector table are initialized and enab
9. put drivers as a function of output voltage over the range of 36 drive strengths Typical drive currents for intermediate temper 27 atures such as 85 C should be obtained from the curves using T 18 en aen RRE s a S s 2 5V 425 b inear interpolation For complete output driver characteristics x z refer to the DSP s IBIS models available on the Analog Devices ui Vpp 10 2 38V 105 C Vpp 2 63V 40 C website www analog com S o o Vpp 10 2 5V 425 C z 9 a Vpp 2 38V 105 C 5 18 STRENGTH 0 15 0 2 27 1 12 5 36 on lot 10 0 ET 0 04 0 8 12 16 2 0 2 4 2 8 7 5 E e Vpp jo 2 63V 40 C OUTPUT PIN VOLTAGE V 50 Vpp io 25V 25 C 25 V 2 63V 40 C Figure 28 Typical Drive Currents at Strength 2 E DD 10 2 63V 2 o Z Von 10 238V 105 C m T 25 o 2 5V 25 C STRENGTH 3 2 z 5 0 2 38V 105 C 5 28 E 5 10 0 o lon 12 5 E 15 0 5 10 04 08 12 1 6 2 0 24 2 8 E OUTPUT PIN VOLTAGE V 4105 C z Figure 26 Typical Drive Currents at Strength 0 E Vpp 10 ZEN 25 C 5 i 2 38V 105 C 2 o STRENGTH 1 30 25 lo 20 0 04 08 1 2 1 6 2 0 24 2 8 we OUTPUT PIN VOLTAGE V Vpp 2 63V 40 C 10 2 5V 25 Figure 29 Typical Drive 5 at Strength 3 mi 5 Vpp 10 2 63 40 C m i 5 ol Men ro 2 38V 105 C o STRENGTH 4 5 25V 25 C o
10. 31 Link Port Data In Timing 34 Quiput Driye Curren yaa E 36 Rev C Page 2 of 48 Test E 37 Output Disable TEBE ad abad 37 Output basble TUUS 38 Gn LL LOB NE RF ges 38 Environmental Conditions sulu adada GL 40 Thermal Characteristics 40 576 Ball BGA ED Pin Configurations 41 e dU asya d 45 Surface Mount DEIN 45 S 46 REVISION HISTORY 12 06 Rev B to Rev C Applied Corrections to Figure 7 SCLK_VREF Filtering Scheme 10 O O I 21 Added On Chip DRAM Refresh asid FY 27 qa q reir MN FYR 46 December 2006 GENERAL DESCRIPTION The ADSP TS201S TigerSHARC processor is an ultrahigh per formance static superscalar processor optimized for large signal processing tasks and communications infrastructure The DSP combines very wide memory widths with dual computation blocks supporting floating point IEEE 32 bit and extended precision 40 bit and fixed point 8 16 32 and 64 bit pro cessing to set a new standard of performance for digital signal processors The TigerSHARC static superscalar architecture lets the DSP execute up to four instructions each cycle performing 24 fixed point 16 bit operations or six floating point operations Four independent 128 bit
11. EH 83 O e by e i e bi bd KKK kK 03 e DO O oooooeee KEY O SIGNAL EH Von Vpp Vpp pRAM e Vop A amp VREF 6 vss amp NO CONNECT OOKUHH OOR AH eoxHme eoxmme CRW H ee CRW e e O o e amp o o e ES EE see Am as Sr se Tonn oo mp SN TOP VIEVV Figure 46 576 Ball BGA ED Pin Configurations Top View Summary For a more detailed pin summary diagram see the EE 179 ADSP TS2018 System Design Guidelines on the Analog Devices website www analog com Rev C Page410f48 December 2006 ADSP TS201S Table 35 576 Ball 25 mm x 25 mm BGA_ED Ball Assignments Ball No Signal Name Ball No Signal Name Ball No Signal Name Ball No Signal Name A1 Vig B1 DATA53 Ci Vss D1 DATA55 A2 DATA51 B2 Ve C2 V D2 DATA56 A3 Vss B3 Vis C3 Ve D3 DATA54 A4 DATA49 B4 DATA50 C4 DATA52 D4 Vss A5 DATA43 B5 DATA44 C5 DATA47 D5 DATA48 A6 DATA41 B6 DATA42 C6 DATA45 D6 DATA46 A7 DATA37 B7 DATA38 C7 DATA39 D7 DATA40 A8 DATA33 B
12. Leakage Current Low OVpp Max Vn 0 V 0 3 0 76 mA los Pu Three State Leakage Current Low OVpp Max Vn 0 V 30 100 HA 102 op Three State Leakage Current Low OVpp Vy 0 V 4 7 6 mA Cn Input Capacitance 1 MHz Tease 25 C Vy 2 5 V 3 pF Parameter name suffix conventions no suffix applies to pins without pull up or pull down resistors PD applies to pin types pd or pd 0 PU applies to pin types pu or pu 0 PU AD applies to pin types pu_ad OD applies to pin types OD PD L applies to pin types pd 1 Applies to output and bidirectional pins 3 Applies to all signals 5 Guaranteed but not tested Rev C Page 22 048 December 2006 PACKAGE INFORMATION The information presented in Figure 8 provide details about the package branding for the ADSP TS201S processors For a com plete listing of product availability see Ordering Guide on Page 46 ANALOG DEVICES ADSP TS20xS tppZ ccc LLLLLLLLL L 2 0 yyww country_of_origin ree SHARC VVVVV Figure 8 Typical Package Brand Table 19 Package Brand Information ADSP TS201 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed below may cause permanent damage to the device These are stress ratings only Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specifica tion is not implied Exposure to
13. Period Figure 25 Greater of 1 8 or 0 9 x tec 12 5 ns tipis LxDATI Input Setup Figure 25 0 20 ns 0 25 ns 0 30 ns 0 35 ns Lou LxDATI Input Hold Figure 25 0 20 ns 0 25 ns 0 30 ns 0 35 ns tacmpis LxBCMPI Setup Figure 24 2 X boer ns BcMpiH LxBCMPI Hold Figure 24 2 X boer ns Timing is relative to the 0 differential voltage Vop 0 Vip 250 mV Vip 2217 mV Vip 206 mV 5 Vip 195 mV LxCLKIN Vop 0V LxDATI Vop 0V scmpis FIRST EDGE IN FIFTH SHORT WORD IN A QUAD WORD BCMPIH LxBCMPI Figure 24 Link Ports Last Received Quad Word Rev C Page 34 of 48 December 2006 ADSP TS201S t l LCLKIP e LxCLKIN Vop V tips on os LpiH pi Fra LxDATI Von V Figure 25 Link Ports Data Input Setup and Hold VThese parameters are valid for both clock edges Rev C Page 35 of48 December 2006 ADSP TS201S OUTPUT DRIVE CURRENTS Figure 26 through Figure 33 show typical I V characteristics for the output drivers of the ADSP TS201S processor The curves in STRENGTH 2 45 these diagrams represent the current drive capability of the out Gr
14. TABLE F CONTENTS Genera Desedplofi 3 Dual Compote Blocked 4 Data Alisnment Butter DA B 4 Dual Integer ALU ALU 4 Programi GEHT YY dal 5 ntermipiConirellar ee aaa o 5 Flexible Instruction 5 LEO e E 5 External Port Off Chip Memory Peripherals cu r Lt M E IE 6 y n NE YF y RR 7 Multiprocessor Enterface vv sica ERR han 7 SDRAM Controller b 7 EPROM Interface si Ga 7 7 Link Pors LVDS O 9 Timer and General Purpose YO aud RYAN 9 Reset and ROGUE Uu See 9 Clock Domains M 9 Power 10 Filtering Reference Voltage and Clocks 10 Development FRO 10 bu unt EE RF 11 Designing an Emulator Compatible DSP 2007700 11 Additional formation 11 Pin Puncton Desconpions 12 Strap Pin Function Descriptions ue een 20 ADSP T 2018 Specificatlons 21 ANM P 21 Electrical Characteristics 22 Package Information 23 Absolute Maximum Ratings 23 ESD Sensitivity uu ay s xaya GRH WW FY 25 Timne Spec cal OTI 24 General AC EC qe Li YER i 24 Link Port Low Voltage Differential Signal LVDS Electrical Characteristics and Timing 30 Link Port Data Out Timing
15. VoL Output Voltage Low Vo p or Vo n R 100 Q 0 92 V Output Differential Voltage 100 O 300 650 mV los Short Circuit Output Current Vo por Von 0V 5 55 mA Von 20V 10 mA Vocm Common Mode Output Voltage 1 20 1 50 V Table 31 Link Port LVDS Receive Electrical Characteristics Parameter Description Test Conditions Min Max Unit Viol Differential Input Voltage tipis tipiy gt 0 20 ns 250 850 mv tipis tipin gt 0 25 ns 217 850 mv tipis Lpin 2 0 30 ns 206 850 mV tipis tipin 2 0 35 ns 195 850 mv Vic Common Mode Input Voltage 0 6 1 57 V Yop Vo p n RL as Vo p Vo n 2 Vo N Figure 16 Link Ports Transmit Electrical Characteristics DIFFERENTIAL PAIR WAVEFORMS Lx lt PIN gt P Lx lt PIN gt N DIFFERENTIAL VOLTAGE WAVEFORM Lx lt PIN gt Vop DN Figure 17 Link Ports Signals Definition Rev C Page300f48 December 2006 ADSP TS201S Link Port Data Out Timing Table 32 with Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 and Figure 23 provide the data out timing for the LVDS link ports Table 32 Link Port Data Out Timing Parameter Description Min Max Unit Outputs treo Rising Edge Figure 19 350 ps treo Falling Edge Figure 19 350 ps LxCLKOUT Period Figure 18 Greater of 2 0 or Smaller of 12 5 or 0 9 x LCR x tc 1 1 x LCR x teak ns tLCLKOH LxCLKOUT High Figure 18 0 4 X tici kop 0 6 x tici kop ns Loo LxCLKOUT Low Figur
16. be used after boot via a DMA DMA CONTROLLER The ADSP TS201S processor s on chip DMA controller with 14 DMA channels provides zero overhead data transfers with out processor intervention The DMA controller operates independently and invisibly to the DSP s core enabling DMA operations to occur while the DSP s core continues to execute program instructions The DMA controller performs DMA transfers between internal memory external memory and memory mapped peripherals the internal memory of other DSPs on a common bus a host processor or link port I O between external memory and exter nal peripherals or link port I O and between an external bus master and internal memory or link port I O The DMA con troller performs the following DMA operations External port block transfers Four dedicated bidirectional DMA channels transfer blocks of data between the DSP s internal memory and any external memory or memory mapped peripheral on the external bus These transfers support master mode and handshake mode protocols Link port transfers Eight dedicated DMA channels four transmit and four receive transfer guad word data only between link ports and between a link port and internal or December 2006 ADSP TS201S AAAA ADSP TS201S 7 ADSP TS201S 6 ADSP TS201S 5 ADSP TS201S 4 ADSP TS201S 3 ADSP TS201S 2 1D2 0 RST_IN ADSP TS201S 1 EO CLKS REFS BR7 2 0 BR1 A
17. by on chip decoding of high order address lines to generate memory bank select signals December 2006 The ADSP T82018 processor provides programmable memory pipeline depth and idle cycle for synchronous accesses and external acknowledge controls to support interfacing to pipe lined or slow devices host processors and other memory mapped peripherals with variable access hold and disable time reguirements Host Interface The ADSP TS201S processor provides an easy and configurable interface between its external bus and host processors through the external port see Figure 4 To accommodate a variety of host processors the host interface supports pipelined or slow protocols for ADSP TS201S processor access of the host as slave or pipelined for host access of the ADSP TS201S processor as slave Each protocol has programmable transmission parame ters such as idle cycles pipe depth and internal wait cycles The host interface supports burst transactions initiated by a host processor After the host issues the starting address of the burst and asserts the BRST signal the DSP increments the address internally while the host continues to assert BRST The host interface provides a deadlock recovery mechanism that enables a host to recover from deadlock situations involving the DSP The BOFF signal provides the deadlock recovery mecha nism When the host asserts BOFF the DSP backs off the current transaction and asserts HBG and
18. file LDF allowing the developer to move between the graphical and textual environments Analog Devices DSP emulators use the IEEE 1149 1 JTAG test access port of the ADSP TS201S processor to monitor and con trol the target board processor during emulation The emulator provides full speed emulation allowing inspection and modifi cation of memory registers and processor stacks Nonintrusive in circuit emulation is assured by the use of the processor s JTAG interface the emulator does not affect target system loading or timing In addition to the software and hardware development tools available from Analog Devices third parties provide a wide range of tools supporting the TigersHARC processor family Hardware tools include TigersHARC processor PC plug in cards Third party software tools include DSP libraries real time operating systems and block diagram design tools EVALUATION KIT Analog Devices offers a range of EZ KTT Lite evaluation plat forms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors platforms and software tools Each EZ KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP development and debugging environment with the C C compiler assembler and linker Also included TEZ Kit Lite is a registered trademark of Analog Devices Inc Rev C Page 11 of 48 ADSP TS201S are sample application progr
19. for booting TMROE Timer expires This output pulses whenever timer 0 expires At reset this is a strap pin For more information see Table 16 on Page 20 I input A asynchronous output OD open drain output T three state P power supply G ground pd internal pull down 5 ko pu internal pull up 5 ko pd_0 internal pull down 5 ko on DSP ID 0 pu_0 internal pull up 5 k2on DSP ID 0 pu_od_0 internal pull up 500 O on DSP ID pd m internal pull down 5 ko on DSP bus master pu m internal pull up 5 ko on DSP bus master pu ad internal pull up 40 ko For more pull down and pull up information see Electrical Characteristics on Page 22 Term termination of unused pins column symbols epd external pull down approximately 5 ko to Vss epu external pull up approx imately 5 kQ to Von jo nc not connected na not applicable always used Von io connect directly to Vpp jo Vss connect directly to Vss Rev C Page 17 of48 December 2006 ADSP TS201S Table 11 Pin Definitions Link Ports Signal Type Term Description LxDATO3 0P o nc Link Ports 3 0 Data 3 0 Transmit LVDS P LxDATO3 0N O nc Link Ports 3 0 Data 3 0 Transmit LVDS N LxCLKOUTP o nc Link Ports 3 0 Transmit Clock LVDS P LxCLKOUTN o nc Link Ports 3 0 Transmit Clock LVDSN LxACKI I pd nc Link Ports 3 0 Receive Acknowledge Using this signal the receiver indicates to the transmitter that it may continue th
20. is active when accessing an odd address word on a 64 bit memory bus to disable the write of the low word HDOM O T nc High Word SDRAM Data Mask When sampled high three states the SDRAM DQ pu 0 buffers HDOM is valid on SDRAM transactions when CAS is asserted and inactive on read transactions On write transactions HDOM is active when accessing an even address in word accesses or when memory is configured for a 32 bit bus to disable the write of the high word SDA10 O T nc SDRAM Address Bit 10 Separate A10 signals enable SDRAM refresh operation while pu 0 the DSP executes non SDRAM transactions SDCKE nc SDRAM Clock Enable Activates the SDRAM clock for SDRAM self refresh or suspend pu_m modes A slave DSP in a multiprocessor system does not have the pull up or pull pd_m down A master DSP or ID in a single processor system has a pull up before granting the bus to the host except when the SDRAM is put in self refresh mode In self refresh mode the master has a pull down before granting the bus to the host SDWE l O T nc SDRAM Write Enable When sampled low while CAS is active SDWE indicates an pu 0 SDRAM write access When sampled high while CAS is active SDWE indicates an SDRAM read access In other SDRAM accesses SDWE defines the type of operation to execute according to SDRAM specification I input A asynchronous O output OD open drain output T three state P power supply G g
21. its own triple buffered guad word input and double buffered guad word output registers The DSP s core can write directly to a link port s transmit register and read from a receive register or the DMA controller can perform DMA transfers through eight four transmit and four receive dedi cated link port DMA channels Each link port direction has three signals that control its opera tion For the transmitter LXCLKOUT is the output transmit clock LxACKI is the handshake input to control the data flow and the LxBCMPO output indicates that the block transfer is complete For the receiver LXCLKIN is the input receive clock LxACKO is the handshake output to control the data flow and the LxBCMPI input indicates that the block transfer is com plete The LxDATO3 0 pins are the data output bus for the transmitter and the LxDAT13 0 pins are the input data bus for the receiver Applications can program separate error detection mechanisms for transmit and receive operations applications can use the checksum mechanism to implement consecutive link port transfers the size of data packets and the speed at which bytes are transmitted TIMER AND GENERAL PURPOSE I O The ADSP TS201S processor has a timer pin TMROE that generates output when a programmed timer counter has expired and four programmable general purpose I O pins FLAG3 0 that can function as either single bit input or out put As outputs these pins can signal peripheral devices
22. nications overhead Provides on chip arbitration for glueless multiprocessing DATA ADDRESS GENERATION 24M BITS INTERNAL MEMORY SOC BUS JTAG PORT INTEGER INTEGER MEMORY BLOCKS be J ALU PAGE CACHE EXTERNAL PROGRAM 32 BIT x 32 BIT 32 BIT x 32 BIT i x CROSSBAR CONNECT SEQUENCER A ADDR k J BUS ADDR FETCH K J BUS DATA 12 K BUS ADDR BTB K K BUS DATA y I BUS ADDR m I BUS DATA CLU DAB DAB Y REGISTER FILE CLU 32 BIT x 32 BI COMPUTATIONAL BLOCKS Figure 1 Functional Block Diagram TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices Inc Rev C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved ADSP TS201S
23. open drain output T three state P power supply G ground pd internal pull down 5 ko pu internal pull up 5 ko pd 0 internal pull down 5 k2on DSP ID 0 pu_0 internal pull up 5 kR on DSP ID 0 pu_od_0 internal pull up 500 on DSP ID 0 pd_m internal pull down 5 kQ on DSP bus master pu_m internal pull up 5 kQ on DSP bus master pu_ad internal pull up 40 ko For more pull down and pull up information see Electrical Characteristics on Page 22 Term termination of unused pins column symbols epd external pull down approximately 5 ko to Vss epu external pull up approx imately 5 to Von jo nc not connected na not applicable always used Von io connect directly to Vpp 0 Vss connect directly to Vss Rev C Page 18 of48 December 2006 Table 13 Impedance Control Selection ADSP TS201S CONTROLIMP1 0 Driver Mode 00 recommended 01 10 default 11 Normal Reserved A D Mode Reserved Table 14 Drive Strength Output Impedance Selection DS2 0 Drive Output Pins Strength Impedance 000 Strength O 11 196 26 001 Strength 1 23 896 320 010 Strength 2 36 5 40 011 Strength 3 49 296 50 Q 100 Strength 4 61 9 62 101 default Strength 5 74 696 70Q 110 Strength 6 87 3 96 Q 111 Strength 7 100 1200 CONTROLIMPI 0 A D mode disabled CONTROLIMPI 1 A D mode enabled Table 15 Pin Definitions Power
24. registers DATA63 0 nc External Data Bus The DSP drives and receives data and instructions on these pins pu_ad Pull up or pull down resistors on unused DATA pins are unnecessary RD epu Memory Read RD is asserted whenever the DSP reads from any slave in the system pu 0 excluding SDRAM When the DSP is a slave RD is an input and indicates read trans actions that access its internal memory or universal registers In a multiprocessor system the bus master drives RD RD changes concurrently with ADDR pins WRL 1 0 T epu Write Low WRL is asserted in two cases when the ADSP TS201S processor writes to pu an even address word of external memory orto another external bus agent and when the ADSP TS201S processor writes to a 32 bit zone host memory or DSP programmed to 32 bit bus An external master host or DSP asserts WRL for writing to a DSP s low word of internal memory In a multiprocessor system the bus master drives WRL WRL changes concurrently with ADDR pins When the DSP is a slave WRL is an input and indicates write transactions that access its internal memory or universal registers WRH VO T epu Write High WRH is asserted when the ADSP TS201S processor writes a long word pu 0 64 bits or writes to an odd address word of external memory or to another external bus agent on a 64 bit data bus An external master host or another DSP must assert WRH for writing to a DSP s high word of 64 bit data bus In a mul
25. sink and or an air flow source may be reguired Table 34 shows the thermal characteristics of the 25 mm x 25 mm BGA_ED package All parameters are based on a JESD51 9 four layer 2s2p board All data are based on 3 W power dissipation Table 34 Thermal Characteristics for 25 mm x 25 mm Package Parameter Condition Typical Unit 0 4 Airflow 0 m s 12 9 C W Airflow 1 m s 10 2 C W Airflow 2 m s 9 0 C W Airflow 3 m s 8 0 C W Og 7 7 C W Oc 0 7 C W 1 0j measured per JEDEC standard JESD51 6 20 12 9 C W for m s is for vertically mounted boards For horizontally mounted boards use 17 0 C W for 0 m s s Dm measured per JEDEC standard JESD51 9 10c measured by cold plate test method no approved JEDEC standard Rev C Page 40 of 48 December 2006 ADSP TS201S 976 BALL BGA_ED PIN CONFIGURATIONS Figure 46 shows a summary of pin configurations for the 576 ball BGA_ED package and Table 35 lists the signal to ball assignments o0ooooooooooooooooo o0ooooooooooooooooo O e Xi X X K X X Xi X OXKHEHHHHNNHHKNNHHHLXO OSG HHHHHNNHHNNHEHHXO o X HEH eeeeennuo eeeeenmoo eeeeeNNKO NNX o G HHKX eeeoeoemmbxo eooo o NNKO NNLX O O HH HHM CO Oo X EHe eeeeeoemmxo OSGHHHHHNNHHNNHHHLXO bi EH EB EB EB EB NL BN EB HB NI NI
26. systems must provide a clean power supply to power input Vpp a Designs must pay critical attention to bypassing the Vpp A supply FILTERING REFERENCE VOLTAGE AND CLOCKS Figure 6 and Figure 7 show possible circuits for filtering Vir and SCLK Vapr These circuits provide the reference voltages for the switching voltage reference and system clock reference Vooo O VREF R1 2kO SERIES RESISTOR 1 R2 2 55 SERIES RESISTOR 1 C1 1pF CAPACITOR SMD C2 1nF CAPACITOR HF SMD PLACED CLOSE TO DSP S PINS Figure 6 Ver Filtering Scheme CLOCK DRIVER VOLTAGE OR SCLK Vger Vpp io R1 R2 C1 C2 Vss R1 2kO SERIES RESISTOR 196 R2 2 55kQ SERIES RESISTOR 196 C1 1pF CAPACITOR SMD C2 1nF CAPACITOR HF SMD PLACED CLOSE TO DSP S PINS IF CLOCK DRIVER VOLTAGE gt Vpp 10 Figure 7 SCLK Var Filtering Scheme DEVELOPMENT TOOLS The ADSP TS201S processor is supported with a complete set of CROSSCORE software and hardware development tools including Analog Devices emulators and VisualDSP devel opment environment The same emulator hardware that supports other TigerSHARC processors also fully emulates the ADSP TS201S processor TCROSSCORE is a registered trademark of Analog Devices Inc VisualDSP is a registered trademark of Analog Devices Inc Rev C Page 10 of 48 The VisualDSP project management environment lets pro grammers develop and debug an application This environment include
27. the external port or a link port IRQEN Interrupt Enable pd 0 disable and set IRO3 0 interrupts to edge sensitive after reset default 1 enable and set IRO3 0 interrupts to level sensitive immediately after reset LINK DWIDTH TMROE Link Port Input Default Data Width pd 0 1 bit default 1 4 bit SYS REG VVE BUSLOCK SYSCON and SDRCON Write Enable pd 0 0 one time writable after reset default 1 always writable TM1 L1BCMPO Test Mode 1 Do not overdrive default value during reset pu TM2 1 L2BCMPO Test Mode 2 Do not overdrive default value during reset pu TM3 13 Test Mode 3 Do not overdrive default value during reset pu I input A asynchronous O output OD open drain output T three state P power supply G ground pd internal pull down 5 ko pu internal pull up 5 ko pd internal pull down 5 ko on DSP ID 0 pu_0 internal pull up 5 k2on DSP ID 0 pu_od_0 internal pull up 500 2 on DSP ID 0 pd m internal pull down 5 ko on DSP bus master pu m internal pull up 5 ko on DSP bus master pu ad internal pull up 40 ko For more pull down and pull up information see Electrical Characteristics on Page 22 When default configuration is used no external resistor is needed on the strap pins To apply other configurations a 500 Q resistor connected to Vpp ro is required If providing external pull downs do not strap these pins directly to Vss t
28. wide internal data buses each con necting to the six 4M bit memory banks enable guad word data instruction and I O access and provide 33 6G bytes per second of internal memory bandwidth Operating at 600 MHz the ADSP TS201S processor s core has a 1 67 ns instruction cycle time Using its single instruction multiple data SIMD features the ADSP TS201S processor can perform 4 8 billion 40 bit MACS or 1 2 billion 80 bit MACS per second Table 1 shows the DSP s performance benchmarks Table 1 General Purpose Algorithm Benchmarks at 600 MHz Clock Benchmark Speed Cycles 32 bit algorithm 1 2 billion MACS s peak performance 1K point complex FFT Radix2 15 7 us 9419 64K point complex FFT Radix2 2 33 ms 1397544 FIR filter per real tap 0 83 ns 0 5 8 x 8 8 x 8 matrix multiply complex floating point 2 3 us 1399 16 bit algorithm 4 8 billion MACS s peak performance 256 point complex FFT Radix 2 0 975 us 585 DMA transfer rate External port 1G bytes s n a Link ports each 1G bytes s n a Cache preloaded The ADSP TS201S processor is code compatible with the other TigerSHARC processors The Functional Block Diagram on Page 1 shows the ADSP TS201S processor s architectural blocks These blocks include e Dual compute blocks each consisting of an ALU multi plier 64 bit shifter 128 bit CLU and 32 word register file and associated data alignment buffers DABs e Dual integer ALUs IALUs each
29. with its own 31 word register file for data addressing and a status register A program seguencer with instruction alignment buffer IAB and branch target buffer BTB Rev C Page3of48 ADSP TS201S An interrupt controller that supports hardware and soft ware interrupts supports level or edge triggers and supports prioritized nested interrupts Four 128 bit internal data buses each connecting to the six 4M bit memory banks e On chip DRAM 24M bit An external port that provides the interface to host proces sors multiprocessing space DSPs off chip memory mapped peripherals and external SRAM and SDRAM e A 14 channel DMA controller Four full duplex LVDS link ports Two 64 bit interval timers and timer expired pin An 1149 1 IEEE compliant JTAG test access port for on chip emulation Figure 2 on Page 3 shows a typical single processor system with external SRAM and SDRAM Figure 4 on Page 8 shows a typical multiprocessor system ADSP TS201S BOOT EPROM OPTIONAL REFERENCE MEMORY OPTIONAL SDRAM MEMORY OPTIONAL HOST PROCESSOR INTERFACE OPTIONAL ADDR DATA DMA DEVICE OPTIONAL DATA DEVICES 4 MAX OPTIONAL CONTROL DATA o o LI m a a CONTROLIMP1 0 BM Figure 2 ADSP TS201S Single Processor System with External SDRAM December 2006 ADSP TS201S The TigerSHARC DSP uses a Static Superscala
30. 0 90 100 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE pF LOAD CAPACITANCE pF Figure 42 Typical Output Rise and Fall Time 10 to 90 Vp 2 5 V Figure 45 Typical Output Valid Vpp jo 2 5 V vs Load Capacitance at Max vs Load Capacitance at Strength 5 Case Temperature and Strength 0 to 7 The line eguations for the output valid vs load capacitance are Strength 0 y 0 1255x 2 7873 Strength 1 y 0 0764x 1 0492 TRENGTH 6 S Strength 2 y 0 0474x 1 0806 Von ro 2 5V Strength 3 y 0 0345x 1 2329 Strength 4 y 0 0296x 1 2064 a Strength 5 y 0 0246x 1 0944 Strength 6 y 0 0187x 1 1005 Strength 7 y 0 0156x 1 084 d a z lt o m RISE TIME FALL TIME Y 0 0377x 0 0374x 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE pF Figure 43 Typical Output Rise and Fall Time 10 to 90 Vpp jo 2 5 V vs Load Capacitance at Strength 6 Rev C Page 39 of48 December 2006 ADSP TS201S ENVIRONMENTAL CONDITIONS The ADSP TS201S processor is rated for performance under Tecase environmental conditions specified in the Operating Con ditions on Page 21 Thermal Characteristics The ADSP TS201S processor is packaged in a 25 mm x 25 mm thermally enhanced ball grid array BGA_ED The ADSP TS201S processor is specified for a case temperature Tcase To ensure that the Tcasg data sheet specification is not exceeded a heat
31. 14 Lyon Tuer yi4 Negus U15 Vss V15 Vbp DRAM W15 Von DRAM Y15 Von io U16 Vss V16 VpD_DRAM W16 Von pRAM Y16 Vss r IVs VI7 Vpp wi7 Vop Y17 Mate U18 Vp V18 von W18 Vop Y18 Vss U19 Vp V19 V w19 Vo Y19 ae U20 Vooo V20 Vop io W20 Ion e Y20 Vss U21 L1CLKINN V21 L1DATI3_N W21 L1CLKON Y21 L1DATO1_N U22 L1CLKINP V22 L1DATI3 P W22 L1CLKOP Y22 L1DATO1_P U23 L1DATI1 N V23 L1DATI2_N W23 L1DATO3_N Y23 L1DATO2_N U24 L1DATI1 P V24 L1DATI2 P W24 L1DATO3_P Y24 L1DATO2_P AAT FLAG2 ABI Vs AC1 FLAGO ADI Vs AA2 FLAG1 AB2 Vs AC2 Vs AD2 101 AA3 1803 AB3 Vs AC3 Voss Ivo io Vs ABA NC ACA TMS ADA TRST AA5 RQO AB5 IRQ2 AC5 TOVVR AD5 TORD AA6 OEN AB6 RQ AC6 DMAR2 AD6 DMAR3 AA7 DMARO AB7 DMAR1 AC7 CPA AD7 DPA AA8 HBR AB8 HBG AC8 BOFF AD8 BUSLOCK AA9 L3BCMPO AB9 L3ACKI AC9 L3DATOO_N AD9 L3DATOO_P AA10 L3DATO1_N AB10 L3DATO1_P AC10 L3CLKON AD10 L3CLKOP AA11 L3DATO3_N AB11 L3DATO3_P AC11 L3DATO2_N AD11 L3DATO2 P AA12 Vss AB12 Vss AC12 L3DATI3_N AD12 L3DATI3 P AA13 L3DATI2 N AB13 L3DATI2 P AC13 L3CLKINN AD13 L3CLKINP AA14 L3DATI1_N AB14 L3DATI1_P AC14 L3DATIO_N AD14 L3DATIO_P AA15 NC AB15 Vss AC15 L3ACKO AD15 L3BCMPI AA16 L2DATOO N AB16 L2DATOO P AC16 L2BCMPO AD16 L2ACKI AA17 L2CLKON AB17 L2CLKOP AC17 L2DATO1_N AD17 L2DATO1_P AA18 L2DATO3_N AB18 L2DATO3_P AC18 L2DATO2_N AD18 L2DATO2_P AA19 L2CLKINN AB19 L2CLKINP AC19 L2DATI3_N AD19 L2DATI3_P AA20 L2DATI1_N AB20 L2DATI1_P AC20 L2DATI2_N AD20 L2DATI2_
32. 2 Xt ak ns FLAG3 0 FLAG3 0 Input 2Xtsc ns 2Xtsc k ns TMROE Timer 0 Expired ns 1m 5T These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference For output specifications on FLAG3 0 pins see Table 29 his pin is a strap option During reset an internal resistor pulls the pin low Table 22 Reference Clocks Core Clock CCLK Cycle Time Parameter Description Grade 060 600 MHz Min Max Grade 050 500 MHz Min Max Unit 1 Core Clock Cycle Time 1 67 12 5 2 0 12 5 ns 1 CCLK is the internal processor clock or instruction cycle time The period of this clock is equal to the system clock period tsc x divided by the system clock ratio SCLKRAT2 0 For information on available part numbers for different internal processor clock rates see the Ordering Guide on Page 46 ccLk CCLK Figure 9 Reference Clocks Core Clock CCLK Cycle Time Rev C Page 24 of 48 December 2006 ADSP TS201S Table 23 Reference Clocks System Clock SCLK Cycle Time SCLKRAT 4x 6x 8x 10x 12x SCLKRAT 5x 7x Parameter Description Min Max Min Max Unit tade System Clock Cycle Time 8 50 8 50 ns tscLKH System Clock Cycle High Time 0 40 X tscik 0 60 x tscik 0 45 X tscik 0 55 X tscik ns tscLkL System Clock Cycle Low Time 0 40 X tscix 0 60 x tscix 0 45 X tscix 0 55 X tscix ns tscike Syst
33. 5 C 600 MHz 24M bit 1 20 Vbo 2 5 1 6 pram BP 576 576 Ball BGA_ED ADSP TS201SABPZ0505 40 C to 85 C 500 MHz 24M bit 11 05 Ven 2 5 1 5 Von pram BP 576 576 Ball BGA ED ADSP TS201SYBPZ0503 40 C to 105 C 500 MHz 24M bit 11 05 Men 2 5 Vopn 1 5 Vbo BP 576 576 Ball BGA ED Represents case temperature The instruction rate is the same as the internal processor core clock CCLK rate 37 Pb free part Rev C Page 46 of 48 December 2006 ADSP TS201S Rev C Page470f48 December 2006 ADSP TS201S 2006 Analog Devices Inc All rights reserved Trademarks and ANALOG zx L DEV CES registered trademarks are the property of their respective ovvners Rev C Page 48 of 48 December 2006
34. 8 DATA34 C8 DATA35 D8 DATA36 A9 DATA29 B9 DATA30 C9 DATA31 D9 DATA32 A10 DATA25 B10 DATA26 C10 DATA27 D10 DATA28 A11 DATA23 B11 DATA24 C11 DATA21 D11 DATA22 A12 DATA19 B12 DATA20 C12 DATA17 D12 DATA18 A13 DATA15 B13 DATA16 C13 ya 013 Vg A14 DATA11 B14 DATA12 C14 DATA13 D14 DATA14 A15 DATA9 B15 DATA10 C15 DATA7 D15 DATA8 A16 DATA5 B16 DATA6 C16 DATA3 D16 DATA4 A17 DATA1 B17 DATA2 C17 ACK D17 DATAO A18 WRL B18 WRH C18 RD D18 BRST A19 ADDR30 B19 ADDR31 C19 ADDR26 D19 ADDR27 A20 ADDR28 B20 ADDR29 C20 ADDR24 D20 ADDR25 A21 ADDR22 B21 ADDR23 C21 ADDR20 D21 Vss A22 V B22 Vs C22 liye D22 ADDR19 A23 ADDR21 823 Vs C23 ING D23 ADDR17 A24 Vs B24 ADDR18 C24 Win ia D24 ADDR16 E1 DATA61 F1 DATA63 G1 MSSD1 H1 Vss E2 DATA62 F2 MST G2 Vss H2 MSH E3 DATA57 F3 DATA59 G3 MSO H3 MSSD3 E4 DATA58 F4 DATA60 G4 BMS H4 SCLKRATO E5 Vss F5 Vpp io G5 Vss H5 Vop io E6 6 Yes G6 Vop H6 Vo E7 Vss F7 Voo G7 Voo H7 Voo E8 Von io F8 Vop G8 Von H8 V E9 Vss F9 Voo G9 Voo H9 Vss 210 Ion e F10 Juve 610 Vip H10 Vs E11 Vop io F11 Von DRAM G11 Von pRAM H11 Vss E12 Von jo F12 Von pRAM G12 Von DRAM H12 Vss E13 Med F13 Us G13 CS H13 Vg E14 Von io F14 Voo G14 Vo H14 Vs E15 jo F15 VpD_DRAM G15 Von pRAM H15 Vss E16 Vss F16 Von DRAM G16 Von pRAM H16 Vss E17 Von 10 F17 Von G17 Vo H17 Vs E18 Vss F18 Vop 618 Vp H18 Ivan E19 Wa F19 Vie G19 Nes H19 Ivan E20 Vss F20 Visio G20 Vu H20 Jee E21 ADDR15 F21 AD
35. A asynchronous O output OD open drain output T three state P power supply G ground pd internal pull down 5 ko pu internal pull up 5 ko pd 0 internal pull down 5 ko on DSP ID 0 pu internal pull up 5 ko on DSP ID 0 pu_od_0 internal pull up 500 on DSP ID 0 pd m internal pull down 5 ko on DSP bus master pu m internal pull up 5 ko on DSP bus master pu ad internal pull up 40 ko For more pull down and pull up information see Electrical Characteristics on Page 22 Term termination of unused pins column symbols epd external pull down approximately 5 ko to Vss epu external pull up approx imately 5 to Von jo nc not connected na not applicable always used Von io connect directly to Vpp io Vss connect directly to Vss See the reference on Page 11 to the JTAG emulation technical reference EE 68 Table 10 Pin Definitions Flags Interrupts and Timer Signal Type Term Description FLAG3 0 nc FLAG pins Bidirectional input output pins can be used as program conditions Each pin pu can be configured individually for input or for output FLAG3 0 are inputs after povver up and reset IRQ3 0 V A nc Interrupt Request When asserted the DSP generates an interrupt Each ofthe IRQ3 0 pins pu can beindependently setfor edge triggered or level sensitive operation After reset these pins are disabled unless the IRQ3 0 strap option and interrupt vectors are initialized
36. ANALOG DEVICES KEY FEATURES Up to 600 MHz 1 67 ns instruction cycle rate 24M bits of internal on chip DRAM memory 25 mm x 25 mm 576 ball thermally enhanced ball grid array package Dual computation blocks each containing an ALU a multiplier a shifter a register file and a communications logic unit CLU Dual integer ALUs providing data addressing and pointer manipulation Integrated I O includes 14 channel DMA controller external port four link ports SDRAM controller programmable flag pins two timers and timer expired pin for system integration 1149 1 IEEE compliant JTAG test access port for on chip emulation Single precision IEEE 32 bit and extended precision 40 bit floating point data formats and 8 16 32 and 64 bit fixed point data formats TigerSHARC Embedded Processor ADSP TS201S KEY BENEFITS Provides high performance static superscalar DSP operations optimized for telecommunications infrastructure and other large demanding multiprocessor DSP applications Performs exceptionally well on DSP algorithm and I O benchmarks see benchmarks in Table 1 Supports low overhead DMA transfers between internal memory external memory memory mapped peripherals link ports host processors and other multiprocessor DSPs Eases DSP programming through extremely flexible instruc tion set and high level language friendly DSP architecture Enables scalable multiprocessing systems with low commu
37. C and assembly programs with the VisualDSP debugger programmers can e View mixed C C and assembly code interleaved source and object information Insert breakpoints Set conditional breakpoints on registers memory and stacks Trace instruction execution Perform linear or statistical profiling of program execution Fill dump and graphically plot the contents of memory Perform source level debugging e Create custom debugger windows The VisualDSP IDE lets programmers define and manage DSP software development Its dialog boxes and property pages let programmers configure and manage all of the TigerSHARC processor development tools including the color syntax high lighting in the VisualDSP editor This capability permits programmers to e Control how the development tools process inputs and generate outputs e Maintain a one to one correspondence with the tool s command line switches The VisualDSP Kernel VDK incorporates scheduling and resource management tailored specifically to address the mem ory and timing constraints of DSP programming These capabilities enable engineers to develop code more effectively December 2006 eliminating the need to start from the very beginning vvhen developing nev application code The VDK features include threads critical and unscheduled regions semaphores events and device flags The VDK also supports priority based pre emptive cooperative and tim
38. DDR31 0 Ki DATA31 0 o lll y LINK DEVICES CONTROL RESET d ID2 0 RST IN CLKS REFS DATA31 4 ADSP TS201S 0 ADDR31 1 CLOCK hd REFERENCE REFERENCE LxDATO3 0P N LxCLKINP N CONTROLIMP1 0 DS2 0 JTAG CONTROL Hmm iH 1177 S poses LxCLKOUTP N TR LINK LxACKI MSSD DEVICES a LxBCMPO SE MAX Le LxDATI3 0P N de OPTIONAL CAS CONTROL ADDRESS 14 ADDRESS GLOBAL AND MEMORY PERIPHERALS OPTIONAL EPROM inm HOST OPTIONAL PROCESSOR INTERFACE OPTIONAL SDRAM MEMORY OPTIONAL Figure 4 ADSP TS201S Shared Memory Multiprocessing System external memory These transfers only use handshake mode protocol DMA priority rotates between the four receive channels e AutoDMA transfers Two dedicated unidirectional DMA channels transfer data received from an external bus master to internal memory or to link port I O These transfers only use slave mode protocol and an external bus master must initiate the transfer The DMA controller provides these additional features e Flyby transfers Flyby operations only occur through the external port DMA Channel 0 and do not involve the DSP s core The DMA controller acts as a conduit to trans fer data from an I O device to exte
39. DR13 G21 ADDR7 H21 ADDR3 E22 ADDR14 F22 ADDR12 G22 ADDR6 H22 ADDR2 E23 ADDR11 F23 ADDR9 G23 ADDR5 H23 ADDR1 E24 ADDR10 F24 ADDR8 G24 ADDR4 H24 ADDRO Rev C Page 42 048 December 2006 ADSP TS201S Table 35 576 Ball 25 mm x 25 mm BGA_ED Ball Assignments Continued Ball No Signal Name Ball No Signal Name Ball No Signal Name Ball No Signal Name n RAS K1 SDA10 L1 SDVVE M1 BR3 22 CAS K2 SDCKE L2 BRO M2 SCLKRAT1 J3 Vss K3 LDQM L3 BRT M3 BR5 J4 VREF K4 HDQM L4 BR2 M4 BR6 J5 Vss K5 Von 1o L5 Von io M5 Vpp io J6 Vbo K6 Vos L6 Von M6 Vbo J7 Vbo K7 Vop L7 Vs M7 Von J8 Vss K8 Vss L8 Vss M8 Vss J9 Vss K9 Vss L9 Vss M9 Vss J10 Vss K10 Vss L10 Vss Min Vs J11 Vss K11 Vss L11 Vss M11 Vss J12 Vss K12 Vss L12 Vss M12 Vs J13 Vss K13 Vss L13 Vss M13 Vs J14 Vss K14 Vss L14 Vss MIA Vs J15 Vss K15 Vss L15 Vss 15 Vs J16 Vss K16 Vss L16 Vss M16 Vs J17 Vss K17 Vss L17 Vss 17 Vss J18 Von K18 Von DRAM L18 VED DRAM M18 Von J19 Von K19 VpD_DRAM L19 VED DRAM M19 Von J20 Vss K20 Vict L20 Vono M20 Vpp io J21 LOACKO K21 LODATI1_N L21 LODATI3_N M21 Vss J22 LOBCMPI K22 LODATI1_P L22 LODATI3_P M22 Vs J23 LODATIO_N K23 LOCLKINN L23 LODATI2_N M23 LODATO3_N J24 LODATIO_P K24 LOCLKINP L24 LODATI2 P M24 LODATO3 P N1 IDO P1 SCLK R1 Vss T1 RST_IN N2 Vss P2 SCLK_VREF R2 NC SCLK T2 SCLKRAT2 N3 Vss R3 NC SCLK_VREF T3 BR4 N4 Von A P4 BM R4 BR7 T4 DS0 N5 Von io P5
40. ITIONS Parameter Description Test Conditions Grade Min Typ Max Unit Von Internal Supply Voltage CCLK 600 MHz 060 1 14 1 20 1 26 V CCLK 500 MHz 050 1 00 1 05 1 10 V a Analog Supply Voltage CCLK 600 MHz 060 1 14 1 20 1 26 V CCLK 500 MHz 050 1 00 1 05 1 10 V 1 0 Supply Voltage all 2 38 2 50 263 V Vop Gau Internal DRAM Supply Voltage CCLK 600 MHz 060 1 52 1 60 1 68 V CCLK 500 MHz 050 1 425 1 500 1 575 V Tease Case Operating Temperature A 40 85 C Tease Case Operating Temperature W 40 4105 C Vu High Level Input Voltage 5 Von Mon Max all 1 7 3 63 V Vi High Level Input Voltage Vo jo all 1 9 3 63 V Vu Low Level Input Voltage Vo Min all 0 33 40 8 V lop Von Supply Current Typical Activity eCCLK 600 MHz Vpp 1 20 V Tcase 25 C 1060 2 90 A Q CCLK 500 MHz Von 1 05 V Tc 25 C 1050 2 06 A Jop A Von a Supply Current Typical Activity CCLK 600 MHz Mon 1 20 V Tease 25 C 060 25 55 mA CCLK 500 MHz Vpp 1 05 V Tease 25 C 1050 20 50 mA Ipp io Von io Supply Current Typical Activity SCLK 62 5 MHz Vpp jo 2 5 V Tase 25 C all 0 15 A lus Bon pram Supply Current Typical Activity amp CCLK 600 MHz Vpp pram 1 6 V Tease 25 C 060 0 28 043 A CCLK 500 MHz Vpp pram 1 5 V Tease 25 C 050 0 25 040 A VREF Voltage Reference all Vpp io X0 56 5 V SCLK Veer Voltage Refere
41. Must Be Constant SCLKRAT2 08 Static Pins Must Be Constant ENEDREG Static Pins Must Be Connected to Vs STRAP SYS 10 Strap Pins 1 5 0 5 SCLK JTAG SYS 12 JTAG System Pins 42 5 10 0 4120 1 0 TCK The external port protocols employ bus IDLE eycles for bus mastership transitions as well as slave access boundary crossings to avoid any potential bus contention The apparent driver overlap due to output disables being larger than output enables is not actual For input specifications on FLAG3 0 pins see Table 21 3 These input pins are asynchronous and therefore do not need to be synchronized to a clock reference For additional requirement details see Reset and Booting on Page 9 RST_IN clock reference is the falling edge of SCLK TDO output clock reference is the falling edge of TCK 7 Reference clock depends on function These pins may change only during reset recommend connecting it to Vpp ro Vss STRAP pins include BMS BM BUSLOCK TMROE LIBCMPO L2BCMPO and L3BCMPO 9Specifications applicable during reset only HJTAG system pins include RST_IN OUT POR IN IRO3 0 DMAR3 0 HBR BOFF MS1 0 MSH SDCKE LDQM HDOM BMS IOWR IORD BM EMU SDA10 IOEN BUSLOCK TMROE DATA63 0 ADDR31 0 RD WRL WRH BRST MSSD3 0 RAS CAS SDWE HBG BR7 0 FLAG3 0 LODATOP3 0 LODATON3 0 LIDATOP3 0 LIDATON3 0 L2DATO
42. P AA21 Vss AB21 L2ACKO AC21 L2DATIO_N AD21 L2DATIO_P AA22 LTBCMPO AB22 Vs AC22 Een AD22 Vpp o AA23 LIDATOO N AB23 Ion io AC23 Na AD23 L2BCMPI AA24 LIDATOO P AB24 Vpo io AC24 LIACKI AD24 Vs 1 On revision 1 x silicon the R2 and R3 balls are NC On revision 0 x silicon the R2 ball is SCLK and the R3 ball is SCLK Ver For more information on SCLK and SCLK Vu on revision 0 x silicon see the EE 179 ADSP TS20x TigerSHARC System Design Guidelines on the Analog Devices website www analog com Rev C Page440f48 December 2006 ADSP TS201S OUTLINE DIMENSIONS The ADSP TS201S processor is available in a 25 mm x 25 mm 576 ball metric thermally enhanced ball grid array BGA_ED package with 24 rows of balls BP 576 25 20 25 00 gt 24 22 20 18 16 14 12 10 8 6 4 2 Y 24 80 Y 23 21 19 17 15 13 131 9 7 5 3 1 oooo oo ooooooooo A oooo oo ooooooooo B 1 25 e 1 00 oooo oo ooooooooo C D l oooo oo ooooooooo 100 Y ATBALL BSC oooo oo 000000000 D E INDICATOR oooo oo ooooooooolF 0 75 oooo oo ooooooooo G oooo oo ooooooooo H 23 00 05 oe as peso Li y oo oo oo ooool L oo oo oo oooolM SO oo oo oo oooo N oo oo oo 100 1977999 oooooooooooooooo R ooo oo ooooooooooo oooo T BSC oooooo 0000000000000000 U BALL 2oosooosecoocoooococoocc W PITCH ooo oo ooooooooooo oooo Y ooo oo ooooooooooo oooo AA ooo oo ooooooooooo oooo AB ooo oo ooooooooooo oooo AC oooooo ooooo
43. P3 0 LADATON3 0 L3DATOP3 0 L3DATON3 0 LOCLKOUTP LOCLKOUTN LICLKOUTP LICLKOUTN L2CLKOUTP L2CLKOUTN L3CLKOUTP L3CLKOUTN LOACKI LIACKI L2ACKI L3ACKI LODATIP3 0 LODATIN3 0 LIDATIP3 0 LIDATIN3 0 LADATIP3 0 L2DATIN3 0 L3DATIP3 0 L3DATIN3 0 LOCLKINP LOCLKINN LICLKINP LICLKINN L2CLKINP L2CLKINN L3CLKINP L3CLKINN LOACKO L ACKO L2ACKO L3ACKO ACK CPA DPA LOBCMPO LIBCMPO L2BCMPO L3BCMPO LOBCMPI LIBCMPI L2BCMPI L3BCMPI ID2 0 CTRL_IMPD1 0 SCLKRAT2 0 DS2 0 ENEDREG system output timing clock reference is the falling edge of TCK REFERENCE CLOCK INPUT SIGNAL OUTPUT SIGNAL OUTPUT VALID OUTPUT 1 25V HOLD THREE STATE OUTPUT DISABLE OUTPUT ENABLE Figure 15 General AC Parameters Timing Rev C Page 29 of 48 December 2006 ADSP TS201S Link Port Low Voltage Differential Signal LVDS Electrical Characteristics and Timing Table 30 and Table 31 with Figure 16 provide the electrical characteristics for the LVDS link ports The LVDS link port sig nal definitions represent all differential signals with a Vop 0 V level and use signal naming without N negative and P posi tive suffixes see Figure 17 Table 30 Link Port LVDS Transmit Electrical Characteristics Parameter Description Test Conditions Min Max Unit Vou Output Voltage High Vo p or Vo n R 100 Q 1 85 V
44. Page 22 Term termination of unused pins column symbols epd external pull down approximately 5 ko to Vss epu external pull up approx imately 5 kQ to Von jo nc not connected na not applicable always used Von io connect directly to Vpp io Vss connect directly to Vss Table 12 Pin Definitions Impedance Control Drive Strength Control and Regulator Enable Signal Type Term Description CONTROLIMPO I pd na Impedance Control As shown in Table 13 the CONTROLIMP1 0 pins select between CONTROLIMP1 I pu na normal driver mode and A D driver mode When using normal mode recommended the output drive strength is set relative to maximum drive strength according to Table 14 When using A D mode the resistance control operates in the analog mode where drive strength is continuously controlled to match a specific line impedance as shown in Table 14 DS2 0 I pu na Digital Drive Strength Selection Selected as shown in Table 14 For drive strength calcu DS1 I pd lation see Output Drive Currents on Page 36 The drive strength for some pins is preset not controlled by the DS2 0 pins The pins that are always at drive strength 7 10096 include CPA DPA TDO EMU and RST_OUT The drive strength for the ACK pin is always x2 drive strength 7 100 ENEDREG I pu Vss Connect the ENEDREG pin to Vss Connect the Vpp pram pins to a properly decoupled DRAM power supply I input A asynchronous O output OD
45. Pins 1 5 0 5 4 0 1 0 SCLK BM Bus Master Debug Aid Only 4 0 1 0 SCLK ORD I O Read Pin 4 0 1 0 1 0 2 0 SCLK OVVR I O Write Pin 4 0 1 0 1 15 2 0 SCLK OEN UO Enable Pin 4 0 1 0 1 15 2 0 SCLK CPA Core Priority Access High to Low 1 5 0 5 4 0 1 0 0 75 2 0 SCLK Core Priority Access Lovv to High 1 5 0 5 29 5 2 0 0 75 2 0 SCLK DPA DMA Priority Access High to Lovv 1 5 0 5 4 0 1 0 0 75 2 0 SCLK DMA Priority Access Low to High 1 5 0 5 29 5 2 0 0 75 2 0 SCLK BMS Boot Memory Select 4 0 1 0 115 120 SCLK FLAG3 0 FLAG Pins 4 0 1 0 1 15 2 0 SCLK RST IN Global Reset Pin 1 5 2 5 m SCLI TMS Test Mode Select JTAG 1 5 0 5 TCK TDI Test Data Input JTAG 1 5 0 5 TCK TDO Test Data Output UTAG 4 0 1 0 0 75 2 0 TCK TRST Test Reset JTAG 1 5 0 5 TCK EMU Emulation High to Low 5 5 2 0 1 15 14 0 TCK or SCLK ID2 05 Static Pins Must Be Constant CONTROLIMP1 05 Static Pins Must Be Constant Rev C Page 28 of48 December 2006 ADSP TS201S Table 29 AC Signal Specifications Continued All values in this table are in nanoseconds D 9 k 5 F s s T o 9 I W a Uu w I EI E w m di 3 p 3 2 v M 2 E 2 E 2x ec ec ex U ur ez 22 z 122 62 lee 386 Name Description z zs o2 JOS OS JOS cu DS2 08 Static Pins
46. absolute maximum rating conditions for extended periods may affect device reliability Table 20 Absolute Maximum Ratings Parameter Rating Internal Core Supply Voltage Vpp 0 3 V to 1 4 V Analog PLL Supply Voltage Vpp a 0 3 V to 1 4 V External I O Supply Voltage Vpp io 0 3 V to 3 5 V External DRAM Supply Voltage Vpp pram 0 3 V to 2 1 V Input Voltage 0 63 V to 3 93 V Output Voltage Swing 0 5 V to Vpp jo 0 5 V Storage Temperature Range 65 C to 150 C 1 Applies to 10 transient duty cycle For other duty cycles see Table 18 Brand Key Field Description t Temperature Range pp Package Type Z Lead Free Option optional ccc See Ordering Guide LLLLLLLLL L Silicon Lot Number R R Silicon Revision yyww Date Code VVVVVV Assembly Lot Code ESD SENSITIVITY ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary circuitry damage may occur 4 on devices subjected to high energy ESD Therefore proper ESD precautions should be take to avoid performance degradation or loss of functionality Rev C Page 23 of 48 December 2006 ADSP TS201S TIMING SPECIFICATIONS With the exception of DMAR3 0 IRO3 0 TMROE and FLAG3 0 input only pins all ac timing for the ADSP TS201S processor is relative to a reference clock edge Because input setup hold output vali
47. ams power supply and a USB cable All evaluation versions of the software tools are limited for use only with the EZ KIT Lite product The USB controller on the EZ KIT Lite board connects the board to the USB port of the user s PC enabling the VisualDSP evaluation suite to emulate the on board processor in circuit This permits the customer to download execute and debug programs for the EZ KIT Lite system It also allows in circuit programming of the on board flash device to store user specific boot code enabling the board to run as a standalone unit without being connected to the PC With a full version of VisualDSP installed sold separately engineers can develop software for the EZ KIT Lite or any custom defined system Connecting one of Analog Devices JTAG emulators to the EZ KIT Lite board enables high speed nonintrusive emulation DESIGNING AN EMULATOR COMPATIBLE DSP BOARD TARGET The Analog Devices family of emulators are tools that every DSP developer needs in order to test and debug hardware and software systems Analog Devices has supplied an IEEE 1149 1 JTAG test access port TAP on each JTAG DSP The emulator uses the TAP to access the internal features of the DSP allowing the developer to load code set breakpoints observe variables observe memory and examine registers The DSP must be halted to send data and commands but once an operation has been completed by the emulator the DSP system is set running at
48. an set up a total of eight circular buffers The IALUs handle address pointer wraparound automatically reducing overhead increas ing performance and simplifying implementation Circular buffers can start and end at any memory location Because the IALU s computational pipeline is one cycle deep in most cases integer results are available in the next cycle Hard ware register dependency check causes a stall if a result is unavailable in a given cycle PROGRAM SEOUENCER The ADSP TS201S processor s program seguencer supports the following e A fully interruptible programming model with flexible pro gramming in assembly and C C languages handles hardware interrupts with high throughput and no aborted instruction cycles A 10 cycle instruction pipeline four cycle fetch pipe and six cycle execution pipe computation results available two cycles after operands are available Supply of instruction fetch memory addresses the seguencer s instruction alignment buffer IAB caches up to five fetched instruction lines waiting to execute the pro gram seguencer extracts an instruction line from the IAB and distributes it to the appropriate core component for execution e Management of program structures and program flow determined according to JUMP CALL RTI RTS instruc tions loop structures conditions interrupts and software exceptions e Branch prediction and a 128 entry branch target buffer BTB to reduce branch de
49. ata from nonaligned addresses Normally load instruc tions must be aligned to their data size so that quad words are loaded from a quad aligned address Using the DAB signifi cantly improves the efficiency of some applications such as FIR filters DUAL INTEGER ALU IALU The ADSP TS201S processor has two IALUs that provide pow erful address generation capabilities and perform many general purpose integer operations The IALUs are referred to as J and K in assembly syntax and have the following features Provide memory addresses for data and update pointers Support circular buffering and bit reverse addressing Perform general purpose integer operations increasing programming flexibility Include a 31 word register file for each IALU As address generators the IALUs perform immediate or indi rect pre and post modify addressing They perform modulus and bit reverse operations with no constraints placed on mem ory addresses for the modulus data buffer placement Each IALU can specify either a single dual or quad word access from memory December 2006 The IALUs have hardware support for circular buffers bit reverse and zero overhead looping Circular buffers facilitate efficient programming of delay lines and other data structures required in digital signal processing and they are commonly used in digital filters and Fourier transforms Each IALU pro vides registers for four circular buffers so applications c
50. d hold and output enable disable times are relative to a clock edge the timing data for the ADSP TS201S processor has few calculated formula based values For information on ac timing see General AC Timing For information on link port transfer timing see Link Port Low Voltage Differential Signal LVDS Electrical Characteristics and Timing on Page 30 General AC Timing The general ac timing data appears in Table 22 and Table 29 All ac specifications are measured with the load specified in Figure 36 on Page 38 and with the output drive strength set to strength 4 In order to calculate the output valid and hold times for different load conditions and or output drive strengths refer to Figure 37 on Page 38 through Figure 44 on Page 39 Rise and Fall Time vs Load Capacitance and Figure 45 on Page 39 Out put Valid vs Load Capacitance and Drive Strength The ac asynchronous timing data for the 1RQ3 0 DMAR3 0 FLAG3 0 and TMROE pins appears in Table 21 Timing is measured on signals when they cross the 1 25 V level as described in Figure 15 on Page 29 All delays in nanosec onds are measured between the point that the first signal reaches 1 25 V and the point that the second signal reaches 1 25 V Table 21 AC Asynchronous Signal Specifications Name Description Pulse Width Low Min Pulse Width High Min IRQ3 0 Interrupt Request 2 xtsc ns 2 X ak ns DMAR3 0 DMA Request 2x ts ns
51. e Note that this graph or derating does not apply to output disable delays see Output Disable Time on Page 37 The graphs of Figure 37 through Figure 45 may not be linear outside the ranges shown TO 500 OUTPUT A OL CER 1 25V PIN T 30pF Figure 36 Eguivalent Device Loading for AC Measurements Includes AlI Fixtures STRENGTH 0 io 2 5V FALL TIME 0 251x 4 2245 RISE TIME RISE AND FALL TIMES ns Y 0 259x 3 0842 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE pF Figure 37 Typical Output Rise and Fall Time 10 to 9096 Vpp 2 5 V vs Load Capacitance at Strength 0 Rev C Page 38 of 48 STRENGTH 1 1o 2 5V FALL TIME Y 0 1527 0 7485 RISE AND FALL TIMES ns RISE TIME 0 1501x 0 05 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE pF Figure 38 Typical Output Rise and Fall Time 10 to 90 Vpp io 2 5 V vs Load Capacitance at Strength 1 STRENGTH 2 Vpp 2 5V 25 m D 20 l amp 15 a z H FALL TIME 2 Y 0 0949x 0 8112 1 5 RISE TIME Y 0 0861x 0 4712 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE pF Figure 39 Typical Output Rise and Fall Time 10 to 90 Vpp io 2 5 V vs Load Capacita
52. e 18 0 4 X tici kop 0 6 X tici kop ns tcoyr LxCLKOUT Jitter Figure 18 1504 6 ps 2507 ps tipos LxDATO Output Setup Figure 20 0 25 x LCR x tay 0 10 x tea 8 ns 0 25 x LCR x tc 0 15 x tea 28 ns 0 25 x LCR x teq 0 30 x tec 7 ns LxDATO Output Hold Figure 20 0 25 x LCR x t ak 0 10 x tec ns 0 25 x LCR x tcc k 0 15 xtcg 9 ns 0 25 x LCR xtcax 0 30 x teg 78 ns LACKID Delay from LxACKI rising edge to first transmission 16 x LCR x ns clock edge Figure 21 BCMPOV LxBCMPO Valid Figure 21 2xLCRxt uk ns BCMPOH LxBCMPO Hold Figure 22 3x TSW 0 57 ns Inputs LACKIS LxACKI low setup to guarantee that the transmitter stops transmitting Figure 22 LxACKI high setup to guarantee that the transmitter continues its transmission without any interruption Figure 23 16 x LCR x tec ns l ACKIH LxACKI High Hold Time Figure 23 0 51 ns Timing is relative to the 0 differential voltage Vop 0 LCR link port clock ratio 1 1 5 2 or 4 tcc is the core period 3 For the cases Of trcygop 2 0 ns and trcrgop 12 5 ns the effect of t oyr specification on output period must be considered 4LCR 1 SLCR 1 5 SLCR 2 7LCR 4 The typos and tipon values include LCLKOUT jitter TSW is a short word transmission period For a 4 bit link it is 2 x LCR x tccyg For a 1 bit link it is 8 x LCR X tecyx ns Rev C Page310f48 December 2006 ADSP TS201S
53. e sliced scheduling approaches In addition the VDK was designed to be scalable If the application does not use a specific feature the support code for that feature is excluded from the target system Because the VDK is a library a developer can decide whether to use it or not The VDK is integrated into the VisualDSP development environment but can also be used via standard command line tools When the VDK is used the development environment assists the developer with many error prone tasks and assists in managing system resources automating the gen eration of various VDK based objects and visualizing the system state when debugging an application that uses the VDK VCSE is Analog Devices technology for creating using and reusing software components independent modules of sub stantial functionality to guickly and reliably assemble software applications It also is used for downloading components from the Web dropping them into the application and publishing component archives from within VisualDSP VCSE supports component implementation in C C or assembly language Use the expert linker to visually manipulate the placement of code and data on the embedded system view memory use in a color coded graphical form easily move code and data to differ ent areas of the DSP or external memory with a drag of the mouse and examine runtime stack and heap usage The expert linker is fully compatible with existing linker definition
54. e transmission LxBCMPO O pu nc Link Ports 3 0 Block Completion When the transmission is executed using DMA this signal indicates to the receiver that the transmitted block is completed The pull up resistor is present on LOBCMPO only At reset the LTBCMPO L2BCMPO and LSBCMPO pins are strap pins For more information see Table 16 on Page 20 LxDATI3 0P 1 Von io Link Ports 3 0 Data 3 0 Receive LVDS P LxDATI3 ON Von io Link Ports 3 0 Data 3 0 Receive LVDS N LxCLKINP VA Von io Link Ports 3 0 Receive Clock LVDS P LxCLKINN VA Link Ports 3 0 Receive Clock LVDSN LxACKO O nc Link Ports 3 0 Transmit Acknowledge Using this signal the receiver indicates to the transmitter that it may continue the transmission LxBCMPI I pd_l Vss Link Ports 3 0 Block Completion When the reception is executed using DMA this signal indicates to the receiver that the transmitted block is completed I input A asynchronous O output OD open drain output T three state P power supply G ground pd internal pull down 5 ko pu internal pull up 5 ko pd internal pull down 5 ko on DSP ID internal pull up 5 ko on DSP ID 0 pu_od_0 internal pull up 500 on DSP ID 0 pd m internal pull down 5 ko on DSP bus master pu m internal pull up 5 ko on DSP bus master pu ad internal pull up 40 ko pd_l internal pull down 50 ko For more pull down and pull up information see Electrical Characteristics on
55. em Clock Transition Time Falling Edge 1 5 1 5 ns tscikn System Clock Transition Time Rising Edge 1 5 1 5 ns tsciig System Clock Jitter Tolerance 500 500 ps For more information see Table 3 on Page 12 For more information see Clock Domains on Page 9 3 The value of tsi SCLKRAT2 0 must not violate the specification for tccrg System clock transition times apply to minimum SCLK cycle time only Actual input jitter should be combined with ac specifications for accurate timing analysis Jitter specification is maximum peak to peak time interval error TIE jitter tscik tscLkF tscLkH scLKL SCLK Figure 10 Reference Clocks System Clock SCLK Cycle Time Table 24 Reference Clocks JTAG Test Clock TCK Cycle Time Parameter Description Min Max Unit trek Test Clock JTAG Cycle Time Greater of 30 or t ak X4 ns rckH Test Clock JTAG Cycle High Time 12 ns trek Test Clock JTAG Cycle Low Time 12 ns TCK Figure 11 Reference Clocks JTAG Test Clock TCK Cycle Time Rev C Page 25 of 48 December 2006 ADSP TS201S Table 25 Power Up Timing Parameter Min Max Unit Timing Reguirement VDD DRAM Vpp DRAM Stable After Von Vpp A Von io Stable gt 0 ms For information about power supply seguencing and monitoring solutions please visit www analog com seguencing
56. est Pins Enable external I O devices to reguest DMA services from the DSP In response to DMARx the DSP performs DMA transfers according to the DMA channel s initialization The DSP ignores DMA reguests from uninitialized channels OVVR O T nc 1 0 Write When a DSP DMA channel initiates a flyby mode read transaction the DSP pu asserts the IOWR signal during the data cycles This assertion makes the UO device sample the data instead of the TigerSHARC ORD O T nc I O Read When a DSP DMA channel initiates a flyby mode write transaction the DSP pu 0 asserts the lORD signal during the data cycle This assertion with the IOEN makes the I O device drive the data instead of the TigerSHARC OEN O T nc I O Device Output Enable Enables the output buffers of an external I O device for fly pu 0 by transactions between the device and external memory Active on flyby transactions I input A asynchronous O output OD open drain output T three state P power supply G ground pd internal pull down 5 ko pu internal pull up 5 ko pd 0 internal pull down 5 ko on DSP ID 0 pu internal pull up 5 k2on DSP ID 0 pu_od_0 internal pull up 500 on DSP ID 0 pd m internal pull down 5 ko on DSP bus master pu m internal pull up 5 ko on DSP bus master pu ad internal pull up 40 ko For more pull down and pull up information see Electrical Characteristics on Page 22 Term termination of unused pins col
57. full speed with no impact on system timing To use these emulators the target board must include a header that connects the DSP s JTAG port to the emulator For details on target board design issues including mechanical layout single processor connections multiprocessor scan chains signal buffering signal termination and emulator pod logic see the EE 68 Analog Devices JTAG Emulation Technical Reference on the Analog Devices website www analog com use the string EE 68 in site search This document is updated regularly to keep pace with improvements to emulator support ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP TS201S processor s architecture and functionality For detailed information on the ADSP TS201S processor s core architecture and instruction set see the ADSP TS201 Tiger SHARC Processor Hardware Reference and the ADSP TS201 TigerSHARC Processor Programming Reference For detailed information on the development tools for this processor see the VisualDSP User s Guide for TigerSHARC Processors December 2006 ADSP TS201S PIN FUNCTION DESGRIPTIONS While most of the ADSP TS201S processor s input pins are nor The output pins can be three stated during normal operation mally synchronous tied to a specific clock a few are The DSP three states all output pins during reset allowing these asynchronous For these asynchronous signals an on chip syn pins to get to their
58. gnal Type Term Description BR7 0 1 0 102 0 w x BOFF l BUSLOCK O T pu_0 T al pu 0 CPA 1 0 OD pu_od 0 DPA 1 0 OD pu_od 0 1 Von na na epu na epu epu epu epu Multiprocessing Bus Reguest Pins Used by the DSPs in a multiprocessor system to arbitrate for bus mastership Each DSP drives its own BRx line corresponding to the value of its ID2 0 inputs and monitors all others In systems with fewer than eight DSPs set the unused BRx pins high Vpp 10 Multiprocessor ID Indicates the DSP s ID from which the DSP determines its order in a multiprocessor system These pins also indicate to the DSP which bus reguest BRO BR7 to assert when requesting the bus 000 BRO 001 BRT 010 BR2 011 BR3 100 BRA 101 BR5 110 BR6 or 111 BR7 ID2 0 must have a constant value during system operation and can change during reset only Bus Master The current bus master DSP asserts BM For debugging only At reset this is a strap pin For more information see Table 16 on Page 20 Back Off A deadlock situation can occur when the host and a DSP try to read from each other s bus at the same time When deadlock occurs the host can assert BOFF to force the DSP to relinquish the bus before completing its outstanding transaction Bus Lock Indication Provides an indication that the current bus master has locked the bus At reset this is a stra
59. he strap pins reguire 500 O resistor straps All strap pins are sampled on the rising edge of RST_IN deas sertion edge Each pin latches the strapped pin state state of the strap pin at the rising edge of RST_IN Shortly after deas sertion of RST_IN these pins are reconfigured to their normal functionality These strap pins have an internal pull down resistor pull up resistor or no resistor three state on each pin The resistor type which is connected to the I O pad depends on whether IN is active low or if RST IN is deasserted high Table 17 shows the resistors that are enabled during active reset and during normal operation Rev C Page 20 of 48 Table 17 Strap Pin Internal Resistors Active Reset RST IN 0 vs Normal Operation RST IN 1 Pin RST IN RST IN 1 BMS pd_0 pu BM pd Driven TMROE pd Driven BUSLOCK pd 0 pu 0 L1BCMPO pu Driven L2BCMPO pu Driven L3BCMPO pu Driven pd internal pull down 5 ko pu internal pull up 5 ko pd 0 internal pull down 5 kQ on DSP ID 0 pu_0 internal pull up 5 ko on DSP ID December 2006 ADSP TS201S ADSP TS201S SPECIFICATIONS Note that component specifications are subject to change with out notice For information on link port electrical characteristics see Link Port Low Voltage Differential Signal LVDS Electrical Characteristics and Timing on Page 30 OPERATING COND
60. internal pull up or pull down state Some chronization circuit prevents metastability problems Use the ac pins have an internal pull up or pull down resistor 3090 toler specification for asynchronous signals when the system design ance that maintains a known value during transitions between requires predictable cycle by cycle behavior for these signals different drivers Table 3 Pin Definitions Clocks and Reset Signal Type Term Description SCLKRAT2 0 I pd na Core Clock Ratio The DSP s core clock CCLK rate n x SCLK where n is user programmable using the SCLKRATx pins to the values shown in Table 4 These pins may change only during reset connect these pins to Vpp jo Or Vss All reset specifica tions in Table 25 Table 26 and Table 27 must be satisfied The core clock rate CCLK is the instruction cycle rate SCLK System Clock Input The DSP s system input clock for cluster bus The core clock rate is user programmable using the SCLKRATx pins For more information see Clock Domains on Page 9 RST_IN V A na Reset Sets the DSP to a known state and causes program to be in idle state RST_IN must be asserted a specified time according to the type of reset operation For details see Reset and Booting on Page 9 Table 25 on Page 26 and Figure 13 on Page 26 RST_OUT o na Reset Output ndicates that the DSP reset is complete Connect to POR IN POR_IN VA na Power On Reset for internal DRAM Connect to RST_OUT I
61. lays for efficient execution of conditional and unconditional branch instructions and zero overhead looping correctly predicted branches occur with zero overhead cycles overcoming the five to nine stage branch penalty e Compact code without the requirement to align code in memory the IAB handles alignment Interrupt Controller The DSP supports nested and nonnested interrupts Each inter rupt type has a register in the interrupt vector table Also each has a bit in both the interrupt latch register and the interrupt mask register All interrupts are fixed as either level sensitive or edge sensitive except the IRQ3 0 hardware interrupts which are programmable Rev C Page 5 of 48 ADSP TS201S The DSP distinguishes between hardware interrupts and soft ware exceptions handling them differently When a software exception occurs the DSP aborts all other instructions in the instruction pipe When a hardware interrupt occurs the DSP continues to execute instructions already in the instruction pipe Flexible Instruction Set The 128 bit instruction line which can contain up to four 32 bit instructions accommodates a variety of parallel operations for concise programming For example one instruction line can direct the DSP to conditionally execute a multiply an add and a subtract in both computation blocks while it also branches to another location in the program Some key features of the instruction set include CLU instr
62. led after reset For more information on boot options see the EE 200 ADSP TS20x TigersHARC Processor Boot Loader Kernels Oper ation on the Analog Devices website www analog com CLOCK DOMAINS The DSP uses calculated ratios of the SCLK clock to operate as shown in Figure 5 The instruction execution rateis egual to CCLK A PLL from SCLK generates CCLK which is phase locked The SCLKRATx pins define the clock multiplication of SCLK to CCLK see Table 4 on Page 12 The link port clock is generated from CCLK via a software programmable divisor and the SOC bus operates at 1 2 CCLK Memory transfers to exter nal and link port buffers operate at the SOCCLK rate SCLK also provides clock input for the external bus interface and defines the ac specification reference for the external bus signals The external bus interface runs at the SCLK frequency The maxi mum SCLK frequency is one quarter the internal DSP clock CCLK frequency EXTERNAL INTERFACE CCLK INSTRUCTION RATE SOCCLK PERIPHERAL BUS RATE LxCLKOUT LINK OUTPUT RATE SCLK SCLKRATx SPD BITS LCTLx REGISTER Figure 5 Clock Domains December 2006 ADSP TS201S POWER DOMAINS The ADSP TS201S processor has separate power supply con nections for internal logic Vpp analog circuits Vpp 4 I O buffer Vpp and internal DRAM Vpp pram power supply Note that the analog Vpp A supply powers the clock generator PLLs To produce a stable clock
63. nal Specifications All values in this table are in nanoseconds 9 KI 5 3 5 3 E E 9 ri o wi a Uu aa reg EE En s 25 22 848 82 82 254 S Description 52 62 jos oz 6 Go ADDR31 0 External Address Bus 1 5 0 5 4 0 1 0 1 15 2 0 SCLK DATA63 0 External Data Bus 1 5 0 5 4 0 1 0 1 15 2 0 SCLK MSH Memory Select HOST Line 4 0 1 0 115 12 0 SCLK MSSD3 0 Memory Select SDRAM Lines 1 5 0 5 4 0 1 0 1 0 2 0 SCLK MS1 0 Memory Select for Static Blocks 4 0 1 0 1 15 2 0 SCLK RD Memory Read 1 5 0 5 4 0 1 0 115 12 0 SCLK WRL Write Low Word 1 5 0 5 4 0 1 0 1 15 20 SCLK WRH Write High Word 1 5 0 5 4 0 1 0 1 15 12 0 SCLK ACK Acknovvledge for Data High to Lovv 1 5 0 5 3 6 1 0 1 15 2 0 SCLK Acknowledge for Data Low to High 1 5 0 5 4 2 0 9 1 15 2 0 SCLK SDCKE SDRAM Clock Enable 1 5 0 5 4 0 1 0 1 15 2 0 SCLK RAS Rovv Address Select 1 5 0 5 4 0 1 0 1 15 2 0 SCLK CAS Column Address Select 1 5 0 5 4 0 1 0 1 15 2 0 SCLK SDWE SDRAM Write Enable 1 5 0 5 4 0 1 0 1 15 2 0 SCLK LDQM Lovv VVord SDRAM Data Mask 4 0 1 0 1 15 2 0 SCLK HDQM High VVord SDRAM Data Mask 4 0 1 0 1 15 2 0 SCLK SDA10 SDRAM ADDR10 4 0 1 0 1 15 2 0 SCLK HBR Host Bus Request 1 5 0 5 SCLK HBG Host Bus Grant 1 5 0 5 4 0 1 0 1 15 20 SCLK BOFF Back Off Reguest 1 5 0 5 SCLK BUSLOCK Bus Lock 4 0 1 0 1 15 2 0 SCLK BRST Burst Pin 1 5 0 5 4 0 1 0 1 15 2 0 SCLK BR7 0 Multiprocessing Bus Reguest
64. nal bus for DMA initiated transactions DPA is an open drain output connected to all DSPs in the system If not required in the system leave DPA uncon nected external pull ups will be required for DSP ID 1 through ID 7 I input A asynchronous output OD open drain output T three state P power supply G ground pd internal pull down 5 ko pu internal pull up 5 ko pd internal pull down 5 kQon DSP ID 0 pu_0 internal pull up 5 ko on DSP ID 0 pu_od_0 internal pull up 500 on DSP ID 0 pd_m internal pull down 5 kQ on DSP bus master pu_m internal pull up 5 kQ on DSP bus master pu_ad internal pull up 40 ko For more pull down and pull up information see Electrical Characteristics on Page 22 Term termination of unused pins column symbols epd external pull down approximately 5 ko to Vss epu external pull up approx imately 5 to Von jo nc not connected na not applicable always used Vpp io connect directly to Vpp io Vss connect directly to Vss 1 2 Rev C The BRx pin matching the 1D2 0 input selection for the processor should be left nc if unused For example the processor with ID 000 has BRO nc and BR7 1 Vpp jo This external pull up resistor may be omitted for the ID 000 TigerSHARC processor Page 14oof48 December 2006 ADSP TS201S Table 7 Pin Definitions External Port DMA Flyby Signal Type Term Description DMAR3 0 VA epu DMA Regu
65. nal pull up 40 ko For more pull down and pull up information see Electrical Characteristics on Page 22 Term termination of unused pins column symbols epd external pull down approximately 5 ko to Vss epu external pull up approx imately 5 to Von jo nc not connected na not applicable always used Von io connect directly to Vpp jo Vss connect directly to Vss Rev C Page 19 of48 December 2006 ADSP TS201S STRAP PIN FUNCTION DESCRIPTIONS Some pins have alternate functions at reset Strap options set DSP operating modes During reset the DSP samples the strap option pins Strap pins have an internal pull up or pull down for the default value If a strap pin is not connected to an over driving external pull up pull down or logic load the DSP samples the default value during reset If strap pins are Table 16 Pin Definitions I O Strap Pins connected to logic inputs a stronger external pull up or pull down may be reguired to ensure default value depending on leakage and or low level input current of the logic load To set a mode other than the default mode connect the strap pin to a sufficiently stronger external pull up or pull down Table 16 lists and describes each of the DSP s strap pins Type at Signal Reset On Pin Description EBOOT l BMS EPROM Boot pd_0 0 boot from EPROM immediately after reset default 1 idle after reset and wait for an external device to boot DSP through
66. nce all Vaoc paw X 0 56 5 V Specifications vary for different grades for example SABP 060 SABP 050 SVVBP 050 For more information on part grades see Ordering Guide on Page 46 Vig specification applies to input and bidirectional pins SCLKRAT2 0 SCLK ADDR31 0 DATA63 0 RD WRL WRH ACK BRST BR7 0 BOFF HBR HBG MSSD3 0 RAS CAS SDCKE SDVVE TCK FLAG3 0 DS2 0 ENEDREG 5 Values represent dc case During transitions the inputs may overshoot or undershoot to the voltage shown in Table 18 based on the transient duty cycle The dc case is eguivalent to 10096 duty eycle Vino specification applies to input and bidirectional pins TDI TMS TRST CIMP1 0 ID2 0 LxBCMPI LxACKI POR IN RST_IN IRQ3 0 CPA DPA DMAR3 0 Applies to input and bidirectional pins For details on internal and external power calculation issues including other operating conditions see the EE 170 Estimating Power for the ADSP TS201S on the Analog Devices website Rev C Page 21 0648 December 2006 ADSP TS201S Table 18 Maximum Duty Cycle for Input Transient Voltage Maximum Duty Vin Max V Vin Min V Cyde 3 63 0 33 100 3 64 0 34 90 3 70 0 40 50 3 78 0 48 30 3 86 0 56 17 3 93 0 63 10 The individual values cannot be combined for analys is of a single instance of overshoot or undershoot The worst case observed value must fall within one of the
67. nce at Strength 2 STRENGTH 3 10 2 5V 25 T E 20 z a a 15 a z 4 FALL TIME 10 2 Y 0 0691 5 t RISE TIME Y 0 06x 1 1362 0 L L L 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE pF Figure 40 Typical Output Rise and Fall Time 10 to 9096 Vp 2 5 V vs Load Capacitance at Strength 3 December 2006 ADSP TS201S STRENGTH 4 STRENGTH 7 Vpp 1o 2 5V 2 5V T T 5 8 5 l a 2 a E 2 a o o KE m FALL TIME m RISE Y 0 0592x 1 0629 FALL TIME Y 0 0321 0 0313x 0 RISE TIME Y 0 0573x 0 9789 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE pF LOAD CAPACITANCE pF j j i 0 0 Figure 41 Typical Output Rise and Fall Time 1096 to 9096 Vpp 2 5 V Figure 44 Typical Output Rise and Fall Time 10 to 9096 Von jo 2 5 V vs Load Capacitance at Strength 4 T T STRENGTH 5 Sea io 25V FE T E a z 2 5 A 9 2 S lt m r u o o 2 FALL TIME EE 0 0493x 0 8389 RISE TIME Y 0 0481x 0 7889 0 10 20 30 40 50 60 70 8
68. ng intermediate results Instructions can access the registers in the register file individually vvord aligned in sets of two dual aligned or in sets of four guad aligned e ALU the ALU performs a standard set of arithmetic oper ations in both fixed and floating point formats It also performs logic operations e Multiplier the multiplier performs both fixed and float ing point multiplication and fixed point multiply and accumulate Shifter the 64 bit shifter performs logical and arithmetic shifts bit and bit stream manipulation and field deposit and extraction operations e Communications Logic Unit CLU this 128 bit unit pro vides trellis decoding for example Viterbi and Turbo decoders and executes complex correlations for CDMA communication applications for example chip rate and symbol rate functions Using these features the compute blocks can Provide 8 MACS per cycle peak and 7 1 MACS per cycle sustained 16 bit performance and provide 2 MACS per cycle peak and 1 8 MACS per cycle sustained 32 bit perfor mance based on FIR Execute six single precision floating point or execute 24 fixed point 16 bit operations per cycle providing 3 6G FLOPS or 14 4G s regular operations performance at 600 MHz Perform two complex 16 bit MACS per cycle Execute eight trellis butterflies in one cycle DATA ALIGNMENT BUFFER DAB The DAB is a quad word FIFO that enables loading of quad word d
69. ns each cycle The DSP s flexible memory structure enables DSP core and I O accesses to different memory blocks in the same cycle DSP core access to three memory blocks in parallel one instruction and two data accesses Programmable partitioning of program and data memory Program access of all memory as 32 64 or 128 bit words 16 bit words with the DAB EXTERNAL PORT OFF CHIP MEMORY PERIPHERALS INTERFACE The ADSP TS201S processor s external port provides the DSP s interface to off chip memory and peripherals The 4G word address space is included in the DSP s unified address space Rev C Page 6 of 48 The separate on chip buses four 128 bit data buses and four 32 bit address buses are multiplexed at the SOC interface and transferred to the external port over the SOC bus to create an external system bus transaction The external system bus pro vides a single 64 bit data bus and a single 32 bit address bus The external port supports data transfer rates of 1G byte per second over the external bus The external bus can be configured for 32 bit or 64 bit little endian operations When the system bus is configured for 64 bit operations the lower 32 bits of the external data bus connect to even addresses and the upper 32 bits connect to odd addresses The external port supports pipelined slow and SDRAM proto cols Addressing of external memory devices and memory mapped peripherals is facilitated
70. of 4G bytes per second The cluster bus provides 1G byte per second throughput with a total of 4 8G bytes per second interprocessor bandwidth lim ited by SOC bandwidth SDRAM Controller The SDRAM controller controls the ADSP TS201S processor s transfers of data to and from external synchronous DRAM SDRAM at a throughput of 32 bits or 64 bits per SCLK cycle using the external port and SDRAM control pins The SDRAM interface provides a glueless interface with stan dard SDRAMs 16M bit 64M bit 128M bit 256M bit and 512M bit The DSP supports directly a maximum of four banks of 64M words x 32 bits of SDRAM The SDRAM interface is mapped in external memory in each DSP s unified memory map EPROM Interface The ADSP TS201S processor can be configured to boot from an external 8 bit EPROM at reset through the external port An automatic process which follows reset loads a program from the EPROM into internal memory This process uses 16 wait cycles for each read access During booting the BMS pin func tions as the EPROM chip select signal The EPROM boot procedure uses DMA Channel 0 which packs the bytes into 32 bit instructions Applications can also access the EPROM write flash memories during normal operation through DMA The EPROM or flash memory interface is not mapped in the DSP s unified memory map It is a byte address space limited to a maximum of 16M bytes 24 address bits The EPROM or flash memory interface can
71. omputational and memory transfer data dependencies In addition the ADSP TS201S processor supports SIMD opera tions two ways SIMD compute blocks and SIMD computations The programmer can load both compute blocks with the same data broadcast distribution or different data merged distribution DUAL COMPUTE BLOCKS The ADSP TS201S processor has compute blocks that can exe cute computations either independently or together as a single instruction multiple data SIMD engine The DSP can issue up to two compute instructions per compute block each cycle instructing the ALU multiplier shifter or CLU to perform independent simultaneous operations Each compute block can execute eight 8 bit four 16 bit two 32 bit or one 64 bit SIMD computations in parallel with the operation in the other block These computation units support IEEE 32 bit single precision floating point extended precision 40 bit floating point and 8 16 32 and 64 bit fixed point processing The compute blocks are referred to as X and Y in assembly syn tax and each block contains four computational units an ALU a multiplier a 64 bit shifter a 128 bit CLU and a 32 word register file Register File each compute block has a multiported 32 word fully orthogonal register file used for transferring data between the computation units and data buses and for Static Superscalar is a trademark of Analog Devices Inc Rev C Page 4 of 48 stori
72. ooooooooooolAD 1 1 00 gt 0 BSC 975 TOPVIEW BOTTOM VIEW 3 10 2 94 yf DETAIL A 0 97 BSC 0 60 d 4 0 50 A r 0 40 NOTES 1 1 ALL DIMENSIONS ARE IN MILLIMETERS dana 0 75 4 2 THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0 25 mm OF ITS 0 65 IDEAL POSITION RELATIVE TO THE PACKAGE EDGES 055 0 20 MAX 3 CENTER DIMENSIONS ARE NOMINAL BALL 4 THIS PACKAGE CONFORMS TO JEDEC MS 034 SPECIFICATION DIAMETER DETAIL A Figure 47 576 Ball BGA_ED BP 576 Table 36 is provided as an aid to PCB design For industry standard design recommendations refer to IPC 7351 Generic Requirements for Surface Mount Design and Land Pattern Standard Table 36 BGA Data for Use with Surface Mount Design Package Ball Attach Type Solder Mask Opening Ball Pad Size 576 Ball BGA_ED Nonsolder Mask Defined NSMD 0 69 mm diameter 0 56 mm diameter BP 576 Rev C Page45of48 December 2006 ADSP TS201S ORDERING GUIDE Temperature Instruction On Chip Package Package Model Range Rate DRAM Operating Voltage Option Description ADSP TS201SABP 060 40 C to 85 C 600 MHz 24M bit 11 20 Ven 2 5 Von 1 6 Men pram BP 576 576 Ball BGA_ED ADSP TS201SABP 050 40 C to 85 C 500 MHz 24M bit 11 05 Vpp 2 5 Von jo 1 5 Vop pram BP 576 576 Ball BGA ED ADSP TS201SYBP 050 402 to 105 C 500 MHz 24M bit 1 05 Vbo 2 5 io 1 5 Mon pram BP 576 576 Ball BGA ED ADSP TS201SABPZ0605 40 C to 8
73. p pin For more information see Table 16 on Page 20 Host Bus Request A host must assert HBR to request control of the DSP s external bus When HBR is asserted in a multiprocessing system the bus master relinquishes the bus and asserts HBG once the outstanding transaction is finished Host Bus Grant Acknowledges HBR and indicates that the host can take control of the external bus When relinquishing the bus the master DSP three states the ADDR31 0 DATA63 0 MSH MSSD3 0 MS1 0 RD WRL WRH BMS BRST IORD IOWR IOEN RAS CAS SDWE SDA10 SDCKE LDQM and HDOM pins and the DSP puts the SDRAM in self refresh mode The DSP asserts HBG until the host deasserts HBR In multiprocessor systems the current bus master DSP drives HBG and all slave DSPs monitor it Core Priority Access Asserted while the DSP s core accesses external memory This pin enables a slave DSP to interrupt a master DSP s background DMA transfers and gain control of the external bus for core initiated transactions CPA is an open drain output connected to all DSPs in the system If not required in the system leave CPA unconnected external pull ups will be required for DSP ID 1 through ID 7 DMA Priority Access Asserted while a high priority DSP DMA channel accesses external memory This pin enables a high priority DMA channel on a slave DSP to interrupt transfers of a normal priority DMA channel ona master DSP and gain control of the exter
74. r architecture This architecture is superscalar in that the ADSP TS201S pro cessor s core can execute simultaneously from one to four 32 bit instructions encoded in a very large instruction word VLIW instruction line using the DSP s dual compute blocks Because the DSP does not perform instruction re ordering at runtime the programmer selects which operations will execute in parallel prior to runtime the order of instructions is static With few exceptions an instruction line whether it contains one two three or four 32 bit instructions executes with a throughput of one cycle in a 10 deep processor pipeline For optimal DSP program execution programmers must follow the DSP s set of instruction parallelism rules when encoding an instruction line In general the selection of instructions that the DSP can execute in parallel each cycle depends on the instruc tion line resources each instruction requires and on the source and destination registers used in the instructions The program mer has direct control of three core components the IALUs the compute blocks and the program sequencer The ADSP TS201S processor in most cases has a two cycle execution pipeline that is fully interlocked so whenever a computation result is unavailable for another operation depen dent on it the DSP automatically inserts one or more stall cycles as needed Efficient programming with dependency free instructions can eliminate most c
75. relinguishes the external bus The host can directly read or write the internal memory of the ADSP TS201S processor and it can access most of the DSP reg isters including DMA control TCB registers Vector interrupts support efficient execution of host commands Multiprocessor Interface The ADSP TS201S processor offers powerful features tailored to multiprocessing DSP systems through the external port and link ports see Figure 4 This multiprocessing capability pro vides the highest bandwidth for interprocessor communication including Up to eight DSPs on a common bus On chip arbitration for glueless multiprocessing e Link ports for point to point communication The external port and link ports provide integrated glueless multiprocessing support The external port supports a unified address space see Figure 3 that enables direct interprocessor accesses of each ADSP TS201S processor s internal memory and registers The DSP s on chip distributed bus arbitration logic provides simple glueless connection for systems containing up to eight ADSP TS201S processors and a host processor Bus arbitration has a rotating priority Bus lock supports indivisible read modify write seguences for semaphores A bus fairness feature prevents one DSP from holding the external bus too long Rev C Page 7 of 48 ADSP TS201S The DSP s four link ports provide a second path for interproces sor communications with throughput
76. rents at Strength 6 STRENGTH 7 Jo 2 63V 40 C Vpp 2 5V 25 C Vpp 2 63V A0 Vpp 2 38V 105 C Vpp jo 2 5V 25 C Von io 2 38V 105 C lon 0 4 0 8 12 1 6 2 0 24 2 8 OUTPUT PIN VOLTAGE V Figure 33 Typical Drive Currents at Strength 7 Rev C Page 37 of 48 ADSP TS201S TEST CONDITIONS The ac signal specifications timing parameters appear in Table 29 on Page 28 These include output disable time output enable time and capacitive loading The timing specifications for the DSP apply for the voltage reference levels in Figure 34 INPUT OR 1 25V 1 25V OUTPUT Figure 34 Voltage Reference Levels for AC Measurements Except Output Enable Disable Output Disable Time Output pins are considered to be disabled when they stop driv ing go into a high impedance state and start to decay from their output high or low voltage The time for the voltage on the bus to decay by AV is dependent on the capacitive load C and the load current Ij This decay time can be approximated by the fol lowing eguation pecay CLAV I The output disable time tpi is the difference between MEASURED DIS and tpecay as shown in Figure 35 The time MEASURED pis is the interval from when the reference signal switches to when the output voltage decays AV from the mea sured output high or output low voltage tpgcay is calculated with test loads C and 1 and with AV equal to 0 4 V
77. rnal SDRAM memory Rev C Page 8 of 48 During a transaction the DSP relinquishes the external data bus outputs addresses and memory selects MSSD3 0 outputs the TORD TOVVR TOEN and RD WR strobes and responds to ACK e DMA chaining DMA chaining operations enable applica tions to automatically link one DMA transfer sequence to another for continuous transmission The sequences can occur over different DMA channels and have different transmission attributes Two dimensional transfers The DMA controller can access and transfer two dimensional memory arrays on any DMA transmit or receive channel These transfers are implemented with index count and modify registers for both the X and Y dimensions December 2006 LINK PORTS LVDS The DSP s four full duplex link ports each provide additional four bit receive and four bit transmit I O capability using low voltage differential signal LVDS technology VVith the ability to operate at a double data rate latching data on both the rising and falling edges of the clock running at up to 500 MHz each link port can support up to 500M bytes per second per direc tion for a combined maximum throughput of 4G bytes per second The link ports provide an optional communications channel that is useful in multiprocessor systems for implementing point to point interprocessor communications Applications can also use the link ports for booting Each link port has
78. round pd internal pull down 5 ko pu internal pull up 5 ko pd 0 internal pull down 5 ko on DSP ID 0 pu_0 internal pull up 5 kR on DSP ID 0 pu_od_0 internal pull up 500 on DSP ID 0 pd m internal pull down 5 ko on DSP bus master pu m internal pull up 5 ko on DSP bus master pu ad internal pull up 40 ko For more pull down and pull up information see Electrical Characteristics on Page 22 Term termination of unused pins column symbols epd external pull down approximately 5 ko to Vss epu external pull up approx imately 5 to Vpp jo nc not connected na not applicable always used Von io connect directly to Vpp io Vss connect directly to Vss Page 16 of48 December 2006 ADSP TS201S Table9 Pin Definitions JTAG Port Signal Type Term Description EMU O OD nc Emulation Connected to the DSP s JTAG emulator target board connector only TCK 1 epd or epul Test Clock JTAG Provides an asynchronous clock for JTAG scan TDI I pu ad nc Test Data Input JTAG A serial data input of the scan path TDO O T nc Test Data Output JTAG A serial data output of the scan path TMS pu ad nc Test Mode Select JTAG Used to control the test state machine TRST l A pu ad na Test Reset JTAG Resets the test state machine TRST must be asserted or pulsed low after power up for proper device operation For more information see Reset and Booting on Page 9 I input
79. s an easy to use assembler which is based on an alge braic syntax an archiver librarian library builder a linker a loader a cycle accurate instruction level simulator a C C compiler and a C C run time library that includes DSP and mathematical functions A key point for theses tools is C C code efficiency The compiler has been developed for efficient translation of C C code to DSP assembly The DSP has archi tectural features that improve the efficiency of compiled C C code The VisualDSP debugger has a number of important features Data visualization is enhanced by a plotting package that offers a significant level of flexibility This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm As algorithms grow in complexity this capability can have increasing significance on the designer s development schedule increasing productivity Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program This feature unique to VisualDSP enables the software developer to passively gather important code execution metrics without interrupting the real time characteristics of the program Essentially the developer can identify bottlenecks in software quickly and efficiently By using the profiler the programmer can focus on those areas in the program that impact performance and take corrective action Debugging both C
80. tiprocessing system the bus master drives WRH WRH changes concurrently with ADDR pins When the DSP isa slave WRH is an input and indicates write transactions that access its internal memory or universal registers ACK epu Acknowledge External slave devices can deassert ACK to add wait states to external pu od 0 memory accesses ACK is used by I O devices memory controllers and other periph erals on the data phase The DSP can deassert ACK to add wait states to read and write accesses of its internal memory The pull up is 50 O on low to high transactions and is 500 O on all other transactions BMS O T na Boot Memory Select BMS is the chip select for boot EPROM or flash memory During pu 0 reset the DSP uses BMS as a strap pin EBOOT for EPROM boot mode In a multipro cessor system the DSP bus master drives BMS For details see Reset and Booting on Page 9 and the EBOOT signal description in Table 16 on Page 20 MS1 0 O T nc Memory Select MSO or MS1 is asserted whenever the DSP accesses memory banks 0 pu 0 or 1 respectively MS1 0 are decoded memory address pins that change concurrently with ADDR pins When ADDR31 27 0600110 MSO is asserted When ADDR31 27 0b00111 MST is asserted In multiprocessor systems the master DSP drives MS1 0 MSH O T nc Memory Select Host MSH is asserted whenever the DSP accesses the host address pu 0 space ADDR31 061 MSH is a decoded memory address pin that changes concur rently
81. truction fetch Each memory segment contains a 128K bit cache to enable single cycle access to internal DRAM The six internal memory blocks connect to the four 128 bit wide internal buses through a crossbar connection enabling the DSP to perform four memory transfers in the same cycle The DSP s internal bus architecture provides a total memory bandwidth of December 2006 ADSP TS201S INTERNAL SPACE O m m s mem stocks INTERNAL MEMORY BLOCK 6 0x03FFFFFF 0x001F03FF 0x001F0000 0x001 E03FF 0x001 E0000 0x001 SFFFF 0x001 40000 0x001 1FFFF 0x001 00000 0x000DFFFF 0x000C0000 0x0009FFFF INTERNAL MEMORY BLOCK 4 0x00080000 0x0005FFFF 0x00040000 0x0001FFFF 0x00000000 N EXTERNAL MEMORY SPACE LLL N RESERVED GLOBAL SPACE HOST MSH MSSD BANK 3 MSSD3 MSSD BANK 2 MSSD2 MSSD BANK 1 MSSD1 MSSD BANK 0 MSSDO BANK 1 MST BANK 0 50 OxFFFFFFFF 0x80000000 0x74000000 0x70000000 0x64000000 0x60000000 0x54000000 0x50000000 0x44000000 0x40000000 0x38000000 0x30000000 0x2C000000 E 0x28000000 0x24000000 0x20000000 EACH IS A COPY 0x1C000000 OF INTERNAL SPACE 0x18000000 0x14000000 0x10000000 P d 0x0c000000 7 0x03FFFFFF INTERNAL MEMOR Y 0x00000000 Figure 3 ADSP TS201S Memory Map 33 6G bytes per second enabling the core and I O to access eight 32 bit data words and four 32 bit instructio
82. uctions for communications infrastructure to govern trellis decoding for example Viterbi and Turbo decoders and despreading via complex correlations e Algebraic assembly language syntax e Direct support for all DSP imaging and video arithmetic types Eliminates toggling DSP hardware modes because modes are supported as options for example rounding satura tion and others within instructions Branch prediction encoded in instruction enables zero overhead loops Parallelism encoded in instruction line e Conditional execution optional for all instructions e User defined partitioning between program and data memory DSP MEMORY The DSP s internal and external memory is organized into a unified memory map which defines the location address of all elements in the system as shown in Figure 3 The memory map is divided into four memory areas host space external memory multiprocessor space and internal memory and each memory space except host memory is sub divided into smaller memory spaces The ADSP TS201S processor internal memory has 24M bits of on chip DRAM memory divided into six blocks of 4M bits 128K words x 32 bits Each block M0 M2 M4 M6 M8 and M10 can store program instructions data or both so applica tions can configure memory to suit specific needs Placing program instructions and data in different memory blocks however enables the DSP to access data while performing an ins
83. umn symbols epd external pull down approximately 5 ko to Vss epu external pull up approx imately 5 to Von io nc not connected na not applicable always used Von io connect directly to Vpp jo Vss connect directly to Vss Page 15 of48 December 2006 ADSP TS201S Table 8 Pin Definitions External Port SDRAM Controller Signal Type Term Description MSSD3 0 1 O T nc Memory Select SDRAM MSSDO MSSD1 MSSD2 or MSSD3 is asserted whenever the pu 0 DSP accesses SDRAM memory space MSSD3 0 are decoded memory address pins that are asserted whenever the DSP issues an SDRAM command cycle access to ADDR31 30 0b01 except reserved spaces shown in Figure 3 on Page 6 In a multi processor system the master DSP drives MSSD3 0 RAS 1 O T nc Row Address Select When sampled low RAS indicates that a row address is valid in pu 0 a read or write of SDRAM In other SDRAM accesses it defines the type of operation to execute according to SDRAM specification CAS l O T nc Column Address Select When sampled low CAS indicates that a column address is pu 0 valid in a read or write of SDRAM In other SDRAM accesses it defines the type of operation to execute according to the SDRAM specification LDOM O T nc Low Word SDRAM Data Mask When sampled high three states the SDRAM DQ pu 0 buffers LDOM is valid on SDRAM transactions when CAS is asserted and inactive on read transactions On write transactions LDOM
84. voltages specified and the total duration of the overshoot or undershoot exceeding the 10096 case must be less than or equal cycle Duty cycle refers to the percentage of time the signal to the corresponding duty exceeds the value for the 10096 case This is eguivalent to the measured duration of a single instance of overshoot or undershoot as a percentage of the period of occurrence The practical worst case for period of occurrence for either overshoot or undershoot is 2 X t cik ELECTRICAL CHARACTERISTICS Parameterl Description Test Conditions Min Max Unit Vou High Level Output Voltage OVpp jo Min 2 mA 2 18 V VoL Low Level Output Voltage Vpp jo Min lo 4 mA 0 4 V li High Level Input Current OVpp Max Vin Max 20 HA l Pu High Level Input Current Vpp jo Max Vin Vin Max 20 HA lin ep High Level Input Current GVpp Max Vin Vpp io Max 0 3 0 76 mA lii PD L High Level Input Current Gun Max Vin Vi Max 30 76 HA lu Low Level Input Current OVpp Max Vy 2 0 V 20 l pu Low Level Input Current OVpp io Max Via OV 0 3 0 76 mA L PU AD Low Level Input Current Vpp_ jo Max Va OV 30 100 HA lozu Three State Leakage Current High 9 Vpp Vy Vin Max 50 HA Joen Pp Three State Leakage Current High Gun Max Vin Vpp Max 0 3 0 76 mA Three State Leakage Current Lovv OVpp oz Max Vy 2 0 V 20 uA lost pu Three State
85. with ADDR pins In a multiprocessor system the bus master DSP drives MSH BRST l O T epu Burst The current bus master DSP or host asserts this pin to indicate that itis reading pu 0 or writing data associated with consecutive addresses A slave device can ignore addresses after the first one and increment an internal address counter after each transfer For host to DSP burst accesses the DSP increments the address automati cally while BRST is asserted I input A asynchronous output OD open drain output T three state P power supply G ground pd internal pull down 5 ko pu internal pull up 5 ko pd 0 internal pull down 5 ko on DSP ID 0 pu internal pull up 5 k2on DSP ID 0 pu_od_0 internal pull up 500 on DSP ID 0 pd m internal pull down 5 ko on DSP bus master pu m internal pull up 5 ko on DSP bus master pu ad internal pull up 40 ko For more pull down and pull up information see Electrical Characteristics on Page 22 Term termination of unused pins column symbols epd external pull down approximately 5 ko to Vss epu external pull up approx imately 5 to Von jo nc not connected na not applicable always used Von io connect directly to Vpp jo Vss connect directly to Vss This external pull up may be omitted for the ID 000 TigerSHARC processor Page130f48 December 2006 ADSP TS201S Table 6 Pin Definitions External Port Arbitration Si

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