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Microchip Technology dsPIC33F Family Specifications
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1. Register 16 9 ADTPCFGH ADC1 Port Configuration Register High R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24 bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown bit 15 0 PCFG lt 31 16 gt ADC Port Configuration Control bits 2 1 Port pin in Digital mode port read input enabled ADC input multiplexor connected to AVss 0 Port pin in Analog mode port read input disabled ADC samples pin voltage Note 1 On devices with less than 32 analog inputs all PCFG bits are R W by user However PCFG bits are ignored on ports without a corresponding input on device 2 ADC2 only supports analog inputs ANO AN15 therefore no ADC2 Port Configuration register exists Register 16 10 ADxPCFGL ADCx Port Configuration Register Low R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFGO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 B
2. ADIPCFGL OxFFFB all PORTB Digital RB2 analog AD1CON1 0x0000 SAMP bit 0 ends sampling and starts converting ADI1CHSO 0x0002 Connect RB2 AN2 as CHO input in this example RB2 AN2 is the input ADICSSL 0 AD1CON3 0x0002 Manual Sample Tad internal 2 Tcy ADICON2 0 AD1CON1bits ADON 1 turn ADC ON while 1 repeat continuously ADICON1bits SAMP 1 start sampling DelayNmSec 100 for 100 mS ADICON1bits SAMP 0 start Converting while ADICON1bits DONE conversion done ADCValue ADC1BUFO yes then get ADC value repeat Figure 16 6 is an example where setting the ASAM bit initiates automatic sampling and clearing the SAMP bit terminates sampling and starts conversion After the conversion completes the ADC module automatically returns to a sampling state The SAMP bit is automatically set at the start of the sample interval The user software must time the clearing of the SAMP bit to ensure adequate sampling time of the input signal understanding that the time between clearing of the SAMP bit includes the conversion time as well as the sampling time See Example 16 2 for code example Figure 16 6 Converting 1 Channel Automatic Sample Start Manual Conversion Start ADC Clock TE m i EE TSAMP CONV TSAMP TCONV gt TADO amp e TADO 9 SAMP
3. AN11 Dd 9 Dd Xt AN7 Bx tti eoj tt oor oe XxX Xt Xt XI AN30 X 1111055 AN31 Xx iil 5 CHO l __VREF S H ro AN1 F Note 1 VREF VREF inputs can be multiplexed with other analog inputs See device data sheet for details 2 Channels 1 2 and 3 are not applicable for the 12 bit mode of operation 3 The ADC1 module can use all 32 analog input pins AN0 AN31 whereas ADC2 can use only 16 analog input pins ANO AN15 2006 Microchip Technology Inc DS70183A page 16 3 dsPIC33F Family Reference Manual 16 2 CONTROL REGISTERS The ADC module has ten Control and Status registers These registers are ADxCON1 ADCx Control Register 1 1 ADxCON2 ADCx Control Register 2 1 ADxCON3 ADCx Control Register 3 1 ADxCON4 ADCx Control Register 4 1 ADxCHS123 ADCx Input Channel 1 2 3 Select Register 1 ADxCHSO ADCx Input Channel 0 Select Register AD1CSSH ADC1 Input Scan Select Register High ADxCSSL ADCx Input Scan Select Register Low AD1PCFGH ADC1 Port Configuration Register High ADxPCFGL ADCx Port Configuration Register Low The ADxCON1 ADxCON2 and ADxCONG registers control the operation of the ADC module The ADxCON4 register sets up the number of conversion results stored in a DMA buffer for each analog input in the Scatter Gather mode The ADxCHS123 and ADxCHSO registers select the input pins to be connected to the Sample Hold amplifiers The ADXPCFGH L regist
4. DONE f i i 1 1 ADC1BUFO vel X A 2006 Microchip Technology Inc DS70183A page 16 23 dsPIC33F Family Reference Manual Example 16 2 Converting 1 Channel Automatic Sample Start Manual Conversion Start Code D DIPCFGL OxFF7F all PORTB Digital but RB7 analog DICON1 0x0004 ASAM bit 1 implies sampling starts immediately after last conversion is done ADICHSO 0x0007 Connect RB7 AN7 as CHO input in this example RB7 AN7 is the input D ADICSSL 0 AD1CON3 0x0002 Sample time manual Tad internal 2 Tcy ADICON2 0 AD1CON1bits ADON 1 turn ADC ON while 1 repeat continuously DelayNmSec 100 sample for 100 mS ADICON1bits SAMP 0 start Converting while AD1CON1bits DONE conversion done ADCValue ADCIBUFO yes then get ADC value repeat 16 11 2 Clocked Conversion Trigger When SSRC lt 2 0 gt 111 the conversion trigger is under A D clock control The Auto Sample Time SAMC lt 4 0 gt bits AD1CON3 lt 12 8 gt select the number of TAD clock cycles between the start of sam pling and the start of conversion This trigger option provides the fastest conversion rates on multiple channels After the start of sampling the ADC module counts a number of TAD clocks specified by the SANC bits Equation 16 2 Clocked Conversion Trigger Time TSMP SAMC lt 4 0 gt TAD When using only one Sample Hold channel
5. Input to i i CH1 ANO AN3 AN9 AN3 AN9 ANO AN3 AN9 r ASAM l i SsAMP poc py X se 1 i i Cleared 1 DONE i s I in software i BUFS ss i s l i Buffer 0 X s i m i Buffer 1 X 5 i Lo os 1 i Buffer 2 X5 2 1 T 7 ys Buffer 3 X 2 i ERU l Buffer 4 s iss uffer s 1 1 s 1 Buffer 6 j s EE NENNEN T M 8 Buffer 7 is X Looss l l Buffer 8 i gt X ADxIF ss Cleared by Software A 2006 Microchip Technology Inc DS70183A page 16 43 dsPIC33F Family Reference Manual Table 16 5 CONTROL BITS Sequence Select SMPI lt 3 0 gt 0001 AMODE 00 DMAxONT 7 Alt Sampling DMA Interrupt on 8th conversion Converting Two Seis of Two Inputs Using Alternating Input Selections OPERATION SEQUENCE Sample MUX A Inputs AN1 gt CHO ANO gt CH1 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request CHPS lt 1 0 gt 01 Sample Channels CHO CH1 SIMSAM 1 Sample all channels simultaneously Sample MUX B Inputs AN15 gt CHO AN3 ANQ gt CH1 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request BUFM 1 Dual 8 word result buffers Sample MUX A Inputs AN1 gt CHO ANO gt CH1 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and ge
6. bit 11 Unimplemented Read as 0 bit 10 AD12B 10 bit or 12 bit Operation Mode bit 1 12 bit 1 channel ADC operation o 10 bit 4 channel ADC operation bit 9 8 FORM lt 1 0 gt Data Output Format bits For 10 bit operation 11 Signed fractional DOUT sddd dddd dadoo 0000 where s NOT d lt 9 gt 10 Fractional DOUT dddd dddd ddoo 0000 01 Signed integer DOUT 2 ssss sssd dddd dddd where s NOT d lt 9 gt 00 Integer DoUT 0000 00dd dddd dddd For 12 bit operation 11 Signed fractional DOUT sddd dddd dddd 0000 where s NOT d lt 11 gt 10 Fractional DOUT dddd dddd dddd 0000 01 Signed Integer DOUT ssss sddd dddd dddd where s NOT d lt 11 gt 00 Integer DOUT 0000 dddd dddd dddd bit 7 5 SSRC lt 2 0 gt Sample Clock Source Select bits 111 Internal counter ends sampling and starts conversion auto convert 110 Reserved 101 Reserved 100 Reserved 011 MPWM interval ends sampling and starts conversion 010 GP timer Timer3 for ADC1 Timer5 for ADC2 compare ends sampling and starts conversion 001 Active transition on INTx pin ends sampling and starts conversion 000 Clearing sample bit ends sampling and starts conversion bit 4 Unimplemented Read as 0 Note 1 The x in ADxCON1 and ADCx refers to ADC 1 or ADC 2 2006 Microchip Technology Inc DS70183A page 16 5 dsPIC33F Family Reference Manual Register 16 1 bit 3 bit 2 bit 1 bit 0 Note 1 ADx
7. gt CHO convert CHO write ADC1BUFO and generate DMA Request Sample MUX A Inputs AN13 gt CHO convert CHO write ADC1BUFO and generate DMA Request CHONB n a Channel CHO input unused Sample MUX A Inputs AN14 gt CHO convert CHO write ADC1BUFO and generate DMA Request CH123SB n a Channel CH1 CH2 CH3 input unused CH123NB lt 1 0 gt n a Channel CH1 CH2 CH3 input unused Sample MUX A Inputs AN15 gt CHO convert CHO write ADC1BUFO and generate DMA Request Interrupt Repeat DMA Buffer 2 1st DMA Interrupt ANO Sample 1 AN1 Sample 2 AN2 Sample 3 AN3 Sample 4 AN4 Sample 5 AN5 Sample 6 AN6 Sample 7 AN7 Sample 8 AN8 Sample 9 AN9 Sample 10 AN10 Sample 11 AN11 Sample 12 AN12 Sample 13 AN13 Sample 14 AN14 Sample 15 AN15 Sample 16 DS70183A page 16 40 DMA Buffer 2nd DMA Interrupt ANO Sample 17 AN1 Sample 18 AN2 Sample 19 AN3 Sample 20 AN4 Sample 21 AN5 Sample 22 AN6 Sample 23 AN7 Sample 24 AN8 Sample 25 AN9 Sample 26 AN10 Sample 27 AN11 Sample 28 AN12 Sample 29 AN13 Sample 30 AN14 Sample 31 AN15 Sample 32 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 14 3 Sampling Three Inputs Frequently While Scanning Four Other Inputs Figure 16 19 and Table 16 4 show how the ADC module could be configured to sample
8. j Teave e lt 1 Buffer 0 X Buffer 1 y Buffer 2 i i i i i i Buffer 3 Cleared DONE i i i in software SAMP i i i i i i DS70183A page 16 30 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 11 3 7 SAMPLE TIME CONSIDERATIONS FOR AUTOMATIC SAMPLING CONVERSION SEQUENCES Different sample conversion sequences provide different available sampling times for the Sam ple Hold channel to acquire the analog signal You must ensure that the sampling time exceeds the sampling requirements as outlined in Section 16 15 A D Sampling Requirements Assuming that the ADC module is set for automatic sampling and an external trigger pulse is used as the conversion trigger the sampling interval is a portion of the trigger pulse interval If the SIMSAM bit specifies simultaneous sampling the sampling time is the trigger pulse period less the time required to complete the specified conversions Equation 16 5 Available Sampling Time Simultaneous Sampling TSMP Trigger Pulse Interval TSEQ Channels per Sample CH S Conversion Time TCONV TSMP TSEQ CH S TCONV Note 1 CH S is specified by CHPS lt 1 0 gt bits 2 TSEQ is the trigger pulse interval time Ifthe SIMSAM bit specifies sequential sampling the sampling time is the trigger pulse period less the time required to complete o
9. nemen 16 53 16 19 ADG AGCUEQCV EFTOT es oi oti pec Der e EE cede ber it ere pe pog 16 54 16 20 Connection Considerations cccecceeeceeseeeeeeeeeeeeeeeeeaeeeeeeeseaeseaeeeaeeseaeeseeeeseeseneeeaees 16 54 16 21 Gode Examples s 2 2 4 38 Be Rt rer or e ed ans de eet 16 54 16 22 Operation During Sleep and Idle Modes eee 16 61 16 23 Effects of a Reset 42 25 esetes e neg nte ap Ee eee te tie tage ita 16 62 16 24 Special Function Registers Associated with the ADC ssssssesss 16 62 16 25 Design Tips isis aie RU E ee 16 64 16 26 Related Application Notes sssseeeeeeneeen meme 16 65 16 27 Revislon History o Let reich te a ae test 16 66 2006 Microchip Technology Inc DS70183A page 16 1 dsPIC33F Family Reference Manual 16 1 INTRODUCTION The dsPIC33F family devices have up to 32 A D input channels These devices also have up to two ADC modules ADCx where x 1 or 2 each with its own set of Special Function Registers SFRs The 10 bit or 12 bit Operation Mode AD12B bit in the ADCx Control 1 ADxCON1 register allows each of the ADC modules to be configured by the user application as either a 10 bit 4 Sample Hold S H ADC default configuration or a 12 bit 1 Sample Hold ADC Note The ADC module needs to be disabled before the AD12B bit is modified The 10 bit ADC configuration AD12B 0 has the following key features S
10. 0340 ADC2 Data Buffer uuuu AD2CON1 0360 ADON ADSIDL ADDMABM AD12B FORM lt 1 0 gt SSRC lt 2 0 gt SIMSAM ASAM SAMP DONE 0000 AD2CON 0362 VCFG lt 2 0 gt CSCNA CHPS lt 1 0 gt BUFS SMPI 3 0 BUFM ALTS 0000 AD2CON3 0364 ADRC SAMC lt 4 0 gt ADCS lt 5 0 gt 0000 AD2CHS123 0366 CH123NB lt 1 0 gt CH123SB CH123NA lt 1 0 gt CH123SA 0000 AD2CHSO 0368 CHONB CHOSB lt 3 0 gt CHONA CHOSA lt 3 0 gt 0000 AD2PCFGL 036C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFGO 0000 AD2CSSL 0370 CSS15 CSS14 CSS13 CSS12 CSS1 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CS84 CSS3 CSS2 CSS1 CSS0 0000 AD2CON4 0372 DMABL lt 2 0 gt 0000 Legend u unknown Note All interrupt sources and their associated control bits may not be available on a particular device Refer to the device data sheet for details ay auo V H q 0 Hojeuy 9 uonoes dsPIC33F Family Reference Manual 16 25 DESIGN TIPS Question 1 How can I optimize the system performance of the ADC module Answer 1 Make sure you are meeting all of the timing specifications If you are turning the ADC mod ule off and on there is a minimum delay you must wait before taking a sample If you are changing input channels there is a minimum delay you must wait for this as well Finally there is TAD which is
11. AN5 AN6 AN7 CH123SA 0 CH1 ANO CH2 AN1 CH3 AN2 CH123NA lt 1 0 gt 0x CH1 CH2 CH3 VREF Sample MUX A Inputs AN7 gt CHO ANO gt CH1 AN1 gt CH2 AN2 gt CH3 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request Convert CH2 write ADC1BUFO and generate DMA Request Convert CH3 write ADC1BUFO and generate DMA Request MUX B Input Select CHOSB lt 3 0 gt n a Channel CHO input unused CHONB n a Channel CHO input unused CH123SB n a Channel CH1 CH2 CH3 input unused CH123NB lt 1 0 gt n a Channel CH1 CH2 CH3 input unused DMA Buffer 2 1st DMA Interrupt AN4 Sample 1 ANO Sample 1 AN1 Sample 1 AN2 Sample 1 AN5 Sample 1 ANO Sample 2 AN1 Sample 2 AN2 Sample 2 AN6 Sample 1 ANO Sample 3 AN1 Sample 3 AN2 Sample 3 AN7 Sample 1 ANO Sample 4 AN1 Sample 4 AN2 Sample 4 Interrupt Repeat DMA Buffer 2nd DMA Interrupt AN4 Sample 2 ANO Sample 5 AN1 Sample 5 AN2 Sample 5 AN5 Sample 2 ANO Sample 6 AN1 Sample 6 AN2 Sample 6 AN6 Sample 2 ANO Sample 7 AN1 Sample 7 AN2 Sample 7 AN7 Sample 2 ANO Sample 8 AN1 Sample 8 AN2 Sample 8 DS70183A page 16 42 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 14 4 Using Alternating MUX A MUX B Input Sel
12. Configure DMA for Peripheral indirect mode 2 Configure DMA for Continuous Ping Pong mode DMAOPAD int amp ADC1BUFO DMAOCNT SAMP BUFF SIZE 2 1 2006 Microchip Technology Inc DS70183A page 16 59 dsPIC33F Family Reference Manual Example 16 5 Code for Alternate Sampling Using DMA Continued DMAOREQ 13 DMAOSTA _ builtin _dmaoffset amp BufferA 0 0 DMAOSTB _ builtin _dmaoffset amp BufferB 0 0 IFSObits DMAOIF 0 Clear the DMA interrupt flag bit IECObits DMAOIE 1 Set the DMA interrupt enable bit DMAOCONbits CHEN 1 DMAOInterrupt ISR name is chosen from the device linker script unsigned int DmaBuffer 0 void attribute interrupt DMAOInterrupt void if DmaBuffer 0 ProcessADCSamples amp BufferA 4 0 ProcessADCSamples amp BufferA 5 0 else ProcessADCSamples amp BufferB 4 0 ProcessADCSamples amp BufferB 5 0 DmaBuffer 1 tglPin Toggle PORTA BITO IFSObits DMAOIF 0 Clear the DMAO Interrupt Flag void ProcessADCSamples int AdcBuffer Do something with ADC Samples DS70183A page 16 60 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 22 OPERATION DURING SLEEP AND IDLE MODES Sleep and Idle modes are useful for minimizing conversion noise because the digital activity of the CPU buses and other peripherals is minimized 16 22
13. Conversion er a er ce er ee es ee NE Trigger TSAMP gt ISAMP gt ISAMP gt TSAMP gt ADC Clock ss i lt I CONV CONV CONV CONV Input to CHO ANO ANO se ANO ANO ASAM i SAMP ss Fl DONE i i ion Buffer 0 X SS Buffer 1 Buffer 2 k i i X i ss l Buffer 15 ee s i AD1IF s BSET AD1CON1 ASAM X Instruction Execution i l 2006 Microchip Technology Inc DS70183A page 16 37 dsPIC33F Family Reference Manual Table 16 2 Converting One Channel 16 Times per DMA Interrupt CONTROL BITS Sequence Select SMPI lt 3 0 gt 0000 AMODE 00 DMAXCNT 15 DMA Interrupt on 16th conversion OPERATION SEQUENCE Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request CHPS lt 1 0 gt 00 Sample Channel CHO Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and Generate DMA Request SIMSAM n a Not applicable for single channel sample Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request BUFM 0 Single 16 word result buffer Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request ALTS 0 Always use MUX A input select Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request
14. MUX A Input Select CHOSA lt 4 0 gt 00000 Select ANO for CHO input Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request CHONA 0 Select VREF for CHO input Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request CSCNA 0 No input scan Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request CSSL lt 15 0 gt n a Scan input select unused Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request CH123SA n a Channel CH1 CH2 CH3 input unused Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request Sample MUX A Inputs ANO gt CHO convert CHO CH123NA lt 1 0 gt n a Channel CH1 CH2 CH3 input unused write ADC1BUFO and generate DMA Request MUX B Input Select CHOSB lt 4 0 gt n a Channel CHO input unused Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request CHONB n a Channel CHO input unused Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request CH123SB n a Channel CH1 CH2 CH3 input unused CH123NB lt 1 0 gt n a Channel CH1 CH2 CH3 input unused DMA Buffer 2 1st DMA Interrupt ANO Sample
15. The MUX A inputs alternate with the MUX B inputs specified by CH123SB and CH123NB lt 1 0 gt when ALTS 1 16 8 ENABLING THE MODULE When the ADC Operating Mode ADON bit ADxCON1 lt 15 gt is 1 the ADC module is in Active mode and is fully powered and functional When ADON is o the ADC module is disabled The digital and analog portions of the circuit are turned off for maximum current savings In order to return to the Active mode from the Off mode the user must wait for the analog stages to stabilize For the stabilization time refer to the Electrical Characteristics section of the device data sheet Note The SSRC lt 2 0 gt SIMSAM ASAM CHPS lt 1 0 gt SMPI lt 3 0 gt BUFM and ALTS bits as well as the ADxCON3 ADxCSSH and ADxCSSL registers should not be written to while ADON 1 This would lead to indeterminate results 16 9 SPECIFYING SAMPLE CONVERSION CONTROL The ADC module uses four Sample Hold amplifiers and one A D Converter in the 10 bit mode The module can perform 1 2 or 4 input samples and A D conversions per sample convert sequence 16 9 1 Number of Sample Hold Channels The CHPS lt 1 0 gt control bits ADXCON2 9 8 are used to select how many Sample Hold ampli fiers are used by the ADC module during sample conversion sequences The following three options can be selected CHO only CHO and CH1 CHO CH1 CH2 CH3 The CHPS control bits work in conjunction with the SIMSAM si
16. d01 doo Read to Bus Integer O O O O d11 d10 d09 dO8 d07 d06 dO5 d04 d03 d02 d01 doo Signed Integer dt1 dt1 dt1 di1 a11 d10 do9 Taos d07 do6 do5 do4 do3 do2 d01 doo Fractional dtt dio doe doS do7z doe dos do4 ao3 do2 do1 do0 0 o0 0 0 Signed Fractional 1 15 d11 d10 d09 d08 d07 d04 d03 d02 d01 d00 d01 d00 0 0 0 O DS70183A page 16 50 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC Table 16 8 Numerical Equivalents of Various Result Codes 10 bit Mode VIN VREF Guinea de 16 bit Integer Format Shade haus 16 bit Fractional Format Eun utt 1023 1024 11 1111 0000 0011 1111 0000 0001 1111 1111 1111 1100 0111 1111 1100 1111 TTIT 1111 0000 0000 1023 511 0 999 0 499 1022 1024 11 1111 0000 0011 1111 0000 0001 1111 1111 1111 1000 0111 1111 1000 1110 1110 1110 0000 0000 1022 5 10 0 998 0 498 513 1024 10 0000 0000 0010 0000 0000 0000 0000 1000 0000 0100 0 000 0000 0100 0001 0001 0001 0000 0000 7513 zou 0 501 0 001 512 1024 10 0000 0000 0010 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 512 3010 0 500 0 000 511 1024 01 1111 0000 0001 1111 1111 1111 1111 0111 1111 1100 1111 1111 1100 1111 1111 1111 0000 0000 511 zx 499 70 901 1 1024 00 00
17. 1 CPU Sleep Mode without RC A D Clock When the device enters Sleep mode all clock sources to the ADC module are shut down and stay at logic o If Sleep occurs in the middle of a conversion the conversion is aborted unless the ADC is clocked from its internal RC clock generator The converter does not resume a partially com pleted conversion on exiting from Sleep mode Register contents are not affected by the device entering or leaving Sleep mode 16 22 2 CPU Sleep Mode with RC A D Clock The ADC module can operate during Sleep mode if the A D clock source is set to the internal A D RC oscillator ADRC 1 This eliminates digital switching noise from the conversion When the conversion is completed the DONE bit is set and the result is loaded into the ADC Result buffer ADCBUF If the ADC interrupt is enabled ADxIE 1 the device wakes up from Sleep when the ADC interrupt occurs Program execution resumes at the ADC Interrupt Service Routine if the ADC interrupt is greater than the current CPU priority Otherwise execution continues from the instruction after the PWRSAV instruction that placed the device in Sleep mode If the ADC interrupt is not enabled the ADC module is turned off although the ADON bit remains set To minimize the effects of digital noise on the ADC module operation the user should select a conversion trigger source that ensures the A D conversion will take place in Sleep mode The automatic conversi
18. 15 Alt sampling DMA interrupt on 16th conversion Sampling Eight Inputs Using Simultaneous Sampling OPERATION SEQUENCE CHPS lt 1 0 gt 1x Sample Channels CHO CH1 CH2 CH3 SIMSAM 1 Sample all channels simultaneously Sample MUX A Inputs AN13 AN1 gt CHO ANO gt CH1 AN1 gt CH2 AN2 gt CH3 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request Convert CH2 write ADC1BUFO and generate DMA Request Convert CH3 write ADC1BUFO and generate DMA Request BUFM 0 Single 16 word result buffer Sample MUX B Inputs AN14 gt CHO ALTS 1 Alternate MUX A MUX B input select MUX A Input Select CHOSA lt 3 0 gt 1101 Select AN13 for CHO input AN3 AN6 gt CH1 AN4 AN7 gt CH2 AN5 AN8 gt CH3 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request Convert CH2 write ADC1BUFO and generate DMA Request Convert CH3 write ADC1BUFO and generate DMA Request CHONA 1 Select AN1 for CHO input CSCNA 0 No input scan CSSL lt 15 0 gt n a Scan input select unused CH123SA 0 CH1 ANO CH2 AN1 CH3 AN2 CH123NA lt 1 0 gt 0x CH1 CH2 CH3 VREF MUX B Input Select CHOSB lt 3 0 gt 1110 Select AN14 for CHO input Sample MUX A Inputs AN13 AN1 gt CHO ANO gt CH1 AN1 gt CH2 AN2 gt CH3 Convert CHO w
19. Buffer Locations AN7 SAMPLE 4 AN7 BLOCK Unused Buffer Locations m mA MA AMA Mo a 0 AN7 SAMPLE 8 AN31 BLOCK 2006 Microchip Technology Inc DS70183A page 16 35 dsPIC33F Family Reference Manual 16 13 2 USING DMA IN THE CONVERSION ORDER MODE When the AADMABM bit ADCON1 lt 12 gt 1 the Conversion Order mode is enabled In this mode the DMA channel can be configured for Register Indirect or Peripheral Indirect Address ing All conversion results are stored in the user specified DMA buffer area in the same order in which the conversions are performed by the ADC module In this mode the buffer is not divided into blocks allocated to different analog inputs Rather the conversion results from different inputs are interleaved according to the specific buffer fill modes being used In this configuration the buffer pointer is always incremented by one word In this case the SMPI lt 3 0 gt bits ADXCON2 5 2 must be cleared and the DMABL lt 2 0 gt bits ADxCON4 lt 2 0 gt are ignored Figure 16 16 illustrates an example identical to the configuration in Figure 16 15 but using the Conversion Order mode In this example the DMAxCNT register has been configured to gener ate the DMA interrupt after 16 conversion results have been obtained Figure 16 16 DMA Buffer in Conversion Order Mode AN4 SAMPLE 1 ANO SAMPLE 1 AN1 SAMPLE
20. Conversion Clock Select ADCS lt 7 0 gt bits ADxCON3 lt 7 0 gt Equation 16 1 gives the TAD value as a function of the ADCS control bits and the device instruction cycle clock period TCY Equation 16 1 A D Conversion Clock Period TAD Tcy ADCS 1 TAD ADCS 1 Tcv For correct A D conversions the A D conversion clock TAD must be selected to ensure a minimum TAD time of 75 nsec The ADC module has a dedicated internal RC clock source that can be used to perform conversions The internal RC clock source should be used when A D conversions are performed while the device is in Sleep mode The internal RC oscillator is selected by setting the ADC Con version Clock Source ADRC bit ADXCONS 15 When the ADRC bit is set the ADCS lt 7 0 gt bits have no effect on the A D operation Figure 16 4 A D Conversion Clock Period Block Diagram ADxCON3 lt 15 gt ADC Internal RC Clock 0 TAD ADxCON3 lt 7 0 gt 1 1 A D Conversion Clock Multiplier Tcv 1 2 3 4 5 256 2006 Microchip Technology Inc DS70183A page 16 17 dsPIC33F Family Reference Manual 16 7 SELECTING ANALOG INPUTS FOR SAMPLING All Sample Hold Amplifiers have analog multiplexers see Figure 16 1 on both their non invert ing and inverting inputs to select which analog input s are sampled Once the sample convert sequence is specified the ADxCHSO and ADxCHS123 regi
21. Rate for DMA Addresses bits 1111 Increments the DMA address or generates interrupt after completion of every 16th sample conversion operation 1110 Increments the DMA address or generates interrupt after completion of every 15th sample conversion operation 0001 Increments the DMA address or generates interrupt after completion of every 2nd sample conversion operation 0000 Increments the DMA address or generates interrupt after completion of every sample conversion operation bit 1 BUFM Buffer Fill Mode Select bit 1 Starts buffer filling the first half of the buffer on the first interrupt and the second half of the buffer on next interrupt 0 Always starts filling the buffer from the start address bit 0 ALTS Alternate Input Sample Mode Select bit 1 Uses channel input selects for Sample A on first sample and Sample B on next sample 0 Always uses channel input selects for Sample A Note 1 The x in ADXCON2 and ADCx refers to ADC 1 or ADC 2 2006 Microchip Technology Inc DS70183A page 16 7 dsPIC33F Family Reference Manual Register 16 3 ADXCONG3 ADCx Control Register 3 R W 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 ADRC SAMC lt 4 0 gt bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 ADCS lt 7 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit
22. are not enabled having a non zero SMPI lt 3 0 gt value results in overwriting the data in the ADCxBUFO register For example if SMPI 3 0 0011 then every 4th conversion result can be read in the ADC Interrupt Service Routine However if channel scanning is enabled the SMPI 3 0 bits must be set to one less than the number of channels to be scanned Similarly if alternate sampling is enabled the SMPI 3 0 bits must be set to 0001 If DMA transfers are enabled the SMPI 3 0 bit must be cleared except when channel scanning or alternate sampling is used Please refer to Section 16 13 Specifying Conversion Results Buffering for more details on SMPI 3 0 setup requirements When the SIMSAM bit ADxCON1 lt 3 gt specifies sequential sampling regardless of the number of channels specified by the CHPS lt 1 0 gt bits ADXCON2 9 8 the ADC module samples once for each conversion and data sample in the buffer The value specified by the DMAxCNT register for the DMA channel being used corresponds to the number of data samples in the buffer When the SIMSAM bit specifies simultaneous sampling the number of data samples in the buffer is related to the CHPS lt 1 0 gt bits Algorithmically the channels per sample CH S times the num ber of samples results in the number of data sample entries in the buffer To avoid loss of data in the buffer due to overruns the DMAxONT register must be set to the desired buffer size Disabl
23. gt control bits in ADCx Control Reg ister 2 ADXCON2 lt 9 8 gt Note The 12 bit ADC configuration can only perform one conversion in a single sam ple convert sequence The CHPS bits are irrelevant in this case A sample convert sequence that uses multiple Sample Hold channels can be simultaneously sampled or sequentially sampled as controlled by the Simultaneous Sample Select SIMSAM bit ADXCON1 3 Simultaneously sampling multiple signals ensures that the snapshot of the analog inputs occurs at precisely the same time for all inputs Sequential sampling takes a snap shot of each analog input just before conversion starts on that input The sampling of multiple inputs is not correlated Figure 16 3 Simultaneous and Sequential Sampling ANO S OT ZU Nc E ae AN2 nw 2 C uz D Simultaneous Sequential Sampling Sampling The start time for sampling can be controlled in software by setting the ADC Sample Enable SAMP control bit ADxXCON1 lt 1 gt The start of the sampling time can also be controlled auto matically by the hardware When the ADC module operates in the Auto Sample mode the Sam ple Hold amplifier s is reconnected to the analog input pin at the end of the conversion in the sample convert sequence The auto sample function is controlled by the ADC Sample Auto Start ASAM control bit ADXCON1 2 The conversion trigger source ends the sampling time and begins an A D conversion or a sam
24. in Scatter Gather mode The ADC module provides a Scatter Gather address to the DMA channel based on the index of the analog input and the size of the DMA buffer 16 13 1 USING DMA IN THE SCATTER GATHER MODE When the ADDMABM bit is o the Scatter Gather mode is enabled In this mode the DMA chan nel must be configured for Peripheral Indirect Addressing The DMA buffer is divided into con secutive memory blocks corresponding to all available analog inputs out of ANO AN31 Each conversion result for a particular analog input is automatically transferred by the ADC module to the corresponding block within the user defined DMA buffer area Successive samples for the same analog input are stored in sequence within the block assigned to that input The number of samples that need to be stored in the DMA buffer for each analog input is speci fied by the DMABL lt 2 0 gt bits ADxCON4 lt 2 0 gt The buffer locations within each block are accessed by the ADC module using an internal pointer which is initialized to o when the ADC module is enabled When this internal pointer reaches the value defined by the DMABL lt 2 0 gt bits it gets reset to o This ensures that conversion results of one analog input do not corrupt the conversion results of other analog inputs The rate at which this internal pointer is incremented when data is written to the DMA buffer is specified by the SMPI lt 3 0 gt bits When no channel scanning or
25. is cleared x Bit is unknown bit 15 ADRC ADC Conversion Clock Source bit 1 ADC Internal RC Clock 0 Clock Derived From System Clock bit 14 13 Unimplemented Read as 0 bit 12 8 SAMC lt 4 0 gt Auto Sample Time bits 11111 31 TAD 00001 1 TAD 00000 0 TAD bit 7 0 ADCS lt 7 0 gt ADC Conversion Clock Select bits 11111111 TCY ADCS lt 7 0 gt 1 256 Tcv TAD 00000010 TCY ADCS lt 7 0 gt 1 2 3 TcY TAD 00000001 TCY ADCS lt 7 0 gt 1 2 2 TCY TAD 00000000 TCY ADCS lt 7 0 gt 1 2 1 TcY TAD Note 1 The x in ADxCONS3 and ADCx refers to ADC 1 or ADC 2 DS70183A page 16 8 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC Register 16 4 ADXCON4 ADCx Control Register 4 U 0 U 0 U 0 U 0 U 0 U 0 U 0 U 0 bit 15 bit 8 U 0 U 0 U 0 U 0 U 0 R W 0 R W 0 R W 0 DMABL lt 2 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 3 Unimplemented Read as 0 bit 2 0 DMABL 2 0 Selects Number of DMA Buffer Locations per Analog Input bits 111 Allocates 128 words of buffer to each analog input 110 Allocates 64 words of buffer to each analog input 101 Allocates 32 words of buffer to each analog input 100 A
26. length 2006 Microchip Technology Inc DS70183A page 16 15 dsPIC33F Family Reference Manual 16 4 ADC MODULE CONFIGURATION The following steps should be followed for performing an A D conversion 1 Select 10 bit or 12 bit mode ADxCON1 lt 10 gt 2 Select voltage reference source to match expected range on analog inputs ADxCON2 lt 15 13 gt 3 Select the analog conversion clock to match desired data rate with processor clock ADxCON3 lt 7 0 gt 4 Select port pins as analog inputs ADxPCFGH lt 15 0 gt and ADxPCFGL lt 15 0 gt 5 Determine how inputs will be allocated to Sample Hold channels ADXCHSO0 15 0 and ADxCHS123 lt 15 0 gt 6 Determine how many Sample Hold channels will be used ADxCON2 lt 9 8 gt ADx PCFGH lt 15 0 gt and ADxPCFGL lt 15 0 gt 7 Determine how sampling will occur ADXCON1 3 ADxCSSH lt 15 0 gt and ADxC SSL lt 15 0 gt 8 Select Manual or Auto Sampling 9 Select conversion trigger and sampling time 10 Select how conversion results are stored in the buffer ADXCON 1 lt 9 8 gt 11 Select interrupt rate or DMA buffer pointer increment rate ADXCON2 lt 9 5 gt 12 Select the number of samples in DMA buffer for each ADC module input ADxCON4 lt 2 0 gt 13 Select the data format 14 Configure ADC interrupt if required Clear ADXIF bit Select interrupt priority ADxIP 2 0 Set ADXIE bit 15 Configure DMA channel if needed 16 Turn on ADC module ADxCON1
27. the time selected for each bit conversion TAD is selected in ADCON3 and should be within a range as specified in the Electrical Characteristics If TAD is too short the result may not be fully converted before the conversion is terminated If TAD is too long the voltage on the sampling capacitor can decay before the conversion is com plete These timing specifications are provided in the Electrical Specifications section of the device data sheets 2 Often the source impedance of the analog signal is high greater than 10 kQ so the current drawn from the source to charge the sample capacitor can affect accuracy If the input signal does not change too quickly try putting a 0 1 uF capacitor on the analog input This capacitor charges to the analog voltage being sampled and supplies the instantaneous current needed to charge the 4 4 pF internal holding capacitor 3 Put the device into Sleep mode before the start of the A D conversion The RC clock source selection is required for conversions in Sleep mode This technique increases accuracy because digital noise from the CPU and other peripherals is minimized Question 2 Do you know of a good reference on ADCs Answer A good reference for understanding A D conversions is the Analog Digital Conversion Handbook third edition published by Prentice Hall ISBN 0 13 03 2848 0 Question 3 My combination of channels sample and samples interrupt is greater than the size of the buffer W
28. write ADC1BUFO and generate DMA Request SIMSAM n a Not applicable for single channel sample Sample MUX A Inputs AN3 gt CHO convert CHO write ADC1BUFO and generate DMA Request BUFM 0 Single 16 word result buffer Sample MUX A Inputs AN4 gt CHO convert CHO write ADC1BUFO and generate DMA Request ALTS 0 Always use MUX A input select Sample MUX A Inputs AN5 gt CHO convert CHO write ADC1BUFO and generate DMA Request MUX A Input Select CHOSA lt 4 0 gt n a Override by CSCNA Sample MUX A Inputs AN6 gt CHO convert CHO write ADC1BUFO and generate DMA Request CHONA 0 Select VREF for CHO input Sample MUX A Inputs AN7 gt CHO convert CHO write ADC1BUFO and generate DMA Request CSCNA 1 Scan CHO Inputs CSSL lt 15 0 gt 21111 1111 1111 1111 16 inputs scanned Sample MUX A Inputs AN8 gt CHO convert CHO write ADC1BUFO and generate DMA Request Sample MUX A Inputs AN9 gt CHO convert CHO write ADC1BUFO and generate DMA Request CH123SA n a Channel CH1 CH2 CH3 input unused Sample MUX A Inputs AN10 gt CHO convert CHO write ADC1BUFO and generate DMA Request CH123NA lt 1 0 gt n a Channel CH1 CH2 CH3 input unused MUX B Input Select CHOSB lt 3 0 gt n a Channel CHO input unused Sample MUX A Inputs AN11 gt CHO convert CHO write ADC1BUFO and generate DMA Request Sample MUX A Inputs AN12
29. 00 DMAxONT 15 Scan 4 inputs Interrupt on 16th conversion Converting Three Inputs Four Times and Four Inputs One Time per DMA Interrupt OPERATION SEQUENCE CHPS lt 1 0 gt 1x Sample Channels CHO CH1 CH2 CH3 SIMSAM 1 Sample all channels simultaneously Sample MUX A Inputs AN4 gt CHO ANO gt CH1 AN1 gt CH2 AN2 gt CH3 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request Convert CH2 write ADC1BUFO and generate DMA Request Convert CH3 write ADC1BUFO and generate DMA Request BUFM 0 Single 16 word result buffer ALTS 0 Always use MUX A input select MUX A Input Select Sample MUX A Inputs AN5 gt CHO ANO gt CH1 AN1 gt CH2 AN2 gt CH3 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request Convert CH2 write ADC1BUFO and generate DMA Request Convert CH3 write ADC1BUFO and generate DMA Request CHOSA lt 3 0 gt n a Override by CSCNA CHONA 0 Select VREF for CHO input CSCNA 1 Scan CHO Inputs Sample MUX A Inputs AN6 CHO ANO gt CH1 AN1 gt CH2 AN2 gt CH3 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request Convert CH2 write ADC1BUFO and generate DMA Request Convert CH3 write ADC1BUFO and generate DMA Request CSSL lt 15 0 gt 0000 0000 1111 0000 Scan AN4
30. 00 0000 0000 0000 1111 1110 0000 0000 0000 0100 1000 0000 0100 0001 0001 0001 0000 0000 zm eb 0 001 0 499 0 1024 00 0000 0000 0000 0000 1111 1110 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0 2512 0 000 0 500 Table 16 9 Numerical Equivalents of Various Result Codes 12 bit Mode VIN VREF 12 bit 16 bit Unsigned 16 bit Signed 16 bit Unsigned 16 bit Signed Output Code Integer Format Integer Format Fractional Format Fractional Format 4095 4096 1111 1111 0000 1111 1111 0000 0111 1111 1111 1111 1111 0111 1111 1111 1111 1111 1111 0000 0000 4095 2047 0 9998 0 9995 4094 4096 1111 1111 0000 1111 1111 0000 0111 1111 1111 1111 1110 0111 1111 1110 1110 1110 1110 0000 0000 4094 2046 v 0 9995 0 9990 2049 4096 1000 0000 0000 1000 0000 0000 0000 0000 1000 0000 0001 0000 0000 0001 0001 0001 0001 0000 0000 2049 1 0 5002 0 0005 2048 4096 1000 0000 0000 1000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 2048 0 0 500 0 000 2047 4096 0111 1111 0000 0111 1111 1111 1111 1111 0111 1111 1111 LITI LITT TITLI 1111 1111 LEIT 0000 0000 2047 gt reT 0 4998 0 0005 1 4096 0000 0000 0000 0000 0000 1111 1000 0000 0000 0000 0001 1000 0000 0001 0001 0001 0001 0000 0000 E 2047 0 0002 0 9995 0 4096 0000 0000 0000 0000 0000 1111 1000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0 2048 0 000 1 000 2006 Microchip Technology Inc DS7
31. 001 the A D conversion is triggered by an active transition on the INTO pin The INTO pin can be programmed for either a rising edge input or a falling edge input 16 11 3 2 GP TIMER COMPARE TRIGGER The ADC is configured in this Trigger mode by setting SSRC 2 0 010 When a match occurs between the 32 bit timer TMR3 TMR2 and the 32 bit Combined Period register PR3 PR2 a special ADC trigger event signal is generated by Timer3 This feature does not exist for the TMR5 TMR4 timer pair Refer to Section 11 Timers for more details Check for the most recent documentation on the Microchip website at www microchip com 16 11 3 8 MOTOR CONTROL PWM TRIGGER The PWM Module has an event trigger that allows A D conversions to be synchronized to the PWM time base When SSRC 2 0 011 the A D sampling and conversion times occur at any user programmable point within the PWM period The special event trigger allows the user to minimize the delay between the time when A D conversion results are acquired and the time when the duty cycle value is updated Refer to Section 14 Motor Control PWM for more details Check for the most recent documentation on the Microchip website at www microchip com 2006 Microchip Technology Inc DS70183A page 16 27 dsPIC33F Family Reference Manual 16 11 3 4 SYNCHRONIZING A D OPERATIONS TO INTERNAL OR EXTERNAL EVENTS Modes where an external event trigger pulse ends sampling and starts conversion SSRC
32. 0183A page 16 51 dsPIC33F Family Reference Manual 16 17 TRANSFER FUNCTION 10 BIT MODE The ideal transfer function of the ADC module is shown in Figure 16 27 The difference of the input voltages VINH VINL is compared to the reference VREFH VREFL The first code transition A occurs when the input voltage is VREFH VREFL 2048 or 0 5 LSb The 00 0000 0001 code is centered at VREFH VREFL 1024 or 1 0 LSb B The 10 0000 0000 Code is centered at 512 VREFH VREFL 1024 C An input voltage less than 1 VREFH VREFL 2048 converts as 00 0000 0000 D An input greater than 2045 VREFH VREFL 2048 converts as 11 1111 1111 E Figure 16 27 ADC Module Transfer Function 10 bit Mode 10 10 10 10 01 01 01 0000 0000 0000 0000 TILL Illl FELL Ade IIIT TIII Ld LLII 1110 00 0000 0001 00 0000 0000 Output Code 1023 ee E 1022 L Lo L oe 4 4 I P Ld I 4 4 a ww 4 0011 515 ee tele dia AE 0010 514 a gh Lol 0001 513 d cds d 4 0000 512 duh 1111 511 L de er 1110 510 Lol aes eke 1101 509 eben ake a Pd Pd B 4 A Pd d D T pace pe T a 0 L L L VREFL VREFL VREFH VREFL 1024 512 VREFH VREFL 1024 VREFL 1023 VREFH Ver VREFH 1024 VREFL VINH VINL DS70183
33. 1 AN2 SAMPLE 1 AN5 SAMPLE 2 ANO SAMPLE 2 AN1 SAMPLE 2 AN2 SAMPLE 2 AN6 SAMPLE 3 ANO SAMPLE 3 AN1 SAMPLE 3 AN2 SAMPLE 3 AN7 SAMPLE 4 ANO SAMPLE 4 AN1 SAMPLE 4 AN2 SAMPLE 4 DMAxSTA DS70183A page 16 36 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 14 CONVERSION SEQUENCE EXAMPLES The following configuration examples show the A D operation in different sampling and buffering configurations In each example setting the ASAM bit starts automatic sampling A conversion trigger ends sampling and starts conversion 16 14 1 Sampling and Converting a Single Channel Multiple Times Figure 16 17 and Table 16 2 illustrate a basic configuration of the ADC In this case one ADC input ANO is sampled by one Sample Hold channel CHO and converted The results are stored in the user configured DMA buffer illustrated as Buffer 0 through Buffer 15 This process repeats 16 times until the buffer is full and then the ADC module generates an interrupt The entire process then repeats The CHPS bits specify that only Sample Hold CHO is active With ALTS clear only the MUX A inputs are active The CHOSA bits and CHONA bit are specified ANO VREF as the input to the Sample Hold channel All other input selection bits are not used Figure 16 17 Converting One Channel 16 Times Interrupt
34. 1 ANO Sample 2 ANO Sample 3 ANO Sample 4 ANO Sample 5 ANO Sample 6 ANO Sample 7 ANO Sample 8 ANO Sample 9 ANO Sample 10 ANO Sample 11 ANO Sample 12 ANO Sample 13 ANO Sample 14 ANO Sample 15 ANO Sample 16 Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request Sample MUX A Inputs ANO gt CHO Convert CHO write ADC1BUFO and generate DMA Request DMA Interrupt Repeat DMA Buffer 2nd DMA Interrupt ANO Sample 17 ANO Sample 18 ANO Sample 19 ANO Sample 20 ANO Sample 21 ANO Sample 22 ANO Sample 23 ANO Sample 24 ANO Sample 25 ANO Sample 26 ANO Sample 27 ANO Sample 28 ANO Sample 29 ANO Sample 30 ANO Sample 31 ANO Sample 32 DS70183A page 16 38 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 14 2 A D Conversions While Scanning Through All Analog Inputs Figure 16 18 and Table 16 3 illustrate a typical setup where all available analog input channels are sampled by one Sample Hold channel CHO and converted The set Scan Input Selection CSCNA bit ADxCON2 lt 10 gt specifies scanning of the ADC inputs to the CHO positive input Other conditions are similar to those described in Section 16 14 1 Sampling and Converting a Single Channel Multiple Times Initially the ANO input is sampled by CHO and converted The
35. A Continued void initDma0 void DMAOCONbits AMODE 2 Configure DMA for Peripheral indirect mode DMAOCONbits MODE 2 Configure DMA for Continuous Ping Pong mode DMAOPAD 0x0300 Point DMA to ADC1BUFO DMAOCNT 31 32 DMA request 4 buffers each with 8 words DMAOREQ 13 Select ADC1 as DMA Request source DMAOSTA _ builtin dmaoffset amp BufferA DMAOSTB _ builtin dmaoffset amp BufferB IFSObits DMAOIF 0 Clear the DMA interrupt flag bit IECObits DMAOIE 1 Set the DMA interrupt enable bit DMAOCONbits CHEN 1 Enable DMA DMAOInterrupt ISR name is chosen from the device linker script unsigned int DmaBuffer 0 void attribute interrupt DMAOInterrupt void if DmaBuffer 0 ProcessADCSamples BufferA Adc1Ch0 ProcessADCSamples BufferA Adc1Ch1 ProcessADCSamples BufferA Adc1Ch2 ProcessADCSamples BufferA Adc1Ch3 else ProcessADCSamples BufferB Adc1Ch0 ProcessADCSamples BufferB Adc1Ch1 ProcessADCSamples BufferB Adc1Ch2 ProcessADCSamples BufferB Adc1Ch3 DmaBuffer 1 IFSObits DMAOIF 0 Clear the DMAO Interrupt Flag void ProcessADCSamples unsigned int AdcBuffer Do something with ADC Samples 2006 Microchip Technology Inc DS70183A page 16 57 dsPIC33F Family Reference Manual Example 16 5 Code for Alternate Sampling Using DMA RRR IRR IR IR IR IR TR IR TR IR IR IR IR TR TR TR
36. A page 16 52 2006 Microchip Technology Inc 16 18 Section 16 Analog to Digital Converter ADC TRANSFER FUNCTION 12 BIT MODE The ideal transfer function of the ADC is shown in Figure 16 27 The difference of the input volt ages VINH VINL is compared to the reference VREFH VREFL The first code transition A occurs when the input voltage is VREFH VREFL 8192 or 0 5 LSb e The 00 0000 0001 code is centered at VREFH VREFL 4096 or 1 0 LSb B The 10 0000 0000 code is centered at 2048 VREFH VREFL 4096 C An input voltage less than 1 VREFH VREFL 8192 converts as 00 0000 0000 D An input greater than 8192 VREFH VREFL 8192 converts as 11 1111 1111 E Figure 16 28 A D Transfer Function 12 bit Mode 1111 1111 1000 1000 1000 1000 0111 0111 0111 Output Code 1111 1111 4095 1111 1110 4094 0000 0011 2051 0000 0010 2050 0000 0001 2049 0000 0000 2048 1111 1111 2047 1111 1110 2046 1111 1101 2045 0000 0000 0001 1 0000 0000 0000 0 ERI T LOT if E rt 1 Ld 1 1 Ld 1 y 1 B x 1 A Pid 1 mei D m T gt L L VAERE VREFH VREFL 2048 VREFH VREFL VREFH VREFL __ VREFL 4096 4096 VINH VINL 2006 Microchip Technology Inc DS70183A page 16 53 dsPIC33F Family Refer
37. ADxCHSO0 15 CH123SB ADxCHS0 8 and CH123NB lt 1 0 gt ADxCHS0 10 9 are collectively called the MUX B inputs When the ALTS bit is 1 the ADC module alternates between the MUX A inputs on one group of samples and the MUX B inputs on the subsequent group of samples DS70183A page 16 18 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC For channel 0 if the ALTS bit is o only the inputs specified by CHOSA lt 4 0 gt and CHONA are selected for sampling If the ALTS bit is 1 on the first sample convert sequence for channel 0 the inputs specified by CHOSA lt 4 0 gt and CHONA are selected for sampling On the next sample convert sequence for channel 0 the inputs specified by CHOSB lt 4 0 gt and CHONB are selected for sampling This pattern repeats for subsequent sample conversion sequences Note that if multiple channels CHPS 01 or 1x and simultaneous sampling SIMSAM 1 are specified alternating inputs change every sample because all channels are sampled on every sample time If multiple channels CHPS 01 or 1x and sequential sampling SIMSAM 0 are specified alternating inputs change only on each sample of a particular channel 16 7 2 2 SCANNING THROUGH SEVERAL INPUTS WITH CHANNEL 0 Channel 0 can scan through a selected vector of inputs The CSCNA bit ADxCON2 lt 10 gt enables the CHO channel inputs to be scanned across a selected number of analog inputs
38. AOIE THE OC1IE IC1IE INTOIE 0000 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE AD2IE INTHE CNIE MI2C1IE SI2C1IE 0000 IPC3 OOAA DMA1IP lt 2 0 gt AD1IP lt 2 0 gt UITXIP lt 2 0 gt 4444 IPC5 OOAE IC8IP lt 2 0 gt IC7IP lt 2 0 gt AD2IP lt 2 0 gt INT1IP 2 0 4444 ADC1BUFO 0300 ADC1 Data Buffer uuuu AD1CON1 0320 ADON ADSIDL ADDMABM AD12B FORM lt 1 0 gt SSRC lt 2 0 gt SIMSAM ASAM SAMP DONE 0000 ADICON2 0322 VCFG lt 2 0 gt CSCNA CHPS lt 1 0 gt BUFS SMPI 3 0 BUFM ALTS 0000 ADICON3 0324 ADRC SAMC lt 4 0 gt ADCS lt 5 0 gt 0000 AD1CHS123 0326 CH123NB lt 1 0 gt CH123SB CH123NA lt 1 0 gt CH123SA 0000 ADICHSO0 0328 CHONB CHOSB lt 4 0 gt CHONA CHOSA lt 4 0 gt 0000 AD1PCFGH 032A PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24 PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16 0000 ADIPCFGL 032C PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFGO 0000 AD1CSSH_ 032E CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 CSS23 CSS22 CSS 1 CSS20 CSS19 CSS18 CSS17 CSS16 0000 AD1CSSL 0330 CSS15 CSS14 CSS13 CSS12 CSSi CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CS84 CSS3 CSS2 CSS1 CSS0 0000 ADICON4 0332 DMABL lt 2 0 gt 0000 ADC2BUFO
39. CON1 ADCx Control Register 1 Continued SIMSAM Simultaneous Sample Select bit only applicable when CHPS lt 1 0 gt 01 or 1x When AD12B 1 SIMSAM is U 0 Unimplemented Read as 0 1 Samples CHO CH1 CH2 CH3 simultaneously when CHPS lt 1 0 gt 1x or Samples CHO and CH1 simultaneously when CHPS 1 0 01 0 Samples multiple channels individually in sequence ASAM ADC Sample Auto Start bit 1 Sampling begins immediately after last conversion SAMP bit is auto set 0 Sampling begins when SAMP bit is set SAMP ADC Sample Enable bit 1 ADC Sample Hold amplifiers are sampling 0 ADC Sample Hold amplifiers are holding If ASAM 0 software can write 1 to begin sampling Automatically set by hardware if ASAM 1 If SSRC 000 software can write 0 to end sampling and start conversion If SSRC 000 automatically cleared by hardware to end sampling and start conversion DONE ADC Conversion Status bit 1 ADC conversion cycle is completed 0 ADC conversion not started or in progress Automatically set by hardware when A D conversion is complete Software can write 0 to clear DONE status software not allowed to write 1 Clearing this bit does NOT affect any operation in progress Automatically cleared by hardware at start of a new conversion The x in ADxCON1 and ADCx refers to ADC 1 or ADC 2 DS70183A page 16 6 2006 Microchip Technology Inc Register 16 2 Secti
40. CONV gt 1 lt TSAMP 1 1 1 ch0 samp chi samp i i ch2_samp i i i ch3_samp Buffer 0 i n X i E X Buffer 1 X Buffer 2 Rid X utei X X DONE SAMP 16 11 2 3 MULTIPLE CHANNELS WITH SEQUENTIAL SAMPLING As shown in Figure 16 10 when using sequential sampling the sample time precedes each conversion time In the example 3 TAD clocks are added for sample time for each channel Figure 16 10 Converting Four Channels Auto Sample Start TAD Conversion Start Sequential Sampling ADCLK DO TCONV R 1 TCONV TCONV CONV Tconyv i lt TSAMP i lt TSAMP ch0 samp chi_samp_ i ie A ch2 samp L ch3_samp o i Loo y i Butero X X Buffer 1 MN X De i X Buffer 2 ANE i X 2E l Buffer 3 X i i X i DONE _ 0 i SAMP DS70183A page 16 26 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 11 2 4 SAMPLE TIME CONSIDERATIONS USING CLOCKED CONVERSION TRIGGER AND AUTOMATIC SAMPLING Different sample conversion sequences provide different available sampling times for the Sam ple Hold channel to acquire the analog signal The user must ensure the sa
41. DMABM 0 DMA buffers are built in scatter gather mode ADICON2bits SMPI 2 37 4 ADC buffers ADICON4bits DMABL 3 Each buffer contains 8 words IFSObits ADI1IF 0 Clear the A D interrupt flag bit IECObits AD1IE 0 Do Not Enable A D interrupt ADICON1bits ADON 1 Turn on the A D converter Timer 3 is setup to time out every 125 microseconds 8Khz Rate As a result the module will stop sampling and trigger a conversion on every Timer3 time out i e Ts 125us void initTmr3 TMR3 0x0000 PR3 4999 Trigger ADC1 every 125usec FSObits T3IF 0 Clear Timer 3 interrupt ECObits T3IE 0 Disable Timer 3 interrupt T3CONbits TON 1 Start Timer 3 Linker will allocate these buffers from the bottom of DMA RAM struct unsigned int Adc1cho 8 unsigned int Adc1Ch1 8 unsigned int Adc1Ch2 8 unsigned int Adc1Cch3 8 BufferA attribute space dma struct unsigned int Adc1cho 8 unsigned int Adc1Ch1 8 unsigned int Adc1Ch2 8 unsigned int Adc1Cch3 8 BufferB attribute space dma DMAO configuration Direction Read from peripheral address 0 x300 ADCIBUFO and write to DMA RAM AMODE Peripheral Indirect Addressing Mode MODE Continuous Ping Pong Mode IRQ ADC Interrupt DS70183A page 16 56 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC Example 16 4 Code for Channel Scanning Using DM
42. FGn bit is set In this configuration the input to the analog multiplexer is connected to AVss Note 1 When the ADC Port register is read any pin configured as an analog input reads asa 0 2 Analog levels on any pin that is defined as a digital input including the AN15 ANO pins may cause the input buffer to consume current that is out of the device s specification 16 7 2 Channel 0 Input Selection Channel 0 is the most flexible of the four Sample Hold channels in terms of selecting analog inputs It allows you to select any of the up to 16 analog inputs as the input to the positive input of the channel The Channel 0 Positive Input Select for Sample A CHOSA lt 4 0 gt bits ADxCHS0 lt 4 0 gt normally select the analog input for the positive input of channel 0 You can select either VREF or AN1 as the negative input of the channel The CHONA bit ADxCHS0 7 normally selects the analog input for the negative input of channel 0 16 7 2 1 SPECIFYING ALTERNATING CHANNEL 0 INPUT SELECTIONS The Alternate Input Sample Mode Select ALTS bit ADXCON2 0 causes the ADC module to alternate between two sets of inputs that are selected during successive samples The inputs specified by CHOSA lt 4 0 gt ADxCHS0 4 0 CHONA ADxCHS0 lt 7 gt CH123SA ADxCHS123 0 and CH123NA lt 1 0 gt ADxCHS123 2 1 are collectively called the MUX A inputs The inputs specified by CHOSB lt 4 0 gt ADxCHS0 lt 12 8 gt CHONB
43. H1 Convert CH1 1x 0 Sample CHO Convert CHO 4 Figure 16 10 Sample CH1 Convert CH1 Figure 16 14 Sample CH2 Convert CH2 Figure 16 22 Sample CH3 Convert CH3 01 1 Sample CHO CH1 simultaneously 1 Figure 16 20 Convert CHO Convert CH1 1x a Sample CHO CH1 CH2 CH3 1 Figure 16 9 simultaneously Figure 16 13 Convert CHO Figure 16 19 Convert CH1 Figure 16 21 Convert CH2 Convert CH3 16 10 HOW TO START SAMPLING 16 10 1 Manual Setting the SAMP bit ADxCON1 lt 1 gt causes the ADC to begin sampling One of several options can be used to end sampling and complete the conversions Sampling does not resume until the SAMP bit is once again set For an example see Figure 16 5 16 10 2 Automatic Setting the ASAM bit ADxCON1 lt 2 gt causes the ADC to automatically begin sampling a channel whenever a conversion is not active on that channel One of several options can be used to end sampling and complete the conversions If the SIMSAM bit specifies sequential sampling sampling on a channel resumes after the conversion of that channel completes If the SIMSAM bit specifies simultaneous sampling sampling on a channel resumes after the conversion of all channels completes For an example see Figure 16 6 2006 Microchip Technology Inc DS70183A page 16 21 dsPIC33F Family Reference Manual 16 11 HOW TO STOP SAMPLING AND START CONVERSIONS The conversion trigger source terminates sampling and starts a selected sequence of con
44. MICROCHIP Section 16 Analog to Digital Converter ADC HIGHLIGHTS This section of the manual contains the following major topics 16t Introd ctionis Ete eee item ttg 16 2 16 2 Control Registers ete aede b bote etie e te eger e dee uie 16 4 16 3 A D Terminology and Conversion Sequence sss 16 14 16 4 ADC Module Configuration essen nennen nnn 16 16 16 5 Selecting the Voltage Reference Source ssssssssseeeeees 16 16 16 6 Selecting the A D Conversion Clock 16 17 16 7 Selecting Analog Inputs for Sampling een 16 18 16 8 Enabling the Module etn t de nee deett en 16 20 16 9 Specifying Sample Conversion Control ccccccccessccceeseeeeeneeeeeeeeeeeeeeeeesueeeseneeeesseeees 16 20 16 10 How to Start Sampling ttem erre tite avin aree e pets 16 21 16 11 How to Stop Sampling and Start Conversions ccccessseeeseeeeeeeneeeesneeeseseeeesneeees 16 22 16 12 Controlling Sample Conversion Operation 16 32 16 13 Specifying Conversion Results Buffering sssseeenee 16 33 16 14 Conversion Sequence Examples sese 16 37 16 15 A D Sampling Requirements sss nennen nennen 16 49 16 16 Reading the ADC Result Buffer sssssssssseeeeeneneneee nennen 16 50 16 17 Transfer Function 10 bit Mode eese eene 16 52 16 18 Transfer Function 12 bit Mode
45. N1 ECAN2 define MAX CHNUM 5 Highest Analog input number enabled for alternate sampling define SAMP BUFF SIZE 16 Size of the input buffer per analog input Number of locations for ADC buffer 2 AN4 and AN5 x 16 32 words Align the buffer to 32words or 64 bytes This is needed for peripheral indirect mode int BufferA MAX CHNUM 1 SAMP_ BUFF SIZE _ attribute space dma aligned 64 int BufferB MAX CHNUM 1 SAMP_BUFF SIZE _ attribute space dma aligned 64 void ProcessADCSamples int AdcBuffer void initAdcl void AD1CON1bits FORM 3 Data Output Format Signed Fraction Q15 format AD1CON1bits SSRC 2 Sample Clock Source GP Timer starts conversion AD1CON1bits ASAM Le ADC Sample Control Sampling begins immediately after conversion ADICON1bits AD12B 0 10 bit ADC operation AD1CON2bits ALTS 1 Alternate Input Sample Mode Select Bit ADICON2bits CHPS 0 Converts CHO DS70183A page 16 58 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC Example 16 5 Code for Alternate Sampling Using DMA Continued AD1CON3bits ADRC AD1CON3bits ADCS 0 ADC Clock is derived from Systems Clock 63 ADC Conversion Clock Tad Tcy ADCS 1 1 40M 64 1 6us 625Khz ADC Conversion Time for 10 bit Tc 12 Tab 19 2us ADICON1bits ADDMABM 0 DMA buffers are built in scatter gather mode LCON2bits SMPI 1 SMPI Must be program
46. REF for CHO input write ADC1BUFO and generate DMA Request CSCNA 0 Sample AN13 AN1 gt CHO convert CHO write ADC1BUFO and generate DMA Request CSSL lt 15 0 gt n a Scan input select unused Sample ANO gt CH1 convert CHO write ADC1BUFO and generate DMA Request CH123SA 0 CH1 ANO CH2 AN1 CH3 AN2 Sample AN1 gt CH2 convert CHO write ADC1BUFO and generate DMA Request CH123NA lt 1 0 gt 0x CH1 CH2 CH3 VREF Sample AN2 gt CH3 convert CHO write ADC1BUFO and generate DMA Request MUX B Input Select CHOSB lt 3 0 gt 0111 Select AN7 for CHO input CHONB 0 Select VREF for CHO input Sample AN14 gt CHO convert CHO write ADC1BUFO and generate DMA Request Sample AN3 AN6 gt CH1 convert CHO write ADC1BUFO and generate DMA Request CH123SB 1 CH1 AN3 CH2 AN4 CH3 AN5 CH123NB lt 1 0 gt 0x CH1 CH2 CH3 VREF DMA Buffer 1st DMA Interrupt AN13 AN1 Sample 1 ANO Sample 1 AN1 Sample 1 AN2 Sample 1 AN14 Sample 1 AN3 AN6 Sample 1 AN4 AN7 Sample 1 AN5 AN8 Sample 1 AN13 AN1 Sample 2 ANO Sample 2 AN1 Sample 2 AN2 Sample 2 AN14 Sample 2 AN3 AN6 Sample 2 AN4 AN7 Sample 2 AN5 AN8 Sample 2 Sample AN4 AN7 gt CH2 convert CHO write ADC1BUFO and generate DMA Request Sample AN5 AN8 gt CH3 convert CHO write ADC1BUFO and generate DMA Re
47. SA bit ADxCHS123 lt 0 gt selects the source for the positive inputs of channel 1 2 and 3 Clearing CH123SA selects ANO AN1 and AN as the analog source to the positive inputs of channel 1 2 and 3 respectively Setting CH123SA selects AN3 AN4 and AN5 as the analog Source The CH123NA lt 1 0 gt bits ADXCHS 2 1 select the source for the negative inputs of channel 1 2 and 3 Programming CH123NA 0x selects VREF as the analog source for the negative inputs of channels 1 2 and 3 Programming CH123NA 10 selects AN6 AN7 and AN8 as the analog source to the negative inputs of channels 1 2 and 3 respectively Programming CH123NA 11 selects AN9 AN10 and AN11 as the analog source 2006 Microchip Technology Inc DS70183A page 16 19 dsPIC33F Family Reference Manual 16 7 3 1 SELECTING MULTIPLE CHANNELS FOR A SINGLE ANALOG INPUT The analog input multiplexer can be configured so that the same input pin is connected to two or more Sample Hold channels The ADC converts the value held on one Sample Hold channel while the second Sample Hold channel acquires a new input sample 16 7 3 2 SPECIFYING ALTERNATING CHANNEL 1 2 AND 3 INPUT SELECTIONS As with the channel 0 inputs the ALTS bit ADXCON2 0 causes the ADC module to alternate between two sets of inputs that are selected during successive samples for channel 1 2 and 3 The MUX A inputs specified by CH123SA and CH123NA lt 1 0 gt always select the input when ALTS 0
48. TO IO II IO IO IO IO IO IO IOI A A k ke 2005 Microchip Technology Inc FileName adcDrvl c Dependencies Header h files if applicable see below Processor dsPIC33Fxxxx Compiler MPLAB C30 v2 01 00 or higher SOFTWARE LICENSE AGREEMENT Microchip Technology Inc Microchip licenses this software to you solely for use with Microchip dsPIC digital signal controller products The software is owned by Microchip and is protected under applicable copyright laws All rights reserved SOFTWARE IS PROVIDED AS IS MICROCHIP EXPRESSLY DISCLAIMS ANY WARRANTY OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY INCIDENTAL SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES LOST PROFITS OR LOST DATA HARM TO YOUR EQUIPMENT COST OF PROCUREMENT OF SUBSTITUTE GOODS TECHNOLOGY OR SERVICES ANY CLAIMS BY THIRD PARTIES INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION OR OTHER SIMILAR COSTS KR KKK KK KR KK KR ck Sk ke KK KR ck Sk ke KK RK e k k k k Sk ke KK k ok Sk ke k k k k k KR k k k k k RR k k k k k RR k k RRR RR k k k k ke ke ke KR k k ke ke k k Hif defined dsPIC33F include p33fxxxx h elif defined PIC24H_ include p24hxxxx h endif include adcDrv1 h include tglPin h Define Message Buffer Length for ECA
49. When CSCNA is set the CHOSA lt 4 0 gt bits are ignored The ADCx Input Scan Select Register High ADxCSSH and ADCx Input Scan Select Register Low ADxCSSL registers specify the inputs to be scanned Each bit in these registers corresponds to an analog input Bit O corresponds to ANO bit 1 corresponds to AN1 and so on If a particular bit is 1 the corresponding input is part of the scan sequence The inputs are always scanned from lower to higher numbered inputs starting at the first selected channel after each interrupt occurs Note If the number of scanned inputs selected is greater than the number of samples taken per interrupt the higher numbered inputs will not be sampled The ADxCSSH and ADxCSSL bits only specify the input of the positive input of the channel The CHONA bit still selects the input of the negative input of the channel during scanning If the ALTS bit is 1 the scanning only applies to the MUX A input selection The MUX B input selection as specified by the CHOSB lt 4 0 gt still selects the alternating channel 0 input When the input selections are programmed in this manner the channel 0 input alternates between a set of scanning inputs specified by the ADxCSSL register and a fixed input specified by the CHOSB bits 16 7 3 Channel 1 2 and 3 Input Selection Channel 1 2 and 3 can sample a subset of the analog input pins Channel 1 2 and 3 can select one of two groups of three inputs The CH123
50. When AD12B 1 CHxSA is U 0 Unimplemented Read as 0 1 CH1 positive input is AN3 CH2 positive input is AN4 CH3 positive input is AN5 0 CH1 positive input is ANO CH2 positive input is AN1 CH3 positive input is AN2 Unimplemented Read as 0 CH123NA 1 0 Channel 1 2 3 Negative Input Select for Sample A bits When AD12B 1 CHxNA is U 0 Unimplemented Read as 0 11 CH1 negative input is AN9 CH2 negative input is AN10 CH3 negative input is AN11 10 CH1 negative input is AN6 CH2 negative input is AN7 CH3 negative input is AN8 0x CH1 CH2 CH3 negative input is VREFL CH123SA Channel 1 2 3 Positive Input Select for Sample A bit When AD12B 1 CHxSA is U 0 Unimplemented Read as 0 1 CH1 positive input is AN3 CH2 positive input is AN4 CH3 positive input is AN5 0 CH1 positive input is ANO CH2 positive input is AN1 CH3 positive input is AN2 The x in ADXCHS123 and ADCx refers to ADC 1 or ADC 2 DS70183A page 16 10 2006 Microchip Technology Inc Register 16 6 Section 16 Analog to Digital Converter ADC ADxCHSO0 ADCx Input Channel 0 Select Register R W 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 CHONB CHOSB lt 4 0 gt bit 15 bit 8 R W 0 U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 CHONA CHOSA lt 4 0 gt bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Va
51. ag Status AD1IF or AD2IF bit in the Interrupt Flag Status Register IFSO or IFS1 respectively in the Interrupt Module gets set as a result of a sample conversion sequence The result of every A D conversion is stored in the ADCxBUFO register If a DMA channel is not enabled for the ADC module each result should be read by the user application before it gets overwritten by the next conversion result However if DMA is enabled multiple conversion results can be automatically transferred from ADCxBUFO to a user defined buffer in the DMA RAM area Thus the application can process several conversion results with minimal software overhead Note For information about how to configure a DMA channel to transfer data from the ADC buffer and define a corresponding DMA buffer area from where the data can be accessed by the application please refer to Section 22 Direct Memory Access DMA For specific information about the Interrupt registers please refer to Section 6 Interrupts The DMA Buffer Build Mode ADDMABM bit in ADCx Control Register 1 ADXCON 1 12 deter mines how the conversion results are filled in the DMA RAM buffer area being used for the ADC If this bit is set ADDMABM 1 DMA buffers are written in the order of conversion The ADC module provides an address to the DMA channel that is the same as the address used for the non DMA stand alone buffer If the ADDMABM bit is cleared then DMA buffers are written
52. alternate sampling is required SMPI 3 0 should be cleared implying that the pointer will increment on every sample Thus it is theoretically possible to use every location in the DMA buffer for the blocks assigned to the analog inputs being sampled In the example illustrated in Figure 16 15 it can be observed that the conversion results for the ANO AN1 and AN2 inputs are stored in sequence leaving no unused locations in their corre sponding memory blocks However for the four analog inputs AN4 AN5 AN6 and AN7 that are scanned by CHO the first location in the AN5 block the first two locations in the AN6 block and the first three locations in the AN7 block are unused resulting in a relatively inefficient arrange ment of data in the DMA buffer 2006 Microchip Technology Inc DS70183A page 16 33 dsPIC33F Family Reference Manual When scanning is used and no simultaneous sampling is performed SIMSAM 0 SMPI 3 0 should be set to one less than the number of inputs being scanned For example if CHPS lt 1 0 gt 00 only one Sample Hold channel is used and AD1CSSL OxFFFF indicating that ANO AN15 are being scanned then set SMPI lt 3 0 gt 1111 so that the internal pointer is incre mented only after every 16th sample conversion sequence This avoids unused locations in the blocks corresponding to the analog inputs being scanned Similarly if ALTS 1 indicating that alternating analog input selections are used t
53. ections Figure 16 20 and Table 16 5 demonstrate alternate sampling of the inputs assigned to MUX A and MUX B In this example two channels are enabled to sample simultaneously Setting the ALTS bit ADCxCON2 lt 0 gt enables alternating input selections The first sample uses the MUX A inputs specified by the CHOSA CHONA CH123SA and CH123NA bits The next sample uses the MUX B inputs specified by the CHOSB CHONB CH123SB and CH123NB bits In this exam ple one of the MUX B input specifications uses two analog inputs as a differential source to the Sample Hold sampling AN3 AN9 Note that using four Sample Hold channels without alternating input selections results in the same number of conversions as this example using two channels with alternating input selec tions However because the CH1 CH2 and CH3 channels are more limited in the selectivity of the analog inputs this example method provides more flexibility of input selection than using four channels Figure 16 20 Converting Two Sets of Two Inputs Using Alternating Input Selections Conversion i i Trigger TSAMP gt ISAMP gt a CLTSAMP gt _TSAMP gt ISAMP gt l ADC Clock 5 t 1 gt gt gt qra TCONVICONV TCONVICONV TCONVICONV TCONVICONV TCONVICONV Input to i i CHO AN15 AN15 ANI AN15
54. ence Manual 16 19 ADC ACCURACY ERROR Refer to Section 16 26 Related Application Notes for a list of documents that discuss ADC accuracy 16 20 CONNECTION CONSIDERATIONS Since the analog inputs employ ESD protection they have diodes to VDD and Vss As a result the analog input must be between VDD and Vss If the input voltage exceeds this range by greater than 0 3 V either direction one of the diodes becomes forward biased and it may damage the device if the input current specification is exceeded An external RC filter is sometimes added for anti aliasing of the input signal The R component should be selected to ensure that the sampling time requirements are satisfied Any external components connected via high impedance to an analog input pin capacitor zener diode etc should have very little leakage current at the pin 16 21 CODE EXAMPLES Two code examples that demonstrate typical ADC usage scenarios are described here 16 21 1 Channel Scanning Using DMA Example 16 4 configures a DMA channel for storing 32 ADC results in the Scatter Gather mode The ADC is set up to scan four analog inputs ANO AN1 AN2 AN3 thereby providing eight samples of each input in the DMA buffer 16 21 2 Alternate Sampling Using DMA Example 16 5 performs alternate sampling of two analog inputs AN4 AN5 and stores the results in a 32 word DMA buffer using the Scatter Gather mode DS70183A page 16 54 2006 Microchip Tech
55. ers configure the analog input pins as analog inputs or as digital I O The ADCSSH L registers select inputs to be sequentially scanned DS70183A page 16 4 2006 Microchip Technology Inc Register 16 1 Section 16 Analog to Digital Converter ADC ADxCON1 ADCx Control Register 1 R W 0 U 0 R W 0 R W 0 U 0 R W 0 R W 0 R W 0 ADON ADSIDL ADDMABM AD12B FORM lt 1 0 gt bit 15 bit 8 R W 0 R W 0 R W 0 U 0 R W 0 R W 0 R W 0 R C 0 HC HS HC HS SSRC lt 2 0 gt SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend HC Cleared by hardware HS Set by hardware R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown bit 15 ADON ADC Operating Mode bit 1 ADC module is operating o ADCis off bit 14 Unimplemented Read as 0 bit 13 ADSIDL Stop in Idle Mode bit 1 Discontinue module operation when device enters Idle mode 0 Continue module operation in Idle mode bit 12 ADDMABM DMA Buffer Build Mode bit 1 DMA buffers are written in the order of conversion The module provides an address to the DMA channel that is the same as the address used for the non DMA stand alone buffer o DMA buffers are written in Scatter Gather mode The module provides a Scatter Gather address to the DMA channel based on the index of the analog input and the size of the DMA buffer
56. f control bits allow two different analog input multiplexer configurations to be programmed called MUX A and MUX B The ADC can optionally switch between the MUX A and MUX B configurations between conversions The ADC can also option ally scan through a series of analog inputs Sample time is the time that the ADC module s Sample Hold Amplifier is connected to the analog input pin The sample time can be started manually by setting the ADC Sample Enable SAMP bit in ADCx Control Register 1 ADXCON 1 1 or started automatically by the ADC hardware The sample time is ended manually by clearing the SAMP control bit in the user software or auto matically by a conversion trigger source Conversion time is the time required for the ADC to convert the voltage held by the Sample Hold Amplifier The ADC is disconnected from the analog input pin at the end of the sample time The ADC requires one A D clock cycle TAD to convert each bit of the result plus two additional clock cycles A total of 12 TAD cycles are required to perform the complete conversion in 10 bit mode A total of 14 TAD cycles are required to perform the complete conversion in 12 bit mode When the conversion time is complete the result is loaded into the ADCxBUFO register the Sam ple Hold Amplifier can be reconnected to the input pin and a CPU interrupt can be generated The sum of the sample time and the A D conversion time provides the total conversion time There is a minimu
57. hat will happen to the buffer Answer This configuration is not recommended The buffer will contain unknown results DS70183A page 16 64 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 206 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual These application notes may not be written specifically for the dsPIC33F Product Family but the concepts are pertinent and could be used with modification and possible limitations The current application notes related to the ADC module are Title Application Note Using the Analog to Digital A D Converter AN546 Four Channel Digital Voltmeter with Display and Keyboard AN557 Understanding A D Converter Performance Specifications AN693 Using the dsPIC30F for Sensorless BLDC Control AN901 Using the dsPIC30F for Vector Control of an ACIM AN908 Sensored BLDC Motor Control Using the dsPIC30F2010 AN957 An Introduction to AC Induction Motor Control Using the dsPIC30F MCU AN984 Note Please visit the Microchip web site www microchip com for additional Application Notes and code examples for the dsPIC33F family of devices 2006 Microchip Technology Inc DS70183A page 16 65 dsPIC33F Family Reference Manual 16 27 REVISION HISTORY Revision A December 2006 This is the initial release of this document DS70183A page 16 66 2006 Microchip Technology Inc
58. hen SMPI 3 0 is set to 0001 thereby incrementing the internal pointer after every 2nd sample Note The module does not perform limit checks on the generated buffer addresses For example you must ensure that the LS bits of the DMAxSTA or DMAxSTB register used are indeed o Also the number of potential analog inputs multiplied by the buffer size specified by DMABL 2 0 must not exceed the total length of the DMA buffer DS70183A page 16 34 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC Figure 16 15 DMA Buffer in Scatter Gather Mode DMAxSTA Be ANO SAMPLE 1 ANO SAMPLE 2 ANO SAMPLE 3 ANO SAMPLE 4 ANO SAMPLE 5 ANO SAMPLE 6 ANO SAMPLE 7 ANO SAMPLE 8 AN1 SAMPLE 1 AN1 SAMPLE 2 AN1 SAMPLE 3 AN1 SAMPLE 4 AN1 SAMPLE 5 ANTBLOGK AN1 SAMPLE 6 AN1 SAMPLE 7 AN1 SAMPLE 8 AN2 SAMPLE 1 AN2 SAMPLE 2 AN2 SAMPLE 3 AN2 SAMPLE 4 AN2 SAMPLE 5 AN2 BLOCK AN2 SAMPLE 6 AN2 SAMPLE 7 AN2 SAMPLE 8 AN3 BLOCK AN4 SAMPLE 1 Unused Buffer Locations AN5 SAMPLE 2 ANO BLOCK AN4 SAMPLE 5 Unused Buffer Locations AN4 BLOCK Unused Buffer Locations AN5 BLOCK AN5 SAMPLE 6 Unused Buffer Locations AN6 SAMPLE 3 AN6 BLOCK Unused Buffer Locations AN6 SAMPLE 7 Unused
59. ing function must be completed prior to starting the conver sion The internal holding capacitor will be in a discharged state prior to each sample operation A minimum time period should be allowed between conversions for the sample time For more details about the minimum sampling time for a device see the device electrical specifications Figure 16 23 Analog Input Model 10 bit Mode vop RIC lt 2502 Sampling PS8 lt 3k2 itch CN ZX Vt 0 6V e pom 1 Rs ANx 1 Rss moa nli eius i Poor city M Oe a tie o DS LEES CHOLD va 1 CPN leakage L DAC capacitance DAE ZA VT 06V V y J 500 nA 4 4 pF Vss Legend CPIN input capacitance VT threshold voltage l leakage leakage current at the pin due to various junctions Ric interconnect resistance Rss sampling switch resistance CHOLD Sample Hold capacitance from DAC Note CPIN value depends on device package and is not tested Effect of CPIN negligible if Rs lt 5000 Figure 16 24 Analog Input Model 12 bit Mode yop RIC lt 2502 Sampling PSS lt 3KQ TX Vr 06V Switch Rs ANx l Rss Mq t t MCI o i E NON d on RER CHOLD VA CPN leakage L DAC capacitance OR AN VT 0 6V 4 500 nA 18 pF m a vss Legend CPIN input capacitance VT threshold voltage l leakage leakage current at the pin due to various junctions Ric interconnect resistance Rss sampling switch resi
60. ing the ADC interrupt is not done with the SMPI lt 3 0 gt bits To disable the interrupt clear the ADxIE analog module interrupt enable bit 16 12 3 Aborting Sampling Clearing the SAMP bit while in Manual Sampling mode terminates sampling but can also start a conversion if SSRC lt 2 0 gt 000 Clearing the ASAM bit while in Automatic Sampling mode does not terminate an on going sample convert sequence however sampling does not automatically resume after subsequent conversions 16 12 4 Aborting a Conversion Clearing the ADON ADxCON1 lt 15 gt bit during a conversion aborts the current conversion The ADC Result register pair is NOT updated with the partially completed A D conversion sample That is the corresponding ADC1BUFO buffer location continues to contain the value of the last completed conversion or the last value written to the buffer DS70183A page 16 32 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 13 SPECIFYING CONVERSION RESULTS BUFFERING The ADC module contains a single word read only dual port register ADCxBUFO which stores the A D conversion result If more than one conversion result needs to be buffered before triggering an interrupt DMA data transfers can be used Both ADC channels ADC1 and ADC2 can trigger a DMA data transfer Depending on which ADC channel is selected as the DMA IRQ source a DMA transfer occurs when the ADC Conversion Complete Interrupt Fl
61. it is cleared x Bit is unknown bit 15 0 PCFG lt 15 0 gt ADC Port Configuration Control bits 2 9 1 Port pin in Digital mode port read input enabled ADC input multiplexor connected to AVss 0 Port pin in Analog mode port read input disabled ADC samples pin voltage Note 1 On devices with less than 16 analog inputs all PCFG bits are R W by user However PCFG bits are ignored on ports without a corresponding input on device 2 On devices with two analog to digital modules both AD1PCFGL and AD2PCFGL affect the configuration of port pins multiplexed with ANO AN15 3 The x in ADXPCFGL and ADx refers to ADC 1 or ADC 2 2006 Microchip Technology Inc DS70183A page 16 13 dsPIC33F Family Reference Manual 16 3 A D TERMINOLOGY AND CONVERSION SEQUENCE Figure 16 2 shows a basic conversion sequence and the terms that are used A sampling of the analog input pin voltage is performed by Sample Hold amplifiers also called Sample Hold chan nels The 10 bit ADC configuration can use up to four Sample Hold channels designated CHO CH3 whereas the 12 bit ADC configuration can use only one Sample Hold channel CHO The Sample Hold channels are connected to the analog input pins via the analog input multiplexer The analog input multiplexer is controlled by the ADxCHS123 and ADxCHSO regis ters There are two sets of multiplexer control bits in the ADC channel select registers that func tion identically These two sets o
62. it is set 0 Bit is cleared X Bit is unknown bit 15 0 CSS lt 31 16 gt ADC Input Scan Selection bits 2 1 Select ANx for input scan 0 Skip ANx for input scan Note 1 On devices with less than 32 analog inputs all ADxCSSL bits can be selected by user However inputs selected for scan without a corresponding input on device convert VREF 2 ADC 2 only supports analog inputs ANO AN15 therefore no ADC 2 Input Scan Select register exists Register 16 8 ADxCSSL ADCx Input Scan Select Register Low R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 0 CSS lt 15 0 gt ADC Input Scan Selection bits 2 1 Select ANx for input scan 0 Skip ANx for input scan Note 1 On devices with less than 16 analog inputs all ADXCSSL bits can be selected by the user However inputs selected for scan without a corresponding input on device convert VREF 2 The x in ADxCSSL and ADCx refers to ADC 1 or ADC 2 DS70183A page 16 12 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC
63. llocates 16 words of buffer to each analog input 011 Allocates 8 words of buffer to each analog input 010 Allocates 4 words of buffer to each analog input 001 Allocates 2 words of buffer to each analog input 000 Allocates 1 word of buffer to each analog input Note 1 The x in ADXCONA4 and ADCx refers to ADC 1 or ADC 2 2006 Microchip Technology Inc DS70183A page 16 9 dsPIC33F Family Reference Manual Register 16 5 ADxCHS123 ADCx Input Channel 1 2 3 Select Register U 0 U 0 U 0 U 0 U 0 R W 0 R W 0 R W 0 CH123NB lt 1 0 gt CH123SB bit 15 bit 8 U 0 U 0 U 0 U 0 U 0 R W 0 R W 0 R W 0 CH123NA lt 1 0 gt CH123SA bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared X Bit is unknown bit 15 11 bit 10 9 bit 8 bit 7 3 bit 2 1 bit 0 Note 1 Unimplemented Read as 0 CH123NB lt 1 0 gt Channel 1 2 3 Negative Input Select for Sample B bits When AD12B 1 CHxNB is U 0 Unimplemented Read as 0 11 CH1 negative input is AN9 CH2 negative input is AN10 CH3 negative input is AN11 10 CH1 negative input is AN6 CH2 negative input is AN7 CH3 negative input is AN8 0x CH1 CH2 CH3 negative input is VREFL CH123SB Channel 1 2 3 Positive Input Select for Sample B bit
64. lt 15 gt The options for these configuration steps are described in the subsequent sections 16 5 SELECTING THE VOLTAGE REFERENCE SOURCE The voltage references for A D conversions are selected using the VCFG lt 2 0 gt control bits ADxCON2 15 13 The upper voltage reference VREFH and the lower voltage reference VREFL can be the internal AVDD and AVss voltage rails or the VREF and VREF input pins The external voltage reference pins can be shared with the ANO and AN1 inputs on low pin count devices The ADC module can still perform conversions on these pins when they are shared with the Vref and Vref input pins The voltages applied to the external reference pins must meet certain specifications Refer to the Electrical Specifications section of the device data sheet for details DS70183A page 16 16 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 6 SELECTING THE A D CONVERSION CLOCK The ADC module has a maximum rate at which conversions can be completed An analog module clock TAD controls the conversion timing The A D conversion requires 12 clock periods 12 TAD in the 10 bit mode and 14 clock periods 14 TAD in the 12 bit mode The A D conversion clock is derived from either the device instruction clock or an internal RC clock source The period of the A D conversion clock is software selected using a 6 bit counter There are 256 possible options for TAD specified by the ADC
65. lt 2 0 gt 001 10 011 can be used in combination with auto sampling ASAM 1 to cause the ADC module to synchronize the sample conversion events to the trigger pulse source For example in Figure 16 12 where SSRC lt 2 0 gt 010 and ASAM 1 the ADC module always ends sam pling and starts conversions synchronously with the timer compare trigger event The ADC has a sample conversion rate that corresponds to the timer comparison event rate Figure 16 11 Converting One Channel Manual Sample Start Conversion Trigger Based Conversion Start Conversion m Trigger i ADCLK MU i TSAMP gt lt TCONV SAMP ADC1BUFO l X Instruction Execution BSET AD1CON1 SAMP X i Figure 16 12 Converting One Channel Auto Sample Start Conversion Trigger Based Conversion Start Conversion L FA Trigger l ji ADCLK Loo o a TSAMP lt TCONV TSAMP a TCONV SAMP DONE i i i i Buffer 0 i X Buffer 1 j X BSET AD1CON1 ASAM X Instruction Execution DS70183A page 16 28 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 11 3 5 MULTIPLE CHANNELS WITH SIMULTANEOUS SAMPLING As shown in Figure 16 13 when simultaneous sampling is used sampling starts on all channels after the ASAM bit is set or when the last conversion ends Sampling stops and conversions start when the c
66. lue at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 CHONB Channel 0 Negative Input Select for Sample B bit Same definition as bit 7 bit 14 13 Unimplemented Read as 0 bit 12 8 CHOSB lt 4 0 gt Channel 0 Positive Input Select for Sample B bits 2 Same definition as bit lt 4 0 gt bit 7 CHONA Channel 0 Negative Input Select for Sample A bit 1 Channel 0 negative input is AN1 0 Channel 0 negative input is VREFL bit 6 5 Unimplemented Read as 0 bit 4 0 CHOSA lt 4 0 gt Channel 0 Positive Input Select for Sample A bits 2 11111 Channel 0 positive input is AN31 11110 Channel 0 positive input is AN30 00010 Channel 0 positive input is AN2 00001 Channel 0 positive input is AN1 00000 Channel 0 positive input is ANO Note1 The AN16 AN31 pins are not available for ADC 2 2 The x in ADXCHSO and ADCx refers to ADC 1 or ADC 2 2006 Microchip Technology Inc DS70183A page 16 11 dsPIC33F Family Reference Manual Register 16 7 AD1CSSH ADC1 Input Scan Select Register High R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 bit 15 bit 8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 B
67. m sample time to ensure that the Sample Hold Amplifier provides the desired accuracy for the A D conversion see 16 15 A D Sampling Requirements Furthermore there are multiple input clock options for the ADC You must select an input clock option that does not violate the minimum TAD specification Figure 16 2 ADC Sample Conversion Sequence 4 ADC Total Conversion Time Sample Time ADC Conversion Time A D conversion complete result is loaded into result buffer Optionally generate interrupt Sample Hold Amplifier is disconnected from input and holds signal level A D conversion is started by the conversion trigger source Sample Hold Amplifier is connected to the analog input pin for sampling The ADC allows many options for specifying the sample convert sequence The sample convert sequence can be very simple using only one Sample Hold amplifier A more elaborate sam ple convert sequence performs multiple conversions using more than one Sample Hold amplifier The 10 bit ADC configuration can use two Sample Hold amplifiers to perform two conversions in a sample convert sequence or four Sample Hold amplifiers with four conversions DS70183A page 16 14 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC The number of Sample Hold amplifiers or channels per sample used in the sample convert sequence is determined by the Channel Select CHPS lt 1 0
68. med to 1 for this case ADICON4bits DMABL 4 Each buffer contains 16 words gt AD1CHSO A D Input Select Register AD1CHSObits CH0SA 4 MUXA ve input selection AIN4 for CHO AD1CHSObits CHONA 0 MUXA ve input selection Vref for CHO AD1CHSObits CHOSB 5 MUXB ve input selection AIN5 for CHO AD1CHSObits CHONB 0 MUXB ve input selection Vref for CHO AD1PCFGH ADIPCFGL Port Configuration Register AD1PCFGL 0xXFFFF AD1PCFGH 0xXFFFF ADIPCFGLbits PCFG4 0 AN4 as Analog Input ADIPCFGLbits PCFG5 0 AN5 as Analog Input IFSObits ADIIF 0 Clear the A D interrupt flag bit IECObits ADIIE 0 Do Not Enable A D interrupt ADICON1bits ADON 1 Turn on the A D converter tglPinInit Timer 3 is set up to time out every 125 microseconds 8Khz Rate As a result the module will stop sampling and trigger a conversion on every Timer3 time out i e Ts 125us void initTmr3 TMR3 0x0000 PR3 4999 FSObits T3IF 0 ECObits T3IE 0 Start Timer 3 T3CONbits TON 1 DMAO configuration Direction Read from peripheral address 0 x300 ADCIBUFO and write to DMA RAM AMODE Peripheral Indirect Addressing Mode MODE Continuous Ping Pong Mode IRQ ADC Interrupt ADC stores results stored alternatively between DMA BASE 0 DMA BASE 16 on every 16th DMA request void initDma0 void DMAOCONbits AMODE DMAOCONbits MODE 25
69. mpling time exceeds the sampling requirements as outlined in Section 16 15 A D Sampling Requirements Assuming that the ADC module is set for automatic sampling and using a clocked conversion trigger the sampling interval is determined by the sample interval specified by the SAMC bits If the SIMSAM bit specifies simultaneous sampling or only one channel is active the sampling time is the period specified by the SAMC bit Equation 16 3 Available Sampling Time Simultaneous Sampling TSMP SAMC 4 0 TAD If the SIMSAM bit specifies sequential sampling the total interval used to convert all channels is the number of channels times the sampling time and conversion time The sampling time for an individual channel is the total interval minus the conversion time for that channel Equation 16 4 Available Sampling Time Simultaneous Sampling TSEQ Channels per Sample CH S SAMC 4 0 TAD Conversion Time TCONV TSMP TSEQ TCONV Note 1 CH S specified by CHPS lt 1 0 gt bits 2 TsEQ is the total time for the sample convert sequence 16 11 3 Event Trigger Conversion Start It is often desirable to synchronize the end of sampling and the start of conversion with some other time event The ADC module can use one of three sources as a conversion trigger External INT trigger GP Timer Compare trigger Motor Control PWM trigger 16 11 3 1 EXTERNAL INT TRIGGER When SSRC 2 0
70. multaneous sample control bit ADxCON1 lt 3 gt The CHPS and SIMSAM bits are not relevant in 12 bit mode as there is only one Sample Hold amplifier 16 9 2 Simultaneous Sampling Enable Some applications can require that multiple signals be sampled simultaneously The SIMSAM control bit ADxCON1 lt 3 gt works in conjunction with the CHPS control bits and controls the sam ple convert sequence for multiple channels as shown in Table 16 1 The SIMSAM control bit has no effect on the ADC module operation if CHPS lt 1 0 gt 00 If more than one Sample Hold ampli fier is enabled by the CHPS control bits and the SIMSAM bit is o the two or four selected chan nels are sampled and converted sequentially with two or four sampling periods If the SIMSAM bit is 1 two or four selected channels are sampled simultaneously with one sampling period The channels are then converted sequentially The SIMSAM bit is not relevant in 12 bit mode as there is only one S H DS70183A page 16 20 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC Table 16 1 Sample Conversion Control Options of Sample CHPS lt 1 0 gt SIMSAM Sample Conversion Sequence Convert Cycles Example to Complete 00 x Sample CHO Convert CHO 1 Figure 16 5 Figure 16 6 Figure 16 7 Figure 16 8 Figure 16 11 Figure 16 12 Figure 16 17 Figure 16 18 01 0 Sample CHO Convert CHO 2 Sample C
71. nerate DMA Request ALTS 1 Alternate MUX A B input select MUX A Input Select Sample MUX B Inputs AN15 gt CHO AN3 ANQ gt CH1 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request CHOSA lt 3 0 gt 0001 Select AN1 for CHO input Interrupt Repeat CHONA 0 Select VREF for CHO input CSCNA 0 No input scan CSSL lt 15 0 gt n a Scan input select unused CH123SA 0 CH1 ANO CH2 AN1 CH3 AN2 CH123NA lt 1 0 gt 0x CH1 CH2 CH3 VREF MUX B Input Select CHOSB lt 3 0 gt 1111 Select AN15 for CHO input CHONB 0 Select VREF for CHO input CH123SB 1 CH1 AN3 CH2 AN4 CH3 AN5 CH123NB lt 1 0 gt 11 CH1 AN9 CH2 AN10 CH3 AN11 DMA Buffer 1st DMA Interrupt AN1 Sample 1 ANO Sample 1 AN15 Sample 1 AN3 AN9 Sample 1 AN1 Sample 2 ANO Sample 2 AN15 Sample 2 AN3 AN9 Sample 2 DMA Buffer 2nd DMA Interrupt AN1 Sample 3 ANO Sample 3 AN15 Sample 3 AN3 AN9 Sample 3 AN1 Sample 4 ANO Sample 4 AN15 Sample 4 AN3 AN9 Sample 4 DS70183A page 16 44 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 14 5 Sampling Eight Inputs Using Simultaneous Sampling This and the next example demonstrate identical setups with the exception that this example
72. nly one conversion Equation 16 6 Available Sampling Time Sequential Sampling TsmP Trigger Pulse Interval TSEQ Conversion Time TCONV TSMP TSEQ TCONV Note TsEQis the trigger pulse interval time 2006 Microchip Technology Inc DS70183A page 16 31 dsPIC33F Family Reference Manual 16 12 CONTROLLING SAMPLE CONVERSION OPERATION The application software can poll the SAMP AD1CON1 lt 1 gt and DONE AD1CON1 lt 05 bits to keep track of A D operations or the ADC module can interrupt the CPU when conversions are complete The application software can also abort A D operations if necessary 16 12 1 Monitoring Sample Conversion Status The SAMP and DONE bits indicate the sampling state and the conversion state of the ADC respectively Generally when the SAMP bit clears indicating end of sampling the DONE bit is automatically set indicating end of conversion If both SAMP and DONE are o the ADC is in an inactive state In some operational modes the SAMP bit can also invoke and terminate sam pling 16 12 2 Generating an ADC Interrupt The SMPI lt 3 0 gt bits ADXCON2 5 2 control the generation of interrupts The interrupt occurs some number of sample conversion sequences after starting sampling and re occurs on each equivalent number of samples Note that the interrupts are specified in terms of samples and not in terms of conversions or data samples in the buffer memory If DMA transfers
73. nology Inc Section 16 Analog to Digital Converter ADC Example 16 4 Code for Channel Scanning Using DMA RRR RR IR IR IR IR IR IR IR IR IR ICR ICR IR IR TOR TOR TIO IOI IO eee ke 2005 Microchip Technology Inc FileName adcDrvl c Dependencies Header h files if applicable see below Processor dsPIC33Fxxxx Compiler MPLAB C30 v2 01 00 or higher SOFTWARE LICENSE AGREEMENT Microchip Technology Inc Microchip licenses this software to you solely for use with Microchip dsPIC digital signal controller products The software is owned by Microchip and is protected under applicable copyright laws All rights reserved SOFTWARE IS PROVIDED AS IS MICROCHIP EXPRESSLY DISCLAIMS ANY WARRANTY OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY INCIDENTAL SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES LOST PROFITS OR LOST DATA HARM TO YOUR EQUIPMENT COST OF PROCUREMENT OF SUBSTITUTE GOODS TECHNOLOGY OR SERVICES ANY CLAIMS BY THIRD PARTIES INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION OR OTHER SIMILAR COSTS FR IR IR IR IR IR IR IR TR IIR IR IR TR TR IR IR TR III IO IOI IOI IOI IO A eee ex f Hif defined dsPIC33F include p33fx
74. ochip Technology Inc Section 16 Analog to Digital Converter ADC 16 14 6 Sampling Eight Inputs Using Sequential Sampling Figure 16 22 and Table 16 7 demonstrate sequential sampling When converting more than one channel and selecting sequential sampling the ADC module starts sampling a channel at the earliest opportunity then performs the required conversions in sequence In this example with ASAM set sampling of a channel begins after the conversion of that channel completes When ASAM is clear sampling does not resume after conversion completion but occurs when the SAMP bit is set When utilizing more than one channel sequential sampling provides more sampling time since a channel can be sampled while conversion occurs on another Figure 16 22 Sampling Eight Inputs Using Sequential Sampling Conversion Trigger SAMP gt SAMP gt a A SAMP gt a ADC Clock CONVICONVIGONVICONY CONVICONVICONVICONV TCONVICONVICONVICONV Input to CHO N13 AN1 AN14 J M AN18 AN1 2 AN14 4 AN13 AN1 Input to CH1 ANO AN3 AN6 ANO ANS AN6 4 ANO Input to CH2 3 AN1 _AN4 AN7 AN1 AN4 AN7 AN1 Input to CH3 q AN2 21 d AN5 AN8 ANZ AN5 AN8 AN2 ASAM xd SAME SE 0o 0 t o7 cope 8o 00 AE DONE Buffer 0 ji Buffer 1 i m mix IO B
75. on 16 Analog to Digital Converter ADC ADxCON2 ADCx Control Register 2 R W 0 R W 0 R W 0 U 0 U 0 R W 0 R W 0 R W 0 VCFG lt 2 0 gt CSCNA CHPS lt 1 0 gt bit 15 bit 8 R 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 BUFS SMPI lt 3 0 gt BUFM ALTS bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 15 13 VCFG lt 2 0 gt Converter Voltage Reference Configuration bits VREFH VREFL 000 AVDD Avss 001 External VREF Avss 010 AVDD External VREF 011 External VREF External VREF 1xx AVDD Avss bit 12 11 Unimplemented Read as 0 bit 10 CSCNA Input Scan Select bit 1 Scan inputs for CHO during Sample A bit 0 Do not scan inputs bit 9 8 CHPS lt 1 0 gt Channel Select bits When AD12B 1 CHPS lt 1 0 gt is U 0 Unimplemented Read as o 1x Converts CHO CH1 CH2 and CH3 01 Converts CHO and CH1 00 Converts CHO bit 7 BUFS Buffer Fill Status bit only valid when BUFM 1 1 ADCis currently filling the second half of the buffer The user application should access data in the first half of the buffer 0 ADC is currently filling the first half of the buffer The user application should access data in the second half of the buffer bit 6 Unimplemented Read as 0 bit 5 2 SMPI lt 3 0 gt Increment
76. on trigger option can be used for sampling and conversion in Sleep SSRC lt 2 0 gt 111 To use the automatic conversion option the ADON bit should be set in the instruction before the PWRSAV instruction Note For the ADC module to operate in Sleep the ADC clock source must be set to RC ADRC 1 16 22 3 ADC Operation During CPU Idle Mode For the A D conversion the ADSIDL bit ADxCON1 lt 13 gt selects if the ADC module stops or con tinues on Idle If ADSIDL 0 the ADC module continues normal operation when the device enters Idle mode If the ADC interrupt is enabled ADxIE 1 the device wakes up from Idle mode when the ADC interrupt occurs Program execution resumes at the ADC Interrupt Service Routine if the ADC interrupt is greater than the current CPU priority Otherwise execution con tinues from the instruction after the PWRSAV instruction that placed the device in Idle mode If ADSIDL 1 the ADC module stops in Idle If the device enters Idle mode in the middle of a conversion the conversion is aborted The converter does not resume a partially completed conversion on exiting from Idle mode 2006 Microchip Technology Inc DS70183A page 16 61 dsPIC33F Family Reference Manual 16 23 EFFECTS OF A RESET A device Reset forces all registers to their Reset state This forces the ADC module to be turned off and any conversion in progress to be aborted All pins that are multiplexed with analog inputs a
77. onversion trigger occurs Figure 16 13 Converting Four Channels Auto Sample Start Trigger Conversion Start Simultaneous Sampling lt TSEQ Conversion FN i f FN Trigger i i i i i i ADCLK i m TCONV TCONV e TCONV 4 ICONV 4 TSAMP lt TSAMP ch0_samp i ch1_samp i ch2 samp ch3 samp Y Buffer 0 X Buffer 1 1 1 1 X 1 1 1 Buffer 2 l X Buffer 3 i i X i i i i i 1 Cleared DONE in software SAMP k 2006 Microchip Technology Inc DS70183A page 16 29 dsPIC33F Family Reference Manual 16 11 3 6 MULTIPLE CHANNELS WITH SEQUENTIAL SAMPLING As shown in Figure 16 14 when sequential sampling is used sampling for a particular channel stops just prior to converting that channel and resumes after the conversion has stopped Figure 16 14 Converting Four Channels Auto Sample Start Trigger Conversion Start Sequential Sampling TsEQ Conversion F i Y Trigger i i i i ADCLK TCONV JTCONV 9 4 ICONV ICONV ch0 samp i l TSAMP TSAMP chi samp i b 1 TSAMP gt ch2 samp i p 1 1 TSAMP gt p 1 1 ch3_samp_
78. or simultaneous sampling SAMC must always be pro grammed for at least one clock cycle When using multiple Sample Hold channels with sequential sampling programming SAMC for zero clock cycles results in the fastest possible conversion rate See Example 16 3 for code example Figure 16 7 Converting 1 Channel Manual Sample Start TAD Based Conversion Start ADC Clock ee 1 lt _ _ TSAMP M4 CONV 16 TAD SAMP ADC1BUFO DONE X Instruction ExecutionPS ET ADICON1 SAMP X DS70183A page 16 24 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC Example 16 3 Converting One Channel Manual Sample Start TAD Based Conversion Start Code D DIPCFGL OXEFFF all PORTB Digital RB12 analog DICON1 0x00E0 SSRC bit 111 implies internal counter ends sampling and starts converting ADI1CHSO 0x000C Connect RB12 AN12 as CHO input in this example RB12 AN12 is the input D ADICSSL 0 AD1CON3 Ox1F02 Sample time 31Tad Tad internal 2 Tcy ADICON2 0 AD1CON1bits ADON 1 turn ADC ON while 1 repeat continuously ADICON1bits SAMP 1 start sampling then after 31Tad go to conversion while ADICON1bits DONE conversion done ADCValue ADC1BUFO yes then get ADC value repeat 16 11 2 1 FREE RUNNING SAMPLE CONVERSION SEQUENCE As shown in Fig
79. ple convert sequence The conversion trigger source is selected by the Sample Clock Source Select SSRC 2 0 control bits ADXCON1 7 5 The conversion trigger can be taken from a variety of hardware sources or can be controlled manually in software by clearing the SAMP control bit One of the conversion trigger sources is an auto conversion The time between auto conversions is set by a counter and the ADC clock The Auto Sample mode and auto con version trigger can be used together to provide endless automatic conversions without software intervention An interrupt can be generated at the end of each sample convert sequence or after multiple sample convert sequences as determined by the value of the Samples Per Interrupt SMPI 3 0 control bits ADXCON2 5 2 The number of sample convert sequences between interrupts can vary between 1 and 16 The total number of conversion results between interrupts is the product of the channels per sample and the SMPI 3 0 value However since only one conversion result is stored in ADCxBUFO each execution of the interrupt service routine can be used to read only one conversion result If multiple conversion results need to be buffered a DMA buffer should be used to store the con version results In this case the SMPI lt 3 0 gt bits are used to select how often the DMA RAM buffer pointer is incremented The frequency of incrementing the DMA RAM buffer pointer should not exceed the DMA RAM buffer
80. quest Interrupt Repeat DMA Buffer 2nd DMA Interrupt AN13 AN1 Sample 3 ANO Sample 3 AN1 Sample 3 AN2 Sample 3 AN14 Sample 3 AN3 AN6 Sample 3 AN4 AN7 Sample 3 AN5 AN8 Sample 3 AN13 AN1 Sample 4 ANO Sample 4 AN1 Sample 4 AN2 Sample 28 AN14 Sample 4 AN3 AN6 Sample 4 AN4 AN7 Sample 4 AN5 AN8 Sample 4 DS70183A page 16 48 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC 16 15 A D SAMPLING REQUIREMENTS The analog input model of the 10 bit and 12 bit ADC modes are shown in Figure 16 23 and Figure 16 24 The total sampling time for the A D conversion is a function of the internal amplifier settling time and the holding capacitor charge time For the ADC module to meet its specified accuracy the charge holding capacitor CHOLD must be allowed to fully charge to the voltage level on the analog input pin The analog output source impedance Rs the interconnect impedance Ric and the internal sampling switch Rss impedance combine to directly affect the time required to charge the capacitor CHOLD The com bined impedance must therefore be small enough to fully charge the holding capacitor within the chosen sample time To minimize the effects of pin leakage currents on the accuracy of the ADC module the maximum recommended source impedance RS is 2009 After the analog input channel is selected this sampl
81. re configured as analog inputs The corresponding TRIS bits are set The value in the ADCxBUFO register is not initialized during a Power on Reset and contain unknown data 16 24 SPECIAL FUNCTION REGISTERS ASSOCIATED WITH THE ADC The following table lists dsPIC33F ADC Special Function registers including their addresses and formats All unimplemented registers and or bits within a register are read as zeros DS70183A page 16 62 2006 Microchip Technology Inc oul Bojouuoe diydosdI 9002 9 9 ebed veg1ozsa Table 16 10 ADC Register Map FileName ADR Bit15 Bit14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset States INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIVOERR DMACERR MATHERR ADDRERR STKERR OSCFAIL 0000 INTCON2 0082 ALTIVT DISI INT4EP INT3EP INT2EP INT1EP INTOEP 0000 IFSO 0084 DMAIIF ADIIF U1TXIF UiRXIF SPHIF SPHEIF T3IF T2IF OC2IF IC2IF DMAOIF THIF OCilF IC1IF INTOIF 0000 IFS1 0086 U2TXIF U2RXIF INT2IF TSIF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF AD2IF INT1IF CNIF MI2C1IF SI2C1IF 0000 IECO 0094 DMAIIE ADIIE UITXIE U1RXIE SPHIE SPHEIE T3IE TIE OC2IE IC2IE DM
82. result is stored in the user config ured DMA buffer Then the AN1 input is sampled and converted This process of scanning the inputs repeats 16 times until the buffer is full Then the ADC module generates an interrupt The entire process then repeats Figure 16 18 Scanning Through 16 Inputs Interrupt Conversion Trigger a TSAMP gt a TSANP gt 1 5s T5AMP gt lt _ISAMP gt gs ADC Clock sg 1 A CONV CONV i CONV ICONV Input to CHO ANO AN1 ss j AN14 AN15 ASAM i SAMP 3s O LO TS Lo To DONE i i 55 i D i i Buffer 0 X Boer 1 s uffer T 7 A s i i i i Buffer 2 p X i i p i i i Buffer 15 1 1 1 35 7 7 15 M X AD1IF i m BSET AD1CON1 ASAM X Instruction Execution f i 2006 Microchip Technology Inc DS70183A page 16 39 dsPIC33F Family Reference Manual Table 16 3 Scanning Through 16 Inputs per DMA Interrupt CONTROL BITS Sequence Select DMA Interrupt on 16th conversion OPERATION SEQUENCE SMPI lt 3 0 gt 1111 AMODE 00 DMAxONT 15 Sample MUX A Inputs ANO gt CHO convert CHO write ADC1BUFO and generate DMA Request Sample MUX A Inputs AN1 gt CHO convert CHO write ADC1BUFO and generate DMA Request CHPS lt 1 0 gt 00 Sample Channel CHO Sample MUX A Inputs AN2 gt CHO convert CHO
83. rite ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request Convert CH2 write ADC1BUFO and generate DMA Request Convert CH3 write ADC1BUFO and generate DMA Request Sample MUX B Inputs AN14 gt CHO AN3 AN6 gt CH1 AN4 AN7 gt CH2 AN5 ANB8 gt CH3 Convert CHO write ADC1BUFO and generate DMA Request Convert CH1 write ADC1BUFO and generate DMA Request Convert CH2 write ADC1BUFO and generate DMA Request Convert CH3 write ADC1BUFO and generate DMA Request Interrupt CHONB 0 Select VREF for CHO input Repeat CH123SB 1 CH1 AN3 CH2 AN4 CH3 AN5 CH123NB lt 1 0 gt 10 CH1 AN6 CH2 AN7 CH3 AN8 DMA Buffer 1st DMA Interrupt AN13 AN1 Sample 1 ANO Sample 1 AN1 Sample 1 AN2 Sample 1 AN14 Sample 1 AN3 AN6 Sample 1 AN4 AN7 Sample 1 AN5 AN8 Sample 1 AN13 AN1 Sample 1 ANO Sample 2 AN1 Sample 2 AN2 Sample 2 AN14 Sample 2 AN3 AN6 Sample 2 AN4 AN7 Sample 2 AN5 AN8 Sample 2 DMA Buffer 2nd DMA Interrupt AN13 AN1 Sample 3 ANO Sample 3 AN1 Sample 3 AN2 Sample 3 AN14 Sample 3 AN3 AN6 Sample 3 AN4 AN7 Sample 3 AN5 AN8 Sample 3 AN13 AN1 Sample 4 ANO Sample 4 AN1 Sample 4 AN2 Sample 4 AN14 Sample 4 AN3 AN6 Sample 4 AN4 AN7 Sample 4 AN5 AN8 Sample 4 DS70183A page 16 46 2006 Micr
84. stance CHOLD Sample Hold capacitance from DAC Note CPIN value depends on device package and is not tested Effect of CPIN negligible if Rs lt 5 kQ 2006 Microchip Technology Inc DS70183A page 16 49 dsPIC33F Family Reference Manual 16 16 READING THE ADC RESULT BUFFER The RAM is 10 bits or 12 bits wide but the data is automatically formatted to one of four select able formats when the buffer is read The FORM lt 1 0 gt bits ADCON1 lt 9 8 gt select the format The formatting hardware provides a 16 bit result on the data bus for all of the data formats Figure 16 25 and Figure 16 26 show the data output formats that can be selected using the FORM lt 1 0 gt control bits Figure 16 25 A D Output Data Formats 10 bit Mode RAM Contents d09 d08 d07 d06 d05 d04 d03 d02 dO1 dOO Read to Bus Integer O 0 0 0 O O d09 d08 dO7 d06 dO5 d04 dO3 d02 d01 doo Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 dO1 doo Fractional 1 15 d09 d08 d07 d06 d05 d04 d03 d02 d01 doo 0 0 0 0 04 0 Signed Fractional 1 15 d09 d08 d07 d06 d05 d04 d03 d02 d01 doo 0 0 0 0 0 0 Figure 16 26 A D Output Data Formats 12 bit Mode RAM Contents dii d10 d09 d08 d07 d06 d05 d04 d03 d02
85. sters determine which analog inputs are selected for each sample Additionally the selected inputs can vary on an alternating sample basis or on a repeated sequence of samples The same analog input can be connected to two or more Sample Hold channels to improve con version rates Note Different devices will have different numbers of analog inputs Verify the analog input availability against the device data sheet 16 7 1 Configuring Analog Port Pins The ADPCFGH and ADPCFGL registers specify the input condition of device pins used as ana log inputs Along with the Data Direction TRISx register in the Parallel I O Port module these registers control the operation of the ADC pins A pin is configured as analog input when the corresponding PCFGn bit ADPCFGH lt n gt or ADPCFGL n is clear The ADPCFGH and ADPCFGL registers are clear at Reset causing the ADC input pins to be configured for analog input by default at Reset When configured for analog input the associated port I O digital input buffer is disabled so it does not consume current The port pins that are desired as analog inputs must have their corresponding TRIS bit set spec ifying port input If the I O pin associated with an A D input is configured as an output the TRIS bit is cleared and the port s digital output level VoH or VOL is converted After a device Reset all TRIS bits are set A pin is configured as digital I O when the corresponding PC
86. three inputs frequently using Sample Hold channels CH1 CH2 and CH3 while four other inputs are sampled less frequently by scanning them using Sample Hold channel CHO In this case only MUX A inputs are used and all four channels are sampled simultaneously Four different inputs AN4 AN5 AN6 AN7 are scanned in CHO whereas ANO AN1 and AN2 are the fixed inputs for CH1 CH2 and CH3 respectively Thus in every set of 16 samples ANO AN1 and AN2 are sam pled four times while AN4 AN5 AN6 and AN7 are sampled only once each Figure 16 19 Converting Three Inputs Four Times and Four Inputs One Time Interrupt Conversion Dog j Trigger r ISAMP C ISAMP lt L ISAMP a ADC Clock m TCONVICONVICONVICONY TCONVICONVICONVICONY TCONVICONVICONVICONY Input to CHO ANS mwy w my Tan Input to CH1 AN M AN RAN ANO ANO Input to CH2 ANT ANT AN1 ANT Input to CH3 AN2 1 AN AN2 AN2 ASAM di SAMP NC DONE l e oa oe Buffer 0 Y INE 1 L 1 m oS IO Buffet mss i X i po Buffer l 5 X i T T 5 T Buffer 3 X je Buffer 12 X Buffer 13 7 X Buffer 14 i E X Buffer 15 i r LLL x AD1IF 2006 Microchip Technology Inc DS70183A page 16 41 dsPIC33F Family Reference Manual Table 16 4 CONTROL BITS Sequence Select SMPI lt 3 0 gt 0011 AMODE
87. uccessive Approximation SAR conversion Conversion speeds of up to 1 1 Msps Up to 32 analog input pins External voltage reference input pins Simultaneous sampling of up to four analog input pins Automatic Channel Scan mode Selectable conversion trigger source Selectable Buffer Fill modes DMA support including Peripheral Indirect Addressing Four result alignment options signed unsigned fractional integer Operation during CPU Sleep and Idle modes Depending on the particular device pinout the ADC can have up to 32 analog input pins desig nated ANO through AN31 In addition there are two analog input pins for external voltage refer ence connections These voltage reference inputs can be shared with other analog input pins The actual number of analog input pins and external voltage reference input configuration will depend on the specific device Refer to the device data sheet for further details The analog inputs are multiplexed to four Sample Hold amplifiers designated CHO CH3 One two or four of the Sample Hold amplifiers can be enabled for acquiring input data The analog input multiplexers can be switched between two sets of analog inputs during conversions Uni polar differential conversions are possible on all channels using certain input pins see Figure 16 1 An Analog Input Scan mode can be enabled for the CHO Sample Hold Amplifier A Control register specifies which analog input channels are incl
88. uded in the scanning sequence The ADC is connected to a single word result buffer However multiple conversion results can be stored in a DMA RAM buffer with no CPU overhead Each conversion result is converted to one of four 16 bit output formats when it is read from the buffer The 12 bit ADC configuration AD12B 1 supports all the above features except n the 12 bit configuration conversion speeds of up to 500 ksps are supported There is only one Sample Hold amplifier in the 12 bit configuration so simultaneous sampling of multiple channels is not supported DS70183A page 16 2 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC Figure 16 1 ADC Block Diagram AVDD oc o vner Dx oO AVss oc o vner X oo ANO Dx e ANO eg S H 1 ADC RE 07 0 AN1 Conversion 1 Conversion Logic lt gt ANI XI M AN4 E e CH22 Result H o O AN10 oo 16 bit VREF ADC Result gt Buffer AN2 x AN2 5 ANS AHAN cua S H co e ANB e CHO CH1 AN11 CH2 CH3 _ o e Sample Sequence VREF Control Data Format Bus Interface 000107 5 Input Input MUX 1 000115 Switches Control AN3 AN4 AN5 Analog Input Pins AN6 AN8 AN9 AN10
89. uffer 2 x SS r i i Buffer 3 X po eie Buffer 12 5 X 35 r Buffer veta em s X Buffer 14 i i X 4 e irr i 1 Buffer 15 3 X 55 AD1IF l TEES 2006 Microchip Technology Inc DS70183A page 16 47 dsPIC33F Family Reference Manual Table 16 7 CONTROL BITS Sequence Select Alt sampling DMA interrupt on 16th sample Sampling Eight Inputs Using Sequential Sampling OPERATION SEQUENCE SMPI lt 3 0 gt 0001 AMODE 00 DMAxONT 15 Sample AN13 AN1 gt CHO convert CHO write ADC1BUFO and generate DMA Request CHPS lt 1 0 gt 1x Sample Channels CHO CH1 CH2 CH3 Sample ANO gt CH1 convert CHO write ADC1BUFO and generate DMA Request SIMSAM 0 Sample all channels sequentially Sample AN1 gt CH2 convert CHO write ADC1BUFO and generate DMA Request BUFM 0 Single 16 word result buffer Sample AN2 gt CH3 convert CHO write ADC1BUFO and generate DMA Request ALTS 1 Alternate MUX A B input select Sample AN14 gt CHO convert CHO write ADC1BUFO and generate DMA Request MUX A Input Select Sample AN3 AN6 gt CH1 convert CHO write ADC1BUFO and generate DMA Request CHOSA lt 3 0 gt 0110 Select AN6 for CHO input Sample AN4 AN7 gt CH2 convert CHO write ADC1BUFO and generate DMA Request No input scan CHONA 0 Sample AN5 AN8 gt CH3 convert CHO Select V
90. ure 16 8 using the Auto Convert Conversion Trigger mode SSRC 111 in combination with the Auto Sample Start mode ASAM 1 allows the ADC module to schedule sample conversion sequences with no intervention by the user or other device resources This Clocked mode allows continuous data collection after module initialization Note This A D configuration must be enabled for the conversion rate of 750 ksps Figure 16 8 Converting One Channel Auto Sample Start TAD Based Conversion Start ADC Clock UU UU UUUUL TSAMP gt a TCONV gt TSAMP CONV lt 16 TAD 16 TAD SAMP DONE i i i i Buffer 0 i X i i Buffer 1 i i X Instruction Execution BSET ADICON1 ASAM i i 2006 Microchip Technology Inc DS70183A page 16 25 dsPIC33F Family Reference Manual 16 11 2 2 MULTIPLE CHANNELS WITH SIMULTANEOUS SAMPLING As shown in Figure 16 9 when using simultaneous sampling the SAMC value specifies the sam pling time In the example SAMC specifies a sample time of 3 TAD Because automatic sample start is active sampling starts on all channels after the last conversion ends and continues for three A D clocks Figure 16 9 Converting Four Channels Auto Sample Start TAD Conversion Start Simultaneous Sampling ADCLK lt TCONV gt lt TCONV gt lt TCONV Ts TCONV CONV T
91. uses simultaneous sampling SIMSAM 1 and the following example uses sequential sam pling SIMSAM 0 Both examples use alternating inputs and specify differential inputs to the Sample Hold Figure 16 21 and Table 16 6 demonstrate simultaneous sampling When converting more than one channel and selecting simultaneous sampling the ADC module samples all channels then performs the required conversions in sequence In this example with ASAM set sampling begins after the conversions complete Figure 16 21 Sampling Eight Inputs Using Simultaneous Sampling Conversion 1 I i 1 Trigger ISAMP gt ISAMP gt A 3S CISAMP gt Pa ADC Clock lt c TCONVICONVICONVICONY TCONVICONVICONVICONY TCONVICONVICONVICONV ET i Input to CHO AN13 AN1 x ANI4 ii ANI4 AN13 ANT Input to CH1 AN0 AN3 AN6 C S ANG ANG X ANO Input to CH2 X ANT ANA AN7 SS ANZ AN7 X ANI Input to CH3 __AN2_ AN5 AN8 7 ANS ANG X AN2 ASAM LE BAM SO DONE a tS Buffer O X f f gp Buffer 1 X j f ee Buffer 2 X 55 i Buffer 3 X i lt 55 Buffer 12 fd X j Buffer 13 i Buffer 14 i Ds esi Buffer 15 2006 Microchip Technology Inc DS70183A page 16 45 dsPIC33F Family Reference Manual Table 16 6 CONTROL BITS Sequence Select SMPI 3 0 0001 AMODE 00 DMAXCNT
92. versions The Sample Clock Source Select SSRC lt 2 0 gt bits ADxCON1 lt 7 5 gt select the source of the conversion trigger Note The available conversion trigger sources can vary depending on the device variant Please refer to the specific device data sheet for the available conversion trigger sources Note The SSRC lt 2 0 gt selection bits should not be changed when the ADC module is enabled If you change the conversion trigger source be sure the ADC module is disabled first by clearing the ADON bit ADXCON1 lt 15 gt 16 11 1 Manual When SSRC lt 2 0 gt 000 the conversion trigger is under software control Clearing the SAMP bit ADxCON1 lt 1 gt starts the conversion sequence Figure 16 5 is an example where setting the SAMP bit initiates sampling and clearing the SAMP bit terminates sampling and starts conversion The user software must time the setting and clearing of the SAMP bit to ensure adequate sampling time of the input signal See Example 16 1 for code example Figure 16 5 Converting 1 Channel Manual Sample Start Manual Conversion Start ADC Clock aL E TSAMP gt TCONV gt Instruction Execution BSET AD1CON1 SAMP Y BCLR AD1CON1 SAMP DS70183A page 16 22 2006 Microchip Technology Inc Section 16 Analog to Digital Converter ADC Example 16 1 Converting 1 Channel Manual Sample Start Manual Conversion Start Code
93. xxx h elif defined PIC24H include p24hxxxx h endif void ProcessADCSamples unsigned int AdcBuffer void initAdcl void LCON1bits FORM LCON1bits SSRC LCON1bits ASAM 1CON1bits AD12B LCON1bits SIMSAM Data Output Format Signed Fraction Q15 format Sample Clock Source GP Timer starts conversion ADC Sample Control Sampling begins immediately after conversion i 10 bit ADC operation i Samples multiple channels individually in sequence pppps UOUCOUOU I OoOonN Uv N nu AD1CON2bits BUFM AD1CON2bits CSCNA 1 Scan Input Selections for CH0 during Sample A bit I eo ADICON2bits CHPS 0 Converts CHO ADICON3bits ADRC 0 ADC Clock is derived from Systems Clock ADICON3bits ADCS 63 ADC Conversion Clock AD1CHSO A D Input Select Register AD1CHSObits CHOSA MUXA ve input selection AINO for CHO ADICHSObits CHONA MUXA ve input selection Vref for CHO 0 0 2006 Microchip Technology Inc DS70183A page 16 55 dsPIC33F Family Reference Manual Example 16 4 Code for Channel Scanning Using DMA Continued AD1CHS123 A D Input Select Register AD1CHS123bits CH123SA 0 MUXA ve input selection AINO for CH1 AD1CHS123bits CH123NA 0 MUXA ve input selection Vref for CH1 AD1CSSH AD1CSSL A D Input Scan Selection Register AD1CSSH 0x0000 AD1CSSL 0x000F Scan AINO AIN1 AIN2 AIN3 inputs AD1CON1bits AD
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