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BasicBoard

1. Most of the pins available in the expansion connectors can be used as general purpose pins see Table 9 However some pins can be used to access specific resources in the FPGA Digital Looked Loops DLLs Threshold Reference Voltages etc For further information on the Spartan XC2S300E pinout please see the datasheets available at the Xilinx website www xilinx com 10 Copyright 2004 Coreworks Lda coreworks Ida http www coreworks pt CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 Pin Name FPGA pin Direction Pin Name FPGA pin Direction c01 GND o D01 45 1 0 c02 VU 0 D02 44 1 0 C03 VDD 3 3 V O D03 46 1 0 C04 16 1 0 D04 125 VO C05 GCK3 Input 185 l D05 122 VO C06 17 1 0 D06 123 1 0 C07 175 1 0 D07 47 VO C08 174 1 0 D08 121 VO Cog 173 1 0 D09 115 VO C10 169 1 0 D10 23 VO C11 168 1 0 D11 113 1 0 C12 167 1 0 D12 114 1 0 C13 166 1 0 D13 111 VO C14 165 1 0 D14 112 1 0 C15 164 1 0 D15 109 1 0 C16 163 1 0 D16 110 1 0 C17 162 1 0 D17 102 VO C18 20 1 0 D18 48 1 0 C19 GCK2 Input 182 l D19 100 VO C20 154 1 0 D20 101 VO C21 152 1 0 D21 98 1 0 C22 151 1 0 D22 99 VO C23 150 1 0 D23 96 VO C24 149 1 0 D24 97 1 0 C25 148 1 0 D25 94 VO C26 147 1 0 D26 95 VO C27 146 1 0 D27 89 1 0 C28 21 1 0 D28 93 1 0 C29 GCK1 Input 77 l D29 87 1 0 C30
2. E L L N oO 7 52 ed e D Latches D Latches D Latches D Latches o5 N e co LEDs FPGA Se 6VDC O O LEDs gt as Power Jack Power O LED7 oO LED EEDE Xilinx LEDS x E Power a O LED4 C25300 Switch O LED3 _ LED2 PROM e O LED1 Jumpers OSC E E HE 52 Oo _ E BE S58 3S e 25 o T STE SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 Q E E as Pe 5 Switches e sw9 Pushbuttons COMM CONF Figure 1 Simplified layout of the BasicBoard 4 Copyright 2004 Coreworks Lda coreworks Ida http www coreworks pt CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 POWER SUPPLY The BasicBoard uses a 6V DC power supply The power supply should have a 2 1 mm female center positive plug and be capable of delivering at least 500 mA The board can be switch on and off using the power switch next to the power jack The board is properly powered when the Power LED is turned on JUMPER SETTINGS The jumpers select the FPGA configuration mode Please see the next section FPGA Configuration for further details By default the jumpers MO M1 and M2 are not placed FPGA CONFIGURATION The FPGA configuration can be loaded from a PC parallel port or from a PROM not included in the kit Typically the FPGA configuration is loaded from a PC In this situation the parallel port should be used The signals required by the JTAG programming mode pass throughout this port To
3. 140 1 0 D30 88 1 0 C31 139 1 0 D31 84 1 0 C32 138 1 0 D32 86 VO C33 136 1 0 D33 82 1 0 C34 22 1 0 D34 83 VO C35 134 1 0 D35 75 1 0 C36 133 1 0 D36 81 1 0 C37 132 1 0 D37 73 1 0 C38 129 1 0 D38 74 VO C39 127 1 0 D39 70 1 0 C40 43 1 0 D40 71 VO Table 9 FPGA pins for the expansion connectors C and D 11 Copyright 2004 Coreworks Lda coreworks Ida http www coreworks pt
4. support the JTAG mode additional circuitry is included in the BasicBoard In order to prevent a communication failure between the PC and the FGPA the power supply must be turned on before attaching the parallel cable To load the configuration from a host computer follow these steps 1 apply power to the board 2 attach the parallel cable included in the kit between the PC and the parallel port connector of the BasicBoard 3 set the slide switch SW9 to the CONF position 4 remove all jumpers MO M1 and M2 5 runthe appropriate configuration software in the PC e g IMPACT from Xilinx To configure the FPGA from a PROM follow these steps 1 place the programmed PROM into the 8 pin socket labeled PROM 2 setthe slide switch SW9 to the COMM position 3 add all jumpers MO M1 and M2 4 power on the board 5 Copyright 2004 Coreworks Lda coreworks Ida http www coreworks pt CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 BASICBOARD COMPONENTS The BasicBoard provides the following resources one 55 MHz crystal oscillator eight leds four 7 segment displays eight slide switches five pushbuttons one RS 232 port one Parallel port two 40 pin expansion connectors These resources are shown in the simplified layout of the BasicBoard Figure 1 and are described in the following sections OSCILLATOR The BasicBoard i
5. CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 BasicBoard FPGA Development and Evaluation Board User Manual Copyright 2004 Coreworks Lda coreworks Ida http www coreworks pt CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 TABLE OF CONTENTS FEATURES ieee cites sc ga Aaa Dada ogee iii 3 DESCRIPTION citrico apatte ha tvavaut agus e api EE ads 4 POWER SUPPLY csi a a E E 5 JUMPER SETTINGS rerna a ele Ee ee i 5 FPGA CONFIGURATION cisci incici eita a db da 5 BASICBOARD COMPONENTS scorrono eiee eane eneee eaii ia 6 OS CILEA TOR a a eas E A EE E EE E E E E ETE 6 MES isso E daa 6 SEVEN SEGMENT DISPLAYS eccccecccceeeeceeeeececeeeeeeceeeeeaeeecaeeeseneeseaeeseaeeeseaeeeeeeeeesneeeeeaeess 6 SLIDE SWITCHES ioiii a a aoa aaa eE aa S ai a EEE 7 PUSHBUT TONS r Gilles dele hades die ii 7 RS2232 PORT iii A A E E E T E E EA 8 PARALLEL PORT encena A ea 8 EXPANSION CONNECTORS 22 e cceeeeceeeeeeeeeeeeceseeeeaeeeseaeeseeaeeccaeesesaeeeseeesaeessaeeeseeeeseeeetees 9 2 Copyright 2004 Coreworks Lda coreworks Ida http www coreworks pt CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 Block Diagram of the BasicBoard 55 MHz 7 segment PROM oscillator disp
6. al communication COMM position Table 8 shows the mapping between the FPGA pins and the parallel port interface The parallel port pinout is shown in Figure 3 EPP Function Write Enable Address Data 1 Address Data 2 Address Data 3 Address Data 4 Address Data 5 Address Data 6 Address Data 7 Address Data 8 Interrupt Wait not connected not connected Data Strobe not connected Reset Ground Table 8 FPGA pins for the parallel port EPP Mode CRR RR RR RRR RRR PREPA Figure 3 Parallel port front view EXPANSION CONNECTORS Expansion boards with specialized circuitry can be connected to the BasicBoard through expansion connectors C and D The connector pins have a pitch spacing of 100 mils or 2 54 mm The ground GND is available on pin 1 of connector C C01 the VDD 3 3 V is routed to pin C03 and pin C02 provides a Voltage Unregulated VU signal direct connection to the voltage provided by the 6 V DC power jack All other pins in connectors C and D are routed directly to the FPGA Among those pins three of them are connected to dedicated FPGA clock pins These inputs are available in pins CO5 C19 and C29 connector C Table 9 shows the mapping between the FPGA pins and the expansion connectors C and D 9 Copyright O 2004 Coreworks Lda coreworks Ida http www coreworks pt CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004
7. cBoard provides an assortment of the most frequently used interfaces for basic laboratory work These interfaces include eight slide switches five pushbuttons eight LEDs and four 7 segment displays There are also two independent expansion connectors with a total of 74 general purpose I O pins connected directly to the FPGA 3 Global Clock inputs GCK and 3 power pins 3 3 VDC Ground and Voltage Unregulated For basic communication with a PC or other equipment the board includes an RS 232 port and a parallel port The parallel port is used to send the configuration file to the FPGA Alternatively the configuration can be stored in a PROM and loaded at power up The PROM is an optional component and a socket is provided for it The BasicBoard is designed to mate with other Coreworks boards by means of the expansion connectors C and D This document describes the main blocks available in the BasicBoard All input output interfaces are described in particular as well as the mapping between the FPGA pins and each I O interface The FPGA configuration options are also described DISP4 DISP3 DISP2 DISP1 eeooeee z RS 232 l gt Hear Ol
8. es SLIDE SWITCHES The BasicBoard contains an array of eight slide switches When closed or ON each slide switch pulls the FPGA pin to ground When the slide switch is open or OFF the pin is pulled high Table 4 shows the mapping between the FPGA pins and each slide switch Slide switch FPGA pin Sw1 SW2 Table 4 FPGA pins for the slide switches PUSHBUTTONS The BasicBoard has five pushbuttons When pressed each pushbutton pulls the FPGA pin to VDD Otherwise the pin is pulled to ground through a resistor The connections between the FPGA and the pushbuttons are presented in Table 5 7 Copyright 2004 Coreworks Lda coreworks Ida http www coreworks pt CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 Pushbutton FPGA pin Table 5 FPGA pins for the pushbuttons RS 232 PORT The BasicBoard has a 9 pin RS 232 port that provides an interface to transmit and receive serial data streams TXD and RXD respectively as well as the flow control signals RTS CTS and DSR The pin functions on the BasicBoard RS 232 port are identical to those found ona PC serial port When the BasicBoard and the PC are to communicate a DTE to DCE cable straight thru cable should be used Table 6 shows the mapping between the FPGA pins and the RS 232 interface The RS 232 pinout is shown in Figure 2 RS 232 signal RS 232 pin FPGA pin Direction RS 232 Fu
9. lays optional 4 e Latches 2 4 AO y 28 N co FPGA us z Xilinx Spartan 3 XC2S300E E sit 33 S 58 Qa c a x E ig LEDs Sigs Pushbuttons switches FEATURES Features a Xilinx Spartan lIIE FPGA XC2S300E with a capacity of 300 000 equivalent system gates Resources for basic lab work five pushbuttons eight LEDs four 7 segment displays and eight slide switches Includes a 55 MHz oscillator useful as a system clock Parallel Port for FPGA configuration and communication purposes RS 232 interface for serial communication Includes two 40 pin expansion connectors with 74 general purpose I Os and 3 FPGA Global Clock Inputs Designed to mate with other Coreworks peripheral by means of the expansion connectors Typical applications basic lab teaching specific applications using dedicated boards plugged to the expansion connectors audio video etc Copyright 2004 Coreworks Lda coreworks Ida http www coreworks pt CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 DESCRIPTION The BasicBoard is an FPGA development and evaluation board suitable for implementation of a wide range of application circuits The board features a Xilinx Spartan IIE FPGA XC2S300E which has a capacity for implementing circuits with up to 300K system gates of complexity A simplified layout of the BasicBoard is shown in Figure 1 The Basi
10. nction 3 2 Transmit Data 7 Request to Send Clear to Send Table 6 FPGA pins for the RS 232 port 00900 0000 Figure 2 RS 232 connector front view o 3 to 2 O 6 20 O DataSetReady 7 pt 8 O PARALLEL PORT The BasicBoard contains a parallel port connector 25 pins female connector This interface establishes a communication channel between a computer and the FPGA The BasicBoard supports both SPP Simple Parallel Port and EPP Enhanced Parallel Port IEEE 1284 protocols The EPP protocol is highly recommended because provides a bidirectional data channel and a much higher data transfer rate see Table 7 NOTE The parallel port must be configured to the selected protocol SPP or EPP In a PC the parallel port protocol is changed in the BIOS setup To enter the BIOS setup the appropriate key F2 DEL etc must be pressed while the system is starting up Maximum Transfer Rate Port Mode MB s Direction SPP 0 15 Unidirectional PC gt BasicBoard EPP 2 Bidirectional Table 7 Comparison between SPP and EPP modes 8 Copyright 2004 Coreworks Lda coreworks Ida http www coreworks pt CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 The FPGA configuration can be loaded using the parallel port interface The slide switch SW9 toggles between the configuration mode CONF position and the norm
11. s shipped with a 55 MHz oscillator whose output is connected to the FPGA GCKO input pin 80 The oscillator module is assembled in an 8 pin socket labeled OSC When a different frequency is required this oscillator can be replaced by any compatible device LEDS The BasicBoard provides eight individual LEDs All of these LEDs are active high Table 1 shows the FPGA pins connected to the LEDs LED FPGA pin Table 1 FPGA pins for the LEDs SEVEN SEGMENT DISPLAYS The BasicBoard provides four seven segment displays Each seven segment display is driven by external D type latches The latches are grouped in arrays of 8 latches one array for each seven segment display Each array is addressed by an enable signal provided by the FPGA see Table 2 The latch is writable when the enable signal is pulled high 6 Copyright 2004 Coreworks Lda coreworks Ida http www coreworks pt CWdeb01 BasicBoard FPGA DEVELOPMENT AND EVALUATION BOARD PRELIMINARY USER MANUAL April 13 2004 Display FPGA pin DISP1 DISP2 DISP3 DISP4 Table 2 FPGA pins for the latch enable signal of each display Each segment in each enabled display is controlled by an FPGA output The segment turns on when the FPGA output is pulled to ground active low signal Table 3 shows the FPGA pins for driving the latches of each segment Segment FPGA pin A 194 193 E F Table 3 FPGA pins for the segment drivers latch

BasicBoard

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