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MC68HC16R1/ MC68HC916R1 USER`S MANUAL

1. Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV 2 V C BITB Bit Test B M IND8 X c9 ff 6 A A 0 IND8 Y D9 ff 6 IND8 Z E9 ff 6 IMM8 F9 ii 2 IND16 X 1709 gggg 6 IND16 Y 17D9 9999 6 IND16 2 17 9 999g 6 EXT 17F9 hh Il 6 E X 27C9 6 E Y 27D9 6 E Z 27 9 6 BLE Branch if Less Than or If Z N V 1 branch REL8 BF 6 2 Equal to Zero BLS2 Branch if Lower or If C Z 1 branch REL8 B3 rr 6 2 Same BLT Branch if Less Than If N V 1 branch REL8 BD 6 2 Zero BMI2 Branch if Minus If N 1 branch REL8 BB 6 2 BNE Branch if Not Equal If Z 0 branch REL8 B6 rr 6 2 BPL2 Branch if Plus If N 0 branch REL8 BA rr 6 2 BRA Branch Always If 1 1 branch REL8 B0 rr 6 BRCLR2 Branch if Bit s Clear If M Mask 0 branch IND8 X CB mm ff rr 10 12 IND8 Y DB mm ff rr 10 12 IND8 Z EB mm ff rr 10 12 IND16 X 0A mm gggg 10 14 rrr IND16 Y 1A mm gggg 10 14 rrr IND16 Z 2A mm gggg 10 14 rrr EXT 3A mm hhll 10 14 rrr BRN Branch Never If 1 0 branch REL8 1 2 BRSET2 Branch if Bit s Set If M Mask 0 branch IND8 X 8B mm ff rr 10 12 IND8 Y 9B mm ff rr 10 12 IND8 Z AB mm ff rr 10 12 IND16 X 0B mm gggg 10 14 rrr IND16 Y 1B mm gggg 10 14 rrr IND16 Z 2B mm gggg 10 14 rrr EXT 3B mm hhll 10 14 r
2. Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV 2 V C ANDB AND B M B IND8 X C6 ff 6 os AY 0s IND8 Y D6 ff 6 IND8 Z E6 ff 6 IMM8 F6 ii 2 IND16 X 17C6 gggg 6 IND16 Y 17D6 9999 6 IND16 2 17 6 999g 6 EXT 17F6 hh Il 6 E X 27C6 6 EY 27D6 6 E Z 27E6 6 ANDD AND D D e M M 1 gt D IND8 X 86 ff 6 ou A 0 IND8 Y 96 ff 6 IND8 Z A6 ff 6 IMM16 37B6 jj kk 4 IND16 X 37C6 9999 6 IND16 Y 37D6 999g 6 IND16 Z 37E6 999g 6 EXT 37F6 hh Il 6 E X 2786 6 EY 2796 6 E Z 27 6 m 6 ANDE AND E E e M M 1 gt E IMM16 3736 jj kk 4 0 IND16 X 3746 999g 6 IND16 Y 3756 9999 6 IND16 Z 3766 9999 6 3776 hh Il 6 ANDP AND CCR CCR IMM16 CCR IMM16 373A jj kk 4 A A AJA A A A ASL Arithmetic Shift Left IND8 X 04 ff 8 A SSS IND8 Y 14 ff 8 CHITI npg z 24 ff 8 IND16 X 1704 999g 8 IND16 Y 1714 999g 8 IND16 Z 1724 999g 8 EXT 1734 hh Il 8 ASLA Arithmetic Shift Left A INH 3704 2 See LA A GALIN ko b7 bo ASLB Arithmetic Shift Left B INH 3714 2 A A p cH ko b7 bo ASLD Arithmetic Shift Left D INH 27F4 2 AAA e TT Lk 015 bo ASLE Arithmetic Shift Left E INH 2774 2 A rt 5 b
3. D 27 D 4 Masked ROM D 28 D 4 1 Masked ROM Module Configuration Register D 28 D 4 2 ROM Array Base Address Registers D 30 D 4 3 HOM Signature Registers D 30 D 4 4 ROM Bootstrap esccain aa D 31 D 5 Analog to Digital Converter D 32 D 5 1 ADC Module Configuration Register D 33 D 5 2 ADC Test Register indo re D 33 D 5 3 Port ADA Data Register die ete brem odo tec n era tee D 33 D 5 4 Control Register O ge D 34 D 5 5 Control Register rre bo D 35 D 5 6 Status Register MC EE D 39 D 5 7 Right Justified Unsigned Result Register D 39 D 6 Multichannel Communication Interface Module D 41 D 6 1 MCCI Module Configuration Register D 41 D 6 2 MCCI Md einge D 42 D 6 3 SCI Interrupt Level Register D 42 D 6 4 MCCI Interrupt Vector Register D 43 D 6 5 SPI Interrupt Level Register esses D 43 D 6 6 MCCI Pin Assi
4. Current DATA DATA Next Cycle Transfer Case 5121 SIZO ADDRO DSACK1 DSACKO 15 8 7 0 Cycle 1 Byte to 8 bit port even 0 1 0 1 0 OPO 2 Byte to 8 bit port odd 0 1 1 1 0 OPO OPO 3 Byte to 16 bit port even 0 1 0 0 1 OPO OPO 4 Byte to 16 bit port odd 0 1 1 0 1 OPO OPO 5 Word to 8 bit port 1 0 0 1 0 OPO OP1 2 aligned 6 port 1 0 1 1 0 1 misaligned 7 SIE s pa 1 0 0 0 1 aligned 8 prone 9 16 Dit port 1 0 1 0 1 OPO OPO 3 misaligned 9 Long word 0 0 1 0 1 13 aligned jg DOR ll 0 1 misaligned 11 Long word to 16 bit port 0 0 0 0 1 7 aligned L 16 bi 12 Epa a 0 1 0 1 3 misaligned 13 Three byte to 8 bit port 1 1 1 1 0 OPO OPO 5 NOTES 1 Operands in parentheses are ignored by the CPU16 during read cycles 2 The CPU16 treats misaligned long word transfers as two misaligned word transfers 3 Three byte transfer cases occur only as a result of an aligned long word to 8 bit port transfer 5 6 Bus Operation Internal microcontroller modules are typically accessed in two system clock cycles Regular external bus cycles use handshaking between the MCU and external peripherals to manage transfer size and data These accesses take three system clock cycles with no w
5. 5 6 2 2 i i 5 6 3 Fast Termination Cycles 5 6 4 CPU Space Cycles uu eo te o tele 5 6 4 1 Breakpoint Acknowledge Cycle 5 6 4 2 LPSTOP Broadcast Cycle 5 6 5 Bus Exception Control Cycles 5 6 5 1 BIS EITDES 2 tuman tal ate et uif 5 6 5 2 Double Bus ten ie noeh hine 5 6 5 3 Halt Operation on exec 5 6 6 External Bus Arbitration 5 6 6 1 Show Cycles 5 7 PROC e M A MM AMA 5 7 1 Reset Exception Processing 5 7 2 sie i eret 5 7 3 Operating Configuration Out of Reset 5 7 3 1 Address and Data Bus Pin Functions 5 7 3 2 Data Bus Mode Selection 5 7 3 3 16 Bit Expanded Mode 5 7 3 4 8 Bit Expanded Mode 5 7 3 5 Single Chip Mode 5 7 3 6 Clock Mode Selection 5 7 3 7 Breakpoint M
6. D 9 3 BEFLASH Base Address Registers D 9 4 BEFLASH Control Register D 9 5 BEFLASH Bootstrap Words MOTOROLA xiv For More Information On This Product Go to www freescale com MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc SECTION 1 INTRODUCTION The MC68HC16R1 and the MC68HC916R1 microcontrollers are high speed 16 bit control units that are upwardly code compatible with M68HC11 controllers Both are members of the M68HC16 Family of modular microcontrollers M68HC16 microcontroller units MCUs are built up from standard modules that interface via a common internal bus Standardization facilitates rapid development of devices tailored for specific applications MC68HC16R1 and the MC68HC916R1 MCUs incorporate a number of different modules Refer to Table 1 1 for information on the contents of a particular MCU x indicates that the module is used in the MCU All of these modules are interconnected by the intermodule bus IMB Table 1 1 MC68HC16R1 916R1 Modules Modules MC68HC16R1 MC68HC916R1 Central Processor Unit CPU16 X X Single Chip Integration Module 2 SCIM2 X X 2 Kbyte Standby RAM SRAM X X 48 Kbyte Masked ROM Module MRM X Analog to Digital Converter ADC X X Multichannel Communication Interface MCCI X X Configurable
7. 9 1 9 3 BEEEASPPAI at tosta ed Aci 9 2 9 4 BEPFEASH Operation ire ab 9 2 9 4 1 i o tubo du ddr 9 2 9 4 2 Bootstrap Operation 2255 erret ep Lege unen 9 3 9 4 3 Normal Operation te 9 3 9 4 4 Program Erase Operation 9 3 9 4 4 1 Programming Sequence 11044 4 04 2 9 5 9 4 4 2 Erasure SoquerGe csv tora in tec aee A 9 6 SECTION 10 ANALOG TO DIGITAL CONVERTER 10 1 10 1 10 2 External Connections 24 o toast a 10 1 10 2 1 Analog Input PINS 10 2 10 2 2 Analog Reference Pins Dee ote doe 10 3 MOTOROLA MC68HC16R1 916R1 viii USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 10 2 3 Analog Supply PINS 10 3 10 3 Programmier s Model oet e ppp tn 10 3 10 4 ADC Bus Interface Unit oai eai ee d e ge ies 10 3 10 5 Special Operating Modes 0 00 1 10 3 10 5 1 Low Power Stop 10 4 10 5 2 Freeze A OGG 10 4 10 6 Analog
8. CSPARO Field Chip Select Signal Alternate Signal Discrete Output CS5PA 1 0 CS5 FC2 PC2 CS4PA1 0 CS4 FC1 PC1 CS3PA 1 0 CS3 FC0 PC0 CS2PA 1 0 CS2 BGACK CS1PA 1 0 CS1 BG CSOPA 1 0 CSO BR CSBTPA 1 0 CSBOOT CSPAR1 Chip Select Pin Assignment Register 1 YFFA46 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 CS10PA 1 0 CS9PA 1 0 CS8P A 1 0 57 1 0 CS 6 1 0 RESET DATA DATA DATA DATA 1 0 0 0 0 0 0 DATA 1 76 1 5 1 74 1 3 NOTES 1 Refer to Table 0 11 for CSPAR1 reset state information CSPAR 1 contains five 2 bit fields that determine the functions of corresponding chip select pins Bits 15 10 are not used These bits always read zero writes have no effect Table 0 10 shows CSPAR 1 pin assignments including alternate functions that can be enabled by data bus mode selection during reset Table D 10 CSPAR1 Pin Assignments CSPAR1 Field Chip Select Signal Alternate Signal Discrete Output CS10PA 1 0 CS10 ADDR23 ECLK CS9PA 1 0 CS9 ADDR22 PC6 CS8PA 1 0 CS8 ADDR21 PC5 CS7PA 1 0 CS7 ADDR20 PC4 CS6PA 1 0 CS6 ADDR19 PC3 NOTES 1 On the CPU16 ADDR 23 20 follow the logic state of ADDR19 unless externally driven The reset state of DATA 7 3 determines whether pins controlled by CSPAR1 are tially configured as high order address lines or chip selects Table D 11 shows the correspondence between DATA 7 3 an
9. 12 9 12 7 5 MCSM Time Base Bus Driver 12 9 12 7 6 MCSM Interr pts u nas al hg m er po eodd 12 10 12 7 7 MGSM Registers 2 andi 12 10 12 8 X Single Action Submodule SASM 12 10 12 8 1 sns Inettpls u ena ORI E 12 11 12 8 2 SASM Registers 5200 Leere bei tien ese n 12 12 12 9 Double Action Submodule 0 12 12 12 9 1 PASM IDterfpls iren Er a ER Eres 12 14 12 9 2 DASM Registers eee 12 14 12 10 Pulse Width Modulation Submodule PWMSM 12 14 12 10 1 Output Flip Flop and Pin te comete oer 12 15 12 10 2 odo eios ECC 12 15 12 10 3 FUWMSN GCOUEGE ud iu 12 16 12 10 4 PWMSM Period Registers and Comparator 12 16 12 10 5 PWMSM Pulse Width Registers and Comparator 12 17 12 10 6 PWMSM Coherencoy a 12 17 12 10 7 PWMSM Interrupts 44 4 48 12 17 12 10 8 PWM EFOOUOPOW ua etaed te erben aqhana eh Sem aa 12 18 12 10 9 PWM Pulse Width t Do ere di pas RR Doreen pede 12 19 MC68HC16R1 916R1
10. S8CM CD CC CB Input Result Register 0 0 0 0 0 ANO RSLT 0 3 0 0 1 AN1 RSLT 0 3 0 0 0 1 0 AN2 RSLT 0 3 0 0 1 AN3 RSLT 0 3 0 0 1 0 0 AN4 RSLT 0 3 0 0 1 AN5 RSLT 0 3 0 0 1 1 0 AN6 RSLT 0 3 0 0 1 AN7 RSLT 0 3 0 1 0 0 0 Reserved RSLT 0 3 0 1 1 Reserved RSLT 0 3 0 1 0 1 0 Reserved RSLT 0 3 0 1 1 Reserved RSLT 0 3 0 1 1 0 0 RSLT 0 3 0 1 1 0 1 VRL RSLT 0 3 0 1 1 1 0 Vn 2 RSLT 0 3 0 1 1 1 1 Test Reserved RSLT 0 3 1 0 0 0 0 ANO RSLT 0 7 1 0 0 0 1 AN1 RSLT 0 7 1 0 0 1 0 AN2 RSLT 0 7 1 0 0 1 1 AN3 RSLT 0 7 1 0 1 0 0 AN4 RSLT 0 7 1 0 1 0 1 AN5 RSLT 0 7 1 0 1 1 0 AN6 RSLT 0 7 1 0 1 1 1 AN7 RSLT 0 7 1 1 0 0 0 Reserved RSLT 0 7 1 1 0 0 1 Reserved RSLT 0 7 1 1 0 1 0 Reserved RSLT 0 7 1 1 0 1 1 Reserved RSLT 0 7 1 1 1 0 0 RSLT 0 7 1 1 1 0 1 VRL RSLT 0 7 1 1 1 1 0 VRH Vn 2 RSLT 0 7 1 1 1 1 1 Test Reserved RSLT 0 7 MOTOROLA 10 10 NOTES 1 Result register RSLT is either RJURRX LJSRRX or LJURRX depending on the address read For More Information On This Product ANALOG TO DIGITAL CONVERTER Go to www freescale com MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc Table 10 8 Multiple Channel Conversions MULT 1 S8CM CD CB Input Result Register 0 0 0 X X ANO RSLTO AN1 RSLT1 AN2 RSLT2 RSLT3 0 0 1 X X AN4 RSLTO AN5 RSLT1 AN6 RSLT2 AN7 R
11. SWP SWT 1 0 Divide Ratio 0 00 29 0 01 211 0 10 213 0 11 215 1 00 218 1 01 220 1 10 222 1 11 224 Figure 5 8 is a block diagram of the watchdog timer and the clock control for the periodic interrupt timer EXTAL XTAL FREEZE MODCLK CRYSTAL 29 PRESCALER SWP OSCILLATOR CLOCK SELECT AND DISABLE PTP SOFTWARE SOFTWARE WATCHDOG TIMER PERIODIC INTERRUPT TIMER WATCHDOG 215 DIVIDER CHAIN 4 TAPS 8 BIT MODULUS COUNTER PIT LPSTOP SWE SWT1 SWTO NOTES 1 1281S PRESENT ONLY ON DEVICES WITH A FAST REFERENCE OSCILLATOR PIT WATCHDOG BLOCK 16 Figure 5 8 Periodic Interrupt Timer and Software Watchdog Timer MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL 5 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 4 6 Periodic Interrupt Timer The periodic interrupt timer PIT allows the generation of interrupts of specific priority at predetermined intervals This capability is often used to schedule control system tasks that must be performed within time constraints The timer consists of a prescaler a modulus counter and registers that determine interrupt timing priority and vector assignment Refer to 4 13 Exceptions for further information about interrupt exception processing The periodic interrupt timer modulus counter is clocked by one of two signals When the PLL is enabled
12. Number of WAIT 1 0 Wait States Clocks per Transfer 00 0 3 01 1 4 10 2 5 11 1 2 Refer to 5 6 Bus Operation for more information concerning access times 7 5 Low Power Stop Mode Operation Low power stop mode minimizes MCU power consumption Setting the STOP bit in MRMCR places the MRM in low power stop mode In low power stop mode the array cannot be accessed The reset state of STOP is the complement of the logic state of DATA14 during reset Low power stop mode is exited by clearing STOP 7 6 ROM Signature Signature registers RSIGHI and RSIGLO contain a user specified mask programmed signature pattern A special signature algorithm allows the user to verify ROM array content 7 7 Reset The state of the MRM following reset is determined by the default values programmed into the MRMCR BOOT LOCK ASPC 1 0 and WAIT 1 0 bits The default array base address is determined by the values programmed into ROMBAL and ROMBAH When the mask programmed value of the MRMCR BOOT bit is zero the contents of MRM bootstrap words ROMBS 0 3 are used as reset vectors When the mask pro grammed value of the MRMCR BOOT bit is one reset vectors are fetched from exter nal memory and system integration module chip select logic is used to assert the boot ROM select signal CSBOOT Refer to 5 9 4 Chip Select Reset Operation for more information concerning external boot ROM selection MC68HC16R1 916R1 MASKED ROM MOD
13. nennen nnne 4 40 4 14 1 Deterministic Opcode Tracking 4 40 4 14 1 1 IPIPEO IPIPE1 Multiplexing gt 4 41 4 14 1 2 Combining Opcode Tracking with Other Capabilities 4 41 4 14 2 au uu u has u 4 41 MOTOROLA MC68HC16R1 916R1 iv USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 4 14 3 Opcode Tracking and Breakpoints 4 42 4 14 4 Background Debug 4 42 4 14 4 1 Enabling BDM s t 4 42 4 14 4 2 BDM Sources MONS 4 42 4 14 4 3 Entering BDM aos a re eee ets 4 43 4 14 4 4 BD MG ONAN GS uice sneen Ente liuysi 4 43 4 14 4 5 Returning from 4 44 4 14 4 6 BDM Serial Interface 4 44 4 15 Recommended BDM Connection 4 45 416 Digital Signal Processing societe oca tete nt ug epp ede AR 4 46 SECTION 5 SINGLE CHIP INTEGRATION MODULE 2 5 1 CIEI MS 5 1 5 2 System Configuration 5 2 5
14. S ADDR CPU ADDR _ MB ADDR2 CPU ADDR3 lt lt 2 ADDR3 CPU ADDR A LMB ADDR4 CPUADDR5 IMB ADDR5 CPUADDR6 AA MB ADDR6 CPU ADDR 7 7 CPU ADDR8 lt 5 ADDR8 CPUADDRG A MB ADDR9 CPU ADDR1O IMB ADDR10 CPU ADDR11 9 MB ADDR11 CPU ADDR12 B ADDR12 CPU ADDR13 IMB ADDR13 CPU ADDR14 AA gt MB ADDR CPU ADDR15 M IMB ADDR15 CPU ADDR16 AA MB ADDR16 CPU ADDR17 MB ADDR17 CPU ADDR18 MB ADDR18 9 9 ADDR1 B ADDR20 B ADDR21 B ADDR22 B ADDR23 gt Figure 3 5 Address Bus Connections Between the CPU16 and IMB CPU16 ADDRESS CONNECTIONS MOTOROLA OVERVIEW MC68HC16R1 916R1 3 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Each address space boundary condition is outlined by the statements that follow Con sider Figure 3 5 and the relationship between CPU address line 19 and IMB address lines 23 20 when exami
15. Cycles S MV H EV 2 V C TMET Transfer Truncated If SM EV MV INH 27B5 2 SS Ae A AM to E then Saturation Value E else AM 31 16 gt E TMXED Transfer AM to 35 32 IX 3 0 INH 27B3 6 IX E D AM35 gt IX 15 4 AM 31 16 E AM 15 0 2 D TPA Transfer CCR to A CCR 15 8 gt A INH 37FC 2 TPD Transfer CCR to D CCR gt D INH 372C 2 TSKB Transfer SK to B SK B 3 0 INH 37AF 2 0 B 7 4 TST Test Byte M 00 IND8 X 06 ff 6 0 0 Zero or Minus IND8 Y 16 ff 6 IND8 Z 26 ff 6 IND16 X 1706 9999 6 IND16 Y 1716 999g 6 IND16 Z 1726 999g 6 EXT 1736 hh Il 6 TSTA Test A for A 00 INH 3706 2 A 0 0 Zero or Minus TSTB Test B for B 00 INH 3716 2 0 0 Zero or Minus TSTD Test D for D 0000 INH 27F6 2 A 0 0 Zero or Minus TSTE Test E for E 0000 INH 2776 2 0 0 Zero or Minus TSTW Test for M M 1 0000 IND16 X 2706 999g 6 0 0 Zero or Minus Word IND16 Y 2716 9999 6 IND16 Z 2726 9999 6 EXT 2736 hh Il 6 TSX Transfer SP to X SK SP 0002 XK IX INH 274F 2 TSY Transfer SP to Y SK SP 0002 2 YK IY INH 275F 2 TSZ Transfer SP to Z SK SP 0002 gt ZK IZ INH 276F 2 TXKB Transfer XK to B 3 0 INH 37AC 2 0 B 7 4 TXS Transfer X to SP XK IX 0002 2 SK SP INH 374E 2 Transfer X to IY
16. that can be obtained is given by the follow ing equation i _ Naiock Negniop 1 PAN eg sys 12 10 10 PWM Period and Pulse Width Register Values The value loaded into PWMA1 to obtain a given period is f PWMA1 xS Noiock PwM The value loaded into PWMB 1 to obtain a given duty cycle is PWMB1 ____ Dully wea tpwmin PwM 100 12 10 10 1 PWM Duty Cycle Boundary Cases PWM duty cycles 0 and 100 are special boundary cases zero pulse width and in finite pulse width that are defined by the always clear and always set states of the output flip flop A zero width pulse is generated by setting PWMB2 to 0000 The output is a true steady state signal An infinite width pulse is generated by setting PWMB2 equal to or greater than the period value in PWMA2 In both cases the state of the output pin will remain unchanged at the polarity defined by the POL bit in PWMSIC MC68HC16R1 916R1 CONFIGURABLE TIMER MODULE 7 MOTOROLA USER S MANUAL For More Information On This Product 12 19 Go to www freescale com Freescale Semiconductor Inc NOTE A duty cycle of 100 is not possible when the output period is set to 65536 PWM clock periods which occurs when PWMB2 is set to 0000 In this case the maximum duty cycle is 99 998 100 x 65535 65536 Even when the duty cycle is 0 or 100 the PWMSM counter con tinues to count 12 10 11 PWMSM Registers The PWMSM cont
17. 050 5 MOTOROLA 3 4 FREEZE Figure 3 1 MC68HC16R1 Block Diagram OVERVIEW For More Information On This Product Go to www freescale com MC68HC16R1 BLOCK MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc Pg EE EEEEBERERRRE CHIP 0 5 C53 C50 ADDR23 CS10 ECLK SELECTS CSM CSE ADDR22 CS9 PC6 ADDR21 CS8 5 ADDR20 CS7 4 ADDR19 CS6 16K 32K FC2 CS5 2 FLASH FLASH FCIPCI U 53 0 SCIM2 50 BG CSM R C a BGACK ICSE PA 7 0VADDR 18 11 ADDR 18 3 d PB 7 0JADDR 10 3 ADDR 2 0 EBI 5121 SIZ1 PE7 5120 SIZO PE6 5 5 05 DS PE4 PE3 ANTIPADAT AN6PADA6 AN5PADA5 1FCSM AN4PADA4 MESH AN3 PADA3 6 SASMs AN2 PADA2 gt 2 DASMs ANIPADAI 2 PWMSMs 5 xn a ANO PADAO Ad AVEC JE AVEC PE2 DSACKI DSACKI PE1 DSACKO DACKO PEO gt RESET 2K X HALT SRAM BEFLASH BERR Ad G 7 0 DATA 15 8 DATAQSO popes TXDA PMC7 K 7 0 7 0 gt RXDA PMC6 O TXDB PMC5 ROTI E gs IRQ6 PF6 RXDB PMC4 IRQ5 PF5 PNG FASTREF j IRQS Olu IRQ4 PF4
18. Minimum Bits of Resolution Divide Pulse Ratio Width 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 3 0 179 us 85 33 170 7 341 3 682 7 1365 2731 5461 10923 21845 43 69k 87 38k 174 8k 349 5k 699 1k 1398k 2796k 6 0 358 us 42 67 85 83 170 7 341 3 682 7 1365 2731 5461 10923 21845 43 69k 87 38k 174 8k 349 5k 699 1k 1398k 12 0 715 us 21 33 42 67 85 33 170 7 341 3 682 7 1365 2731 5461 10923 21845 43 69k 87 38k 174 8k 349 5k 699 1k 24 1 431 us 10 67 21 33 42 67 85 33 170 7 341 3 682 7 1365 2731 5461 10923 21845 43 69k 87 38k 174 8k 349 5k 48 2 861 us 5 333 10 67 21 33 42 67 85 33 170 7 341 3 682 7 1365 2781 5461 10923 21845 43 69k 87 38k 174 8k 96 5 722 us 2 667 5 333 10 67 21 33 42 67 85 33 170 7 341 3 682 7 1365 2731 5461 10923 21845 43 69k 87 38k 192 11 44 us 1 333 2 667 5 333 10 67 21 33 42 67 85 33 170 7 341 3 682 7 1365 2731 5461 10923 21845 43 69k 768 45 78 us 0 333 0 667 1 333 2 667 5 333 10 67 21 33 42 67 85 33 170 7 341 3 682 7 1365 2731 5461 10923 12 10 9 PWM Pulse Width The shortest output pulse width tpowwiN that can be obtained is given by the following equation t _ Natock PWMIN 7 f Sys The maximum output pulse width
19. ETS SUBMODULE FCSM3 lt 513 SINGLE ACTION ga o SUBMODULE SASM8B CTD8B SINGLE ACTION gt SUBMODULE SASM8A CTD8A SINGLE ACTION SUBMODULE SASM6B 068 SINGLE ACTION gt SUBMODULE SASM6A CTD6A DOUBLE ACTION suBMODULE DASMS CTD5 GLOBAL TIME BASE BUS A DOUBLE ACTION GLOBAL TIME BASE BUS B TIME BASE BUS 2 TBB2 SUBMODULE DASM4 CTM7 BLOCK Figure 12 1 CTM7 Block Diagram MC68HC16R1 916R1 CONFIGURABLE TIMER MODULE 7 MOTOROLA USER S MANUAL For More Information On This Product 12 1 Go to www freescale com Freescale Semiconductor Inc The time base buses originate in a counter submodule and are used by the action submodules Two time base buses are accessible to each submodule The bus interface unit submodule BIUSM allows all the CTM7 submodules to pass data to and from the IMB via the submodule bus SMB The counter prescaler submodule CPSM generates six different clock frequencies which can be used by any counter submodule This submodule is contained within the BIUSM The free running counter submodule FCSM has a 16 bit up counter with an associated clock source selector selectable time base bus drivers writable control registers readable status bits and interrupt logic The CTM7 has one FCSM The modulus counter submodule MCSM is an enhanced FCSM A modulus register gives the additional flexibility of recycling the counter at a count other tha
20. FASTREF PFO 83 SCIM2 B 0 5 117 SCIM2 A FC1 PC1 118 SCIM2 A FC2 CS5 PC2 119 SCIM2 A FREEZE QUOT 74 CPU16 A HALT 72 SCIM2 Bo Y N MC68HC16R1 916R1 OVERVIEW MOTOROLA USER S MANUAL For More Information On This Product 3 9 Go to www freescale com Freescale Semiconductor Inc Table 3 1 MC68HC16R1 MC68HC916R1 Pin Characteristics Pin Pin Associated Driver Synchronized Input Mnemonic s Number s Module Type Input Hysteresis IPIPEO DSO 67 CPU16 A IPIPE1 DSI 68 CPU16 A Y Y IRQ1 PF1 82 IRQ2 PF2 81 IRQ3 PF3 80 IRQ4 PF4 79 SCIM2 B Y Y IRQ5 PF5 78 IRQ6 PF6 77 IRQ7 PF7 76 MISO PMCO 50 MCCI Bo Y MOSI PMC1 49 89 SCIM2 B Y Y R W 84 SCIM2 A RESET 71 SCIM2 Bo Y Y RXDA PMC6 53 j RXDB PMC4 55 MERI Bo X SCK PMC2 51 Y SIZO PE6 86 SIZ1 PE7 85 SiMe A SS PMC3 48 MCCI Bo TSC 75 SCIM2 Y Y TXDA PMC7 52 1 5 54 MEBI Bo id 14 27 61 VoD 63 m E m m 116 131 VDDA 26 ADC Vopsyn MODCLK 58 SCIM2 1 132 BEFLASH es FLASH1 VFPE2 d FLASH2 es a VRH 18 VRL 17 ADG E I 13 28 34 64 Vss 66 v 100 115 130 Vssa 25 ADC 60 SCIM2 MOTOROLA OVERVIEW MC68HC16R1 916R1 3 10 For More Information On This Product USER S MANUAL Go to www freescale com T
21. CTS16A CTS16B CPWMIS CPWMI9 ADDR23 CS10 ECLK FCO CS3 PCO O MC68HC16R1 ATWLYYWW uus page a gee i ilr 588 U zi j 7 1 OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATION YEAR WEEK VDD VSS BGACK CSE BG CSM BR CSO CSBOOT DATAO PH DATA1 PH DATA2 PH DATA3 PH DATA4 PH DATAS PH DATA6 PH DATA7 PH DATAB8 PGO DATA9 PG1 VSS DATA10 PG2 DATA11 P G3 DATA12 P G4 DATA13 P G5 DATA14 P G6 DATA15 PG7 ADDRO DSACKO PEO DSACK1 PE1 AVEC PE2 PE3 DS PE4 5 SIZO PE6 SIZ1PE7 RAV n gt CU MC68HC16R1 132 PIN QFP Figure B 1 MC68HC16R1 Pin Assignment for 132 Pin Package MOTOROLA B 2 MECHANICAL DATA AND ORDERING INFORMATION MC68HC16R1 916R1 For More Information On This Product Go to www freescale com USER S MANUAL Freescale Semiconductor Inc ADDR22 CS9 PC6 ADDR21 CS8 PC5 ADDR2Q CS7 PCA ADDR2J CS10 ECLK ADDR19 CS6 PC3 CTS16A CTS16B CPWMIS CPWMI9 FC2 CS5 PC2 FCQ CS3 PCO VRH VDD AN5 PADA5 VSS AN4 PADA4 BGACK CSE AN3 PADA3 BG CSM AN2 PADA2 BR CSO AN1 PADA1 CSBOOT ANO PADAO DATAO PHO VSSA DATAL PH1 VDDA DATA2 PH2 VDD DATA3 PH3 VSS DATAA PH4 ADDR1 DATA5 PH5 ADDR2 DATAG PH6 ADDR3 PBO DATAT PH7 ADDRA PB1 DATAB PGO ADDR5 PB2 MC68HC916R1 DATA9 PG1 VSS VSS ADDR6 PB3 A
22. 0 0 0 0 0 0 0 0 0 0 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMBAH and RAMBAL specify the SRAM array base address in the system memory map They can only be written while the SRAM is in low power stop mode STOP 1 the default out of reset and the base address lock is disabled RLCK 0 the default out of reset This prevents accidental remapping of the array Because the CPU16 drives ADDR 23 20 to the same logic level as ADDR19 the values of the RAMBAH ADDR 23 20 fields must match the value of the ADDR19 field for the array to be accessible These registers may be read at any time RAMBAH 15 8 are unimplemented and will always read zero MC68HC16R1 916R1 USER S MANUAL REGISTER SUMMARY MOTOROLA For More Information On This Product D 27 Go to www freescale com Freescale Semiconductor Inc D 4 Masked ROM Module The MRM is used only the MC68HC16R1 Table D 20 shows the MRM address map The reset states shown for the MRM registers are for the generic blank ROM versions of the device Several MRM register bit fields can be user specified on a custom masked ROM device Contact a Motorola sales representative for information on ordering a custom ROM device Table D 20 MRM Address Map Address 15 0 YFF820 Masked ROM Module Configuration Register MRMCR YFF822 Not Implemented YFF82
23. COMBINED V pp AND V rpg 6 5V 45 40V OV 0 30 V NORMAL PROGRAM ON READ ERASE DOWN VERIFY PROG VOLT ENVELOPE Figure A 22 Programming Voltage Envelope PROGRAMMING VOLTAGE POWER SUPPLY D1 45V Vepe CIRCUIT Figure A 23 Vrpg Conditioning Circuit MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product A 31 Go to www freescale com Freescale Semiconductor Inc MOTOROLA MC68HC16R1 916R1 A 32 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION MC68HC16R1 916R1 microcontrollers are available in a 132 pin plastic surface mount package This appendix provides package pin assignment drawings a dimensional drawing and ordering information MC68HC16R1 916R1 MECHANICAL DATA AND ORDERING INFORMATION MOTOROLA USER S MANUAL For More Information On This Product 1 Go to www freescale com VRH AN5 PADA5 AN4 P ADA4 AN3 PADA3 AN2 P ADA2 AN1 PADA1 ANO P ADAO VSSA VDDA VDD VSS ADDR1 ADDR2 ADDR3 PBO ADDR4 PB1 ADDR5 PB2 VSS ADDR6 PB3 ADDR7 PB4 ADDR8 PB5 ADDR9 PB6 ADDR10 PB7 ADDR11 PA0 ADDR12 PA1 ADDR13 PA2 ADDR14 PA3 ADDR15 PA4 ADDR16 PA5 ADDR17 PA6 ADDR18 PA7 SS PMC3 MOSI PMC1 MISO PMCO NOTES Freescale Semiconductor Inc ADDR22 CS9 PC6 ADDR21 CS8 PC5 ADDR20 CS7 PC4 ADDR19 CS6 PC3 FC2 CS5 PC2
24. INH 3729 38 A AAA Integer Divide Quotient Remainder D EMUL Extended Unsigned 0 2 E D INH 3725 10 A A Multiply EMULS Extended Signed E 0 E D INH 3726 8 A A Multiply EORA Exclusive OR A M gt A IND8 X 44 ff 6 A 0 IND8 Y 54 ff 6 IND8 Z 64 ff 6 IMM8 74 ii 2 IND16 X 1744 999g 6 IND16 Y 1754 999g 6 IND16 Z 1764 9999 6 1774 hh Il 6 E X 2744 6 E Y 2754 6 E Z 2764 6 EORB Exclusive OR B B IND8 C4 ff 6 A 0 IND8 Y D4 ff 6 IND8 Z 4 ff 6 IMM8 F4 ii 2 IND16 X 17C4 9999 6 IND16 Y 17D4 999g 6 IND16 Z 17E4 999g 6 EXT 17F4 hh Il 6 E X 27C4 6 E Y 27D4 6 E Z 27E4 6 EORD Exclusive OR D D 1 D IND8 84 ff 6 A 0 IND8 Y 94 ff 6 IND8 Z A4 ff 6 IMM16 37B4 jj kk 4 IND16 X 3704 9999 6 IND16 Y 37D4 9999 6 IND16 2 37E4 9999 6 37F4 hh Il 6 2784 6 E Y 2794 6 E Z 27 4 6 EORE Exclusive OR E E 1 IMM16 3734 jj kk 4 A 0 IND16 X 3744 gggg 6 IND16 Y 3754 9999 6 IND16 2 3764 9999 6 3774 hh Il 6 FDIV Fractional D IX IX INH 372B 22 A AA Unsigned Divide Remainder gt D FMULS Fractional Signed E D E D 31 1 INH 3727 8 A AAA Multiply 0 D 0 IDIV Integer Divide D IX IX INH 372
25. Program and data accesses X1 Program access only WAIT 1 0 Wait States Field WAIT 1 0 specifies the number of wait states inserted by the MRM during ROM array accesses The reset state of WAIT 1 0 is user specified The field can be written only if LOCK 0 and STOP 1 Table D 22 shows the wait states field Table D 22 Wait States Field WAIT 1 0 Clocks per Transfer 00 0 3 01 1 4 10 2 11 4 2 MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 29 Go to www freescale com Freescale Semiconductor Inc D 4 2 ROM Array Base Address Registers ROMBAH ROM Array Base Address Register High YFF824 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lel elo EBENEN RESET 1 1 1 1 1 1 1 1 NOTES 1 Reset value of the shaded bits is user specified but the bits can be written after reset to change the base address If the values of ROMBAH bits ADDR 23 20 do not match that of ADDR19 however the CPU16 cannot access the ROM array ROMBAL ROM Array Base Address Register Low YFF826 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR ADDR ADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET 0 0 0 ROMBAH and ROMBAL specify ROM array base address The reset state of these registers is specified at mask time They can only be
26. 0 LOW POWER 0 0011 1111111111111110 STOP BROADCAST 2 0 23 i NOWLEDGE Sc ear a RE uswa 8 CPU SPACE TYPE FIELD CPU SPACE CYC TIM Figure 5 13 CPU Space Address Encoding 5 6 4 1 Breakpoint Acknowledge Cycle Breakpoints stop program execution at a predefined point during system development In the MC68HC16R1 916R1 breakpoints are treated as a type of exception process ing Breakpoints can be used alone or in conjunction with background debug mode The MC68HC16R1 916R1 has only one source and type of breakpoint This is a hardware breakpoint initiated by assertion of the BKPT input Other modular microcontrollers may have more than one source or type breakpoint acknowledge cycle discussed here is the bus cycle that occurs as a part of breakpoint exception processing when a breakpoint is initiated while background debug mode is not enabled BKPT is sampled on the same clock phase as data BKPT is valid the data is tagged as it enters the CPU16 pipeline When BKPT is asserted while data is valid during an instruction prefetch the acknowledge cycle occurs immediately after that instruction has executed When BKPT is asserted while data is valid during an operand fetch the acknowledge cycle occurs immediately after execution of the instruction during which it is latched BKPT is asserted for only one bus cycle and a pipe flush occurs before BKPT is detected by the CPU16 no ack
27. MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The following equation calculates the PIT period for an externally input clock frequency on both slow and fast reference frequency devices PIT Period ref 5 4 7 Interrupt Priority and Vectoring Interrupt priority and vectoring are determined by the values of the periodic interrupt request level PIRQL 2 0 and periodic interrupt vector PIV fields in the periodic interrupt control register PICR The PIRQL field is compared to the CPU16 interrupt priority mask to determine whether the interrupt is recognized Table 5 8 shows PIRQL 2 0 priority values Be cause of SCIM2 hardware prioritization a PIT interrupt is serviced before an external interrupt request of the same priority The periodic timer continues to run when the in terrupt is disabled Table 5 8 Periodic Interrupt Priority PIRQL 2 0 Priority Level 000 Periodic Interrupt Disabled 001 Interrupt priority level 1 010 Interrupt priority level 2 011 Interrupt priority level 3 100 Interrupt priority level 4 101 Interrupt priority level 5 110 Interrupt priority level 6 111 Interrupt priority level 7 The PIV field contains the periodic interrupt vector The vector is placed on the IMB when an interrupt request is made The vector number is used to calculate t
28. tcHAV Chip select access time 2 WS tci sA tpicL Where WS number of wait states When fast termination is used 2 clock bus WS 1 5 Specification 9A is the worst case skew between AS and DS or CS The amount of skew depends on the relative loading of these signals When loads are kept within specified limits skew will not cause AS and DS to fall outside the limits shown in specification 9 6 If multiple chip selects are used CS width negated specification 15 applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles 7 Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads The user is free to use either hold time 8 Maximum value is equal to 2 25 ns 9 If the asynchronous setup time specification 47A requirements are satisfied the DSACK 1 0 low to data setup time specification 31 and DSACK 1 0 low to BERR low setup time specification 48 can be ignored The data must only satisfy the data in to clock low setup time specification 27 for the following clock cycle BERR must satisfy only the late BERR low to clock low setup time specification 27A for the following clock cycle 10 To ensure coherency during every opera
29. 5010000 0008 4 BKPT BREAKPOINT 000 5 BERR BUS ERROR 020000 L oe 5 USES BANKAS or S 020000 0010 8 DIVISION BY ZERO 0012 001C 9 E UNASSIGNED RESERVED __ _ _ _ 030000 F guk3 7777 7070777774 OOLE F UNINITIALIZED INTERRUPT BANK 3 030000 0020 10 UNASSIGNED RESERVED 512 KBYTE 0022 II LEVEL LINTERRUPT AUTOVECTOR Digs Al ss ele sd aod 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR ideis oua Ene a 5040000 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR BANK 4 5040000 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002 15 LEVEL 5 INTERRUPT AUTOVECTOR 5 002C 16 LEVEL 6 INTERRUPT AUTOVECTOR 1 5050000 wes 002E 17 LEVEL 7 INTERRUPT AUTOVECTOR BANKS 5050000 0030 18 SPURIOUS INTERRUPT 0032 006E 19 37 UNASSIGNED RESERVED 060000 1600 Qa SGS AMAS 0070 01FE 38 FF USER DEFINED INTERRUPTS 060000 PROGRAM DATA SPACE YFF700 SPACE 070000 2 ADC 7777777 070000 I 080000 YFF73F 080000 UNDEFINED UNDEFINED UNDEFINED MELIA SEES UNDEFINED Y FF IBF FIFFFF Y FF 800 16K FLASH SF7FFFF F80000 Banks VEESIF CONTROL BANK 8 F 80000 ay eee oe 32K FLASH M F90000 erras Cono F 90000 FA0000 00100 YFF900 NKU 7 0000 7 0000 baku 1 Y FF OFF FB0000 512 KBYTE Y FFA00 SECUDOD a samana ss see Mice FC0000 YFFA7F FD0000 yu ttt YFFBOO RAM BAKIB 7 FD0000 sveRBo7 C
30. Unsigned left justified format Refer to APPENDIX D REGISTER SUMMARY for register mapping and configuration 10 8 Pin Considerations The ADC requires accurate noise free input signals for proper operation The follow ing sections discuss the design of external circuitry to maximize ADC performance 10 8 1 Analog Reference Pins No A D converter can be more accurate than its analog reference Any noise in the reference can result in at least that much error in a conversion The reference for the supplied by pins Vay and Vg should be low pass filtered from its source to ob tain a noise free clean signal In many cases simple capacitive bypassing may suf fice In extreme cases inductors or ferrite beads may be necessary if noise or RF energy is present Series resistance is not advisable since there is an effective DC cur rent requirement from the reference voltage by the internal resistor string in the RC DAC array External resistance may introduce error in this architecture under certain conditions Any series devices in the filter network should contain a minimum amount of DC resistance For accurate conversion results the analog reference voltages must be within the lim its defined by Vpp4 and as explained in the following subsection 10 8 2 Analog Power Pins The analog supply pins and define the limits of the analog reference volt ages Vay and Vg and of the analog multiplexer i
31. When the MSB is set in the operand of a read operation When the MSB is set in the result of a logic or arithmetic operation Z Zero Flag Z is set under the following conditions When all bits are zero in the operand of a read operation When all bits are zero in the result of a logic or arithmetic operation V Overflow Flag V is set when a two s complement overflow occurs as the result of an operation C Carry Flag C is set when a carry or borrow occurs during an arithmetic operation This flag is also used during shift and rotate to facilitate multiple word operations IP 2 0 Interrupt Priority Field The priority value in this field 0 to 7 is used to mask interrupts MOTOROLA CENTRAL PROCESSOR UNIT MC68HC16R1 916R1 44 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SM Saturate Mode Bit When SM is set and either EV or MV is set data read from AM using TMER or TMET is given maximum positive or negative value depending on the state of the AM sign bit before overflow PK 3 0 Program Counter Address Extension Field This field is concatenated with the program counter to form a 20 bit address 4 2 6 Address Extension Register and Address Extension Fields There are six 4 bit address extension fields EK XK YK and ZK are contained by the address extension register K PK is part of the CCR and SK stands alone Extension fields a
32. 16 RD CYC TIM Figure A 4 Read Cycle Timing Diagram MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product A 11 Go to www freescale com Freescale Semiconductor Inc m wn w a CLKOUT ADDR 23 20 PM H pA xri _ Dim LX 2 e our 3m 15 0 PT SZ ER 9 797 IPIPEO O mel TD Figure A 5 Write Cycle Timing MOTOROLA A 12 For More Information On This Product 16 WR CYC Diagram MC68HC16R1 916R1 USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 41 5 ew namn a a Ci T ss m 120 2 i ies Sats OG Pres DATA 15 0 Re id 0 IPIPE1 EL 16 FAST RD CYC TIM Figure A 6 Fast Termination Read Cycle Timing Diagram MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product A 13 Go to www freescale com Freescale Semiconductor Inc A NL L L D i al ES SIZ 1 0 JE E ET DATA 15 0 p 100 0 erpa D E HH 16 FAST WR CYC TIM Figure A 7 Fast Termination Write Cycle
33. Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles 7 V C Add B to A gt A 370B 2 A AAA Add B to IX XK IX 000 B gt XK IX INH 374F 2 Add B to IY IY 000 B 2 YK IY INH 375F 2 ABZ Add B to IZ ZK IZ 000 B gt ZK IZ INH 376F 2 ACE Add E to AM AM 31 16 E AM INH 3722 2 ACED Add E D to AM AM E D INH 3723 4 ADCA Add with Carry to A A G IND8 X 43 ff 6 A AAA IND8 Y 53 ff 6 IND8 Z 63 ff 6 IMM8 73 ii 2 IND16 X 1743 gggg 6 IND16 Y 1753 gggg 6 IND16 Z 1763 gggg 6 EXT 1773 hh Il 6 2743 6 E Y 2753 6 E Z 2763 6 ADCB Add with Carry to B M C gt B IND8 X C3 ff 6 A A A IND8 Y D3 ff 6 IND8 Z E3 ff 6 IMM8 F3 ii 2 IND16 X 17C3 999g 6 IND16 Y 17D3 999g 6 IND16 2 17 0099 6 17 hh Il 6 2763 6 E Y 27D3 6 E Z 27E3 6 ADCD Add with Carry to D D M M 1 C gt D IND8 X 83 ff 6 AAA IND8 Y 93 ff 6 IND8 Z A3 ff 6 IMM16 37B3 jj kk 4 IND16 X 37C3 gggg 6 IND16 Y 37D3 9999 6 IND16 2 7 9999 6 37F3 hh Il 6 2783 6 EY 2793 6 E Z 27A3 6 ADCE Add w
34. GO x Pp 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Pp at equilibrium for a known Using this value of the values of Pp and Ty can be obtained by solving equations 1 and 2 iteratively for any value of MC68HC16R1 916R1 ELECTRICAL CHARACTERISTICS MOTOROLA USER S MANUAL For More Information On This Product A 3 Go to www freescale com Freescale Semiconductor Inc Table A 4 Clock Control Timing Vpp and VDDSYN 5 0 10 Vss 0 Ta to Ty Num Characteristic Symbol Min Max Unit PLL Reference Frequency Range em 3 2 4 2 MHz System Frequency dc 16 78 Slow On Chip PLL System Frequency 4 fret 16 78 MHz Fast On Chip PLL System Frequency Sys 4 fret 128 16 78 External Clock Operation dc 16 78 PLL Lock Time 8 9 Changing W or Y in SYNCR or exiting from LPSTOP t 20 rs Warm Start up 50 Cold Start up fast reference option only 75 VCO Frequency fvco 2 max MHz Limp Mode Clock Frequency SYNCR X bit 0 f f 2 MHz SYNCR X bit 1 limp T max CLKOUT Jitter 799 10 Short term 5 us interval J 0 5 0 5 Long term 500 us interval clk 0 05 0 05 NOTES 1 Tested with either a 4 194 MHz reference or a 32 768 kHz reference 2 All internal registers retain data at 0 Hz 3 Assumes that Vppsyn and Vpp are stable that a
35. Write PC and SP Write to program counter and stack pointer Read Data Memory Read byte from specified 20 bit address in data space Write Data Memory Read Program Memory Write byte to specified 20 bit address in data space Read word from specified 20 bit address in program space Write Program Memory Write word to specified 20 bit address in program space Execute from Current PK PC Null Operation NOP Instruction pipeline flushed and refilled instructions executed from current PC 0006 Null command performs no operation MC68HC16R1 916R1 USER S MANUAL For More Information On This Product MOTOROLA 4 43 Go to www freescale com Freescale Semiconductor Inc 4 14 4 5 Returning from BDM BDM is terminated when a resume execution GO command is received GO refills the instruction pipeline from address PK PC 0006 FREEZE is negated before the first prefetch Upon negation of FREEZE the BDM serial subsystem is disabled and the DSO DSI signals revert to IPIPEO IPIPE1 functionality 4 14 4 6 BDM Serial Interface The BDM serial interface uses a synchronous protocol similar to that of the Motorola serial peripheral interface SPI Figure 4 7 is a diagram of the serial logic required to use BDM with a development system The development system serves as the master of the serial link and is responsible for the generation of the serial interface clock signal DSCLK
36. 0 branch REL16 3784 rrrr 6 4 Clear LBCS Long Branch if Carry If C 1 branch REL16 3785 rrrr 6 4 Set LBEQ Long Branch if Equal If Z 1 branch REL16 3787 rrrr 6 4 to Zero LBEV2 Long Branch if EV Set If EV 1 branch REL16 3791 rrr 6 4 LBGE _ Long Branch if Greater If N 6 V 0 branch REL16 378C reve 6 4 Than or Equal to Zero LBGT LongBranchif Greater If Z N V 0 branch REL16 378E rrrr 6 4 Than Zero LBHI 2 Long Branch if Higher If C Z 0 branch REL16 3782 rrrr 6 4 LBLE2 Long Branch if Less If Z N V 1 branch REL16 378F rrrr 6 4 Than or Equal to Zero LBLS2 Long Branch if Lower If C Z 1 branch REL16 3783 rrr 6 4 or Same LBLT2 Long Branch if Less If N V 1 branch REL16 378D rrr 6 4 Than Zero LBMI2 Long Branch if Minus If N 1 branch REL16 378B rrrr 6 4 LBMV Long Branch if MV Set If MV 1 branch REL16 3790 rrrr 6 4 LBNE2 Long Branch if Not If Z 0 branch REL16 3786 rrrr 6 4 Equal to Zero LBPL2 Long Branch if Plus If N 0 branch REL16 378A rrrr 6 4 LBRA Long Branch Always If 1 1 branch REL16 3780 rrrr 6 LBRN Long Branch Never If 1 2 0 branch REL16 3781 rrrr 6 LBSR Long Branch to Push PC REL16 27F9 rrrr 10 Subroutine SK SP 2 gt SK SP Push CCR SK SP 2 gt SK SP PK PC Offset PK PC LBVC Long Branch if If V 0 branch REL16 3788 rrr 6 4 Overflow Clear 1 52 Long Branch if If V 1 branch REL16 3789 rrr 6 4 Overflow Set LDAA Load A A IND8 X 45 ff
37. 4 4 MC68HC16R1 916R1 MOTOROLA USER S MANUAL ii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 4 2 6 Address Extension Register and Address Extension Fields 4 5 4 2 7 Multiply and Accumulate Registers 4 5 4 3 Memory Management I hb qi et 4 5 4 3 1 Address Extension 2 orn nore Era 4 6 4 3 2 Extension Fields 4 6 4 4 PVD CS sites E E 4 6 4 5 Memory Organization 0 4 7 4 6 Addressing UU 4 8 4 6 1 Immediate Addressing Modes 4444222 01 4 9 4 6 2 Extended Addressing Modes 2 4441 1 4 10 4 6 3 Indexed Addressing Modes b 4 10 4 6 4 Inherent Addressing Mode aa 4 10 4 6 5 Accumulator Offset Addressing Mode 4 10 4 6 6 Relative Addressing 4 10 4 6 7 Post Modified Index Addressing Mode 4 10 4 6 8 Use of CPU16 Indexed Mode to Re
38. Figure B 3 Case 831A 01 132 Package Dimensions MOTOROLA MECHANICAL DATA AND ORDERING INFORMATION MC68HC16R1 916R1 B 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc B 1 Obtaining Updated MC68HC16R1 916R1 MCU Mechanical Information Although all devices manufactured by Motorola conform to current JEDEC standards complete mechanical information regarding MC68HC16R1 916R1 microcontrollers is available through Motorola s Design Net To download updated package specifications perform the following steps 1 Visit the Design Net case outline database search engine at http design net com cgi bin cases 2 Enter the case outline number located in Figure B 3 without the revision code for example 831A not 831A 01 in the field next to the search button 3 Download the file with the new package diagram B 2 Ordering Information Use the information in Table B 1 to specify the appropriate device when placing an order NOTE Ordering information for MC68HC16R1 and MC68HC916R1 micro controllers is currently not available for this revision Table B 1 M68HC16R1 916R1 Ordering Information Package Device Crystal Package Type Temperature Frequency Order Order Number Input MHz Quantity NOT AVAILABLE AT THIS TIME MC68HC16R1 916R1 MECHANICAL DATA AND ORDERING INFORMATION MOTOROLA USER S MANUAL For More Information On This Product 5
39. Freescale Semiconductor Inc MC68HC16R1 MC68HC916R1 USER S MANUAL PRELIMINARY THIS DOCUMENT IS PRODUCED FOR ON LINE DISTRIBUTION ONLY IT IS NOT AVAILABLE AT THE MOTOROLA LITERATURE DISTRIBUTION CENTER PLEASE DIRECT ANY QUESTIONS CONCERNING THIS DOCUMENTATION TO A REPRESENTATIVE AT YOUR LOCAL MOTOROLA SALES OFFICE OR MOTOROLA DISTRIBUTOR Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended o
40. MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 40 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SIZ 1 0 signals reflect bus allocation during show cycles Only the appropriate portion of the data bus is valid during the cycle During a byte write to an internal address the portion of the bus that represents the byte that is not written reflects internal bus con ditions and is indeterminate During a byte write to an external address the data mul tiplexer in the SCIM2 causes the value of the byte that is written to be driven out on both bytes of the data bus 5 7 Reset Reset occurs when an active low logic level on the RESET pin is clocked into the SCIM2 The RESET input is synchronized to the system clock If there is no clock when RESET is asserted reset does not occur until the clock starts Resets are clocked to allow completion of write cycles in progress at the time RESET is asserted Reset procedures handle system initialization and recovery from catastrophic failure The MCU performs resets with a combination of hardware and software The SCIM2 determines whether a reset is valid asserts control signals performs basic system configuration and boot ROM selection based on hardware mode select inputs then passes control to the CPU16 5 7 1 Reset Exception Processing The CPU16 processes resets as a type of asynchronous exception An except
41. TSTRC Test Module Repetition Count YFFA36 Used for factory test only MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 24 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 2 31 Test Module Control Register CREG Test Module Control Register YFFA38 Used for factory test only D 2 32 Test Module Distributed Register DREG Test Module Distributed Register YFFA3A Used for factory test only MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 25 Go to www freescale com Freescale Semiconductor Inc D 3 Standby RAM Module Table D 18 shows the SRAM address map Table D 18 SRAM Address Map Address 15 0 YFFBOO RAM Module Configuration Register RAMMCR YFFBO2 RAM Test Register RAMTST YFFB04 RAM Array Base Address Register High RAMBAH YFFBOG RAM Array Base Address Register Low RAMBAL NOTES 1 Y M111 where M is the logic state of the module mapping MM bit in the SCIMCR D 3 1 RAM Module Configuration Register RAMMCR RAM Module Configuration Register YFFBOO 15 11 9 8 0 STOP 0 0 0 RLCK 0 RASP 1 0 NOT USED RESET 1 0 0 0 0 0 1 1 STOP Low Power Stop Mode Enable 0 SRAM operates normally 1 SRAM enters low power stop mode This bit controls whether SRAM operates normally or enters low power stop mode In low power stop mo
42. al capabilities associated with 16 and 32 bit data sizes 20 bit addressing and digital signal processing CPU16 registers an integral part of the CPU and not ad dressed as memory locations The CPU16 treats all peripheral and memory locations as parts of a linear 1 Megabyte address space There are no special instructions for I O that are separate from instructions for addressing memory Address space is made up of sixteen 64 Kbyte banks Specialized bank addressing techniques and support registers provide transparent access across bank boundaries The CPU16 interacts with external devices and with other modules within the micro controller via a standardized bus and bus interface There are bus protocols used for memory and peripheral accesses as well as for managing a hierarchy of interrupt priorities 4 2 Register Model Figure 4 1 shows the CPU16 register model Refer to the paragraphs that follow for a detailed description of each register MC68HC16R1 916R1 CENTRAL PROCESSOR UNIT MOTOROLA USER S MANUAL For More Information On This Product 4 1 Go to www freescale com Freescale Semiconductor Inc MOTOROLA 4 2 20 16 15 8 7 0 A B D E XK X YK Y ZK Z SK SP PK PC CCR PK EK XK YK ZK K SK HR IR A A XMSK YMSK BIT POSITION ACCUMULATORS A AND B
43. 00 gt B INH 3715 2 0 1 0 0 CLRD Clear D 0000 gt D INH 27F5 2 0 1 0 0 CLRE Clear E 0000 gt E INH 2775 2 0 1 0 0 CLRM Clear AM 000000000 AM 35 0 INH 27B7 2 0 0 CLRW Clear a Word in 0000 gt M M 1 IND16 X 2705 gggg 6 0 1 0 0 Memory IND16 Y 2715 9999 6 IND16 Z 2725 9999 6 2735 hh Il 6 CMPA A to Memory A IND8 48 ff 6 A AAA IND8 Y 58 ff 6 IND8 Z 68 ff 6 IMM8 78 ii 2 IND16 X 1748 gggg 6 IND16 Y 1758 9999 6 IND16 2 1768 9999 6 1778 hh Il 6 2748 6 E Y 2758 6 E Z 2768 E 6 CMPB Compare B to Memory B M IND8 X C8 ff 6 A IND8 Y D8 ff 6 IND8 Z E8 ff 6 IMM8 F8 ii 2 IND16 X 17C8 9999 6 IND16 Y 17D8 9999 6 IND16 Z 17E8 999g 6 EXT 17F8 hh Il 6 27 8 6 E Y 27D8 6 E Z 27E8 6 COM One s Complement FF M orM M IND8 X 00 ff 8 ce Se An A 2702 4 IND8 Y 10 ff 8 IND8 Z 20 ff 8 IND16 X 1700 999g 8 IND16 Y 1710 999g 8 IND16 Z 1720 999g 8 EXT 1730 hh Il 8 COMA One s Complement A FF or M INH 3700 2 eS A O 1 COMB One s Complement FF B B or B gt INH 3710 2 SSeS GA 1 COMD One s Complement D FFFF D D or D gt D INH 27F0 2 0 1 COME One s Complement E FFFF E or E E INH 2770 2 0 7 COMW One s Complement FFFF M
44. 11 4 3 Receive Data Pins RXDA RXDB 11 17 11 4 4 Transmit Data Pins TXDA TXDB 11 17 11 4 5 SG ODOIatoll s x u teh aan 11 17 11 4 5 1 Definition of TermS deus tue a t e bot io NOR EU ede 11 17 11 4 5 2 Serial 11 18 11 4 5 3 Baud GlOCK Janna IER 11 18 11 4 5 4 Facio dac tct 11 19 11 4 5 5 Transmitter Operation 11 19 11 4 5 6 Receiver Operation 11 20 11 4 5 7 Idle Line Detection 11 21 11 4 5 8 Receiver Wake Up 11 22 11 4 5 9 diel da tei Loop ducto nouit usa a uhupi S 11 22 11 5 MCCI Initialization 11 23 SECTION 12 CONFIGURABLE TIMER MODULE 7 12 1 Cz iz 65 12 1 12 2 Address M p gti tat 12 2 MOTOROLA MC68HC16R1 916R1 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 12 9 Tine Base Bus Syste pusasqa 12 2 12 4 Bus Interface Unit Submodule BIUSM 12 3 12 4 1 STOP Effect On the BIUSM usa ects ti
45. A B ACCUMULATOR E DEX REGISTER X DEX REGISTER Y DEX REGISTER Z STACK POINTER SP PROGRAM COUNTER PC CONDITION CODE REGISTER CCR PC EXTENSION FIELD PK ADDRESS EXTENSION REGISTER K STACK EXTENSION REGISTER SK AC MULTIPLIER REGISTER HR AC MULTIPLICAND REGISTER IR AC ACCUMULATOR MSB 35 16 AM AC ACCUMULATOR LSB 15 0 AM AC XY MASK REGISTER CPU16 REGISTER MODEL Figure D 1 CPU16 Register Model For More Information On This Product REGISTER SUMMARY MC68HC16R1 916R1 USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 1 1 Condition Code Register CCR Condition Code Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 MV H EV N 2 2 0 SM PK 3 0 The CCR contains processor status flags the interrupt priority field and the program counter address extension field The CPU16 has a special set of instructions that ma nipulate the CCR S STOP Enable 0 Stop CPU16 clocks when LPSTOP instruction is executed 1 Perform NOPs when LPSTOP instruction is executed MV Accumulator M overflow flag Set when overflow into AM35 has occurred H Half Carry Flag Set when a carry from A3 or B3 occurs during BCD addition EV Extension Bit Overflow Flag Set when an overflow into AM31 has occurred N Negative Flag Set when the MSB of a result register is set Z Zero Flag Se
46. ACCUMULATOR D ACCUMULATOR E DEX REGISTER X DEX REGISTER Y DEX REGISTER Z STACK POINTER SP PROGRAM COUNTER PC CONDITION CODE REGISTER CCR PC EXTENSION FIELD PK ADDRESS EXTENSION REGISTER K STACK EXTENSION FIELD SK AC MULTIPLIER REGISTER HR AC MULTIPLICAND REGISTER IR AC ACCUMULATOR MSB 35 16 AM AC ACCUMULATOR LSB 15 0 AM AC XY MASK REGISTER CPU16 REGISTER MODEL Figure 4 1 CPU16 Register Model CENTRAL PROCESSOR UNIT For More Information On This Product MC68HC16R1 916R1 USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 2 1 Accumulators The CPU16 has two 8 bit accumulators A and B and one 16 bit accumulator E In addition accumulators A and B can be concatenated into a second 16 bit double ac cumulator D Accumulators A B and D are general purpose registers that hold operands and re sults during mathematical and data manipulation operations Accumulator E which can be used in the same way as accumulator D also extends CPU16 capabilities It allows more data to be held within the CPU16 during operations simplifies 32 bit arithmetic and digital signal processing and provides a practical 16 bit accumulator offset indexed addressing mode 4 2 2 Index Registers The CPU16 has three 16 bit index registers IX IY and IZ Each index register has an associated 4 bit extension field XK YK and ZK Concatenated re
47. ADDR ADDR ADDR ADDR ADDR ADDR ADDR 23 22 21 20 19 18 17 16 15 14 13 12 11 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLKSZ 2 0 Each chip select pin has an associated base address register A base address is the lowest address in the block of addresses enabled by a chip select CSBARBT contains the base address for selection of a boot memory device Bit and field definitions for CSBARBT and CSBAR 0 10 are the same but reset block sizes differ These registers may be read or written at any time ADDR 23 11 Base Address This field sets the starting address of a particular chip select s address space The address compare logic uses only the most significant bits to match an address within a block The value of the base address must be an integer multiple of the block size Base address register diagrams show how base register bits correspond to address lines BLKSZ 2 0 Block Size Field This field determines the size of the block that is enabled by the chip select Table D 12 shows bit encoding for the base address registers block size field MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table D 12 Block Size Field Bit Encoding BLKSZ 2 0 Block Size Address Lines Compared 000 2 Kbytes ADDR 23 11 001 8 Kbytes ADDR 23 13 010 16 Kbytes ADDR 23 14 011 64 Kbytes ADDR 23
48. CSOR10 YFFA78 Not Used YFFA7A Not Used YFFA7C Not Used YFFA7E Not Used NOTES 1 Y 2 M111 where M is the logic state of the module mapping MM bit in the SCIMCR MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL D 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc D 2 1 SCIM Configuration Register SCIMCR SCIM Module Configuration Register YFFAOO 15 14 13 12 1 10 9 8 7 6 5 4 2 1 0 EXOFF FRzsw FRZBM CPUD RSVD2 0 SHEN SUPV MM ABD RWD IARB RESET 0 0 0 0 0 0 0 1 1 cx 133 NOTES 1 Reset state is mode dependent Refer to the following bit descriptions 2 This bit is reserved for future use Ensure that initialization software does not change its value it should always read zero SCIMCR controls system configuration SCIMCR can be read or written at any time except for the module mapping MM bit which can only be written once after reset and the reserved bit which is read only Write has no effect EXOFF External Clock Off 0 The CLKOUT pin is driven during normal operation 1 The CLKOUT pin is placed in a high impedance state FRZSW Freeze Software Enable 0 When FREEZE is asserted the software watchdog and periodic interrupt timer continue to operate allowing interrupts during background debug mode 1 When FREEZE is asserted the software watchdog and periodic interrupt
49. Freescale Semiconductor Inc 5 9 4 Chip Select Reset Operation The least significant bit of each of the 2 bit chip select pin assignment fields in CSPARO and CSPAR1 each have a reset value of one The reset values of the most significant bits of each field are determined by the states of DATA 7 1 during reset There are weak internal pull up drivers for each of the data lines so that chip select operation is selected by default out of reset However the internal pull up drivers can be overcome by bus loading effects To ensure a particular configuration out of reset use an active device to put the data lines in a known state during reset The base address fields in chip select base address registers CSBAR 0 10 and chip select option registers CSOR 0 10 have the reset values shown in Table 5 25 The BYTE fields of CSOR 0 10 have a reset value of disable so that a chip select signal cannot be asserted until the base and option registers are initialized Table 5 25 Chip Select Base and Option Register Reset Values Fields Reset Values Base address 000000 Block size 2 Kbyte Async sync Mode Asynchronous mode Upper lower byte Disabled Read write Disabled AS DS AS DSACK No wait states Address space CPU space IPL Any level Autovector External interrupt vector Following reset the MCU fetches the initial stack pointer and program counter values from the exception vector table beginning at 000000 in supervi
50. Go to www freescale com Freescale Semiconductor Inc MOTOROLA MECHANICAL DATA AND ORDERING INFORMATION MC68HC16R1 916R1 B 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc APPENDIX C DEVELOPMENT SUPPORT This section serves as a brief reference to Motorola development tools for MC68HC16R1 916R1 microcontrollers Information provided is complete as of the time of publication but new systems and software are continually being developed In addition there is a growing number of third party tools available The Motorola Microcontroller Development Tools Directory MCUDEVTLDIR D Revision 3 provides an up to date list of development tools Contact your Motorola representative for further information C 1 M68MMDS1632 Modular Development System The M68MMDS1632 Motorola Modular Development System MMDS is a develop ment tool for evaluating M68HC16 and M68300 MCU based systems The MMDS1632 is an in circuit emulator which includes a station module and active probe A separately purchased MPB and PPB completes MMDS functionality with re gard to a particular MCU or MCU family The many MPBs and PPBs available let your MMDS emulate a variety of different MCUs Contact your Motorola sales representa tive who will assist you in selecting and configuring the modular system that fits your needs A full featured development system the MMDS provides both in circuit emula tion an
51. Inc Table 11 5 SCI Pins Pin Mode SCI Function Port I O Signal TXDA Serial data output from SCIA TE 1 PMC7 Transmit data TXDB Serial data output from SCIB TE 1 PMC5 RXDA Serial data input to SCIA RE 1 PMC6 Receive data z RXDB Serial data input to SCIB RE 1 PMC4 11 4 3 Receive Data Pins RXDA RXDB RXDA and RXDB are the serial data inputs to the SCIA and SCIB interfaces respec tively Each pin is also available as a general purpose I O pin when the RE bit in SCCR1 of the associated SCI submodule is cleared When used for general purpose RXDA and RXDB may be configured either as input or output as determined by the RXDA and RXDB bits in the MDDR 11 4 4 Transmit Data Pins TXDA TXDB When used for general purpose I O TXDA and TXDB can be configured either as input or output as determined by the TXDA and TXDB bits in the MDDR The TXDA and TXDB pins are enabled for SCI use by setting the TE bit in SCCR1 of each SCI interface 11 4 5 SCI Operation SCI operation can be polled by means of status flags in the SCSR or interrupt driven operation can be employed by means of the interrupt enable bits in SCCR1 11 4 5 1 Definition of Terms Data can be transmitted and received in a number of formats The following terms con cerning data format are used in this section e Bit Time The time required to transmit or receive one bit of data which is equal to one cycle of the ba
52. MODCLK 1 during reset fio is used with a slow reference oscillator 128 is used with fast reference oscillator When the PLL is disabled MODCLK 0 during reset fref is used The value of the periodic timer prescaler PTP bit in the periodic interrupt timer register PITR determines system clock prescaling for the periodic interrupt timer One of two options either no prescaling or prescaling by a factor of 512 can be selected The value of PTP is affected by the state of the MODCLK pin during reset as shown in Table 5 7 System software can change PTP value Table 5 7 MODCLK Pin and PTP Bit at Reset MODCLK PTP 0 External Clock 1 512 1 Internal Clock 0 1 Either clock signal selected by the PTP is divided by four before driving the modulus counter The modulus counter is initialized by writing a value to the periodic interrupt timer modulus PITM 7 0 field in PITR A zero value turns off the periodic timer When the modulus counter value reaches zero an interrupt is generated The modulus counter is then reloaded with the value in PITM 7 0 and counting repeats If a new value is written to PITR it is loaded into the modulus counter when the current count is completed The following equation calculates the PIT period when a slow reference frequency is used fret PIT Period The following equation calculates the PIT period when a fast reference frequency is used ref PIT Period
53. MSTRST and external EXTRST reset lines The power on reset circuit releases the internal reset line as Vpp ramps up to the minimum operating voltage and SCIM2 pins are initialized to the values shown in Table 5 21 When Vpp reaches the minimum op erating voltage the clock synthesizer VCO begins operation Clock frequency ramps up to specified limp mode frequency The external RESET line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse NOTE Vppsyn and all Vpp pins must be powered Applying power to VppsvN Only will cause errant behavior of the MCU MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 54 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The SCIM2 clock synthesizer provides clock signals to the other MCU modules After the clock is running and MSTRST is asserted for at least four clock cycles these mod ules reset Vpp ramp time and VCO frequency ramp time determine how long the four cycles take Worst case is approximately 15 milliseconds During this period module port pins may be in an indeterminate state While input only pins can be put in a known state by external pull up resistors external logic on input output or output only pins during this time must condition the lines Active drivers require high impedance buffers or isolation resistors to prevent conflict Figure 5 19 is a timing diagram for po
54. STANDBY RAM MODULE The standby RAM SRAM module consists of a fixed location control register block and 2 Kbyte array of fast two clock static RAM that may be mapped to a user spec ified location in the system memory map The SRAM is especially useful for system stacks and variable storage The SRAM can be mapped to any address that is a mul tiple of the array size so long as SRAM boundaries do not overlap the module control registers overlap makes the registers inaccessible Data can be read written in bytes words or long words SRAM is powered by Vpp in normal operation During power down SRAM contents can be maintained by power from the Vstpy input Power switching between sources is automatic 6 1 SRAM Register Block There are four SRAM control registers the RAM module configuration register RAMMCR the RAM test register RAMTST and the RAM array base address reg isters RAMBAH RAMBAL The module mapping bit MM in the SCIM configuration register SCIMCR defines the most significant bit ADDR23 of the IMB address for each MC68HC16R1 916R1 module Because ADDR 23 20 are driven to the same value as ADDR19 MM must be set to one If MM is cleared IMB modules are inaccessible For more information about how the state of MM affects the system refer to 5 2 1 Module Mapping The SRAM control register consists of eight bytes but not all locations are implement ed Unimplemented register addresses are read as zeros and w
55. The WOMP bit in the SPI control register SPCR determines whether each SPI pin that is configured for output functions as an open drain output or a normal CMOS output The MDDR and WOMP assignments are valid regardless of whether the pins are configured for SPI use or general purpose I O The operation of pins configured for SCI use depends on whether the SCI is operating as a master or a slave determined by the MSTR bit in the SPCR Table 11 3 shows SPI pins and their functions MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 11 3 SPI Pin Functions Pin Name Mode Function Master in slave out MISO Master Provides serial data input to the SPI Slave Provides serial data output from the SPI Master out slave in MOSI Master Provides serial output from the SPI Slave Provides serial input to the SPI Serial clock SCK Master Provides clock output from the SPI Slave Provides clock input to the SPI Slave select SS Master Detects bus master mode fault Slave Selects the SPI for an externally initiated serial transfer 11 3 3 SPI Operating Modes The SPI operates in either master or slave mode Master mode is used when the MCU originates data transfers Slave mode is used when an external device initiates serial transfers to the MCU The MSTR bit in SPCR selects master or slave
56. Transmit Complete 0 SCI transmitter is busy 1 SCI transmitter is idle MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product D 49 Go to www freescale com Freescale Semiconductor Inc RDRF Receive Data Register Full 0 Receive data register is empty or contains previously read data 1 Receive data register contains new data RAF Receiver Active 0 SCI receiver is idle 1 SCI receiver is busy IDLE Idle Line Detected 0 SCI receiver did not detect an idle line condition 1 SCI receiver detected an idle line condition OR Overrun Error 0 Receive data register is empty and can accept data from the receive serial shifter 1 Receive data register is full and cannot accept data from the receive serial shifter Any data in the shifter is lost and RDRF remains set NF Noise Error 0 No noise detected in the received data 1 Noise detected in the received data FE Framing Error 0 No framing error detected in the received data 1 Framing error or break detected in the received data PF Parity Error 0 No parity error detected in the received data 1 Parity error detected in the received data D 6 12 SCI Data Register SCDRA SCIA Data Register 1 SCDRB SCIB Data Register YFFC2E 15 9 8 7 6 5 4 3 2 1 0 NOT USED 8 78 R7 T7 8616 R5 TS R3 T3 8272 RIT ROMO RESET U
57. Y 17DF gggg 6 IND16 Z 17EF gggg 6 EXT 17FF hh Il 6 IMM16 37BF jj kk 4 LDX Load IX M M 1 IX IND8 X CC ff 6 A 0 IND8 Y DC ff 6 IND8 Z EC ff 6 IMM16 37BC jj kk 4 IND16 X 17 999g 6 IND16 Y 17DC 9999 6 IND16 2 17 9999 6 17 hh Il 6 LDY Load IY 1 IY IND8 cD ff 6 0 IND8 Y DD ff 6 IND8 Z ED ff 6 IMM16 37BD jj kk 4 IND16 X 17CD 9999 6 IND16 Y 17DD 9999 6 IND16 2 17ED 9999 6 EXT 17FD hh Il 6 LDZ Load IZ 1 12 IND8 6 A 0 IND8 Y DE ff 6 IND8 Z EE ff 6 IMM16 37BE jj kk 4 IND16 X 17CE 999g 6 IND16 Y 17DE 9999 6 IND16 2 17 9999 6 17FE hh 6 MC68HC16R1 916R1 MOTOROLA USER S MANUAL 4 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles 5 MV H EV 2 V C LPSTOP Low Power Stop IfS INH 27F1 4 20 then STOP else NOP LSR Logical Shift Right IND8 X OF ff 8 0 AAA IND8 Y 1F ff 8 eX EEEPLEEHE IND8 Z 2F ff 8 IND16 X 170F 9999 8 IND16 Y 171F 999g 8 IND16 Z 172F 9999 8 173F hh Il 8 LSRA Logical Shift
58. Y REGISTER B 16 BIT REGISTER B2 INTERRUPT CONTROL AA 16 BIT COMPARATOR B FLAG IL2 IL1 IL0 IARB3 CONTROL REGISTER BITS MODE3 MODE2 MODE1 MODEO CONTROL REGISTER BITS SUBMODULE BUS CTM DASM BLOCK Figure 12 6 DASM Block Diagram MC68HC16R1 916R1 CONFIGURABLE TIMER MODULE 7 MOTOROLA USER S MANUAL For More Information On This Product 12 13 Go to www freescale com Freescale Semiconductor Inc 12 9 1 DASM Interrupts The DASM can optionally request an interrupt when the FLAG bit in DASMSIC is set To enable interrupts set the IL 2 0 field in DASMSIC to a non zero value The CTM7 compares the CPU16 IP mask value to the priority of the requested interrupt designat ed by IL 2 0 to determine whether it should contend for arbitration priority During ar bitration the BIUSM provides the arbitration value specified by IARB 2 0 in BIUMCR and IARB3 in DASMSIC If the CTM7 wins arbitration it responds with a vector num ber generated by concatenating VECT 7 6 in BIUMCR and the six low order bits specified by the number of the submodule requesting service Thus for DASM9 in the CTM the six low order bits would be nine in decimal or 96001001 in binary 12 9 2 DASM Registers The DASM contains one status interrupt control register and two data registers A and B All unused bits and reser
59. YE Ne SY FF OFF 512 KBYTE 00 SECUQUUA Gui a SY FFAT7F FD0000 sanki 77000000007 YFFBOO CONTROL YFFBOT FE0000 2 2 4 BANK 14 YFFC00 MCCI FF0000 YFFC3F INTERNAL REGISTERS SYFFDFF Y FFFFFF TE 1 ADDRESSES DISPLA YED IN THIS MEMOR Y MAP ARE THE FULL 24 BIT IMB ADDRESSES THE CPU16 ADDRESS B US IS 20 BITS WIDE AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES 23 20 THE BLOCK OF ADDRESSES OM 080000 TO F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB MEMOR Y BANKS 0 TO 15 APPEAR FULL Y CONTIGUOUS IN THE 165 FLA T 20 BIT ADDRESS SP ACE THE CPU16 NEED ONL Y GENERA TE A 20 BIT EFFECTIVE ADDRESS ACCESS ANY LOCA TION IN THIS RANGE 916R1MEM MAP C Figure 3 10 MC68HC916R1 Combined Program and Data Space Map MC68HC16R1 916R1 OVERVIEW MOTOROLA USER S MANUAL For More Information On This Product 3 23 Go to www freescale com Freescale Semiconductor Inc VECTOR VECTOR YPE OF ADDRESS NUMBER EXCEPTION 0000 0 RESET INITIAL ZK SK AND PK 0002 1 RESET INITIAL PC 0004 2 RESET INITIAL SP 5000000 0006 3 RESET INITIAL Iz DIRECT PAGE T 000000 000008 I EXCEPTION VECTORS 000008 5010000 7 777
60. address function code size and read write signals revert to the previous driven states The MCU cannot service inter rupt requests while halted 5 6 6 External Bus Arbitration The MCU bus design provides for a single bus master at any one time Either the MCU or an external device can be master Bus arbitration protocols determine when an ex ternal device can become bus master Bus arbitration requests are recognized during normal processing HALT assertion and when the CPU has halted due to a double bus fault The bus controller in the MCU manages bus arbitration signals so that the MCU has the lowest priority External devices that need to obtain the bus must assert bus arbi tration signals in the sequences described in the following paragraphs Systems that include several devices that can become bus master require external cir cuitry to assign priorities to the devices so that when two or more external devices at tempt to become bus master at the same time the one having the highest priority becomes bus master first The protocol sequence is 1 An external device asserts the bus request signal BR 2 The MCU asserts the bus grant signal BG to indicate that the bus is available 3 An external device asserts the bus grant acknowledge BGACK signal to indicate that it has assumed bus mastership BR can be asserted during a bus cycle or between cycles BG is asserted in response to BR To guarantee operand cohere
61. follow the state of ADDR19 in the MCU 5 5 4 Misaligned Operands The CPU16 uses a basic operand size of 16 bits An operand is misaligned when it overlaps a word boundary This is determined by the value of ADDRO When ADDRO 0 an even address the address is on a word and byte boundary When ADDRO 1 an odd address the address is on a byte boundary only A byte operand is aligned at any address a word or long word operand is misaligned at an odd address The largest amount of data that can be transferred by a single bus cycle is an aligned word If the MCU transfers a long word operand through a 16 bit port the most signif icant operand word is transferred on the first bus cycle and the least significant oper and word is transferred on a following bus cycle The CPU16 can perform misaligned word transfers This capability makes it compati ble with the M68HC11 CPU The CPU16 treats misaligned long word transfers as two misaligned word transfers 5 5 5 Operand Transfer Cases Table 5 12 shows how operands are aligned for various types of transfers OPn entries are portions of a requested operand that are read or written during a bus cycle and are defined by SIZ1 SIZO and ADDRO for that bus cycle MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 28 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 12 Operand Alignment
62. or 16 ADC clock cycles depending on the value of the STS field in ADCTLO Resolution time is ten cycles for 8 bit conversion and twelve cycles for 10 bit conversion Transfer and resolution require a minimum of 16 ADC clocks 8 us with a 2 1 MHz ADC clock for 8 bit resolution or 18 ADC clocks 9 us with a 2 1 MHz ADC clock for 10 bit resolution If maximum final sample time 16 ADC clocks is used total conversion time is 15 us for an 8 bit conversion or 16 us for a 10 bit conversion with a 2 1 MHz ADC clock Figures 10 2 and 10 3 illustrate the timing for 8 and 10 bit conversions respectively These diagrams assume a final sampling period of two ADC clocks TRANSFER CONVERSION TO RESULT REGISTER AND SET CCF INITIAL FINAL SAMPLE TRANSFER SAMPLE 2 ADC CLOCKS RESOLUTION TIME 1 16 1 1 1 1 CYCLE CYCLE CYCLE CYCLE 1 1 1 1 CYCLE CYCLE CYCLE CYCLE SAR6 SARS5 SAR4 5AR3 SAR2 SARI SARO EOC 6 CYCLES SART lt SAMPLE AND TRANSFER SUCCESSIVE APPROXIMATION 35 END PERIOD SEQUENCE CH1 CH 2 CH 3 CH 4 CH5 CH 6 CH7 CH 8 SCF FLAG SET HERE AND SEQUENCE SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 4 CHANNEL MODE ENDS IF IN THE 8 CHANNEL MODE 16 ADC 8 BIT TIM 1 Figure 10 2 8 Bit Conversion Timing MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC16R1 916R1 10 12 For More Information On This Product USER S MANUAL
63. should place valid data on the bus DS PE4 88 0 SCIM2 during a read cycle that valid has y o been placed on the bus during a write cycle or digital I O port E4 DSACKO PEO 92 Data size and acknowledge inputs or DSACKT PE1 91 o SCIM2 digital O ports E 1 0 IS EXTAL 59 E SCIM2 oscillator or external clock in Z Phase locked loop reference select FASTREF PFO 83 1 SCIM2 input or digital VO port FO MC68HC16R1 916R1 OVERVIEW MOTOROLA USER S MANUAL For More Information On This Product 3 13 Go to www freescale com Table 3 3 MC68HC16R1 MC68HC916R1 Pin Functions Freescale Semiconductor Inc Pin Pin Active Associated Discrete Mnemonic s Number s State s Module Description Use m Function code output 0 chip select id output 3 or digital output port 1 1 118 SCIM2 Function code output 1 or digital out 1 uU Function code output 2 chip select FG2 GSSIPG2 192 5 SGIMZ output 5 or digital output port C2 3 Indicates that the CPU16 has en s tered background debug mode or FREEZEIQUET P i provides the quotient bit of the poly nomial divider in test mode HALT 72 0 SCIM2 Suspends bus activity Instruction pipeline state output 0 or IPIPEO DSO 67 CPU16 background debug mode serial data output Instruction pipeline state output 1 or IPIPE1 DSI
64. use an active device to drive MODCLK during reset 5 7 3 7 Breakpoint Mode Selection Background debug mode BDM is enabled when the breakpoint BKPT pin is sampled at a logic level zero at the release of RESET Subsequent assertion of the BKPT pin or the internal breakpoint signal for instance the execution of the CPU16 BKPT instruction will place the CPU16 in BDM If BKPT is sampled at a logic level one at the rising edge of RESET BDM is disabled Assertion of the BKPT pin or execution of the BKPT instruction will result in normal breakpoint exception processing BDM remains enabled until the next system reset BKPT is relatched on each rising transition of RESET BKPT is internally synchronized and must be held low for at least two clock cycles prior to RESET negation for BDM to be enabled BKPT assertion logic must be designed with special care If BKPT assertion extends into the first bus cycle following the release of RESET the bus cycle could inadvertently be tagged with a breakpoint Refer to 4 14 4 Background Debug Mode and the CPU16 Reference Manual CPU16RM AD for more information on background debug mode Refer to the SC M Reference Manual SCIMRM AD and APPENDIX A ELECTRICAL CHARACTERIS TICS for more information concerning BKPT signal timing 5 7 3 8 Emulation Mode Selection The SCIM2 contains logic that can be used to replace on chip ports externally The SCIM2 also contains special support logic t
65. 0 Periodic Interrupt Vector This field specifies the periodic interrupt vector number supplied by the SCIM2 when the CPU16 acknowledges an interrupt request D 2 17 Periodic Interrupt Timer Register PITR Periodic Interrupt Timer Register YFFA24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 PTP PITM 7 0 0 0 0 0 0 0 0 MODCLK 0 0 0 0 0 0 0 0 Contains the count value for the periodic timer This register can be read or written at any time PTP Periodic Timer Prescaler 0 Periodic timer clock not prescaled 1 Periodic timer clock prescaled by a value of 512 PITM 7 0 Periodic Interrupt Timing Modulus This field determines the periodic interrupt rate Use the following equations to calculate timer period MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 15 Go to www freescale com Freescale Semiconductor Inc The following equation calculates the PIT period when a slow reference frequency is used PIT Period The following equation calculates the PIT period when fast reference frequency is used PIT Period 128 PITM 7 0 1 if PTP 0 512 if PTP 1 4 fret The following equation calculates the PIT period for an externally input clock frequency on both slow and fast reference frequency devices PIT Period fsys D 2 18 Software Watchdog Service Register SWSR Software
66. 1 VRL RSLT 0 7 1 1 1 1 0 VRH Vn 2 RSLT 0 7 1 1 1 1 1 Test Reserved RSLT 0 7 NOTES 1 Result register RSLT is either RJURRX LJSRRX or LJURRX depending on the address read MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product D 37 Go to www freescale com Freescale Semiconductor Inc Table D 29 Multiple Channel Conversions MULT 1 S8CM CD CC CB Input Result Register 0 0 0 X X ANO RSLTO AN1 RSLT1 AN2 RSLT2 RSLT3 0 0 1 X X AN4 RSLTO AN5 RSLT1 AN6 RSLT2 AN7 RSLT3 0 1 0 X X Reserved RSLTO Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 0 1 1 X X VRH RSLTO VRL RSLT1 2 RSLT2 Test Reserved RSLT3 1 0 X X X ANO RSLTO AN1 RSLT1 AN2 RSLT2 RSLT3 AN4 RSLT4 AN5 RSLT5 AN6 RSLT6 AN7 RSLT7 1 1 X X X Reserved RSLTO Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 RSLT4 VRL RSLT5 2 RSLT6 Test Reserved RSLT7 NOTES 1 Result register is either RJURRX LJSRRX or LJURRX depending on the address read MOTOROLA D 38 For More Information On This Product Go to www freescale com MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc D 5 6 Status Register ADCSTAT Status Register YFF70E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCF NOT USED CCTR 2 0 CCF 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 ADCSTAT contains information related
67. 1 for more information Figure 12 7 shows a block diagram of the PWMSM MOTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 14 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 256 PRESCALER PCLKL ef ENABLE Fol SET OUTPUT OUTPUT OUTPUT CLOCK gt gt BUFFER SELECT CLEAR CLEAR CLK2 CLK1 CLKO 16 BIT UP COUNTER PWMC Y ALL ZEROS STATE ZERO 16 BIT COMPARATOR SEQUENCER 16 BIT COMPARATOR DETECT LOAD PERIOD REGISTER PULSE WIDTH REGISTER PWMA2 1e PWMB2 PWMA Y PWMB NEXT PERIOD REGISTER INTERRUPT NEXT PULSE WIDTH PWMAI CONTROL REGISTER PWMBI AAAA FLAG IL2 IL1 ILO IARB3 CONTROL REGISTER BITS SUBMODULE BUS CTM PWM BLOCK Figure 12 7 Pulse Width Modulation Submodule Block Diagram 12 10 1 Output Flip Flop and Pin The output flip flop is the basic output mechanism of the PWMSM Except when the required duty cycle is 0 or 100 the output flip flop is set at the beginning of each period and is cleared at the end of the designated pulse width The polarity of the out put pulse is user programmable The output flip
68. 10 9 8 7 6 5 0 8 10 8 10 8 10 8 10 8 10 8 10 8 10 8 10 10 10 NOT USED Conversion result is signed left justified data Bits 15 6 are used for 10 bit resolution For 8 bit conversions bits 15 8 contain data and bits 7 6 are zero Although the ADC is unipolar it is assumed that the zero point is halfway between low and high reference when this format is used Vay 1 2 For positive input bit 15 0 For negative input bit 15 1 Bits 5 0 always return zero when read MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product D 39 Go to www freescale com Freescale Semiconductor Inc D 5 9 Left Justified Unsigned Result Register LJURR Left Justified Unsigned Result Register YFF730 YFF73F 15 14 13 12 11 10 9 8 7 6 5 0 euo euo eno eno eno eno n n NOT USED Conversion result is unsigned left justified data Bits 15 6 are used for 10 bit resolu tion For 8 bit conversions bits 15 8 contain data and bits 7 6 are zero Bits 5 0 al ways return zero when read MOTOROLA MC68HC16R1 916R1 D 40 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 6 Multichannel Communication Interface Module Table D 30 MCCI Address Map Address 15 8 7 0 YFFCOO MCCI Mod
69. 11 14 Go to www freescale com Freescale Semiconductor Inc 11 3 8 Write Collision A write collision occurs if an attempt is made to write the SPDR while a transfer is in progress Since the SPDR is not double buffered in the transmit direction a successful write to SPDR would cause data to be written directly into the SPI shift register Because this would corrupt any transfer in progress a write collision error is generated instead The transfer continues undisturbed the data that caused the error is not writ ten to the shifter and the WCOL bit in SPSR is set No SPI interrupt is generated A write collision is normally a slave error because a slave has no control over when a master initiates a transfer Since a master is in control of the transfer software can avoid a write collision error generated by the master The SPI logic can however detect a write collision in a master as well as in a slave What constitutes a transfer in progress depends on the SPI configuration For a master a transfer starts when data is written to the SPDR and ends when SPIF is set For a slave the beginning and ending points of a transfer depend on the value of CPHA When CPHA 0 the transfer begins when SS is asserted and ends when it is negated When CPHA 1 a transfer begins at the edge of the first SCK cycle and ends when SPIF is set Refer to 11 3 4 SPI Clock Phase and Polarity Controls for more information on transfer periods and on avoiding w
70. 15 0 ROMBS3 ROM Bootstrap Word 3 YFF836 15 14 13 12 11 10 9 8 7 1 0 12 15 0 Typically CPU16 reset vectors reside in non volatile memory and are only fetched when the CPU16 comes out of reset These four words can be used as reset vectors with the contents specified at mask time The content of these words cannot be changed On generic blank ROM MC68HC16R1 916R1 devices ROMBS 0 3 are masked to 0000 When the ROM on the MC68HC16R1 916R1 is masked with cus tomer specific code ROMBS 0 3 respond to system addresses 00000 to 00006 during the reset vector fetch if BOOT 0 MC68HC16R1 916R1 USER S MANUAL REGISTER SUMMARY For More Information On This Product Go to www freescale com MOTOROLA D 31 Freescale Semiconductor Inc D 5 Analog to Digital Converter Module Table D 23 ADC Module Address Map Address 15 8 7 0 YFF700 ADC Module Configuration Register ADCMCR YFF702 ADC Test Register ADCTEST YFF704 Not Used YFF706 Not Used Port ADA Data Register PORTADA YFF708 Not Used YFF70A Control Register 0 ADCTLO YFF70C Control Register 1 ADCTL1 YFF70E Status Register ADCSTAT YFF710 Right Justified Unsigned Result Register 0 RJURRO YFF712 Right Justified Unsigned Result Register 1 RJURR1 YFF714 Right Justified Unsigned Result Register 2 RJ
71. 16 100 128 Kbytes ADDR 23 17 101 256 Kbytes ADDR 23 18 110 512 Kbytes ADDR 23 19 111 512 Kbytes ADDR 23 20 NOTES 1 ADDR 23 20 are the same logic level as ADDR19 during normal operation D 2 26 Chip Select Option Register Boot CSORBT Chip Select Option Register Boot YFFA4A 15 14 13 12 11 10 9 8 1 6 5 4 3 2 1 0 MODE BYTE 1 0 RAWI1 0 STRB DSACK 3 0 SPACE 1 0 2 0 AVEC RESET 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 D 2 27 Chip Select Option Registers CSOR 0 10 Chip Select Option Registers YFFA4E YFFA76 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE BYTE 1 0 RAWI1 0 STRB DSACK 3 0 SPACE 1 0 IPL 2 0 AVEC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSORBT and CSOR 0 10 contain parameters that support operations from external memory devices Bit and field definitions for CSORBT and CSOR 0 10 are the same MODE Asynchronous Synchronous Mode 0 Asynchronous mode is selected 1 Synchronous mode is selected and used with ECLK peripherals In asynchronous mode chip select assertion is synchronized with AS and DS In synchronous mode the chip select signal is asserted with ECLK BYTE 1 0 Upper Lower Byte Option This field is used only when the chip select 16 bit port option is selected in the pin assignment register This allows the usage of two external 8 bit memory devices to be concatenated to form a 16 bit memory Table D 13 shows upper l
72. 2 0 bits are being changed internal circuitry guarantees that spurious edges occurring on the CTM2C pin do not affect the MCSM The read only IN2 bit in MCSMSIC reflects the state of CTM2C This pin is Schmitt triggered and is synchronized with the system clock The maximum allowable frequency for a clock signal input CTM2C is fsys 4 12 7 4 MCSM External Event Counting When an external clock source is selected the MCSM can act as an event counter simply by counting the number of events occurring on the CTM2C input pin Alterna tively the MCSM can be programmed to generate an interrupt when a predefined number of events have been counted This is done by presetting the counter with the two s complement value of the desired number of events 12 7 5 MCSM Time Base Bus Driver The DRVA and DRVB bits in MCSMSIC select the time base bus to be driven Which of the time base buses is driven depends on where the MCSM is physically placed in any particular CTM implementation Refer to Figure 12 1 and Table 12 1 for more information WARNING Two time base buses should not be driven at the same time MC68HC16R1 916R1 CONFIGURABLE TIMER MODULE 7 MOTOROLA USER S MANUAL For More Information On This Product 12 9 Go to www freescale com Freescale Semiconductor Inc 12 7 6 MCSM Interrupts The MCSM can optionally request an interrupt when its counter overflows and the COF bit in MCSMSIC is set To enable interrupts set the IL 2 0 fi
73. 2 1 Module Mapping s 5 3 5 2 2 Interrupt Arbitration 5 3 5 2 3 Single Chip Operation Support 2 5 3 5 2 4 SHOW Internal mt eene ae UI S 5 4 5 2 5 Register ACCESS iere do popa SO gui lere 5 4 5 2 6 Freeze OpeTallofi uu uu hee Lot RR ERES 5 4 5 3 System KR eod edic Boote ee ribbon dieto noce 5 4 5 3 1 Clock SOUS cuca 5 5 5 3 2 Clock Synthesizer Operation 4 5 6 5 3 3 External Bus Clock ooa eicit ere rep set 5 14 5 3 4 Low Power Operation hose eate a etus E 5 14 5 4 System Protection RT 5 16 5 4 1 Reset Status a E ETE 5 16 5 4 2 Bus Monillora AU as 5 16 5 4 3 aa aE 5 17 5 4 4 Spurious Interrupt 5 17 5 4 5 Software Watchdog Ended 5 17 5 4 6 Periodic Interrupt Timer sho tected ie eb edt itae 5 20 5 4 7 Interrupt Priority and Vectoring 2 2 5 21 5 4 8 Low Power STOP Operation 044 5 21 55 External Bus Iniferf886s usa uuu a u deb ees asa d 5 22 5 5 1 Bus Coritrol SIgialS ea
74. 7 Function Codes for more information concerning address space types and program data space access Refer to 4 6 Addressing Modes for more in formation on addressing modes 6 4 Normal Access The array can be accessed by byte word or long word A byte or aligned word access takes one bus cycle or two system clocks A long word or misaligned word access re quires two bus cycles Refer to 5 6 Bus Operation for more information concerning access times 6 5 Standby and Low Power Stop Operation Standby and low power modes should not be confused Standby mode maintains the RAM array when the main MCU power supply is turned off Low power stop mode al lows the CPU16 to control MCU power consumption by disabling unused modules Relative voltage levels of the MCU Vpp and Vstpy pins determine whether the SRAM is in standby mode SRAM circuitry switches to the standby power source when Vpp drops below specified limits If specified standby supply voltage levels are maintained during the transition there is no loss of memory when switching occurs The RAM ar ray cannot be accessed while the SRAM module is powered from Vsrpy If standby operation is not desired connect the Vstpy pin to Vss Isp SRAM standby current values may vary while Vpp transitions occur Refer to AP PENDIX A ELECTRICAL CHARACTERISTICS for standby switching and power con sumption specifications 6 6 Reset Reset places the SRAM in low power stop mode enables program sp
75. BAUD RATE CLOCK PARITY GENERATOR SIZE 89 BREAK J 5 SCDR TX BUFFER WRITE ONLY E 10 11 BIT TX SHIFT REGISTER 6 5 4 3 2 1 0 SHIFT ENABLE PREAMBLE J 15 TRANSFER TX BUFFER FORCE PIN DIRECTION OUT TRANSMITTER CONTROL LOGIC MDDR7 MDDR5 A PIN BUFFER AND CONTROL OPEN DRAIN OUTPUT MODE ENABLE o gt i E CONTROL REGISTER 1 TOE RIE TE RE SCSR STATUS REGISTER u TC SCIRX REQUESTS SCIINTERRUPT REQUEST Figure 11 5 SCI Transmitter Block Diagram MOTOROLA 11 14 For More Information On This Product Go to www freescale com MULTICHANNEL COMMUNICATION INTERFACE INTERNAL DATA BUS MCCI SCI TX BLOCK MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc RECEIVER BAUD RATE 16 CLOCK DATA PIN BUFFER RECOVERY ALL ONES parity lt lt gt D gt wake up lt LOGIC 5 i 3 E z 15 SCCR1 CONTROL REGISTER 1 0 SCDR RX BUFFER S Ez READ ONLY Eg Bigl dl s el el e 15 SCSR STATUS REGISTER 0 SCI TX Y REQUESTS SCI INTERRUPT REQUEST INTERNAL DATA BUS 5 RX BLOCK Figure 11 6 SCI Receiver Block Diagram MC68HC16R1 916R1 MULTICHANNEL COMM
76. Chip Integration Module 2 5 2 3 1 3 1 3 Standby RAM SRAM e RP EUR dnd 3 1 3 1 4 Masked ROM Module MRM MC68HC16R1 Only 3 2 3 1 5 Flash EEPROM Modules FLASH MC68HC916R1 Only 3 2 3 1 6 Block Erasable Flash EEPROM BEFLASH MC68HC916R1 Only 3 2 3 1 7 Analog to Digital Converter ADC 3 2 3 1 8 Multichannel Communication Interface MCCI 3 2 3 1 9 Configurable Timer Module 7 CTM7 3 2 3 2 Interimodule BS eee ette esee ated te bep retenu cise 3 2 3 3 System Block Diagram and Pin Assignment Diagrams 3 3 3 4 Pili Descriptions 2 6 3 8 3 5 CPU16 Memory Mapping cet t o Er Ee ie P 3 16 3 6 Internal Register Maps rea eie Sepe 3 17 3 7 Address Space 3 20 SECTION 4 CENTRAL PROCESSOR UNIT 4 1 EI MEE 4 1 4 2 Regist r Model iiei a a Eear iea 4 1 4 2 1 PCCUIMUIALONS 4 3 4 2 2 Index 4 3 4 2 3 Slack ua L au ua 4 3 4 2 4 Program Courter s 4 3 4 2 5 Condition Code Register
77. Control Cycles An external device or a chip select circuit must assert at least one of the DSACK 1 0 signals or the AVEC signal to terminate a bus cycle normally Bus exception control cycles are used when bus cycles are not terminated in the expected manner There are two sources of bus exception control cycles Bus error signal BERR When neither DSACK nor AVEC is asserted within a specified period after as sertion of AS the internal bus monitor asserts internal BERR The spurious interrupt monitor asserts internal BERR when an interrupt re quest is acknowledged and no IARB contention occurs BERR assertion termi nates a cycle and causes the MCU to process a bus error exception External devices can assert BERR to indicate an external bus error Halt signal HALT HALT can be asserted by an external device to cause single bus cycle opera tion HALT is typically used for debugging purposes To control termination of a bus cycle for a bus error condition properly DSACK BERR and HALT must be asserted and negated synchronously with the rising edge of CLKOUT This ensures that setup time and hold time requirements are met for the same falling edge of the MCU clock when two signals are asserted simultaneously Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more information Ex ternal circuitry that provides these signals must be designed with these constraints in mind or the internal bus monitor must be us
78. D 6 10 SCI Control Register 1 SCCR1A SCIA Control Register 1 YFFC1A SCCR1B SCIB Control Register 1 YFFC2A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pu LOOPS 5 ILT PT PE M WAKE TIE TCIE RIE ILIE TE RE RWU SBK RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 contains SCI configuration parameters including transmitter and receiver en able bits interrupt enable bits and operating mode enable bits SCCRO can be read or written at any time The SCI can modify the RWU bit under certain circumstances Changing the value of SCCR1 bits during a transfer operation can disrupt the transfer MC68 USER S MANUAL HC16R1 916R1 MOTOROLA For More Information On This Product D 47 Go to www freescale com Freescale Semiconductor Inc Bit 15 Not Implemented LOOPS Loop Mode 0 Normal SCI operation no looping feedback path disabled 1 Test SCI operation looping feedback path enabled The LOOPS bit in SCCR1 controls a feedback path on the data serial shifter When LOOPS is set SCI transmitter output is fed back into the receive serial shifter The TXD pin is asserted idle line Both transmitter and receiver must be enabled prior to entering loop mode WOMS Wired OR Mode for SCI Pins 0 If configured as an output TXD is a normal CMOS output 1 If configured as an output TXD is an open drain output ILT Idle Line Detect Type 0 Short idle lin
79. D 7 8 MCSM Modulus Latch Registers D 7 9 FCSM Status Interrupt Control Register D 7 10 ECSM Counter Register D 7 11 DASM Status Interrupt Control Registers D 7 12 DASM Data Register A D 7 13 DASM Data Register D 7 14 SASM Status Interrupt Control Registers D 7 15 SASM Data Registers D 7 16 PWM Status Interrupt Control Register D 7 17 PWM Period Register D 7 18 PWM Pulse Width Register D 7 19 PWM Counter Register D 8 Flash EEPROM Modules D 8 1 Flash EEPROM Module Configuration Registers D 8 2 Flash EEPROM Test Registers D 8 3 Flash EEPROM Base Address Registers D 8 4 Flash EEPROM Control Register D 8 5 Flash EEPROM Bootstrap Words D 9 Block t ertt E D 9 1 BEFLASH Module Configuration Register D 9 2 BEFLASH Test Register
80. DEVICE S0 1 SET RW TO READ 2 DRIVE ADDRESS ON ADDR 23 0 3 DRIVE FUNCTION CODE ON FC 2 0 4 DRIVE SIZ 1 0 FOR OPERAND SIZE Y ASSERT AS AND DS S1 PRESENT DATA 52 1 DECODE ADDR R W SIZ 1 0 DS XC 2 PLACE DATA ON DATA 15 0 OR DECODE DSACK 53 DATA 15 8 IF 8 BIT DATA 3 DRIVE DSACK SIGNALS Y LATCH DATA 54 Y NEGATE AS ANDIDS 155 TERMINATE CYCLE 55 Y 1 REMOVE DATA FROM DATA BUS START NEXT CYCLE S0 2 NEGATE DSACK RD CYC FLOW Figure 5 11 Word Read Cycle Flowchart 5 6 2 2 Write Cycle During a write cycle the MCU transfers data to an external memory or peripheral device If the instruction specifies a long word or word operation the MCU attempts to write two bytes at once For a byte operation the MCU writes one byte The portion of the data bus upon which each byte is written depends on operand size peripheral ad dress and peripheral port size Refer to 5 5 2 Dynamic Bus Sizing and 5 5 4 Misaligned Operands for more infor mation Figure 5 12 is a flow chart of a write cycle operation for a word transfer Refer to the SCIM Reference Manual SCIMRM AD for more information MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 31 Go to www freescale com Freescale Semiconductor Inc MCU ADDRESS DEVICE S0 1 SET R W
81. E Signal Bus Control Signal PEPA7 PE7 SIZ1 6 PE6 SIZO 5 5 5 PEPA4 PE4 DS PEPA3 PE3 2 2 AVEC 1 PE1 DSACK1 PEPAO PEO DSACKO NOTES 1 The CPU16 does not support the RMC function for this pin This bit is not connected to a pin for I O usage D 2 12 Port F Data Register PORTFO Port F Data Register 0 YFFA19 PORTF1 Port F Data Register 1 YFFA1B 15 8 7 6 5 4 3 2 1 0 NOT USED PF7 PF6 PF5 PF4 2 1 PFO RESET U U U U U U U U This register can be accessed in two locations and can be read or written at any time A write to this register is stored in an internal data latch and if any pin in the corresponding port is configured as an output the value stored for that bit is driven out on the pin A read of this data register returns the value at the pin only if the pin is configured as a discrete input Otherwise the value read is the value stored in the register Bits 15 8 are unimplemented will always read zero D 2 13 Port F Data Direction Register DDRF Port F Data Direction Register YFFA1D 15 8 7 6 5 4 3 2 1 0 NOT USED DDF7 DDF6 DDF5 DDF3 DDF2 DDF1 DDFO RESET 0 0 0 0 0 0 0 0 This register controls the direction of the port F pin drivers when pins are configured for I O Setting a bit configures the corresponding pin as an output clearing a bit configures t
82. EEPROM YFF800 MC68HC916R1 only BEFLASH YFF7A0 MC68HC916R1 only Control registers for all the modules in the microcontroller are mapped into a 4 Kbyte block The state of the module mapping MM bit in SCIMCR determines where the control registers block is located in the system memory map When MM 0 register addresses range from 7FF000 to 7FFFFF when MM 1 register addresses range from FFFOOO to FFFFFF With the CPU16 ADDR 23 20 follow the logic state of ADDR19 unless driven externally MM corresponds to IMB ADDR23 If it is cleared the SCIM2 maps IMB modules into address space 7FF000 7FFFFF which is inaccessible to the CPU16 Modules remain inaccessible until reset occurs The reset state of MM is one but the bit is onetime writable Initialization software should make certain it remains set D 1 Central Processing Unit CPU16 registers are not part of the module address map Figure D 1 is a functional representation of CPU resources MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 1 Go to www freescale com Freescale Semiconductor Inc MOTOROLA D 2 20 16 15 8 7 0 A B D E XK X YK Y ZK Z SK SP PK PC CCR PK EK XK YK ZK SK HR IR A A XMSK YMSK BIT POSITION ACCUMULATORS A AND B ACCUMULATOR D
83. Freescale Semiconductor Inc Address Type 0000 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT 15 14 13 12 11110 9 8 7 6 5 4 3 2 1 0 0002 BYTEO BYTE1 0004 X OFFSET Y OFFSET X OFFSET OFFSET 0006 BCD1 BCDO BCD1 BCDO 0008 WORD 0 000A WORD1 000C MSW LONG WORD 0 000E LSW LONG WORD 0 0010 MSW LONG WORD 1 0012 LSW LONG WORD 1 0014 lt Radix Point 16 BIT SIGNED FRACTION 0 0016 lt Radix Point 16 BIT SIGNED FRACTION 1 0018 lt Radix Point MSW 32 BIT SIGNED FRACTION 0 001A LSW 32 BIT SIGNED FRACTION 0 0 001C lt Radix Point MSW 32 BIT SIGNED FRACTION 1 001E LSW 32 BIT SIGNED FRACTION 1 0 MAC Data Types 5 _ gt eee KK Cw 7 lt Radix Point MSW 32 BIT SIGNED FRACTION 15 0 LSW 32 BIT SIGNED FRACTION Radix Point 16 BIT SIGNED FRACTION Address Data Type 19 16 15 0 4 Bit Address Extension 16 Bit Byte Address Figure 4 3 Data Types and Memory Organization 4 6 Addressing Modes The CPU16 uses nine types of addressing There are one or more addressing modes within each type Table 4 1 shows the addressing modes MOTOROLA CENTRAL PROCESSOR UNIT MC68HC16R1 916R1 4 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semicondu
84. Go to www freescale com Freescale Semiconductor Inc TRANSFER CONVERSION TO RESULT REGISTER AND SET CCF INITIAL FINAL SAMPLE TRANSFER SAMPLE TIME TIME TIME RESOLUTION TIME gt 2 ADC CLOCKS 1 16 1 2 1 1 1 1 1 1 1 1 1 1 6 CYCLES CYCLES L a Eve ue var vere esee event ete ayar CYCLE SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 SARI SARO EOC SAMPLE AND TRANSFER gt lt SUCCESSIVE APPROXIMATION P END PERIOD SEQUENCE CH1 CH 2 CH 3 CH4 CH5 CH6 CH7 CH8 SCF FLAG SET HERE AND SEQUENCE SCF FLAG SET HERE AND SEQUENCE ENDS IF IN THE 4 CHANNEL MODE ENDS IF IN THE 8 CHANNEL MODE 16 ADC 10 BIT TIM Figure 10 3 10 Bit Conversion Timing 10 7 7 Successive Approximation Register The successive approximation register SAR accumulates the result of each conver sion one bit at a time starting with the most significant bit At the start of the resolution period the MSB of the SAR is set and all less significant bits are cleared Depending on the result of the first comparison the MSB is either left set or cleared Each successive bit is set or left cleared in descending order until all eight or ten bits have been resolved When conversion is complete the content of the SAR is transferred to the appropriate result register Refer to APPENDIX D REGISTER SUMMARY for register mapping and configuration 10 7 8 Result Registers Result registers are used to store data afte
85. Inc VppA vega SUPPLY V Var REFERENCE RC DAC ARRAY AND ANTIPADAT COMPARATOR ANG PADAG ANALOG 5 5 MUX AN4 PADA4 AND SAMPLE AN3 PADA3 BUFFER AMP AN2 PADA2 ANI PADAI ANO PADAO SAR RESERVED RESERVED RESERVED RESULTO RESERVED INTERNAL y CONNECTIONS RESERVED L RESULT 2 i PORT ADA DATA RESULT 3 REGISTER RESULT 5 o RESULT 6 gt RESULT 7 CLK SELECT PRESCALE ADC BUS INTERFACE UNIT INTERMODULE BUS IMB 16 ADC BLOCK 2 Figure 10 1 ADC Block Diagram 10 2 1 Analog Input Pins Each of the eight analog input pins AN 7 0 is connected to a multiplexer in the ADC The multiplexer selects an analog input for conversion to digital data Analog input pins can also be read as digital inputs provided the applied voltage meet Vin and specification When used as digital inputs the pins are organized into 8 bit port PORTADA and referred to as PADA 7 0 There is no data direction regis ter because port pins are input only MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC16R1 916R1 10 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 10 2 2 Analog Reference Pins Separate high Vay and low Vp analog reference voltages are connected to the an alog reference pins The pins permit connection of regulated and filtered supplies that allow the ADC to achieve its highest degree of accu
86. MANUAL For More Information On This Product 3 3 Go to www freescale com Freescale Semiconductor Inc TE CTS12A 512 CTS10A CTS10B CTS8A 44 CTS8B 4 CTS16B 4 9 CTS14A 2 5 CTS14B 4 56 lt CTS6B CHIP ADDR23 CS10 SELECTS ADDR22 CS9 PC6 ADDR21 CS8 5 ADDR20 CS7 4 ADDRI9 CS6 PC3 48K FC2 CS5 PC2 MASKED FC1 PC1 ROM TT FCO CS3 PCO SCIM2 BRICSO ADDR 23 19 BGICSM AN6PA BGACK ICSE ANS PA 1 5 1 5 AN3 PA 6 SASMs d g PA 7 0 ADDR 18 11 AN2IPA 2 DASMs ADDR 18 3 ANIPA 2 PWMSMs i PBOJADDR IO3 ANO PA UL ADDR 2 0 EBI 5171 5171 7 5170 5170 6 AS E AS PES DS OJ w DS PE4 AVEC AVEC PE2 Gare eee cen ees DSACKI DSACKI PE1 DSACKO DSACKO PEO RW RESET at HALT BERR 8 5 5 55 DATA 15 0 E TXDA PMC7 g PHIZ OVDATAIZ0 poud JE ARE ROW IRQTIPF7 TROOIPFO oe FASTREF IROSIPES SS PMC3 IRQ4 PF4 TCKPMC7 E IRQ3 PF3 MOSI PMC1 amp IRQ2 PF2 MISO PMCO IRQI PFI E i FASTREF PFO CLOCK CLKOUT XTAL EXTAL XFC Vopsyn MODCLK Vsssyn VsrTBY TSC BKPT DSCLK TEST d IPIPE1 DSI QUOT
87. MANUAL For More Information On This Product A 17 Go to www freescale com Freescale Semiconductor Inc CLKOU ADDR 23 0 gt FC 2 0 SIZ 1 0 BERR 9 DATA 15 0 rag 16 CHIP SEL Figure A 11 Chip Select Timing Diagram RESET DATA 15 0 MODCLK BKPT 16 RST MODE SEL TIM Figure A 12 Reset and Mode Select Timing Diagram MOTOROLA MC68HC16R1 916R1 A 18 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 7 20 97 MHz Background Debug Mode Timing Vbo and 5 0 5 Vos 0 Vdc T to T Num Characteristic Symbol Min Max Unit BO DSI Input Setup Time tpsisu 15 ns B1 DSI Input Hold Time tpsiH 10 ns B2 DSCLK Setup Time tpscsu 15 ns B3 DSCLK Hold Time tpscH 10 ns B4 050 Delay Time tpsop 25 ns B5 DSCLK Cycle Time tpsccvc 2 B6 High to FREEZE Asserted Negated tERZAN 50 ns B7 CLKOUT High to IPIPE1 High Impedance tirz TBD ns B8 CLKOUT High to IPIPE1 Valid tir TBD ns B9 DSCLK Low Time tpscLo 1 B10 IPIPE1 High Impedance to FREEZE Asserted tiPFA TBD lcyc B11 FREEZE Negated to IPIPE 0 1 Active TBD lcyc NOTES 1 All AC timing is shown with respect to Vi Vij levels unless otherwise noted FREEZE A BKPT DSCLK I
88. MCU does not come out of reset until the synthesizer locks Crystal type characteristic frequency and layout of external oscillator circuitry affect lock time When the clock synthesizer is used SYNCR determines the system clock frequency and certain operating parameters The W and Y 5 0 bits are located in the PLL feed back path enabling frequency multiplication by a factor of up to 256 When the W or Y values change VCO frequency changes and there is a VCO relock delay The SYNCR X bit controls a divide by circuit that is not in the synthesizer feedback loop When X 0 reset state a divide by four circuit is enabled and the system clock frequency is one fourth the VCO frequency fyco When X 1 a divide by two circuit is enabled and system clock frequency is one half the VCO frequency fyco There is no relock delay when clock speed is changed by the X bit When a slow reference is used one W bit and six Y bits are located in the PLL feed back path enabling frequency multiplication by a factor of up to 256 The X bit is located in the VCO clock output path to enable dividing the system clock frequency by two without disturbing the PLL When using a slow reference the clock frequency is determined by SYNCR bit settings as follows 2W X fsys 4fe Y 1 2 The reset state of SYNCR 3F00 results in a power on fsys of 8 388 MHz when fref is 32 768 kHz When a fast reference is used three W bits are located in th
89. O Pins BG CSM or 0 4 lo 12 mA Group 3 0 4 10 Three State Control Input High Voltage 1 6 Vpp 94 V Data Bus Mode Select Pull up Current 10 11 Vin Vi DATA 15 0 IMSP 120 pA Vin DATA 15 0 15 MC68HC16R1 Vpp Supply Current 12 13 12 Run 125 mA LPSTOP crystal VCO Off STSCIM 0 DD TBD uA LPSTOP external clock input frequency maximum fsys 10 mA MC68HC916R1 Vpp Supply Current 12 13 12A Run 160 mA LPSTOP crystal VCO Off STSCIM 0 DD TBD uA LPSTOP external clock input frequency maximum fsys 10 mA 13 Clock Synthesizer Operating Voltage VppsYN 4 5 5 5 V Supply Current t 13 VCO on 4 195 MHZ crystal reference maximum fsys 2 mA External Clock maximum fsys 7 mA VCO on 32 786 kHZ crystal reference maximum TBD mA 14 External Clock maximum fsys IDDSYN TBD mA LPSTOP 4 195 MHZ crystal reference VCO off STSCIM 0 2 4 195 MHZ crystal Vpp powered down 2 LPSTOP 32 768 kHZ crystal reference VCO off STSCIM 0 TBD uA 32 768 kHZ crystal Vpp powered down TBD uA RAM Standby Voltage 15 Specified Vpp applied Vsp 0 0 5 5 V Vpp Vss 3 0 5 5 MC68HC16R1 916R1 ELECTRICAL CHARACTERISTICS MOTOROLA USER S MANUAL For More Information On This Product 5 Go to www freescale com Freescale Semiconductor Inc Table A 5 DC Characteristics Continued Vip ANd Vppsyn 5 0 5 Veg 0 Vd
90. PLANE H IS LOCATED AT THE UNDERSIDE EADS WHERE LEADS EXIT PACKAGE BODY ATUMS L M AND N TO BE DETERMINED WHERE ER LEADS EXIT PACKAGE BODY AT DATUM H MENSIONS S AND V TO BE DETERMINED AT EATING PLANE DATUM T PLANE 7 DIMENSIONS A B J AND P TO BE DETERMINED AT ATUM PLANE H T 8 DIMENSION F DOES NOT INCLUDE DAMBAR ROTRUSIONS DAMBAR PROTRUSION SHALL 132x D1 NOT CAUSE THE LEAD WIDTH TO EXCEED 0 019 0 008 0 0 010 T L MI N ax 33 TIPS 2 3 lt 0 9595 MEE m 0004 T 132x E SEATING U CJ C Q Q UO O OC L MI N INCHES DIM MIN A 1 100 BSC A1 0 550 BSC B 1 100 BSC B1 0 550 BSC Y C 0160 0 180 K1 C1 0 020 0 040 H 1 C2 0 135 0 145 Wa t Y y D 0 008 0 012 D m ESS PLANE Di 0 012 0 016 D2 0 008 0 011 U w E 0 006 0 008 K E1 0 005 0 007 132x D r F 0 014 0 014 G 0 025 BSC 0 008 W 1 6 1 025550 J1 0 475 BSC SECTION AA AA K 0 034 0 044 K1 0 010 BSC P 0 950 BSC P1 0 475 BSC R1 0 013 REF S 1 080 BSC S1 0 540 BSC U 0 025 REF 1 080 5 Vi 0 540 BSC W 0 006 0 008 0 09 89
91. Semiconductor Inc Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV 2 V C SUBB Subtract from B gt B IND8 co ff 6 A AAA IND8 Y DO ff 6 IND8 Z EO ff 6 IMM8 FO ii 2 IND16 X 17 0 999g 6 IND16 Y 17D0 999g 6 IND16 Z 17E0 999g 6 EXT 17F0 hh Il 6 E X 27C0 6 2700 6 E Z 27E0 6 SUBD Subtract from D D M M 1 gt D IND8 X 80 ff 6 A AAA IND8 Y 90 ff 6 IND8 Z AO ff 6 IMM16 37 0 jj kk 4 IND16 X 37C0 9999 6 IND16 Y 37D0 90909 6 IND16 2 37E0 9999 6 37 0 hh Il 6 2780 6 2790 6 2 27 0 6 SUBE Subtract from E E M M 1 gt E IMM16 3730 jj kk 4 A AAA IND16 X 3740 gggg 6 IND16 Y 3750 90909 6 IND16 2 3760 9999 6 3770 hh Il 6 SWI Software Interrupt PK PC 0002 2 PK PC INH 3720 16 Push PC SK SP 0002 2 SK SP Push CCR SK SP 0002 2 SK SP 0 PK SWI Vector SXT Sign Extend B into A If B7 1 INH 27F8 2 A A then FF gt A else 00 gt A TAB Transfer A to B INH 3717 2 0 Transfer A to CCR A 7 0 CCR 15 8 INH 37FD 4 A A A AJA A A TBA Transfer B to A gt A INH 3707 2 A 0 TBEK Tran
92. Serial clock frequency range is from DC to one half the CPU16 clock frequency If DSCLK is derived from the CPU16 system clock development system serial logic can be synchronized with the target processor The serial interface operates in full duplex mode Data transfers occur on the falling edge of DSCLK and are stable by the following rising edge of DSCLK Data is trans mitted MSB first and is latched on the rising edge of DSCLK The serial data word is 17 bits wide which includes 16 data bits and a status control bit Bit 16 indicates status of CPU generated messages Command and data transfers initiated by the development system must clear bit 16 All commands that return a result return 16 bits of data plus one status bit MOTOROLA MC68HC16R1 916R1 4 44 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc CPU DEVELOPMENT SYSTEM INSTRUCTION i REGISTER BUS 16 RCV DATA LATCH COMMAND LATCH SERIAL IN PARALLEL IN PARALLEL OUT SERIAL OUT PARALLEL IN SERIAL IN SERIAL OUT PARALLEL OUT 16 STATUS lt W RESULT LATCH EXECUTION UNIT 16 SYNCHRONIZE MICROSEQUENCER STATUS DATA DSC CONTROL SERIAL LOGIC CLOCK BDM SER COM BLOCK CONTROL LOGIC Figure 4 7 BDM Serial I O Block Diagram 4 15 Recommended BDM Connection In order to use BDM development tools when an MCU is installed in a system Motor ola recommen
93. Single Chip None None ADDR 2 0 are normally placed in a high impedance state in single chip mode and function as normal address bus pins in the expanded modes Refer to D 2 1 SCIM Configuration Register for information on the address bus disable ABD bit The ADDR 23 19 pins can also be used as chip selects or discrete output pins de pending on the external bus configuration selected at reset The following paragraphs contain a summary of pin configuration options for each external bus configuration MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 43 Go to www freescale com Freescale Semiconductor Inc 5 7 3 2 Data Bus Mode Selection All data lines have weak internal pull up devices When pins are held high by the internal pull ups the MCU uses a default operating configuration However specific lines can be held low externally during reset to achieve an alternate configuration NOTE External bus loading can overcome the weak internal pull up drivers on data bus lines and hold pins low during reset Use an active device to hold data bus lines low Data bus configuration logic must release the bus before the first bus cycle after reset to prevent conflict with external memory devices The first bus cycle occurs ten CLKOUT cycles after RESET is released If external mode selection logic causes a conflict of this type an isolation resistor on the dr
94. Subsystem uuu a epar uev PR pa eO HL pe aa a u ha 10 4 10 6 1 M lliplGXOI uiuo eer HEREDI HARUM A Riu 10 5 10 6 2 Sample Capacitor and Buffer Amplifier 10 5 10 6 3 HO DAGABITIV Se at a 10 6 10 6 4 Comparator lt ui UM M uM 10 6 10 7 Digital Control Subsystem s a coe reti oH De rx ne et ou es ence ae 10 6 10 7 1 Control Status Registers 10 6 10 7 2 Clock and Prescaler 10 6 10 7 3 cmm 10 7 10 7 4 PICS OI TON Go 10 7 10 7 5 Conversion Control Logic PE teta estt 10 7 10 7 5 1 Conversion Parameters 10 8 10 7 5 2 Conversion Modes 10 8 10 7 6 Conversion Timing seti 10 12 10 7 7 Successive Approximation Register 10 13 10 7 8 Result Registers err aad shan bese 10 13 10 87 PiniorsidelallOris ooo ini er i E c Re Q auqa a 10 14 10 8 1 Analog Reference Pins anre eeu ip das acu aude 10 14 10 8 2 Analog Power Pis u u u unn RERUM 10 14 10 8 3 Analog Supply Filte
95. TA 25 G MC68HC16R1 Vpp Supply Current LPSTOP External clock maximum fsys 3 mA MC68HC916R1 Vpp Supply Current 3A RUN Ipp 130 mA LPSTOP External clock maximum fsys 5 mA 4 Synthesizer Operating Voltage VDDSYN 5 0 V Vppsvw Supply Current VCO on maximum fsys 1 0 mA 5 External Clock maximum fsys IDDSYN 4 0 mA LPSTOP VCO off 250 uA Vpp powered down 50 uA 6 RAM Standby Voltage Vsp 3 0 V RAM Standby Current 7 Normal RAM operation Isp 7 0 uA Standby operation 40 uA 8 MC68HC16R1 Power Dissipation Pp 500 mW MC68HC916R1 Power Dissipation Pp 675 mW MOTOROLA ELECTRICAL CHARACTERISTICS MC68HC16R1 916R1 A 2 For More Information On This Product Go to www freescale com USER S MANUAL Freescale Semiconductor Inc Table A 3 Thermal Characteristics Num Characteristic Symbol Value Unit Thermal Resistance 5 Plastic 132 Surface Mount ua 38 e W The average chip junction temperature TJ in C can be obtained from Ty TA PpxOjA 1 where Ta Ambient Temperature C a Package Thermal Resistance Junction to Ambient C W Pp Pint Pro Pint lpp Watts Chip Internal Power Pyo Power Dissipation on Input and Output Pins User Determined For most applications Pyo lt and can be neglected An approximate relationship between Pp and Ty if Pyo is neglected is Pp K Ty 273 C 2 Solving equations 1 and 2 for K gives Pp x Ty 273 C
96. There are 52 predefined or reserved vectors and 200 user defined vectors Each vector is assigned an 8 bit number Vector numbers for some exceptions are generated by external devices others are supplied by the processor There is a direct mapping of vector number to vector table address The processor left shifts the vector number one place multiplies by two to convert it to an address MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product 4 37 Go to www freescale com Freescale Semiconductor Inc Table 4 5 Exception Vector Table Vector Vector Address Type of Number Address Space Exception 0 0000 P Reset Initial ZK SK and PK 0002 P Reset Initial PC 0004 P Reset Initial SP 0006 P Reset Initial IZ Direct Page 4 0008 D Breakpoint 5 000A D Bus Error 6 000C D Software Interrupt 7 000 D Illegal Instruction 8 0010 D Division by Zero 9 0012 001 D Unassigned Reserved F 001 D Uninitialized Interrupt 10 0020 D Unassigned Reserved 11 0022 D Level 1 Interrupt Autovector 12 0024 D Level 2 Interrupt Autovector 13 0026 D Level 3 Interrupt Autovector 14 0028 D Level 4 Interrupt Autovector 15 002A D Level 5 Interrupt Autovector 16 002C D Level 6 Interrupt Autovector 17 002E D Level 7 Interrupt Autovector 18 0030 D Spurious Interrupt 19 37 0032 006E D Unassigned Reserved 38 FF 0070 01FE D User Defined Interr
97. Timing Diagram MOTOROLA MC68HC16R1 916R1 A 14 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc wn w wn wn a wn gt gt a gt CLKOUT ADDR 23 0 DATA 15 0 DSACKO TSG 5 PI Y EE 08 IPIPEO PHASE 1 PHASE 2 IPIPEL aero L 16 BUS ARB TIM Figure A 8 Bus Arbitration Timing Diagram Active Bus Case MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product A 15 Go to www freescale com Freescale Semiconductor Inc gt 0 gt CLKOUT ADDR 23 0 DATA 15 0 ef UU a 16 BUS ARB TIM IDLE Figure A 9 Bus Arbitration Timing Diagram Idle Bus Case MOTOROLA MC68HC16R1 916R1 A 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 50 541 542 543 50 51 52 PL E ADDR 23 0 2 DATA 15 0 Ba d IA EI pad a mu PT IPIPE0 CD 0 73 n Oian Oan Osan V je SHOW CYCLE gt lt start OF EXTERNAL CYCLE gt NOTE SHOW CYCLES CAN STRETCH DURING CLOCK PHASE 542 WHEN BUS ACCESSES TAKE LONGER THAN TWO CYCLES DUE TO IMB MODULE WAIT STATE INSERTION 16 SHW CYC TIM Figure A 10 Show Cycle Timing Diagram MC68HC16R1 916R1 MOTOROLA USER S
98. To mini mize overall microcontroller power consumption the CPU can execute the LPSTOP instruction which causes the SCIMe to turn off the system clock When individual module STOP bits are set clock signals inside each module are turned off but module registers are still accessible When the CPU executes LPSTOP a special CPU space bus cycle writes a copy of the current interrupt mask into the clock control logic The SCIM2 brings the MCU out of low power stop mode when one of the following exceptions occur e RESET Trace SCIM2 interrupt of higher priority than the stored interrupt mask Refer to 5 6 4 2 LPSTOP Broadcast Cycle for more information During a low power stop mode unless the system clock signal is supplied by an external source and that source is removed the SCIM clock control logic and the SCIM clock signal SCIMCLK continue to operate The periodic interrupt timer and input logic for the RESET and IRQ pins are clocked by SCIMCLK The SCIM2 can also continue to generate the CLKOUT signal while in low power stop mode During low power stop mode the address bus continues to drive the LPSTOP instruction and bus control signals are negated I O pins configured as outputs con tinue to hold their previous state l O pins configured as inputs will be in a three state condition STSCIM and STEXT bits in SYNCR determine clock operation during low power stop mode The flow chart shown in Figure 5 6 summarizes the effe
99. U U U U U U U U SCDR consists of two data registers located at the same address The receive data register RDR is a read only register that contains data received by the SCI serial interface Data comes into the receive serial shifter and is transferred to RDR The transmit data register TDR is a write only register that contains data to be transmitted Data is first written to TDR then transferred to the transmit serial shifter where additional format bits are added before transmission R 7 0 T 7 0 contain either the first eight data bits received when SCDR is read or the first eight data bits to be transmitted when SCDR is written R8 T8 are used when the SCI is configured for nine bit operation When the SCI is configured for 8 bit operation R8 T8 have no meaning or effect MOTOROLA MC68HC16R1 916R1 D 50 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 6 13 SPI Control Register SPCR SPI Control Register YFFC38 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPIE SPE WOMP MSTR CPOL LSBF SIZE SPBR 7 0 RESET 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 The SPCR contains parameters for configuring the SPI The register can be read or written at any time SPIE SPI Interrupt Enable 0 SPI interrupts disabled 1 SPI interrupts enabled SPE SPI Enable 0 SPI is disabled 1 is enabled WOMP Wired OR
100. UNASSIGNED RESERVED ed 5070000 sank7 0070 01FE 38 FF USER DEFINED INTERRUPTS BANK 7 070000 Y A 5080000 UNDEFINED Y FF700 UNDEFINED 080000 UNDEFINED ADC UNDEFINED YFF73F y SFUFFFF F7FFFF F80000 BANK 8 80000 Y FF820 ROM F90000 YFFO3F CONTROL BINGO ava qe Eo m NT F 90000 FA0000 j YFF900 SINC o va VER ure y FA0000 CTM7 0000 lawn 7 Y FFOFF 7 FB0000 512 KBYTE 00 FC0000 kp Sci S HN REED 0000 Y FFA7F 00000 SCO StS Y FFB00 BNK FD0000 CONTROL YFFB07 FE0000 Baku 17777777 AKU 77077 0000 5 BANK 14 BANK 14 T E E RETE MCCI ee FF0000 15 Y FFC3F BANK 15 0000 Y FEDEF INTERNAL REGISTERS Y FFFFFF Y Y FFFFFF NOTE 1 THE ADDRESSES DISPLA YED IN THIS MEMOR Y MAP ARE THE FULL 24 IMB ADDRESSES THE CPU16 ADDRESS B US IS 20 BITS WIDE AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES 23 20 THE BLOCK OF ADDRESSES FR OM 5080000 TO F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB MEMOR Y BANKS 0 TO 15 APPEAR FULL Y CONTIGUOUS IN THE 0165 FLA T 20 BIT ADDRESS SP ACE THE CPU16 NEED ONL Y GENERA TE A 20 BIT EFFECTIVE ADDRESS TO ACCESS ANY LOCA TION IN THIS RANGE 16R1 MEM MAP S Figure 3 9 MC68HC16R1 Separate Program and Data Space Map MOTOROLA OVERVIEW MC68HC16R1 916R1 3 22 For More Information On This Product USER S MANUAL Go to www freescal
101. VDDA V 7 Veer Differential Voltage Vnu VRL 4 5 5 5 V 8 Input Voltage ViNDC Vssa Vok V 9 Input High Port ADA Vin 0 7 Vppa 03 V 10 Input Low Port ADA Vi Vgsa_0 3 0 2 Vppa V Analog Supply Current 11 Normal Operation IDDA 1 0 mA Low power stop 200 uA 12 Reference Supply Current IREF 250 uA 13 Input Current Off Channel lorF 150 nA 14 Total Input Capacitance Not Sampling Cinn 10 pF 15 Total Input Capacitance Sampling Cins 15 pF NOTES 1 Refers to operation over full temperature and frequency range 2 To obtain full scale full range results Vssa lt Vn lt ViNpc lt Vnu lt 3 Accuracy tested and guaranteed at Vay Vg 5 0 V 5 4 Current measured at maximum system clock frequency with ADC active 5 Maximum leakage occurs at maximum operating temperature Current decreases by approximately one half for each 10 C decrease from maximum temperature Table A 12 ADC AC Characteristics Operating Vpp and Vpp4 5 0 5 Vss 0 T4 within operating temperature range Num Parameter Symbol Min Max Unit 1 ADC Clock Frequency fADCLK 0 5 2 1 MHz 8 bit Conversion Time 2 fADCLK 1 0 MHz tconv 15 2 us faDCLK 2 1 MHz 7 6 10 bit Conversion Time 3 fADCLK 1 0 MHz tconv 17 1 us fADCLK 2 1 MHz 8 6 4 Stop Recovery Time tsp 10 us NOTES 1 Conversion accuracy varies with
102. XK IX 2 YK IY INH 275C 2 TXZ Transfer X to Z XK IX ZK 12 INH 276C 2 TYKB Transfer YK to B YK 3 0 INH 37AD 2 0 B 7 4 TYS Transfer Y to SP YK IY 0002 2 SK SP INH 375E 2 TYX Transfer Y to X IY XK IX INH 274D 2 TYZ Transfer Y to Z IY 2 ZK IZ INH 276D 2 TZKB Transfer ZK to B ZK B 3 0 INH 37AE 2 0 B 7 4 TZS Transfer Z to SP ZK IZ 0002 2 SK SP INH 376E 2 TZX Transfer Z to X ZK IZ XK IX INH 274E 2 TZY Transfer Z to Y ZK 12 YK IY INH 275E 2 WAI Wait for Interrupt WAIT INH 27F3 8 XGAB Exchange A with B A lt gt 371A 2 XGDE Exchange D with E D E INH 277A 2 XGDX Exchange D with IX D INH 37CC 2 MOTOROLA MC68HC16R1 916R1 4 28 USER S MANUAL For More Information On This Product Go to www freescale com Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV 2 V C XGDY Exchange D with IY D e IY INH 37DC 2 XGDZ Exchange D with IZ D IZ INH 37EC 2 XGEX Exchange E with IX E IX INH 374C 2 XGEY Exchange E with IY E IY INH 375C 2 XGEZ Exchange E with IZ E IZ INH 376C 2 NOTES 1 CCR 15 4 change according to th
103. a master or slave device Clock con trol logic allows a selection of clock polarity and a choice of two clocking protocols to accommodate most available synchronous serial peripheral devices When the SPI is configured as a master software selects one of 254 different bit rates for the serial clock MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL For More Information On This Product 11 1 Go to www freescale com Freescale Semiconductor Inc The SCI is a universal asynchronous receiver transmitter UART serial interface with a standard non return to zero NRZ mark space format It operates in either full or half duplex mode it contains separate transmitter and receiver enable bits and a dou ble transmit buffer A modulus type baud rate generator provides rates from 64 baud to 524 kbaud with a 16 78 MHz system clock Word length of either 8 or 9 bits is soft ware selectable Optional parity generation and detection provide either even or odd parity check capability Advanced error detection circuitry catches glitches of up to 1 16 of a bit time in duration Wakeup functions allow the CPU to run uninterrupted until meaningful data is received 11 2 MCCI Registers and Address Map The MCCI address map occupies 64 bytes from address YFFCOO to YFFC3F It consists of MCCI global registers and SPI and SCI control status and data registers Writes to unimplemented register bits have no effect and reads of
104. be placed as close as possible to the Vppsvw to assure a stable operating frequency When an external system clock signal is applied and the PLL is disabled Vppsyn should be connected to the Vpp supply MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc A voltage controlled oscillator VCO in the PLL generates the system clock signal To maintain a 50 clock duty cycle the VCO frequency fyco is either two or four times the system clock frequency depending on the state of the X bit in SYNCR The clock signal is fed back to a divider counter The divider controls the frequency of one input to a phase comparator The other phase comparator input is a reference signal either from the crystal oscillator or from an external source The comparator generates a control signal proportional to the difference in phase between the two inputs This signal is low pass filtered and used to correct the VCO output frequency Filter circuit implementation can vary depending upon the external environment and required clock stability Figure 5 5 shows two recommended system clock filter networks XFC pin leakage must be kept as low as possible to maintain optimum sta bility and PLL performance NOTE The standard filter used in normal operating environments is a single 0 1 uf capacitor connected from the XFC pin to the Vpps
105. be relocated The CPU16 program counter stack pointer and Z index register can be initialized to any address in memory but exception vectors are limited to 16 bit addresses To access locations outside of bank 0 during exception handler routines including interrupt ex ceptions a jump table must be used Refer to SECTION 4 CENTRAL PROCESSOR UNIT for more information on extended addressing and exception processing Refer to SECTION 5 SINGLE CHIP INTEGRATION MODULE 2 for more information con cerning function codes address space types resets and interrupts MOTOROLA OVERVIEW MC68HC16R1 916R1 3 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc VECTOR VECTOR YPE OF ADDRESS NUMBER EXCEPTION 5000000 EI scr ano EXCEPTION 0000 0 RESET INITIAL ZK SK AND PK 5000000 VECTORS 0002 RESET INITIAL PC i 0004 RESET INITIAL SP 80000 ae RECT 000A 5 BERR BUS ERROR 000 6 SWI SOFTWARE INTERRUPT T EREMO KE 000E 7 ILLEGAL INSTRUCTION BANK 0010 8 DIVISION BY ZERO 0012 001C 9 UNASSIGNED RESERVED 001 F UNINITIALIZED INTERRUPT 5030000 gus 0020 10 UNASSIGNED RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 512 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR io SE See BoE zeig
106. bit fixed point numbers are used only by the MAC unit Bit 35 is the sign bit Bits 34 31 are sign extension bits There is an implied radix point between bits 31 and 30 There are 31 bits of magnitude but use of the extension bits allows representation of numbers in the range 16 800000000 to 15 999969482 7FFFFFFFF 4 5 Memory Organization Both program and data memory are divided into sixteen 64 Kbyte banks Addressing is linear A 20 bit extended address can access any byte location in the appropriate address space A word is composed of two consecutive bytes A word address is normally an even byte address Byte 0 of a word has a lower 16 bit address than byte 1 Long words and 32 bit signed fractions consist of two consecutive words and are normally accessed at the address of byte 0 in word 0 Instruction fetches always access word addresses Word operands are normally ac cessed at even byte addresses but can be accessed at odd byte addresses with a substantial performance penalty To permit compatibility with the M68HC11 misaligned word transfers and misaligned stack accesses are allowed Transferring a misaligned word requires two successive byte transfer operations Figure 4 3 shows how each CPU16 data type is organized in memory Consecutive even addresses show size and alignment MC68HC16R1 916R1 CENTRAL PROCESSOR UNIT MOTOROLA USER S MANUAL For More Information On This Product 4 7 Go to www freescale com
107. by setting PWMB to FFFF and PWMA to 0000 12 10 6 PWMSM Coherency Access to PWMSM registers can be accomplished with 16 bit transfers in most cases The PWMSM treats a 32 bit access as two 16 bit accesses except when the access is a write to the period and pulse width registers A single long word write can set both PWMA1 and PWMB1 because they occupy subsequent memory addresses If the write can be completed within the current PWM period there is no visible effect on the output signal New values loaded into PWMA1 and PWMB1 will be transferred into PWMA2 and PWMB2 at the start of the next period If the write coincides with the end of the current PWM period the transfer of values from PWMA1 and PWMB 1 into PWMA2 and PWMB2 will be suppressed until the end of the next period This prevents undesired glitches on the output signal During the period that is output before the sup pressed transfer completes the current values in PWMA2 PWMB2 are used 12 10 7 PWMSM Interrupts The FLAG bit in PWMSIC is set when a new PWM period begins and indicates that the period and pulse width registers PWMA1 and PWMB1 may be updated with new values for the next output period The PWMSM can optionally request an interrupt when FLAG is set To enable interrupts set the IL 2 0 field in PWMSIC to a non zero value The CTM7 compares the CPU16 IP mask value to the priority of the requested interrupt designated by IL 2 0 to determine whether it should c
108. can select which if any time base bus is to be driven by the 16 bit counter A software control register selects whether the clock input to the counter is one of the taps from the prescaler or an input pin The polarity of the external input pin is also programmable In order to count the FCSM requires the CPSM clock signals to be present After re set the FCSM does not count until the prescaler in the CPSM starts running when the software sets the PRUN bit This allows all counters in the CTM7 submodules to be synchronized The CTM7 has one FCSM Figure 12 3 shows a block diagram of the FCSM MC68HC16R1 916R1 CONFIGURABLE TIMER MODULE 7 MOTOROLA USER S MANUAL For More Information On This Product 12 5 Go to www freescale com Freescale Semiconductor Inc TBBA i I TIME BASE BUSES 1 6 CLOCKS 1 6 FROM PRESCALER SELECT TBBB lt lt DRVA DRVB CONTROL REGISTER BITS OVERFLOW CLOCK NTERRUPT SELECT gt gt 16 UP COUNTER CONTROL T inr IN cor u2 wo CONTROL REGISTER BITS CONTROL REGISTER BITS EDGE DETECT INPUT PIN CTM2C SUBMODULE BUS CTM FCSM BLOCK Figure 12 3 FCSM Block Diagram 12 6 1 FCSM Counter The FCSM counter consists of a 16 bit register and a 16 bit u
109. chip select function Block sizes of 2 Kbytes to 1 Mbyte can be selected by writing values to the appropriate base address register CSBAR 10 0 and CSBARBT However because the logic state of ADDR20 is al ways the same as the state of ADDR19 in the MCU the largest usable block size is 512 Kbytes Multiple chip selects assigned to the same block of addresses must have the same number of wait states Chip select option registers CSORBT CSOR 0 10 determine timing of and con ditions for assertion of chip select signals Eight parameters including operating mode access size synchronization and wait state insertion can be specified Initialization software usually resides in a peripheral memory device controlled by the chip select circuits A set of special chip select functions and registers CSORBT and CSBARBT is provided to support bootstrap operation Comprehensive address maps and register diagrams are provided in APPENDIX D REGISTER SUMMARY 5 9 1 1 Chip Select Pin Assignment Registers The pin assignment registers contain twelve 2 bit fields that determine the functions of the chip select pins Each pin has two or three possible functions as shown in Table 5 22 Table 5 22 Chip Select Pin Functions Chip Select Function Output CSBOOT CSBOOT CSO BR E CS1 BG 52 CS3 FCO PCO 54 1 1 55 2 2 56 ADDR19 PC3 57 ADDR20 PC4 CS8 ADDR2
110. close to the power pins as possible e The analog ground should be isolated from the digital ground This can be done by cutting a separate ground plane for the analog ground e Non minimum traces should be utilized for connecting bypass capacitors and filters to their corresponding ground power points e Minimum distance for trace runs when possible 10 8 4 Accommodating Positive Negative Stress Conditions Positive or negative stress refers to conditions which exceed nominally defined oper ating limits Examples include applying a voltage exceeding the normal limit on an in put for example voltages outside of the suggested supply reference ranges or causing currents into or out of the pin which exceed normal limits ADC specific con siderations are voltages greater than Vay or less than Vssa applied to an analog input which cause excessive currents into or out of the input Refer to APPENDIX ELECTRICAL CHARACTERISTICS on exact magnitudes Both stress conditions can potentially disrupt conversion results on neighboring inputs Parasitic devices associated with CMOS processes can cause an immediate disrup tive influence on neighboring pins Common examples of parasitic devices are diodes to substrate and bipolar devices with the base terminal tied to substrate Vss VssA ground Under stress conditions current introduced on an adjacent pin can cause er rors on adjacent channels by developing a voltage drop across the adjacen
111. control logic when low power stop mode is initiated LPSTOP can be terminated by a reset 5 5 External Bus Interface The external bus interface EBI transfers information between the internal MCU bus and external devices Figure 5 9 shows a basic system with external memory and peripherals MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 22 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Vpp Vpp Vpp Vpp Vpp Vpp A A A A A 10ko 1WkAS 10ko 10KES ADDR 3 0 ADDR 17 1 DATA 15 0 Vpp Kas 102 ADDR 15 1 DATA 15 8 ADDR 15 1 DATA T 0 NOTES 1 ALL CHIP SELECT LINES IN THIS EXAMPLE MUST BE CONFIGURED AS 16 BIT Figure 5 9 MCU Basic System MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 USER S MANUAL For More Information On This Product Go to www freescale com MC68HC681 ASYNC BUS PERIPHERAL HC16 SIM SCIM BUS MOTOROLA 5 23 Freescale Semiconductor Inc The external bus has 24 address lines and 16 data lines ADDR 19 0 are normal ad dress outputs ADDR 23 20 follow the output state of ADDR19 The EBI provides dynamic sizing between 8 bit and 16 bit data accesses It supports byte word and long word transfers Port width is the maximum number of bits accepted or provided by the external memory system during a bus transfer Widths o
112. dress function code size and read write signals are again driven to their previous states The MCU does not service interrupt requests while it is halted Refer to 5 6 5 Bus Exception Control Cycles for further information 5 5 1 11 Autovector Signal The autovector signal AVEC can be used to terminate external interrupt acknowl edgement cycles Assertion of AVEC causes the CPU16 to generate vector numbers to locate an interrupt handler routine If AVEC is continuously asserted autovectors are generated for all external interrupt requests AVEC is ignored during all other bus cycles Refer to 5 8 Interrupts for more information AVEC for external interrupt requests can also be supplied internally by chip select logic Refer to 5 9 Chip Se lects for more information The autovector function is disabled when there is an external bus master Refer to 5 6 6 External Bus Arbitration for more information 5 5 2 Dynamic Bus Sizing The MCU dynamically interprets the port size of an addressed device during each bus cycle allowing operand transfers to or from 8 bit and 16 bit ports During a a bus transfer cycle an external device signals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK inputs as shown in Table 5 11 Chip select logic can generate data size acknowledge signals for an external device Refer to 5 9 Chip Selects for more information MOTOROLA SINGLE CHIP INT
113. during mask programming but field val ue can be changed after reset if the LOCK bit in the MRMCR has not been masked to a value of one Table 7 1 shows ASPC 1 0 field encodings Table 7 1 ROM Array Space Field ASPC 1 0 State Specified Program and data accesses X1 Program access only Refer to 4 6 Addressing Modes for more information on addressing modes Refer to 5 5 1 7 Function Codes for more information concerning address space types and program data space access 7 4 Normal Access The array can be accessed by byte word or long word A byte or aligned word access takes one bus cycle or two system clocks A long word or misaligned word access re quires two bus cycles Refer to 5 6 Bus Operation for more information concerning access times Access time can be optimized for a particular application by inserting wait states into each access The number of wait states inserted is determined by the value of WAIT 1 0 in the MRMCR Two three four or five bus cycle accesses can be speci fied The default value WAIT 1 0 is established during mask programming but field value can be changed after reset if the LOCK bit in the MRMCR has not been masked to a value of one Table 7 2 shows WAIT 1 0 field encodings MOTOROLA MASKED ROM MODULE MC68HC16R1 916R1 7 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 7 2 Wait States Field
114. good high frequency characteristics This capac itor has two effects First it helps attenuate any noise that may exist on the input Second it sources charge during the sample period when the analog signal source is a high impedance source Series resistance can be used with the capacitor on an input pin to implement a simple RC filter The maximum level of filtering at the input pins is application dependent and is based on the bandpass characteristics required to accurately track the dynamic characteristics of an input Simple RC filtering at the pin may be limited by the source impedance of the transducer or circuit supplying the analog signal to be measured Refer to 10 8 6 2 Error Resulting from Leakage In some cases the size of the ca pacitor at the pin may be very small Figure 10 10 is a simplified model of an input channel Refer to this model in the fol lowing discussion of the interaction between the user s external circuitry and the cir cuitry inside the ADC EXTERNAL CIRCUIT INTERNAL CIRCUIT MODEL 51 RF 52 53 54 Yee Ye o yer 2 Vsnc Cr Cs Conc Vi Vsnc SOURCE VOLTAGE FILTER IMPEDANCE SOURCE IMPEDANCE INCLUDED FILTER CAPACITOR Cs INTERNAL CAPACITANCE FOR A BYPASSED CHANNEL THIS 15 THE CAPACITANCE CpAC CAPACITOR ARRAY Vj INTERNAL VOLTAGE SOURCE FOR PRECHARGE 2 ADC SAMPLE AMP MODEL Figure 10 10 Electrical Model of an A D Input Pin MOTOROLA ANALOG T
115. in SPCR1 Clearing a bit in MPAR assigns the corresponding to general purpose I O setting a bit assigns the pin to the SPI Refer to Table D 32 Table D 32 MPAR Pin Assignments MPAR Field MPAR Bit Pin Function 0 PMCO MISO 1 x PMC1 MOSI PMC2 SCK PMC3 55 PMC4 RXDB PMC5 TXDB PMC6 RXDA PMC7 TXDA NOTES 1 MPA 7 4 MPA2 are not implemented Bits 15 8 7 4 2 Not Implemented MOTOROLA D 44 For More Information On This Product Go to www freescale com MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc SPI pins designated by the MPAR as general purpose I O are controlled only by MDDR and PORTMC The SPI has no effect on these pins The MPAR does not affect the operation of the SCI submodule D 6 7 MCCI Data Direction Register MDDR MCCI Data Direction Register YFFCOA 15 8 7 6 5 4 3 2 1 0 NOT USED DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDRO RESET 0 0 0 0 0 0 0 0 MDDR determines whether pins configured for general purpose I O are inputs or outputs MDDR affects both SPI function and I O function During reset all MCCI pins are configured as inputs Table D 33 shows the effect of MDDR on MCCI pin function Table D 33 Effect of MDDR on MCCI Pin Function MCCI Pin Mode MDDR Bit Bit State Pin Function MISO Master DDRO 0 Serial data
116. involved in fetching decod ing and executing instructions These are the microsequencer the instruction pipe line and the execution unit These elements function concurrently All three may be active at any given time MOTOROLA MC68HC16R1 916R1 4 34 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc IPIPEO IPIPE1 MICROSEQUENCER INSTRUCTION PIPELINE DATA 1 A Y EXECUTION UNIT 16 EXEC UNIT MODEL Figure 4 5 Instruction Execution Model 4 10 1 Microsequencer The microsequencer controls the order in which instructions are fetched advanced through the pipeline and executed It increments the program counter and generates multiplexed external tracking signals IPIPEO and IPIPE1 from internal signals that con trol execution sequence 4 10 2 Instruction Pipeline The pipeline is a three stage FIFO that holds instructions while they are decoded and executed Depending upon instruction size as many as three instructions can be in the pipeline at one time single word instructions one held in stage C one being exe cuted in stage B and one latched in stage A 4 10 3 Execution Unit The execution unit evaluates opcodes interfaces with the microsequencer to advance instructions through the pipeline and performs instruction operations MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Informat
117. is comprised of a set of modules connected by the intermodule bus IMB The full IMB has a 16 bit data bus a 24 bit address bus and three function code lines and ideally provides eight distinct memory maps each with 16 megabytes of address space In practice only four of these memory maps are available for user code and data Three are inaccessible because the function codes lines are never driven to states that allow them to be decoded and one is devoted ex clusively to control information not associated with normal read and write bus cycles The total amount of addressable memory is further limited on the CPU16 While the CPU32 can operate in both the user and supervisor modes denoted by the function code lines the CPU16 operates only in supervisor mode Excluding the CPU space memory map used for special bus cycles the CPU16 can access only the supervisor program space and supervisor data space memory maps The CPU16 also has only 20 address lines This limits the total address space in each of the two memory maps to one megabyte Although the CPU16 has only 20 addresses lines it still drives all 24 IMB address lines IMB address lines 19 0 follow CPU address lines 19 0 and IMB address lines 23 20 follow the state of CPU address line 19 as shown in Figure 3 5 This causes an address space discontinuity to appear on the IMB when the CPU16 address bus rolls over from 7FFFF to 80000 CPU ADDRO TT IMB ADDRO CPUADDR1
118. not apply to Port MCCI 7 0 TXDA TXDB PMC 3 0 in wired OR mode 7 Applies to Group 1 2 4 input output and all output pins 8 Applies to Group 1 2 3 4 input output pins BG CS CLKOUT CSBOOT FREEZE QUOT and IPIPEO 9 Applies to DATA 15 0 10 Use of an active pulldown device is recommended 11 Total operating current is the sum of the appropriate Ipp Ippsyn Isp and Ippa 12 Current measured at maximum system clock frequency all modules active 13 The MC68HC16R1 916R1 can be ordered with either a a 32 768 kHz crystal reference or a 4 194 MHz crystal reference as a mask option 14 The RAM module will not switch into standby mode as long as does not exceed Vpp by more than 0 5 volts The RAM array cannot be accessed while the module is in standby mode 15 When is more than 0 3 V greater than Vpp current flows between the and Vpp pins which causes standby current to increase toward the maximum transient condition specification System noise on the Vpp and pin can contribute to this condition 16 Power dissipation measured with system clock frequency of 16 78 MHz all modules active Power dissipation can be calculated using the following expression Pp Maximum Vpp 1 IDDSYN Isp Maximum VppA Ippa includes supply currents for all device modules powered by Vpp pins MOTOROLA ELECTRICAL CHARACTERISTICS MC68HC16R1 916R1 A 6 For More Information On Th
119. pin function options for 16 bit data bus operation Table 5 17 16 Bit Expanded Mode Reset Configuration Default Function Alternate Function Pin s Affected Select Pin Pin Held High Pin Held Low CSBOOT DATAO CSBOOT 16 Bit CSBOOT 8 Bit BR CSO CS0 BR FCO CSS3 CS3 FCO FC1 PC1 1 1 FC2 CS5 PC2 55 2 ADDR19 CS6 PC3 DATA3 CS6 ADDR19 ADDR20 CS7 PC4 DATA4 CS 7 6 ADDR 20 19 ADDR21 CS8 PC5 DATA5 CS 8 6 ADDR 21 19 ADDR22 CS9 PC6 DATA6 CS 9 6 ADDR 22 19 ADDR23 CS10 ECLK DATA7 CS 10 6 ADDR 23 19 DSACKO PEO DSACKO ies DSACK1 PE1 DSACK1 PED AVEC PE2 AVEC PE3 PE3 PES DS PE4 Dee DS AS PE5 AS PEG SIZ0 PE6 5170 7 SIZ1 PE7 6171 FASTREF PFO FASTREF PFO IRQ 7 1 PF 7 1 DATAS IRQ 7 1 PF 7 1 BGACK CSE BGACK CSE BG CSM PATA BG CSM Reserved DATA11 Normal Operation Reserved Emulation Mode SCIM2 DATA10 Disabled Enabled STOP Mode BEFLASH DATA12 Array Enabled Array Disabled STOP Mode MRM DATA14 Array Enabled Array Disabled STOP Mode 16K and 32K 6 Flash EEPROM Modules DATA14 Array Enabled Array Disabled NOTES 1 CSE is enabled when DATA10 DATA1 0 during reset 2 CSM is enabled when DATA13 DATA10 and DATA1 0 during reset 3 DATA11 must remain high during reset to ensure normal operation of MCU 4 Driven to put BEFLASH in STOP mode STOP mode disabled when DATA12 is held high and STOP shadow bit is cleared MC68HC916R1 only 5
120. programmed these registers can be written after reset to change the default array address if the base address lock bit LOCK in MRMCR is not masked to a value of one The MRM array can be mapped to any 48 Kbyte boundary in the memory map but must not overlap other module control registers overlap makes the registers inacces sible If the array overlaps the MRM register block addresses in the block are access ed instead of the corresponding array addresses ROMBAH and ROMBAL can only be written while the ROM is in low power stop mode MRMCR STOP 1 and the base address lock MRMCR LOCK 0 is disabled MC68HC16R1 916R1 MASKED ROM MODULE MOTOROLA USER S MANUAL For More Information On This Product 7 1 Go to www freescale com Freescale Semiconductor Inc LOCK can be written once only to a value of one This prevents accidental remapping of the array 7 3 MRM Array Address Space Type ASPC 1 0 in MRMCR determines ROM array address space type The module can respond to both program and data space accesses or to program space accesses only This allows code to be executed from ROM and permits use of program counter relative addressing mode for operand fetches from the array In addition ASPC 1 0 specify whether access to the MRM can be made in supervisor mode only or in either user or Supervisor mode Because the CPU16 operates in su pervisor mode only ASPC1 has no effect The default value of ASPC 1 0 is established
121. s function code outputs When this technique is used instruction fetches and reset vector fetches access program space while exception vector fetches other than for reset data accesses and stack accesses are made in data space MC68HC16R1 916R1 CENTRAL PROCESSOR UNIT MOTOROLA USER S MANUAL For More Information On This Product 4 5 Go to www freescale com Freescale Semiconductor Inc 4 3 1 Address Extension All CPU16 resources used to generate addresses are effectively 20 bits wide These resources include the index registers program counter and stack pointer All address ing modes use 20 bit addresses Twenty bit addresses are formed from a 16 bit byte address generated by an individ ual CPU16 register and a 4 bit address extension contained in an associated exten sion field The byte address corresponds to ADDR 15 0 and the address extension corresponds to ADDR 19 16 4 3 2 Extension Fields Each of the six address extension fields is used for a different type of access All but EK are associated with particular CPU16 registers There are several ways to manip ulate extension fields and the address map Refer to the CPU16 Reference Manual CPU16RM AD for detailed information 4 4 Data Types The CPU16 uses the following types of data Bits 4 bit signed integers 8 bit byte signed and unsigned integers 8 bit 2 digit binary coded decimal BCD numbers 16 bit word signed and unsigned integers
122. select functions and only eight associated data bus pins There is not a one to one correspondence Refer to 5 9 4 Chip Select Reset Operation for more detailed information The CSBOOT signal is enabled out of reset The state of the DATAO line during reset determines what port width CSBOOT uses If DATAO is held high either by the weak internal pull up driver or by an external pull up device 16 bit port size is selected If DATAO is held low 8 bit port size is selected A pin programmed as a discrete output drives an external signal to the value specified in the Port C register No discrete output function is available on pins CSBOOT BR BG or BGACK ADDR23 provides the ECLK output rather than a discrete output sig nal When a pin is programmed for discrete output or alternate function internal chip select logic still functions and can be used to generate DSACK or AVEC internally on an ad dress and control signal match 5 9 1 2 Chip Select Base Address Registers Each chip select has an associated base address register A base address is the low est address in the block of addresses enabled by a chip select Block size is the extent of the address block above the base address Block size is determined by the value contained in BLKSZ 2 0 Multiple chip selects assigned to the same block of addresses must have the same number of wait states BLKSZ 2 0 determines which bits in the base address field are compared to corre sp
123. stores the results of comparison in the successive approxi mation register then transfers results to the result registers 10 7 1 Control Status Registers There are two control registers ADCTLO ADCTL1 and one status register ADSTAT ADCTLO controls conversion resolution sample time and clock prescaler value ADCTL1 controls analog input selection conversion mode and initiation of conversion A write to ADCTLO aborts the current conversion sequence and halts the ADC Conversion must be restarted by writing to ADCTL1 A write to ADCTL1 aborts the current conversion sequence and starts a new sequence with parameters altered by the write ADSTAT shows conversion sequence status conversion channel status and conversion completion status The following paragraphs are a general discussion of control function D 5 Analog to Digital Converter Module shows the ADC address map and discusses register bits and fields 10 7 2 Clock and Prescaler Control The ADC clock is derived from the system clock by a programmable prescaler ADC clock period is determined by the value of the PRS field in ADCTLO The prescaler has two stages The first stage is a 5 bit modulus counter It divides the system clock by any value from 2 to 32 PRS 4 0 00001 to 11111 The second stage is a divide by two circuit Table 10 3 shows prescaler output values MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC16R1 916R1 10 6 For More Information On This Product USE
124. the associated chip select and all lower numbered chip selects down through CS6 For example if DATAS is pulled low during reset CS 8 6 are configured as address bus signals ADDR 21 19 and CS 10 9 are configured as chip selects On MC68HC16R1 916 MCUs ADDR 23 20 follow the state of ADDR19 and DATA 7 4 have limited use Refer to 5 9 4 Chip Select Reset Operation for more information DATAS determines the function of the DSACK 1 0 AVEC DS AS and SIZ 1 0 pins If DATAS is held low during reset these pins are used for discrete I O port E DATA9 determines the function of interrupt request pins IRQ 7 0 and the clock mode select pin MODCLK When DATA9 is held low during reset these pins are used for discrete I O port F DATA11 determines whether the SCIM2 operates in test mode out of reset This capability is used for factory testing of the MCU MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 46 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc DATAO determines the port size of the boot ROM chip select signal CSBOOT Unlike other chip select signals CSBOOT is active at the release of reset When DATAO is held low port size is 8 bits when DATAO is held high either by the weak internal pull up driver or by an external pull up port size is 16 bits Refer to 5 9 4 Chip Select Re set Operation for more information Table 5 17 summarizes
125. timing When fast termination is in use DS is asserted during read cycles but not during write cycles The STRB field in the chip select option register used must be programmed with the address strobe encoding to assert the chip select signal for a fast termination write 5 6 4 CPU Space Cycles Function code signals FC 2 0 designate which of eight external address spaces is ac cessed during a bus cycle Address space 7 is designated CPU space CPU space is used for control information not normally associated with read or write bus cycles Function codes are valid only while AS is asserted Refer to 5 5 1 7 Function Codes for more information on codes and encoding MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 33 to www freescale com Freescale Semiconductor Inc During a CPU space access ADDR 19 16 are encoded to reflect the type of access being made Three encodings are used by the MCU as shown in Figure 5 13 These encodings represent breakpoint acknowledge Type 0 cycles low power stop broadcast Type 3 cycles and interrupt acknowledge Type F cycles Type 0 and type 3 cycles are discussed in the following paragraphs Refer to 5 8 Interrupts for information about interrupt acknowledge bus cycles CPU SPACE CYCLES FUNCTION ADDRESS BUS CODE 2 0 23 16 4 210 BREAKPOINT ACKNOWLEDGE ferfe 2 0 23 P
126. unimplemented bits always return zero The MM bit in the single chip integration module 2 configuration register SCIM2CHR defines the most significant bit ADDR23 of the IMB address for each module Because ADDR 23 20 are driven to the same bit as ADDR19 MM must be set to one If MM is cleared IMB modules are inaccessible Refer to 5 2 1 Module Mapping for more information about how the state of MM affects the system 11 2 1 MCCI Global Registers The MCCI module configuration register MMCR contains bits and fields to place the MCCI in low power operation establish the privilege level required to access MCCI registers and establish the priority of the MCCI during interrupt arbitration The MCCI test register MTEST is used only during factory test of the MCCI The SCI interrupt level register ILSCI determines the level of interrupts requested by each SCI Separate fields hold the interrupt request levels for SCIA and SCIB The MCCI interrupt vector register MIVR determines which three vectors in the exception vector table are to be used for MCCI interrupts The SPI and both SCI interfaces have separate interrupt vectors adjacent to one another The SPI interrupt level register ILSPI determines the priority level of interrupts requested by the SPI The MCCI port data registers PORTMC PORTMCP are used to configure port MCCI for general purpose I O The MCCI pin assignment register MPAR determines which of the SPI pins with the e
127. until the BYTE 1 0 field in the corresponding option register is programmed to a non zero val ue to select a transfer size The chip select option register must not be written until a base address has been written to a proper base address register Alternate functions for chip select pins are enabled if appropriate data bus pins are held low at the release of RESET Refer to 5 7 3 2 Data Bus Mode Selection for more information Figure 5 21 is a functional diagram of a single chip select circuit INTERNAL SIGNALS ADDRESS ADDRESS COMPARATOR gt TIMING AND CONTROL BASE ADDRESS REGISTER BUS CONTROL OPTION COMPARE OPTION REGISTER PIN ASSIGNMENT REGISTER PIN DATA REGISTER AVEC DSACK GENERATOR GENERATOR Figure 5 21 Chip Select Circuit Block Diagram AVEC DSACK lt CHIP SEL BLOCK MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 62 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 9 1 Chip Select Registers Each chip select pin can have one or more functions Chip select pin assignment reg isters CSPAR 1 0 determine functions of the pins Pin assignment registers also de termine port size 8 or 16 bit for dynamic bus allocation A pin data register PORTC latches data for chip select pins that are used for discrete output Blocks of addresses are assigned to each
128. verify access privileges All control block ad dresses must be in supervisor data space Array accesses are defined by the state of ASPC 1 0 in FEEXMCR Access time is governed by the WAIT 1 0 field in FEEXMCR Accesses to any address in the address block defined by and FEExBAL which does not fall within the array are ignored allowing external devices to adjoin flash EEPROM arrays which do not entirely fill the entire address space specified by FEExBAH and FEExBAL 8 3 4 Program Erase Operation An erased flash bit has a logic state of one A bit must be programmed to change its state from one to zero Erasing a bit returns it to a logic state of one Programming and erasing the flash module requires a series of control register writes and a write to an array address The same procedure is used to program control registers that contain flash shadow bits Programming is restricted to a single byte or aligned word at a time The entire array and the shadow register bits are erased at the same time When multiple flash modules share a single Vepg pin do not program or erase more than one flash module at a time Normal accesses to modules that are not being pro grammed are not affected by programming or erasure of another flash module The following paragraphs give step by step procedures for programming and erasure of flash EEPROM arrays Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for information on programming and erasing sp
129. written when STOP 1 and LOCK 0 This prevents accidental remapping of the array Because the 8 Kbyte ROM array in the MC68HC16R1 916R1 must be mapped to an 8 Kbyte boundary ROMBAL bits 12 0 always contain 0000 ROMBAH ADDR 15 8 read zero D 4 3 ROM Signature Registers RSIGHI ROM Signature High Register YFF828 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED RSP18 RSP17 RSP16 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSIGLO ROM Signature Low Register YFF82A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSP15 RSP14 RSP13 RSP12 5 11 RSP10 RSP9 RSP8 RSP7 RSP6 RSP5 RSP4 RSP3 RSP2 RSP1 RSPO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSIGHI and RSIGLO specify a ROM signature pattern A user written signature iden tification algorithm allows identification of the ROM array content The signature is specified at mask time and cannot be changed MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 30 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 4 4 ROM Bootstrap Words 50 ROM Bootstrap Word 0 YFF830 15 14 13 12 11 10 9 8 7 6 5 2 1 0 NOT USED ZK 3 0 SK 3 0 PK 3 0 ROMBS1 ROM Bootstrap Word 1 YFF832 15 14 13 12 11 10 9 8 7 6 5 2 1 0 15 0 ROMBS2 ROM Bootstrap Word 2 YFF834 15 14 13 12 11 10 9 8 7 6 5 2 1 0 SP
130. 00 SCIA 01 SCIB 10 SPI Writes to INTVO and INTV1 have no meaning or effect Reads of INTVO and INTV1 return a value of one D 6 5 SPI Interrupt Level Register ILSPI SPI Interrupt Level Register YFFCO6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 5 102 0 0 0 0 NOT USED 0 0 0 0 0 0 0 0 The ILSPI determines the priority level of interrupts requested by the SPI Bits 15 14 Not Implemented MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product D 43 Go to www freescale com Freescale Semiconductor Inc ILSPI 2 0 Interrupt Level for SPI ILSPI 2 0 determine the interrupt request levels of SPI interrupts Program this field to a value from 0 interrupts disabled through 7 highest priority If the interrupt request level programmed in this field matches the interrupt request level programmed for one of the SCI interfaces and both request an interrupt simultaneous ly the SPI is given priority Bits 10 8 Not Implemented D 6 6 MCCI Pin Assignment Register MPAR MCCI Pin Assignment Register YFFCO8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT NOT USED MPA3 USED 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 The MPAR determines which of the SPI pins with the exception of the SCK pin are actually used by the SPI submodule and which pins are available for general purpose The state of SCK is determined by the SPI enable bit
131. 1 0 is set to 00 CPU space interrupt priority ADDR 3 1 is compared to the IPL field If the values are the same and other option register constraints are satisfied a chip select signal is asserted This field only affects the response of chip selects and does not affect in terrupt recognition by the CPU Encoding 96000 in the IPL field causes a chip select signal to be asserted regardless of interrupt acknowledge cycle priority provided all other constraints are met The AVEC bit is used to make a chip select respond to an interrupt acknowledge cycle If the AVEC bit is set an autovector will be selected for the particular external interrupt being serviced If AVEC is zero the interrupt acknowledge cycle will be ter minated with DSACK and an external vector number must be supplied by an external device 5 9 1 4 PORTC Data Register The PORTO data register latches data for PORTC pins programmed as discrete out puts When a pin is assigned as a discrete output the value in this register appears at the output PC 6 0 correspond to CS 9 3 Bit 7 is not used Writing to this bit has no effect and it always reads zero MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 66 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 9 2 Chip Select Operation When the MCU makes an access enabled chip select circuits compare the following items Fu
132. 1 6 11 3 1 2 SPI Status Register SPSR 11 6 11 3 1 3 SPI Data Register SPDR 11 6 11 3 2 sibus e 11 6 11 3 3 SPI Operating MOGGS aesti eere esencia id onde ne 11 7 11 3 3 1 Master Mode u rro RERO EHE Dr HRS 11 7 11 3 3 2 Slave ModE ua De eka bein 11 8 11 3 4 SPI Clock Phase and Polarity Controls 11 8 11 3 4 1 CPHA 0 Transfer Format uuu uuu 11 9 11 3 4 2 1 Transfer Format 11 10 11 3 5 SPI Serial Glock Baud Rate 11 11 11 3 6 Wired OR Open Drain Outputs 11 11 11 3 7 Transfer Size and Direction 11 11 11 3 8 Write Collision y a S odo 11 12 11 3 9 uu aaa E 11 12 11 4 Serial Communication Interface 11 13 11 4 1 slept EID 11 13 11 4 1 1 SCI Control Registers 11 13 11 4 1 2 SCI Status Register 11 16 11 4 1 3 SCI Data Register 11 16 11 4 2 Siem 11 16
133. 1 PC5 59 ADDR22 PC6 510 ADDR23 ECLK Table 5 23 shows pin assignment field encoding Pins that have no discrete output function must not use the 00 encoding as this will cause the alternate function to be selected For instance 00 for CSO BR will cause the pin to perform the BR function MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 63 Go to www freescale com Freescale Semiconductor Inc Table 5 23 Pin Assignment Field Encoding CSxPA 1 0 Description 00 Discrete output 01 Alternate function 10 Chip select 8 bit port 11 Chip select 16 bit port Port size determines the way in which bus transfers to an external address are allo cated Port size of eight bits or sixteen bits can be selected when a pin is assigned as a chip select Port size and transfer size affect how the chip select signal is asserted Refer to 5 9 1 3 Chip Select Option Registers for more information Out of reset chip select pin function is determined by the logic level on a correspond ing data bus pin The data bus pins have weak internal pull up drivers but can be held low by external devices Refer to 5 7 3 2 Data Bus Mode Selection for more informa tion Either 16 bit chip select function 9611 or alternate function 9601 can be select ed during reset All pins except the boot ROM select pin CSBOOT are disabled out of reset There are twelve chip
134. 1 count 2 counts 20 counts MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC16R1 916R1 10 24 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 11 MULTICHANNEL COMMUNICATION INTERFACE This section is an overview of the multichannel communication interface MCCI module Refer to the MCCI Reference Manual MCCIRM AD for more information on MCCI capabilities Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for MCCI timing and electrical specifications Refer to D 6 Multichannel Communication Interface Module for register address mapping and bit field definitions 11 1 General The MCCI contains three serial interfaces a serial peripheral interface SPI and two serial communication interfaces SCI Figure 11 1 is a block diagram of the MCCI INTERMODULE BUS IMB BUS INTERFACE UNIT ae SERIAL PERIPHERAL INTERFACE SPI gt PMCIMOSI c 4 MEREK E al eu PORT PMC4 RXDB SERIAL COMMUNICATION INTERFACE SCIB ACER OE E PMC6 RXDA SERIAL COMMUNICATION INTERFACE SCIA PMCTITXDA MCCI BLOCK Figure 11 1 MCCI Block Diagram The SPI provides easy peripheral expansion or interprocessor communication via a full duplex synchronous three line bus data in data out and a serial clock Serial transfer of 8 or 16 bits can begin with the most significant bit MSB or least significant bit LSB The MCCI module can be configured as
135. 10 effectively corresponds to 1 wait states MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 22 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table D 15 DSACK Field Encoding 0000 3 9 0001 4 1 0010 5 2 0011 6 3 0100 7 4 0101 8 0110 9 i 0111 10 1000 11 B 1001 12 9 1010 13 10 1011 14 11 1100 15 1101 16 19 1110 2 1 Fast termination 1111 External DSACK SPACE 1 0 Address Space Select Use this option field to select an address space for chip select assertion or to configure a chip select as an interrupt acknowledge strobe for an external device The CPU16 normally operates in supervisor mode only but interrupt acknowledge cycles take place in CPU space Table D 16 shows address space bit encodings Table D 16 Address Space Bit Encodings SPACE 1 0 Address Space 00 CPU Space 01 User Space 10 Supervisor Space 11 Supervisor User Space IPL 2 0 Interrupt Priority Level When SPACE 1 0 is set for CPU space 9600 chip select logic can be used as interrupt acknowledge strobe for an external device During an interrupt acknowledge cycle the interrupt priority level is driven on address lines ADDR 3 1 is then compared to the value in IPL 2 0 If the values match an interrupt acknowledge strobe will be generated on the particul
136. 10 8 6 2 Error Resulting from Leakage A series resistor limits the current to a pin therefore input leakage acting through a large source impedance can degrade A D accuracy The maximum input leakage cur rent is specified in APPENDIX A ELECTRICAL CHARACTERISTICS Input leakage is greatest at high operating temperatures and as a general rule decreases by one half for each 10 C decrease in temperature Assuming Vay Vg 5 12 V 1 count assuming 10 bit resolution corresponds to 5 mV of input voltage A typical input leakage of 50 nA acting through 100 kQ of external series resistance results in an error of less than 1 count 5 0 mV If the source imped ance is 1 MO and a typical leakage of 50 nA is present an error of 10 counts 50 mV is introduced In addition to internal junction leakage external leakage e g if external clamping di odes are used and charge sharing effects with internal capacitors also contribute to the total leakage current Table 10 11 illustrates the effect of different levels of total leakage on accuracy for different values of source impedance The error is listed in terms of 10 bit counts CAUTION Leakage from the part of 10 nA is obtainable only within a limited temperature range Table 10 11 Error Resulting From Input Leakage IOFF Source Leakage Value 10 Bit Conversions Impedance 10 nA 50 nA 100 nA 1000 nA 1 kO 0 2 counts 10 KQ 0 1 counts 0 2 counts 2 counts 100 kQ 0 2 counts
137. 111 6291 12583 25166 50332 110000 6423 12845 25690 51380 110001 6554 13107 26214 52428 110010 6685 13369 26739 53477 110011 6816 13631 27263 54526 110100 6947 13894 27787 55575 110101 7078 14156 28312 56623 110110 7209 14418 28836 57672 110111 7340 14680 29360 58720 111000 7471 14942 2988 59769 111001 7602 15204 30409 60817 111010 7733 15466 30933 61866 111011 7864 15729 31457 62915 111100 7995 15991 31982 63963 111101 8126 16253 32506 65011 111110 8258 16515 33030 66060 111111 8389 16777 33554 67109 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA MC68HC16R1 916R1 USER S MANUAL For More Information On This Product Go to www freescale com 5 13 Freescale Semiconductor Inc 5 3 3 External Bus Clock The state of the E clock division bit EDIV in SYNCR determines clock rate for the E clock signal ECLK available on pin ADDR23 ECLK is a bus clock for MC6800 devices and peripherals ECLK frequency can be set to system clock frequency divided by eight or system clock frequency divided by sixteen The clock is enabled by the CS10PA 1 0 field chip select pin assignment register 1 CSPAR1 operation during low power stop is described in the following paragraph Refer to 5 9 Chip Selects for more information about the external bus clock 5 3 4 Low Power Operation Low power operation is initiated by the CPU16 To reduce power consumption selec tively the CPU can set the STOP bits in each module configuration register
138. 112 0 0 SCIM2 Rr M add input or chip select out _ CLKOUT 65 SCIM2 System clock output MOTOROLA OVERVIEW MC68HC16R1 916R1 3 12 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 3 3 MC68HC16R1 MC68HC916R1 Pin Functions Pin Pin Active Associated Discrete Mnemonic s Number s State s Module Description Use Pulse width modulation submodule CPWM18 126 an 1 CPWM19 125 CTM7 PWMSWM outputs or digital output O ports CSBOOT 111 0 SCIM2 E memory device chip select out u CTD4 11 Bidirectional double action submod CTM7 DASM timer pins or digital I O 10 CTD5 10 ports Free running counter submodule m FCSM and modulus counter sub 1 CIM Te SIME module MCSM external clock input or digital input port CTS6A 9 CTS6B 8 CTS8A 7 CTS8B 6 ra A x Bidirectional single action submod CTS12A 3 CTM7 D EAE timer pins or digital I O CTS12B 2 poner CTS14A 1 CTS14B 129 CTS16A 128 CTS16B 127 DATAO PHO 110 DATA1 PH1 109 DATA2 PH2 108 DATA3 PH3 107 ed Data bus lines 7 0 or digital I O port DATA4 PH4 106 pote H 7 0 VO DATA5 PH5 105 DATA6 PH6 104 DATA7 PH7 103 DATA8 PGO 102 DATA9 PG1 101 DATA10 PG2 99 DATA11 PG3 98 Data bus lines 15 8 or digital I O DATA12 PG4 97 i SCIM2 port G 7 0 us DATA13 PG5 96 DATA14 PG6 95 DATA15 PG7 94 Indicates that an external device
139. 16 X 3747 0099 6 IND16 Y 3757 999g 6 IND16 Z 3767 999g 6 EXT 3777 hh Il 6 ORP OR Condition Code CCR IMM16 CCR IMM16 373B jj kk 4 A A A AJA A A A Register PSHA Push A SK SP 0001 SK SP INH 3708 4 SK SP 0002 2 SK SP PSHB Push B SK SP 0001 SK SP INH 3718 4 Push B SK SP 0002 2 SK SP PSHM Push Multiple For mask bits O to 7 IMM8 34 ii 4 2 Registers If mask bit set Mask bits Push register N 0 D SK SP 2 gt SK SP numberof 1 registers 2 1X pushed 3 1 4 12 5 K 6 CCR 7 Reserved PSHMAC Push MAC Registers MAC Registers Stack INH 27B8 14 PULA Pull A SK SP 0002 2 SK SP INH 3709 6 Pull A SK SP 0001 gt SK SP Pull B SK SP 0001 2 SK SP MC68HC16R1 916R1 MOTOROLA USER S MANUAL 4 23 Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles 5 2 V C PULM Pull Multiple Registers For mask bits 0 to 7 IMM8 35 ii 4 2 N 1 A A A AJA A A A Mask bits If mask bit set N 0 CCR 15 4 SK SP 2 SK SP numberof 1 K Pull register re
140. 16 bit relative 4 bit address extension 8 bit unsigned offset 16 bit signed offset High byte of 16 bit extended address 8 bit immediate data High byte of 16 bit immediate data Low byte of 16 bit immediate data Low byte of 16 bit extended address 8 bit mask 16 bit mask 8 bit unsigned relative offset 16 bit signed relative offset MAC index register X offset MAC index register Y offset 4 bit zero extension AND Inclusive OR OR Exclusive OR EOR Complementation Concatenation Transferred Exchanged Sign bit also used to show tolerance Sign extension Binary value Hexadecimal value MC68HC16R1 916R1 USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 8 Comparison of CPU16 and M68HC11 CPU Instruction Sets Most M68HC11 CPU instructions are a source code compatible subset of the CPU16 instruction set However certain M68HC11 CPU instructions have been replaced by functionally equivalent CPU16 instructions and some CPUf16 instructions with the same mnemonics as M68HC11 CPU instructions operate differently Table 4 4 shows M68HC11 CPU instructions that either have been replaced by CPU16 instructions or that operate differently on the CPU16 Replacement instruc tions are not identical to M68HC11 CPU instructions M68HC11 code must be altered to establish proper preconditions All CPU16 instruction execution times differ from those of the M68HC11 Motorola Programming Note M68HC16PN01 D Transpor
141. 2 8 2 SASM Registers The SASM contains one status interrupt control register and two data registers A and B All unused bits and reserved address locations return zero when read Writes to unused bits and reserved address locations have no effect The CTM7 contains six SASMs each with its own set of registers Refer to D 7 14 SASM Status Interrupt Control Registers and D 7 15 SASM Data Registers for information concerning SASM register and bit descriptions 12 9 Double Action Submodule DASM The double action submodule DASM allows two 16 bit input capture or two 16 bit output compare functions to occur automatically without software intervention The in put edge detector can be programmed to trigger the capture function on user specified edges The output flip can be set by one of the output compare functions and re set by the other one Interrupt requests can optionally be generated by the input cap ture and the output compare functions The user can select one of two incoming time bases for the input capture and output compare functions Six operating modes allow the DASM input capture and output compare functions to perform pulse width measurement period measurement single pulse generation and continuous pulse width modulation as well as standard input capture and output com pare The DASM can also function as a single I O pin DASM operating mode is determined by the mode select field MODE 3 0 in the DASM status inte
142. 2 Address lines 2 0 ADDR2 30 ADDR3 PBO 31 ADDR4 PB1 32 ADDR5 PB2 33 ADDR6 PB3 35 gt agri Address lines 10 3 or digital I O port ADDR7 PB4 36 4 SoMa B 7 0 9 ADDR8 PB5 37 ADDR9 PB6 38 ADDR10 PB7 39 ADDR 11 PAO 40 ADDR12 PA1 41 ADDR13 PA2 42 ADDR14 PA3 43 B Address lines 18 11 or digital I O ADDR15 PA4 44 SGIM port A 7 0 ADDR16 PA5 45 ADDR17 PA6 46 ADDR18 PA7 47 ADDAI S CSSIPCS 150 Address lines 22 19 chip select Pati ee 22 o SCIM2 outputs 9 6 or digital output portC 0 ADDR21 CS8 PC5 122 6 3 UE TS PERE ADDR22 CS9 PC6 123 es Address line 23 chip select output ADDR23 CS10 ECLK 124 0 SCIM2 10 or E clock output for M6800 bus devices ANO PADAO 24 AN1 PADA1 23 AN2 PADA2 22 AN3 PADA3 21 ADC Analog inputs to ADC multiplexer or AN4 PADA4 20 digital input port ADA 7 0 AN5 PADA5 19 AN6 PADA6 16 AN7 PADA7 15 4c Indicates that a valid address is on AS PES Si the address bus or digital I O port E5 15 Requests automatic vector during AVEC PE2 90 0 SCIM2 an interrupt acknowledge cycle or y o digital I O port E2 BERR 73 0 SCIM2 Requests a bus error exception BG CSM 113 0 0 SCIM2 Bus granted output or emulation memory chip select output AE Bus grant acknowledge input or ie 90 SOINS SCIM2 emulation chip select output Hardware breakpoint input or back BKPT DSCLK 69 0 CPU16 ground debug mode serial data clock input BR CSO
143. 2 can turn off system clocks after execution of the LPSTOP instruction When the CPU16 exe cutes LPSTOP the LPSTOP broadcast cycle is generated The SCIM2 brings the MCU out of low power mode when either an interrupt of higher priority than the inter rupt mask level in the CPU16 condition code register or a reset occurs Refer to 5 3 4 Low Power Operation and SECTION 4 CENTRAL PROCESSOR UNIT for more in formation During an LPSTOP broadcast cycle the CPU16 performs a CPU space write to ad dress 3FFFE This write puts a copy of the interrupt mask value in the clock control logic The mask is encoded on the data bus as shown in Figure 5 15 MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 35 Go to www freescale com Freescale Semiconductor Inc The LPSTOP CPU space cycle is shown externally if the bus is available as an indi cation to external devices that the MCU is going into low power stop mode The SCIM2 provides an internally generated DSACK response to this cycle The timing of this bus cycle is the same as for a fast termination write cycle If the bus is not available arbi trated away the LPSTOP broadcast cycle is not shown externally NOTE BERR during the LPSTOP broadcast cycle is ignored 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 o mask LPSTOP MASK LEVEL Figure 5 15 LPSTOP Interrupt Mask Level 5 6 5 Bus Exception
144. 256K x 16 or 512K x 16 Fast RAM 32K x 16 or 128K x 16 Background mode operation for detailed operation from a personal computer platform without an on board monitor ntegrated assembly editing evaluation programming environment for easy development As many as seven software breakpoints Re usable ICD hardware for your target application debug or control e Two RS 232C terminal input output I O ports for user evaluation of the serial communication interface Logic analyzer pod connectors e Port replacement unit PRU to rebuild I O ports lost to address data control On board Vpp 12 VDC generation for MCU and flash EEPROM programming On board wire wrap area MOTOROLA DEVELOPMENT SUPPORT MC68HC16R1 916R1 C 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc APPENDIX D REGISTER SUMMARY This appendix contains address maps register diagrams and bit field definitions for MC68HC16R1 916R1 MCUs More detailed information about register function is pro vided in the appropriate sections of the manual Except for central processing unit resources information is presented in the intermod ule bus address order shown in Table D 1 Table D 1 Module Address Map Size Base Bytes Address Module SCIM2 SRAM YFFBOO MRM MC68HC16R1 only YFF820 ADC YFF700 YFFCOO CTM7 YFF900 16K AND 32K FLASH
145. 32 bit long word signed and unsigned integers 16 bit signed fractions 32 bit signed fractions 36 bit signed fixed point numbers 20 bit effective addresses There are 8 bits in a byte and 16 bits in a word Bit set and clear instructions use both byte and word operands Bit test instructions use byte operands Negative integers are represented in two s complement form 4 bit signed integers packed two to a byte are used only as X and Y offsets in MAC and RMAC operations 32 bit integers are used only by extended multiply and divide instructions and by the associated LDED and STED instructions BCD numbers are packed two digits per byte BCD operations use byte operands Signed 16 bit fractions are used by the fractional multiplication instructions and as multiplicand and multiplier operands in the MAC unit Bit 15 is the sign bit and there is an implied radix point between bits 15 and 14 There are 15 bits of magnitude The range of values is 1 8000 to 1 215 7FFF Signed 32 bit fractions are used only by the fractional multiplication and division instructions Bit 31 is the sign bit An implied radix point lies between bits 31 and 30 There 31 bits of magnitude The range of values is 1 80000000 to 1 231 7FFFFFFF MOTOROLA CENTRAL PROCESSOR UNIT MC68HC16R1 916R1 4 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Signed 36
146. 4 ROM Array Base Address Register High ROMBAH YFF826 ROM Array Base Address Register Low ROMBAL YFF828 Signature Register High SIGHI YFF82A Signature Register Low SIGLO YFF82C Not Implemented YFF82E Not Implemented YFF830 ROM Bootstrap Word 0 ROMBSO YFF832 ROM Bootstrap Word 1 ROMBS1 YFF834 ROM Bootstrap Word 2 ROMBS2 YFF836 ROM Bootstrap Word 3 ROMBS3 YFF838 Not Implemented YFF83A Not Implemented YFF83C Not Implemented YFF83E Not Implemented NOTES 1 Y M111 where is the logic state of the module mapping MM bit in the SCIMCR D 4 1 Masked ROM Module Configuration Register MRMCR Masked ROM Module Configuration Register YFF820 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STOP 0 0 BOOT LOCK EMUL ASPC 1 0 WAIT 1 0 NOT USED RESET DATA14 0 0 1 0 0 1 1 1 1 STOP Low Power Stop Mode Enable The reset state of the STOP bit is the complement of DATA14 state during reset The ROM array base address cannot be changed unless the STOP bit is set 0 ROM array operates normally 1 ROM array operates in low power stop mode The ROM array cannot be read in this mode This bit may be read or written at any time MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 28 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc BOOT Boot ROM Control Reset state of BOOT is specified at mask time This is a read only bit 0 ROM responds to bootstr
147. 46 ADDR18 PA7 47 ADDR19 CS6 PC3 120 ADDR20 CS7 PC4 121 ADDR21 CS8 PC5 122 ADDR22 CS9 PC6 123 ADDR23 CS10 ECLK 124 SCIM2 A ANO PADAO 24 AN1 PADA1 23 AN2 PADA2 22 21 1 AN4 PADA4 20 ADG D Y AN5 PADA5 19 AN6 PADA6 16 AN7 PADA7 15 AS PE5 87 SCIM2 B AVEC PE2 90 SCIM2 B Y N BERR 73 SCIM2 Y N BG CSM 113 SCIM2 B MOTOROLA OVERVIEW MC68HC16R1 916R1 3 8 For More Information On This Product Go to www freescale com USER S MANUAL Freescale Semiconductor Inc Table 3 1 MC68HC16R1 MC68HC916R1 Pin Characteristics Pin Pin Associated Driver Synchronized Input Mnemonic s Number s Module Type Input Hysteresis BGACK CSE 114 SCIM2 B Y N BKPT DSCLK 69 CPU16 Y Y BR CSO 112 SCIM2 B Y N CLKOUT 65 SCIM2 A CPWM18 126 CPWM19 125 5 111 SCIM2 B CTD4 11 CTD5 10 CTM7 A Y Y CTM2C 12 CTM7 Y Y CTS6A 9 CTS6B 8 CTS8A 7 CTS8B 6 CTS10A 5 CTS10B 4 CTS12A 3 A Y X CTS12B 2 CTS14A 1 CTS14B 129 CTS16A 128 CTS16B 127 DATAO PHO 110 DATA1 PH1 109 DATA2 PH2 108 DATA3 PH3 107 3 DATA4 PH4 106 SEINE AW X x DATA5 PH5 105 DATA6 PH6 104 DATA7 PH7 103 DATA8 PGO 102 DATA9 PG1 101 DATA10 PG2 99 DATA11 PG3 98 3 DATA12 PG4 97 Sot Aw X DATA13 PG5 96 DATA14 PG6 95 DATA15 PG7 94 DS PE4 88 SCIM2 B Y Y DSACKO PEO 92 DSACK1 PE1 91 SCIMZ B Y EXTAL 59 SCIM2
148. 6 A0 IND8 Y 55 ff 6 IND8 Z 65 ff 6 IMM8 75 ii 2 IND16 X 1745 9000 6 IND16 1755 9090 6 IND16 2 1765 0099 6 1775 hh II 6 E X 2745 6 E Y 2755 6 2 2765 6 MOTOROLA MC68HC16R1 916R1 4 20 USER S MANUAL Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV 2 V C LDAB Load B M gt B IND8 X 5 ff 6 A 0 A IND8 Y D5 ff 6 IND8 Z E5 ff 6 IMM8 F5 ii 2 IND16 X 17 5 999g 6 IND16 Y 17D5 999g 6 IND16 Z 17E5 999g 6 EXT 17F5 hh Il 6 E X 27 5 6 E Y 27D5 6 2 27 5 6 LDD Load D M M 1 gt D IND8 X 85 ff 6 A 0 IND8 Y 95 ff 6 IND8 Z A5 ff 6 IMM16 37B5 jj kk 4 IND16 X 37C5 gggg 6 IND16 Y 37D5 gggg 6 IND16 Z 37E5 gggg 6 EXT 37F5 hh Il 6 E X 2785 6 2795 6 2 27 5 6 LDE Load E 1 16 3735 jj kk 4 0 IND16 X 3745 gggg 6 IND16 Y 3755 gggg 6 IND16 Z 3765 gggg 6 EXT 3775 hh Il 6 LDED Load Concatenated 1 2771 hh Il 8 E and D 2 3 0 LDHI Initialize H and M M 1 x HR INH 27B0 8 M M 1 y gt IR LDS Load SP 1 SP IND8 6 A 0 IND8 Y DF ff 6 IND8 Z EF ff 6 IND16 X 17CF gggg 6 IND16
149. 6 PADAS PADM PADA3 PADA2 PADA1 PADAO REFLECTS STATE OF THE INPUT PINS Port ADA is an input port that shares pins with the A D converter inputs MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product D 33 Go to www freescale com Freescale Semiconductor Inc PADA 5 0 Port ADA Data Pins A read of PADA 7 0 returns the logic level of the port ADA pins If an input is not at an appropriate logic level that is outside the defined levels the read is indeterminate Use of a port ADA pin for digital input does not preclude its simultaneous use as an analog input D 5 4 Control Register 0 ADCTLO Control Register 0 YFF70A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED RES10 515141 PRS 4 0 0 0 0 0 0 0 1 1 ADCTLO is used to select 8 or 10 bit conversions sample time and ADC clock frequency Writes to it have immediate effect RES10 10 Bit Resolution 0 8 bit conversion 1 10 bit conversion Conversion results are appropriately aligned in result registers to reflect the number of bits STS 1 0 Sample Time Selection Total conversion time is the sum of initial sample time transfer time final sample time and resolution time Initial sample time is fixed at two ADC clocks Transfer time is fixed at two ADC clocks Resolution time is fixed at 10 ADC clocks for an 8 bit conver sion and 12 ADC clocks for a 10 bit conversion F
150. 6 Indexed Mode to Replace M68HC11 Direct Mode In M68HC11 systems the direct addressing mode can be used to perform rapid accesses to RAM or I O mapped from 0000 to 00FF The CPU16 uses the first 512 bytes of Bank 0 for exception vectors To provide an enhanced replacement for the MC68HC11 s direct addressing mode the ZK field and index register Z have been as signed reset initialization vectors By resetting the ZK field to a chosen page and using indexed mode addressing a programmer can access useful data structures anywhere in the address map 4 7 Instruction Set The CPU16 instruction set is based on the M68HC11 instruction set but the opcode map has been rearranged to maximize performance with a 16 bit data bus Most M68HC11 code can run on the CPU16 following reassembly The user must take into account changed instruction times the interrupt mask and the changed interrupt stack frame Refer to Motorola Programming Note M68HC16PNO01 D Transporting M68HC11 Code to M68HC16 Devices for more information 4 7 1 Instruction Set Summary Table 4 2 is a quick reference to the entire CPU16 instruction set Refer to the CPU16 Reference Manual CPU16RM AD for detailed information about each instruction as sembler syntax and condition code evaluation Table 4 3 provides a key to the table nomenclature MC68HC16R1 916R1 CENTRAL PROCESSOR UNIT MOTOROLA USER S MANUAL For More Information On This Product 4 11 Go to www freescale com
151. 68 CPU16 background debug mode serial data IRQ1 PF1 82 IRQ2 PF2 81 IRQS PF3 80 IRQ4 PF4 79 0 SCIM2 pelle inputs IRQ5 PF5 78 9 P 22 IRQ6 PF6 77 IRQ7 PF7 76 SPI master input slave output data or MISO PMCO 50 digital port SPI master output slave input data MOSI PMC1 49 or digital l O port y o 89 SCIM2 Digital I O port R W 84 1 0 SCIM2 Indicates a data bus read when high gt and a data bus write when low RESET 71 0 SCIM2 System reset RXDA PMC6 53 E MCCI SCI A and B receive data inputs or lO RXDB PMC4 55 digital I O ports MC6 and 4 SPI serial clock input output digital SCK PMC2 51 port MC2 SIZ0 PE6 86 a Data transfer size outputs or digital 1 SIZ1 PE7 85 SCIM2 o ports E 7 6 TE SPI slave select input or digital I O SS PMC3 48 0 MCCI port TSC 75 1 SCIM2 Places MCU outputs in high imped ance state TXDA PMC7 52 es MCCI SCI A and B transmit data outputs or lO TXDB PMC5 54 digital I O ports MC7 and MC5 MOTOROLA OVERVIEW MC68HC16R1 916R1 3 14 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 3 3 MC68HC16R1 MC68HC916R1 Pin Functions Pin Pin Active Associated eer Discrete Mnemonic s Number s State s Module Description Use 14 27 61 mi Vpp 63 Digital sup
152. 75 1760 13 75 110111 224 1 75 448 3 5 896 7 1792 14 111000 228 1 78125 456 3 5625 912 7 125 1824 14 25 111001 232 1 8125 464 3 625 928 7 25 1856 14 5 111010 236 1 84375 472 3 6875 944 7 375 1888 14 75 111011 240 1 875 480 3 75 960 7 5 1920 15 111100 244 1 90625 488 3 8125 976 7 625 1952 15 25 111101 248 1 9375 496 3 875 992 7 75 1984 15 5 111110 252 1 96875 504 3 9375 1008 7 875 2016 15 75 111111 256 2 512 4 1024 8 2048 16 MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL 5 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 3 16 78 MHz System Clock Frequencies Shaded cells represent values that exceed 16 78 MHz specifications Modulus Prescaler W X 00 W X 01 W X 10 W X 11 fuco 2x Value fyco Value fyco 2 x Value fyco Value 000000 131 kHz 262 kHz 524 kHz 1049 kHz 000001 262 524 1049 2097 000010 393 786 1573 3146 000011 524 1049 2097 4194 000100 655 1311 2621 5243 000101 786 1573 3146 6291 000110 918 1835 3670 7340 000111 1049 2097 4194 8389 001000 1180 2359 4719 9437 001001 1311 2621 5243 10486 001010 1442 2884 5767 11534 001011 1573 3146 6291 12583 001100 1704 3408 6816 13631 001101 1835 3670 7340 14680 001110 1966 3932 7864 15729 001111 2097 4194 8389 16777 010000 2228 4456 8913 17826 010001 235
153. 75 24 1875 48 375 96 75 000011 16 125 32 25 64 5 128 1 000100 20 15625 40 3125 80 625 160 1 25 000101 24 1875 48 375 96 75 192 1 5 000110 28 21875 56 4375 112 875 224 1 75 000111 32 25 64 5 128 1 256 2 001000 36 21825 72 5625 144 1 125 288 2 25 001001 40 3125 80 625 160 1 25 320 2 5 001010 44 94375 88 6875 176 1 375 352 2 75 001011 48 375 96 75 192 1 5 384 3 001100 52 40625 104 8125 208 1 625 416 3 25 001101 56 4375 112 875 224 1 75 448 3 5 001110 60 46875 120 9375 240 1 875 480 3 75 001111 64 5 128 1 256 2 512 4 010000 68 53125 136 1 0625 272 2 125 544 4 25 010001 72 5625 144 1 125 288 2 25 576 4 5 010010 76 59375 152 1 1875 304 2 375 608 4 75 010011 80 625 160 1 25 320 2 5 640 5 010100 84 65625 168 1 3125 336 2 625 672 5 25 010101 88 6875 176 1 375 352 2 75 704 5 5 010110 92 71875 184 1 4375 368 2 875 736 5 75 010111 96 75 192 1 5 384 3 768 6 011000 100 78125 200 1 5625 400 3 125 800 6 25 011001 104 8125 208 1 625 416 3 25 832 6 5 011010 108 84375 216 1 6875 432 3 375 864 6 75 011011 112 875 224 1 75 448 3 5 896 7 011100 116 90625 232 1 8125 464 3 625 928 7 25 011101 120 9375 240 1 875 480 3 75 960 7 5 011110 124 96875 248 1 9375 496 3 875 992 7 75 011111 128 1 256 2 512 4 1024 8 MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 10 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 2 16 78 MHz Clock Control Mult
154. 8 Conversion Multichannel Sequences CD CA Channel Selection Bits in this field select input channel or channels for A D conversion Conversion mode determines which channel or channels are selected for conversion and which result registers are used to store conversion results Tables D 28 and D 29 contain a summary of the effects of ADCTL1 bits and fields MOTOROLA MC68HC16R1 916R1 D 36 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table D 28 Single Channel Conversions MULT 0 S8CM CD CC CB Input Result Register 0 0 0 0 0 ANO RSLT 0 3 0 0 1 AN1 RSLT 0 3 0 0 0 1 0 AN2 RSLT 0 3 0 0 1 AN3 RSLT 0 3 0 0 1 0 0 AN4 RSLT 0 3 0 0 1 AN5 RSLT 0 3 0 0 1 1 0 AN6 RSLT 0 3 0 0 1 AN7 RSLT 0 3 0 1 0 0 0 Reserved RSLT 0 3 0 1 1 Reserved RSLT 0 3 0 1 0 1 0 Reserved RSLT 0 3 0 1 1 Reserved RSLT 0 3 0 1 1 0 0 RSLT 0 3 0 1 1 0 1 VRL RSLT 0 3 0 1 1 1 0 Vn 2 RSLT 0 3 0 1 1 1 1 Test Reserved RSLT 0 3 1 0 0 0 0 ANO RSLT 0 7 1 0 0 0 1 AN1 RSLT 0 7 1 0 0 1 0 AN2 RSLT 0 7 1 0 0 1 1 AN3 RSLT 0 7 1 0 1 0 0 AN4 RSLT 0 7 1 0 1 0 1 AN5 RSLT 0 7 1 0 1 1 0 AN6 RSLT 0 7 1 0 1 1 1 AN7 RSLT 0 7 1 1 0 0 0 Reserved RSLT 0 7 1 1 0 0 1 Reserved RSLT 0 7 1 1 0 1 0 Reserved RSLT 0 7 1 1 0 1 1 Reserved RSLT 0 7 1 1 1 0 0 RSLT 0 7 1 1 1 0
155. 9 4719 9437 18874 010010 2490 4981 9961 19923 010011 2621 5243 10486 20972 010100 2753 5505 11010 22020 010101 2884 5767 11534 23069 010110 3015 6029 12059 24117 010111 3146 6291 12583 25166 011000 3277 6554 13107 26214 011001 3408 6816 13631 27263 011010 3539 7078 14156 28312 011011 3670 7340 14680 29360 011100 3801 7602 15204 30409 011101 3932 7864 15729 31457 011110 4063 8126 16253 32506 011111 4194 8389 16777 33554 MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 12 For More Information On This Product Go to www freescale com USER S MANUAL Freescale Semiconductor Inc Table 5 3 16 78 MHz System Clock Frequencies Continued Shaded cells represent values that exceed 16 78 MHz specifications Modulus Prescaler W X 00 W X 01 W X 10 W X 11 fuco 2x Value fyco Value fyco 2 x Value fyco Value 100000 4325 kHz 8651 kHz 17302 kHz 34603 kHz 100001 4456 8913 17826 35652 100010 4588 9175 18350 36700 100011 4719 9437 18874 37749 100100 4850 9699 19399 38797 100101 4981 9961 19923 39846 100110 5112 10224 20447 40894 100111 5243 10486 20972 41943 101000 5374 10748 21496 42992 101001 5505 11010 22020 44040 101010 5636 11272 22544 45089 101011 5767 11534 23069 46137 101100 5898 11796 23593 47186 101101 6029 12059 24117 48234 101110 6160 12321 24642 49283 101
156. 9 8 7 6 5 4 3 2 1 0 NOT USED PFIVR 7 0 RESET 0 0 0 0 0 0 0 0 This register determines which vector in the exception vector table is used for inter rupts generated by the port F edge detect logic Program PFIVR 7 0 to the value pointing to the appropriate interrupt vector Bits 15 8 are unimplemented and will al ways read zero D 2 21 Port F Edge Detect Interrupt Level PFLVR Port F Edge Detect Interrupt Level Register YFFA2C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED 0 0 0 0 0 PFLV 2 0 RESET 0 0 0 0 0 0 0 0 This register determines the priority level of the port F edge detect interrupt The reset value is 00 indicating that the interrupt is disabled When several sources of inter rupts from the SCIM are arbitrating for the same level the port F edge detect interrupt has the lowest arbitration priority Bits 15 8 are unimplemented and will always read zero MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 17 Go to www freescale com Freescale Semiconductor Inc D 2 22 Port C Data Register PORTC Port C Data Register YFFA41 15 8 7 6 5 4 3 2 1 0 NOT USED 0 PC6 PC5 4 2 1 PCO RESET 0 1 1 1 1 1 1 1 PORTC latches data for chip select pins configured as discrete outputs D 2 23 Chip Select Pin Assignment Registers CSPAR
157. A 22 A 0 A Remainder D INC Increment Memory M 01 IND8 X 03 ff 8 a A A IND8 Y 13 ff 8 IND8 Z 23 ff 8 IND16 X 1703 9999 8 IND16 Y 1713 9999 8 IND16 Z 1723 9999 8 1733 hh Il 8 INCA Increment A A 01 gt A INH 3703 2 A A A INCB Increment B B 012 B INH 3713 2 A A INCW Increment Memory M M 1 0001 IND16 X 2703 999g 8 LG XA Word gt M M 1 IND16 Y 2713 9999 8 IND16 2 2723 9999 8 2733 hh 8 MC68HC16R1 916R1 MOTOROLA USER S MANUAL 4 19 For More Information On This Product Go to www freescale com Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S 27 C JMP Jump ea 2 PK PC EXT20 7A zb hh Il 6 IND20 X 4B 29 9999 8 IND20 Y 5B zg 9999 8 IND20 2 6B 29 9090 8 JSR Jump to Subroutine Push PC EXT20 FA zb hh ll 10 SK SP 0002 2 SK SP IND20 X 89 zg gggg 12 Push CCR IND20 Y 99 zg gggg 12 SK SP 0002 2 SK SP IND20 Z AQ 29 9999 12 ea 2 PK PC LBCC2 Long Branch if Carry If C
158. AA Word IND16 Y 271D 9999 8 LLL IPE IND16 Z 272D 9999 8 EXT 273D hh Il 8 BCC2 Branch if Carry Clear If C 0 branch REL8 B4 rr 6 2 BCLR Clear Bit s Mask IND8 1708 mm ff 8 A 0 IND8 Y 1718 mm ff 8 IND8 Z 1728 mm ff 8 IND16 X 08 mm gggg 8 IND16 Y 18 mm gggg 8 IND16 Z 28 mm gggg 8 EXT 38 mm hhll 8 BCLRW Clear Bit s in a Word M M 1 Mask IND16 X 2708 999g 10 Se A 0 M M 1 mmmm IND16 Y 2718 999g 10 mmmm IND16 Z 2728 999g 10 mmmm EXT 2738 hh Il 10 mmmm BCS Branch if Carry Set If C 1 branch REL8 B5 rr 6 2 2 Branch if Equal If Z 1 branch REL8 B7 rr 6 2 BGE2 Branch if Greater Than If N 6 V 0 branch REL8 BC rr 6 2 or Equal to Zero BGND Enter Background If BDM enabled INH 37A6 Debug Mode begin debug else illegal instruction trap BGT2 Branch if Greater Than If Z N V 0 branch REL8 BE rr 6 2 Zero BHI2 Branch if Higher If C Z 0 branch REL8 B2 6 2 Bit Test A IND8 X 49 ff 6 A 0 IND8 Y 59 ff 6 IND8 Z 69 ff 6 IMM8 79 ii 2 IND16 X 1749 9999 6 IND16 Y 1759 9999 6 IND16 Z 1769 9999 6 EXT 1779 hh Il 6 E X 2749 6 E Y 2759 6 E Z 2769 6 MC68HC16R1 916R1 MOTOROLA USER S MANUAL 4 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued
159. AA from D IND8 Y 92 ff 6 IND8 Z A2 ff 6 IMM16 37B2 jj kk 4 IND16 X 37C2 gggg 6 IND16 Y 37D2 gggg 6 IND16 Z 37E2 gggg 6 EXT 37F2 hh Il 6 2782 6 E Y 2792 6 E Z 27A2 6 SBCE Subtract with Carry E M M 1 C gt E IMM16 3732 jj kk 4 AAA from E IND16 X 3742 9999 6 IND16 Y 3752 999g 6 IND16 Z 3762 9999 6 3772 hh Il 6 SDE Subtract D from E D E INH 2779 2 AAA STAA Store A M IND8 X 4A ff 4 0 IND8 Y 5A ff 4 IND8 Z 6A ff 4 IND16 X 174A 9999 6 IND16 Y 175A 999g 6 IND16 Z 176A 999g 6 EXT 177A hh Il 6 E X 274A 4 E Y 275A 4 2 276 E 4 MC68HC16R1 916R1 MOTOROLA USER S MANUAL 4 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV 2 V C STAB Store B B M IND8 X CA ff 4 A 0 IND8 Y DA ff 4 IND8 Z EA ff 4 IND16 X 17CA gggg 6 IND16 Y 17DA 0099 6 IND16 2 17 999g 6 EXT 17FA hh Il 6 27 4 27DA 4 2 27EA 4 STD Store D D gt 1 IND8 X 8A ff 4 A 0 IND8 Y 9A ff 4 IND8 Z AA ff 4 IND16 X 37CA 999g 6 IND16 Y 37DA 999g 6 IND16 Z 37EA 999g 6 EXT 37FA
160. ASTER 2 NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3 NEXT BUS MASTER ASSERTS BGACK TERMINATE ARBITRATION 4 BUS MASTER NEGATES BRT 1 NEGATE BG AND WAIT FOR BGACK TO BE NEGATED OPERATE AS BUS MASTER 1 PERFORM DATA TRANSFERS READ AND WRITE CYCLES ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP 1 NEGATE BGACK RE ARBITRATE OR RESUME PROCESSOR OPERATION BUS ARB FLOW Figure 5 16 Bus Arbitration Flowchart for Single Request 5 6 6 1 Show Cycles The MCU normally performs internal data transfers without affecting the external bus but it is possible to show these transfers during debugging AS is not asserted exter nally during show cycles Show cycles are controlled by the SHEN 1 0 in SCIMCR This field set to 00 by re set When show cycles are disabled the address bus function codes size and read write signals reflect internal bus activity but AS and DS are not asserted externally and external data bus pins are in high impedance state during internal accesses Refer to 5 2 4 Show Internal Cycles and the SC M Reference Manual SCIMRM AD for more information When show cycles are enabled DS is asserted externally during internal cycles and internal data is driven out on the external data bus Because internal cycles normally continue to run when the external bus is granted one SHEN 1 0 encoding halts inter nal bus activity while there is an external master
161. ATA 15 0 form a bidirectional non multiplexed parallel bus that transfers data to or from the MCU A read or write operation can transfer 8 or 16 bits of data in one bus cycle For a write cycle all 16 bits of the data bus are driven regardless of the port width or operand size 5 5 1 4 Data Strobe Data strobe DS is a timing signal For a read cycle the MCU asserts DS to signal an external device to place data on the bus DS is asserted at the same time as AS during a read cycle For a write cycle DS signals an external device that data on the bus is valid MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 24 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 5 1 5 Read Write Signal The read write signal R W determines the direction of the transfer during a bus cycle This signal changes state when required at the beginning of a bus cycle and is valid while AS is asserted R W only transitions when a write cycle is preceded by a read cycle or vice versa The signal may remain low for two consecutive write cycles 5 5 1 6 Size Signals Size signals SIZ 1 0 indicate the number of bytes remaining to be transferred during an operand cycle They are valid while AS is asserted Table 5 9 shows SIZO and SIZ1 encoding Table 5 9 Size Signal Encoding SIZ1 SIZO Transfer Size 0 1 Byte 1 0 Word 1 1 3 Byte 0 0 Long word 5 5 1 7 Function
162. ATUS REGISTER SPI CONTROL REGISTER SPI INTERRUPT INTERNAL REQUEST DATA BUS MCCI SPI BLOCK Figure 11 2 SPI Block Diagram Clock control logic allows a selection of clock polarity and a choice of two clocking pro tocols to accommodate most available synchronous serial peripheral devices When the SPI is configured as a master software selects one of 254 different bit rates for the serial clock During an SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially A serial clock line synchronizes shifting and sampling of the information on the two serial data lines A slave select line allows individual selection of a slave SPI device Slave devices which are not selected do not interfere with SPI bus activities On a master SPI device the slave select line can optionally be used to indicate a multiple master bus contention MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL For More Information On This Product 11 5 Go to www freescale com Freescale Semiconductor Inc Error detection logic is included to support interprocessor interfacing A write collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress A multiple master mode fault detector automatically dis ables SPI output drivers if more than one MCU simultaneously attempts to become bus master 11 3 1 SPI Registers SPI control regi
163. C 1 0 in BFEMCR 9 4 4 Program Erase Operation An unprogrammed flash bit has a logic state of one A bit must be programmed to change its state from one to zero Erasing a bit returns it to a logic state of one Pro gramming or erasing the BEFLASH array requires a series of control register writes and a write to an array address The same procedure is used to program control reg isters that contain flash bits Programming is restricted to a single byte or aligned word at a time Erasure of BEFLASH array blocks and control shadow bits are dependent on the setting of ADDR 3 1 of the address written to during an erase operation Refer to Table 9 2 for the address bit patterns corresponding to specific BEFLASH blocks MC68HC16R1 916R1 BLOCK ERASABLE FLASH EEPROM MOTOROLA USER S MANUAL For More Information On This Product 9 3 Go to www freescale com Freescale Semiconductor Inc Table 9 2 BEFLASH Erase Operation Address Ranges Address Bits Used to Specify Block for Erasure Block Addresses Affected ADDR 23 11 ADDR 10 6 5 4 2 1 0 0 0000 007F 1 0 0 0 0 1 0080 0100 1 0 0 0 1 2 0100 017F 1 0 0 1 0 3 0180 01FF 1 0 0 1 1 4 0200 02FF BFEBAH 2 1 0 1 0 0 2 5 0300 BFEBAL 191114111 6 0400 05FF 1 0 1 1 0 7 0600 07FF 1 0 1 1 1 Reserved 1 1 X X X Entire Array 0600 07FF 0 X X X X NOTES 1 The block erasable f
164. C2 CS5 PC2 CTS16A CTS16B CPWMI9 ADDR23 CS10 ECLK FCO CS3 PCO For More Information On This Product Go to www freescale com VRH AN5 PADA5 AN4 PADA4 AN3 PADA3 AN2 PADA2 AN1 PADA1 ANO P ADAO VSSA VDDA VDD VSS ADDR1 ADDR2 ADDR3 PBO ADDR4 PB1 ADDR5 PB2 VSS ADDR6 P B3 ADDR7 PB4 ADDR8 PB5 ADDR9 PB6 ADDR10 PB7 ADDR11 PA0 ADDR12 PA1 ADDR13 PA2 ADDR14 PA3 ADDR 15 PA4 ADDR16 PA5 ADDR17 PA6 ADDR18 PA7 SS PMC3 MOSI PMC1 MISO PMCO NOTES Freescale Semiconductor Inc ADDR22 CS9 PC6 ADDR21 CS8 PC5 ADDR20 CS7 PC4 ADDR1S CS6 PC3 CTS10A CTS10B 12 CTS12B CTS14A VFPE1 VDD VSS CTS14B CTS16A CTS16B CPWMI9 ADDR23 CS10 ECLK FC2 CS5 PC2 FCO CS3 PCO MC68HC916R1 ATWLYYWW2 QDEQEE EA ERLE SURES iu 1 E up MIU SERES a 7 1 OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATION Y EAR WEEK MC68HC16R1 916R1 USER S MANUAL OVERVIEW For More Information On This Product Go to www freescale com VDD VSS BGACK CSE 50 CSBOOT DATAO PHO DATAI PH1 DATA2 PH2 DATA3 PH3 DATA4 PH4 DATAS PH5 DATAG PH6 DATATIPH7 DATA8 PGO DATA9 PG1 VSS DATA10 PG2 DATA11 PG3 DATA12 PG4 DATA13 PG5 DATAMJPG6 DATA15 PG7 ADDRO DSACKO PEO DSACKI PE1 AVEC 2 PE3 DS PE4 AS PES SI
165. C68HC916R1 MCUs It lists features of each of the modules shows device functional divisions and pinouts summarizes signal and pin functions discusses the intermodule bus and pro vides system memory maps Timing and electrical specifications for the entire micro controller and for individual modules are provided in APPENDIX A ELECTRICAL CHARACTERISTICS Comprehensive module register descriptions and memory maps are provided in APPENDIX D REGISTER SUMMARY 3 1 MC68HC16R1 916R1 MCU Features The following paragraphs highlight capabilities of each of the MCU modules Each module is discussed separately in a subsequent section of this manual 3 1 1 Central Processor Unit CPU16 16 Bit architecture Full set of 16 bit instructions Three 16 bit index registers Two 16 bit accumulators Control oriented digital signal processing capability Addresses up to 1 Mbyte of program memory 1 Mbyte of data memory Background debug mode Fully static operation 3 1 2 Single Chip Integration Module 2 SCIM2 e Single chip and expanded operating modes External bus support in expanded mode Nine programmable chip select outputs Phase locked loop system clock with user selectable fast or slow reference Watchdog timer clock monitor and bus monitor Address and data bus provide 32 discrete I O lines in single chip mode Enhanced reset controller 3 1 3 Standby RAM SRAM 2 Kbytes of static RAM e Standby voltage Vst
166. CL Where Total clock periods per instruction Clock periods used for internal operation CLp Clock periods used for program access CLo Clock periods used for operand access Refer to the CPU16 Reference Manual CPU16RM AD for more information on this topic 4 13 Exceptions An exception is an event that preempts normal instruction processing Exception pro cessing makes the transition from normal instruction execution to execution of a rou tine that deals with the exception Each exception has an assigned vector that points to an associated handler routine Exception processing includes all operations required to transfer control to a handler routine but does not include execution of the handler routine itself Keep the distinc tion between exception processing and execution of an exception handler in mind while reading this section 4 13 1 Exception Vectors An exception vector is the address of a routine that handles an exception Exception vectors are contained in a data structure called the exception vector table which is lo cated in the first 512 bytes of bank 0 Refer to Table 4 5 for the exception vector table All vectors except the reset vector consist of one word and reside in data space The reset vector consists of four words that reside in program space Refer to SECTION 5 SINGLE CHIP INTEGRATION MODULE 2 for information concerning address space types and the function code outputs
167. CPOL c Specify an 8 or 16 bit transfer SIZE and MSB or LSB first transfer mode LSBF d Select master or slave operating mode MSTR e Enable or disable wired OR operation WOMP f Enable or disable SPI interrupts SPIE g Enable the SPI by setting the SPE bit C Serial Communication Interface SCIA SCIB 1 Totransmit read the SCSR and then write transmit data to the SCDR This clears the TDRE and TC indicators in the SCSR a SCI control register 0 SCCRO b Write a baud rate value into the BR field 2 Configure SCCR1 a Select 8 or 9 bit frame format M b Determine use PE and type PT of parity generation or detection C To receive set the RE and RIE bits in SCCR1 Select use RWU and type WAKE of receiver wakeup Select idle line detection type ILT and enable or disable idle line interrupt ILIE d To transmit set TE and TIE bits in SCCR1 and enable or disable WOMC and TCIE bits Disable break transmission SBK for normal operation MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL For More Information On This Product 11 23 Go to www freescale com Freescale Semiconductor Inc MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 24 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 12 CONFIGURABLE TIMER MODULE 7 This section is an overview of CTM7 function Refer to t
168. Codes The CPU generates function code signals FC 2 0 to indicate the type of activity oc curring on the data or address bus These signals can be considered address exten sions that can be externally decoded to determine which of eight external address spaces is accessed during a bus cycle Because the CPU16 always operates in supervisor mode FC2 1 address spaces 0 to 3 are not used Address space 7 is designated CPU space CPU space is used for control information not normally associated with read or write bus cycles Function codes are valid while AS is asserted Table 5 10 shows address space encoding Table 5 10 Address Space Encoding FC2 FC1 FCO Address Space 1 0 0 Reserved 1 0 1 Data space 1 1 0 Program space 1 1 1 CPU space 5 5 1 8 Data Size Acknowledge Signals During normal bus transfers external devices assert the data size acknowledge signals DSACK 1 0 to indicate port width to the MCU During a read cycle these signals tell the MCU to terminate the bus cycle and to latch data During a write cycle the signals indicate that an external device has successfully stored data and that the cycle can terminate DSACK 1 0 can also be supplied internally by chip select logic Refer to 5 9 Chip Selects for more information MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 25 Go to www freescale com Freescale Semiconduc
169. D8 X 4D ff 6 A A Memory IND8 Y 5D ff 6 IND8 Z 6D ff 6 IMM16 377D jj Kk 4 IND16 X 174D 999g 6 IND16 Y 175D 999g 6 IND16 Z 176D 999g 6 EXT 177D hh Il 6 CPZ Compare IZ to IZ M M 1 IND8 X 4E ff 6 A A Memory IND8 Y ff 6 IND8 Z 6E ff 6 IMM16 377E jj Kk 4 IND16 X 174E 999g 6 IND16 Y 175E 999g 6 IND16 Z 176E 999g 6 EXT 177E hh Il 6 DAA Decimal Adjust A A 10 INH 3721 2 DEC Decrement Memory 01 IND8 X 01 ff 8 a IND8 Y 11 ff 8 IND8 Z 21 ff 8 IND16 X 1701 999g 8 IND16 Y 1711 999g 8 IND16 Z 1721 9999 8 1731 hh Il 8 DECA Decrement A A 01 A INH 3701 2 A DECB Decrement B 01 B INH 3711 2 A DECW Decrement Memory M M 1 0001 IND16 X 2701 999g 8 A Word M M 1 IND16 Y 2711 90909 8 IND16 Z 2721 gggg 8 EXT 2731 hh Il 8 EDIV Extended Unsigned E D 3728 24 A A Integer Divide Quotient Remainder MOTOROLA MC68HC16R1 916R1 4 18 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV 2 V C EDIVS Extended Signed E D
170. DC 5 MC54HC4053 ue FILTER CsoURCE 25 4 E C FILTER C MUXIN R SOURCE 2 R FILTER 2 xe C SOURCE C FILTER CMUXIN R SOURCE 2 R FILTER 2 T R MUXOUT CeQURCE AAA C FILTER CMUXIN R source 2 R FILTER 2 gt L L L C 01yri MUXOUT Cin CSAMPLE C SOURCE Ed C FILTER CMUXIN Cin Cin 1 R SOURCE 2 R FILTER 2 L TE em C SOURCE ka C FILTER CMUXIN R SOURCE 2 R FILTER 2 I iti em C SOURCE C FILTER CMUXIN R SOURCE 2 R FILTER 2 em C SOURCE ACE C FILTER CMUXIN R SOURCE 2 R FILTER 2 ES olu C FILTER CMUXIN R SOURCE 2 R FILTER AJ ses 1 NOTES C FILTER 1 TYPICAL VALUE Cin CSAMPLE 2 Rei reg TYPICALLY 10KQ 20KQ ADC EXT MUX EX Figure 10 9 External Multiplexing Of Analog Signal Sources MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For More Information On This Product 10 21 Go to www freescale com Freescale Semiconductor Inc 10 8 6 Analog Input Pins Analog inputs should have low AC impedance at the pins Low AC impedance can be realized by placing a capacitor with good high frequency characteristics at the input pin of the part Ideally that capacitor should be as large as possible within the practi cal range of capacitors that still have
171. Data Register PORTA Port B Data Register PORTB YFFAOC Port G Data Register PORTG Port H Data Register PORTH YFFAOE Port G Data Direction Register DDRG Port H Data Direction Register DDRH YFFA10 Not Used Port E Data Register YFFA12 Not Used Port E Data Register 1 PORTE1 YFFA14 Port A B Data Direction Register DDRAB Port E Data Direction Register DDRE YFFA16 Not Used Port E Pin Assignment Register PEPAR YFFA18 Not Used Port F Data Register 0 PORTFO YFFA1A Not Used Port F Data Register 1 PORTF1 YFFA1C Not Used Port F Data Direction Register DDRF YFFA1E Not Used Port F Pin Assignment Register PFPAR YFFA20 Not Used System Protection Control Register SYPCR YFFA22 Periodic Interrupt Control Register PICR YFFA24 Periodic Interrupt Timing Register PITR YFFA26 Not Used Software Service Register SWSR YFFA28 Not Used Port F Edge Detect Flags PORTFE YFFA2A Not Used Port F Edge Detect Interrupt Vector PFIVR YFFA2C Not Used Port F Edge Detect Interrupt Level PFLVR YFFA2E Not Used YFFA30 Test Module Master Shift A Register TSTMSRA YFFA32 Test Module Master Shift B Register TSTMSRB YFFA34 Test Module Shift Count Register TSTSC YFFA36 Test Module Repetition Counter Register TSTRC YFFA38 Test Module Control Register CREG YFFA3A Test Module Distributed Register DREG YFFA3C Not Used YFFASE Not Used YFFA40 Not Used Port C Data Register PORTC YFFA42 Not Used Not Used Y
172. Driven to put MRM in STOP mode STOP mode disabled when DATA14 is held high and STOP shadow bit is cleared MC68HC16R 1 only 6 Driven to put 16K and 32K flash EEPROM modules in STOP mode STOP mode disabled when DATA14 is held high and STOP shadow bit is cleared MC68HC916R1 only MC68HC16R1 916R1 USER S MANUAL SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA For More Information On This Product 5 47 Go to www freescale com Freescale Semiconductor Inc 5 7 3 4 8 Bit Expanded Mode The SCIM2 uses an 8 bit data bus when BERR 1 and DATA1 1 during reset In this configuration pins DATA 7 0 are configured as port H an 8 bit I O port Pins DATA 15 8 are configured as data bus pins and ADDR 18 3 are configured as address bus pins The alternate functions for these address and data bus pins as ports A B and G are unavailable ADDR 23 19 CS 10 6 are configured as chip selects ADDR 2 0 are configured as address bus pins Emulator mode is always disabled DATAS determines the function of the DSACK 1 0 AVEC DS AS and SIZ 1 0 pins If DATAS is held low during reset these pins are used for discrete I O port E DATA9 determines the function of interrupt request pins IRQ 7 1 and the clock mode select pin MODCLK When DATAS is held low during reset these pins are used for discrete I O port F Table 5 18 summarizes pin function selections for 8 bit data bus operation Table 5 18 8 Bit Expanded Mode Reset Configu
173. E 7 For More Information On This Product Go to www freescale com MOTOROLA 12 21 Freescale Semiconductor Inc MOTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 22 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc APPENDIX A ELECTRICAL CHARACTERISTICS Table A 1 Maximum Ratings Num Rating Symbol Value Unit 1 Supply Voltage 23 Vos 0 3 to 6 5 V 2 Input Voltage 2 9 5 7 V 0 3 to 6 5 V 3 Instantaneous Maximum Current m Single pin limit applies to all pins 3 5 6 D 25 4 Operating Maximum Current PP 2 Lo 500 to 500 uA Vpp 0 3 V 5 EEPROM Program Erase Supply Voltage 10 VFPE Vpp 0 5 to 12 6 V 6 Operating Temperature Range T T to T Suffix 40 to 85 7 Storage Temperature Range 55 to 150 C NOTES 1 2 3 4 5 6 7 8 9 10 Permanent damage can occur if maximum ratings are exceeded Exposure to voltages or currents in ex cess of recommended values affects device reliability Device modules may not operate normally while be ing exposed to electrical extremes Although sections of the device contain circuitry to protect against damage from high static voltages or elec trical fields take normal precautions to avoid exposure to voltages higher than maximum rated vo
174. E IRQ3IPF3 m r Seeds 1 FASTREF PFO CLOCK CLKOUT XTAL EXTAL XFC Vopsyn MODCLK VsssyN TSC TEST 9 BKPT DSCLK QUOT FREEZEQUOT IPIPE1 DSI 0 050 FREEZE MC68HC916R1 BLOCK Figure 3 2 MC68HC916R1 Block Diagram MC68HC16R1 916R1 OVERVIEW MOTOROLA USER S MANUAL 3 5 For More Information On This Product Go to www freescale com VRH VDD AN5 PADA5 O VSS AN4 PADA4 BGACK 5 AN3 PADA3 BG ICS AN2 PADA2 BR CSO AN1 PADA1 CSBOOT ANO PADAO DATAO PHO VSSA DATAIPH1 VDDA DATA2 PH2 DATA3 PH3 55 DATAA PH4 ADDR1 DATA5 PH5 ADDR2 DATAG PH6 ADDR3 PBO DATAT PH7 ADDR 4 PB1 DATA8 PGO ADDR5 PB2 MC68HC16R1 DATA9 PG1 VSS VSS ADDR6 PB3 ATWLYYWW DATA10 PG2 ADDR7 PB4 DATA11 PG3 ADDR8 PB5 DATA12 PG4 ADDR9 PB6 DATA13 PG5 ADDR 10 PB7 DATA14 PG6 ADDR11 PA0 DATA15 PG7 ADDR12 PA1 ADDRO ADDR13 PA2 DSACKO PEO ADDR 14 PA3 DSACKT PE1 ADDR15 PA4 AVEC PE2 ADDR16 PA5 PE3 ADDR17 PA6 DS PE4 ADDR18 PA7 AS PE5 SSJPMC3 SIZO PE6 MOSIPMC1 5121 7 MISO PMCO RW Nhons ZAUANHENOG yrontma dP DD a 3 NOTES 1 MMMMM MASK OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATION Y EAR WEEK MEER ELO QI Figure 3 3 MC68HC16R1 Pin Assignment for 132 Pin Package MOTOROLA OVERVIEW MC68HC16R1 916R1 3 6 USER S MANUAL Freescale Semiconductor Inc ADDR22 CS9 PC6 ADDR21 CS8 PC5 ADDR2Q CS7 PCA ADDR19 CS6 PC3 F
175. EGRATION MODULE 2 MC68HC16R1 916R1 5 26 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 11 Effect of DSACK Signals DSACK1 DSACKO Result 1 Insert wait states in current bus cycle Complete cycle Data bus port size is 8 bits Complete cycle Data bus port size is 16 bits Q Oj 1 0 0 Reserved If the CPU is executing an instruction that reads a long word operand from a 16 bit port the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits The operation for an 8 bit port is similar but requires four read cycles The addressed device uses the DSACK signals to indicate the port width For instance a 16 bit external device always returns DSACK for a 16 bit port regardless of whether the bus cycle is a byte or word operation Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed A 16 bit port must reside on data bus bits 15 0 and an 8 bit port must reside on data bus bits 15 8 This minimizes the number of bus cycles needed to transfer data and ensures that the MCU transfers valid data The MCU always attempts to transfer the maximum amount of data on all bus cycles For a word operation it is assumed that the port is 16 bits wide when the bus cycle begins Operand bytes are designated as shown in Fi
176. F Data Registers 0 1 PORTG SCIM 2 Port G Data Register PORTH SCIM2 Port H Data Register PORTF SCIM2 Port F Data Register PORTFE SCIM2 Port F Edge Detect Flag PORTMC MCCI Port Data Register PORTMCP MCCI Port Pin State Register PWM 18 19 A CTM7 PWSM Period 18 19 PWM 18 19 B CTM7 PWSM Pulse Width 18 19 PWM 18 19 C CTM7 PWSM Counter 18 19 PWM 18 19 SIC CTM7 PWSM Status Interrupt Control Registers 18 19 RAMBAH RAM Array Base Address High Register RAMBAL RAM Array Base Address Low Register RAMMCR RAM Module Configuration Register RAMTST RAM Test Register RJURR 0 7 ADC Right Justified Unsigned Result Registers 0 7 ROMBAH ROM Base Address High Register ROMBAL ROM Base Address Low Register ROMBSJ 0 3 ROM Bootstrap Words 0 3 RSR SCIM2 Reset Status Register SCCR 0 1 SCI Control Registers 0 1 SCDR SCI Data Register MOTOROLA NOMENCLATURE MC68HC16R1 916R1 2 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Mnemonic Register SCSR SCI Status Register SCIM2CR SCIM2 Module Configuration Register SCIM2TR SCIM2 Test Register SCIM2TRE SCIM2 Test Register ECLK 51 6 81 10 1 2 14 116 CTM7 SASM A Status Interrupt Control Registers 6 8V 10 12 14 16 SIC 6 8 10 12 14 16 B CTM7 SASM B Status Interrupt Control Registers 6 8 10 12 14 16 S ey 8y 10y 12V 14 16 DATA CTM7 SASM A Data Registe
177. FFA44 Chip Select Pin Assignment Register 0 CSPARO YFFA46 Chip Select Pin Assignment Register 1 CSPAR1 YFFA48 Chip Select Base Address Register Boot CSBARBT YFFA4A Chip Select Option Register Boot CSORBT YFFA4C Chip Select Base Address Register 0 CSBARO MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 4 For More Information On This Product Go to www freescale com USER S MANUAL Freescale Semiconductor Inc Table D 2 SCIM2 Address Map Continued Address 15 8 7 0 YFFA4E Chip Select Option Address Register 0 CSORO YFFA5O Not Used YFFA52 Not Used YFFA54 Not Used YFFA56 Not Used YFFA58 Chip Select Base Address Register 3 CSBAR3 YFFA5A Chip Select Option Address Register 3 CSOR3 YFFA5C Not Used YFFASE Not Used YFFA60 Chip Select Base Address Register 5 CSBARS5 YFFA62 Chip Select Option Address Register 5 CSOR5 YFFA64 Chip Select Base Address Register 6 CSBAR6 YFFA66 Chip Select Option Address Register 6 CSOR6 YFFA68 Chip Select Base Address Register 7 CSBAR7 YFFAGA Chip Select Option Address Register 7 CSOR7 YFFA6C Chip Select Base Address Register 8 CSBAR8 YFFAGE Chip Select Option Address Register 8 CSOR8 YFFA70 Chip Select Base Address Register 9 CSBAR9 YFFA72 Chip Select Option Address Register 9 CSOR9 YFFA74 Chip Select Base Address Register 10 CSBAR10 YFFA76 Chip Select Option Address Register 10
178. FLAG THAT INDICATES WHETHER THE PROGRAM SEQUENCE IS GENERATING ERASE PULSES OR MARGIN PULSES FEEPROM PGM FLOW2TD Figure 8 2 Erasure Flow MC68HC16R1 916R1 FLASH EEPROM MODULE MOTOROLA USER S MANUAL For More Information On This Product 8 7 Go to www freescale com Freescale Semiconductor Inc MOTOROLA FLASH EEPROM MODULE MC68HC16R1 916R1 8 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 9 BLOCK ERASABLE FLASH EEPROM The 2 Kbyte block erasable flash EEPROM module BEFLASH serves as nonvolatile fast access ROM emulation memory It is used only in the MC68HC916R1 The module can be used for program code that must either execute at high speed or is frequently executed such as operating system kernels and stan dard subroutines or it can be used for static data that is read frequently The module can also be configured to provide bootstrap vectors for system reset 9 1 Overview The BEFLASH module consists of a control register block that occupies a fixed position in MCU address space and a 2 Kbyte flash EEPROM array that can be mapped to any 2 Kbyte boundary in MCU address space The array can be configured to reside in both program and data space or in program space alone The flash EEPROM array can be read as either bytes words or long words The module responds to back to back IMB accesses providing two bus cycle four system clocks ac
179. For More Information On This Product Go to www freescale com ADC 8 BIT ACCURACY MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc 5 v y ou ak ee S IDEAL TRANSFER CURVE gu M HM 10 BIT TRANSFER CURVE NO CIRCUIT ERROR QU C 4 d ee 5 ee T E rd PE 4 Tu 9 6 F z S of 4 VE A Ed A M ee MS P y 1241 L j L I L I 0 20 40 60 INPUT IN mV Vay VRL 5 120 V A 5 COUNT 2 5 mV INHERENT QUANTIZATION ERROR B CIRCUIT CONTRIBUTED 10 mV ERROR C 12 5 mV ABSOLUTE ERROR 2 5 10 BIT COUNTS ADC 10 BIT ACCURACY Figure A 21 10 Bit ADC Conversion Accuracy MC68HC16R1 916R1 USER S MANUAL Go to www freescale com For More Information On This Product MOTOROLA A 29 Freescale Semiconductor Inc Table A 14 BEFLASH Flash EEPROM Module Specifications Num Characteristic Symbol Min Max Unit Program Erase Supply Voltage 1 Read Operation VrpE Vpp 0 5 5 5 V Program Erase Verify Operation 11 4 12 6 Program Erase Supply Current 52 15 Read Operation Program Erase Verify Operation 50 A 2 Verify ENPE 0 ese H 15 mA Program Byte ENPE 1 30 mA Program Word ENPE 1 _ 4 mA Erase ENPE 1 3 Program Recovery Time tor 1 usecs 4 Program Pulse Width PWpp 20 25 usecs 5 Number of Program
180. IY AIZ ADDD and ADDE instructions decrease execution time by sign extending the 8 bit immediate operand to 16 bits then adding it to an appropriate register The MAC and RMAC instructions use an 8 bit immediate operand to specify two signed 4 bit index register offsets MC68HC16R1 916R1 CENTRAL PROCESSOR UNIT MOTOROLA USER S MANUAL For More Information On This Product 4 9 Go to www freescale com Freescale Semiconductor Inc PSHM and PULM instructions use an 8 bit immediate mask operand to indi cate which registers must be pushed to or pulled from the stack 4 6 2 Extended Addressing Modes Regular extended mode instructions contain ADDR 15 0 in the word following the op code The effective address is formed by concatenating the EK field and the 16 bit byte address EXT20 mode is used only by the JMP and JSR instructions These instruc tions contain a 20 bit effective address that is zero extended to 24 bits to give the in struction an even number of bytes 4 6 3 Indexed Addressing Modes In the indexed modes registers IX lY and IZ together with their associated extension fields are used to calculate the effective address For 8 bit indexed modes an 8 bit unsigned offset contained in the instruction is added to the value contained in an index register and its extension field For 16 bit modes a 16 bit signed offset contained in the instruction is added to the val ue contained in an index register and it
181. LL PEH b15 b0 MOTOROLA MC68HC16R1 916R1 4 24 USER S MANUAL Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles 7 V C RORW Rotate Right Word IND16 X 270E 999g 8 A A a al IND16 271E 999g 8 LLL TE he IND16 Z 272E 09999 8 EXT 273E hh Il 8 RTI Return from Interrupt SK SP 2 gt SK SP INH 2777 12 A A A Pull CCR SK SP 2 SK SP Pull PC PK PC 6 PK PC RTS4 Return from Subrou SK SP 2 gt SK SP INH 27F7 12 tine Pull PK SK SP 2 gt SK SP Pull PC PK PC 2 PK PC SBA Subtract B from A A INH 370A 2 AAA SBCA Subtract with Carry A M C gt A IND8 X 42 ff 6 A AAA from A IND8 Y 52 ff 6 IND8 Z 62 ff 6 IMM8 72 ii 2 IND16 X 1742 999g 6 IND16 Y 1752 999g 6 IND16 Z 1762 999g 6 EXT 1772 hh Il 6 2742 6 E Y 2752 6 E Z 2762 6 SBCB Subtract with Carry IND8 2 ff 6 A AAA from B IND8 Y D2 ff 6 IND8 Z E2 ff 6 IMM8 F2 ii 2 IND16 X 17C2 999g 6 IND16 Y 17D2 999g 6 IND16 Z 17E2 9999 6 17F2 hh Il 6 27 2 6 E Y 27D2 6 E Z 27E2 6 SBCD Subtract with Carry 0 M M 1 C D IND8 X 82 ff 6 A A
182. Loop The LOOPS bit in SCCR1 controls a feedback path in the data serial shifter When LOOPS is set the SCI transmitter output is fed back into the receive serial shifter TXD is asserted idle line Both transmitter and receiver must be enabled before entering loop mode MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 22 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 11 5 MCCI Initialization After reset the MCCI remains in an idle state Several registers must be initialized be fore serial operations begin A general sequence guide for initialization follows A Global 1 Configure MMCR a Write an interrupt arbitration number greater than zero into the IARB field b Clear the STOP bit if it is not already cleared 2 Interrupt vector and interrupt level registers MIVR ILSPI and ILSCI a Write the SPI SCI interrupt vector into MIVR b Write the SPI interrupt request level into the ILSPI and the interrupt request levels for the two SCI interfaces into the ILSCI 3 Port data register a Write a data word to PORTMC b Read a port pin state from PORTMCP 4 Pin control registers a Establish the direction of MCCI pins by writing to the MDDR b Assign pin functions by writing to the MPAR B Serial Peripheral Interface 1 Configure SPCR a Write a transfer rate value into the BAUD field b Determine clock phase CPHA and clock polarity
183. M 1 gt IND16 X 2700 gggg 8 A 0 1 Word 1 1 IND16 Y 2710 9999 8 M M 1 IND16 Z 2720 gggg 8 EXT 2730 hh Il 8 MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product Go to www freescale com 4 17 Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S Z CPD Compare D to Memory D M M 1 IND8 X 88 ff 6 AAA IND8 Y 98 ff 6 IND8 Z A8 ff 6 IMM16 37B8 jj Kk 4 IND16 X 37C8 9999 6 IND16 37D8 9999 6 IND16 2 37E8 999g 6 EXT 37F8 hh Il 6 2788 6 EY 2798 6 E Z 27A8 6 Compare E to Memory 1 IMM16 3738 jjkk 4 A IND16 X 3748 999g 6 IND16 Y 3758 9999 6 IND16 2 3768 9999 6 3778 hhil 6 CPS Compare Stack SP M M 1 IND8 X 4F ff 6 A Pointer to Memory IND8 Y 5F ff 6 IND8 Z 6F ff 6 IMM16 377F jj kk 4 IND16 X 174F 999g 6 IND16 Y 175F 0999 6 IND16 2 176F 999g 6 EXT 177F hh Il 6 CPX Compare IX to IX M M 1 IND8 X 4C ff 6 A A Memory IND8 Y 5 ff 6 IND8 Z 6 ff 6 IMM16 377C jj kk 4 IND16 X 174 9999 6 IND16 Y 175C 9999 6 IND16 2 176C gggg 6 EXT 177 hh Il 6 CPY Compare IY to IY M M 1 IN
184. MM must remain set to logic 1 on all CPU16 derivatives in order for MCU control registers to remain accessible As discussed in 3 5 CPU16 Memory Mapping CPU16 address lines 19 0 drive IMB address lines 19 0 and CPU16 address line 19 drives IMB address lines 23 20 For this reason addresses between 080000 and F7FFFF will never be seen on the IMB Setting MM to logic 0 on the MC68HC16R1 and MC68HC916R1 would map the con trol registers from 7FF700 to 7FFC3F where they would be inaccessible until a reset occurs As long as MM is set to logic 1 MCU control registers will be accessible and the CPU16 need only generate 20 bit effective addresses to access them Thus to access SCIMCR which is mapped at IMB address 00 the CPU16 must generate the 20 bit effective address FFAOO MC68HC16R1 916R1 OVERVIEW MOTOROLA USER S MANUAL For More Information On This Product 3 17 Go to www freescale com MOTOROLA 3 18 000000 YFF700 YFF73F YFF820 YFF83F YFF900 YFF9FF YFFA00 Y FFATF Y FF B00 YFFBO7 YFFCOO YFFC3F FFFFFF Freescale Semiconductor Inc ADC 64 BYTES ROM CONTROL 32 BYTES CTM7 256 BYTES SCIM2 128 BYTES SRAM CONTROL 8 BYTES MCCI 64 BYTES 48K ROM ARRAY 2K SRAM ARRAY Figure 3 6 MC68HC16 R1 Address Map OVERVIEW For More Information On This Product Go to www freescale com MC68HC16
185. MOTOROLA USER S MANUAL xi For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 12 10 10 PWM Period and Pulse Width Register Values 12 19 12 10 10 1 PWM Duty Cycle Boundary Cases 12 19 12 10 11 PWMSM Registers 12 20 12 11 7 12 20 APPENDIX A ELECTRICAL CHARACTERISTICS APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION B 1 Obtaining Updated MC68HC16R1 916R1 MCU Mechanical Information B 5 B 2 Ordering Infotimalloli z oce pocos 5 APPENDIX DEVELOPMENT SUPPORT C 1 M68MMDS1632 Modular Development System C 1 C 2 M68MEVB1632 Modular Evaluation Board C 1 APPENDIX D REGISTER SUMMARY D 1 Central Processing Unit zi saei iip etes d diese koe int D 1 D 1 1 Condition Code Register bcr rn E torta D 3 D 2 Single Chip Integration Module 2 D 4 D 2 1 Configuration Register 0 001 D 6 D 2 2 SCIM Test Register cs testa bct Spe AS e D 7 D 2 3 Clock Synthesizer Control Register D 8 D 2 4 Reset S
186. Mode for SPI Pins 0 Outputs have normal CMOS drivers 1 Pins designated for output by MDDR have open drain drivers regardless of whether the pins are used as SPI outputs or for general purpose I O and regardless of whether the SPI is enabled MSTR Master Slave Mode Select 0 SPI is a slave device 1 SPI is system master CPOL Clock Polarity 0 The inactive state value of SCK is logic level zero 1 The inactive state value of SCK is logic level one CPOL is used to determine the inactive state of the serial clock 5 It is used with CPHA to produce a desired clock data relationship between master and slave devices CPHA Clock Phase 0 Data captured on the leading edge of SCK and changed on the trailing edge of SCK 1 Data is changed on the leading edge of SCK and captured on the trailing edge of SCK CPHA determines which edge of SCK causes data to change and which edge causes data to be captured is used with CPOL to produce a desired clock data rela tionship between master and slave devices LSBF Least Significant Bit First 0 Serial data transfer starts with LSB 1 Serial data transfer starts with MSB MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product 0 51 Go to www freescale com Freescale Semiconductor Inc SIZE Transfer Data Size 0 8 bit data transfer 1 16 bit data transfer SPBR 7 0 Serial Clock Baud Rate The SPI uses a modulus
187. More Information On This Product 10 19 Go to www freescale com Freescale Semiconductor Inc VDD kR EXTERNAL VOLTAGE gt TO DEVICE VSS ADC NEG STRESS CONN Figure 10 8 Voltage Limiting Diodes in a Negative Stress Circuit Another method for minimizing the impact of stress conditions on the ADC is to stra tegically allocate ADC inputs so that the lower accuracy inputs are adjacent to the in puts most likely to see stress conditions Finally suitable source impedances should be selected to meet design goals and min imize the effect of stress conditions 10 8 5 Analog Input Considerations The source impedance of the analog signal to be measured and any intermediate fil tering should be considered whether external multiplexing is used or not Figure 10 9 shows the connection of eight typical analog signal sources to one ADC analog input pin through a separate multiplexer chip Also an example of an analog signal source connected directly to a ADC analog input channel is displayed MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC16R1 916R1 10 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc FILTERING AND i eae MC54HC4051 MC74HC4051 ANALOG SIGNAL SOURCE INTERCONNECT MC54HC4052 MC74HC4052 INTERCONNECT A
188. N 7 MASKED ROM MODULE MC68HC16R1 916R1 MOTOROLA USER S MANUAL vii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 7 1 MEM Register Block ar EL eb e Ou dE ERE 7 1 7 2 MRM Array Address Mapping 7 1 7 3 MRM Array Address Space 7 2 7 4 Normal ACCESS oe ota cost tester 7 2 7 5 Low Power Stop Mode Operation 7 3 7 6 iP Ese RR AA 7 3 7 7 s 7 3 SECTION 8 FLASH EEPROM MODULE 8 1 Flash EEPROM Control Block a 8 1 8 2 Flash EEPROM AWay ae 8 2 8 3 Flash EEPROM 52 8 2 8 3 1 Reset 8 2 8 3 2 Bootstrap Operation ceo tue ia tt tp Lon Eee 8 3 8 3 3 Normal Operation dudo dece ae Teer a S LA A A EL 8 3 8 3 4 Program Erase Operation sess 8 3 8 3 5 Programi irig ee TEC EE 8 4 8 3 5 1 ELA SUID octo d A ute dis 8 5 SECTION 9 BLOCK ERASABLE FLASH EEPROM 9 1 OI AMORC 9 1 9 2 BEFLASH Control Block b
189. ND16 Y 3751 9999 6 IND16 Z 3761 9999 6 EXT 3771 hh II 6 ADE Add D to E D SE INH 2778 2 A AAA ADX Add D to IX XK IX 20 lt D gt INH 37CD 2 XK IX ADY Add D to IY YK IY 20 D gt INH 37DD 2 YK IY ADZ Add D to IZ ZK IZ 20 D gt INH 37ED 2 ZK IZ AEX Add E to IX XK IX 20 lt E gt INH 374D 2 XK IX AEY Add E to IY 20 E gt INH 375D 2 YK IY AEZ Add E to IZ ZK IZ 20 lt E gt INH 376D 2 ZK IZ AIS Add Immediate Data SK SP 20 IMM IMM8 3F ii 2 to Stack Pointer SK SP IMM16 373F jj kk 4 AIX Add Immediate Value XK IX 20 lt IMM IMM8 3C ii 2 A to IX XK IX IMM16 373C jj kk 4 Add Immediate Value YK IY 20 lt IMM IMM8 3D ii 2 A to IY 16 3730 jj kk 4 AIZ Add Immediate Value ZK IZ 20 lt IMM gt IMM8 3E ii 2 A to IZ ZK IZ IMM16 373E jj kk 4 ANDA ANDA gt A IND8 46 ff 6 A 0 IND8 Y 56 ff 6 IND8 Z 66 ff 6 IMM8 76 ii 2 IND16 X 1746 9999 6 IND16 Y 1756 9999 6 IND16 Z 1766 9999 6 1776 hh Il 6 E X 2746 6 2756 6 2 2766 6 MC68HC16R1 916R1 MOTOROLA USER S MANUAL 4 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued
190. NUAL For More Information On This Product 8 1 Go to www freescale com Freescale Semiconductor Inc Four additional flash EEPROM words in the control block can contain bootstrap information for use during reset Control registers are located in supervisor data space Refer to D 8 Flash EEPROM Modules for register and bit field information The control register blocks for the 16 and 32 Kbyte flash EEPROM modules start at locations YFF800 and YFF820 respectively The following register descriptions ap ply to the corresponding register in either control block References to FEExMCR for example apply to both FEE1MCR in the 16 Kbyte module and FEE2MCR in the 32 Kbyte module A number of control register bits have associated bits in shadow registers The values of the shadow bits determine the reset states of the control register bits Shad OW registers are programmed or erased in the same manner as a location in the array using the address of the corresponding control registers When a shadow register is programmed the data is not written to the corresponding control register The new data is not copied into the control register until the next reset The contents of shadow registers are erased when the array is erased Configuration information is specified and programmed independently of the array After reset registers in the control block that contain writable bits can be modified Writes to these registers do not affect t
191. O Chip Select Pin Assignment Register 0 YFFA44 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 5 CS4PADLOJ CS3PA L 0 CS2P A L 0 CSIPAILO csoang CSBTPAILO RESET 0 0 DATA2 1 DATA2 1 DATA2 1 DATA1 1 DATA1 1 DATA1 1 1 DATAO Chip select pin assignment registers configure the chip select pins for discrete I O an alternate function or as an 8 bit or 16 bit chip select The possible encodings for each 2 bit field in CSPAR 0 1 except for CSBTPA 1 0 are shown in Table D 8 Table D 8 Pin Assignment Field Encoding CSxPA 1 0 Description 00 Discrete output 01 Alternate function 10 Chip select 8 bit port 11 Chip select 16 bit port NOTES 1 Does not apply to the CSBOOT field This register contains seven 2 bit fields that determine the function of corresponding chip select pins Bits 15 14 are not used These bits always read zero writes have no effect CSPARO bit 1 always reads one writes to CSPARO bit 1 have no effect The alternate functions can be enabled by data bus mode selection during reset This register may be read or written at any time After reset software may enable one or more pins as discrete outputs Table D 9 shows CSPARO pin assignments MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 18 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table D 9 CSPARO Pin Assignments
192. O DIGITAL CONVERTER MC68HC16R1 916R1 10 22 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc In Figure 10 10 Re and comprise the user s external filter circuit Cs is the internal sample capacitor Each channel has its own capacitor is never precharged it retains the value of the last sample V is an internal voltage source used to precharge the DAC capacitor array before each sample The value of this supply is 2 or 2 5 volts for 5 volt operation The following paragraphs provide a simplified description of the interaction between the ADC and the user s external circuitry This circuitry is assumed to be a simple RC low pass filter passing a signal from a source to the ADC input pin The following sim plifying assumptions are made source impedance is included with the series resistor of the RC filter external capacitor is perfect no leakage no significant dielectric absorption characteristics etc All parasitic capacitance associated with the input pin is included in the value of the external capacitor Inductance is ignored resistance of the internal switches is zero ohms and the off resistance is infinite 10 8 6 1 Settling Time for the External Circuit The values for Re and in the user s external circuitry determine the length of time required to charge Cr to the source volta
193. ONTROL FE0000 77 YFFC00 BAKM 7 7 FE0000 FF0000 ki 77 YFFC3F BAKIS FF0000 YFFDFF INTERNAL REGISTERS Y FFFFFF Y Y FFFFFF OTE 1 THE ADDRESSES DISPLA YED IN THIS MEMOR Y ARE THE FULL 24 IMB ADDRESSES CPU16 ADDRESS B US IS 20 BITS WIDE AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES 23 20 THE BLOCK OF ADDRESSES FR OM 080000 TO F7FFFF MARKED AS UNDEFINED WILLNEVER APPEAR ON THE IMB MEMOR Y BANKS 0 TO 15 APPEAR FULL Y CONTIGUOUS IN THE 165 FLA T 20 BIT ADDRESS SP ACE THE CPU16 NEED ONL Y GENERA TE A 20 BIT EFFECTIVE ADDRESS ACCESS ANY LOCA TION IN THIS RANGE 916R1 MEM MAP 5 Figure 3 11 MC68HC916R1 Separate Program and Data Space Map MOTOROLA OVERVIEW MC68HC16R1 916R1 3 24 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc MC68HC16R1 916R1 OVERVIEW MOTOROLA USER S MANUAL For More Information On This Product 3 25 Go to www freescale com Freescale Semiconductor Inc MOTOROLA OVERVIEW MC68HC16R1 916R1 3 26 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 4 CENTRAL PROCESSOR UNIT This section is an overview of the central processor unit CPU16 For detailed infor mation refer to the CPU16 Reference Manual CPU16RM AD 4 1 General The CPU16 provides compatibility with the M68HC11 CPU and also provides addition
194. OTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc FIRST CPSM PRESCALER 5 42 08 3 8 BIT i 4 f 16 foyer 24 PRESCALER sys sys PCLK5 5 222 48 64 SELECT ma PCLK6 fs 64 96 128 fsy 192 256 fsys 384 fsys 512 768 P DIV23 2 DIV23 3 PRUN DIV23 PSEL1 PSELO CPCR CTM CPSM BLOCK Figure 12 2 CPSM Block Diagram 12 5 1 CPSM Registers The CPSM contains a control register CPCR and a test register CPTR All unused bits and reserved address locations return zero when read Writes to unused bits and reserved address locations have no effect Refer to D 7 4 CPSM Control Register and D 7 5 CPSM Test Register for information concerning CPSM register and bit descriptions 12 6 Free Running Counter Submodule FCSM The free running counter submodule FCSM has a 16 bit up counter with an associ ated clock source selector selectable time base bus drivers control registers status bits and interrupt logic When the 16 bit up counter overflows from FFFF to 0000 an optional overflow interrupt request can be generated The current state of the 16 bit counter is the primary output of the counter submodules The user
195. One external clock pin for the modulus and free running counter submodules 3 2 Intermodule Bus The intermodule bus IMB is a standardized bus developed to facilitate the design and operation of modular microcontrollers It contains circuitry that supports exception pro cessing address space partitioning multiple interrupt levels and vectored interrupts The standardized modules in the MCU communicate with one another through the IMB Although the full IMB supports 24 address and 16 data lines CPU16 based MCUs use only 20 address lines ADDR 23 20 follow the state of ADDR19 MOTOROLA OVERVIEW MC68HC16R1 916R1 3 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 3 3 System Block Diagram and Pin Assignment Diagrams Figures 3 1 and 3 2 show functional block diagrams of MC68HC16R1 and MC68HC916R1 MCUs Although diagram blocks represent the relative location of the physical modules there is not a one to one correspondence between the location and size of blocks in the diagram and the location and size of modules on the integrated circuit Figures 3 3 and 3 4 shows the pin assignments for the MC68HC16R1 and MC68HC916R1 MCUs in a 132 pin plastic surface mount package Refer to APPEN DIX MECHANICAL DATA AND ORDERING INFORMATION for package dimensions Refer to subsequent paragraphs in this section for pin and signal descriptions MC68HC16R1 916R1 OVERVIEW MOTOROLA USER S
196. PA6 PA5 PA4 PA3 PA2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 1 0 RESET U U U U U U U U U U U U U U U U Ports A and B are available in single chip mode only PORTA and PORTB can be read or written any time the MCU is not in emulator mode D 2 7 Port G and H Data Registers PORTG Port G Data Register YFFAOC PORTH Port H Data Register YFFAOD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PG7 PG6 PG5 PG4 PG2 PG1 PGO PH7 PH6 5 4 PH3 PH2 PH1 PHO RESET U U U U U U U U U U U U U U U U Port G is available in single chip mode only These pins are always configured for use as general purpose I O in single chip mode Port H is available in single chip and 8 bit expanded modes only The function of these pins is determined by the operating mode There is no pin assignment register asso ciated with this port These port data registers can be read or written any time the MCU is not in emulation mode Reset has no effect D 2 8 Port G and H Data Direction Registers DDRG Port G Data Direction Register YFFAOE DDRH Port H Data Direction Register YFFAOF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0067 0066 0065 DDG4 0063 0062 DDG1 DDGO DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDHO RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The bits in this register control the direction of the port pin drivers when pi
197. PI node requested to become the network SPI master while the SPI was enabled in master mode SS input taken low The SPI asserts MODF when the SPI is in master mode MSTR 1 and the SS input pin is negated by an external driver D 6 15 SPI Data Register SPDR SPI Data Register YFFC3E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UPPB 0 LOWB 7 0 RESET U U U U U U U U U U U U U U U U UPPB Upper Byte In 16 bit transfer mode the upper byte is contains the most significant 8 bits of the transmitted or received data Bit 15 of the SPDR is the MSB of the 16 bit data LOWB Lower Byte In 8 bit transfer mode the lower byte contains the transmitted or received data MSB in 8 bit transfer mode is bit 7 of the SPDR In 16 bit transfer mode the lower byte holds the least significant 8 bits of the data MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product D 53 Go to www freescale com
198. PIPEO DSO 16 BDM SER COM TIM Figure A 13 Background Debug Mode Timing Diagram Serial Communication MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product A 19 Go to www freescale com Freescale Semiconductor Inc CLKOUT FREEZE IPIPET DSI 16 BDM FRZ TIM Figure A 14 Background Debug Mode Timing Diagram Freeze Assertion Table A 8 ECLK Bus Timing Vpp and V5os 5 0 Vde 5 Vss 0 T T to T Num Characteristic Symbol Min Max Unit E1 ECLK Low to Address Valid teap 60 ns E2 ECLK Low to Address Hold tEAH 10 ns ECLK Low to CS Valid CS Delay tecsp 150 ns 4 ECLK Low to CS Hold tecsH 15 ns E5 5 Negated Width tecsn 30 ns E6 Read Data Setup Time tEpsn 30 ns E7 Read Data Hold Time tEpHR 15 ns 8 ECLK Low to Data High Impedance tEDHZ 60 ns E9 CS Negated to Data Hold Read 0 ns E10 CS Negated to Data High Impedance tecpz 1 E11 ECLK Low to Data Valid Write teppw 2 E12 Low to Data Hold Write tEDHW 5 m ns E13 CS Negated to Data Hold Write tEcuw 0 ns E14 Address Access Time Read teacc 386 ns E15 Chip Select Access Time Read tEACS 296 ns E16 Address Setup Time teas 1 2 NOTES 1 All AC timing is shown with respect to Vi Vi levels unless otherwise noted 2 When previous bus cycle is not
199. Pulses thes 50 6 Program Margin Pm 100 7 Number of Erase Pulses 5 8 Erase Pulse Time x k tepk 90 550 ms 9 Amount to Increment tep tei 90 110 ms Erase Margin 10 tei x k em 90 1650 ms k 1 11 Erase Recovery Time ter 1 ms 12 Low Power Stop Recovery Time 6 tsb 1 usecs NOTES 1 Vepe must not be raised to programming voltage while Vpp is below specified minimum value Vepe must not be reduced below minimum specified value while Vpp is applied 2 Current parameters apply to each individual EEPROM module 3 Minimum software delay from the end of the write cycle that clears ENPE bit to the read of the flash array 4 Without margin 5 At 100 margin the number of margin pulses required is the same as the number of pulses used to program the byte or word 6 Minimum software delay from the end of the write cycle that clears the STOP bit to the read of the flash array Table A 15 BEFLASH Flash EEPROM Module Life Num Parameter Symbol Value Unit 1 Program Erase Endurance 100 2 Data Retention 10 NOTES 1 Number of program erase cycles 1 to 0 0 to 1 per bit 2 Parameter based on accelerated life testing with standard test pattern MOTOROLA MC68HC16R1 916R1 A 30 For More Information On This Product Go to www freescale com USER S MANUAL Freescale Semiconductor Inc 30 ns MAXIMUM 13 5 V ENVELOPE 12 6V Vpp ENVELOPE 114V
200. R S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 10 3 Prescaler Output 5 4 0 ADCClock System Clock System Clock 00000 Reserved 00001 System Clock 4 2 0 MHz 8 4 MHz 00010 System Clock 6 3 0 MHz 12 6 MHz 0001 1 System Clock 8 4 0 MHz 16 8 MHz 11101 System Clock 60 30 0 MHz 2611110 System Clock 62 31 0 MHz 9611111 System Clock 64 32 0 MHz ADC clock speed must be between 0 5 MHz and 2 1 MHz The reset value of the PRS field is 9600011 which divides a nominal 16 78 MHz system clock by eight yielding maximum ADC clock frequency There are a minimum of four IMB clock cycles for each ADC clock cycle 10 7 3 Sample Time The first two portions of all sample periods require four ADC clock cycles During the third portion of a sample period the selected channel is connected directly to the RC DAC array for a specified number of clock cycles The value of the STS field in ADCTLO determines the number of cycles Refer to Table 10 4 The number of clock cycles required for a sample period is the value specified by STS plus four Sample time is determined by PRS value Table 10 4 Sample Time Selection STS 1 0 Sample Time 00 2 ADC Clock Periods 01 4 ADC Clock Periods 10 8 ADC Clock Periods 11 16 ADC Clock Periods 10 7 4 Resolution ADC resolution can be either eight or ten bits Resolution is determined by the stat
201. R1 10 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Mode 2 A single conversion is performed on each of four sequential input channels starting with the channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT3 The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the last conversion is complete Mode 3 A single conversion is performed on each of eight sequential input chan nels starting with the channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT7 The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the last conversion is complete Mode 4 Continuous four conversion sequences are performed on a single input channel specified by the value in CD CA Each result is stored in a separate result reg ister RSLTO to RSLT3 Previous results are overwritten when a sequence repeats The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in AD STAT is set when the first four conversion sequence is complete Mode 5 Continuous eight conversion sequences are performed on a single input channel specified by the value in CD CA Each result is stored in a separate result reg ister RSLTO to RSLT7 Previous results are overwritten when a seque
202. R1ADDRESS MAP MC68HC16R1 916R1 USER S MANUAL 000000 Y FF 700 Y FF 73F YFF7A0 Y FF 7BF Y FF 800 YFF820 YFF83F YFF900 YFFOFF Y FFA00 YFFATF YFFBOO YFFBO7 00 YFFC3F FFFFFF MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc ADC 64 BYTES 2K BLOCK ERASEABLE FLASH EEPROM CONTROL 32 BYTES 2K BEFLASH EEPROM ARRAY 16K FLASHEEPROM CONTROL 32 BYTES 16K FLASH EEPROM ARRAY 32K FLASH EEPROM CONTROL 32 BYTES 32K FLASH EEPROM ARRAY CTM7 256 BYTES SCIM2 128 BYTES SRAM CONTROL 8 BYTES 2K SRAM ARRAY 64 5 MC68HC916R1 ADDRESS Figure 3 7 MC68HC916R1 Address Map OVERVIEW For More Information On This Product Go to www freescale com MOTOROLA 3 19 Freescale Semiconductor Inc 3 7 Address Space Maps Figures 3 10 and 3 11 show CPU16 address space for the MC68HC16R1 MCU Figures 3 10 and 3 11 show CPU16 address space for the MC68HC916R1 MCU Address space can be split into physically distinct program and data spaces by decoding the MCU function code outputs Figures 3 10 and 3 10 show the memory map of a system that has combined program and data spaces Figures 3 11 and 3 11 show the memory map when MCU function code outputs are decoded Reset and exception vectors are mapped into bank 0 and cannot
203. RAMMING Y REDUCE 1 NORMAL READ LEVEL EXIT PROGRAM ROUTINE 2 THE MARGIN FLAG IS A SOFTWARE DEFINED FLAG THAT INDICATES WHETHER THE PROGRAM SEQUENCE IS GENERATING PROGRAM PULSES OR MARGIN PULSES 3 TO SIMPLIFY THE PROGRAM OPERATION THE V ppg BIT IN FEEXCTL CAN BE SET 4 CLEAR V fpg BIT ALSO IF ROUTINE USES THIS FUNCTION Figure 8 1 Programming Flow MOTOROLA FLASH EEPROM MODULE 8 6 For More Information On This Product Go to www freescale com FEEPROM PGM FLOWI TD MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc REDUCE Vepg TO 1 PROGRAM ERASE VERIFY LEVEL Y CLEAR n COUNTER j CLEAR MARGIN FLAG SET LAT SET ERAS OR CONTROL BLOCK Y SET ENPE Y START ERASE PULSE TIMER Y DELAY FOR tepk Y WRITE TO ARRAY CLEAR ENPE START ty TIMER Y DELAY FOR tpr MARGIN FL SET CLEAR LAT CALCULATE NEW READ ARRAY AND SHADOW REGISTERS TO VERIFY ERASE ALL LOCATIONS ERASED CALCULATE EM gt SET te EM SET MARGIN FLAG Y INCREMENT n COUNTER Y Y ARRAY FAILED TO ERASE Y REDUCE VFPETO 1 NORMAL READ LEVEL NOTES EXIT ERASE ROUTINE 1 SEE ELECTRICAL CHARACTERISTICS FOR ppg PIN VOLTAGE SEQUENCING 2 THE MARGIN FLAG IS A SOFTWARE DEFINED
204. RANSMITTED CHARACTER 1 5 TRANSFER Figure 11 4 1 SPI Transfer Format For a master writing to the SPDR initiates the transfer For a slave the first edge of SCK indicates the start of a transfer The SPI is left shifted on the first and each succeeding odd clock edge and data is latched on the second and succeeding even clock edges SCK is inactive for the last half of the eighth SCK cycle For a master SPIF is set at the end of the eighth SCK cycle after the seventeenth SCK edge Since the last SCK edge occurs in the middle of the eighth SCK cycle however the slave has no way of knowing when the end of the last SCK cycle occurs The slave therefore considers the transfer complete after the last bit of serial data has been sampled which corresponds to the middle of the eighth SCK cycle When CPHA is one the SS line may remain at its active low level between transfers This format is sometimes preferred in systems having a single fixed master and only one slave that needs to drive the MISO data line MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 10 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 11 3 5 SPI Serial Clock Baud Rate Baud rate is selected by writing a value from 2 to 255 into SPBR 7 0 in the SPCR of the master MCU Writing a SPBR 7 0 value into the SPCR of the slave device has no effect The SPI uses a modulu
205. ROM module does not acknowledge IMB accesses while in emulation mode This causes the SCIM2 to run an external bus cycle for each access NOTE The MC68HC916R1 flash modules do not yet support the emulator mode If ROM emulation is enabled the CSM chip select will be driven high at all times 5 7 4 MCU Module Pin Function During Reset Usually module pins default to port functions and input output ports are set to input state This is accomplished by disabling pin functions in the appropriate control registers and by clearing the appropriate port data direction registers Refer to individual module sections in this manual for more information Table 5 20 is a summary of module pin function out of reset Refer to APPENDIX D REGISTER SUM MARY for register function and reset state MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 51 Go to www freescale com Freescale Semiconductor Inc Table 5 20 Module Pin Functions Module Pin Mnemonic Function ADC PADA 7 O AN 7 0 Discrete input Reference voltage VRL Reference voltage CPU DSI IPIPE1 DSI IPIPE1 DSO IPIPEO DSO IPIPEO BKPT DSCLK BKPT DSCLK CTM7 CPWM 19 18 Discrete output CTS16 A B Discrete input CTS14 A B Discrete input CTS12 A B Discrete input CTS10 A B Discrete input 58 Discrete input CTS6 A B Discre
206. Refer to the CPU16 Reference Manual CPU16RM AD for more information on the CLKOUT signal state signals and state signal demux logic 4 14 1 2 Combining Opcode Tracking with Other Capabilities Pipeline state signals are useful during normal instruction execution and execution of exception handlers The signals provide a complete model of the pipeline up to the point a breakpoint is acknowledged Breakpoints are acknowledged after an instruction has executed when it is in pipeline Stage A breakpoint can initiate either exception processing or background debug ging mode IPIPEO IPIPE1 are not usable when the CPU16 is in background debug ging mode 4 14 2 Breakpoints Breakpoints are set by assertion of the microcontroller BKPT pin The CPU16 supports breakpoints on any memory access Acknowledged breakpoints can initiate either ex ception processing or background debug mode After BDM has been enabled the CPU16 will enter BDM when the BKPT input is asserted e If BKPT assertion is synchronized with an instruction prefetch the instruction is tagged with the breakpoint when it enters the pipeline and the breakpoint occurs after the instruction executes MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product 4 41 Go to www freescale com Freescale Semiconductor Inc e If BKPT assertion is synchronized with an operand fetch breakpoint processing occurs at the end of the instruction during which BKP
207. Right A INH 370F 2 0 A M 09 TT b7 bo LSRB Logical Shift Right B INH 371F 2 0 AAA gt 9 4 b7 00 LSRD Logical Shift Right D INH 27FF 2 0 AAA SLLL TL LSRE Logical Shift Right E INH 277F 2 0 AAA i b15 x m LSRW Logical Shift Right IND16 X 270F 9999 8 0 A Word IND16 Y 271F gggg 8 CTL IPE IND16 Z 272F 9999 8 27 hh Il 8 MAC Multiply and HR IR gt E D IMM8 7B 12 Accumulate E D Signed 16 Bit Qualified IX IX Fractions Qualified IY 2 IY HR 2 IZ M M 1 HR M M 1 y S IR MOVB Move Byte Mi 2 Mo IXP to EXT 30 ff hh Il 8 a 0 EXT to IXP 32 ff hh Il 8 EXT to 37FE hh Il hh Il 10 EXT MOVW Move Word 13 15 IXP to EXT 31 ff hh Il 8 A 0 EXT to IXP 33 ff hh Il 8 EXT to 37FF hh Il hh Il 10 EXT MUL Multiply D INH 3724 10 A NEG Negate Memory 00 M 2 IND8 X 02 ff 8 A AAA IND8 Y 12 ff 8 IND8 Z 22 ff 8 IND16 X 1702 999g 8 IND16 Y 1712 999g 8 IND16 Z 1722 999g 8 EXT 1732 hh Il 8 NEGA Negate A 00 A A INH 3702 x 2 A AAA NEGB Negate B 00 B 2 B INH 3712 2 A AA NEGD Negate D 0000 D D INH 27F2 2 SS SAS AT A A NEGE Negate E 0000 E 2 E INH 2772 2 A AAA NEGW Negate Memory Wor
208. SLT3 0 1 0 X X Reserved RSLTO Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 0 1 1 X X VRH RSLTO VRL RSLT1 2 RSLT2 Test Reserved RSLT3 1 0 X X X ANO RSLTO AN1 RSLT1 AN2 RSLT2 RSLT3 AN4 RSLT4 AN5 RSLT5 AN6 RSLT6 AN7 RSLT7 1 1 X X X Reserved RSLTO Reserved RSLT1 Reserved RSLT2 Reserved RSLT3 RSLT4 VRL RSLT5 2 RSLT6 Test Reserved RSLT7 NOTES 1 Result register RSLT is either RJURRX LJSRRX or LJURRX depending on the address read MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For More Information On This Product 10 11 Go to www freescale com Freescale Semiconductor Inc 10 7 6 Conversion Timing Total conversion time is made up of initial sample time transfer time final sample time and resolution time Initial sample time is the time during which a selected input chan nel is connected to the sample buffer amplifier through a sample capacitor During transfer time the sample capacitor is disconnected from the multiplexer and the RC DAC array is driven by the sample buffer amp During final sampling time the sample capacitor and amplifier are bypassed and the multiplexer input charges the RC DAC array directly During resolution time the voltage in the RC DAC array is converted to a digital value and the value is stored in the SAR Initial sample time and transfer time are fixed at two ADC clock cycles each Final sam ple time can be 2 4 8
209. STREF All G DATA 15 8 Single chip H DATA 7 0 Single chip 8 Bit expanded SINGLE CHIP INTEGRATION MODULE 2 For More Information On This Product Go to www freescale com MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc Access to the port A B E F G and H data and data direction registers and the port C E and F pin assignment registers require three clock cycles to ensure timing com patibility with external port replacement logic Port registers are byte addressable and are grouped to allow coherent word access to port data register pairs A B and G H as well as word aligned long word coherency of A B G H port data registers If emulation mode is enabled the emulation mode chip select signal CSE is asserted whenever an access to ports A B E G and H data and data direction registers or the port E pin assignment register is made The SCIM2 does not respond to these access es but allows external logic such as a Motorola port replacement unit PRU MC68HC33 to respond Port C data and data direction register port F data and data direction register and the port F pin assignment register remain accessible A write to the port A B E F G or H data register is stored in the internal data latch If any port pin is configured as an output the value stored for that bit is driven on the pin A read of the port data register returns the value at the pin only if the pin is config ured as a discrete input O
210. T 0 NOTES 1 ALL CHIP SELECT LINES IN THIS EXAMPLE MUST BE CONFIGURED AS 16 BIT Figure 5 20 Basic MCU System MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 USER S MANUAL For More Information On This Product Go to www freescale com MC68HC681 ASYNC BUS PERIPHERAL HC16 SIM SCIM BUS MOTOROLA 5 61 Freescale Semiconductor Inc Chip select assertion can be synchronized with bus control signals to provide output enable read write strobe or interrupt acknowledge signals Logic can also generate DSACK and AVEC signals internally A single DSACK generator is shared by all chip selects Each signal can also be synchronized with the ECLK signal available on ADDR23 When a memory access occurs chip select logic compares address space type address type of access transfer size and interrupt priority in the case of interrupt acknowledge to parameters stored in chip select registers If all parameters match the appropriate chip select signal is asserted Select signals are active low If a chip select function is given the same address as a microcontroller module or an internal memory array an access to that address goes to the module or array and the chip select signal is not asserted The external address and data buses do not reflect the internal access All chip select circuits are configured for operation out of reset However all chip select signals except CSBOOT are disabled and cannot be asserted
211. T is latched Breakpoints on instructions that are flushed from the pipeline before execution are not acknowledged Operand breakpoints are always acknowledged There is no break point acknowledge bus cycle when BDM is entered Refer to 5 6 4 1 Breakpoint Ac knowledge Cycle for more information about breakpoints 4 14 3 Opcode Tracking and Breakpoints Breakpoints are acknowledged after a tagged instruction has executed that is when the instruction is copied from pipeline stage B to stage C Stage C contains the opcode of the previous instruction when execution of the current instruction begins When an instruction is tagged IPIPEO IPIPE1 reflect the start of execution and the ap propriate number of pipeline advances and operand fetches before the breakpoint is acknowledged If background debug mode is enabled these signals model the pipe line before BDM is entered 4 14 4 Background Debug Mode Microprocessor debugging programs are generally implemented in external software CPU16 BDM provides a debugger implemented in CPU microcode BDM incorporates a full set of debug options Registers can be viewed and altered memory can be read or written and test features can be invoked BDM is an alternate CPU16 operating mode While the CPU16 is in BDM normal instruction execution is suspended and special microcode performs debugging functions under external control While in BDM the CPU16 ceases to fetch instructions through the data bus
212. TO WRITE 2 DRIVE ADDRESS ON ADDR 23 0 3 DRIVE FUNCTION CODE ON FC 2 0 4 DRIVE SIZ 1 0 FOR OPERAND SIZE ASSERT 5 51 Y PLACE DATA ON DATA 15 0 52 PERIPHERAL ASSERT DS AND WAIT FOR DSACK 53 OPTIONAL STATE 54 NO CHANGE Y ACCEPT DATA 52 53 1 DECODE ADDRESS 2 LATCH DATA FROM DATA BUS 3 ASSERT DSACK SIGNALS TERMINATE OUTPUT TRANSFER S5 1 NEGATE DS AND 5 2 REMOVE DATA FROM DATA BUS TERMINATE CYCLE START NEXT CYCLE NEGATE DSACK Figure 5 12 Write Cycle Flowchart 5 6 3 Fast Termination Cycles When an external device can meet fast access timing an internal chip select circuit fast termination option can provide a two cycle external bus transfer Because the chip select circuits are driven from the system clock the bus cycle termination is in herently synchronized with the system clock SINGLE CHIP INTEGRATION MODULE 2 For More Information On This Product Go to www freescale com WR CYC FLOW If multiple chip selects are to be used to provide control signals to a single device and match conditions occur simultaneously all MODE STRB and associated DSACK fields must be programmed to the same value This prevents a conflict on the internal bus when the wait states are loaded into the DSACK counter shared by all chip MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc Fast terminatio
213. TWLYYWW DATA10 PG2 ADDR7 PB4 DATA11 PG3 ADDR8 PB5 DATA12 PG4 ADDRO PB6 DATA13 PG5 ADDR10 PB7 DATAL4 PG6 ADDR11 PA0 DATA15 PG7 ADDR12 PA1 ADDRO ADDR13 PA2 DSACKO PEO ADDR 14 PA3 5 1 ADDR15 PA4 AVEC PE2 ADDR16 PA5 PE3 ADDR17 PA6 DS PE4 ADDR18 PA7 AS PE5 SS PMC3 SIZO PE6 MOSI PMC1 SIZ1 PE7 MISO PMCO RW in g ZQVUAMENOAGYAIFIE urenymermre 5 mE i NOTES 1 MMMMM MASK OPTION NUMBER 2 ATWLYYWW ASSEMBLY TEST LOCATION YEAR WEEK GER Figure 2 68 916 1 Pin Assignment for 132 Pin Package MC68HC16R1 916R1 MECHANICAL DATA AND ORDERING INFORMATION MOTOROLA USER S MANUAL For More Information On This Product Go to www freescale com B 3 Freescale Semiconductor Inc gt Y RRA gt Y o Y V1 B1 VIEW AB BASE METAL Y Y B E D l D2 E1 PLATING SECTION AC AC 0 002 L M ay NOTES 1 DIMENSIONING AND TOLERANCING PER ASME 4 5M 1982 MENSIONS IN INCHES MENSIONS A B J AND P DO NOT INCLUDE OLD PROTRUSION ALLOWABLE MOLD ROTRUSION FOR DIMENSIONS A AND B IS 0 007 DIMENSIONS J AND P IS 0 010 M
214. Timer Module 7 CTM7 X X 16 and 32 Kbyte Flash EEPROM Modules X 2 Kbyte Block Erasable Flash EEPROM X The maximum system clock for MC68HC16R1 and MC68HC916R1 MCUs is 16 78 MHz An internal phase locked loop circuit synthesizes the system clock from either a slow typically 32 768 kHz or fast typically 4 194 MHz reference or uses an external frequency source System hardware and software support changes in clock rate during operation Because the MCUS are a fully static design register and memory contents are not affected by clock rate changes High density complementary metal oxide semiconductor HCMOS architecture makes the basic power consumption low Power consumption can be minimized by stopping the system clock The M68HC16 instruction set includes a low power stop LPSTOP command that efficiently implements this capability MC68HC16R1 916R1 INTRODUCTION MOTOROLA USER S MANUAL For More Information On This Product 1 1 Go to www freescale com Freescale Semiconductor Inc Documentation for the Modular Microcontroller Family follows the modular construc tion of the devices in the product line Each device has a comprehensive user s manual that provides sufficient information for normal operation of the device The user s manual is supplemented by module reference manuals that provide detailed information about module operation and applications Refer to Motorola publication Advanced Microcontroller Unit AMCU Litera
215. ULE MOTOROLA USER S MANUAL For More Information On This Product 7 3 Go to www freescale com Freescale Semiconductor Inc MOTOROLA MASKED ROM MODULE MC68HC16R1 916R1 7 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 8 FLASH EEPROM MODULE The flash EEPROM modules serve as nonvolatile fast access electrically erasable and programmable ROM emulation memory These modules are used only in the MC68HC916R1 The MC68HC916R1 contains two flash electrically erasable programmable read only memory EEPROM modules a 16 Kbyte module and a 32 Kbyte module The modules can contain program code for example operating system kernels and standard subroutines which must execute at high speed or is frequently executed or static data which is read frequently The flash EEPROM supports both byte and word reads It is capable of responding to back to back IMB accesses to provide two bus cycle four system clock access for aligned long words It can also be programmed to insert up to three wait states to accommodate migration from slower external development memory to onboard flash EEPROM without the need for retiming the system The 16 Kbyte flash EEPROM array can begin on any 16 Kbyte boundary and the 32 Kbyte array can begin on any 32 Kbyte boundary The two arrays can be configured to appear as a single contiguous memory block with the 16 Kbyte array immediately precedi
216. UNICATION INTERFACE MOTOROLA USER S MANUAL 11 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SCCR1 contains a number of SCI configuration parameters including transmitter and receiver enable bits interrupt enable bits and operating mode enable bits The CPU16 can read and write this register at any time The SCI can modify the RWU bit under certain circumstances Changing the value of SCI control bits during a transfer may disrupt operation Before changing register values allow the SCI to complete the current transfer then disable the receiver and transmitter 11 4 1 2 SCI Status Register The SCSR contains flags that show operating conditions These flags are cleared either by SCI hardware or by a read write sequence To clear SCI transmitter flags read the SCSR and then write to the SCDR To clear SCI receiver flags read the SCSR and then read the SCDR A long word read can consecutively access both the SCSR and the SCDR This action clears receiver status flag bits that were set at the time of the read but does not clear TDRE or TC flags If an internal SCI signal for setting a status bit comes after the CPU has read the asserted status bits but before the CPU has written or read the SCDR the newly set status bit is not cleared The SCSR must be read again with the bit set and the SCDR must be written to or read before the status bit is cleared Reading either byte o
217. URR2 YFF716 Right Justified Unsigned Result Register 3 RJURR3 YFF718 Right Justified Unsigned Result Register 4 RJURR4 YFF71A Right Justified Unsigned Result Register 5 RJURR5 YFF71C Right Justified Unsigned Result Register 6 RJURR6 YFF71E Right Justified Unsigned Result Register 7 RJURR7 YFF720 Left Justified Signed Result Register 0 LJSRRO YFF722 Left Justified Signed Result Register 1 LUSRR1 YFF724 Left Justified Signed Result Register 2 LUSRR2 YFF726 Left Justified Signed Result Register 3 LUSRR3 YFF728 Left Justified Signed Result Register 4 LUSRR4 YFF72A Left Justified Signed Result Register 5 LUSRR5 YFF72C Left Justified Signed Result Register 6 _LUSRR6 YFF72E Left Justified Signed Result Register 7 LUSRR7 YFF730 Left Justified Unsigned Result Register 0 LJURRO YFF732 Left Justified Unsigned Result Register 1 LJURR1 YFF734 Left Justified Unsigned Result Register 2 LJURR2 YFF736 Left Justified Unsigned Result Register LJURR3 YFF738 Left Justified Unsigned Result Register 4 LJURR4 YFF73A Left Justified Unsigned Result Register 5 LJURR5 YFF73C Left Justified Unsigned Result Register 6 LJURR6 YFF73E Left Justified Unsigned Result Register 7 LJURR7 NOTES 1 Y M111 where M is the logic state of the MM bit in the SCIMCR MOTOROLA MC68HC16R1 916R1 D 32 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconduc
218. USED PMC7 PMC6 PMC5 PMC5 PMC4 PMC3 PMC2 PMCO RESET 0 0 0 0 0 0 0 U U U U U U U U U Two registers are associated with port MCCI the MCCI general purpose I O port Pins used for general purpose I O must be configured for that function When using port MCCI as an output port after configuring the pins as I O write the first byte to be output before writing to the MDDR Afterwards write to the MDDR to assign each pin as either input or output This outputs the value contained in register PORTMC for all pins defined as outputs To output different data write another byte to PORTMC Writes to PORTMC are stored in the internal data latch If any bit of PORTMC is configured as discrete output the value latched for that bit is driven onto the pin Reads of PORTMC return the value of the pin only if the pin is configured as a discrete input Otherwise the value read is the value of the latch Reads of PORTMCP always return the state of the pins regardless of whether the pins are configured for input or output Writes to PORTMCP have no effect D 6 9 SCI Control Register 0 SCCROA SCIA Control Register 0 YFFC18 SCCROB SCIB Control Register 0 YFFC28 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED SCBR 12 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 SCCRO contains the SCI baud rate selection field Baud rate must be set before the SCI is enabled The CPU16 can rea
219. W pin This pin is not normally used during single chip operation The reset state of each of these three bits is one if BERR is held low during reset configuring the MCU for single chip operation or zero if BERR is held high during reset MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 3 Go to www freescale com Freescale Semiconductor Inc 5 2 4 Show Internal Cycles A show cycle allows internal bus transfers to be monitored externally The SHEN field in SCIMCR determines what the external bus interface does during internal transfer operations Table 5 1 shows whether data is driven externally and whether external bus arbitration can occur Refer to 5 6 6 1 Show Cycles for more information Table 5 1 Show Cycle Enable Bits SHEN 1 0 Action Show cycles disabled external arbitration enabled 10 Show cycles enabled external arbitration enabled 11 Show cycles enabled external arbitration enabled internal activity is halted by a bus grant 5 2 5 Register Access MC68HC16R1 916R1 MCUs always operates at the supervisor level The state of the SUPV bit has no meaning 5 2 6 Freeze Operation The FREEZE signal halts MCU operations during debugging FREEZE is asserted internally by the CPU16 if a breakpoint occurs while background mode is enabled When FREEZE is asserted only the bus monitor software watchdog and periodic in terrupt timer ar
220. Watchdog Service Register YFFA26 15 8 7 6 5 4 3 2 1 0 NOT USED SWSR 7 0 RESET 0 0 0 0 0 0 0 0 NOTES 1 This register is shown with a read value This register can be read or written at any time Bits 15 8 are unimplemented and will always read zero To reset the software watchdog 1 Write 55 to SWSR 2 Write AA to SWSR Both writes must occur in the order specified before the software watchdog times out but any number of instructions can occur between the two writes MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 2 19 Port F Edge Detect Flag Register PORTFE Port F Edge Detect Flag Register YFFA28 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PEE EF6 RESERVED PEFO RESET 0 0 0 0 0 0 0 0 When the corresponding pin is configured for edge detection a PORTFE bit is set if an edge is detected PORTFE bits remain set regardless of the subsequent state of the corresponding pin until cleared To clear a bit first read PORTFE then write the bit to zero When pin is configured for general purpose I O or for use as an interrupt request input PORTFE bits do not change state Bits 15 8 are unimplemented and will always read zero D 2 20 Port F Edge Detect Interrupt Vector PFIVR Port F Edge Detect Interrupt Vector Register YFFA2A 15 14 13 12 11 10
221. ZO PE6 5121 7 RAV MC68HC916R1 132 PIN QFP Figure 3 4 MC68HC916R1 Pin Assignment for 132 Pin Package MOTOROLA 3 7 3 4 Pin Descriptions Table 3 1 summarizes pin characteristics of the MC68HC16R1 and MC68HC916R1 MCUs Entries in the Associated Module column indicate to which module individual pins belong For MCU pins that can be outputs the Driver Type column lists which output driver type is used Table 3 2 briefly describes the four primary driver types A in the Driver Type column indicates either that the pin is an input only and thus does not have a driver or that the pin has a special driver like the XTAL pin Entries in the Synchronized Input and Input Hysteresis columns denote whether MCU pins that can be inputs are synchronized to the system clock and if they have hysteresis Pins that are outputs only or that have special characteristics like the EXTAL pin have a in these columns Table 3 1 MC68HC16R1 MC68HC916R1 Pin Characteristics Freescale Semiconductor Inc Pin Pin Associated Driver Synchronized Input Mnemonic s Number s Module Type Input Hysteresis ADDRO 93 ADDR1 29 SCIM2 A ADDR2 30 ADDR3 PBO 31 ADDR4 PB1 32 ADDR5 PB2 33 ADDR6 PB3 35 ADDR7 PB4 36 5 5 ADDR8 PB5 37 ADDR9 PB6 38 ADDR10 PB7 39 ADDR1 1 PAO 40 ADDR12 PA1 41 ADDR13 PA2 42 ADDR14 PA3 43 ADDR15 PA4 44 SCIM2 Y Y ADDR16 PA5 45 ADDR17 PA6
222. a simple serial interface and a terminal 4 14 1 Deterministic Opcode Tracking The CPU16 has two multiplexed outputs IPIPEO and IPIPE1 that enable external hardware to monitor the instruction pipeline during normal program execution The signals IPIPEO and IPIPE1 can be demultiplexed into six pipeline state signals that allow a state analyzer to synchronize with instruction stream activity MOTOROLA MC68HC16R1 916R1 4 40 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 14 1 1 IPIPEO IPIPE1 Multiplexing Six types of information are required to track pipeline activity To generate the six state signals eight pipeline states are encoded and multiplexed into IPIPEO and IPIPE1 The multiplexed signals have two phases State signals are active low Table 4 6 shows the encoding scheme Table 4 6 IPIPEO IPIPE1 Encoding Phase IPIPE1 State IPIPEO State State Signal Name START and FETCH FETCH START NULL INVALID ADVANCE EXCEPTION NULL IPIPEO and IPIPE1 are timed so that a logic analyzer can capture all six pipeline state signals and address data or control bus state in any single bus cycle Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for specifications State signals can be latched asynchronously on the falling and rising edges of either address strobe AS or data strobe DS They can also be latched synchronously us ing the microcontroller CLKOUT signal
223. able 3 1 MC68HC16R1 MC68HC916R1 Pin Characteristics Freescale Semiconductor Inc Pin Pin Associated Driver Synchronized Input Mnemonic s Number s Module Type Input Hysteresis VsrBY 56 SRAM XFC 62 SCIM2 XTAL 57 SCIM2 TEE TES NOTES 1 AN 7 0 PADA 7 0 FASTREF PF0 MISO PMCO MOSI PMC1 SCK PMC2 SS PMC3 RXDB PMC4 TXDB PMC5 RXDA PMC6 and TXDA PMCT7 inputs are only synchronized when used as discrete general purpose inputs 2 BERR is only synchronized when executing retry or late bus cycle operations HALT is only synchronized when executing retry or single step bus cycle operations These uses of HALT and BERR are only supported on the CPU32 and not the CPU16 3 DATA 15 8 PG 7 0 and DATA 7 0 PH 7 0 are only synchronized during reset and when being used as discrete general purpose inputs Table 3 2 MC68HC16R1 916R1 Driver Types Type 1 0 Description A Three state capable output signals Aw A output with weak p channel pullup during reset B Three state output that includes circuitry to pull up output before high impedance is established to ensure rapid rise time Bo output that be operated in an open drain mode Table 3 3 summarizes pin functions of the MC68HC16R1 and MC68HC916R1 MCUs Entries in the Active State s column denote the polarity of each MCU pin in its active state Some MCU pin
224. ables these pins and leaving the bit set its single chip reset state leaves the pins in a disabled high impedance state Table 5 19 summarizes SCIM2 pin functions during single chip operation MC68HC16R1 916R1 USER S MANUAL Table 5 19 Single Chip Mode Reset Configuration Pin s Affected Function CSBOOT CSBOOT 16 Bit ADDR 18 11 PA 7 0 ADDR 10 3 PB 7 0 BR CSO cso FCO CS3 PCO FC1 PC1 FC2 CS5 PC2 ADDR19 CS6 PC3 PC 6 0 ADDR20 CS7 PC4 ADDR21 CS8 PC5 ADDR22 CS9 PC6 ADDR23 CS10 ECLK DSACKO PEO DSACK1 PE1 AVEC PE2 PE3 DS PE4 PE 7 0 AS PE5 SIZO PE6 SIZ1 PE7 FASTREF PFO PFO TRQ 7 6 PF 7 6 PF 7 6 DATA 15 8 PG 7 0 DATA 7 0 PH 7 0 BGACK CSE BGACK BG CSM BG SINGLE CHIP INTEGRATION MODULE 2 For More Information On This Product Go to www freescale com MOTOROLA 5 49 Freescale Semiconductor Inc 5 7 3 6 Clock Mode Selection The state of the clock mode MODCLK pin during reset determines what clock source the MCU uses When MODCLK is held high during reset the clock signal is generated from a reference frequency using the clock synthesizer When MODCLK is held low during reset the clock synthesizer is disabled and an external system clock signal must be applied Refer to 5 3 System Clock for more information NOTE The MODCLK pin can also be used as parallel I O pin PFO To pre vent inadvertent clock mode selection by logic connected to port F
225. ace access and clears the base address registers and the register lock bit These actions make it pos sible to write a new base address into the ROMBAH and ROMBAL registers When a synchronous reset occurs while a byte or word SRAM access is in progress the access is completed If reset occurs during the first word access of a long word operation only the first word access is completed If reset occurs during the second word access of a long word operation the entire access is completed Data being read MOTOROLA STANDBY RAM MODULE MC68HC16R1 916R1 6 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc from or written to the RAM may be corrupted by an asynchronous reset For more in formation refer to 5 7 Reset for more information MC68HC16R1 916R1 STANDBY RAM MODULE MOTOROLA USER S MANUAL For More Information On This Product 6 3 Go to www freescale com Freescale Semiconductor Inc MOTOROLA STANDBY RAM MODULE MC68HC16R1 916R1 6 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 7 MASKED ROM MODULE The masked ROM module MRM consists of a fixed location control register block and a 48 Kbyte mask programmed read only memory array that can be mapped to any 48 Kbyte boundary in the system memory map It is used only in the MC68HC16R1 The MRM can be programmed to insert wait states to accommod
226. acknowledge cycle 12 4 1 STOP Effect On the BIUSM When the CPU16 STOP instruction is executed only the CPU16 is stopped the CTM7 continues to operate as normal 12 4 2 Freeze Effect On the BIUSM CTM7 response to assertion of the IMB FREEZE signal is controlled by the FRZ bit in the BIUSM configuration register BIUMCR Since the BIUSM propagates FREEZE to the CTM7 submodules via the SMB the setting of FRZ affects all CTM7 submod ules If the IMB FREEZE signal is asserted and FRZ 1 all CTM7 submodules freeze The following conditions apply when the CTM7 is frozen All submodule registers can still be accessed The CPSM FCSM MCSM and PWMSM counters stop counting The IN status bit still reflects the state of the FCSM external clock input pin The IN2 status bit still reflects the state of the MCSM external clock input pin and the IN1 status bit still reflects the state of the MCSM modulus load input pin DASM capture and compare functions are disabled MC68HC16R1 916R1 CONFIGURABLE TIMER MODULE 7 MOTOROLA USER S MANUAL For More Information On This Product 12 3 Go to www freescale com Freescale Semiconductor Inc The DASM IN status bit still reflects the state of its associated pin in the DIS IPWM IPM and IC modes In the OCB OCAB and OPWM modes IN reflects the state of the DASM output flip flop e When configured for OCB OCAB or OPWM modes the state of the DASM output flip flop will remain
227. ains a status interrupt control register a period register a pulse width register and a counter register All unused bits and reserved address locations return zero when read Writes to unused bits and reserved address locations have no effect The CTM7 contains two PWMSMs each with its own set of registers Refer to D 7 16 PWM Status Interrupt Control Register D 7 17 PWM Period Register D 7 18 PWM Pulse Width Register and D 7 19 PWM Counter Register for informa tion concerning PWMSM register and bit descriptions 12 11 CTM7 Interrupts The is able to generate as many as 11 requests for interrupt service Each sub module capable of requesting an interrupt can do so on any of seven levels Submod ules that can request interrupt service have a 3 bit level number and a 1 bit arbitration number that is user initialized The 3 bit level number selects which of seven interrupt signals on the IMB are driven by that submodule to generate an interrupt request Of the four priority bits provided by the IMB to the CTM7 for interrupt arbitration one of them comes from the chosen submodule and the BIUSM provides the other three Thus the CTM7 can respond with two of the 15 possible arbitration numbers During the IMB arbitration process the BIUSM manages the separate arbitration among the CTM7 submodules to determine which submodule should respond The CTM7 has a fixed hardware prioritization scheme for all submodules When two or more sub
228. ait states During regular cycles wait states can be inserted as needed by bus control logic Refer to 5 6 2 Regular Bus Cycle for more information Fast termination cycles which are two cycle external accesses with no wait states use chip select logic to generate handshaking signals internally Refer to 5 6 3 Fast Termination Cycles and 5 9 Chip Selects for more information Bus control signal timing as well as chip select signal timing are specified in APPENDIX A ELECTRI CAL CHARACTERISTICS Refer to the SC M Reference Manual SCIMRM AD for more information about each type of bus cycle MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 29 Go to www freescale com Freescale Semiconductor Inc 5 6 1 Synchronization to CLKOUT External devices connected to the MCU bus can operate at a clock frequency different from the frequencies of the MCU as long as the external devices satisfy the interface signal timing constraints Although bus cycles are classified as asynchronous they are interpreted relative to the MCU system clock output CLKOUT Descriptions are made in terms of individual system clock states labelled SO S1 S2 SN The designation state refers to the logic level of the clock signal and does not correspond to any implemented machine state A clock cycle consists of two successive states Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for more in
229. ale Semiconductor Inc 5 7 2 Reset Control Logic SCIM2 reset control logic determines the cause of a reset synchronizes request signals to CLKOUT and asserts reset control signals Reset control logic can drive three different internal signals EXTRST external reset drives the external reset pin CLKRST clock reset resets the clock module MSTRST master reset goes to all other internal circuits All resets are gated by CLKOUT Asynchronous resets are assumed to be catastroph ic An asynchronous reset can occur on any clock edge Synchronous resets are timed to occur at the end of bus cycles The SCIM2 bus monitor is automatically enabled for synchronous resets When a bus cycle does not terminate normally the bus monitor terminates it Table 5 14 is a summary of reset sources Table 5 14 Reset Source Summary Type Source Timing Cause Reset pou by External External Synch RESET pin MSTRST CLKRST EXTRST Power up EBI Asynch Vpp MSTRST CLKRST EXTRST Software watchdog Monitor Asynch Time out MSTRST CLKRST EXTRST HALT Monitor Asynch ntemal HALT assertion creer CLKRST EXTRST e g double bus fault Loss of clock Clock Synch Loss of reference MSTRST CLKRST EXTRST Test Test Synch Test mode MSTRST EXTRST Internal single byte or aligned word writes are guaranteed valid for synchronous re sets External writes are also guaranteed to complete pr
230. an ECLK cycle the address may be valid before ECLK goes low Address access time tEcyc teap tEDSR 4 Chip select access time tecsp tgpsn MOTOROLA MC68HC16R1 916R1 A 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc um PUE NG Nf NET NE NN ECLK DATA 15 0 AN READ WRITE 1 HC16 E CYCLE TIM Figure A 15 ECLK Timing Diagram MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product A 21 Go to www freescale com Freescale Semiconductor Inc Table A 9 SPI Timing c E 1 Vbo and 5 0 5 Vos 0 Vdc Ts Ti to Ta Num Function Symbol Min Max Unit Operating Frequency 1 Master fop DC 1 4 Slave DC 1 4 sys Cycle Time 2 Master tacye 4 510 Slave 4 Enable Lead Time 3 Master tlead 2 128 Slave 2 Enable Lag Time 4 Master tlag 1 2 SCK Slave 2 Clock SCK High or Low Time 5 Master tow 2 teye 60 255 teyc ns Slave 2 toyo ns Sequential Transfer Delay 6 Master 17 8192 Slave Does Not Require Deselect 13 Data Setup Time Inputs 7 Master tsu 30 ES ns Slave 20 ns Data Hold Time Inputs 8 Master thi 0 ns Slave 20 ns 9 Slave Access Time ta 1 10 Slave MISO Disable Time ldis 2 Data Valid after 5 Edge 11 Mast
231. and communicates with the development system through a dedicated serial interface 4 14 4 1 Enabling BDM The CPU16 samples the BKPT input during reset to determine whether to enable BDM When is asserted at the rising edge of the RESET signal BDM operation is enabled BDM remains enabled until the next system reset If BKPT is at logic level one on the trailing edge of RESET BDM is disabled BKPT is relatched on each rising transition of RESET BKPT is synchronized internally and must be asserted for at least two clock cycles before negation of RESET 4 14 4 2 BDM Sources When BDM is enabled external breakpoint hardware and the BGND instruction can cause the CPU16 to enter BDM If BDM is not enabled when a breakpoint occurs a breakpoint exception is processed MOTOROLA MC68HC16R1 916R1 4 42 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 14 4 3 Entering BDM When the CPU16 detects a breakpoint or decodes a BGND instruction when BDM is enabled it suspends instruction execution and asserts the FREEZE signal Once FREEZE has been asserted the CPU16 enables the BDM serial communication hard ware and awaits a command Assertion of FREEZE causes opcode tracking signals IPIPEO and IPIPE1 to change definition and become serial communication signals DSO and DSI FREEZE is asserted at the next instruction boundary after the assertion of BKPT or ex
232. ap word locations during reset vector fetch 1 ROM does not respond to bootstrap word locations during reset vector fetch Bootstrap operation is overridden if STOP 1 at reset LOCK Lock Registers The reset state of LOCK is specified at mask time If the reset state of the LOCK is zero it can be set once after reset to allow protection of the registers after initialization Once the LOCK bit is set it cannot be cleared again until after a reset LOCK protects the ASPC and WAIT fields as well as the ROMBAL and ROMBAH registers ASPC ROMBAL and ROMBAH are also protected by the STOP bit 0 Write lock disabled Protected registers and fields can be written 1 Write lock enabled Protected registers and fields cannot be written EMUL Emulation Mode Control 0 Normal ROM operation 1 Accesses to the ROM array are forced external allowing memory selected by the CSM pin to respond to the access Because the MC68HC16R1 916R1 does not support ROM emulation mode this bit should never be set ASPC 1 0 ROM Array Space The ASPC field limits access to the SRAM array in microcontrollers that support separate user and supervisor operating modes ASPC1 has no effect because the CPU16 operates in supervisor mode only This bit may be read or written at any time The reset state of ASPC 1 0 is specified at mask time Table D 21 shows ASPC 1 0 encoding Table D 21 ROM Array Space Field ASPC 1 0 State Specified
233. ar chip select pin provided other option register conditions are met Table D 17 shows IPL 2 0 field encoding MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 23 Go to www freescale com Freescale Semiconductor Inc Table D 17 Interrupt Priority Level Field Encoding IPL 2 0 Interrupt Priority Level 000 Any l NOTES 1 Any level means that chip select is asserted regardless of the level of the interrupt acknowledge cycle AVEC Autovector Enable This field selects one of two methods of acquiring an interrupt vector during an interrupt acknowledge cycle This field is not applicable when SPACE 1 0 9600 0 External interrupt vector enabled 1 Autovector enabled If the chip select is configured to trigger on an interrupt acknowledge cycle SPACE 1 0 00 and the AVEC field is set to one the chip select automatically generates AVEC and completes the interrupt acknowledge cycle Otherwise the vector must be supplied by the requesting external device to complete the IACK read cycle D 2 28 Master Shift Registers TSTMSRA Test Module Master Shift Register A YFFA30 Used for factory test only TSTMSRB Test Module Master Shift Register B YFFA32 Used for factory test only D 2 29 Test Module Shift Count Register TSTSC Test Module Shift Count YFFA34 Used for factory test only D 2 30 Test Module Repetition Count Register
234. ate migration from slow external development memory Access time depends upon the number of wait states specified but can be as fast as two clock cycles The MRM can be used for program accesses only or for program and data accesses Data can be read in bytes words or long words The MRM can be configured to support system bootstrap during reset 7 1 MRM Register Block There are three MRM control registers the masked ROM module configuration regis ter MRMCR and the ROM array base address registers ROMBAH and ROMBAL In addition the MRM register block contains signature registers SIGHI and SIGLO and ROM bootstrap words ROMBS 0 3 The module mapping bit MM in the SCIMCR defines the most significant bit ADDR23 of the IMB address for each MC68HC16R1 916R1 module Because the CPU16 drives only ADDR 19 0 and ADDR 23 20 follow the logic state of ADDR19 MM must equal one 5 2 1 Module Mapping contains information about how the state of MM affects the system The MRM control register block consists of 32 bytes but not all locations are imple mented Unimplemented register addresses are read as zeros and writes have no ef fect Refer to D 4 Masked ROM Module for register block address map and register bit field definitions 7 2 MRM Array Address Mapping Base address registers ROMBAH and ROMBAL are used to specify the ROM array base address in the memory map Although the base address contained ROMBAH and ROMBAL is mask
235. atus Register RSR Reset Status Register YFFAO6 15 8 7 6 5 4 3 2 1 0 SYS TST RE NOT USED EXT POW SW HLT 0 SERVED RSR contains a status bit for each reset source in the MCU RSR is updated when the MCU comes out of reset A set bit indicates what type of reset occurred If multiple sources assert reset signals at the same time more than one bit in RSR may be set This register can be read at any time a write has no effect Bits 15 8 are unimplemented and always read zero EXT External Reset Reset caused by the RESET pin POW Power Up Reset Reset caused by the power up reset circuit SW Software Watchdog Reset Reset caused by the software watchdog circuit HLT Halt Monitor Reset Reset caused by the halt monitor SYS System Reset The CPU16 does not support this function This bit will never be set TST Test Submodule Reset Reset caused by the test submodule Used during factory test reserved operating mode only D 2 5 SCIM Test Register E SCIMTRE Single Chip Integration Module Test Register E YFFA08 Used for factory test only MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 9 Go to www freescale com Freescale Semiconductor Inc D 2 6 Port A and B Data Registers PORTA Port A Data Register YFFAOA PORTB Port B Data Register YFFAOB 15 8 7 6 5 4 3 2 1 0 7
236. ay This results in a maximum obtainable 10 bit conversion value of 3FE At the bottom of the signal range VssA is 15 mV higher than resulting in a minimum obtainable 10 bit conversion value of 3 MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For More Information On This Product 10 15 Go to www freescale com Freescale Semiconductor Inc ff 1 1 3FD 3FC ff 3rB E 3FAL P S U 8 ff B E 9 al 5 4 ff 3 P ee ee bho ee ee eu eed 2 1 ff 0 010 00 4030 5100 510 5120 5130 INPUT IN VOLTS Vay 5 120 V Vg 0 V ADC CLIPPING Figure 10 5 Errors Resulting from Clipping 10 8 3 Analog Supply Filtering and Grounding Two important factors influencing performance in analog integrated circuits are supply filtering and grounding Generally digital circuits use bypass capacitors on every Vss pin pair This applies to analog subsystems or submodules also Equally important as bypassing is the distribution of power and ground Analog supplies should be isolated from digital supplies as much as possible This ne cessity stems from the higher performance requirements often associated with analog circuits Therefore deriving an analog supply from a local digital supply is not recom mended However if for economic reasons digital and analog power are derived fro
237. boot chip select base address register CSBARBT has a reset value of 000 which corresponds to a base address of 000000 and a block size of 512 Kbytes A memory device containing the reset vector and initialization routine can be automatically enabled by CSBOOT after a reset Refer to 5 9 4 Chip Select Reset Operation for more information 5 9 1 3 Chip Select Option Registers Option register fields determine timing of and conditions for assertion of chip select signals To assert a chip select signal and to provide DSACK or autovector support other constraints set by fields in the option register and in the base address register must also be satisfied The following paragraphs summarize option register functions Refer to D 2 27 Chip Select Option Registers for register and bit field information The MODE bit determines whether chip select assertion simulates an asynchronous bus cycle or is synchronized to the M6800 type bus clock signal ECLK available on ADDR23 Refer to 5 3 System Clock for more information on ECLK MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 65 Go to www freescale com Freescale Semiconductor Inc BYTE 1 0 controls bus allocation for chip select transfers Port size set when a chip select is enabled by a pin assignment register affects signal assertion When an 8 bit port is assigned any BYTE field value other than 9600 enables the chip s
238. bus cycle termination and synchronizes internal ADC signals with IMB signals The ABIU also manages data bus routing to accommo date the three conversion data formats and controls the interface to the module differ ential data bus 10 5 Special Operating Modes Low power stop mode and freeze mode are ADC operating modes associated with as sertion of IMB signals by other microcontroller modules or by external sources These modes are controlled by the values of bits in the ADC module configuration register ADCMCR MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For More Information On This Product 10 3 Go to www freescale com Freescale Semiconductor Inc 10 5 1 Low Power Stop Mode When the STOP bit in ADCMCR is set the IMB clock signal to the ADC is disabled This places the module in an idle state and power consumption is minimized The ABIU does not shut down and ADC registers are still accessible If a conversion is in progress when STOP is set it is aborted STOP is set during system reset and must be cleared before the ADC can be used Because analog circuit bias currents are turned off during low power stop mode the ADC requires recovery time after STOP is cleared Execution of the CPU16 LPSTOP command places the entire modular microcontroller in low power stop mode Refer to 5 3 4 Low Power Operation for more information 10 5 2 Freeze Mode When the CPU16 in the modular microcontroller ente
239. c T T to T Num Characteristic Symbol Min Max Unit RAM Standby Current ig Normal RAM operation Vpp gt Vsg 0 5 V 50 uA Transient condition 0 5 V gt Vpp 2 Vss 0 5 V SB 3 mA Standby operation Vpp lt Vss 0 5 V 100 pA 17 MC68HC16R1 Power Dissipation 732 mW 17 MC68HC916R1 Power Dissipation 924 mW Input Capacitance 13 46 18 All input only pins except ADC pins Cin 20 All input output pins Load Capacitance Group 1 I O Pins CLKOUT FREEZE QUOT IPIPEO 90 19 Group 2 I O Pins and CSBOOT BG CS C 100 pF Group 3 I O Pins 130 Group 4 I O Pins 200 NOTES 1 Applies to Port ADA 7 0 AN 7 0 Port E 7 4 SIZ 1 0 AS DS Port F 7 0 IRQ 7 1 MODCLK Port MCCI 7 0 TXDA TXDB PMC 3 0 BKPT DSCLK DSI IPIPE1 RESET RXD TSC EXTAL when PLL enabled 2 This parameter is periodically sampled rather than 100 tested 3 Applies to all input only pins except ADC pins 4 Input Only Pins EXTAL TSC BKPT DSCLK RXDA RXDB Output Only Pins Group 1 Port C 6 0 ADDR 22 19 CS 9 6 FC 2 0 CS5 CS3 Port E 7 0 SIZ 1 0 AS DS AVEC DSACK 1 0 Port F 7 0 IRQ 7 1 MODCLK Port PMC 7 3 TXDA TXDB PCS 3 0 ADDR23 CS10 ECLK ADDR 18 0 RW BERR 50 BGACK CSE 5 Applies to all input output and output pins 6 Does not apply to HALT and RESET because they are open drain pins Does
240. cale Semiconductor Inc Table 5 4 Bus Monitor Period BMT 1 0 Bus Monitor Timeout Period 00 64 System clocks 01 32 System clocks 10 16 System clocks 11 8 System clocks The monitor does not check DSACK response on the external bus unless the CPU16 initiates a bus cycle The BME bit in SYPCR enables the internal bus monitor for internal to external bus cycles If a system contains external bus masters an external bus monitor must be implemented and the internal to external bus monitor option must be disabled When monitoring transfers to an 8 bit port the bus monitor does not reset until both byte accesses of a word transfer are completed Monitor timeout period must be at least twice the number of clocks that a single byte access requires 5 4 3 Halt Monitor The halt monitor responds to an assertion of the HALT signal on the internal bus caused by a double bus fault A flag in the reset status register RSR can indicate that the last reset was caused by the halt monitor Halt monitor reset can be inhibited by the halt monitor HME enable bit in SYPCR Refer to 5 6 5 2 Double Bus Faults for more information 5 4 4 Spurious Interrupt Monitor During interrupt exception processing the CPU16 normally acknowledges an interrupt request arbitrates among various sources of interrupt recognizes the highest priority source and then acquires a vector or responds to a request for autovectoring The spurious interrupt monit
241. cated in Table 11 1 Table 11 1 MCCI Interrupt Vectors Interface INTV 1 0 SCIA 00 SCIB 01 SPI 10 MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL For More Information On This Product 11 3 Go to www freescale com Freescale Semiconductor Inc Select a value for INTV so that each interrupt vector corresponds to one of the user defined vectors 40 FF Refer to the CPU16 Reference Manual CPU16RM AD for additional information on interrupt vectors 11 2 2 Pin Control and General Purpose I O The eight pins used by the SPI and SCI subsystems have alternate functions as general purpose I O pins Configuring the MCCI submodule includes programming each pin for either general purpose I O or its serial interface function In either function each pin must also be programmed as input or output The MCCI data direction register MDDR assigns each MCCI pin as either input or output The MCCI pin assignment register MPAR assigns the MOSI MISO and SS pins as either SPI pins or general purpose I O The fourth SCK is automatically assigned to the SPI whenever the SPI is enabled for example when the SPE bit in the SPI control register is set The receiver enable RE and transmitter enable TE bits in the SCI control registers SCCROA SCCROB automatically assign the associ ated pin as an SCI pin when set or general purpose I O when cleared Table 11 2 summarizes
242. ce non listening receivers in wake up mode between transmissions or to signal a retransmission by forcing an idle line clear and then set TE before data in the serial shifter has shifted out The transmitter finishes the transmission then sends a preamble After the preamble is transmitted if TDRE is set the transmitter will mark idle Otherwise normal transmission of the next sequence will begin Both TDRE and TC have associated interrupts The interrupts are enabled by the transmit interrupt enable TIE and transmission complete interrupt enable TCIE bits in SCCR1 Service routines can load the last byte of data in a sequence into SCDR then terminate the transmission when a TDRE interrupt occurs 11 4 5 6 Receiver Operation The RE bit in SCCR1 enables RE 1 and disables RE 0 the receiver The receiver contains a receive serial shifter and a parallel receive data register RDR located in the SCI data register SCDR The serial shifter cannot be directly accessed by the CPU16 The receiver is double buffered allowing data to be held in the RDR while other data is shifted in MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Receiver bit processor logic drives a state machine that determines the logic level for each bit time This state machine controls when the bit processor logic is to sample
243. ceived data ignored until receiver is awakened SBK Send Break 0 Normal operation 1 Break frame s transmitted after completion of the current frame D 6 11 SCI Status Register SCSRA SCIA Status Register YFFC1C SCSRB SCIB Status Register YFFC2C 15 9 8 7 6 5 4 3 2 1 0 NOT USED TDRE TC RDRF RAF IDLE OR NF FE PF RESET 1 1 0 0 0 0 0 0 0 SCSR contains flags that show SCI operating conditions These flags are cleared either by SCI hardware or by a read write sequence The sequence consists of reading SCSR then reading or writing SCDR If an internal SCI signal for setting a status bit comes after reading the asserted status bits but before writing or reading SCDR the newly set status bit is not cleared SCSR must be read again with the bit set and SCDR must be read or written before the status bit is cleared A long word read can consecutively access both SCSR SCDR This action clears receive status flag bits that were set at the time of the read but does not clear TDRE or TC flags Reading either byte of SCSR causes all 16 bits to be accessed and any status bit already set in either byte is cleared on a subsequent read or write of SCDR Bits 15 9 Not Implemented TDRE Transmit Data Register Empty 0 Transmit data register still contains data to be sent to the transmit serial shifter 1 A new character can now be written to the transmit data register TC
244. cess for aligned long words The module can also be programmed to insert up to three wait states per access to accommodate migration from slower external de velopment memory without re timing the system Both the array and the individual control bits are programmable and erasable under software control Program erase voltage must be supplied via the external VEppoy pin Data is programmed in byte or word aligned fashion The module supports both block and bulk erase modes and has a minimum program erase life of 100 cycles Hard ware interlocks protect stored data from corruption if the program erase voltage to the BEFLASH EEPROM array is enabled accidently The BEFLASH array is enabled disabled by a combination of DATA15 and the STOP shadow bit after reset 9 2 BEFLASH Control Block The BEFLASH module control block contains five registers the BEFLASH module configuration register BFEMCR the BEFLASH test register BFETST the BE FLASH array base address registers BFEBAH and BFEBAL and the BEFLASH con trol register BFECTL Four additional words in the control block can contain bootstrap information when the BEFLASH is used as bootstrap memory Refer to D 9 Block Erasable Flash for register and bit field information Each register in the control block has an associated shadow register that is physically located in a spare BEFLASH row During reset fields within the registers are loaded with default information from the shadow register
245. ck period incre ments until either DSACK signal goes low If bus termination signals remain unasserted the MCU will continue to insert wait states and the bus cycle will never end If no peripheral responds to an access or if an access is invalid external logic should assert the BERR or HALT signals to abort the bus cycle when BERR and HALT are asserted simultaneously the CPU16 acts as though only BERR is asserted When enabled the SCIM2 bus monitor asserts BERR when DSACK response time exceeds a predetermined limit The bus monitor timeout period is determined by the BMT 1 0 field in SYPCR The maximum bus mon itor timeout period is 64 system clock cycles MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 30 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 6 2 1 Read Cycle During a read cycle the MCU transfers data from an external memory or peripheral device If the instruction specifies a long word or word operation the MCU attempts to read two bytes at once For a byte operation the MCU reads one byte The portion of the data bus from which each byte is read depends on operand size peripheral ad dress and peripheral port size Figure 5 11 is a flow chart of a word read cycle Refer to 5 5 2 Dynamic Bus Sizing 5 5 4 Misaligned Operands and the SC M Reference Manual SCIMRM AD for more information MCU PERIPHERAL ADDRESS
246. conversion channel or channels It can be read or written at any time A write to ADCTL1 initiates a conversion sequence If a conversion sequence is already in progress a write to ADCTL1 aborts it and resets the SCF and CCF flags in the ADC status register SCAN Scan Mode Selection 0 Single conversion 1 Continuous conversions Length of conversion sequence s is determined by S8CM MULT Multichannel Conversion 0 Conversion sequence s run on a single channel selected by CD CA 1 Sequential conversions of four or eight channels selected by CD CA Length of conversion sequence s is determined by S8CM S8CM Select Eight Conversion Sequence Mode 0 Four conversion sequence 1 Eight conversion sequence This bit determines the number of conversions in a conversion sequence Table D 27 displays the different ADC conversion modes MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product D 35 Go to www freescale com Freescale Semiconductor Inc Table D 27 ADC Conversion Mode SCAN MULT S8CM MODE 0 0 0 Single 4 Conversion Single Channel Sequence 0 0 1 Single 8 Conversion Single Channel Sequence 0 1 0 Single 4 Conversion Multichannel Sequence 0 1 1 Single 8 Conversion Multichannel Sequence 1 0 0 Multiple 4 Conversion Single Channel Sequences 1 0 1 Multiple 8 Conversion Single Channel Sequences 1 1 0 Multiple 4 Conversion Multichannel Sequences 1 1 1 Multiple
247. counter to derive the SCK baud rate from the MCU system clock Baud rate is selected by writing a value from 2 to 255 into SPBR 7 0 The following expressions apply to SCK baud rate fsys or f sys SPBR 0 5 SGK Baud Rate Desired Giving SPBR 7 0 a value of zero or one disables SCK disable state determined by CPOL At reset the SCK baud rate is initialized to one eighth of the system clock frequency D 6 14 SPI Status Register SPSR SPI Status Register YFFC3C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPIF WwcoL 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPSR contains information concerning the current serial transmission Only the SPI can set bits in SPSR The CPU16 reads SPSR to obtain SPI status information and writes it to clear status flags SPIF SPI Finished Flag 0 SPI is not finished 1 SPI is finished WCOL Write Collision 0 No attempt to write to the SPDR happened during the serial transfer 1 Write collision occurred Clearing WCOL is accomplished by reading the SPSR while WCOL is set and then either reading the SPDR prior to SPIF being set or reading or writing the SPDR after SPIF is set MOTOROLA MC68HC16R1 916R1 D S2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc MODF Mode Fault Flag 0 Normal operation 1 Another S
248. ct TSC Input TSC Input 5 7 5 2 Reset States of Pins Assigned to Other MCU Modules As a rule module pins that are assigned to general purpose I O ports go into a high impedance state following reset However during power on reset module port pins may be in an indeterminate state for a short period Refer to 5 7 7 Power On Reset for more information MC68HC16R1 916R1 USER S MANUAL SINGLE CHIP INTEGRATION MODULE 2 Go to www freescale com For More Information On This Product MOTOROLA 5 53 Freescale Semiconductor Inc 5 7 6 Reset Timing The RESET input must be asserted for a specified minimum period for reset to occur External RESET assertion can be delayed internally for a period equal to the longest bus cycle time or the bus monitor timeout period in order to protect write cycles from being aborted by reset While RESET is asserted SCIM2 pins are either in an inactive high impedance state or are driven to their inactive states When an external device asserts RESET for the proper period reset control logic clocks the signal into an internal latch The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer being externally driven to guarantee this length of reset to the entire system If an internal source asserts a reset signal the reset control logic asserts the RESET pin for a minimum of 512 cycles If the reset signal i
249. ctor Inc Table 4 1 Addressing Modes Mode Mnemonic Description Index register X with accumulator E offset 2 Index register Z with accumulator E offset Extended EXT20 20 bit extended IMM8 8 bit immediate IMM16 16 bit immediate IND8 X Index register X with unsigned 8 bit offset Immediate Indexed 8 Bit IND8 Y Index register Y with unsigned 8 bit offset IND16 X Index register X with signed 16 bit offset IND16 Z Index register Z with signed 16 bit offset Indexed 20 Bit IND20 Y Index register Y with signed 20 bit offset Inherent INH Inherent Signed 8 bit offset added to index register Post Modified Index X after effective address is used REL8 8 bit relative Relative REL16 16 bit relative All modes generate ADDR 15 0 This address is combined with ADDR 19 16 from an operand or an extension field to form a 20 bit effective address NOTE Access across 64 Kbyte address boundaries is transparent AD DR 19 16 of the effective address are changed to make an access across a bank boundary Extension field values will not change as a result of effective address computation 4 6 1 Immediate Addressing Modes In the immediate modes an argument is contained in a byte or word immediately fol lowing the instruction For IMM8 and IMM16 modes the effective address is the ad dress of the argument There are three specialized forms of IMM8 addressing The AIS AIX A
250. cts of the STSCIM and STEXT bits when the MCU enters normal low power stop mode Any clock in the off state is held low If the synthesizer VCO is turned off during low power stop mode there is a PLL relock delay after the VCO is turned back on MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 14 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc NOTE The internal oscillator which supplies the input frequency for the PLL always runs when a crystal is used SETUP INTERRUPT TO WAKE UP MCU FROM LPSTOP US EXTERNA NG L CLOCK USE SYSTEM CLOCK AS SCIMCLK IN LPSTOP SET STSCIM 1 SET STSCIM 0 het IN LPSTOP IN LPSTOP NO WANT CLKOUT ON IN LPSTOP SET STEXT 1 f clkout sys feck 5 IN LPSTOP NO WANT CLKOUT ON IN LPSTOP SET STEXT 0 fekout 0 Hz feck 0 Hz IN LPSTOP SET STEXT 1 SET STEXT 0 fet 0 Hz fec 0 Hz fec 0 Hz IN LPSTOP IN LPSTOP ENTER LPSTOP MC68HC16R1 916R1 USER S MANUAL NOTES 1 THE SCIMCLK IS USED BY THE PIT IRQ AND INPUT BLOCKS OF THE SCIM2 2 CLKOUT CONTROL DURING LPSTOP IS OVERRIDDEN BY THE EXOFF BIT IN SCIMCR IF EXOFF 1 THE CLKOUT PIN IS ALWAYS IN A HIGH IMPEDANCE STATE AND STEXT HAS NO EFFECT IN LPSTOP IF EXOFF 0 CLKOUT IS CONTROLLED BY STEXT IN LPSTOP LPSTOPFLOW Figure 5 6 LPSTOP Flowchar
251. d 0000 M M 1 IND16 X 2702 999g 8 m A A gt M M 1 IND16 Y 2712 9999 8 IND16 Z 2722 9999 8 EXT 2732 hh Il 8 NOP Null Operation INH 274C 2 MOTOROLA MC68HC16R1 916R1 4 22 For More Information On This Product USER S MANUAL Go to www freescale com Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV 2 V C ORAA ORA A gt A IND8 X 47 ff 6 A 0 IND8 Y 57 ff 6 IND8 Z 67 ff 6 IMM8 77 ii 2 IND16 X 1747 gggg 6 IND16 Y 1757 gggg 6 IND16 Z 1767 gggg 6 EXT 1777 hh Il 6 E X 2747 6 2757 6 2 2767 6 ORAB ORB gt B IND8 X C7 ff 6 A 0 IND8 Y D7 ff 6 IND8 Z E7 ff 6 IMM8 F7 ii 2 IND16 X 17 7 999g 6 IND16 Y 17D7 999g 6 IND16 Z 17E7 9999 6 17F7 hh Il 6 27 7 6 EY 27D7 6 2 27 7 6 ORD OR D D M M 1 gt D IND8 X 87 ff 6 A 0 IND8 Y 97 ff 6 IND8 Z A7 ff 6 IMM16 37B7 jj kk 4 IND16 X 37C7 999g 6 IND16 Y 37D7 999g 6 IND16 Z 37E7 999g 6 EXT 37F7 hh Il 6 2787 6 E Y 2797 6 E Z 27A7 6 ORE ORE E M M 1 gt IMM16 3737 jj kk 4 0 IND
252. d and write SCCRO at any time Changing the value of SCCRO bits during a transfer operation can disrupt the transfer Bits 15 13 Not Implemented SCBR 12 0 SCI Baud Rate SCI baud rate is programmed by writing a 13 bit value to this field Writing a value of zero to SCBR disables the baud rate generator Baud clock rate is calculated as fol lows MOTOROLA MC68HC16R1 916R1 D 46 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc sys SCI Baud Rate 32 x SCBR 12 0 or fs A ys SOBRMAO 32 x SCI Baud Rate Desired where SCBR 12 0 is in the range of 1 to 8191 Writing a value of zero to SCBR dis ables the baud rate generator There are 8191 different bauds available The baud val ue depends on the value for SCBR and the system clock as used in the equation above Table D 34 shows possible baud rates for a 16 78 MHz system clock The maximum baud rate with this system clock speed is 524 kbaud Table D 34 Examples of SCI Baud Rates Ch pied Percent Error Value of SCBR 500 00 00 524 288 00 4 86 1 38 400 00 37 449 14 2 48 14 32 768 00 32 768 00 0 00 16 19 200 00 19 418 07 1 14 27 9 600 00 9 532 51 0 70 55 4 800 00 4 809 98 0 21 109 2 400 00 2 404 99 0 21 218 1 200 00 1 199 74 0 02 437 600 00 599 87 0 02 874 300 00 299 94 0 02 1 748 110 00 110 01 0 01 4 766 64 00 64 00 0 01 8 191
253. d bus analysis capabilities including Real time in circuit emulation at maximum speed of 16 MHz Built in emulation memory 1 Mbyte main emulation memory three clock bus cycle 256 Kbyte fast termination two clock bus cycle 4 Kbyte dual port emulation memory three clock bus cycle Real time bus analysis Instruction disassembly State machine controlled triggering Four hardware breakpoints bitwise masking e Analog digital emulation Synchronized signal output Built in AC power supply 90 264 V 50 60 Hz FCC and EMI compliant RS 232 connection to host capable of communicating at 1200 2400 4800 9600 19200 38400 or 57600 baud C 2 M68MEVB1632 Modular Evaluation Board The M68MEVB1632 Modular Evaluation Board MEVB is a development tool for evaluating M68HC16 and M68300 MCU based systems The MEVB consists of the M68MPFB1632 modular platform board an MCU personality board MPB an in circuit debugger ICD16 or ICD32 and development software MEVB features include MC68HC16R1 916R1 DEVELOPMENT SUPPORT MOTOROLA USER S MANUAL For More Information On This Product 1 Go to www freescale com Freescale Semiconductor Inc An economical means of evaluating target systems incorporating M68HC16 and M68300 HCMOS MCU devices Expansion memory sockets for installing RAM EPROM or EEPROM Data RAM 32K x 16 128K x 16 or 512K x 16 EPROM EEPROM 32K x 16 64K x 16 128K x 16
254. d the reset configuration of CS 10 6 ADDR 23 19 This register may be read or written at any time After reset software may enable one or more pins as discrete outputs MC68HC16R1 916R1 REGISTER SUMMARY USER S MANUAL MOTOROLA For More Information On This Product D 19 Go to www freescale com Freescale Semiconductor Inc Table D 11 Reset Pin Function of CS 10 6 Data Bus Pins at Reset Chip Select Address Bus Pin Function CS10 CS9 CS8 CS7 CS6 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 CS10 59 CS8 CS7 CS6 CS10 59 CS8 CS7 ADDR19 CS10 CS9 CS8 ADDR20 ADDR19 CS9 ADDR21 ADDR20 ADDR19 510 ADDR22 ADDR21 ADDR20 ADDR19 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 DATA6 DATAS DATA4 DATAS3 x x XxX O 4 x x x X oj st C 1 1 1 1 1 1 1 1 1 0 0 X D 2 24 Chip Select Base Address Register Boot CSBARBT Chip Select Base Address Register Boot YFFA48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 23 22 21 20 19 18 17 16 15 14 13 12 11 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 BLKSZ 2 0 D 2 25 Chip Select Base Address Registers CSBAR 0 10 Chip Select Base Address Registers YFFA4C YFFA74 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR ADDR ADDR ADDR ADDR ADDR
255. de the array retains its contents but cannot be read or written This bit can be read or written at any time RLCK RAM Base Address Lock 0 SRAM base address registers can be written 1 SRAM base address registers are locked and cannot be modified RLCK defaults to zero on reset it can be written once to a one and may be read at any time RASP 1 0 RAM Array Space The RASP field limits access to the SRAM array in microcontrollers that support separate user and supervisor operating modes RASP1 has no effect because the CPU16 operates in supervisor mode only This bit may be read or written at any time Refer to Table D 19 Table D 19 SRAM Array Address Space Type RASP 1 0 Space X0 Program and data accesses X1 Program access only MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 26 For More Information On This Product USER S MANUAL Go to www freescale com D 3 2 RAM Test Register Freescale Semiconductor Inc RAMTST RAM Test Register YFFBO2 Used for factory test only D 3 3 Array Base Address Registers RAMBAH Array Base Address Register High YFFBOA 15 8 1 6 5 4 3 2 1 0 RESET NOT USED ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 RAMBAL Array Base Address Register Low YFFBO6G 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR 15 ADDR 14 ADDR 13 ADDR 12 ADDR 11
256. detects assertion of the IMB BERR signal BERR assertions do not force immediate exception processing The signal is synchro nized with normal bus cycles and is latched into the CPU16 at the end of the bus cycle in which it was asserted Because bus cycles can overlap instruction boundaries bus error exception processing may not occur at the end of the instruction in which the bus cycle begins Timing of BERR detection acknowledge is dependent upon several factors Which bus cycle of an instruction is terminated by assertion of BERR The number of bus cycles in the instruction during which BERR is asserted The number of bus cycles in the instruction following the instruction in which BERR is asserted Whether BERR is asserted during a program space access or a data space access Because of these factors it is impossible to predict precisely how long after occur rence of a bus error the bus error exception is processed MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 37 Go to www freescale com Freescale Semiconductor Inc NOTE The external bus interface does not latch data when an external bus cycle is terminated by a bus error When this occurs during an in struction prefetch the IMB precharge state bus pulled high or FF is latched into the CPU16 instruction register with indeterminate re sults 5 6 5 2 Double Bus Faults Except
257. dog timer and determines that one of two options either no prescaling or prescaling by a factor of 512 can be selected The value of SWP is affected by the state of the MODCLK pin during reset as shown in Table 5 5 System software can change SWP value Table 5 5 MODCLK Pin and SWP Bit During Reset MODCLK SWP 0 External Clock 1 512 1 Internal Clock 0 1 SWT 1 0 selects the divide ratio used to establish the software watchdog timeout period The following equation calculates the timeout period for a slow reference frequency Divide Ratio Specified by SWP SWTT 1 0 Timeout Period ref The following equation calculates the timeout period for a fast reference frequency 128 Divide Ratio Specified by SWP and SWT 1 0 Timeout Period The following equation calculates the timeout period for an externally input clock frequency on both slow and fast reference frequency devices Divide Ratio Specified by SWP SWTT 1 0 Timeout Period ref Table 5 6 shows the divide ratio for each combination of SWP and SWT 1 0 bits When SWT 1 0 are modified a watchdog service sequence must be performed be fore the new timeout period can take effect MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 18 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 6 Software Watchdog Divide Ratio
258. ds that appropriate signal lines be routed to a male Berg connector or double row header installed on the circuit board with the MCU Refer to Figure 4 8 BKPT DSCLK FREEZE IPIPE1 DSI IPIPEQ DSO BDM CONN Figure 4 8 BDM Connector Pinout MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product 4 45 Go to www freescale com Freescale Semiconductor Inc 4 16 Digital Signal Processing The CPU16 performs low frequency digital signal processing DSP algorithms in real time The most common DSP operation in embedded control applications is filtering but the CPU16 can perform several other useful DSP functions These include auto correlation detecting a periodic signal in the presence of noise cross correlation de termining the presence of a defined periodic signal and closed loop control routines selective filtration in a feedback path Although derivation of DSP algorithms is often a complex mathematical task the algo rithms themselves typically consist of a series of multiply and accumulate MAC op erations The CPU16 contains a dedicated set of registers that perform MAC operations As a group these registers are called the MAC unit DSP operations generally require a large number of MAC iterations The CPU16 in struction set includes instructions that perform MAC setup and repetitive MAC opera tions Other instructions such as 32 bit load and store instructions can also be used in DSP
259. e 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 5040000 suc 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 002 16 LEVEL 6 INTERRUPT AUTOVECTOR 050000 7777777 002 17 LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032 006 19 37 UNASSIGNED RESERVED 060000 4 0070 01 38 FF USER DEFINED INTERRUPTS 0001FE BANK 6 PROGRAM 070000 gak AND DATA 777 SPACE Y 5080000 UNDEFINED YFF700 UNDEFINED ADC YFF73F y FIFFFF 580000 Banks ROM Y FF 820 F90000 7777777 CONTROL FA0000 77777 900 7 0000 BANK 11 KU ge Ne SY FF OFF 512 KBYTE 00 SECUQUUA aa So SY FFAT7F FD0000 guis SRAM YFFBOO CONTROL YFFBOT FE0000 7 YFFCOO0 MCCI 0000 pas Y YFFC3F INTERNAL REGISTERS YFFDFF Y FFFFFF TE 1 ADDRESSES DISPLA YED IN THIS MEMOR Y MAP ARE THE FULL 24 IMB ADDRESSES THE CPU16 ADDRESS B US IS 20 BITS WIDE AND CPU16 ADDRESS LINE 19 DRIVES IMB ADDRESS LINES 23 20 THE BLOCK OF ADDRESSES FR 5080000 TO F7FFFF MARKED AS UNDEFINED WILL NEVER APPEAR ON THE IMB MEMOR Y BANKS 0 TO 15 APPEAR FULL Y CONTIGUOUS IN THE CPU16 S FLA T 20 BIT ADDRESS SP ACE THE CPU16 NEED ONL Y GENERA TE A 20 BIT EFFECTIVE ADDRESS ACCESS ANY LOCA TION IN THIS RANGE 16R1 MEM MAP C Figure 3 8 MC68HC16R1 Combined Program and Data Space Map MC68HC16R1 916R1 OVERVIEW MOTOROLA USER S MANUAL For More Informa
260. e BEFLASH module for erasure Write to any valid address in the control block or array This allows the erase voltage to be turned on The data written and the address written to are of no consequence Set ENPE to apply programming voltage Delay long enough for one erase pulse to occur tepulse Clear ENPE to remove programming voltage Delay while high voltage is turning off tyerase Clear LAT ERAS and VFPE to allow normal access to the BEFLASH Read the entire array and control block to ensure that the entire module is erased If all of the locations are not erased calculate a new value for tepuise and repeat steps 3 through 10 until either the remaining locations are erased or the maxi mum erase time terasemax has expired 12 If all locations are erased calculate temargin and repeat steps 3 through 10 If all locations do not remain erased the BEFLASH module may be bad 13 Turn off VEpgak reduce voltage on Vrepgoy pin to Vpp MOTOROLA BLOCK ERASABLE FLASH EEPROM MC68HC16R1 916R1 9 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 10 ANALOG TO DIGITAL CONVERTER This section is an overview of the analog to digital converter module ADC Refer to the ADC Reference Manual ADCRM AD for a comprehensive discussion of ADC ca pabilities Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for ADC timing and electrical specifications Refer t
261. e PLL feedback path enabling frequency multiplication by a factor from one to eight Three Y bits and the X bit are located in the VCO clock output path to provide the ability to slow the system clock without disturbing the PLL When using a fast reference the clock frequency is determined by SYNCR bit settings as follows f fsys ig 4 Y 1 The reset state of SYNCR 3F00 results in a power on fey of 8 388 MHz when fref is 4 194 MHz MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc For the device to perform correctly both the clock frequency and VCO frequency selected by the W X and Y bits must be within the limits specified for the MCU In order for the VCO frequency to be within specifications less than or equal to the maximum system clock frequency multiplied by two the X bit must be set for system clock frequencies greater than one half the maximum specified system clock Internal VCO frequency is determined by the following equations fvco 4fsys if X 0 or fvco 2fsys if X 1 On both slow and fast reference devices when an external system clock signal is applied MODCLK 0 during reset the PLL is disabled The duty cycle of this signal is critical especially at operating frequencies close to maximum The relationship between clock signal duty cycle and clock signal period is ex
262. e affected The halt monitor and spurious interrupt monitor continue to operate normally Setting the freeze bus monitor FRZBM bit in SCIMCR disables the bus monitor when FREEZE is asserted Setting the freeze software watchdog FRZSW bit disables the software watchdog and the periodic interrupt timer when FREEZE is asserted 5 3 System Clock The system clock in the SCIM2 provides timing signals for the IMB modules and for an external peripheral bus Because the MCU is a fully static design register and memory contents are not affected when the clock rate changes System hardware and software support changes in clock rate during operation The system clock signal can be generated from one of three sources An internal phase locked loop PLL can synthesize the clock from a fast reference a slow reference or the clock signal can be directly input from an external frequency source NOTE Whether the PLL can use a fast or slow reference is determined by the device A particular device cannot use both a fast and slow reference MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The fast reference is typically a 4 194 MHz crystal the slow reference is typically 32 768 kHz crystal Each reference frequency may be generated by sources other than a crystal Keep these sources in mind while reading the rest of this sect
263. e chip and 8 bit expanded modes only The function of these pins is determined by the operating mode There is no pin assignment register associated with this port The port H data register PORTH can be read or written any time the MCU is not in emulation mode Reset has no effect Port H data direction register DDRH bits control the direction of the port pin drivers when pins are configured as I O Setting a bit configures the corresponding pin as an output Clearing a bit configures the corresponding pin as an input MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 74 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 11 Factory Test The test submodule supports scan based testing of the various MCU modules It is in tegrated into the SCIM2 to support production test Test submodule registers are in tended for Motorola use only Register names and addresses are provided in APPENDIX D REGISTER SUMMARY to show the user that these addresses are oc cupied The QUOT pin is also used for factory test MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 75 Go to www freescale com Freescale Semiconductor Inc MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 76 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 6
264. e com Freescale Semiconductor Inc VECTOR VECTOR YPE OF ADDRESS NUMBER EXCEPTION 5000000 EI scr ano EXCEPTION 0000 0 RESET INITIAL ZK SK AND PK 5000000 VECTORS 0002 RESET INITIAL PC n RESET SA PAGE 5010000 0008 4 BKPT BREAKPOINT 000A 5 BERR BUS ERROR 000 6 SWI SOFTWARE INTERRUPT 020000 gQuk2 777777 000 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO 0012 001C 9 UNASSIGNED RESERVED 001 F UNINITIALIZED INTERRUPT 030000 aa 7771777770707 0020 10 UNASSIGNED RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 512 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR io SE See BoE zeige 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 5040000 suc 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVEL 5 INTERRUPT AUTOVECTOR 002 16 LEVEL 6 INTERRUPT AUTOVECTOR 050000 7777777 002 17 LEVEL 7 INTERRUPT AUTOVECTOR 0030 18 SPURIOUS INTERRUPT 0032 006 19 37 UNASSIGNED RESERVED 060000 lid 0070 01 38 FF USER DEFINED INTERRUPTS PROGRAM YFF700 5070000 AND DATA ADC SPACE Y YFF73F 5080000 UNDEFINED UNDEFINED BEFLASH MELIND YFF7BF y FIFFFF 16K FLASH YFF800 A F 80000 BANK8 CONTROL 32K FLASH YFF820 F90000 7777777 CONTROL FA0000 77777 900 7 0000 BANK 11
265. e detect start count on first one 1 Long idle line detect start count on first one after stop bit s PT Parity Type 0 Even parity 1 Odd parity PE Parity Enable 0 SCI parity disabled 1 SCI parity enabled Mode Select 0 10 bit SCI frame 1 start bit 8 data bits 1 stop bit 1 11 bit SCI frame 1 start bit 9 data bits 1 stop bit WAKE Wakeup by Address Mark 0 SCI receiver awakened by idle line detection 1 SCI receiver awakened by address mark last data bit set TIE Transmit Interrupt Enable 0 SCI TDRE interrupts disabled 1 SCI interrupts enabled TCIE Transmit Complete Interrupt Enable 0 SCI TC interrupts disabled 1 SCI TC interrupts enabled RIE Receiver Interrupt Enable 0 SCI RDRF OR interrupts disabled 1 SCI RDRF and OR interrupts enabled ILIE Idle Line Interrupt Enable 0 SCI IDLE interrupts disabled 1 SCI IDLE interrupts enabled MOTOROLA MC68HC16R1 916R1 D 48 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc TE Transmitter Enable 0 SCI transmitter disabled TXD can be used as 1 1 SCI transmitter enabled TXD pin dedicated to SCI transmitter RE Receiver Enable 0 SCI receiver disabled 1 SCI receiver enabled RWU Receiver Wakeup 0 Normal receiver operation received data recognized 1 Wakeup mode enabled re
266. e fetched from even word boundaries Address line 0 always has a value of zero during instruction fetches to ensure that instructions are fetched from word aligned addresses MC68HC16R1 916R1 CENTRAL PROCESSOR UNIT MOTOROLA USER S MANUAL For More Information On This Product 4 3 Go to www freescale com Freescale Semiconductor Inc 4 2 5 Condition Code Register The 16 bit condition code register is composed of two functional blocks The eight MSB which correspond to the CCR on the M68HC11 contain the low power stop con trol bit and processor status flags The eight LSB contain the interrupt priority field the DSP saturation mode control bit and the program counter address extension field Figure 4 2 shows the condition code register Detailed descriptions of each status in dicator and field in the register follow the figure 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 MV H EV N 2 IP 2 0 SM PK 3 0 Figure 4 2 Condition Code Register S STOP Enable 0 Stop clock when LPSTOP instruction is executed 1 Perform NOP when LPSTOP instruction is executed MV Accumulator M Overflow Flag MV is set when an overflow into AM35 has occurred H Half Carry Flag H is set when a carry from A3 or B3 occurs during BCD addition EV Accumulator M Extension Overflow Flag EV is set when an overflow into AM31 has occurred N Negative Flag N is set under the following conditions
267. e flash EEPROM array base address MOTOROLA FLASH EEPROM MODULE MC68HC16R1 916R1 8 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc If the STOP shadow bit is one or the module s associated data bus pin is pulled low during reset the STOP bit in the FEExMCR is set The flash EEPROM array is disabled until the STOP bit is cleared by software It will not respond to the bootstrap address range or the flash EEPROM array base address in and FEExBAL allowing an external device to respond to the flash EEPROM array s address space or bootstrap information Since the erased state of the shadow bits is one erased flash EEPROM modules which include the shadow registers in the control blocks come out of reset in STOP mode 8 3 2 Bootstrap Operation After reset the CPU begins bootstrap operation by fetching initial values for its internal registers from special bootstrap word addresses 000000 through 000006 If BOOT 0 and STOP 0 in FEExMCR the flash EEPROM module is configured to recognize these addresses after a reset and provide this information from the FEExBS 3 0 bootstrap registers in the flash EEPROM control block The information in these registers is programmed by the user 8 3 3 Normal Operation The flash EEPROM module allows a byte or aligned word read in one bus cycle Long word reads require two bus cycles The module checks function codes to
268. e of the RES10 bit in ADCTLO Both 8 bit and 10 bit conversion results are automatically aligned in the result registers 10 7 5 Conversion Control Logic MC68HC16R1 916R1 USER S MANUAL Analog to digital conversions are performed in sequences Sequences are initiated by any write to ADCTL1 If a conversion sequence is already in progress a write to either control register will abort it and reset the SCF and CCF flags in the A D status register There are eight conversion modes Conversion mode is determined by ADCTL1 con trol bits Each conversion mode affects the bits in status register ADSTAT differently Result storage differs from mode to mode MOTOROLA 10 7 ANALOG TO DIGITAL CONVERTER For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 10 7 5 1 Conversion Parameters Table 10 5 describes the conversion parameters controlled by bits in ADCTL1 Table 10 5 Conversion Parameters Controlled by ADCTL1 Conversion Parameter Description The value of the channel selection field CD CA in ADCTL1 determines which multiplexer inputs are used in a conversion sequence There are 16 possible inputs Seven inputs are external pins AN 6 0 and nine are internal Conversion channel conversion sequence consists of either four or eight conversions The Length of sequence number of conversions in a sequence is determined by the state of the S8CM bit in ADCTL1 Conversion can be li
269. e results of the operation The PK field is not affected 2 Cycle times for conditional branches are shown in taken not taken order 3 CCR 15 0 change according to the copy of the CCR pulled from the stack 4 PK field changes according to the state pulled from the stack The rest of the CCR is not affected MC68HC16R1 916R1 USER S MANUAL For More Information On This Product Go to www freescale com MOTOROLA 4 29 AM CCR XMSK YMSK MV EV OD A VvV ll A lt 4 30 Freescale Semiconductor Inc Table 4 3 Instruction Set Abbreviations and Symbols Accumulator A Accumulator M Accumulator B Condition code register Accumulator D Accumulator E Extended addressing extension field MAC multiplicand register MAC multiplier register Index register X Index register Y Index register Z Address extension register Program counter Program counter extension field Stack pointer extension field Multiply and accumulate sign latch Stack pointer Index register X extension field Index register Y extension field Index register Z extension field Modulo addressing index register X mask Modulo addressing index register Y mask Stop disable control bit AM overflow indicator Half carry indicator extended overflow indicator Negative indicator Zero
270. e shown in Table 11 6 Table 11 6 Serial Frame Formats 10 Bit Frames Start Data Parity Control Stop 1 7 2 1 7 1 1 1 8 1 11 Bit Frames Start Data Parity Control Stop 1 7 1 2 1 8 1 1 11 4 5 3 Baud Clock The SCI baud rate is programmed by writing a 13 bit value to the SCBR field in SCI control register zero SCCRO The baud rate is derived from the MCU system clock by a modulus counter Writing a value of zero to SCBR 12 0 disables the baud rate generator Baud rate is calculated as follows f o s yY SCI Baud Rate 45 SCBRI12 0 or sys SCBR 12 0 32 x SCI Baud Rate Desired where SCBR 12 0 is in the range 1 2 3 8191 The SCI receiver operates asynchronously An internal clock is necessary to synchro nize with an incoming data stream The SCI baud rate generator produces a receive time sampling clock with a frequency 16 times that of the SCI baud rate The SCI de termines the position of bit boundaries from transitions within the received waveform and adjusts sampling points to the proper positions within the bit period MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 18 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 11 4 5 4 Parity Checking The PT bit in SCCR1 selects either even PT 0 or odd PT 1 parity PT affects received and transmitted data The PE bit in SCCR1 d
271. e tet idee 12 3 12 4 2 Freeze Effect On the BIUSM 12 3 12 4 3 LPSTOP Effect on the BIUSM 12 4 12 4 4 BIUSNIERGQSISIBIS rx ro o eve ts a egeta inci t emi am qn 12 4 12 5 Counter Prescaler Submodule CPSM 12 4 12 5 1 CPSM Registers HR HIER tI uS 12 5 12 6 Free Running Counter Submodule FCSM 12 5 12 6 1 xeu ge eeu Or p CU CE EE 12 6 12 6 2 POM ClOCK SOUFGOS tui cp DER REN 12 6 12 6 3 FCSM External Event Counting 12 7 12 6 4 FCSM Time Base Bus Driver 12 7 12 6 5 FCSM 12 7 12 6 6 FCSM 12 7 12 7 Modulus Counter Submodule 12 7 12 7 1 MOSM Modulus Latch erp 12 8 12 7 2 MC SM Co teru us 12 8 12 7 2 1 Loading the Counter Register 12 9 12 7 2 2 Using the as a Free Running Counter 12 9 12 7 3 MCSM Clock Sources 12 9 12 7 4 MCSM External Event Counting
272. e the array can be accessed Avoid using a base address value that causes the array to overlap control registers If a portion of the array overlaps the EEPROM register block the registers remain accessible but accesses to that portion of the array are ignored If the array overlaps the control block of another module however those registers may become inaccessible If the BEFLASH array overlaps another memory array RAM or flash EEPROM proper access to one or both arrays may not be possible 9 4 BEFLASH Operation The following paragraphs describe the operation of the BEFLASH during reset sys tem boot normal operation and while it is being programmed or erased 9 4 1 Reset Operation Reset initializes all BEFLASH control registers Some bits have fixed default values and some take values that are programmed into the associated BEFLASH shadow registers If the state of the STOP shadow bit is zero and data bus pin DATA15 is pulled high during reset the STOP bit in BFEMCR is cleared during reset and the module responds to accesses in the range specified by BFEBAH and BFEBAL When the BOOT bit is cleared the module also responds to bootstrap vector accesses If the state of the STOP shadow bit is one or data bus pin DATA15 is pulled low during reset the STOP bit in BFEMCR is set during reset and the BEFLASH array is disabled The module does not respond to array or bootstrap vector accesses until the STOP bit is cleared This all
273. ecifications for the flash EEPROM module MC68HC16R1 916R1 FLASH EEPROM MODULE MOTOROLA USER S MANUAL For More Information On This Product 8 3 Go to www freescale com Freescale Semiconductor Inc 8 3 5 Programming The following steps are used to program a flash EEPROM array Figure 8 1 is a flowchart of the programming operation Figures A 22 and A 23 in APPENDIX A ELECTRICAL CHARACTERISTICS for Vepe to Vpp relationships during programming 1 2 3 Increase voltage applied to the pin to program erase verify level Clear the ERAS bit and set the LAT bit in FEExCTL This enables the program ming address and data latches Write data to the address to be programmed This latches the address to be programmed and the programming data Setthe ENPE bit in FEExCTL This starts the program pulse Delay the proper amount of time for one programming pulse to take place De lay is specified by parameter p Clear the ENPE bit in FEExCTL This stops the program pulse Delay while high voltage to array is turned off Delay is specified by parameter tor pr Read the address to verify that it has been programmed If the location is not programmed repeat steps 4 through 7 until the location is programmed or until the specified maximum number of program pulses has been reached Maximum number of pulses is specified by parameter Npp 10 If the location is programmed repeat the same number
274. ecognition The CPU16 provides for seven levels of interrupt priority 1 7 seven automatic interrupt vectors and 200 assignable interrupt vectors All interrupts with priorities less than seven can be masked by the interrupt priority IP field in the condition code register There are seven interrupt request signals IRQ 7 1 These signals are used internally on the IMB and there are corresponding pins for external interrupt service requests The CPU16 treats all interrupt requests as though they come from internal modules external interrupt requests are treated as interrupt service requests from the SCIM2 Each of the interrupt request signals corresponds to an interrupt priority level IRQ1 has the lowest priority and IRQ7 the highest The IP field consists of three bits CCR 7 5 Binary values 96000 to 96111 provide eight priority masks Masks prevent an interrupt request of a priority less than or equal to the mask value except for IRQ7 from being recognized and processed When IP contains 96000 no interrupt is masked During exception processing the IP field is set to the priority of the interrupt being serviced Interrupt recognition is determined by interrupt priority level and interrupt priority IP mask value The interrupt priority mask consists of three bits in the CPU16 condition code register CCR 7 5 Binary values 96000 to 96111 provide eight priority masks Masks prevent an interrupt request of a priority
275. ecution of the BGND instruction IPIPEO and IPIPE1 change function be fore an exception signal can be generated The development system must use FREEZE assertion as an indication that BDM has been entered When BDM is exited FREEZE is negated before initiation of normal bus cycles IPIPEO and IPIPE1 are valid when normal instruction prefetch begins 4 14 4 4 BDM Commands Commands consist of one 16 bit operation word and can include one or more 16 bit extension words Each incoming word is read as it is assembled by the serial interface The microcode routine corresponding to a command is executed as soon as the command is complete Result operands are loaded into the output shift register to be shifted out as the next command is read This process is repeated for each command until the CPU returns to normal operating mode The BDM command set is summa rized in Table 4 7 Refer to the CPU16 Reference Manual CPU16RM AD for a BDM command glossary Table 4 7 Command Summary Command Mnemonic Description Read Registers Read contents of registers specified by command RREGM from Mask Write Registers from Mask word register mask Write to registers specified by command word register mask Read MAC Registers Read contents of entire multiply and accumulate register set Write MAC Registers Write to entire multiply and accumulate register set Read PC and SP Read contents of program counter and stack pointer
276. ed Table 5 13 is a summary of the acceptable bus cycle terminations for asynchronous cycles in relation to DSACK assertion MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 36 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 13 DSACK BERR and HALT Assertion Results Type of Conirol Asserted on Rising Description Termination Signal Edge of State of Result s 2 NORMAL DSACK Normal cycle terminate and continue BERR x HALT DSACK A RA Normal cycle terminate and halt BERR NA NA Continue when HALT is negated HALT A RA RA BUS ERROR DSACK NA A X Terminate and take bus error exception 1 BERR A RA HALT NA X BUS ERROR DSACK A X Terminate and take bus error exception 2 BERR A RA HALT NA NA BUS ERROR DSACK NA A X Terminate and take bus error exception 3 BERR A RA HALT A S RA BUS ERROR DSACK A X Terminate and take bus error exception 4 BERR NA A HALT NA A NOTES 1 S The number of current even bus state for example S2 S4 etc 2 A Signal is asserted in this bus state 3 NA Signal is not asserted in this state 4 RA Signal was asserted in previous state and remains asserted in this state 5 X Don t care 5 6 5 1 Bus Errors The CPU16 treats bus errors as a type of exception Bus error exception processing begins when the CPU16
277. ed Because of pipelining the value of PK PC at the time a synchronous exception exe cutes is equal to the address of the instruction that causes the exception plus 0006 Because RTI always subtracts 0006 upon return the stacked PK PC must be ad justed by the instruction that caused the exception so that execution resumes with the following instruction For this reason 0002 is added to the PK PC value before it is stacked MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product 4 39 Go to www freescale com Freescale Semiconductor Inc 4 13 5 Multiple Exceptions Each exception has a hardware priority based upon its relative importance to system operation Asynchronous exceptions have higher priorities than synchronous excep tions Exception processing for multiple exceptions is completed by priority from high est to lowest Priority governs the order in which exception processing occurs not the order in which exception handlers are executed Unless a bus error a breakpoint or a reset occurs during exception processing the first instruction of all exception handler routines is guaranteed to execute before an other exception is processed Because interrupt exceptions have higher priority than synchronous exceptions the first instruction in an interrupt handler are executed be fore other interrupts are sensed Bus error breakpoint and reset exceptions that occur during exception processing o
278. ed BERR Expanded mode Single chip mode DATA if BERR 1 8 Bit expanded mode 16 Bit expanded mode BERR BKPT and MODCLK do not have internal pull ups and must be driven to the desired state during reset When BERR is high during reset the MCU is configured for partially or fully expanded operation DATA2 is then decoded to select 8 or 16 bit data bus operation DATA8 is decoded to configure pins for bus control or port E operation and DATAQ is decoded to configure pins for interrupt requests or port F operation If DATA1 is held low at re set selecting 16 bit data bus operation DATA11 DATA 7 2 and DATAO are also de coded The following subsections explain the process in greater detail 5 7 3 1 Address and Data Bus Pin Functions External bus configuration determines whether certain address and data pins are used for those functions or for general purpose I O ADDR 18 3 serve as pins for ports A and B when the MCU is operating in single chip mode DATA 7 0 serve as port H pins in partially expanded and single chip modes and DATA 15 8 serve as port G pins during single chip operation Table 5 16 summarizes bus and port configuration op tions Table 5 16 Bus and Port Configuration Options Mode Address Bus Data Bus Ports 16 Bit Expanded ADDR 18 3 DATA 15 0 8 Bit Expanded ADDR 18 3 DATA 15 8 DATA 7 0 Port H ADDR 18 11 Port A ADDR 10 3 Port B DATA 15 8 Port G DATA 7 0 Port H
279. eld in the MCSMSIC to a non zero value The CTM7 compares the CPU16 IP mask value to the priority of the requested interrupt designated by IL 2 0 to determine whether it should contend for arbitration priority During arbitration the BIUSM provides the arbitration value specified by IARB 2 0 in BIUMCR and IARB3 MCSMSIC If the CTM7 wins arbitra tion it responds with a vector number generated by concatenating VECT 7 6 in BIUMCR and the six low order bits specified by the number of the submodule request ing service Thus for MCSM12 CTM7 six low order bits would be 12 in decimal or 001100 in binary 12 7 7 MCSM Registers The MCSM contains a status interrupt control register a counter and a modulus latch All unused bits and reserved address locations return zero when read Writes to un used bits and reserved address locations have no effect The CTM7 contains three MCSMs each with its own set of registers Refer to D 7 6 MCSM Status Interrupt Control Registers D 7 7 MCSM Counter Registers and D 7 8 MCSM Modulus Latch Registers for information concerning MCSM register and bit descriptions 12 8 Single Action Submodule SASM The single action submodule SASM provides two identical channels each having its own input output pin but sharing the same interrupt logic priority level and arbitration number Each channel can be configured independently to perform either input cap ture or output compare Table 12 2 shows the di
280. elect signal When a 16 bit port is assigned however BYTE field value determines when the chip select is enabled The BYTE fields for CS 10 0 are cleared during reset However both bits in the boot ROM chip select option register CSORBT BYTE field are set 11 when the RESET signal is released R W 1 0 causes chip select signal to be asserted only for a read only for a write or for both read and write Use this field in conjunction with the STRB bit to generate asynchronous control signals for external devices The STRB bit controls the timing of a chip select assertion in asynchronous mode Se lecting address strobe causes a chip select signal to be asserted synchronized with the address strobe Selecting data strobe causes a chip select signal to be asserted synchronized with the data strobe This bit has no effect in synchronous mode DSACK 3 0 specifies the source of DSACK in asynchronous mode It also allows the user to optimize bus speed in a particular application by controlling the number of wait states that are inserted NOTE The external DSACK pins are always active SPACE 1 0 determines the address space in which a chip select is asserted An ac cess must have the space type represented by the SPACE 1 0 encoding in order for a chip select signal to be asserted IPL 2 0 contains an interrupt priority mask that is used when chip select logic is set to trigger on external interrupt acknowledge cycles When SPACE
281. en the true analog ground and the microcontroller s ground pin The end result is that the ground observed by the analog circuit is no longer true ground and often ends in skewed results Two similar approaches designed to improve or eliminate the problems associated with grounding excess transient currents involve star point ground systems One ap proach is to star point the different grounds at the power supply origin thus keeping the ground isolated Refer to Figure 10 6 ANALOG POWER SUPPLY DIGITAL POWER SUPPLY AGND x PGND ADC POWER SCHEM Figure 10 6 Star Ground at the Point of Power Supply Origin MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For More Information On This Product 10 17 Go to www freescale com Freescale Semiconductor Inc Another approach is to star point the different grounds near the analog ground pin on the microcontroller by using small traces for connecting the nonanalog grounds to the analog ground The small traces are meant only to accommodate DC differences not AC transients NOTE This star point scheme still requires adequate grounding for digital and analog subsystems in addition to the star point ground Other suggestions for PCB layout in which the ADC is employed include the following analog ground must be low impedance to all analog ground points in the cir cuit e Bypass capacitors should be as
282. ent quantization error and 2 counts 10 mV circuit differential integral and offset error 5 Maximum source impedance is application dependent Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge sharing with internal capacitance Error from junction leakage is a function of external source impedance and input leakage current Expected error in result value due to junction leakage is expressed in voltage Venn Rsx lore where is a function of operating temperature as shown in Table 11 Charge sharing leakage is a function of input source impedance conversion rate change in voltage between successive conversions and the size of the decoupling capacitor used Error levels are best determined em pirically In general continuous conversion of the same channel may not be compatible with high source im pedance MC68HC16R1 916R1 USER S MANUAL For More Information On This Product Go to www freescale com MOTOROLA A 27 MOTOROLA A 28 DIGITAL OUTPUT Freescale Semiconductor Inc I N IDEAL TRANSFER CURVE Z i eet TRANSFER CURVE NO CIRCUIT ERROR 2 NN qv 20 INPUT IN mV Vp 40 H VRL 725 120 V A 1 2 COUNT 10 mV INHERENT QUANTIZATION ERROR B CIRCUIT CONTRIBUTED 10mV ERROR C 20 mV ABSOLUTE ERROR ONE 8 BIT COUNT Figure A 20 8 Bit ADC Conversion Accuracy
283. er counts logic ones after the stop bit is received Only a complete idle frame causes the IDLE flag to be set MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL For More Information On This Product 11 21 Go to www freescale com Freescale Semiconductor Inc In some applications software overhead can cause a bit time of logic level one to oc cur between frames This bit time does not affect content but if it occurs after a frame of ones when short detection is enabled the receiver flags an idle line When the bit in SCCR1 is set an interrupt request is generated when the IDLE flag is set The flag is cleared by reading SCSR and SCDR in sequence IDLE is not set again until after at least one frame has been received RDRF 1 This prevents an extended idle interval from causing more than one interrupt 11 4 5 8 Receiver Wake Up The receiver wake up function allows a transmitting device to direct a transmission to a single receiver or to a group of receivers by sending an address frame at the start of a message Hardware activates each receiver in a system under certain conditions Resident software must process address information and enable or disable receiver operation A receiver is placed in wake up mode by setting the RWU bit in SCCR1 While RWU is set receiver status flags and interrupts are disabled Although the CPUS2 can clear RWU it is normally cleared by hardware during wake up T
284. er ty m 50 ns Slave 50 ns Data Hold Time Outputs 12 Master tho 0 E ns Slave 0 ns Rise Time 13 Input tri 2 us Output tro 30 ns Fall Time 14 Input tfi 2 us Output t o 30 ns NOTES 1 All AC timing is shown with respect to Vjy V levels unless otherwise noted 2 For high time n External SCK rise time for low time n External SCK fall time MOTOROLA MC68HC16R1 916R1 A 22 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT 16 MCCI MAST CPHAO SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT MOSI OUTPUT 16 MCCI MAST 1 Figure A 17 SPI Timing Master CPHA 1 MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product A 23 Go to www freescale com Freescale Semiconductor Inc MSB OUT LSB IN 16 MCCI SLV CPHAO OUTPUT 16 MCCI SLV CPHA1 Figure A 19 SPI Timing Slave CPHA 1 MOTOROLA MC68HC16R1 916R1 A 24 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 10 ADC Maximum Ratings Num Parameter Symbol Min Max Unit 1 Analog Supply VDDA 0 3 6 5 V 2 Internal Digital Supply with reference to Vas 0 3 6 5 V 3 Reference Supply with refere
285. erased If all locations not erased calculate a new value for tepk tei x pulse number and repeat steps 3 through 10 until all locations erase or the maximum number of pulses has been applied 10 If all locations are erased calculate the erase margin m and repeat steps 3 through 10 for the single margin pulse 11 Clear the LAT and ERAS bits in FEExCTL This allows normal access to the flash 12 Reduce voltage applied to the VEpg to normal read level MC68HC16R1 916R1 FLASH EEPROM MODULE MOTOROLA USER S MANUAL For More Information On This Product 8 5 Go to www freescale com Freescale Semiconductor Inc INCREASE V ppp T0 1 PROGRAM ERASE VERIFY LEVEL Y CLEAR ng COUNTER 2 CLEAR MARGIN FLAG Y SET LAT 3 CLEAR ERAS WRITE DATA TO ADDRESS f 2 SET ENPE 4 3 Y START PROGRAM PULSE TIMER pw pp Y DELAY FOR pw p Y CLEAR ENPE START tpr TIMER N Y Y READ LOCATION DELAY FOR tpr Tovey DECREMENT MARGIN FLAG COUNTER SET N INCREMENT n pp COUNTER READ LOCATION TO VERIFY N DATA CORRECT DATA CORRECT SET MARGIN FLAG Y LOCATION FAILED TO PROGRAM NOTES 1 SEE ELECTRICAL CHARACTERISTICS FOR V ppg PIN VOLTAGE SEQUENCING INCREMENT ADDRESS Y 4 CLEAR LAT DONE PROG
286. erate an interrupt One of the two incoming time base buses may be selected for each channel Each channel can also work as a simple I O pin A total of six SASMs 12 channels are contained in the CTM6 Figure 12 5 shows block diagram of the SASM INTERRUPT CONTROL SINGLE ACTION CHANNEL A IARB3 e m SINGLE ACTION CHANNEL B SUBMODULE BUS ba TIME BASE BUSES CTM SASM BLOCK Figure 12 5 SASM Block Diagram 12 8 1 SASM Interrupts The SASM can optionally request an interrupt when the FLAG bit in SASMSIC is set To enable interrupts set the IL 2 0 field in SASMSIC to a non zero value The CTM7 compares the CPU16 IP mask value to the priority of the requested interrupt designat ed by IL 2 0 to determine whether it should contend for arbitration priority During ar bitration the BIUSM provides the arbitration value specified by IARB 2 0 in BIUMCR and in SASMSIC If the CTM7 wins arbitration it responds with a vector number generated by concatenating VECT 7 6 in BIUMCR and the six low order bits specified by the number of the submodule requesting service Thus for SASM6 in the CTM7 the six low order bits would be six in decimal or 26000110 in binary MC68HC16R1 916R1 CONFIGURABLE TIMER MODULE 7 MOTOROLA USER S MANUAL For More Information On This Product 12 11 Go to www freescale com Freescale Semiconductor Inc 1
287. errupt request If an interrupt source of higher priority makes a service request while a lower priority request is pend ing the higher priority request is serviced If an interrupt request with a priority equal to or lower than the current IP mask value is made the CPU16 does not recognize the occurrence of the request If simultaneous interrupt requests of different priorities are made and both have a priority greater than the mask value the CPU16 recognizes the higher level request 5 8 3 Interrupt Acknowledge and Arbitration When the CPU16 detects one or more interrupt requests of a priority higher than the interrupt priority mask value it places the interrupt request level on the address bus and initiates a CPU space read cycle The request level serves two purposes it is decoded by modules or external devices that have requested interrupt service to de termine whether the current interrupt acknowledge cycle pertains to them and it is latched into the interrupt priority mask field in the CPU16 condition code register to preclude further interrupts of lower priority during interrupt service Modules or external devices that have requested interrupt service must decode the IP mask value placed on the address bus during the interrupt acknowledge cycle and re spond if the priority of the service request corresponds to the mask value However before modules or external devices respond interrupt arbitration takes place Arbitration is pe
288. errupt vector number The vector number is converted to a vector address The content of the vector address is loaded into the PC and the processor transfers control to the exception handler routine 5 8 5 Interrupt Acknowledge Bus Cycles Interrupt acknowledge bus cycles are CPU space cycles that are generated during ex ception processing For further information about the types of interrupt acknowledge bus cycles determined by AVEC or DSACK refer to APPENDIX A ELECTRICAL CHARACTERISTICS and the SC M Reference Manual SCIMRM AD 5 9 Chip Selects Typical microcontrollers require additional hardware to provide external chip select signals The MCU includes 12 programmable chip select circuits that can provide from 2 to 16 clock cycle access to external memory and peripherals Address block sizes of 2 Kbytes to 512 Kbytes can be selected However because ADDR 23 20 follow the state of ADDR19 512 Kbyte blocks are the largest usable size Figure 5 20 is a diagram of a basic system that uses chip selects MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 60 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Vpp Vpp Vpp Vpp Vpp Vpp A A A A A 10ko 1WkAS 10ko 10KES ADDR 3 0 ADDR 17 1 DATA 15 0 Vpp Kas 102 ADDR 15 1 DATA 15 8 ADDR 15 1 DATA
289. etermines whether parity check ing is enabled PE 1 or disabled PE 0 When is set the MSB of data in frame is used for the parity function For transmitted data a parity bit is generated for received data the parity bit is checked When parity checking is enabled the PF bit in the SCI status register SCSR is set if a parity error is detected Enabling parity affects the number of data bits in a frame which can in turn affect frame size Table 11 7 shows possible data and parity formats Table 11 7 Effect of Parity Checking on Data Size M PE Result 0 0 8 data bits 0 1 7 data bits 1 parity bit 1 0 9 data bits 1 1 8 data bits 1 parity bit 11 4 5 5 Transmitter Operation The transmitter consists of a serial shifter and a parallel data register TDR located in the SCI data register SCDR The serial shifter cannot be directly accessed by the CPU16 The transmitter is double buffered which means that data can be loaded into the TDR while other data is shifted out The TE bit in SCCR1 enables TE 1 and disables TE 0 the transmitter Shifter output is connected to the TXD pin while the transmitter is operating TE 1 or TE 0 and transmission in progress Wired OR operation should be specified when more than one transmitter is used on the same SCI bus The WOMS bit in SCCR1 determines whether TXD is an open drain wired OR output or a normal CMOS output An external pull up resistor on TXD
290. except during the proper clearing sequence INDE MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 12 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 11 4 Serial Communication Interface SCI The SCI submodule contains two independent SCI systems Each is a full duplex universal asynchronous receiver transmitter UART This SCI system is fully compatible with SCI systems found on other Motorola devices such as the M68HC11 and M68HC05 families The SCI uses a standard non return to zero NRZ transmission format An on chip baud rate generator derives standard baud rate frequencies from the MCU oscillator Both the transmitter and the receiver are double buffered so that back to back characters can be handled easily even if the CPU is delayed in responding to the completion of an individual character The SCI transmitter and receiver are functionally independent but use the same data format and baud rate Figure 11 5 shows a block diagram of the SCI transmitter Figure 11 6 shows a block diagram of the SCI receiver The two independent SCI systems are called SCIA and SCIB These SCls are identical in register set and hardware configuration providing an application with full flexibility in using the dual SCI system References to SCI registers in this section do not always distinguish between the two SCI systems A reference to SCCR1 for example ap
291. f a previous exception are processed before the first instruction of that exception s handler routine The converse is not true If an interrupt occurs during bus error excep tion processing for example the first instruction of the exception handler is executed before interrupts are sensed This permits the exception handler to mask interrupts during execution Refer to SECTION 5 SINGLE CHIP INTEGRATION MODULE 2 for detailed information concerning interrupts and system reset Refer to the CPU16 Reference Manual CPU16RM AD for information concerning processing of specific exceptions 4 13 6 RTI Instruction The return from interrupt instruction RTI must be the last instruction in all exception handlers except the RESET handler RTI pulls the exception stack frame that was pushed onto the system stack during exception processing and restores processor state Normal program flow resumes at the address of the instruction that follows the last instruction executed before exception processing began RTI is not used in the RESET handler because RESET initializes the stack pointer and does not create a stack frame 4 14 Development Support The CPU16 incorporates powerful tools for tracking program execution and for system debugging These tools are deterministic opcode tracking breakpoint exceptions and background debug mode Judicious use of CPU16 capabilities permits in circuit emu lation and system debugging using a bus state analyzer
292. f eight and sixteen bits are accessed through the use of asynchronous cycles controlled by the size SIZ1 and SIZO and data size acknowledge DSACK1 and DSACKO pins Multiple bus cycles may be required for a dynamically sized transfers To add flexibility and minimize the necessity for external logic MCU chip select logic is synchronized with EBI transfers Refer to 5 9 Chip Selects for more information 5 5 1 Bus Control Signals The address bus provides addressing information to external devices The data bus transfers 8 bit and 16 bit data between the MCU and external devices Strobe signals one for the address bus and another for the data bus indicate the validity of an address and provide timing information for data Control signals indicate the beginning of each bus cycle the address space the size of the transfer and the type of cycle External devices decode these signals and respond to transfer data and terminate the bus cycle The EBI can operate in an asynchronous mode for any port width 5 5 1 1 Address Bus Bus signals ADDR 19 0 define the address of the byte or the most significant byte to be transferred during a bus cycle The MCU places the address on the bus at the beginning of a bus cycle The address is valid while AS is asserted 5 5 1 2 Address Strobe Address strobe AS is a timing signal that indicates the validity of an address on the address bus and of many control signals 5 5 1 3 Data Bus Signals D
293. f the SCSR causes all 16 bits to be accessed and any status bit already set in either byte will be cleared on a subsequent read or write of the SCDR 11 4 1 3 SCI Data Register The SCDR contains two data registers at the same address The RDR is a read only register that contains data received by the SCI serial interface The data comes into the receive serial shifter and is transferred to the RDR The TDR is a write only register that contains data to be transmitted The data is first written to the TDR then trans ferred to the transmit serial shifter where additional format bits are added before trans mission 11 4 2 SCI Pins Four pins are associated with the SCI TXDA TXDB RXDA and RXDB The state of the TE or RE bit in SCI control register 1 of each SCI submodule SCCR1A SCCR1B determines whether the associated pin is configured for SCI operation or general pur pose I O The MDDR assigns each as either input or output The WOMC bit in SCCR1A or SCCR1B determines whether the associated RXD and TXD pins when configured as outputs function as open drain output pins or normal CMOS outputs MDDR and WOMC assignments are valid regardless of whether the pins are con figured for SPI use or general purpose SCI pins are listed in Table 11 5 MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor
294. fApc rate Reduced conversion accuracy occurs at maximum MOTOROLA MC68HC16R1 916R1 A 26 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 13 ADC Conversion Characteristics Operating Voo and Vona 5 0 5 Vss 0 Vde T to Ty 0 5 MHz lt fapcik lt 1 0 MHz 2 clock input sample time Num Parameter Symbol Min Typical Max Unit 1 8 bit Resolution 1 Count 20 mV 2 8 bit Differential Nonlinearity DNL 0 5 0 5 Counts 3 8 bit Integral Nonlinearity INL 1 1 Counts 4 8 bit Absolute Error AE 1 1 Counts 5 10 bit Resolution 1 Count 5 mV 6 10 bit Differential Nonlinearity DNL 0 5 0 5 Counts 7 10 bit Integral Nonlinearity INL 2 0 2 0 Counts 8 10 bit Absolute Error AE 2 5 2 5 Counts 9 Impedance at Input Rs 20 kQ NOTES 1 At Vay 5 12 V one 10 bit count 5 mV and 8 bit count 20 mV 2 8 bit absolute error of 1 count 20 mV includes 1 2 count 10 mV inherent quantization error and 1 2 count 10 mV circuit differential integral and offset error 3 Conversion accuracy varies with fApc rate Reduced conversion accuracy occurs at maximum fApc AS sumes that minimum sample time 2 ADC Clocks is selected 4 10 bit absolute error of 2 5 counts 12 5 mV includes 1 2 count 2 5 mV inher
295. fferent operational modes Table 12 2 SASM Operational Modes Mode Function Input capture either a rising or falling edge or as a read only input port OC Output compare OCT Output compare and toggle OP Output port NOTES 1 When a channel is operating in IC mode the IN bit in the SIC register reflects the logic state of the corresponding input pin after being Schmitt triggered and synchronized 2 When a channel is operating in OC OCT or OP mode the IN bit in the SIC register reflects the logic state of the output of the output flip flop NOTE All of the functions associated with one pin are caled a SASM channel MOTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 10 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The SASM can perform a single timing action input capture or output compare before software intervention is required Each channel includes a 16 bit comparator and one 16 bit register for saving an input capture value or for holding an output compare val ue The input edge detector associated with each pin is programmable to cause the capture function to occur on the rising or falling edge The output flip flop can be set to either toggle when an output compare occurs or to transfer a software provided bit val ue to the output pin In either input capture or output compare mode each channel can be programmed to gen
296. flop is connected to a buffer that drives the PWMSM s associated output pin PWMSM is disabled by clearing the EN bit in the PWMSM status interrupt control register PWMSIC When the PWMSM is not in use the output pin can be used as a digital output controlled by the POL bit in PWMSIC 12 10 2 Clock Selection The PWMSM contains an 8 bit prescaler that is clocked by the PCLK1 signal fsys 2 fsys 3 from the CPSM The CLK 2 0 field in PWMSIC selects which of the eight prescaler outputs drives the PWMSM counter Refer to Table 12 5 for the prescaler output MC68HC16R1 916R1 CONFIGURABLE TIMER MODULE 7 MOTOROLA USER S MANUAL For More Information On This Product 12 15 Go to www freescale com Freescale Semiconductor Inc Table 12 5 PWMSM Divide By Options CLK2 CLK1 CLKO 820 0 open 0 0 0 0 faye 92 fsys 3 0 0 1 fjs 4 fsys 6 0 1 0 fsys 8 fsys 12 0 1 1 fsys 16 fsys 24 1 0 0 fsys 32 fsys 48 1 0 1 fsys 64 fsys 96 1 1 0 fsys 128 fsys 192 1 1 1 fsys 512 fsys 768 12 10 3 PWMSM Counter The 16 bit up counter in the PWMSM provides the time base for the PWM output sig nal The counter is held in the 0001 state after reset or when the PWMSM is disabled When the PWMSM is enabled the counter begins counting at the rate selected by CLK 2 0 in PWMSIC Each time the counter matches the contents of the period reg ister the counter is
297. formation Bus cycles terminated by DSACK assertion normally require a minimum of three CLK OUT cycles To support systems that use CLKOUT to generate DSACK and other in puts asynchronous input setup time and asynchronous input hold times are specified When these specifications are met the MCU is guaranteed to recognize the appropri ate signal on a specific edge of the CLKOUT signal 5 6 2 Regular Bus Cycle The following paragraphs contain a discussion of cycles that use external bus control logic Refer to 5 6 3 Fast Termination Cycles for information about fast termination cycles To initiate a transfer the MCU asserts an address and the SIZ 1 0 signals The SIZ signals and ADDRO are externally decoded to select the active portion of the data bus Refer to 5 5 2 Dynamic Bus Sizing When AS DS and R W are valid a peripheral device either places data on the bus read cycle or latches data from the bus write cycle then asserts a DSACK 1 0 combination that indicates port size The DSACK 1 0 signals be asserted before the data from a peripheral device is valid on a read cycle To ensure valid data is latched into the MCU a maximum period between DSACK assertion and DS assertion is specified There is no specified maximum for the period between the assertion of AS and DSACK Although the MCU can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK the MCU inserts wait cycles in clo
298. formation There are no differences in flow for chip selects in each type of space but base and option registers must be properly programmed for each type of external bus cycle During a CPU space cycle bits 15 3 of the appropriate base register must be config ured to match ADDR 23 11 as the address is compared to an address generated by the CPU ADDR 23 20 follow the state of ADDR19 in this MCU The states of base register bits 15 12 must match that of bit 11 Figure 5 22 shows CPU space encoding for an interrupt acknowledge cycle FC 2 0 are set to 96111 designating CPU space access ADDR 3 1 indicate interrupt priority and the space type field ADDR 19 16 is set to 961111 the interrupt acknowledge code The rest of the address lines are set to one MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 67 Go to www freescale com Freescale Semiconductor Inc FUNCTION ADDRESS BUS CODE 19 16 2 0 2 0 VOWLEDGE Kepowleboe 111 1 1111 11111111111 es CPU SPACE TYPE FIELD CPU SPACE IACK TIM Figure 5 22 CPU Space Encoding for Interrupt Acknowledge Because address match logic functions only after the EBI transfers an interrupt acknowledge cycle to the external address bus following IARB contention chip select logic generates AVEC or DSACK signals only in response to interrupt requests from external IRQ pins If an internal module makes an in
299. ge level At time t 0 51 in Figure 10 10 closes S2 is open disconnecting the internal circuitry from the external circuitry Assume that the initial voltage across CF is 0 As CF charges the voltage across it is determined by the following equation where t is the total charge time Vor Vgnc 1 e When t 0 the voltage across Cr 0 As t approaches infinity Vor will equal Vsnc This assumes no internal leakage With 10 bit resolution 1 2 of a count is equal to 1 2048 full scale value Assuming worst case full scale Table 10 10 shows the required time for Cp to charge to within 1 2 of a count of the actual source voltage during 10 bit conversions Table 10 10 is based on the RC network in Figure 10 10 NOTE The following times are completely independent of the A D converter architecture assuming the ADC is not affecting the charging MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For More Information On This Product 10 23 Go to www freescale com Freescale Semiconductor Inc Table 10 10 External Circuit Settling Time 10 Bit Conversions Filter Capacitor Source Resistance 1000 1 10 100 1 uF 760 us 7 6 ms 76 ms 760 ms The external circuit described in Table 10 10 is a low pass filter A user interested in measuring an AC component of the external signal must take the characteristics of this filter into account
300. generated when SPIF is asserted After the SPSR is read with SPIF set and then the SPDR is read or written to the SPIF flag is automatically cleared MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL For More Information On This Product 11 7 Go to www freescale com Freescale Semiconductor Inc Data transfer is synchronized with the internally generated serial clock SCK Control bits CPHA and CPOL in SPCR control clock phase and polarity Combinations of CPHA and CPOL determine the SCK edge on which the master MCU drives outgoing data from the MOSI pin and latches incoming data from the MISO pin 11 3 3 2 Slave Mode Clearing the MSTR bit in SPCR selects slave mode operation In slave mode the SPI is unable to initiate serial transfers Transfers are initiated by an external bus master Slave mode is typically used on a multimaster bus Only one device can be bus master operate in master mode at any given time When using the SPI in slave mode include the following steps 1 Write to the MMCR and interrupt registers Refer to 11 5 MCCI Initialization for more information 2 Write to the MPAR to assign the following pins to the SPI MISO MOSI and SS MISO is used for serial data output in slave mode and MOSI is used for serial data input Either or both may be necessary depending on the particular application SCK is the input serial clock SS selects the SPI when asserted 3 Write to t
301. gisters 2 12 pulled 4 1 5 E 6 D 7 Reserved PULMAC Pull MAC State Stack MAC Registers INH 27B9 16 RMAC Repeating Repeat until E 0 IMM8 FB xoyo 6 12 A A Multiply and AM H I per Accumulate Qualified IX iteration Signed 16 Bit Qualified IY Fractions M M 1 x 1 gt l E 12E Until E 0000 ROL Rotate Left IND8 X 0c ff 8 A A A IND8 Y 1 ff 8 u IND8 Z 2 8 IND16 X 170C 9999 8 IND16 Y 171C 9999 8 IND16 Z 172C 9999 8 173 hh Il 8 ROLA Rotate Left A INH 370C 2 A AAA ed d b7 bo ROLB Rotate Left B INH 371C 2 Teo oeque A Loe d b7 bo ROLD Rotate Left D INH 27FC 2 A A Se TI 5 bo ROLE Rotate Left E INH 277C 2 o A A SA A SM TI 5 bo ROLW Rotate Left Word IND16 X 270 9999 8 AAA IND16 Y 271C 9999 8 M IND16 Z 272C 9999 8 EXT 273C hh Il 8 ROR Rotate Right Byte IND8 X ff 8 A A IND8 1E ff 8 FLT iT he IND8 Z 2E ff 8 IND16 X 170E 9999 8 IND16 171 9999 8 IND16 Z 172E 999g 8 EXT 173E hh 8 RORA Rotate Right A NH 370E 2 A A bj 07 00 RORB Rotate Right B NH 371E 2 SS ee A ITIIIIILPEF 07 b0 RORD Rotate Right D NH 27FE 2 AAA D LL PeH b15 b0 RORE Rotate Right E NH 277E 2 A AAA D
302. gisters and extension fields provide 20 bit indexed addressing and support data structure functions anywhere in the CPU16 address space IX and can perform the same operations as M68HC11 registers of the same names but the CPU16 instruction set provides additional indexed operations IZ can perform the same operations as and IY IZ also provides an additional in dexed addressing capability that replaces M68HC11 direct addressing mode Initial IZ and ZK extension field values are included in the RESET exception vector so that ZK IZ can be used as a direct page pointer out of reset 4 2 3 Stack Pointer The CPU16 stack pointer SP is 16 bits wide An associated 4 bit extension field SK provides 20 bit stack addressing Stack implementation in the CPU16 is from high to low memory The stack grows downward as it is filled SK SP are decremented each time data is pushed on the stack and incremented each time data is pulled from the stack SK SP point to the next available stack address rather than to the address of the latest stack entry Although the stack pointer is normally incremented or decremented by word address it is possible to push and pull byte sized data Setting the stack pointer to an odd value causes data misalignment which reduces performance 4 2 4 Program Counter The CPU16 program counter PC is 16 bits wide An associated 4 bit extension field PK provides 20 bit program addressing CPU16 instructions ar
303. gnment Register D 44 D 6 7 MCCI Data Direction Register D 45 MC68HC16R1 916R1 MOTOROLA USER S MANUAL xii For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title D 6 8 MCCI Port Data Registers D 6 9 SCI Control Register 0 4222212 D 6 11 SCI Status Register D 6 12 SCI Data Register D 6 13 SPI Control Register D 6 14 SPI Status REGISTE t coe tener eoe reda D 6 15 SPI Data Register D 7 Configurable Timer Module 7 D 7 1 BIU Module Configuration Register D 7 2 BIUSM Test Configuration Register D 7 3 BIUSM Time Base Register D 7 4 CPSM Control Register D 7 5 CPSM Test Register D 7 6 MCSM Status Interrupt Control Registers D 7 7 MCSM Counter Registers
304. gure 5 10 OP 0 3 represent the order of access For instance OPO is the most significant byte of a long word operand and is accessed first while OP3 the least significant byte is accessed last The two bytes of a word length operand are OPO most significant and OP1 The single byte of a byte length operand is OPO OPERAND BYTE ORDER 31 24 23 1615 87 0 LONG WORD OPO OP1 OP2 OP3 THREE BYTE 0 0 0 1 0 2 WORD 0 0 0 1 0 0 OPERAND BYTE ORDER Figure 5 10 Operand Byte Order MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 27 to www freescale com Freescale Semiconductor Inc 5 5 3 Operand Alignment The EBI data multiplexer establishes the necessary connections for different combi nations of address and data sizes The multiplexer takes the two bytes of the 16 bit bus and routes them to their required positions Positioning of bytes is determined by the size and address outputs SIZ1 and SIZO indicate the number of bytes remaining to be transferred during the current bus cycle The number of bytes transferred is equal to or less than the size indicated by SIZ1 and SIZO depending on port width ADDRO also affects the operation of the data multiplexer During a bus transfer AD DR 23 1 indicate the word base address of the portion of the operand to be accessed and ADDRO indicates the byte offset from the base NOTE ADDR 23 20
305. hat allows external emulation of internal ROM This emulation support feature enables the development of a single chip appli cation in expanded mode NOTE The masked ROM is available only on the MC68HC16R1 MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 50 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Emulator mode is a special type of 16 bit expanded operation It is entered by holding DATA10 low BERR high and DATA1 low during reset In emulator mode all port A B E G and H data and data direction registers and the port E pin assignment register are mapped externally Port C data port F data and data direction registers and port F pin assignment register are accessible normally in emulator mode An emulator chip select CSE is asserted whenever any of the externally mapped registers are addressed The signal is asserted on the falling edge of AS The SCIM2 does not respond to these accesses allowing external logic such as a port replace ment unit PRU to respond Accesses to externally mapped registers require three clock cycles External ROM emulation is enabled by holding DATA1 DATA10 and DATA13 low during reset BERR must be held high during reset to enable the ROM module While ROM emulation mode is enabled memory chip select signal CSM is asserted when ever a valid access to an address assigned to the masked ROM array is made The
306. he modulus latch and the counter register immediately with the new value The modulus latch register is cleared to 0000 by reset 12 7 2 MCSM Counter The counter is composed of a 16 bit read write register associated with a 16 bit incrementer Reading the counter transfers the contents of the counter register to the data bus Writing to the counter loads the modulus latch and the counter register immediately with the new value MOTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 12 7 2 1 Loading the MCSM Counter Register The MCSM counter is loaded either by writing to the counter register or by loading it from the modulus latch when a counter overflow occurs Counter overflow will set the COF bit in the MCSM status interrupt control register MCSMSIC NOTE When the modulus latch is loaded with FFFF the overflow flag is set on every counter clock pulse 12 7 2 2 Using the MCSM as a Free Running Counter Although the MCSM is a modulus counter it can operate like a free running counter by loading the modulus register with 0000 12 7 3 MCSM Clock Sources The MCSM has eight software selectable counter clock sources including e Six CPSM prescaler outputs PCLK 1 6 Rising edge on the CTM2C input Falling edge on the CTM2C input The clock source is selected by the CLK 2 0 bits in MCSMSIC When the CLK
307. he CTM Reference Manual CTMRM AD for a comprehensive discussion of CTM capabilities 12 1 General The configurable timer module 7 CTM7 consists of several submodules which are lo cated on either side of the CTM7 internal submodule bus SMB All data and control signals within the CTM7 are passed over this bus The SMB is connected to the out side world via the bus interface unit submodule BIUSM which is connected to the intermodule bus IMB and subsequently the CPU16 This configuration allows the CPU16 to access the data and control registers in each CTM7 submodule on the SMB Two time base buses TBB1 and TBB2 each 16 bits wide are used to transfer timing information from counters to action submodules Figure 12 1 shows a block diagram of the CTM7 PULSE WIDTH MODULATION SUBMODULE PWMSM19 CPWMI9 PCLKL fs 2 OF fys 3 PULSE WIDTH MODULATION SUBMODULE PWMSM18 18 EXTERNAL CLOCK CTM2C TIME BASE BUS 1 TBB1 EAS MEI CTD16B SINGLE ACTION gt SUBMODULE SASM16A CTD16A SINGLE ACTION j SUBMODULE SASM148 CTD148 SINGLE ACTION gt SUBMODULE SASM14A CTD14A SINGLE ACTION SUBMODULE SASM12B CTD128 SINGLE ACTION MODULUS COUNTER gt i CTD12A SUBMODULE 5 2 SUBMODULE SASMTAN cD x 54 42 SINGLE ACTION E b gt SUBMODULE SASM10B GTD1OB Epi FREE RUNNING SINGLE ACTION COUNTER SUBMODULE SASM10A CTD10A
308. he MDDR to direct the data flow on SPI pins Configure the SCK MOSI and SS pins as inputs Configure MISO as an output 4 Write to the SPCR to assign values for CPHA CPOL SIZE LSBF WOMP and SPIE Set the MSTR bit to select master operation Set the SPE bit to enable the SPI The BAUD field in the SPCR of the slave device has no effect on SPI operation When SPE is set and MSTR is clear a low state on the SS pin initiates slave mode operation The SS pin is used only as an input After a byte or word of data is transmitted the SPI sets the SPIF flag If the SPIE bit in SPCR is set an interrupt request is generated when SPIF is asserted Transfer is synchronized with the externally generated SCK The CPHA and CPOL bits determine the SCK edge on which the slave MCU latches incoming data from the MOSI pin and drives outgoing data from the MISO pin 11 3 4 SPI Clock Phase and Polarity Controls Two bits in the SPCR determine SCK phase and polarity The clock polarity CPOL bit selects clock polarity high true or low true clock The clock phase control bit CPHA selects one of two transfer formats and affects the timing of the transfer The clock phase and polarity should be the same for the master and slave devices In some cases the phase and polarity may be changed between transfers to allow a master device to communicate with slave devices with different requirements The flexibility of the SPI system allows it to be directly inte
309. he WAKE bit in SCCR1 determines which type of wake up is used When WAKE 0 idle line wake up is selected When WAKE 1 address mark wake up is selected Both types require a software based device addressing and recognition scheme Idle line wake up allows a receiver to sleep until an idle line is detected When an idle line is detected the receiver clears RWU and wakes up The receiver waits for the first frame of the next transmission The byte is received normally transferred to the RDR and the RDRF flag is set If software does not recognize the address it can set RWU and put the receiver back to sleep For idle line wake up to work there must be a min imum of one frame of idle line between transmissions There must be no idle time be tween frames within a transmission Address mark wake up uses a special frame format to wake up the receiver When the MSB of an address mark frame is set that frame contains address information The first frame of each transmission must be an address frame When the MSB of a frame is set the receiver clears RWU and wakes up The byte is received normally trans ferred to the RDR and the RDRF flag is set If software does not recognize the ad dress it can set RWU and put the receiver back to sleep Address mark wake up allows idle time between frames and eliminates idle time between transmissions How ever there is a loss of efficiency because of an additional bit time per frame 11 4 5 9 Internal
310. he address of the appropriate exception vector in the exception vector table The reset value of the PIV field is 0F which corresponds to the uninitialized interrupt exception vector 5 4 8 Low Power STOP Operation When the CPU16 executes the LPSTOP instruction the current interrupt priority mask is stored in the clock control logic internal clocks are disabled according to the state of the STSCIM bit in the SYNCR and the MCU enters low power stop mode The bus monitor halt monitor and spurious interrupt monitor are all inactive during low power stop During low power stop mode the clock input to the software watchdog timer is dis abled and the timer stops The software watchdog begins to run again on the first rising clock edge after low power stop mode ends The watchdog is not reset by low power stop mode A service sequence must be performed to reset the timer MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 21 Go to www freescale com Freescale Semiconductor Inc The periodic interrupt timer does not respond to the LPSTOP instruction but continues to run during LPSTOP To stop the periodic interrupt timer PITR must be loaded with a zero value before the LPSTOP instruction is executed A PIT interrupt or an external interrupt request can bring the MCU out of the low power stop mode if it has a higher priority than the interrupt mask value stored in the clock
311. he associated shadow register Certain registers can be written only when LOCK 0 or STOP 1 in FEEXMCR 8 2 Flash EEPROM Array The base address registers specify the starting address of the flash EEPROM array The user programs the reset base address The base address of the 16 Kbyte array must be on a 16 Kbyte boundary the base address of the 32 Kbyte array must be on a 32 Kbyte boundary Behavior will be indeterminate if one flash EEPROM array over laps the other The base address must also be set so that an array does not overlap a flash EEPROM control block in the data space memory map If an array does overlap a control block accesses to the 32 bytes in the array that is overlapped are ignored allowing the flash EEPROM control blocks to remain accessible If the array overlaps the control block of another module the results will be indeterminate 8 3 Flash EEPROM Operation The following paragraphs describe the operation of the flash EEPROM module during reset system boot normal operation and while it is being programmed or erased 8 3 1 Reset Operation Reset initializes all registers to certain default values Some of these reset values are programmable by the user and are contained in flash EEPROM shadow registers If the state of the STOP shadow bit is zero and bus pin DATA14 is pulled high during reset the STOP bit in the FEExMCR is cleared during reset The array responds normally to the bootstrap address range and th
312. he corresponding pin as an input This register can be read or written at any time Bits 15 8 are unimplemented and will always read zero MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 12 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 2 14 Port F Pin Assignment Register PFPAR Port F Pin Assignment Register YFFA1F 15 8 7 6 5 4 3 2 1 0 NOT USED PFPA7 PFPA6 5 PFPA4 PFPA3 PFPA2 1 PFPAO RESET 8 AND 16 BIT EXPANDED MODES DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 9 SINGLE CHIP MODE 0 0 0 0 0 0 0 0 This register determines the function of port F pins Setting a bit assigns the corresponding pin to a control signal clearing a bit assigns the pin to port F Bits 15 8 are unimplemented and will always read zero Refer to Table D 5 Table D 5 Port F Pin Assignments PFPAR Field Port F Signal Alternate Signal PFPA7 PF7 IRQ7 PFPA6 PF6 IRQ6 PFPA5 PF5 IRQ5 PFPA4 PF4 IRQ4 PFPA3 PF3 IRQ3 PFPA2 PF2 IRQ2 PFPA1 PF1 IRQ1 PFPA0 PF0 FASTREF D 2 15 System Protection Control Register SYPCR System Protection Control Register YFFA20 15 8 7 6 5 4 3 2 1 0 NOT USED SWE SWP SWT 1 0 HME BME BMT 1 0 RESET 1 MODCLK 0 0 0 0 0 0 This register controls system monitor functions software watchdog clock prescaling and bus moni
313. hh Il 6 278 6 279 6 2 27 6 STE Store E 1 IND16 374A 999g 6 A A 0 IND16 Y 375A gggg 6 IND16 Z 376A gggg 6 EXT 377A hh Il 6 STED Store Concatenated gt 1 2773 hh Il 8 DandE 0 gt M 2 M 3 STS Store Stack Pointer SP 1 IND8 8F ff 4 A A 0 IND8 Y 9F ff 4 IND8 Z AF ff 4 IND16 X 178F 999g 6 IND16 Y 179F 9999 6 IND16 2 17AF 0099 6 17 hh Il 6 STX Store IX IX gt M M 1 IND8 X 8C ff 4 A 0 IND8 Y 9C ff 4 IND8 Z AC ff 4 IND16 X 178C gggg 6 IND16 Y 179C 0999 6 IND16 2 17 9999 6 17BC hh Il 6 STY Store IY IY gt M M 1 IND8 X 8D ff 4 0 IND8 Y 9D ff 4 IND8 Z AD ff 4 IND16 X 178D gggg 6 IND16 Y 179D gggg 6 IND16 Z 17AD gggg 6 EXT 17BD hh Il 6 STZ Store Z IZ M M 1 IND8 X 8E ff 4 A 0 IND8 Y 9E ff 4 IND8 Z AE ff 4 IND16 X 178E gggg 6 IND16 Y 179E gggg 6 IND16 Z 17AE 9999 6 17 hh Il 6 SUBA Subtract from A A gt A IND8 X 40 ff 6 A AAA IND8 Y 50 ff 6 IND8 Z 60 ff 6 IMM8 70 ii 2 IND16 X 1740 999g 6 IND16 Y 1750 9999 6 IND16 2 1760 0099 6 1770 hh Il 6 2740 6 E Y 2750 6 E Z 2760 6 MOTOROLA MC68HC16R1 916R1 4 26 USER S MANUAL For More Information On This Product Go to www freescale com Table 4 2 Instruction Set Summary Continued Freescale
314. hip Integration Module Test Register YFFA02 Used for factory test only MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 7 Go to www freescale com Freescale Semiconductor Inc D 2 3 Clock Synthesizer Control Register SYNCR Clock Synthesizer Control Register YFFA04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RE W X 5 0 EDIV 0 0 SERVED 1 SLOCK STSCIM STEXT RE SERVED RESET 0 0 1 1 1 1 1 1 0 0 0 0 U 0 0 0 NOTES 1 Ensure that initialization software does not change the value of these bits They should always be 0 This register determines system clock operating frequency and operation during low power stop mode With a slow reference frequency between 25 and 50 kHz typically a 32 768 kHz crystal the clock frequency is determined by the following equation ate X fsys fretl4 Y 1 With a fast reference frequency between 1 and 6 MHz typically a 4 194 MHz crystal the reference frequency is divided by 128 before it is passed to the PLL system The clock frequency is determined by the following equation f fos y Teer sys 128 W Frequency Control VCO This bit controls a prescaler tap in the synthesizer feedback loop Setting this bit increases the VCO speed by a factor of four VCO relock delay is required X Frequency Control Prescaler This bit controls a divide by two prescaler
315. how pin function and direction are assigned Table 11 2 Pin Assignments Pin Function Assigned By Direction Assigned By TXDA PMC7 TE bit in SCCROA MMDR7 RXDA PMC6 RE bit in SCCROA MMDR6 TXDB PMC5 TE bit in SCCROB MMDR5 RXDB PMC4 RE bit in SCCROB MMDR4 SS PMC3 SS bit in MPAR MMDR3 5 2 SPE bit in SPCR MMDR2 MOSI PMC1 MOSI bit in MPAR MMDR1 MISO PMCO MISO bit in MPAR MMDRO 11 3 Serial Peripheral Interface SPI The SPI submodule communicates with external peripherals and other MCUs via a synchronous serial bus The SPI is fully compatible with the serial peripheral interface systems found on other Motorola devices such as the M68HC11 and M68HCO05 families The SPI can perform full duplex three wire or half duplex two wire transfers Serial transfer of 8 or 16 bits can begin with the MSB or LSB The system can be con figured as a master or slave device Figure 11 2 shows a block diagram of the SPI MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc INTERNAL MCU CLOCK MSB LSB 8 16 SHIFT REGISTER e CLOCK 5 2 CD CE SPI CLOCK MASTER sauer CLOCK LOGIC BAUD MSTR SPE WOMP SPI CONTROL SPIF WCOL MODF CPOL LSBF SIZE BAUD SPI ST
316. igh Impedance tcLDH 90 ns 31 DSACK 1 0 Asserted to Data In Valid 50 ns 33 Clock Low to BG Asserted Negated tCLBAN 29 ns 35 BR Asserted to BG Asserted tBRAGA 1 toyo 37 Asserted to Negated tGAGN 1 2 loyc 39 BG Width Negated tau 2 loyc 39A BG Width Asserted ton 1 loyc 46 R W Width Asserted Write or Read tRWA 150 ns 46A R W Width Asserted Fast Write or Read Cycle trwas 90 ns 47A Asynchronous Input Setup Time igs 5 h BR BGACK DSACK 1 0 BERR AVEC HALT 47B Asynchronous Input Hold Time tAIHT 15 ns 48 DSACK 1 0 Asserted to BERR HALT Asserted tpABA 30 ns 53 Data Out Hold from Clock High tpocH 0 ns 54 Clock High to Data Out High Impedance tcHDH 28 ns 55 R W Asserted to Data Bus Impedance Change tRADC 40 ns 70 Clock Low to Data Bus Driven Show Cycle tecLDD 0 19 ns 71 Data Setup Time to Clock Low Show Cycle teci ps 15 ns 72 Data Hold from Clock Low Show Cycle teci pH 10 ns 73 BKPT Input Setup Time iBksT 15 ns 74 BKPT Input Hold Time tBKHT 10 ns 75 Mode Select Setup Time DATA 15 0 MODCLK BKPT 20 loyc 76 Mode Select Hold Time DATA 15 0 MODCLK 0 ns 77 RESET Assertion 2 tRSTa 4 78 RESET Rise Time tRSTR 10 ios 100 CLKOUT High to Phase 1 Asserted tCHP1A 3 40 ns 101 CLKOUT High to Phase 2 Asserted 2 3 40 ns 102 Phase 1 Valid to AS or DS Asserted
317. in drivers when pins are configured for I O Setting bit configures the corresponding pin as an output clearing a bit configures the corresponding pin as an input This register can be read or written at any time The port A B data direction register controls the direction of the pin drivers for ports A and B respectively when the pins are configured for I O Setting DDA or DDB to one configures all pins in the corresponding port as outputs Clearing DDA or DDB to zero configures all pins in the corresponding port as inputs Bits 15 10 are unimplemented and will always read zero D 2 11 Port E Pin Assignment Register PEPAR Port E Pin Assignment YFFA17 15 8 7 6 5 4 3 2 1 0 NOT USED 7 PEPA6 5 PEPA4 PEPA3 2 1 PEPAO RESET DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 This register determines the function of port E pins Setting a bit assigns the corre sponding pin to a bus control signal clearing a bit assigns the pin to I O port E is not connected to a pin PEPA3 can be read and written but has no function Bits 15 8 are unimplemented and will always read zero Table D 4 displays port E pin assignments MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 11 Go to www freescale com Freescale Semiconductor Inc Table D 4 Port E Pin Assignments PEPAR Bit Port
318. inal sample time is determined by the STS 1 0 field Refer to Table D 25 Table D 25 Sample Time Selection STS 1 0 Sample Time 00 2 ADC Clock Periods 01 4 ADC Clock Periods 10 8 ADC Clock Periods 11 16 ADC Clock Periods PRS 4 0 Prescaler Rate Selection The ADC clock is derived from the system clock by a programmable prescaler ADC clock period is determined by the value of the PRS field in ADCTLO The prescaler has two stages The first stage is a 5 bit modulus counter It divides the system clock by any value from 2 to 32 PRS 4 0 9600000 to 9611111 The second stage is a divide by two circuit Refer to Table D 26 MOTOROLA MC68HC16R1 916R1 D 34 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table D 26 Prescaler Output Minimum Maximum PRS 4 0 ADC Clock System Clock System Clock 9600000 Reserved 9600001 System Clock 4 2 0 MHz 8 4 MHz 9600010 System Clock 6 3 0 MHz 12 6 MHz 960001 1 System Clock 8 4 0 MHz 16 8 MHz 9611101 System Clock 60 30 0 MHz 2611110 System Clock 62 31 0 MHz 9611111 System Clock 64 32 0 MHz D 5 5 Control Register 1 ADCTL1 Control Register 1 YFF70C 15 7 6 5 4 3 2 1 0 NOT USED SCAN MULT S8CM CD cc CB CA RESET 0 0 0 0 0 0 0 ADCTL1 is used to initiate an A D conversion and to select conversion modes and a
319. indicator Two s complement overflow indicator Carry borrow indicator Interrupt priority field Saturation mode control bit Program counter extension field Bit not affected Bit changes as specified Bit cleared Bit set Memory location used in operation Result of operation Source data Addition Subtraction or negation two s complement Multiplication Division Greater Less Equal Equal or greater Equal less Not equal For More Information On This Product x M M 1 M M 1 X Z E X E Y E Z EXT EXT20 IMM8 IMM16 IND8 X IND8 Y IND8 Z IND16 X IND16 Y IND16 Z IND20 X IND20 Y IND20 Z INH IXP REL8 REL16 b ff 9999 Register used in operation Address of one memory byte Address of byte at M 0001 Address of one memory word Contents of address pointed to by IX Contents of address pointed to by IY Contents of address pointed to by IZ IX with E offset IY with E offset IZ with E offset Extended 20 bit extended 8 bit immediate 16 bit immediate IX with unsigned 8 bit offset IY with unsigned 8 bit offset IZ with unsigned 8 bit offset IX with signed 16 bit offset IY with signed 16 bit offset IZ with signed 16 bit offset IX with signed 20 bit offset IY with signed 20 bit offset IZ with signed 20 bit offset Inherent Post modified indexed 8 bit relative
320. input to SPI 1 Disables data input Slave 0 Disables data output 1 Serial data output from SPI MOSI Master DDR1 0 Disables data output 1 Serial data output from SPI Slave 0 Serial data input to SPI 1 Disables data input SCK Master DDR2 Clock output from SPI Slave Clock input to SPI SS Master DDR3 0 Assertion causes mode fault 1 General purpose I O Slave 0 SPI slave select input 1 Disables slave select input RXDBE DDR4 0 General purpose I O 1 Serial data input to SCIB TXDB DDR5 0 General purpose I O 1 Serial data output from SCIB RXDA DDR6 0 General purpose I O 1 Serial data input to SCIA TXDA3 DDR7 0 General purpose I O 1 Serial data output from SCIA NOTES 1 SCK is automatically assigned to the SPI whenever the SPI is enabled when the SPE bit in the SPCR1 is set 2 PMC4 and PMC6 function as general purpose pins when the corresponding RE bit in the SCI control register SCCROA or SCCROB is cleared 3 PMC5 and PMC7 function as general purpose I O pins when the corresponding TE bit in the SCI control register SCCROA or SCCROB is cleared MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product D 45 Go to www freescale com Freescale Semiconductor Inc D 6 8 MCCI Port Data Registers PORTMC Port Data Register YFFCOC PORTMCP MCCI Port Pin State Register YFFCOE 15 9 8 7 6 5 4 3 2 1 0 NOT
321. interrupt request pins can be configured as general purpose l O ports MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 1 Go to www freescale com Freescale Semiconductor Inc e Single chip mode in which the SCIM2 provides seven general purpose I O ports no external address or data buses one general purpose chip select line and a boot ROM chip select line Although the full IMB supports 24 address and 16 data lines MC68HC16R1 916 MCUS use only 20 address lines Because the CPU16 uses only 20 address lines ADDR 23 20 follow the state of ADDR19 Operating mode is determined by the logic states of specific MCU pins during reset Refer to 5 7 3 Operating Configuration Out of Reset for more detailed information SYSTEM CONFIGURATION XTAL CLKOUT CLOCK SYNTHESIZER EXTAL MODCLK SYSTEM PROTECTION CHIP SELECTS CHIP SELECTS EXTERNAL BUS EXTERNAL BUS INTERFACE FACTORY TEST FREEZE QUOT S C IM BLOCK Figure 5 1 SCIM2 Block Diagram 5 2 System Configuration The MCU can operate as a stand alone device single chip mode with a 20 bit external address bus and an 8 bit external data bus or with a 20 bit external address bus and a 16 bit external data bus SCIM2 pins can be configured for use as I O ports or programmable chip select signals Refer to 5 9 Chip Selects and 5 10 General Purpose Input Output for more information System configurat
322. ion Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for clock specifications Figure 5 2 is a block diagram of the clock submodule MODCLK lt p gt SYSTEM CLOCK CONTROL A Ex CLOCK NOTES 1 128 IS PRESENT ONLY ON DEVICES WITH A FAST REFERENCE OSCILLATOR PLLBLOCK Figure 5 2 System Clock Block Diagram 5 3 1 Clock Sources The state of the clock mode MODCLK pin during reset determines the system clock source When MODCLK is held high during reset the clock synthesizer generates a clock signal from an external reference frequency The clock synthesizer control reg ister SYNCR determines operating frequency and mode of operation When MODCLK is held low during reset the clock synthesizer is disabled and an external system clock signal must be driven onto the EXTAL pin The input clock referred to as can be either a crystal an external clock source The output of the clock system is referred to as fsys Ensure that fret and fsys are within normal operating limits To generate a reference frequency using the crystal oscillator a reference crystal must be connected between the EXTAL and XTAL pins Typically a 32 768 kHz crystal is used for a slow reference but the frequency may vary between 25 kHz to 50 kHz Figure 5 3 shows a typical circuit MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Prod
323. ion On This Product 4 35 Go to www freescale com Freescale Semiconductor Inc 4 11 Execution Process Fetched opcodes are latched into stage A then advanced to stage B Opcodes are evaluated in stage B The execution unit can access operands in either stage A or stage B stage B accesses are limited to 8 bit operands When execution is complete opcodes are moved from stage B to stage C where they remain until the next instruc tion is complete A prefetch mechanism in the microsequencer reads instruction words from memory and increments the program counter When instruction execution begins the program counter points to an address six bytes after the address of the first word of the instruc tion being executed The number of machine cycles necessary to complete an execution sequence varies according to the complexity of the instruction Refer to the CPU16 Reference Manual CPU16RM AD for details 4 11 1 Changes in Program Flow When program flow changes instructions are fetched from a new address Before ex ecution can begin at the new address instructions and operands from the previous in struction stream must be removed from the pipeline If a change in flow is temporary a return address must be stored so that execution of the original instruction stream can resume after the change in flow When an instruction that causes a change in program flow executes PK PC point to the address of the first word of the instructio
324. ion is an event that preempts normal processing and can be caused by internal or external events Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an exception Each exception has an assigned vector that points to an associated handler routine These vectors are stored in the exception vector table The exception vector table consists of 256 four byte vectors and occupies 512 bytes of address space The exception vector table can be relocated in memory by changing its base address in the vector base register VBR The CPU16 uses vector numbers to calculate displacement into the table Refer to 4 13 Excep tions for more information Reset is the highest priority CPU16 exception Unlike all other exceptions a reset oc curs at the end of a bus cycle and not at an instruction boundary Handling resets in this way prevents write cycles in progress at the time the reset signal is asserted from being corrupted However any processing in progress is aborted by the reset excep tion and cannot be restarted Only essential reset tasks are performed during excep tion processing Other initialization tasks must be accomplished by the exception handler routine Refer to 5 7 9 Reset Processing Summary for details on exception processing MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 41 Go to www freescale com Freesc
325. ion is determined by setting bits in the SCIM2 configuration register and by asserting MCU pins during reset The following paragraphs describe those configuration options controlled by SCIMCR MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 2 1 Module Mapping Control registers for all the modules in the microcontroller are mapped into a 4 Kbyte block The state of the module mapping MM bit in SCIMCR determines where the control register block is located in the system memory map When MM register addresses range from 97 000 to 7FFFFF when MM 1 register addresses range from 000 to FFFFFF In MC68HC16R1 916R1 MCUs ADDR 23 20 follow the logic state of ADDR19 unless externally driven MM corresponds to IMB ADDR23 If MM is cleared the SCIM2 maps IMB modules into address space 7FF000 7FFFFF which is inaccessible to the CPU16 Modules remain inaccessible until reset occurs The reset state of MM is one but the bit can be written once Initialization software should make certain MM remains set 5 2 2 Interrupt Arbitration Each module that can request interrupts has an interrupt arbitration IARB field Arbitration between interrupt requests of the same priority is performed by serial contention between IARB field bit values Contention will take place whenever an inte
326. ion processing for bus error exceptions follows the standard exception process ing sequence Refer to 4 13 Exceptions for more information However two special cases of bus error called double bus faults can abort exception processing BERR assertion is not detected until an instruction is complete The BERR latch is cleared by the first instruction of the BERR exception handler Double bus fault occurs in two ways 1 When bus error exception processing begins and a second BERR is detected before the first instruction of the exception handler is executed 2 When one or more bus errors occur before the first instruction after a RESET exception is executed Multiple bus errors within a single instruction that can generate multiple bus cycles cause a single bus error exception after the instruction has been executed Immediately after assertion of a second BERR the MCU halts and drives the HALT line low Only a reset can restart a halted MCU However bus arbitration can still occur Refer to 5 6 6 External Bus Arbitration for more information A bus error or address error that occurs after exception processing has been completed during the execution of the exception handler routine or later does not cause a double bus fault The MCU continues to retry the same bus cycle as long as the external hardware requests it 5 6 5 3 Halt Operation When HALT is asserted while BERR is not asserted the MCU halts external bus ac tivity after
327. ip Select Registers 5 63 5 9 1 1 Chip Select Pin Assignment Registers 5 63 5 9 1 2 Chip Select Base Address Registers 5 64 5 9 1 3 Chip Select Option Registers 5 65 5 9 1 4 POR TG Data Register 5 66 5 9 2 Chip Select Operation 5 67 5 9 3 Using Chip Select Signals for Interrupt Acknowledge 5 67 5 9 4 Chip Select Reset Operation 5 69 5 10 General Purpose Input Output 2 2 5 70 5 10 1 Ponts UNL Bs mo n susu kasa a S ua kapas 5 71 5 10 2 POUL E bi ed pem netu au en yuaya go 5 71 5 10 3 POIDE D EU II I IM UM ILE as 5 72 5 10 4 5 74 5 10 5 T A RM M Ma M A E 5 74 5 11 Factory cL 5 75 SECTION 6 STANDBY RAM MODULE 6 1 SRAM Register Block iore epe kage nbd geet ee oe 6 1 6 2 SRAM Array Address Mapping usi De don ten ket 6 1 6 3 SRAM Array Address Space 6 2 6 4 Normal ACCESS aside ere n tet utes 6 2 6 5 Standby and Low Power Stop Operation 6 2 6 6 RESET TD 6 2 SECTIO
328. ipliers Continued Shaded cells represent values that exceed 16 78 MHz specifications Prescalers Modulus W X 00 W X 01 W X 10 W X 11 fuco 2 x Value fuco Value fuco 2 x Value fyco Value Y Slow Fast Slow Fast Slow Fast Slow Fast 100000 132 1 03125 264 2 0625 528 4 125 1056 8 25 100001 136 1 0625 272 2 125 544 4 25 1088 8 5 100010 140 1 09375 280 2 1875 560 4 375 1120 8 75 100011 144 1 125 288 2 25 576 4 5 1152 9 100100 148 1 15625 296 2 3125 592 4 675 1184 9 25 100101 152 1 1875 304 2 375 608 4 75 1216 9 5 100110 156 1 21875 312 2 4375 624 4 875 1248 9 75 100111 160 1 25 320 2 5 640 5 1280 10 101000 164 1 28125 328 2 5625 656 5 125 1312 10 25 101001 168 1 3125 336 2 625 672 5 25 1344 10 5 101010 172 1 34375 344 2 6875 688 5 375 1376 10 75 101011 176 1 375 352 2 75 704 5 5 1408 11 101100 180 1 40625 360 2 8125 720 5 625 1440 11 25 101101 184 1 4375 368 2 875 736 5 75 1472 11 5 101110 188 1 46875 376 2 9375 752 5 875 1504 11 75 101111 192 1 5 384 3 768 6 1536 12 110000 196 1 53125 392 3 0625 784 6 125 1568 12 25 110001 200 1 5625 400 3 125 800 6 25 1600 12 5 110010 204 1 59375 408 3 1875 816 6 375 1632 12 75 110011 208 1 625 416 3 25 832 6 5 1664 13 110100 212 1 65625 424 3 3125 848 6 625 1696 13 25 110101 216 1 6875 432 3 375 864 6 75 1728 13 5 110110 220 1 71875 440 3 4375 880 6 8
329. is Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 6 AC Timing Vip and Voss 5 0 Vdc 10 V 0 Vdc T T to Tj Num Characteristic Symbol Min Max Unit F1 Frequency of Operation f 16 78 MHz 1 Clock Period 59 6 ns 1A ECLK Period tEcyc 476 ns 1B External Clock Input Period txcyc 59 6 ns 2 3 Clock Pulse Width tew 24 ns 2A 3A ECLK Pulse Width tecw 236 ns 2B 3B External Clock Input High Low Time txcHL 29 8 ns 4 5 CLKOUT Rise and Fall Time tort 5 ns 4A 5A Rise and Fall Time All Outputs except CLKOUT 8 ns 4B 5B External Clock Input Rise and Fall Time txcrt 5 ns 6 High to ADDR FC SIZE Valid tcHav 0 29 ns 7 Clock High to ADDR Data FC SIZE High Impedance lCHAZx 0 59 ns 8 High to ADDR FC SIZE Invalid 0 ns 9 Clock Low to AS DS CS Asserted tCLSA 2 24 ns 9A AS to DS or CS Asserted Read tSTSA 15 15 ns 11 ADDR FC SIZE Valid to AS CS and DS Read Asserted tAVSA 15 ns 12 Low to AS DS CS Negated 2 29 ns 13 AS DS CS Negated to ADDR FC SIZE Invalid Address Hold tsNAI 15 ns 14 AS CS and DS Read Width Asserted tswa 100 ns 14 DS CS Width Asserted Write tswaw 45 ns 14B AS CS and DS Read Width Asserted Fast C
330. is con nected as its time base Control bits within each CTM7 submodule select connection to the appropriate time base bus MOTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The time base buses are precharge discharge type buses with wired OR capability Therefore no hardware damage occurs when more than one counter drives the same bus at the same time In the CTM7 TBB1 and 2 are global and accessible to every submodule Table 12 1 shows which time base buses are available to each CTM7 submodule Table 12 1 CTM7 Time Base Bus Allocation Global Time Base Submodule Bus Allocation Global Bus A Global Bus B MCSM2 TBB1 TBB2 FCSM3 1 2 DASM4 5 TBB1 TBB2 SASM6 8 10 12 14 16 TBB1 TBB2 Each PWMSM has an independent 16 bit counter and 8 bit prescaler clocked by the PCLK1 signal which is generated by the CPSM The PWMSMs are not connected to any of the time base buses Refer to 12 10 Pulse Width Modulation Submodule PWMSM for more information 12 4 Bus Interface Unit Submodule BIUSM The BIUSM connects the SMB to the IMB and allows the CTM7 submodules to com municate with the CPU16 The BIUSM also communicates CTM7 submodule interrupt requests to the IMB and transfers the interrupt level arbitration number and vector number to the CPU16 during the interrupt
331. is necessary for wired OR opera tion WOMS controls TXD function whether the pin is used by the SCI or as a general purpose pin Data to be transmitted is written to SCDR then transferred to the serial shifter The transmit data register empty TDRE flag in SCSR shows the status of TDR When TDRE 0 the TDR contains data that has not been transferred to the shifter Writing to SCDR again overwrites the data TDRE is set when the data in the TDR is trans ferred to the shifter Before new data can be written to the SCDR however the pro cessor must clear TDRE by writing to SCSR If new data is written to the SCDR without first clearing TDRE the data will not be transmitted The transmission complete TC flag in SCSR shows transmitter shifter state When TC 0 the shifter is busy TC is set when all shifting operations are completed TC is not automatically cleared The processor must clear it by first reading SCSR while TC is set then writing new data to SCDR MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL For More Information On This Product 11 19 Go to www freescale com Freescale Semiconductor Inc The state of the serial shifter is checked when the TE bit is set If TC 1 an idle frame is transmitted as a preamble to the following data frame If TC 0 the current opera tion continues until the final bit in the frame is sent then the preamble is transmitted The TC bit is set at the e
332. ister D 17 D 2 20 Port F Edge Detect Interrupt Vector D 17 D 2 21 Port F Edge Detect Interrupt Level D 17 D 2 22 Port C Data Register soie oo et detenti rehenes D 18 D 2 23 Chip Select Pin Assignment Registers D 18 D 2 24 Chip Select Base Address Register D 20 D 2 25 Chip Select Base Address Registers D 20 D 2 26 Chip Select Option Register D 21 D 2 27 Chip Select Option Registers D 21 D 2 28 Master Shift Registers ese eerte credet eee nie D 24 D 2 29 Test Module Shift Count Register D 24 D 2 30 Test Module Repetition Count Register D 24 D 2 31 Test Module Control Register 2 D 25 D 2 32 Test Module Distributed Register D 25 D 3 Standby FAM MOGUIG uus ctor ceti o or to See t ERE pru pera qup qs D 26 D 3 1 RAM Module Configuration Register D 26 D 3 2 HAM Test Register tei rp e te te ee D 27 D 3 3 Array Base Address Registers
333. isters The FCSM contains a status interrupt control register and a counter register All un used bits and reserved address locations return zero when read Writes to unused bits and reserved address locations have no effect Refer to D 7 9 FCSM Status Inter rupt Control Register and D 7 10 FCSM Counter Register for information concern ing FCSM register and bit descriptions 12 7 Modulus Counter Submodule MCSM The modulus counter submodule MCSM is an enhanced FCSM The MCSM con tains a 16 bit modulus latch a 16 bit loadable up counter counter loading logic a clock selector selectable time base bus drivers and an interrupt interface A modulus register provides the added flexibility of recycling the counter at a count other than 64K clock cycles The content of the modulus latch is transferred to the counter when an overflow occurs or when a user specified edge transition occurs on a designated modulus load input pin In addition a write to the modulus counter simultaneously loads both the counter and the modulus latch with the specified value The counter then begins incrementing from this new value MC68HC16R1 916R1 CONFIGURABLE TIMER MODULE 7 MOTOROLA USER S MANUAL For More Information On This Product 12 7 Go to www freescale com Freescale Semiconductor Inc In order to count the MCSM requires the CPSM clock signals to be present After re set the MCSM does not count until the prescaler in the CPSM starts running whe
334. istor calculate resistance values using positive and negative clamp values then use the larger of the calcu lated values 5 This parameter is periodically sampled rather than 100 tested 6 Applies to single pin only 7 The values of external system components can change the maximum input current value and affect operation A voltage drop may occur across the external source impedances of the adjacent pins impacting conversions on these adjacent pins The actual maximum may need to be determined by testing the complete design 8 Current coupling is the ratio of the current induced from overvoltage positive or negative through an external series coupling resistor divided by the current induced on adjacent pins A voltage drop may occur across the external source impedances of the adjacent pins impacting conversions on these adjacent pins MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product A 25 Go to www freescale com Freescale Semiconductor Inc Table A 11 ADC DC Electrical Characteristics Operating Vss 0 Vdc ADCLK 2 1 MHz T T to T Num Parameter Symbol Min Max Unit 1 Analog Supply VDDA 4 5 5 5 V 2 Internal Digital Supply Vppi 4 5 5 5 V 3 Vgg Differential Voltage Vssi VssA 1 0 1 0 4 Vpp Differential Voltage Vppi 1 0 1 0 V 5 Reference Voltage Low VRL Vssa VppA 2 V 6 Reference Voltage High VRH Vppa 2
335. it always takes place even when a single source is requesting service This is important for two reasons the EBI does not transfer the interrupt acknowledge read cycle to the external bus unless the SCIM2 wins contention and failure to con tend causes the interrupt acknowledge bus cycle to be terminated early by a bus error When arbitration is complete the module with both the highest asserted interrupt level and the highest arbitration priority must terminate the bus cycle Internal modules place an interrupt vector number on the data bus and generate appropriate internal cycle termination signals In the case of an external interrupt request after the interrupt acknowledge cycle is transferred to the external bus the appropriate external device must respond with a vector number then generate data size acknowledge DSACK termination signals or it must assert the autovector AVEC request signal If the de vice does not respond in time the SCIM2 bus monitor if enabled asserts the bus error signal BERR and a spurious interrupt exception is taken Chip select logic can also be used to generate internal AVEC or DSACK signals in response to interrupt acknowledgement cycles Refer to 5 9 3 Using Chip Select Sig nals for Interrupt Acknowledge for more information Chip select address match logic functions only after the EBI transfers an interrupt acknowledge cycle to the exter nal bus following IARB contention All interrupts from interna
336. ith Carry to E E M M 1 C gt E IMM16 3733 jj kk 4 A AAA IND16 X 3743 999g 6 IND16 Y 3753 999g 6 IND16 2 3763 9999 6 3773 hh Il 6 ADDA Add to A M gt A IND8 X 41 ff 6 A AAA IND8 Y 51 ff 6 IND8 Z 61 ff 6 IMM8 71 ii 2 IND16 X 1741 9999 6 IND16 Y 1751 999g 6 IND16 Z 1761 9999 6 EXT 1771 hh Il 6 2741 6 E Y 2751 6 2 2761 6 MC68HC16R1 916R1 MOTOROLA USER S MANUAL 4 12 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 4 2 Instruction Set Summary Continued Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Operand Cycles S MV H EV 2 V C ADDB Add to B M B IND8 X C1 ff 6 A AAA IND8 Y D1 ff 6 IND8 Z E1 ff 6 IMM8 F1 ii 2 IND16 X 17C1 9999 6 IND16 Y 17D1 9999 6 IND16 2 17 1 9999 6 17 1 hh Il 6 E X 27C1 6 2701 6 2 27 1 6 ADDD Add to D D M M 1 gt 5D IND8 X 81 ff 6 A AAA IND8 Y 91 ff 6 IND8 Z Al ff 6 IMM8 FC ii 2 IMM16 37B1 jj kk 4 IND16 X 37C1 999g 6 IND16 Y 37D1 9999 6 IND16 2 37 1 9999 6 37F1 hh Il 6 E X 2781 6 E Y 2791 6 E Z 27A1 6 ADDE Add to E 1 IMM8 7 ii 2 A AAA IMM16 3731 jj kk 4 IND16 X 3741 gggg 6 I
337. iven lines may be required Figure 5 17 shows a recommended method for conditioning the mode select signals The mode configuration drivers are conditioned with R W and DS to prevent conflicts between external devices and the MCU when reset is asserted If external RESET is asserted during an external write cycle R W conditioning as shown in Figure 5 17 prevents corruption of the data during the write Similarly DS conditions the mode con figuration drivers so that external reads are not corrupted when RESET is asserted during an external read cycle MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 44 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc DATA15 gt e DATA8 gt DATA7 gt e DATAO gt OUT1 OUT8 OUT1 OUT8 74HC244 OF 74HC244 OE IN8 IN8 Vpp TIE INPUTS TIE INPUTS A A HIGH OR LOW HIGH OR LOW AS NEEDED AS NEEDED 820 Q Z ns RESET DS e R W DATA BUS SELECT CONDITIONING Figure 5 17 Preferred Circuit for Data Bus Mode Select Conditioning Alternate methods can be used for driving data bus pins low during reset Figure 5 18 shows two of these options The simplest is to connect a resistor in series with a diode from the data bus pin to the RESET line A bipolar transistor can be used for the same purpose but an additional current limiting resis
338. l modules have their associated IACK cycles terminated with an internal DSACK Thus user vectors instead of autovectors must always be used for interrupts generated from internal modules If an internal module makes an interrupt request of a certain priority and the appropriate chip select registers are programmed to generate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority level chip select logic does not respond to the interrupt acknowledge cycle and the internal module supplies a vector number and generates internal cycle termination signals For periodic timer interrupts the PIRQ 2 0 field in the periodic interrupt control register PICR determines PIT priority level PIRQ 2 0 value of 96000 means that PIT interrupts are inactive By hardware convention when the CPU16 receives simulta neous interrupt requests of the same level from more than one SCIM2 source includ ing external devices the periodic interrupt timer is given the highest priority followed by the IRQ pins MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 59 Go to www freescale com Freescale Semiconductor Inc 5 8 4 Interrupt Processing Summary A summary of the entire interrupt processing sequence follows When the sequence begins a valid interrupt service request has been detected and is pending A B C The CPU16 finishes higher priorit
339. lash base address high and low registers BFEBAH and BFEBAL specify ADDR 23 11 of the block to be erased 2 These address bits are don t cares when specifying the block to be erased 3 Erasing the entire array also erases the BEFLASH control register shadow bits NOTE In order to program the array programming voltage must be applied to the VEpg pin VEpg gt Vpp 0 3 V must be applied at all times or damage to the BEFLASH module can occur Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for information on pro gramming and erasing specifications for the BEFLASH module MOTOROLA BLOCK ERASABLE FLASH EEPROM MC68HC16R1 916R1 9 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 9 4 4 1 Programming Sequence Use the following procedure to program the BEFLASH Figures A 22 and A 23 in APPENDIX A ELECTRICAL CHARACTERISTICS for Vepe to Vpp relationships during 1 2 9 10 11 12 13 programming Turn on Vepe apply program erase voltage to pin Clear ERAS and set LAT and VFPE bits in BFECTL to set program mode en able programming address and data latches and invoke special verification read circuitry Set initial value of topuise tO tomin Write new data to the desired address This causes the address and data of the location to be programmed to be latched in the programming latches Set ENPE to apply
340. less than or equal to the mask value from being recognized and processed 7 however is always recognized even if the mask value is 96111 IRQ 7 1 are active low level sensitive inputs The low on the pin must remain asserted until an interrupt acknowledge cycle corresponding to that level is detected MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 57 Go to www freescale com Freescale Semiconductor Inc IRQ7 is transition sensitive as well as level sensitive a level 7 interrupt is not detected unless a falling edge transition is detected on the IRQ line This prevents redundant servicing and stack overflow A non maskable interrupt is generated each time IRQ7 is asserted as well as each time the priority mask is written while IRQ7 is asserted If IRQ7 is asserted and the IP mask is written to any new value including 96111 IRQ7 will be recognized as a new IRQ7 Interrupt requests are sampled on consecutive falling edges of the system clock In terrupt request input circuitry has hysteresis To be valid a request signal must be as serted for at least two consecutive clock periods Valid requests do not cause immediate exception processing but are left pending Pending requests are pro cessed at instruction boundaries or when exception processing of higher priority interrupts is complete The CPU16 does not latch the priority of a pending int
341. lock edg es SPIF is set at the end of the eighth SCK cycle When CPHA equals zero the SS line must be negated and reasserted between each successive serial byte If the slave writes data to the SPI data register while SS is as serted low a write collision error results To avoid this problem the slave should read bit three of PORTMCP which indicates the state of the SS pin before writing to the SPDR again MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL For More Information On This Product 11 9 Go to www freescale com Freescale Semiconductor Inc 11 3 4 2 CPHA 1 Transfer Format Figure 11 4 is a timing diagram of an eight bit MSB first SPI transfer in which CPHA equals one Two waveforms are shown for SCK one for CPOL equal to zero and another for CPOL equal to one The diagram may be interpreted as a master or slave timing diagram since the SCK MISO and MOSI pins are directly connected between the master and the slave The MISO signal shown is the output from the slave and the MOSI signal shown is the output from the master The SS line is the slave select input to the slave SCK CYCLE emma 2 2 2 J espe e SCK CPOL 0 E SCK CPOL 21 MOSI M FROM MASTER Que X 6 X 5 X 4 A2 AL AU use X 3 ED ED X2 Xa X s mso FROM SLAVE S TO SLAVE NOT DEFINED BUT NORMALLY LSB OF PREVIOUSLY T
342. ltages This parameter is periodically sampled rather than 100 tested All pins except TSC Input must be current limited to the value specified To determine the value of the required current limiting resistor calculate resistance values for positive and negative clamp voltages then use the larger of the two values Power supply must maintain regulation within operating Vpp range during instantaneous and operating maximum current conditions All functional non supply pins are internally clamped to Vss for transitions below Vas All functional pins except EXTAL TSC and XFC are internally clamped to Vpp for transitions below Vpp Total input current for all digital input only and all digital input output pins must not exceed 10 mA Exceed ing this limit can cause disruption of normal operation Vepe must not be raised to programming level while Vpp is below specified minimum value Vepe must not be reduced below minimum specified value while Vpp is applied Flash EEPROM modules can be damaged by power on and power off Vep_e transients Maximum power on overshoot tolerance is 13 5 V for periods of less than 30 ns MC68HC16R1 916R1 ELECTRICAL CHARACTERISTICS MOTOROLA USER S MANUAL For More Information On This Product 1 Go to www freescale com Freescale Semiconductor Table A 2 Typical Ratings Inc Num Rating Symbol Value Unit 1 Supply Voltage Vpp 5 0 V 2 Operating Temperature
343. m a common regulator filtering of the analog power is recommended in addition to the bypassing of the supplies already mentioned For example a RC low pass filter could be used to isolate the digital and analog supplies when generated by a common reg ulator If multiple high precision analog circuits are locally employed such as two A D converters the analog supplies should be isolated from each other as sharing sup plies introduces the potential for interference between analog circuits MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC16R1 916R1 10 16 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Grounding is the most important factor influencing analog circuit performance in mixed signal systems or in stand alone analog systems Close attention must be paid not to introduce additional sources of noise into the analog circuitry Common sources of noise include ground loops inductive coupling and combining digital and analog grounds together inappropriately The problem of how and when to combine digital and analog grounds arises from the large transients which the digital ground must handle If the digital ground is not able to handle the large transients the current from the large transients can return to ground through the analog ground It is the excess current overflowing into the analog ground which causes performance degradation by developing a differential voltage betwe
344. m counter PK Program counter extension field SK Stack pointer extension field SP Stack pointer XK Index register X extension field YK Index register Y extension field ZK Index register Z extension field XMSK Modulo addressing index register X mask YMSK Modulo addressing index register Y mask 5 LPSTOP mode control bit MV AM overflow flag H Half carry flag EV AM extended overflow flag N Negative flag Z Zero flag V Two s complement overflow flag C Carry borrow flag IP Interrupt priority field SM Saturation mode control bit NOMENCLATURE For More Information On This Product Go to www freescale com MC68HC16R1 916R1 USER S MANUAL 2 3 Pin and Signal Mnemonics Freescale Semiconductor Inc Mnemonic Register ADDR 23 0 Address bus AN 7 0 ADC Analog inputs AS Address strobe AVEC Autovector BERR Bus error BG Bus grant BGACK Bus grant acknowledge BKPT Breakpoint BR Bus request CLKOUT System clock CPWM 19 18 CS 10 5 CS3 CTM7 PWM outputs Chip selects MC68HC16R1 916R1 USER S MANUAL CSBOOT Boot ROM chip select CSE Emulation chip select CSM Module chip select CTD 5 4 Double action submodule outputs CTM2C CTM7 Modulus clock CTS 16A 16B CTM7 SASM 16 Channels CTS 14A 14B CTM7 SASM 14 Channels CTS 12A 12B CTM7 SASM 12 Channels CTS 10A 10B CTM7 SASM 10 Channels CTS 8A 8B CTM7 SASM 8 Channels CTS 6A 6B CTM7 SASM 6 Channel
345. m of port F pins registers and control logic Port F pins can be configured as interrupt request inputs edge detect input outputs or discrete input outputs When port F pins are configured for edge detection and a priority level is specified by writing a value to the port F edge detect interrupt level register PFLVR port F control logic generates an interrupt request when the specified edge is detected Interrupt vector assignment is made by writing a value to the port F edge detect interrupt vector register PFIVR The edge detect interrupt has the lowest arbitration priority in the SCIM2 A write to the port F data register PORTF is stored in the internal data latch and if any port F pin is configured as an output the value stored for that bit is driven on the pin A read of PORTF returns the value on a pin only if the pin is configured as a dis crete input Otherwise the value read is the value stored in the data register PORTF is a single register that can be accessed in two locations PORTF1 PORTFO It can be read or written at any time including when the MCU is in emulator mode Port F data direction register DDRF bits control the direction of port F pin drivers when the pins are configured for I O Setting any bit in this register configures the corresponding pin as an output Clearing any bit in this register configures the corresponding pin as an input MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 72 F
346. mited to a single sequence or a sequence can be Single or continuous conversion performed continuously The state of the SCAN bit in ADCTL1 deter mines whether single or continuous conversion is performed Conversion sequence s can be run on a single channel or on a block of Single or multiple channel conversion or eight channels Channel conversion is controlled by the state of the MULT bit in ADCTL1 10 7 5 2 Conversion Modes Conversion modes are defined by the state of the SCAN MULT and S8CM bits in ADCTL1 Table 10 6 shows mode numbering Table 10 6 ADC Conversion Modes SCAN MULT S8CM Mode 0 0 0 0 0 0 1 1 0 EN EN N The following paragraphs describe each type of conversion mode Mode 0 A single four conversion sequence is performed on a single input channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT3 The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the conversion sequence is complete Mode 1 A single eight conversion sequence is performed on a single input channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT7 The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in ADSTAT is set when the conversion sequence is complete MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC16R1 916
347. modules have an interrupt request pending at the level being arbitrated on the IMB the submodule with the lowest number also the lowest status interrupt con trol register address is given the highest priority to respond If the CTM7 wins arbitration it responds with a vector number generated by concate nating VECT 7 6 in BIUMCR and the six low order bits specified by the number of the submodule requesting service Table 12 8 shows the allocation of CTM7 submodule numbers and interrupt vector numbers MOTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 20 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 12 8 CTM7 Interrupt Priority and Vector Pin Allocation Submodule Submodule Submodule Base Submodule Binary Name Number Address Vector Number BIUSM 0 YFF900 None CPSM 1 YFF908 None MCSM 2 YFF910 xx000010 FCSM 3 YFF918 xx00001 1 DASM 4 YFF920 xx000100 DASM 5 YFF928 xx000101 SASM 6 YFF930 xx0001 10 SASM 8 YFF940 xx001000 SASM 10 YFF950 xx001010 SASM 12 YFF960 xx001100 SASM 14 YFF970 xx001110 SASM 16 YFF980 xx010000 PWMSM 18 YFF990 xx010010 PWMSM 19 YFF998 xx010011 NOTES 1 Y M111 where M is the state of the MM bit in SCIMCR Y 7 or F 2 xx represents VECT 7 6 in the BIUSM module configuration register MC68HC16R1 916R1 USER S MANUAL CONFIGURABLE TIMER MODUL
348. n 0006 During execution of the instruc tion PK PC is loaded with the address of the first instruction word in the new instruc tion stream However stages A and B still contain words from the old instruction stream Extra processing steps must be performed before execution from the new in struction stream 4 12 Instruction Timing The execution time of CPU16 instructions has three components Bus cycles required to prefetch the next instruction e Bus cycles required for operand accesses e Time required for internal operations A bus cycle requires a minimum of two system clock periods If the access time of a memory device is greater than two clock periods bus cycles are longer However all bus cycles must be an integer number of clock periods CPU16 internal operations are always an integer multiple of two clock periods Dynamic bus sizing affects bus cycle time The integration module manages all ac cesses Refer to SECTION 5 SINGLE CHIP INTEGRATION MODULE 2 for more in formation The CPU16 does not execute more than one instruction at a time The total time re quired to execute a particular instruction stream can be calculated by summing the in dividual execution times of each instruction in the stream MOTOROLA MC68HC16R1 916R1 4 36 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Total execution time is calculated using the expression CLp
349. n the software sets the PRUN bit This allows all counters in the CTM7 submodules to be synchronized The CTM7 contains one MCSM Figure 12 4 shows a block diagram of the MCSM A TIME BASE BUSES TBBB 6 CLOCKS PCLK 1 6 FROM PRESCALER BUS lt SELECT lt UR EDGE gt SELECT MARS DETECT DRVA DRVB CONTROL REGISTER BITS IN2 CLK2 cua CLKO CONTROL REGISTER BIT CONTROL REGISTER BITS OVERFLOW _ INTERRUPT gt CONTROL AA 16 BIT UP COUNTER MODULUS MODULUS LOAD CONTROL INPUT PIN CTML MODULUS EDGE LOAD INPU PIN CTD9 DETEC Aw IN1 EDGEN EDGEP CONTROL REGISTER BIT CONTROL REGISTER BITS MODULUS REGISTER A IL1 ILO REGISTE m SUBMODULE BUS CTM MCSM BLOCK Figure 12 4 MCSM Block Diagram 12 7 1 MCSM Modulus Latch The 16 bit modulus latch is a read write register that is used to reload the counter automatically with a predetermined value The contents of the modulus latch register can be read at any time Writing to the register loads the modulus latch with the new value This value is then transferred to the counter register when the next load condition occurs However writing to the corresponding counter register loads t
350. n 64K clock cycles The CTM7 has one MCSM The single action submodule SASM provides an input capture and an output com pare for each of two bidirectional pins A total of six SASMs eight channels are con tained in the CTM7 The double action submodule DASM provides two 16 bit input capture or two 16 bit output compare functions that can occur automatically without software intervention The CTM7 has two DASMs The pulse width modulation submodule PWMSM can generate pulse width modulat ed signals over a wide range of frequencies independently of other CTM output sig nals PWMSMs are not affected by time base bus activity The CTM7 has two PWMSMs 12 2 Address Map CTM7 address map occupies 256 bytes from address YFF900 to YFF9FF All CTM7 registers are accessible only when the CPU16 is in supervisor mode All re served addresses return zero when read and writes have no effect Refer to D 7 Con figurable Timer Module 7 for information concerning CTM7 address map and register bit field descriptions 12 3 Time Base Bus System The CTM7 time base bus system is composed of two 16 bit buses TBB1 and TBB2 These buses are used to transfer timing information from the counter submodules to the action submodules Two time base buses are available to each submodule A counter submodule can drive one of the two time base buses to which it is connected Each action submodule can choose one of the two time base buses to which it
351. n Register Reset Values Fields Reset Values Base address 000000 Block size 512 Kbyte Async sync mode Asynchronous mode Upper lower byte Both bytes Read write Read write AS DS AS DSACK 13 Wait states Address space Supervisor space IPL Any level Autovector Interrupt vector externally NOTES 1 These fields not used unless Address space is set to CPU space 5 10 General Purpose Input Output The SCIM2 contains six general purpose input output ports ports A B E F G and H Port C an output only port is included under the discussion of chip selects Ports A B and G are available in single chip mode only and port H is available in single chip or 8 bit expanded modes only Ports E F G and H have an associated data direction register to configure each pin as input or output Ports A and B share a data direction register that configures each port as input or output Ports E and F have associated pin assignment registers that configure each pin as digital I O or an alternate function Port F has an edge detect flag register that indicates whether a transition has occurred on any of its pins Table 5 27 shows the shared functions of the general purpose I O ports and the modes in which they are available Table 5 27 General Purpose I O Ports MOTOROLA 5 70 Port Shared Function Modes A ADDR 18 11 Single chip B ADDR 10 3 Single chip E Bus Control All F TRQ 7 1 FA
352. n This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc NOTE Values of 0002 in the period register PWMA2 and 0001 in the pulse width register PWMB2 result in the maximum possible output frequency for a given PWM counter clock frequency 12 10 5 PWMSM Pulse Width Registers and Comparator The pulse width section of the PWMSM consists of two 16 bit pulse width registers PWMB1 PWMB2 and one 16 bit comparator PWMB2 holds the current PWM pulse width value and PWMB 1 holds the next PWM pulse width value The next pulse width of the output PWM signal is established by writing a value into PWMB1 PWMB2 acts as a double buffer for PWMB1 allowing the contents of PWMB1 to be changed at any time without affecting the pulse width of the current output signal PWMB2 is not user accessible PWMB1 can be read or written at any time The new value in PWMBI is transferred to PWMB2 on the next full cycle of the output or when a one is written to the LOAD bit in PWMSIC The comparator continuously compares the contents of PWMB2 with the counter When a match occurs the output flip flop is cleared This pulse width match completes the pulse width however it does not affect the counter The PWM output pulse may be as short as one PWM counter clock period PWMB2 0001 It may be as long as one PWM clock period less than the PWM period For example a pulse width equal to 65535 PWM clock periods can be obtained
353. n bank 0 4 13 4 Types of Exceptions Exceptions can be either internally or externally generated External exceptions which are defined as asynchronous include interrupts bus errors breakpoints and resets Internal exceptions which are defined as synchronous include the software interrupt SWI instruction the background BGND instruction illegal instruction exceptions and the divide by zero exception 4 13 4 1 Asynchronous Exceptions Asynchronous exceptions occur without reference to CPU16 or IMB clocks but excep tion processing is synchronized For all asynchronous exceptions but RESET excep tion processing begins at the first instruction boundary following recognition of an exception Refer to 5 8 1 Interrupt Exception Processing for more information con cerning asynchronous exceptions Because of pipelining the stacked return PK PC value for all asynchronous excep tions other than reset is equal to the address of the next instruction in the current in struction stream plus 0006 The RTI instruction which must terminate all exception handler routines subtracts 0006 from the stacked value to resume execution of the interrupted instruction stream 4 13 4 2 Synchronous Exceptions Synchronous exception processing is part of an instruction definition Exception pro cessing for synchronous exceptions is always completed and the first instruction of the handler routine is always executed before interrupts are detect
354. n be fetched simultaneously Instructions that use 8 bit indexed immediate and relative addressing modes have this form Code written with these instructions is very compact Figure 4 4 shows basic CPU16 instruction formats MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product 4 33 Go to www freescale com Freescale Semiconductor Inc 8 Bit Opcode with 8 Bit Operand 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode Operand 8 Bit Opcode with 4 Bit Index Extensions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode X Extension Y Extension 8 Bit Opcode Argument s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode Operand Operand s Operand s 8 Bit Opcode with 8 Bit Prebyte No Argument 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Prebyte Opcode 8 Bit Opcode with 8 Bit Prebyte Argument s 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Prebyte Opcode Operand s Operand s 8 Bit Opcode with 20 Bit Argument 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode 0 Extension Operand Figure 4 4 Basic Instruction Formats 4 10 Execution Model This description builds up a conceptual model of the mechanism the CPU16 uses to fetch and execute instructions The functional divisions in the model do not necessarily correspond to physical subunits of the microprocessor As shown in Figure 4 5 there are three functional blocks
355. n cycles use internal handshaking signals generated by the chip select logic To initiate a transfer the MCU asserts an address and the SIZ 1 0 signals When AS DS and R W are valid a peripheral device either places data on the bus read cycle or latches data from the bus write cycle At the appropriate time chip select logic asserts data size acknowledge signals The DSACK option fields in the chip select option registers determine whether inter nally generated DSACK or externally generated DSACK is used The external DSACK lines are always active regardless of the setting of the DSACK field in the chip select option registers Thus an external DSACK can always terminate a bus cycle Holding a DSACK line low will cause essentially all external bus cycles to be three cycle zero wait states accesses unless the chip select option register specifies fast accesses NOTE There are certain exceptions to the three cycle rule when one or both DSACK lines are asserted Check the current device and mask set errata for details For fast termination cycles the fast termination encoding 1110 must be used Re fer to 5 9 1 Chip Select Registers for information about fast termination setup To use fast termination an external device must be fast enough to have data ready within the specified setup time for example by the falling edge of S4 Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for information about fast termina tion
356. n external filter is attached to the pin and that the crystal oscillator is stable 4 Assumes that Vppsyn is stable that an external filter is attached to the XFC pin and that the crystal oscillator is stable followed by Vpp ramp up Lock time is measured from Vpp at specified minimum to RESET negated 5 Cold start is measured from Vppsyn and Vpp at specified minimum to RESET negated 6 Internal VCO frequency fyco is determined by SYNCR W and Y bit values The SYNCR X bit controls a divide by two circuit that is not in the synthesizer feedback loop When X 0 the divider is enabled and fsys fyco 4 When X 1 the divider is disabled and fsys fyco 2 X must equal one when operating at maximum specified 7 This parameter is periodically sampled rather than 100 tested 8 Assumes that a low leakage external filter network is used to condition clock synthesizer input voltage Total external resistance from the XFC pin due to external leakage must be greater than 15 MO to guarantee this spec ification Filter network geometry can vary depending upon operating environment 9 Proper layout procedures must be followed to achieve specifications 10 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal Noise injected into the PLL circuitry via V
357. nce repeats The appropriate CCF bit in ADSTAT is set as each register is filled The SCF bit in AD STAT is set when the first eight conversion sequence is complete Mode 6 Continuous conversions are performed on each of four sequential input channels starting with the channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT3 The appropriate CCF bit in AD STAT is set as each register is filled The SCF bit in ADSTAT is set when the first four conversion sequence is complete Mode 7 Continuous conversions are performed on each of eight sequential input channels starting with the channel specified by the value in CD CA Each result is stored in a separate result register RSLTO to RSLT7 The appropriate CCF bit in AD STAT is set as each register is filled The SCF bit in ADSTAT is set when the first eight conversion sequence is complete Table 10 7 is a summary of ADC operation when MULT is cleared single channel modes Table 10 8 is a summary of ADC operation when MULT is set multi channel modes Number of conversions per channel is determined by SCAN Channel num bers are given in order of conversion MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For More Information On This Product 10 9 Go to www freescale com Freescale Semiconductor Inc Table 10 7 Single Channel Conversions MULT 0
358. nce to Vss VRL 0 3 6 5 V 4 Differential Voltage Vssi Vssa 0 1 0 1 V 5 VppDifferential Voltage Vppi VppA 6 5 6 5 V 6 Veer Differential Voltage VRH VRL 6 5 6 5 V 7 Ven to Differential Voltage VRH VppA 6 5 6 5 V 8 to Vssa Differential Voltage Vni VssA 6 5 6 5 V Disruptive Input Current 2 9 4 5 6 7 9 VuEGCLAMP 0 3 V INA 500 500 uA Veosctamp 8 V 10 Positive Overvoltage Current Coupling gt 56 8 Kp 2000 11 Negative Overvoltage Current Coupling Ratio gt 68 KN 500 Maximum Input Current 346 12 VNuEGCLAMP 0 3 V IMA 25 25 mA 8 V NOTES 1 Below disruptive current conditions a stressed channel will store the maximum conversion value for analog inputs greater than Vay and the minimum conversion value for inputs less than VgL This assumes that Vay lt VppA Vg gt due to the presence of the sample amplifier Other channels are not affected by non disruptive conditions 2 Input signals with large slew rates or high frequency noise components cannot be converted accurately These signals also interfere with conversion of other channels 3 Exceeding limit may cause conversion error on stressed channels and on unstressed channels Transitions within the limit do not affect device reliability or cause permanent damage 4 Input must be current limited to the value specified To determine the value of the required current limiting re s
359. nction codes to SPACE fields and to the IP mask if the SPACE field encoding is not for CPU space Appropriate address bus bits to base address fields e Read write status to R W fields ADDRO and or SIZ 1 0 bits to BYTE field 16 bit ports only Priority of the interrupt being acknowledged ADDR 3 1 to IPL fields when the access is an interrupt acknowledge cycle When a match occurs the chip select signal is asserted Assertion occurs at the same time as AS or DS assertion in asynchronous mode Assertion is synchronized with ECLK in synchronous mode In asynchronous mode the value of the DSACK field de termines whether DSACK is generated internally DSACK 3 0 also determines the number of wait states inserted before internal DSACK assertion The speed of an external device determines whether internal wait states are needed Normally wait states are inserted into the bus cycle during S3 until a peripheral as serts DSACK If a peripheral does not generate DSACK internal DSACK generation must be selected and a predetermined number of wait states can be programmed into the chip select option register Refer to the SC M Reference Manual SCIMRM AD for further information 5 9 3 Using Chip Select Signals for Interrupt Acknowledge Ordinary bus cycles use supervisor or user space access but interrupt acknowledge bus cycles use CPU space access Refer to 5 6 4 CPU Space Cycles and 5 8 Inter rupts for more in
360. ncy BG is only asserted at the end of operand transfer If more than one external device can be bus master required external arbitration must begin when a requesting device receives BG An external device must assert BGACK when it assumes mastership and must maintain BGACK assertion as long as it is bus master Two conditions must be met for an external device to assume bus mastership The de vice must receive BG through the arbitration process and BGACK must be inactive indicating that no other bus master is active This technique allows the processing of bus requests during data transfer cycles BG is negated a few clock cycles after BGACK transition However if bus requests are still pending after BG is negated the MCU asserts BG again within a few clock cycles MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 39 Go to www freescale com Freescale Semiconductor Inc This additional BG assertion allows external arbitration circuitry to select the next bus master before the current master has released the bus Refer to Figure 5 16 which shows bus arbitration for a single device The flow chart shows BR negated at the same time BGACK is asserted MCU REQUESTING DEVICE REQUEST THE BUS 1 ASSERT BUS REQUEST BR GRANT BUS ARBITRATION 1 ASSERT BUS GRANT BG ACKNOWLEDGE BUS MASTERSHIP 1 EXTERNAL ARBITRATION DETERMINES NEXT BUS M
361. nd of preamble transmission The SBK bit SCCR1 is used to insert break frames in a transmission A non zero integer number of break frames is transmitted while SBK is set Break transmission begins when SBK is set and ends with the transmission in progress at the time either SBK or TE is cleared If SBK is set while a transmission is in progress that transmis sion finishes normally before the break begins To assure the minimum break time toggle SBK quickly to one and back to zero The TC bit is set at the end of break trans mission After break transmission at least one bit time of logic level one mark idle is transmitted to ensure that a subsequent start bit can be detected If TE remains set after all pending idle data and break frames are shifted out and TC are set and TXD is held at logic level one mark When TE is cleared the transmitter is disabled after all pending idle data and break frames are transmitted The TC flag is set and control of the TXD pin reverts to PQSPAR and DDRQS Buffered data is not transmitted after TE is cleared To avoid losing data in the buffer do not clear TE until TDRE is set Some serial communication systems require a mark on the TXD pin even when the transmitter is disabled Configure the TXD pin as an output then write a one to PQS7 When the transmitter releases control of the TXD pin it reverts to driving a logic one output To insert a delimiter between two messages to pla
362. nd one 16 bit compar ator though internally channel B has two data registers B1 and B2 DASM operating mode determines which register is software accessible Refer to Table 12 4 Table 12 4 Channel B Data Register Access Mode Data Register Input Capture Registers A and B2 are used to hold the captured values In these modes IPWM IPM IC the B1 register is used as a temporary latch for channel B Output Compare Registers A and B2 are used to define the output pulse Register B1 is not OCA OCAB used in these modes Output Pulse Width Modulation Mode OPWM Registers A and B1 are used as primary registers and hidden register B2 is used as a double buffer for channel B Register contents are always transferred automatically at the correct time so that the minimum pulse measured or generated is just one time base bus count The A and B data registers are always read write registers accessible via the CTM7 submodule bus The CTM7 has two DASMs Figure 12 6 shows a block diagram of the DASM 2 BASE BUSES TBBB 8U5 BSL FORCA FORCB WOR IN SELECT TN i 16 BIT COMPARATOR A OUTPUT OUTPUT gt FLIP FLOP gt BUFFER PIN A 16 BIT REGISTER A EDPOL Y EDGE 16 BIT REGISTER B1 DETECT
363. nd transfer BG is not asserted in response to BR until after all cycles of the current operand transfer are complete 11 In the absence of DSACK 1 0 BERR is an asynchronous input using the asynchronous setup time specification 47A 12 After external RESET negation is detected a short transition period approximately 2 elapses then the SCIM2 drives RESET low for 512 toy 13 External logic must pull RESET high during this period in order for normal MCU operation to begin 14 Eight pipeline states are multiplexed into IPIPE 1 0 The multiplexed signals have two phases MC68HC16R1 916R1 ELECTRICAL CHARACTERISTICS MOTOROLA USER S MANUAL For More Information On This Product A 9 Go to www freescale com Freescale Semiconductor Inc CLKOUT 16 CLKOUT TIM Figure A 1 CLKOUT Output Timing Diagram EXTAL NOTE TIMING SHOWN WITH RESPECT TOV Wy LEVELS PULSE WIDTH SHOWN WITH RESPECT TO 50 V pp 16 EXT CLK INPUT TIM Figure A 2 External Clock Input Timing Diagram ECLK NOTE TIMING SHOWN WITH RESPECT TOV LEVELS 16 OUTPUT TIM Figure A 3 ECLK Output Timing Diagram MOTOROLA MC68HC16R1 916R1 A 10 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc rim ADDR 23 0 B C 2 0 12 E Ee s w DT TT eu 1 TEN Y TL IPIPE0 L le O O OF
364. negation of DSACK The MCU may complete the current word transfer in progress For a long word to byte transfer this could be after S2 or S4 For a word to byte transfer activity ceases after S2 Negating and reasserting HALT according to timing requirements provides single step bus cycle to bus cycle operation The HALT signal affects external bus cycles only so that a program that does not use external bus can continue executing During dy namically sized 8 bit transfers external bus activity may not stop at the next cycle 8 bit transfers external bus activity may not stop at the next cycle boundary Occurrence of a bus error while HALT is asserted causes the CPU16 to process a bus error exception MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 38 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc When the MCU completes a bus cycle while the HALT signal is asserted the data bus goes into a high impedance state and the AS and DS signals are driven to their inac tive states Address function code size and read write signals remain in the same state The halt operation has no effect on bus arbitration However when external bus arbi tration occurs while the MCU is halted address and control signals go into a high impedance state If HALT is still asserted when the MCU regains state If HALT is still asserted when the MCU regains control of the bus
365. nemonic Register ADCMCR ADC Module Configuration Register ADTEST ADC Test Register ADCTL 0 1 ADC Control Registers 0 1 ADSTAT ADC Status Register BFEBAH BEFLASH Base Address High Register BFEBAL BEFLASH Base Address Low Register BFEBS 0 3 BEFLASH Bootstrap Words 0 3 BFECTL BEFLASH Control Register BFEMCR BEFLASH Module Configuration Register BFETST BEFLASH Test Register BIUMCR CTM7 BIUSM Module Configuration Register BIUTEST CTM7 BIUSM Test Register BIUTBR CTM7 BIUSM Time Base Register CPCR CTM7 CPSM Control Register CPTR CTM7 CPSM Test Register CREG SCIM2 Test Module Control Register CSBARBT SCIM2 Chip Select Base Address Register Boot ROM CSBAR 0 10 SCIM2 Chip Select Base Address Registers 0 10 CSORBT SCIM2 Chip Select Option Register Boot ROM CSOR 0 10 SCIM 2 Chip Select Option Registers 0 10 CSPAR 0 1 SCIM2 Chip Select Pin Assignment Registers 0 1 DASM 4 5 A CTM7 DASM A Data Registers 4 5 DASM 4 5 B CTM7 DASM B Data Registers 4 5 DASM 4 5 SIC CTM7 DASM Status Interrupt Control Registers 4 5 DDRAB SCIM 2 Port A B Data Direction Register DDRE SCIM Port E Data Direction Register DDRF SCIM2 Port F Data Direction Register DDRG SCIM2 Port G Data Direction Register DDRH SCIM2 Port H Data Direction Register DDRM MCCI Data Direction Register DREG SCIM2 Test Module Distributed Register FCSMS3SIC CTM7 5 Status Interrupt Control Register FCSM3CNT CTM7 FCSMS Counter Register FEE 1 2 BAH Flash EEPROM Base Address High Regi
366. ng or immediately following the 32 Kbyte array Pulling data bus pin DATA14 low during reset disables both the 16 and 32 Kbyte flash EEPROM modules and places them in stop mode Either of the flash EEPROM modules can be configured to generate bootstrap infor mation on system reset Bootstrap information consists of the initial program counter and stack pointer values for the CPU16 The flash EEPROM and its control bits are erasable and programmable under soft ware control Program erase voltage must be supplied via external Vep_ pins Data is programmed in byte or word aligned fashion Multiple word programming is not sup ported The flash EEPROM modules support bulk erase only and have a minimum program erase life of 100 cycles The flash EEPROM modules have hardware interlocks which protect stored data from corruption by accidental enabling of the program erase voltage to the flash EEPROM arrays With the hardware interlocks inadvertent programming or erasure is highly un likely 8 1 Flash EEPROM Control Block Each flash EEPROM module has a 32 byte control block with five registers to control flash EEPROM operation the flash EEPROM module configuration register FEE1MCR FEE2MCR the flash EEPROM test register FEE1TST FEE2TST the flash EEPROM array base address registers FEE1BAH FEE2BAH and FEE1BAL FEE2BAL and the flash EEPROM control register FEE1CTL FEE2CTL MC68HC16R1 916R1 FLASH EEPROM MODULE MOTOROLA USER S MA
367. ning these boundary conditions The first boundary condition occurs when the CPU16 drives 7FFFF onto its address bus and is derived as follows 1 If CPU ADDR 19 0 7FFFF 960111 1111 1111 1111 1111 2 Then CPU ADDR19 960 and IMB ADDR19 0 3 Consequently IMB ADDR 23 20 0000 0 4 Thus IMB ADDR 23 0 07FFFF 0000 0111 1111 1111 1111 1111 The second boundary condition occurs when the CPU16 drives 80000 onto its ad dress bus and is derived as follows 1 If CPU ADDR 19 0 80000 1000 0000 0000 0000 0000 2 Then CPU ADDR19 1 and IMB ADDR19 1 3 Consequently IMB ADDR 23 20 1111 F 4 Thus IMB ADDR 23 0 F80000 1111 1000 0000 0000 0000 0000 As the above boundary conditions illustrate addresses between 080000 and F7FFFF will never be seen on the IMB of a CPU16 derivative At no time will IMB ad dress lines 23 19 be driven to states opposite that of CPU address line 19 It is important to note that this gap is present on the IMB only The CPU16 simply sees a flat one megabyte memory map from 00000 to FFFFF and user software need only generate 20 bit effective addresses to access any location in this range 3 6 Internal Register Maps In Figures 3 6 and 3 7 IMB address lines 23 20 are represented by the letter Y The value of Y is equal to M111 where M is the logic state of the module mapping MM bit in the single chip integration module configuration register SCIMCR NOTE
368. no effect because the CPU16 always operates in the supervisor mode MM Module Mapping 0 Internal modules are addressed from 7FF000 7FFFFF 1 Internal modules are addressed from FFFO000 FFFFFF The logic state of the MM determines the value of ADDR23 for IMB module addresses Because ADDR 23 20 are driven to the same state as ADDR19 MM must be set to one If MM is cleared IMB modules are inaccessible to the CPU16 This bit can be written only once after reset ABD Address Bus Disable 0 Pins ADDR 2 0 operate normally 1 Pins ADDR 2 0 are disabled ABD is cleared to zero when the MCU is in an expanded mode and set to one in single chip mode ABD can be written only once after reset RWD Read Write Disable 0 R W signal operates normally 1 R W signal placed in high impedance state RWD is cleared to zero when the MCU is in an expanded mode and set to one in single chip mode RWD can be written only once after reset IARB 3 0 Interrupt Arbitration ID Each module that can generate interrupts including the SCIM2 has an IARB field Each IARB field can be assigned a value from 0 to F During an interrupt acknowledge cycle IARB permits arbitration among simultaneous interrupts of the same priority level The reset value of the SCIM2 IARB field is F the highest priority This prevents SCIM2 interrupts from being discarded during system initialization D 2 2 SCIM Test Register SCIMTR Single C
369. nowledge cycle occurs To ensure detection BKPT should be asserted until a breakpoint acknowledge cycle is recognized MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 34 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc When assertion is acknowledged by the CPU16 the MCU performs a word read from CPU space address 00001E This corresponds to the breakpoint number field ADDR 4 2 and the type bit T being set to all ones source 7 type 1 If this bus cycle is terminated by BERR or by DSACK the MCU performs breakpoint exception processing Refer to Figure 5 14 for a flow chart of the breakpoint operation Refer to the SCIM Reference Manual SCIMRM AD for further information BREAKPOINT OPERATION FLOW CPU16 PERIPHERAL ACKNOWLEDGE BREAKPOINT 1 SET RW TO READ 2 SET FUNCTION CODE TO CPU SPACE 3 PLACE CPU SPACE TYPE 0 ON ADDR 19 16 4 PLACE ALL ONES ON ADDR 4 2 ASSERT DSACK OR BERR TO INITIATE EXCEPTION PROCESSING 5 SET ADDR1TO ONE 6 SET SIZE TO WORD 7 ASSERT AS AND DS NEGATE AS orDS NEGATE DSACK orBERR INITIATE HARDWARE BREAKPOINT PROCESSING CPU16 BREAKPOINT OPERATION FLOW Figure 5 14 Breakpoint Operation Flowchart 5 6 4 2 LPSTOP Broadcast Cycle Low power stop mode is initiated by the CPU16 Individual modules can be stopped by setting the STOP bits in each module configuration register The SCIM
370. nputs Figure 10 4 is a diagram of the analog input circuitry MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC16R1 916R1 10 14 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Vppa o Yoo Y O j 0 M SAMPLE AMP COMPARATOR e F RC DAC 8CHANNELS TOTAL e ARRAY e e e Em 07 0 107 0 Vesa Va REF 2 TWO SAMPLE AMPS EXIST ON THE ADC WITH 8 CHANNELS ON EACH SAMPLE AMP ADC 8CH SAMPLE Figure 10 4 Analog Input Circuitry Since the sample amplifier is powered by it can accurately transfer input signal levels up to but not exceeding and down to but not below Vasa If the input signal is outside of this range the output from the sample amplifier is clipped In addition Vay and Vg must be within the range defined by Vpp4 and As long as is less than or equal to and Vg is greater than or equal to and the sample amplifier has accurately transferred the input signal resolution is ratiometric within the limits defined by Vp and Vax If Vay is greater than Vppa the sample am plifier can never transfer a full scale value If Vp is less than Vssa the sample ampli fier can never transfer a zero value Figure 10 5 shows the results of reference voltages outside the range defined by VppA and Vasa At the top of the input signal range VppA is 10 mV lower than V
371. ns are con figured as I O Setting a bit configures the corresponding pin as an output Clearing a bit configures the corresponding pin as an input MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 10 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 2 9 Port E Data Register PORTEO Port EO Data Register YFFA10 PORTE1 Port E1 Data Register YFFA12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PE7 PE6 PE5 PE4 PE3 PE2 1 PEO RESET U U U U U U U U This register can be accessed in two locations and can be read or written at any time A write to this register is stored in an internal data latch and if any pin in the corresponding port is configured as an output the value stored for that bit is driven out on the pin A read of this data register returns the value at the pin only if the pin is configured as a discrete input Otherwise the value read is the value stored in the register Bits 15 8 are unimplemented and will always read zero D 2 10 Port E Data Direction Register DDRAB Port A B Data Direction Register YFFA14 DDRE Port E Data Direction Register YFFA15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 DDA DDB DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDEO 0 0 0 0 0 0 0 0 The port E data direction register controls the direction of the port E p
372. nting the number of events occurring on the CTM2C input pin Alterna tively the FCSM can be programmed to generate an interrupt request when a pre defined number of events have been counted This is done by presetting the counter with the two s complement value of the desired number of events 12 6 4 FCSM Time Base Bus Driver The DRVA and DRVB bits in FCSMSIC select the time base bus to be driven Which of the time base buses is driven depends on where the FCSM is physically placed in any particular CTM implementation Refer to Figure 12 1 and Table 12 1 for more information WARNING Two time base buses should not be driven at the same time 12 6 5 FCSM Interrupts The FCSM can optionally request an interrupt when its counter overflows and the COF bit in FCSMSIC is set To enable interrupts set the IL 2 0 field in the FCSMSIC to a non zero value The CTM7 compares the CPU16 IP mask value to the priority of the requested interrupt designated by IL 2 0 to determine whether it should contend for arbitration priority During arbitration the BIUSM provides the arbitration value speci fied by IARB 2 0 in BIUMCR and IARB3 FCSMSIC If the CTM7 wins arbitration it responds with a vector number generated by concatenating VECT 7 6 in BIUMCR and the six low order bits specified by the number of the submodule requesting ser vice Thus for FCSM12 CTMT six low order bits would be 12 in decimal or 96001100 in binary 12 6 6 FCSM Reg
373. o ASLM Arithmetic Shift Left INH 27B6 4 A A A AM EELTT IIee b35 bo ASLW Arithmetic Shift Left IND16 X 2704 999g 8 A A A A Word _ lt IND16 Y 2714 gggg 8 SKLLL TL IND16 Z 2724 gggg 8 EXT 2734 hh Il 8 ASR Arithmetic Shift Right IND8 X 00 ff 8 A IND8 Y 1D ff 8 ELIT ITT TMl IND8 Z 2D ff 8 IND16 X 170D 9999 8 IND16 171D 999g 8 IND16 Z 172D 9999 8 EXT 173D hh Il 8 MOTOROLA MC68HC16R1 916R1 4 14 For More Information On This Product USER S MANUAL Go to www freescale com Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles S MV H EV 2 V C ASRA Arithmetic Shift Right INH 370D 2 A AAA A gt LOTIT Pel b bo ASRB Arithmetic Shift Right INH 371D 2 A AAA B ITT TL Pe b7 bo ASRD Arithmetic Shift Right INH 27FD 2 AAA D T TPE 5 ASRE Arithmetic Shift Right INH 277D 2 A AAA E Th 5 bo ASRM Arithmetic Shift Right INH 27BA 4 A AM DIT b35 bo ASRW Arithmetic Shift Right IND16 X 270D 999g 8 A
374. o D 5 Analog to Digital Converter Module for register address mapping and bit field definitions 10 1 General The ADC is a unipolar successive approximation converter with eight modes of oper ation It has selectable 8 or 10 bit resolution Monotonicity is guaranteed in both modes A bus interface unit handles communication between the ADC and other microcontrol ler modules and supplies IMB timing signals to the ADC Special operating modes and test functions are controlled by a module configuration register ADCMCR and a factory test register ADCTST ADC module conversion functions can be grouped into three basic subsystems an analog front end a digital control section and result storage Figure 10 1 is a func tional block diagram of the ADC module In addition to use as multiplexer inputs the eight analog inputs can be used as a gen eral purpose digital input port port ADA provided signals are within logic level spec ification A port data register PORTADA is used to access input data 10 2 External Connections The ADC uses 12 pins on the MCU package Eight pins are analog inputs which can also be used as digital inputs two pins are dedicated analog reference connections and Vg and two pins are analog supply connections and VssA MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For More Information On This Product 10 1 Go to www freescale com Freescale Semiconductor
375. ode Selection 5 7 3 8 Emulation Mode Selection 5 7 4 MCU Module Pin Function During Reset 5 7 5 Pin State During Reset 5 7 5 1 Reset States of SCIM2 Pins MOTOROLA VI For More Information On This Product Go to www freescale com MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 5 7 5 2 Reset States of Pins Assigned to Other MCU Modules 5 53 5 7 6 Reset IMNO nds 5 54 5 7 7 Power On Reset rm 5 54 5 7 8 Use of the Three State Control Pin 5 55 5 7 9 Reset Processing 5 56 5 7 10 Res t Stat s IRGOISICN 5 56 5 8 5 57 5 8 1 Interrupt Exception Processing 5 57 5 8 2 Interrupt Priority and Recognition 242 21 5 57 5 8 3 Interrupt Acknowledge and Arbitration 5 58 5 8 4 Interrupt Processing Summary EE 5 60 5 8 5 Interrupt Acknowledge Bus Cycles 5 60 5 9 CNID SGICCIS oii T 5 60 5 9 1 Ch
376. of pulses as required to program the location This provides 100 program margin 11 Read the address to verify that it remains programmed 12 Clear the LAT bit in FEExCTL This disables the programming address and data latches 13 If more locations are to be programmed repeat steps 2 through 10 14 Reduce voltage applied to the VEpg to normal read level MOTOROLA FLASH EEPROM MODULE MC68HC16R1 916R1 8 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 8 3 5 1 Erasure The following steps are used to erase a flash EEPROM array Figure 8 2 is a flowchart of the erasure operation Refer to Figures A 22 and A 23 in APPENDIX A ELECTRI CAL CHARACTERISTICS for Vepe to Vpp relationships during erasure 1 2 3 Increase voltage applied to the Vepg pin to program erase verify level Set the ERAS bit and the LAT bit in FEExCTL This configures the module for erasure Perform a write to any valid address in the control block or array The data writ ten does not matter Set the ENPE bit in FEExCTL This applies the erase voltage to the array Delay the proper amount of time for one erase pulse Delay is specified by pa rameter topi Clear the ENPE bit in FEExCTL This turns off erase voltage to the array Delay while high voltage to array is turned off Delay is specified by parameter ter Read the entire array and control block to ensure all locations are
377. onding bits on the address bus during an access Provided other constraints deter mined by option register fields are also satisfied when a match occurs the associated chip select signal is asserted Table 5 24 shows BLKSZ 2 0 encoding MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 64 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 24 Block Size Encoding BLKSZ 2 0 Block Size Address Lines Compared 000 2 Kbytes ADDR 23 11 001 8 Kbytes ADDR 23 13 010 16 Kbytes ADDR 23 14 011 64 Kbytes ADDR 23 16 100 128 Kbytes ADDR 23 17 101 256 Kbytes ADDR 23 18 110 512 Kbytes ADDR 23 19 111 512 Kbytes ADDR 23 20 NOTES 1 ADDR 23 20 are the same logic level as ADDR19 during normal operation The chip select address compare logic uses only the most significant bits to match an address within a block The value of the base address must be an integer multiple of the block size Because the logic state of ADDR 23 20 follows that of ADDR19 in the CPU16 maxi mum block size is 512 Kbytes Because ADDR 23 20 follow the logic state of ADDR19 addresses from 080000 to F7FFFF are inaccessible After reset the MCU fetches the initialization routine from the address contained in the reset vector located beginning at address 000000 of program space To support bootstrap operation from reset the base address field in the
378. ontend for arbitration priority MC68HC16R1 916R1 CONFIGURABLE TIMER MODULE 7 MOTOROLA USER S MANUAL For More Information On This Product 12 17 Go to www freescale com Freescale Semiconductor Inc During arbitration the BIUSM provides the arbitration value specified by IARB 2 0 in BIUMCR and IARB3 in PWMSIC If the CTM7 wins arbitration it responds with a vec tor number generated by concatenating VECT 7 6 in BIUMCR and the six low order bits specified by the number of the submodule requesting service Thus for PWMSM8 in the CTM7 the six low order bits would be eight in decimal or 00100 in binary 12 10 8 PWM Frequency The relationship between the PWM output frequency fpyy and the MCU system clock frequency fsys is given by the following equation f sys Neeriop where is the divide ratio specified by the CLK 2 0 field in PWMSIC and Nperiop is the period specified by PWMA1 The minimum PWM output frequency achievable with a specified number of bits of res olution for a given system clock frequency is fsys Bits of Resolution 256 2 where Ncpsy is the CPSM divide ratio of two or three Similarly the maximum PWM output frequency achievable with a specified number of bits of resolution for a given system clock frequency is f sys Maximum Bits of Resolution CPSM 2 Tables 12 6 and 12 7 summarize the minimum pulse widths and frequency range
379. operation 11 3 3 1 Master Mode Setting the MSTR bit in SPCR selects master mode operation In master mode the SPI can initiate serial transfers but cannot respond to externally initiated transfers When the slave select input of a device configured for master mode is asserted a mode fault occurs When using the SPI in master mode include the following steps 1 Write to the MMCR MIVR and ILSPI Refer to 11 5 MCCI Initialization for more information 2 Write to the MPAR to assign the following pins to the SPI MISO MOSI and optionally SS MISO is used for serial data input in master mode and MOSI is used for serial data output Either or both may be necessary depending on the particular application SS is used to generate a mode fault in master mode If this SPI is the only possible master in the system the SS pin may be used for general purpose 3 Write to the MDDR to direct the data flow on SPI pins Configure the SCK serial clock and MOSI pins as outputs Configure MISO and optionally SS as in puts 4 Write to the SPCR to assign values for BAUD CPHA CPOL SIZE LSBF WOMP and SPIE Set the MSTR bit to select master operation Set the SPE bit to enable the SPI 5 Enable the slave device 6 Write appropriate data to the SPI data register to initiate the transfer When the SPI reaches the end of the transmission it sets the SPIF flag in the SPSR If the SPIE bit in the SPCR is set an interrupt request is
380. or More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc PORT F DATA 8 PORTF DDR FASTREF PF0 39 EDGE DETECT LOGIC PORTFE FLAGS Figure 5 23 Port F Block Diagram PORTF LEVEL 3 PORTF VECTOR 8 PORT F BLOCK Port F pin assignment register PFPAR fields determine the functions of pairs of port F pins Table 5 29 shows port F pin assignments Table 5 30 shows PFPAR pin functions In single chip mode BERR 0 during reset this register is set to 00 defining all port F pins to be I O pins In 8 and 16 bit expanded modes the state of DATA9 during reset determines the default value for PFPAR Table 5 29 Port F Pin Assignments PFPAR Field Port F Signal Alternate Signal PF 7 6 IRQ 7 1 PFPA2 PF 5 4 IRQ 5 4 PFPA1 PF 3 2 IRQ 3 2 PFPAO PF 1 0 IRQ1 FASTREF MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 USER S MANUAL For More Information On This Product Go to www freescale com MOTOROLA 5 73 Freescale Semiconductor Inc Table 5 30 PFPAR Pin Functions PFPAx Bits Port F Signal 00 I O pin without edge detect 01 Rising edge detect 10 Falling edge detect 11 Interrupt request When the corresponding pin is configured for edge detection a port F edge detect flag register PORTFE bit is set if an edge is detected PORTFE bits remain set regard less of the subsequen
381. or asserts the internal bus error signal BERR if no interrupt arbitration occurs during interrupt exception processing The assertion of BERR caus es the CPU16 to load the spurious interrupt exception vector into the program counter The spurious interrupt monitor cannot be disabled Refer to 5 8 Interrupts for further information For detailed information about interrupt exception processing refer to 4 13 Exceptions 5 4 5 Software Watchdog The software watchdog is controlled by the software watchdog enable SWE bit in SYPCR When enabled the watchdog requires that a service sequence be written to the software service register SWSR on a periodic basis servicing does not take place the watchdog times out and asserts the RESET signal Each time the service sequence is written the software watchdog timer restarts The sequence to restart the software watchdog consists of the following steps Write 55 to SWSR Write AA to SWSR MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 17 Go to www freescale com Freescale Semiconductor Inc Both writes must occur before timeout in the order listed Any number of instructions can be executed between the two writes Watchdog clock rate is affected by the software watchdog prescale SWP bit and the software watchdog timing SWT 1 0 field in SYPCR SWP determines system clock prescaling for the watch
382. or more MCCI sub modules request an interrupt simultaneously and are assigned the same interrupt re quest level the SPI submodule is given the highest priority and SCIB is given the lowest When an interrupt is requested which is at a higher level than the interrupt mask in the CPU status register the CPU initiates an interrupt acknowledge cycle During this cy cle the MCCI compares its interrupt request level to the level recognized by the CPU If a match occurs arbitration with other modules begins Interrupting modules present their arbitration number on the IMB and the module with the highest number wins The arbitration number for the MCCI is programmed into the interrupt arbitration IARB field of the MMCR Each module should be assigned a unique arbitration number The reset value of the IARB field is 0 which prevents the MCCI from arbitrating during an interrupt acknowledge cycle The IARB field should be initialized by system software to a value from F highest priority through 1 low est priority Otherwise the CPU identifies any interrupts generated as spurious and takes a spurious interrupt exception If the MCCI wins the arbitration it generates an interrupt vector that uniquely identifies the interrupting serial interface The six MSBs are read from the interrupt vector INTV field in the MCCI interrupt vector register MIVR The two LSBs are assigned by the MCCI according to the interrupting serial interface as indi
383. ource in the MCU When a reset occurs a bit corresponding to the reset type is set When multiple causes of reset occur at the same time more than one bit in RSR may be set The reset status register is updated by the reset control logic when the RESET signal is released Refer to APPENDIX D REGISTER SUMMARY MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 56 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 8 Interrupts Interrupt recognition and servicing involve complex interaction between the SCIM2 the CPU16 and a device or module requesting interrupt service This discussion pro vides an overview of the entire interrupt process Chip select logic can also be used to respond to interrupt requests Refer to 5 9 Chip Selects for more information 5 8 1 Interrupt Exception Processing The CPU16 handles interrupts as a type of asynchronous exception An exception is an event that preempts normal processing Exception processing makes the transition from normal instruction execution to execution of a routine that deals with an excep tion Each exception has an assigned vector that points to an associated handler rou tine These vectors are stored in a vector table located in the first 512 bytes of address bank 0 The CPU16 uses vector numbers to calculate displacement into the table Re fer to 4 13 Exceptions for more information 5 8 2 Interrupt Priority and R
384. ovided the external configu ration logic on the data bus is conditioned as shown in Figure 5 17 5 7 3 Operating Configuration Out of Reset The logic states of certain pins during reset determine SCIM2 operating configuration During reset the SCIM2 reads pin configuration from DATA 11 2 and DATAO internal module configuration from DATA 15 12 and basic operating information from BERR MODCLK DATA1 and BKPT These pins are normally pulled high internally during reset causing the MCU to default to a specific configuration However the user can drive the desired pins low during reset to achieve alternate configurations Basic operating options include system clock selection background mode disable enable and external bus configuration The SCIM2 supports three external bus configurations Fully expanded operation with a 24 bit address bus and 16 bit data bus with chip selects e Single chip operation with no external address and data bus Partially expanded operation with a 24 bit address bus and an 8 bit external data bus Table 5 15 shows the basic configuration options MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 42 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table 5 15 Basic Configuration Options Select Pin A ERE MODCLK Synthesized system clock External system clock BKPT Background mode disabled Background mode enabl
385. ower byte options MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 21 Go to www freescale com Freescale Semiconductor Inc Table D 13 BYTE Field Bit Encoding BYTE 1 0 Description 00 Disable 01 Lower byte 10 Upper byte 11 Both bytes R W 1 0 Read Write This field causes a chip select to be asserted only for a read only for a write or for both reads and writes Table D 14 shows the options Table D 14 Read Write Field Bit Encoding R W 1 0 Description 00 Disable 01 Read only 10 Write only 11 Read Write STRB Address Strobe Data Strobe This bit controls the timing for assertion of a chip select in asynchronous mode only Selecting address strobe causes the chip select to be asserted synchronized with address strobe Selecting data strobe causes the chip select to be asserted synchronized with data strobe Data strobe timing is used to create a write strobe when needed 0 Address strobe 1 Data strobe DSACK S3 0 Data Strobe Acknowledge This field specifies the source of DSACK in asynchronous mode as internally generated or externally supplied It also allows the user to adjust bus timing with internal DSACK generation by controlling the number of wait states that are inserted to optimize bus speed in a particular application Table D 15 shows the DSACK 3 0 field encoding The fast termination encoding 11
386. ows an external device to respond to accesses to the BEFLASH array address space or to bootstrap accesses The erased state of the shadow bits is one An erased module comes out of reset in STOP mode MOTOROLA BLOCK ERASABLE FLASH EEPROM MC68HC16R1 916R1 9 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 9 4 2 Bootstrap Operation After reset the CPU16 begins bootstrap operation by fetching initial values for its internal registers from IMB addresses 000000 through 000006 in program space These are the addresses of the bootstrap vectors in the exception vector table If BOOT 0 and STOP 0 in BFEMCR during reset the BEFLASH module is configured to respond to bootstrap vector accesses Vector assignments are shown in Table 9 1 Table 9 1 Bootstrap Vector Assignments EEPROM Bootstrap Word IMB Vector Address MCU Reset Vector Content BFEBSO 000000 Initial ZK SK and PK BFEBS1 000002 Initial PC BFEBS2 000004 Initial SP BFEBS3 000006 Initial IZ As soon as address 000006 has been read BEFLASH operation returns to normal and the module no longer responds to bootstrap vector accesses 9 4 3 Normal Operation The BEFLASH module allows a byte or aligned word read in one bus cycle Long word reads require two bus cycles The module checks function codes to verify address space access type Array access es are defined by the state of ASP
387. p counter Reading the register transfers the contents of the counter to the data bus while a write to the register loads the counter with a new value Overflow of the counter is defined to be the transition from FFFF to 0000 An overflow condition sets the counter overflow flag COF in the FCSM status interrupt control register FCSMSIC NOTE Reset presets the counter register to 0000 Writing 0000 to the counter register while the counter s value is F FFF does not set the COF flag and does not generate an interrupt request 12 6 2 FCSM Clock Sources The FCSM has eight software selectable counter clock sources including e Six CPSM prescaler outputs PCLK 1 6 e Rising edge on CTM2C input Falling edge on the CTM2C input The clock source is selected by the CLK 2 0 bits in FCSMSIC When the CLK 2 0 bits are being changed internal circuitry guarantees that spurious edges occurring on the 2 pin do not affect the FCSM The read only IN bit in FCSMSIC reflects the state of CTM2C This pin is Schmitt triggered and is synchronized with the system clock The maximum allowable frequency for a clock input CTM2C is fsys 4 MOTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 12 6 3 FCSM External Event Counting When an external clock source is selected the FCSM can act as an event counter simply by cou
388. place M68HC11 Direct Mode 4 11 4 7 Instruction Set su n ku Tessa 4 11 4 7 1 4 11 4 8 Comparison of CPU16 and M68HC11 CPU Instruction Sets 4 31 4 9 Instruction Format c 4 33 410 4 34 4 10 1 Microsequencer ee 4 35 4 10 2 4 35 410 3 Exec tior 4 35 4 11 656 ee un 4 36 4 11 1 Changes in Program Flow oro edi Eo dt ee o eed 4 36 4 12 Instr eti ni TIMIN Wie 4 36 4 13 EXCODIODS Rt a aE 4 37 4 13 1 Exception ccc coe i gunna eet ee ee eles 4 37 4 13 2 Exception Stack Frannie eoe epar tud Hec etn ix exam 4 38 4 13 3 Exception Processing Sequence 2 4 39 4 13 4 Types of Exceptions r 4 39 4 13 4 1 Asynchronous Exceptions 4 04221 4 39 4 13 4 2 Synchronous Exceptions 4 39 4 13 5 Multiple EXCODIOfIS dansin aaa f isu qa 4 40 4 13 6 RTIINSIUCHOM E Rau 4 40 4 14 Development
389. plies to both SCCR1A SCIA control register 1 and SCCR1B SCIB control register 1 11 4 1 SCI Registers The SCI programming model includes the MCCI global and pin control registers and eight SCI registers Each of the two SCI units contains two SCI control registers one status register and one data register Refer to D 6 9 SCI Control Register 0 D 6 11 SCI Status Register and D 6 12 SCI Data Register for register bit and field defini tions All registers may be read or written at any time by the CPU Rewriting the same value to any SCI register does not disrupt operation however writing a different value into an SCI register when the SCI is running may disrupt operation To change register val ues the receiver and transmitter should be disabled with the transmitter allowed to fin ish first The status flags in the SCSR may be cleared at any time When initializing the SCI set the transmitter enable TE and receiver enable RE bits in SCCR1 last A single word write to SCCR1 can be used to initialize the SCI and en able the transmitter and receiver 11 4 1 1 SCI Control Registers SCCRO contains the baud rate selection field The baud rate must be set before the SCI is enabled The CPU16 can read and write this register at any time MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL For More Information On This Product 11 13 Go to www freescale com Freescale Semiconductor Inc TRANSMITTER
390. ply voltage inputs 116 131 VppA 26 ADC ADC analog supply voltage input Clock synthesizer power supply in put If Vppsyn is grounded the MCU V MODCLK h IM2 DESSEN 28 2 will operate at the frequency of the signal input on the EXTAL pin VEBEi 132 BEFLASH Block erasable flash EEPROM pro gram erase supply voltage input FLASH1 Flash EEPROM program erase sup VrPE2 a FLASH2 voltage inputs d VRH 18 ADC Analog to digital converter high and _ VRL 17 low voltage reference inputs 13 28 34 64 T SS 66 Digital ground reference 100 115 130 Vssa 25 ADC ADC analog ground reference VsssyYn 60 SCIM2 Clock synthesizer ground reference VsTBY 56 SRAM SRAM standby voltage supply input XFC 62 m SCIM2 Clock synthesizer filter connection XTAL 57 SCIM2 Crystal oscillator output NOTES 1 CTM7 pins that can be used for general purpose I O are not grouped into ports like PORTMC on the MCCI and PORTADA on the ADC Instead the I O capability of the pin s associated with each CTM7 submodule is con trolled individually by bits in the submodule s status interrupt control register MC68HC16R1 916R1 OVERVIEW MOTOROLA USER S MANUAL For More Information On This Product 3 15 Go to www freescale com Freescale Semiconductor Inc 3 5 CPU16 Memory Mapping Each member of the M68HC16 family
391. ppsyn and Vss and variation in crystal oscillator frequency in crease the Jak percentage for a given interval When clock jitter is a critical constraint on control system opera tion this parameter should be measured during functional testing of the final system MOTOROLA ELECTRICAL CHARACTERISTICS MC68HC16R1 916R1 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table A 5 DC Characteristics VbpsyN 5 0 Vdc 5 Vos 0 Vdc Ty Ti to Ty Num Characteristic Symbol Min Max Unit 1 Input High Voltage Vin 0 7 Vpp O 3 V 2 Input Low Voltage Vy Vss 0 3 0 2 Vpp V 3 Input Hysteresis 2 Vuvs 0 5 V Input Leakage Current 4 4 Vin Vpp or Vss Allinput only pins except ADC pins 59 29 MA 5 High Impedance Off State Leakage Current 5 Dam we Vin Vss All input output and output pins 02 i H g CMOS Output High Voltage 6 7 V _ 10 0 pA Group 1 2 4 input output all output pins OH DD CMOS Output Low Voltage 8 7 VoL 0 2 V loi 10 0 pA Group 1 2 4 input output and all output pins Output High Voltage amp 7 E _ 8 loH 0 8 mA Group 1 2 4 input output and all output pins 98 Y Output Low Voltage 9 loi 1 6 mA Group1 I O Pins CLKOUT FREEZE QUOT IPIPEO V LI 0 4 V lo 5 3 mA Group 2 and Group 4 I
392. preset to 0001 and starts to count from that value The counter can be read at any time from the PWMC register without affecting its value Writing to the counter has no effect 12 10 4 PWMSM Period Registers and Comparator The period section of the PWMSM consists of two 16 bit period registers PWMA1 and 2 and one 16 bit comparator PWMA holds the current PWM period value 1 holds the next PWM period value The next period of the output PWM signal is established by writing a value into PWMA1 PWMA2 acts as a double buffer for PWMAt allowing the contents of PWMA1 to be changed at any time without af fecting the period of the current output signal PWMA2 is not user accessible PWMA1 can be read or written at any time The new value in PWMAT is transferred to PWMA2 on the next full cycle of the PWM output or when a one is written to the LOAD bit in PWMSIC The comparator continuously compares the contents of PWMA2 with the value in the PWMSM counter When a match occurs the state sequencer sets the output flip flop and resets the counter to 0001 Period values 0000 and 0001 are special cases When PWMA contains 0000 an output period of 65536 PWM clock periods is generated When PWMA contains 0001 a period match occurs on every PWM clock period The counter never increments beyond 0001 and the output level never changes MOTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 16 For More Information O
393. pressed as follows Minimum External Clock Period Minimum External Clock High Low Time 50 Percentage Variation of External Clock Input Duty Cycle Table 5 2 shows 16 78 MHz clock control multipliers for all possible combinations of SYNCR bits To obtain clock frequency find counter modulus in the leftmost column then multiply the reference frequency by the value in the appropriate prescaler cell Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for maximum allowable clock rate Table 5 3 shows actual 16 78 MHz clock frequencies for the same combinations of SYNCR bits To obtain clock frequency find counter modulus in the leftmost column then refer to appropriate prescaler cell Refer to APPENDIX A ELECTRICAL CHAR ACTERISTICS for maximum system frequency MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 9 Go to www freescale com Freescale Semiconductor Inc Table 5 2 16 78 MHz Clock Control Multipliers Shaded cells represent values that exceed 16 78 MHz specifications Prescalers Modulus W X 00 W X 01 W X 10 W X 11 fyco 2 x Value fyco Value fyco 2 x Value fuco Value Y Slow Fast Slow Fast Slow Fast Slow Fast 000000 4 03125 8 625 16 125 32 25 000001 8 0625 16 125 32 25 64 5 000010 12 093
394. programming voltage Delay long enough for one programming pulse to occur topulse Clear ENPE to remove programming voltage Delay while high voltage is turning off typrog Read the location just programmed If the value read is all zeros proceed to step 9 If not calculate a new value for topuise and repeat steps 4 through 7 until either the location is verified or the total programming time torogmax has been exceeded If torogmax has been exceeded the location may be bad and should not be used If the location is programmed calculate tomargin and repeat steps 4 through 7 If the location does not remain programmed the location is bad Clear VFPE and LAT If there are more locations to program repeat steps 2 through 10 Turn off VEpgok reduce voltage on Vrpgoy pin to Vpp Read the entire array to verify that all locations are correct If any locations are incorrect the array is bad MC68HC16R1 916R1 BLOCK ERASABLE FLASH EEPROM MOTOROLA USER S MANUAL For More Information On This Product 9 5 Go to www freescale com Freescale Semiconductor Inc 9 4 4 2 Erasure Sequence Use the following procedure to erase the BEFLASH Figures A 22 and A 23 in APPENDIX A ELECTRICAL CHARACTERISTICS for Vepe to Vpp relationships during erasure PrO Po s XO OO Turn on Vepe apply program erase voltage to pin Set initial value of tepulse 10 temin Set LAT VFPE and ERAS bits to configure th
395. protection block provides bus and software watchdog monitors The chip select block provides five general purpose chip select signals and two emulation support chip select signals The general purpose chip select signals have associated base address registers and option registers The external bus interface handles the transfer of information between IMB modules and external address space The system test block incorporates hardware necessary for testing the MCU It is used to perform factory tests and its use in normal applications is not supported The SCIM2 has three basic operating modes 16 bit expanded mode in which the SCIM2 provides a 24 bit external address bus and a 16 bit external data bus eight general purpose chip select lines a boot ROM chip select line and seven interrupt request inputs The bus control pins the chip select pins and the interrupt request pins can be configured as general purpose 1 ports In addition two emulation chip select lines are available CSE and CSM The CSE line can be used to select an external port replacement unit and the CSM line can be used to select an external ROM emulation device 8 bit expanded mode in which the SCIM2 provides a single general purpose I O port a 24 bit external address bus an 8 bit external data bus seven general pur pose chip select lines a boot ROM chip select line and seven interrupt request lines The bus control pins the chip select pins and the
396. py input for low power standby operation e Power down status flag denotes loss of Vstpy during low power standby opera tion MC68HC16R1 916R1 OVERVIEW MOTOROLA USER S MANUAL For More Information On This Product 3 1 Go to www freescale com Freescale Semiconductor Inc 3 1 4 Masked ROM Module MRM MC68HC16R1 Only 48 Kbyte array accessible as bytes or words User selectable default base address User selectable bootstrap ROM function User selectable ROM verification code 3 1 5 Flash EEPROM Modules FLASH MC68HC916R1 Only 16 Kbyte and 32 Kbyte flash EEPROM modules Bulk erase and byte word program with 12 volt external program erase voltage Modules can be mapped to provide 48 Kbytes of contiguous address space 3 1 6 Block Erasable Flash EEPROM BEFLASH MC68HC916R1 Only 2 Kbyte block erasable flash EEPROM Bulk block erase and byte word program with 12 volt external program erase volt age 3 1 7 Analog to Digital Converter ADC Eight channels eight result registers three result alignment modes Eight automated modes 3 1 8 Multichannel Communication Interface MCCI Two channels of enhanced SCI UART One channel of SPI 3 1 9 Configurable Timer Module 7 CTM7 One 16 bit free running counter submodule FCSM One 16 bit modulus counter submodule MCSM Six single action submodules SASMs Two double action submodules DASMs Two pulse width submodules PWMSMs
397. r conversion is complete The registers can be accessed from the IMB under ABIU control Each register can be read from three different addresses in the ADC memory map The format of the result data depends on the address from which it is read Table 10 9 shows the three types of formats MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For More Information On This Product 10 13 Go to www freescale com Freescale Semiconductor Inc Table 10 9 Result Register Formats Result Data Format Description Conversion result is unsigned right justified data Bits 9 0 are used for 10 bit resolution bits 7 0 are used for 8 bit conversion bits 9 8 are zero Bits 15 10 always return zero when read Unsigned right justified format Conversion result is signed left justified data Bits 15 6 are used for 10 bit resolution bits 15 8 are used for 8 bit conversion bits 7 6 are zero Although the ADC is unipolar it is assumed that the zero point is VRH VRL 2 when this format is used The value read from the register is an offset two s complement number for positive input bit 15 equals zero for negative input bit 15 equals one Bits 5 0 always return zero when read Signed left justified format Conversion result is unsigned left justified data Bits 15 6 are used for 10 bit resolution bits 15 8 are used for 8 bit conversion bits 7 6 are zero Bits 5 0 always return zero when read
398. r unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer MOTOROLA INC 1997 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Paragraph Title Page SECTION 1 INTRODUCTION SECTION 2 NOMENCLATURE 2 1 Symbols and Operators ae 2 1 2 2 CPU16 Register Mnemonics 2 2 2 3 Pin and Signal Mnemonics eiie rone ea c 2 3 2 4 FlegiSter MhOermoris su eie rea dii co rb an Q me sx epa ee RR RE ERREUR 2 5 2 5 Conventions TH 2 8 SECTION 3 OVERVIEW 3 1 MC68HC16R1 916R1 MCU Features 3 1 3 1 1 Central Processor Unit CPU B iiri reti meii 3 1 3 1 2 Single
399. racy 10 2 3 Analog Supply Pins Pins VppA VssA supply power to analog circuitry associated with the RC DAC Other circuitry in the ADC is powered from the digital power bus pins Vpp and Dedicated analog power supplies are necessary to isolate sensitive ADC circuitry from noise on the digital power bus 10 3 Programmer s Model The ADC module is mapped into 32 words of address space Five words are control status registers one word is digital port data and 24 words provide access to the re sults of AD conversion eight addresses for each type of converted data Two words are reserved for expansion The ADC module base address is determined by the value of the MM bit in the single chip integration module configuration register SCIMCR The base address is normal ly FFF700 Internally the ADC has both a differential data bus and a buffered IMB data bus Reg isters not directly associated with conversion functions such as the module configu ration register the module test register and the port data register reside on the buffered bus while conversion registers and result registers reside on the differential bus Registers that reside on the buffered bus are updated immediately when written How ever writes to ADC control registers abort any conversion in progress 10 4 ADC Bus Interface Unit The ADC is designed to act as a slave device on the intermodule bus The ADC bus interface unit ABIU provides IMB
400. ransfer to XK IX TSY Adds 2 to SK SP before transfer to YK IY TXS Subtracts 2 from XK IX before transfer to SK SP TXY Transfers XK field to YK field TYS Subtracts 2 from YK IY before transfer to SK SP TYX Transfers YK field to XK field WAI Waits indefinitely for interrupt or reset Generates a different stack frame NOTES 1 Motorola assemblers automatically translate ASL mnemonics MOTOROLA MC68HC16R1 916R1 4 32 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 9 Instruction Format CPU16 instructions consist of an 8 bit opcode that can be preceded by an 8 bit prebyte and followed by one or more operands Opcodes are mapped in four 256 instruction pages Page 0 opcodes stand alone Page 1 2 and 3 opcodes are pointed to by a prebyte code on page 0 prebytes are 17 page 1 27 page 2 and 37 page 3 Operands can be four bits eight bits or sixteen bits in length Since the CPU16 fetches 16 bit instruction words from even byte boundaries each instruction must contain an even number of bytes Operands are organized as bytes words or a combination of bytes and words Oper ands of four bits are either zero extended to eight bits or packed two to a byte The largest instructions are six bytes in length Size order and function of operands are evaluated when an instruction is decoded A page 0 opcode and an 8 bit operand ca
401. ration Default Function Alternate Function Pin s Affected Select Pin Pin Held High Pin Held Low CSBOOT N A CSBOOT 8 Bit CSBOOT 8 Bit BR CSO CSO BR FCO CSS PCO CS3 FCO FC1 PC1 FC1 FC1 FC2 CS5 PC2 CS5 FC2 ADDR19 CS6 PC3 ADDR20 CS7 PC4 ADDR21 CS8 PC5 N A CS 10 6 CS 10 6 ADDR22 CS9 PC6 ADDR23 CS10 ECLK DSACKO PEO DSACKO PEO DSACK1 PE1 DSACK1 PE1 AVEC PE2 AVEC PE2 PE3 PE3 PE3 DS PE4 DATAB DS PE4 AS PE5 AS PE5 SIZ0 PE6 SIZO PE6 SIZ1 PE7 SIZ1 PE7 FASTREF PFO FASTREF PFO IRQ 7 1 PF 7 1 DUNS IRQ 7 1 PF 7 1 BGACK CSE 1 BGACK BGACK BG CSM N A BG BG NOTES 1 These pins have only one reset configuration in 8 bit expanded mode MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 48 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 5 7 3 5 Single Chip Mode Single chip operation is selected when BERR 0 during reset BERR can be tied low permanently to select this configuration In single chip configuration pins DATA 15 0 are configured as two 8 bit I O ports ports G and H ADDR 18 3 are configured as two 8 bit I O ports ports A and B There is no external data bus path Expanded mode con figuration options are not available I O ports C E F G and are always se lected ADDR 2 0 come out of reset in a high impedance state After reset clearing the ABD bit in SCIMCR en
402. re the bank portions of 20 bit concatenated bank byte addresses used in the CPU16 linear memory management scheme All extension fields except EK correspond directly to a register XK YK and ZK extend registers IX IY and IZ PK extends the PC and SK extends the SP EK holds the four MSB of the 20 bit address used by the extended addressing mode 4 2 7 Multiply and Accumulate Registers The multiply and accumulate MAC registers are part of a CPU submodule that per forms repetitive signed fractional multiplication and stores the cumulative result These operations are part of control oriented digital signal processing There are four MAC registers Register H contains the 16 bit signed fractional multipli er Register contains the 16 bit signed fractional multiplicand Accumulator M is a specialized 36 bit product accumulation register XMSK and YMSK contain 8 bit mask values used in modulo addressing The CPU16 has a special subset of signal processing instructions that manipulate the MAC registers and perform signal processing calculations 4 3 Memory Management The CPU16 provides a 1 Mbyte address space There are 16 banks within the address space Each bank is made up of 64 Kbytes addressed from 0000 to FFFF Banks are selected by means of the address extension fields associated with individual CPU16 registers In addition address space can be split into discrete 1 Mbyte program and data spaces by externally decoding the MCU
403. rfaced to almost any existing synchronous serial peripheral MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 11 3 4 1 CPHA 0 Transfer Format Figure 11 3 is a timing diagram of an eight bit MSB first SPI transfer in which CPHA equals zero Two waveforms are shown for SCK one for CPOL equal to zero and an other for CPOL equal to one The diagram may be interpreted as a master or slave timing diagram since the SCK MISO and MOSI pins are directly connected between the master and the slave The MISO signal shown is the output from the slave and the MOSI signal shown is the output from the master SS line is the chip select input to the slave SCK CYCLE 2 2 3 5 7 MOSI MASTER s X3 X2 X w Y s Xs Xs X3 Yi MISO FROM SLAVE S TO SLAVE 0 SPI TRANSFER Figure 11 3 0 SPI Transfer Format For a master writing to the SPDR initiates the transfer For a slave the falling edge of SS indicates the start of a transfer The SCK signal remains inactive for the first half of the first SCK cycle Data is latched on the first and each succeeding odd clock edge and the SPI shift register is left shifted on the second and succeeding even c
404. rformed by means of serial contention between values stored in indi vidual module interrupt arbitration IARB fields Each module that can make an inter rupt service request including the SCIM2 has an IARB field in its configuration register IARB fields can be assigned values from 960000 to 961111 In order to imple ment an arbitration scheme each module that can request interrupt service must be assigned a unique non zero IARB field value during system initialization Arbitration priorities range from 960001 lowest to 961111 highest if the CPU16 recognizes an interrupt service request from a source that has an IARB field value of 960000 a spurious interrupt exception is processed MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 58 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc WARNING Do not assign the same arbitration priority to more than one module When two or more IARB fields have the same nonzero value the CPU16 interprets multiple vector numbers at the same time with unpredictable consequences Because the EBI manages external interrupt requests the SCIM2 IARB value is used for arbitration between internal and external interrupt requests The reset value of IARB for the SCIM2 is 1111 and the reset IARB value for all other modules is 0000 Although arbitration is intended to deal with simultaneous requests of the same interrupt level
405. rial shifter FE NF and PF cannot occur at the same time as OR When the CPU16 reads SCSR and SCDR in sequence it acquires status and data and also clears the status flags Reading SCSR acquires status and arms the clearing mechanism Reading SCDR acquires data and clears SCSR When RIE in SCCR1 is set an interrupt request is generated whenever RDRF is set Because receiver status flags are set at the same time as RDRF they do not have separate interrupt enables 11 4 5 7 Idle Line Detection During a typical serial transmission frames are transmitted isochronally and no idle time occurs between frames Even when all the data bits in a frame are logic ones the start bit provides one logic zero bit time during the frame An idle line is a sequence of contiguous ones equal to the current frame size Frame size is determined by the state of the M bit in SCCR1 The SCI receiver has both short and long idle line detection capability Idle line detec tion is always enabled The idle line type ILT bit in SCCR1 determines which type of detection is used When an idle line condition is detected the IDLE flag in SCSR is set For short idle line detection the receiver bit processor counts contiguous logic one bit times whenever they occur Short detection provides the earliest possible recognition of an idle line condition because the stop bit and contiguous logic ones before and after it are counted For long idle line detection the receiv
406. ring and Grounding 10 16 10 8 4 Accommodating Positive Negative Stress Conditions 10 18 10 8 5 Analog Input Considerations 10 20 10 8 6 Analog Input Pins eet 10 22 10 8 6 1 Settling Time for the External Circuit 10 23 10 8 6 2 Error Resulting from Leakage 10 24 SECTION 11 MULTICHANNEL COMMUNICATION INTERFACE 11 1 GCN alt TET T REPE 11 1 11 2 Registers and Address 11 2 11 2 1 MCCI Global Registers ether ER Saee 11 2 11 2 1 1 Low Power Stop Mode 11 2 11 2 1 2 Privilege Levels 11 3 11 2 1 3 MCCI Interrupts idu Me s te 11 3 11 2 2 Pin Control and General Purpose I O 11 4 MC68HC16R1 916R1 MOTOROLA USER S MANUAL ix For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page 11 3 Serial Peripheral Interface SPI 11 4 11 3 1 SPIRegISIerS u a sa RT 11 6 11 3 1 1 SPI Control Register SPOR 1
407. rite collision errors When awrite collision occurs the WCOL bit in the SPSR is set To clear WCOL read the SPSR while WCOL is set and then either read the SPDR either before or after SPIF is set or write the SPDR after SPIF is set Writing the SPDR before SPIF is set results in a second write collision error This process clears SPIF as well as WCOL 11 3 9 Mode Fault When the SPI system is configured as a master and the SS input line is asserted a mode fault error occurs and the MODF bit in the SPSR is set Only an SPI master can experience a mode fault error caused when a second SPI device becomes a master and selects this device as if it were a slave To avoid latchup caused by contention between two pin drivers the MCU does the fol lowing when it detects a mode fault error Forces the MSTR control bit to zero to reconfigure the SPI as a slave Forces the SPE control bit to zero to disable the SPI system Sets the MODF status flag and generates an SPI interrupt if SPIE 1 Clears the appropriate bits in the MDDR to configure all SPI pins except the SS pin as inputs After correcting the problems that led to the mode fault clear MODF by reading the SPSR while MODF is set and then writing to the SPCR Control bits SPE and MSTR may be restored to their original set state during this clearing sequence or after the MODF bit has been cleared Hardware does not allow the user to set the SPE and MSTR bits while MODF is a logic one
408. rites have no effect Refer to D 3 Standby RAM Module for register block address map and register bit field definitions 6 2 SRAM Array Address Mapping Base address registers RAMBAH and RAMBAL are used to specify the SRAM array base address in the memory map RAMBAH and RAMBAL can only be written while the SRAM is in low power stop mode RAMMCR STOP 1 and the base address lock RAMMCR RLCK 0 is disabled RLCK can be written once only to a value of one subsequent writes are ignored This prevents accidental remapping of the array NOTE In the CPU16 ADDR 23 20 follow the logic state of ADDR19 The SRAM array must not be mapped to addresses 080000 7FFFFF which are inaccessible to the CPU16 If mapped to these addresses the array remains inaccessible until a reset occurs or it is remapped outside of this range MC68HC16R1 916R1 STANDBY RAM MODULE MOTOROLA USER S MANUAL For More Information On This Product 6 1 Go to www freescale com Freescale Semiconductor Inc 6 3 SRAM Array Address Space Type RASP 1 0 in RAMMCR determine the SRAM array address space type The SRAM module can respond to both program and data space accesses or to program space accesses only Because the CPU16 operates in supervisor mode only RASP1 has no effect Table 6 1 shows RASP 1 0 encodings Table 6 1 SRAM Array Address Space Type RASP 1 0 Space Program and data accesses x1 Program access only Refer to 5 5 1
409. rnally input clock frequency on both slow and fast reference frequency devices when fsys is equal to the system clock frequency Divide Ratio Specified by SWP SWTT 1 0 Timeout Period sys HME Halt Monitor Enable 0 Halt monitor is disabled 1 Halt monitor is enabled BME Bus Monitor External Enable 0 Disable bus monitor for external bus cycles 1 Enable bus monitor for external bus cycles MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 14 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc BMT 1 0 Bus Monitor Timing This field selects the bus monitor timeout period Refer to Table D 7 Table D 7 Bus Monitor Timeout Period BMTT 1 0 Bus Monitor Timeout Period 00 64 System clocks 01 32 System clocks 10 16 System clocks 11 8 System clocks D 2 16 Periodic Interrupt Control Register PICR Periodic Interrupt Control Register YFFA22 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 PIRQL 2 0 PIV 7 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 PICR sets the interrupt level and vector number for the periodic interrupt timer PIT Bits 10 0 can be read or written at any time Bits 15 11 are unimplemented and always read zero PIRQL 2 0 Periodic Interrupt Request Level This field determines the priority of periodic interrupt requests A value of 000 disables PIT interrupts PIV 7
410. ro to logic level one Negated means that an asserted signal changes logic state An active low signal changes from logic level zero to logic level one when negated and an active high signal changes from logic level one to logic level zero A specific mnemonic within a range is referred to by mnemonic and number A15 is bit 15 of Accumulator ADDR7 is line 7 of the address bus CSORO is chip select option register 0 A range of mnemonics is referred to by mnemonic and the numbers that define the range VBR 4 0 are bits four to zero of the Vector Base Register CSOR O0 5 are the first six chip select option registers Parentheses are used to indicate the content of a register or memory location rather than the register or memory location itself For example A is the content of Accumulator A M M 1 is the content of the word at address LSB means least significant bit or bits MSB means most significant bit or bits References to low and high bytes are spelled out LSW means least significant word or words MSW means most significant word or words ADDR is the address bus ADDR 7 0 are the eight LSB of the address bus DATA is the data bus DATA 15 8 are the eight MSB of the data bus MOTOROLA NOMENCLATURE MC68HC16R1 916R1 2 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 3 OVERVIEW This section provides general information on MC68HC16R1and M
411. routines Many DSP algorithms require extensive data address manipulation To increase throughput the CPU16 performs effective address calculations and data prefetches during MAC operations In addition the MAC unit provides modulo addressing to im plement circular DSP buffers efficiently Refer to the CPU16 Reference Manual CPU16RM AD for detailed information con cerning the MAC unit and execution of DSP instructions MOTOROLA MC68HC16R1 916R1 4 46 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 5 SINGLE CHIP INTEGRATION MODULE 2 This section is an overview of the single chip integration module 2 SCIM2 Refer to the SCIM Reference Manual SCIMRM AD for a comprehensive discussion of SCIM2 capabilities Refer to D 2 Single Chip Integration Module 2 for information concern ing the SCIM2 address map and register structure 5 1 General The single chip integration module 2 SCIM2 consists of six submodules that with minimum of external devices control system startup initialization configuration and the external bus Figure 5 1 shows a block diagram of the SCIM2 The system configuration block controls MCU configuration and operating mode The system clock generates clock signals used by the SCIM2 other IMB modules and external devices In addition a periodic interrupt generator supports execution of time critical control routines The system
412. rr BSET Set Bit s Mask 2 IND8 X 1709 mm ff 8 A 0 A IND8 Y 1719 mm ff 8 IND8 Z 1729 mm ff 8 IND16 X 09 mm gggg 8 IND16 Y 19 mm gggg 8 IND16 Z 29 mm gggg 8 EXT 39 mm hh II 8 BSETW Set Bit s in Word M M 1 Mask IND16 X 2709 999g 10 A 0 A 1 mmmm IND16 Y 2719 0099 10 mmmm IND16 Z 2729 999g 10 mmmm EXT 2739 hh Il 10 mmmm MOTOROLA MC68HC16R1 916R1 4 16 USER S MANUAL For More Information On This Product Go to www freescale com Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode Cycles 5 MV H EV 2 V C BSR Branch to Subroutine PK PC 2 PK PC REL8 36 rr 10 Push PC SK SP 2 gt SK SP Push CCR SK SP 2 gt SK SP PK PC Offset gt PK PC BVC2 Branch if Overflow If V 0 branch REL8 rr 6 2 Clear 52 Branch if Overflow Set If V 1 branch REL8 9 rr 6 2 Compare A to B A INH 371B 2 A A CLR Clear a Byte in 00 gt M IND8 X 05 ff 4 0 1 0 0 Memory IND8 Y 15 ff 4 IND8 Z 25 ff 4 IND16 X 1705 gggg 6 IND16 Y 1715 9999 6 IND16 2 1725 0999 6 1735 hh Il 6 CLRA Clear A 00 gt INH 3705 2 0 1 0 0 CLRB Clear B
413. rrupt control register DASMSIC Table 12 3 shows the different DASM operating modes Table 12 3 DASM Modes of Operation MODE 3 0 Mode Description of Mode 0000 DIS Disabled Input pin is high impedance IN gives state of input pin 0001 IPWM das measurement Capture on leading edge and the trailing edge 0010 IPM Input period measurement Capture two consecutive rising falling edges 0011 IC Input capture Capture when the designated edge is detected Output compare flag set on B compare Generate leading and trailing edges of 0109 an output pulse and set the flag Output compare flag set on A and B compare Generate leading and trailing 0101 OCAB edges of an output pulse and set the flag 0110 Reserved 0111 Reserved TEN OPWM Output pulse width modulation Generate continuous PWM output with 7 9 11 12 13 14 15 or 16 bits of resolution The DASM is composed of two timing channels A and B an output flip flop an input edge detector some control logic and an interrupt interface All control and status bits are contained in DASMSIC MOTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 12 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Channel A consists of one 16 bit data register and one 16 bit comparator To the user channel B also appears to consist of one 16 bit data register a
414. rrupt request is acknowledged even when there is only a single request pending For an interrupt to be serviced the appropriate IARB field must have a non zero value If an interrupt request from a module with an IARB field value of 960000 is recognized the CPU16 processes a spurious interrupt exception Because the SCIM2 routes external interrupt requests to the CPU16 the SCIM2 IARB field value is used for arbitration between internal and external interrupts of the same priority The reset value of for the SCIM2 is 961111 and the reset IARB value for all other modules is 960000 which prevents SCIM2 interrupts from being discarded during initialization Refer to 5 8 Interrupts for a discussion of interrupt arbitration 5 2 3 Single Chip Operation Support The SCIMCR contains three bits that support single chip operation Setting the CPU development support disable bit CPUD disables places in a high impedance state the instruction tracking pins whenever the FREEZE signal is not asserted The instruction tracking pins on CPU16 based MCUs are IPIPE1 and IPIPEO When CPUD is cleared to zero the instruction tracking pins operate normally Setting the address bus disable bit ABD disables ADDR 2 0 by placing the pins in a high impedance state During single chip operation the ADDR 23 3 pins are configured for discrete output or input output and ADDR 2 0 should normally be disabled Setting the R W disable bit RWD disables the R
415. rs 6 8 10 12 14 16 S ey 8y 10 12 14V 16 DATB CTM7 SASM B Data Registers 6 8V 10 12 14 16 SIGHI ROM Signature High Register SIGLO ROM Signature Low Register SCCRO A B MCCI SCI Control 0 Registers A B SCCRI1 A B MCCI SCI Control 1 Registers A B SCDR A B MCCI SCI Data Registers A B SCDR A B MCCI SCI Status Registers A B SPCR MCCI SPI Control Register SPDR MCCI SPI Data Register SPSR MCCI SPI Status Register SWSR SCIM2 Software Watchdog Service Register SYNCR SCIM2 Clock Synthesizer Control Register SYPCR SCIM2 System Protection Control Register TCNT SCIM2 Timer Counter Register TSTMSRA SCIM2 Test Master Shift Register A TSTMSRB SCIM2 Test Master Shift Register B TSTRC SCIM2 Test Repetition Count Register TSTSC SCIM2 Test Shift Count Register MC68HC16R1 916R1 NOMENCLATURE MOTOROLA USER S MANUAL For More Information On This Product 2 7 Go to www freescale com Freescale Semiconductor Inc 2 5 Conventions Logic level one is the voltage that corresponds to a Boolean true 1 state Logic level zero is the voltage that corresponds to a Boolean false 0 state Set refers specifically to establishing logic level one on a bit or bits Clear refers specifically to establishing logic level zero on a bit or bits Asserted means that a signal is in active logic state An active low signal changes from logic level one to logic level zero when asserted and an active high signal changes from logic level ze
416. rs background debugging mode the FREEZE signal is asserted The type of response is determined by the value of the FRZ 1 0 field in the ADCMCR Table 10 1 shows the different ADC responses to FREEZE assertion Table 10 1 FRZ Field Selection FRZ 1 0 Response Ignore FREEZE Reserved Finish conversion then freeze Freeze immediately When the ADC freezes the ADC clock stops and all sequential activity ceases Con tents of control and status registers remain valid while frozen When the FREEZE sig nal is negated ADC activity resumes If the ADC freezes during a conversion activity resumes with the next step in the con version sequence However capacitors in the analog conversion circuitry discharge while the ADC is frozen as a result the conversion will be inaccurate Refer to 4 14 4 Background Debug Mode for more information 10 6 Analog Subsystem The analog subsystem consists of a multiplexer sample capacitors a buffer amplifier an RC DAC array and a high gain comparator Comparator output sequences the successive approximation register SAR The interface between the comparator and the SAR is the boundary between ADC analog and digital subsystems MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC16R1 916R1 10 4 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 10 6 1 Multiplexer The multiplexer selects one of 16 sources for conversion Eight so
417. s DATA 15 0 Data bus DS Data strobe DSACK 1 0 Data and size acknowledge DSCLK Development serial clock DSI Development serial input DSO Development serial output ECLK 6800 Bus clock EXTAL External crystal oscillator connection FASTREF Fast slow reference select FC 2 0 Function codes FREEZE Freeze HALT Halt IPIPE 1 0 Instruction pipeline MUX IRQ 7 1 Interrupt request MISO Master in slave out MODCLK Clock mode select MOSI Master out slave in PADA 7 0 ADC I O port A NOMENCLATURE For More Information On This Product Go to www freescale com MOTOROLA 2 3 MOTOROLA 2 4 Freescale Semiconductor Inc Mnemonic Register PC 6 0 SCIM2 I O port C PE 7 0 SCIM2 I O port E PF 7 0 SCIM2 I O port F PMC 7 0 MCCI port QUOT Quotient out RESET Reset R W Read Write RXDA SCI A Receive Data RXDB SCI B Receive Data SCK Serial clock SPI SIZ 1 0 Size SS Slave select TSC Three state control TXDA SCI A Transmit Data TXDB SCI B Transmit Data Vnu Vni A D Reference voltage XFC External filter capacitor connection XTAL External crystal oscillator connection NOMENCLATURE For More Information On This Product Go to www freescale com MC68HC16R1 916R1 USER S MANUAL 2 4 Register Mnemonics Freescale Semiconductor Inc For More Information On This Product Go to www freescale com M
418. s Shadow registers are programmed or erased in the same manner as locations in the BEFLASH array using the address of the corresponding control registers When a shadow register is programmed the data is not written to the corresponding control register The new data is not copied into the control register until the next reset The contents of shadow registers are erased whenever the BEFLASH array is erased MC68HC16R1 916R1 BLOCK ERASABLE FLASH EEPROM MOTOROLA USER S MANUAL For More Information On This Product 9 1 Go to www freescale com Freescale Semiconductor Inc Configuration information is specified and programmed independently of the BEFLASH array After reset registers in the control block that contain writable bits can be modified Writes to these registers do not affect the associated shadow register Certain registers are writable only when the LOCK bit in BFEMCR is disabled or when the STOP bit in BFEMCR is set These restrictions are noted in the individual register descriptions 9 3 BEFLASH Array The base address registers specify the starting address of the BEFLASH array A default base address can be programmed into the base address shadow registers The array base address must be on a 2 Kbyte boundary Because the states of ADDR 23 20 follow the state of ADDR19 addresses in the range 080000 to F7FFFF cannot be accessed by the CPU16 If the BEFLASH array is mapped to these addresses the system must be reset befor
419. s available from the PWMSM based on the CPSM system clock divide ratio and a system clock frequency of 16 78 MHz Table 12 6 PWM Pulse and Frequency Ranges in Hz Using 2 Option 16 78 MHz fsys Minimum Bits of Resolution Divide Pulse Ratio Width 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2 0 119 us 128 256 512 1024 2048 4096 8192 16384 32768 65 5k 131k 262k 524k 1049k 2097k 4195k 4 0 238 us 64 128 256 512 1024 2048 4096 8192 16384 32768 65 5k 131k 262k 524k 1049k 2097k 8 0 477 us 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65 5k 131k 262k 524k 1049k 16 0 954 us 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65 5k 131k 262k 524k 32 1 91 us 8 0 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65 5k 131k 262k 64 3 81 us 4 0 8 0 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65 5k 131k 128 7 63 us 2 0 4 0 8 0 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65 5k 512 30 5 us 0 5 1 0 2 0 4 0 8 0 16 32 64 128 256 512 1024 2048 4096 8192 16384 MOTOROLA CONFIGURABLE TIMER MODULE 7 MC68HC16R1 916R1 12 18 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 12 7 PWM Pulse and Frequency Ranges in Hz Using 3 Option 16 78 MHz
420. s counter to derive SCK baud rate from the MCU system clock The following expressions apply to SCK baud rate fs E ys SCK Baud Rate sPBR 720 or sys SPBR 7 0 2 x SCK Baud Rate Desired Giving SPBR 7 0 a value of zero or one disables the baud rate generator SCK is disabled and assumes its inactive state value SPBR 7 0 has 254 active values Table 11 4 lists several possible baud values and the corresponding SCK frequency based on a 16 78 MHz system clock Table 11 4 SCK Frequencies Seal nee a a Value of SPBR Actual SCK Frequency 16 78 MHz 4 2 4 19 MHz 8 4 2 10 MHz 16 8 1 05 MHz 34 17 493 kHz 168 84 100 kHz 510 255 33 kHz 11 3 6 Wired OR Open Drain Outputs Typically SPI bus outputs are not open drain unless multiple SPI masters in the system If needed the WOMP bit in SPCR can be set to provide wired OR open drain outputs An external pull up resistor should be used on each output line WOMP affects all SPI pins regardless of whether they are assigned to the SPI or used as general purpose I O 11 3 7 Transfer Size and Direction The SIZE bit in the SPCR selects a transfer size of 8 SIZE 0 or 16 SIZE 1 bits The LSBF bit in the SPCR determines whether serial shifting to and from the data register begins with the LSB LSBF 1 or MSB LSBF 0 MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL For More Information On This Product
421. s extension field For 20 bit modes a 20 bit signed offset zero extended to 24 bits is added to the val ue contained in an index register These modes are used for JMP and JSR instructions only 4 6 4 Inherent Addressing Mode Inherent mode instructions use information directly available to the processor to deter mine the effective address Operands if any are system resources and are thus not fetched from memory 4 6 5 Accumulator Offset Addressing Mode Accumulator offset modes form an effective address by sign extending the content of accumulator E to 20 bits then adding the result to an index register and its associated extension field This mode allows use of an index register and an accumulator within a loop without corrupting accumulator D 4 6 6 Relative Addressing Modes Relative modes are used for branch and long branch instructions If a branch condition is satisfied a byte or word signed two s complement offset is added to the concatenat ed PK field and program counter The new PK PC value is the effective address 4 6 7 Post Modified Index Addressing Mode Post modified index mode is used by the MOVB and MOVW instructions A signed 8 bit offset is added to index register X after the effective address formed by XK IX is used MOTOROLA CENTRAL PROCESSOR UNIT MC68HC16R1 916R1 4 10 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 6 8 Use of CPU1
422. s have multiple functions and thus have multiple entries in the Active State s column For example the ADDR23 CS10 ECLK pin can be pro grammed to be either address line 23 ADDR23 chip select output 10 CS10 or the M6800 bus clock Its entry in the Active State s column is 0 which indicates the following When programmed as ADDR23 the pin has no active state it conveys in formation when driven by the MCU to logic 0 or logic 1 When programmed as 510 the pin is active when driven to logic 0 0 by the MCU When driven to logic 1 the chip select function is inactive e When programmed as the pin has no active state M6800 bus de vices drive or prepare to latch an address when is logic 0 and drive or pre pare to latch data when ECLK is logic 1 The Discrete I O Use column indicates whether each can be used as a general purpose input output or both Those pins that cannot be used for general purpose will have a in this column MOTOROLA 3 11 MC68HC16R1 916R1 OVERVIEW USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 3 MC68HC16R1 MC68HC916R1 Pin Functions Pin Pin Active Associated er Discrete Mnemonic s Number s State s Module Description Use ADDR0 93 ADDR1 29 SCIM
423. s still asserted at the end of 512 cycles the control logic continues to assert the RESET pin until the internal reset signal is negated After 512 cycles have elapsed the RESET pin goes to an inactive high impedance state for ten cycles At the end of this 10 cycle period the RESET input is tested When the input is at logic level one reset exception processing begins If however the RESET input is at logic level zero reset control logic drives the pin low for another 512 cycles At the end of this period the pin again goes to high impedance state for ten cycles then it is tested again The process repeats until external RESET is released 5 7 7 Power On Reset When the SCIM2 clock synthesizer is used to generate system clocks power on reset involves special circumstances related to application of the system and the clock syn thesizer power Regardless of clock source voltage must be applied to clock synthe sizer power input pin Vppsyw for the MCU to operate The following discussion assumes that Vppsyn is applied before and during reset which minimizes crystal start up time When Vppsyn is applied at power on start up time is affected by spe cific crystal parameters and by oscillator circuit design ramp up time also affects pin state during reset Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for voltage and timing specifications During power on reset an internal circuit in the SCIM2 drives the IMB internal
424. se prem eta aa dus ipm 5 24 5 5 1 1 Address BUS ia iei LEE M ads 5 24 5 5 1 2 Address DIIOBO u u u u 5 24 5 5 1 3 Data cM AM a M a RE 5 24 5 5 1 4 Data SUHODe 5 24 MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title 5 5 1 5 Read Write Signal 5 5 1 6 Size Signals 5 5 1 7 Function Codes 5 5 1 8 Data Size Acknowledge Signals 5 5 1 9 Bus Error Signal 5 5 1 10 5 5 1 11 Autovector Signal 2 ere iat cde oet 5 5 2 Dynamic BUS SIZING UD ERE RE 5 5 3 Operand Alignment 5 5 4 Misaligned Operands 555 Operand Transfer Cases 5 6 B s OST ATO re breton Exit ded cte een ce 5 6 1 Synchronization to CLKOUT 5 6 2 Regular Bus 4 40 40 2 224 4 1 200 5 6 2 1 Read Cycle
425. sfer B to EK B 3 0 EK INH 27FA 2 TBSK Transfer B to SK B 3 0 SK INH 379F 2 TBXK Transfer B to XK B 3 0 XK INH 379C 2 TBYK Transfer B to YK B 3 0 YK INH 379D 2 TBZK Transfer B to ZK B 3 0 ZK INH 379E 2 TDE Transfer D to E 0 INH 277B 2 A 0 TDMSK Transfer D to D 15 8 X MASK INH 372F 2 XMSK YMSK D 7 0 Y MASK TDP Transfer D to CCR D 2 CCR 15 4 INH 372D 4 A A A A TED Transfer E to D E D INH 27FB 2 TEDM Transfer E and D to E AM 31 16 INH 27 1 4 0 0 31 0 0 15 0 Sign Extend AM AM 35 32 AM31 TEKB Transfer EK to B EK B 3 0 INH 27BB 2 0 B 7 4 TEM Transfer E to E AM 31 16 INH 27B2 4 0 0 AM 31 16 00 AM 15 0 Sign Extend AM 35 32 AM31 Clear AM LSB TMER Transfer Rounded AM Rounded AM Temp INH 27B4 6 A A toE If SM EV MV then Saturation Value E else Temp 31 16 2 E MC68HC16R1 916R1 MOTOROLA USER S MANUAL 4 27 For More Information On This Product Go to www freescale com Table 4 2 Instruction Set Summary Continued Freescale Semiconductor Inc Mnemonic Operation Description Address Instruction Condition Codes Mode Opcode
426. sor program space The CSBOOT chip select signal is used to select an external boot device mapped to a base address of 000000 The MSB of the CSBTPA field in CSPARO has a reset value of one so that chip select function is selected by default out of reset The BYTE field in chip select option register CSORBT has a reset value of both bytes so that the select signal is enabled out of reset The LSB of the CSBOOT field determined by the logic level of DATAO during reset selects the boot ROM port size When DATAO is held low during reset port size is eight bits When DATAO is held high during reset port size is 16 bits DATAO has a weak internal pull up driver so that a 16 bit port is selected by default out of reset However the internal pull up driver can be overcome by bus loading effects To en sure a particular configuration out of reset use an active device to put DATAO in a known state during reset MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 69 Go to www freescale com Freescale Semiconductor Inc The base address field in the boot chip select base address register CSBARBT has a reset value of all zeros so that when the initial access to address 000000 is made an address match occurs and the CSBOOT signal is asserted The block size field in CSBARBT has a reset value of 512 Kbytes Table 5 26 shows CSBOOT reset values Table 5 26 CSBOOT Base and Optio
427. st levels of SCIA and SCIB interrupts respectively Program this field to a value from 0 interrupts disabled through 7 highest priority MOTOROLA MC68HC16R1 916R1 D 42 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc D 6 4 MCCI Interrupt Vector Register MIVR MCCI Interrupt Vector Register YFFCO5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTV 7 2 INTV 1 0 0 0 0 0 1 1 1 1 The MIVR determines which three vectors in the exception vector table are to be used for MCCI interrupts The SPI and both SCI interfaces have separate interrupt vectors adjacent to one another When initializing the MCCI program INTV 7 2 so that INTV 7 0 correspond to three of the user defined vectors 40 FF INTV 1 0 are determined by the serial interface causing the interrupt and are set by the MCCI At reset MIVR is initialized to 0F which corresponds to the uninitialized interrupt vector in the exception table INTV 7 2 Interrupt Vector INTV 7 2 are the six high order bits of the three MCCI interrupt vectors for the MCCI as programmed by the user INTV 1 0 Interrupt Vector Source INTV 1 0 are the two low order bits of the three interrupt vectors for the MCCI They are automatically set by the MCCI to indicate the source of the interrupt Refer to Table D 31 Table D 31 Interrupt Vector Sources INTV 1 0 Source of Interrupt
428. st be driven to the desired active state Pull up or pull down circuitry may be necessary Pins configured as outputs begin to function after RESET is released Table 5 21 is a summary of SCIM2 pin states during reset Table 5 21 SCIM2 Pin Reset States Pin State After RESET Released Pin State Pin s While RESET Default Function Alternate Function Asserted pin Function Pin State Pin Function Pin State CS10 ADDR23 ECLK Vpp CS10 Vpp ADDR23 Unknown CS 9 6J ADDR 22 19J PC 6 3 Vpp 5 9 6 Vpp ADDR 22 19 Unknown ADDR 18 0 High Z ADDR 18 0 Unknown ADDR 18 0 Unknown AS PE5 High Z AS Output PE5 Input AVEC PE2 High Z AVEC Input PE2 Input BERR High Z BERR Input BERR Input CSM BG Vpp CS1 Vpp BG Vpp CSE BGACK Vpp CS2 Vpp BGACK Input CSO BR Vpp 50 Vpp BR Input CLKOUT Output CLKOUT Output CLKOUT Output CSBOOT Vpp CSBOOT Vss CSBOOT Vss DATA 15 0 Mode select DATA 15 0 Input DATA 15 0 Input DS PE4 High Z DS Output PE4 Input DSACKO PEO High Z DSACKO Input PEO Input DSACK1 PE1 High Z DSACK1 Input PE1 Input CS 5 3 FC 2 0J PC 2 0 Vpp CS 5 3 VDD FC 2 0 Unknown HALT High Z HALT Input HALT Input IRQ 7 1 PF 7 1 High Z IRQ 7 1 Input PF 7 1 Input FASTREF PFO Mode Select FASTREF Input PFO Input RAN High Z R W Output R W Output RESET Asserted RESET Input RESET Input SIZ 1 0 PE 7 6 High Z SIZ 1 0 Unknown PE 7 6 Input TSC Mode sele
429. sters 1 2 FEE 1 2 BAL Flash EEPROM Base Address Low Registers 1 2 FEE 1 2 BS 0 3 Flash EEPROM 1 2 Bootstrap Words 0 3 FEE 1 2 CTL Flash EEPROM Control Registers 1 2 FEE 1 2 MCR Flash EEPROM Module Configuration Registers 1 2 FEE 1 2 TST Flash EEPROM Test Registers 1 2 ILSCI MCCI SCI Interrupt Level Register ILSPI MCCI SPI Interrupt Level Register MC68HC16R1 916R1 NOMENCLATURE MOTOROLA USER S MANUAL 2 5 Freescale Semiconductor Inc Mnemonic Register LJSRR 0 7 ADC Left Justified Signed Result Registers 0 7 LJURR 0 7 ADC Left Justified Unsigned Result Registers 0 7 MCSM2SIC CTM7 MCSM2 Status Interrupt Control Register MCSM2CNT CTM7 MCSM2 Counter Register MCSM2ML CTM7 MCSM2 Modulus Latch MIVR Interrupt Vector Register MMCR Module Configuration Register MPAR MCCI Pin Assignment Register MRMCR Masked ROM Module Configuration Register MTEST Test Register PEPAR SCIM2 Port E Pin Assignment Register PFIVR SCIM2 Port F Edge Detect Interrupt Vector PFLVR SCIM2 Port F Edge Detect Interrupt Level PFPAR SCIM2 Port F Pin Assignment Register PICR SCIM2 Periodic Interrupt Control Register PITR SCIM2 Periodic Interrupt Timer Register PORTA SCIM2 Port A Data Register PORTADA ADC Port ADA Data Register PORTB SCIM2 Port B Data Register PORTC SCIM2 Port C Data Register PORTE 0 1 SCIM2 Port E Data Registers 0 1 PORTF 0 1 SCIM2 Port
430. sters include the SPI control register SPCR the SPI status register SPSR and the SPI data register SPDR Refer to D 6 13 SPI Control Register D 6 14 SPI Status Register and D 6 15 SPI Data Register for register bit and field definitions 11 3 1 1 SPI Control Register SPCR The SPCR contains parameters for configuring the SPI The register can be read or written at any time 11 3 1 2 SPI Status Register SPSR The SPSR contains SPI status information Only the SPI can set the bits in this register The CPU reads the register to obtain status information 11 3 1 3 SPI Data Register SPDR The SPDR is used to transmit and receive data on the serial bus A write to this register in the master device initiates transmission or reception of another byte or word After a byte or word of data is transmitted the SPIF status bit is set in both the master and slave devices A read of the SPDR actually reads a buffer If the first SPIF is not cleared by the time a second transfer of data from the shift register to the read buffer is initiated an over run condition occurs In cases of overrun the byte or word causing the overrun is lost A write to the SPDR is not buffered and places data directly into the shift register for transmission 11 3 2 SPI Pins Four bi directional pins are associated with the SPI The MPAR configures each pin for either SPI function or general purpose I O The MDDR assigns each pin as either input or output
431. t SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA For More Information On This Product 5 15 Go to www freescale com Freescale Semiconductor Inc 5 4 System Protection The system protection block preserves reset status monitors internal activity and provides periodic interrupt generation Figure 5 7 is a block diagram of the submodule MODULE CONFIGURATION AND TEST RESET STATUS HALT MONITOR RESET REQUEST BUS MONITOR BERR SPURIOUS INTERRUPT MONITOR SOFTWARE WATCHDOG TIMER RESET REQUEST CLOCK 29 PRESCALER PERIODIC INTERRUPT TIMER IRQ 7 1 SYS PROTECT BLOCK Figure 5 7 System Protection 5 4 1 Reset Status The reset status register RSR latches internal MCU status during reset Refer to 5 7 10 Reset Status Register for more information 5 4 2 Bus Monitor The internal bus monitor checks data size acknowledge DSACK or autovector AVEC signal response times during normal bus cycles The monitor asserts the internal bus error BERR signal when the response time is excessively long DSACK and AVEC response times are measured in clock cycles Maximum allowable response time can be selected by setting the bus monitor timing BMT 1 0 field in the system protection control register SYPCR Table 5 4 shows the periods allowed MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 16 For More Information On This Product USER S MANUAL Go to www freescale com Frees
432. t D 41 Go to www freescale com Freescale Semiconductor Inc STOP Low Power Stop Mode Enable 0 MCCI clock operates normally 1 MCCI clock is stopped When STOP is set the MCCI enters low power stop mode The system clock input to the module is disabled While STOP is set only MMCR reads and writes are guaran teed to be valid Only writes to other MCCI registers are guaranteed valid The SCI receiver and transmitter must be disabled before STOP is set To stop the SPI set the HALT bit in SPCRS3 wait until the HALTA flag is set then set STOP Bits 14 8 Not Implemented SUPV Supervisor Unrestricted This bit has no effect because the CPU16 in the MCU operates only in supervisor mode Bits 6 4 Not Implemented IARB 3 0 Interrupt Arbitration ID The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority Each module that can generate interrupt requests must be assigned a unique non zero IARB field value D 6 2 MCCI Test Register MTEST MCCI Test Register YFFCO2 Used for factory test only D 6 3 SCI Interrupt Level Register ILSCI SCI Interrupt Level Register YFFCOA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 ILSCIB 2 0 ILSCIA 2 0 MIVR 0 0 0 0 0 0 0 0 Bits 15 14 Not Implemented ILSCIA 2 0 ILSCIB 2 0 Interrupt Level for SCIA SCIB The values of ILSCIA 2 0 and ILSCIB 2 0 in ILSCI determine the interrupt reque
433. t external channel source impedances Figure 10 7 shows an active parasitic bipolar when an input pin is subjected to nega tive stress conditions Positive stress conditions do not activate a similar parasitic de vice MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC16R1 916R1 10 18 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc NEGATIVE STRESS VOLTAGE Retress QUT pid 10K PARASITIC A RADJACENT NT ADC PAR STRESS CONN Figure 10 7 Input Pin Subjected to Negative Stress The current out of the pin lour under negative stress is determined by the following equation _ Verness Veel DUI Bye STRESS where Vstress Adjustable voltage source Vege Parasitic bipolar base emitter voltage refer to in APPENDIX A ELECTRICAL CHARACTERISTICS Rstress Source impedance 10K resistor in Figure 10 7 on stressed channel The current into liy the neighboring pin is determined by the 1 Ky Gain of the parasitic bipolar transistor 1 Ky 1 One way to minimize the impact of stress conditions on the ADC is to apply voltage limiting circuits such as diodes to supply and ground However leakage from such cir cuits and the potential influence on the sampled voltage to be converted must be con sidered Refer to Figure 10 8 MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For
434. t in this register cleared to zero configures the corresponding pin as an input This register can be read or written at any time the MCU is not in emulator mode MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 71 Go to www freescale com Freescale Semiconductor Inc Port E pin assignment register PEPAR bits control the function of each port E pin Any bit set to one defines the corresponding pin to be a bus control signal with the function shown in Table 5 28 Any bit cleared to zero defines the corresponding pin to be an I O pin controlled by PORTE and DDRE Table 5 28 Port E Pin Assignments PEPAR Bit Port E Signal Bus Control Signal PEPA7 PE7 SIZ1 PEPA6 PE6 SIZO PEPA5 PE5 AS PEPA4 PE4 DS PEPA2 PE2 AVEC PEPA1 PE1 DSACKT PEPAO PEO DSACKO BERR and DATAS control the state of this register following reset If BERR and or DATAS are low during reset this register is set to 00 defining all port E pins as I O pins If BERR and DATA8 are both high during reset the register is set to FF which defines all port E pins as bus control signals 5 10 3 Port F Port F consists of eight I O pins a data register a data direction register a pin assign ment register an edge detect flag register an edge detect interrupt vector register an edge detect interrupt level register and associated control logic Figure 5 23 is a block diagra
435. t state of the corresponding pin until cleared To clear a bit first read PORTFE then write the bit to zero When a pin is configured for general purpose I O or for use as an interrupt request input PORTFE bits do not change state The port F edge detect interrupt vector register PFIVR determines which vector in the exception vector table is used for interrupts generated by the port F edge detect logic Program PFIVR 7 0 to the value pointing to the appropriate interrupt vector Refer to SECTION 4 CENTRAL PROCESSOR UNIT for interrupt vector assignments The port F edge detect interrupt level register PFLVR determines the priority level of the port F edge detect interrupt The reset value is 00 indicating that the interrupt is disabled When several sources of interrupts from the SCIM2 are arbitrating for the same level the port F edge detect interrupt has the lowest arbitration priority 5 10 4 Port G Port G is available in single chip mode only These pins are always configured for use as general purpose l O in single chip mode The port G data register PORTG can be read or written any time the MCU is not in emulation mode Reset has no effect Port G data direction register DDRG bits control the direction of the port pin drivers when pins are configured as I O Setting a bit configures the corresponding pin as an output Clearing a bit configures the corresponding pin as an input 5 10 5 Port H Port H is available in singl
436. t when all bits of a result register are zero V Overflow Flag Set when two s complement overflow occurs as the result of an operation C Carry Flag Set when carry or borrow occurs during arithmetic operation Also used during shifts and rotates IP 2 0 Interrupt Priority Field The priority value in this field 0 to 7 is used to mask low priority interrupts SM Saturate Mode Bit When SM is set if either EV or MV is set data read from AM using TMER or TMET will be given maximum positive or negative value depending on the state of the AM sign bit before overflow occurred PK 3 0 Program Counter Address Extension Field This field is concatenated with the program counter to form a 20 bit address There are no instructions to manipulate this field The CPU16 updates the PK field automatically and transparently to the user MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 3 Go to www freescale com Freescale Semiconductor Inc D 2 Single Chip Integration Module 2 Table D 2 shows the SCIM2 address map Table D 2 SCIM2 Address Map Address 8 7 0 SCIM Module Configuration Register SCIMCR YFFA02 SCIM Test Register SCIMTR YFFA04 Clock Synthesizer Control Register SYNCR YFFAO6 Not Used Reset Status Register RSR YFFA08 SCIM Test Register E SCIMTRE YFFAOA Port A
437. tP1VSA 10 ns 103 Phase 2 Valid to AS or DS Asserted tpovsn 10 ns MOTOROLA ELECTRICAL CHARACTERISTICS MC68HC16R1 916R1 A 8 USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table A 6 AC Timing Continued Vip and Vbpsyn 5 0 Vde 10 V 0 Vdc T T to Characteristic Symbol Min Max Unit 104 AS or DS Valid to Phase 1 Negated SAPIN 10 ns 105 AS or DS Negated to Phase 2 Negated teNP2N 10 ns NOTES 1 All AC timing is shown with respect to Vi Vi levels unless otherwise noted 2 When an external clock is used minimum high and low times are based on a 5096 duty cycle The minimum allowable txcyc period is reduced when the duty cycle of the external clock varies The relationship between external clock input duty cycle and minimum txcyc is expressed Minimum txcyc period minimum tycy 50 external clock input duty cycle tolerance 3 Parameters for an external clock signal applied while the internal PLL is disabled MODCLK pin held low during reset do not pertain to an external reference applied while the PLL is enabled MODCLK pin held high during reset When the PLL is enabled the clock synthesizer detects successive transitions of the ref erence signal If transitions occur within the correct clock period rise fall times and duty cycle are not critical 4 Address access time 2 5 WS
438. tatus Register 2 41111 D 9 D 2 5 SCIM Test Register od D 9 D 2 6 Port A and B Data Registers D 10 D 2 7 Port G and H Data Registers D 10 D 2 8 Port G and H Data Direction Registers D 10 D 2 9 Port E Data Begulslel ee o obe Eo oae cota bur D 11 D 2 10 Port E Data Direction Register D 11 D 2 11 Port E Pin Assignment Register D 11 D 2 12 Fort E Data BBOlSIel gus pu uuu tt ea Uer eh eos D 12 D 2 13 Port F Data Direction Register D 12 D 2 14 Port F Pin Assignment Register D 13 D 2 15 System Protection Control Register D 13 D 2 16 Periodic Interrupt Control Register D 15 MOTOROLA MC68HC16R1 916R1 xii USER S MANUAL For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLE OF CONTENTS Continued Paragraph Title Page D 2 17 Periodic Interrupt Timer Register D 15 D 2 18 Software Watchdog Service Register D 16 D 2 19 Port F Edge Detect Flag Reg
439. te the MCU must be powered down and restarted before normal operation can resume 5 7 9 Reset Processing Summary To prevent write cycles in progress from being corrupted a reset is recognized at the end of a bus cycle and not at an instruction boundary Any processing in progress at the time a reset occurs is aborted After SCIM2 reset control logic has synchronized an internal or external reset request the MSTRST signal is asserted The following events take place when MSTRST is asserted A Instruction execution is aborted B The condition code register is initialized 1 The IP field is set to 7 disabling all interrupts below priority 7 2 The S bit is set disabling LPSTOP mode 3 The SM bit is cleared disabling MAC saturation mode C The K register is cleared NOTE All CCR bits that are not initialized are not affected by reset Howev er out of power on reset these bits are indeterminate The following events take place when MSTRST is negated after assertion A The CPU16 samples the BKPT input B The CPU16 fetches RESET vectors in the following order Initial ZK SK and PK extension field values Initial PC Initial SP Initial IZ value B wm Vectors can be fetched from internal RAM or from external ROM enabled by the CSBOOT signal C The CPU16 begins fetching instructions pointed to by the initial PK PC 5 7 10 Reset Status Register The reset status register RSR contains a bit for each reset s
440. te input CTD 5 4 Discrete input CTM2C Discrete input MCCI TXDA PMC7 Discrete input RXDA PMC6 Discrete input TXDB PMC5 Discrete input RXDB PMC4 Discrete input SS PMC3 Discrete input SCK PMC2 Discrete input MOSI PMC1 Discrete input MISO PMCO Discrete input NOTES 1 Module port pins may be in an indeterminate state for up to 15 milliseconds at power up 5 7 5 Pin State During Reset It is important to keep the distinction between pin function and pin electrical state clear Although control register values and mode select inputs determine pin function a pin driver can be active inactive or in high impedance state while reset occurs During power on reset pin state is subject to the constraints discussed in 5 7 7 Power On Reset NOTE Pins that are not used should either be configured as outputs or if configured as inputs pulled to the appropriate inactive state This decreases additional Ipp caused by digital inputs floating near mid supply level MOTOROLA 5 52 SINGLE CHIP INTEGRATION MODULE 2 For More Information On This Product Go to www freescale com MC68HC16R1 916R1 USER S MANUAL Freescale Semiconductor Inc 5 7 5 1 Reset States of SCIM2 Pins Generally while RESET is asserted SCIM2 pins either go to an inactive high impedance state or are driven to their inactive states After RESET is released mode selection occurs and reset exception processing begins Pins configured as inputs mu
441. terrupt request of a certain priority and the chip select base address and option registers are programmed to generate AVEC or DSACK signals in response to an interrupt acknowledge cycle for that priority level chip select logic does not respond to the interrupt acknowledge cycle and the internal module supplies a vector number and generates an internal DSACK signal to terminate the cycle Perform the following operations before using a chip select to generate an interrupt acknowledge signal 1 Program the base address field to all ones 2 Program block size to no more than 64 Kbytes so that the address comparator checks ADDR 19 16 against the corresponding bits in the base address register The CPU16 places the CPU space bus cycle type on ADDR 19 16 3 Set the R W field to read only An interrupt acknowledge cycle is performed as a read cycle 4 Set the BYTE field to lower byte when using a 16 bit port as the external vector for a 16 bit port is fetched from the lower byte Set the BYTE field to upper byte when using an 8 bit port If an interrupting device does not provide a vector number an autovector acknowledge must be generated either by asserting the AVEC pin or by generat ing AVEC internally using the chip select option register This terminates the bus cycle MOTOROLA SINGLE CHIP INTEGRATION MODULE 2 MC68HC16R1 916R1 5 68 For More Information On This Product USER S MANUAL Go to www freescale com
442. that is not in the synthesizer feedback loop Setting the bit doubles clock speed without changing the VCO speed No VCO relock delay is required Y 5 0 Frequency Control Counter The Y field controls the modulus down counter in the synthesizer feedback loop causing it to divide by a value of Y 1 Values range from 0 to 63 VCO relock delay is required EDIV E Clock Divide Rate 0 ECLK frequency is system clock divided by 8 1 ECLK frequency is system clock divided by 16 SLOCK Synthesizer Lock Flag 0 VCO is enabled but has not locked 1 VCO has locked on the desired frequency or VCO is disabled MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 8 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc The MCU remains in reset until the synthesizer locks but SLOCK does not indicate synthesizer lock status until after the user writes to SYNCR STSCIM Stop Mode SCIM Clock 0 When LPSTOP is executed the SCIM clock is driven from the external crystal oscillator and the VCO is turned off to conserve power 1 When LPSTOP is executed the SCIM clock is driven from the internal VCO STEXT Stop Mode External Clock 0 When LPSTOP is executed the CLKOUT signal is held negated to conserve power 1 When LPSTOP is executed and EXOFF z 1 in SCIMCR the CLKOUT signal is driven from the SCIM2 clock as determined by the state of the STSCIM bit D 2 4 Reset St
443. the RXD pin and also controls when data is to be passed to the receive serial shifter A receive time clock is used to control sampling and synchronization Data is shifted into the receive serial shifter according to the most recent synchronization of the receive time clock with the incoming data stream From this point on data movement is synchronized with the MCU system clock The number of bits shifted in by the receiver depends on the serial format However all frames must end with at least one stop bit When the stop bit is received the frame is considered to be complete and the received data in the serial shifter is transferred to the RDR The receiver data register flag RDRF is set when the data is transferred Noise errors parity errors and framing errors can be detected while a data stream is being received Although error conditions are detected as bits are received the noise flag NF the parity flag PF and the framing error FE flag in SCSR are not set until data is transferred from the serial shifter to the RDR RDRF must be cleared before the next transfer from the shifter can take place If RDRF is set when the shifter is full transfers are inhibited and the overrun error OR flag in SCSR is set OR indicates that the RDR needs to be serviced faster When OR is set the data in the RDR is preserved but the data in the serial shifter is lost Be cause framing noise and parity errors are detected while data is in the se
444. therwise the value read is the value stored in the register 5 10 1 Ports A and B Ports A and B are available in single chip mode only One data direction register con trols data direction for both ports Port A and B registers can be read or written at any time the MCU is not in emulator mode Port A B data direction bits DDA and DDB control the direction of the pin drivers for ports A and B respectively when the pins are configured for I O Setting DDA or DDB to one configures all pins in the corresponding port as outputs Clearing DDA or DDB to zero configures all pins in the corresponding port as inputs 5 10 2 Port E Port E can be made available in all operating modes The state of BERR and DATA8 during reset controls whether the port E pins are used as bus control signals or dis crete I O lines If the MCU is in emulator mode an access of the port E data data direction or pin assignment registers PORTE DDRE PEPAR is forced to go external This allows port replacement logic to be supplied externally giving an emulator access to the bus control signals The port E data register PORTE is a single register that can be accessed in two locations It can be read or written at any time the MCU is not in emulator mode Port E data direction register DDRE bits control the direction of the pin drivers when the pins are configured as I O Any bit in this register set to one configures the corresponding pin as an output Any bi
445. timer are disabled preventing interrupts during background debug mode CPUD CPU Development Support Disable 0 Instruction pipeline signals available on pins IPIPE1 and IPIPEO 1 Pins IPIPE1 and IPIPEO placed in high impedance state unless a breakpoint occurs CPUD is cleared to zero when the MCU is in an expanded mode and set to one in single chip mode FRZBM Freeze Bus Monitor Enable 0 When FREEZE is asserted the bus monitor continues to operate 1 When FREEZE is asserted the bus monitor is disabled SHEN 1 0 Show Cycle Enable The SHEN field determines how the external bus is driven during internal transfer operations A show cycle allows internal transfers to be monitored externally Table D 3 indicates whether show cycle data is driven externally and whether exter nal bus arbitration can occur To prevent bus conflict external devices must not be selected during show cycles MOTOROLA REGISTER SUMMARY MC68HC16R1 916R1 D 6 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc Table D 3 Show Cycle Enable Bits SHEN 1 0 Action 00 Show cycles disabled external arbitration enabled 01 Show cycles enabled external arbitration disabled 10 Show cycles enabled external arbitration enabled 11 Show cycles enabled external arbitration enabled internal activity is halted by a bus grant SUPV Supervisor User Data Space This bit has
446. ting M68HC11 Code to M68HC16 Devices contains detailed information about differences between the two instruction sets Refer to the CPU16 Reference Manual CPU16RM AD for further details about CPU operations MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Product 4 31 Go to www freescale com Freescale Semiconductor Inc Table 4 4 CPU16 Implementation of M68HC11 CPU Instructions M68HC11 Instruction CPU16 Implementation BHS BCC only BLO BCS only BSR Generates a different stack frame CLC Replaced by ANDP CLI Replaced by ANDP CLV Replaced by ANDP DES Replaced by AIS DEX Replaced by AIX DEY Replaced by AIY INS Replaced by AIS INX Replaced by AIX INY Replaced by AIY JMP IND8 and EXT addressing modes replaced by IND20 and EXT20 modes JSR 2 addressing modes replaced by IND20 and 20 modes enerates a different stack frame LSL LSLD Use ASL instructions PSHX Replaced by PSHM PSHY Replaced by PSHM PULX Replaced by PULM PULY Replaced by PULM RTI Reloads PC and CCR only RTS Uses two word stack frame SEC Replaced by ORP SEI Replaced by ORP SEV Replaced by ORP STOP Replaced by LPSTOP TAP CPU16 CCR bits differ from M68HC1 1 CPU16 interrupt priority scheme differs from M68HC1 1 TPA CPU16 CCR bits differ from M68HC1 1 CPU16 interrupt priority scheme differs from M68HC1 1 TSX Adds 2 to SK SP before t
447. tion On This Product 3 21 Go to www freescale com Freescale Semiconductor Inc VECTOR VECTOR YPE OF ADDRESS NUMBER EXCEPTION 5000000 0000 0 RESET INITIAL ZK SK AND PK BANK 0 5000000 5000009 0002 1 RESET INITIAL PC EXCEPTION VECTORS 000008 0004 2 RESET INITIAL SP r i 010000 0006 3 RESET INITIAL IZ DIRECT PAGE el 010000 020000 777777 VECTOR VECTOR YPE OF RANK Se te ee 020000 ADDRESS NUMBER EXCEPTION 0008 4 BKPT BREAKPOINT s mas a E seed 0004 5 BERR BUS ERROR PENES 030000 e SWS OFTWARE INTERRUPT BANK3 030000 512 KBYTE 000 7 ILLEGAL INSTRUCTION 0010 8 DIVISION BY ZERO amare TO DO t UWASSIGNED RESERVED 4 42 5040000 0020 10 UNASSIGNED RESERVED 0022 11 LEVEL 1 INTERRUPT AUTOVECTOR 050000 0024 12 LEVEL 2 INTERRUPT AUTOVECTOR BANKS t le R RS 050000 0026 13 LEVEL 3 INTERRUPT AUTOVECTOR 0028 14 LEVEL 4 INTERRUPT AUTOVECTOR 002A 15 LEVELS INTERRUPT AUTOVECTOR LARA EL da Ut f ceo 060000 sank 002C 16 LEVEL6 INTERRUPT AUTOVECTOR BANK 6 060000 PROGRAM 002E 17 LEVEL 7 INTERRUPT AUTOVECTOR DATA SPACE 0030 18 SPURIOUS INTERRUPT SPACE ier AT e ur 0032 006E 19 37
448. to the status of a conversion sequence SCF Sequence Complete Flag 0 Sequence not complete 1 Sequence complete SCF is set at the end of the conversion sequence when SCAN is cleared and at the end of the first conversion sequence when SCAN is set SCF is cleared when ADCTL1 is written and a new conversion sequence begins CCTR 2 0 Conversion Counter This field reflects the contents of the conversion counter pointer in either four or eight count conversion sequence The value corresponds to the number of the next result register to be written and thus indicates which channel is being converted CCF 7 0 Conversion Complete Flags Each bit in this field corresponds to an A D result register for example CCF7 to RSLT7 A bit is set when conversion for the corresponding channel is complete and remains set until the associated result register is read D 5 7 Right Justified Unsigned Result Register RJURR Right Justified Unsigned Result Register YFF710 YFF71F 15 10 9 8 7 6 5 4 3 2 1 0 NOT USED 10 10 8 10 8 10 8 10 8 10 8 10 8 10 8 10 8 10 Conversion result is unsigned right justified data Bits 9 0 used for 10 bit resolu tion For 8 bit conversions bits 7 0 contain data and bits 9 8 are zero Bits 15 10 always return zero when read D 5 8 Left Justified Signed Result Register LJSRR Left Justified Signed Result Register YFF720 YFF72F 15 14 13 12 11
449. tor Inc 5 5 1 9 Bus Error Signal The bus error signal BERR is asserted when a bus cycle is not properly terminated by DSACK or AVEC assertion It can also be asserted in conjunction with DSACK to indicate a bus error condition provided it meets the appropriate timing requirements Refer to 5 6 5 Bus Exception Control Cycles for more information The internal bus monitor can generate the BERR signal for internal to internal and internal to external transfers In systems with an external bus master the SCIM2 bus monitor must be disabled and external logic must be provided to drive the BERR pin because the internal BERR monitor has no information about transfers initiated by an external bus master Refer to 5 6 6 External Bus Arbitration for more information 5 5 1 10 Halt Signal The halt signal HALT can be asserted by an external device for debugging purposes to cause single bus cycle operation or in combination with BERR a retry of a bus cycle in error The HALT signal affects external bus cycles only As a result a program not requiring use of the external bus may continue executing unaffected by the HALT signal When the MCU completes a bus cycle with the HALT signal asserted DATA 15 0 is placed in a high impedance state and bus control signals are driven in active the address function code size and read write signals remain in the same state If HALT is still asserted once bus mastership is returned to the MCU the ad
450. tor Inc D 5 1 ADC Module Configuration Register ADCMCR ADC Module Configuration Register YFF700 15 14 13 12 8 7 6 0 STOP FRZ NOT USED SUPV NOT USED RESET 1 0 0 1 ADCMCR controls ADC operation during low power stop mode background debug mode and freeze mode STOP Low Power Stop Mode Enable 0 Normal operation 1 Low power operation STOP places the ADC in low power state Setting STOP aborts any conversion in progress STOP is set to logic level one during reset and may be cleared to logic level zero by the CPU16 Clearing STOP enables normal ADC operation However because analog circuitry bias current has been turned off there is a period of recovery before output stabilization FRZ 1 0 Freeze Assertion Response The FRZ field determines ADC response to assertion of the FREEZE signal when the device is placed in background debug mode Refer to Table D 24 Table D 24 Freeze Encoding FRZ 1 0 Response 00 Ignore FREEZE continue conversions 01 Reserved 10 Finish conversion in process then freeze 11 Freeze immediately SUPV Supervisor Unrestricted This bit has no effect because the CPU16 always operates in supervisor mode D 5 2 ADC Test Register ADCTEST ADC Test Register YFF702 Used for factory test only D 5 3 Port ADA Data Register PORTADA Port ADA Data Register YFF706 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOT USED PADA7 PADA
451. tor and buffer ampli fier are bypassed and multiplexer input charges the DAC array directly The length of this third portion of a sampling period is determined by the value of the STS field in ADCTLO MC68HC16R1 916R1 ANALOG TO DIGITAL CONVERTER MOTOROLA USER S MANUAL For More Information On This Product 10 5 Go to www freescale com Freescale Semiconductor Inc 10 6 3 RC DAC Array The RC DAC array consists of binary weighted capacitors and a resistor divider chain The array performs two functions it acts as a sample hold circuit during conversion and it provides each successive digital to analog comparison voltage to the compara tor Conversion begins with MSB comparison and ends with LSB comparison Array switching is controlled by the digital subsystem 10 6 4 Comparator The comparator indicates whether each approximation output from the RC DAC array during resolution is higher or lower than the sampled input voltage Comparator output is fed to the digital control logic which sets or clears each bit in the successive approx imation register in sequence MSB first 10 7 Digital Control Subsystem The digital control subsystem includes control and status registers clock and prescal er control logic channel and reference select logic conversion sequence control logic and the successive approximation register The subsystem controls the multiplexer and the output of the RC array during sample and conversion periods
452. tor must be connected between the base of the transistor and the RESET pin If a MOSFET is substituted for the bipolar transistor only the 1 kQ isolation resistor is required These simpler circuits do not offer the protection from potential memory corruption during RESET assertion as does the circuit shown in Figure 5 17 MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 45 Go to www freescale com Freescale Semiconductor Inc DATA PIN DATA PIN gt la RESET 203906 104148 WA ALTERNATE DATA BUS CONDITION CIRCUIT Figure 5 18 Alternate Circuit for Data Bus Mode Select Conditioning Data bus mode select current is specified in APPENDIX A ELECTRICAL CHARAC TERISTICS Do not confuse pin function with pin electrical state Refer to 5 7 5 Pin State During Reset for more information 5 7 3 3 16 Bit Expanded Mode 16 bit data bus operation is selected when BERR 1 and DATA1 0 during reset In this configuration pins ADDR 18 3 and DATA 15 0 are configured as address and data pins respectively The alternate functions for these pins as ports A B G and H are unavailable ADDR 23 20 can be configured as chip selects or address bus pins ADDR 2 0 are configured as address bus pins DATA2 determines the functions of BR CSO FC0 CS3 FC2 CS5 DATA 7 3 determine the functions of ADDR 23 19 CS 10 6 A data bus pin pulled low selects
453. tor timing This register can be written once following power on or reset Bits 15 8 are unimplemented and will always read zero SWE Software Watchdog Enable 0 Software watchdog is disabled 1 Software watchdog is enabled SWP Software Watchdog Prescaler This bit controls the value of the software watchdog prescaler 0 Software watchdog clock is not prescaled 1 Software watchdog clock is prescaled by 512 MC68HC16R1 916R1 REGISTER SUMMARY MOTOROLA USER S MANUAL For More Information On This Product D 13 Go to www freescale com Freescale Semiconductor Inc The reset value of SWP is the complement of the state of the MODCLK pin during reset SWT 1 0 Software Watchdog Timing This field selects the divide ratio used to establish the software watchdog timeout period Refer to Table D 6 Table D 6 Software Watchdog Divide Ratio SWP SWT 1 0 Divide Ratio 0 00 29 0 01 211 0 10 213 0 11 215 1 00 218 1 01 220 1 10 222 1 11 224 The following equation calculates the timeout period for a slow reference frequency where fret is equal to the EXTAL crystal frequency Divide Ratio Specified by SWP SWTT 1 0 Timeout Period ref The following equation calculates the timeout period for a fast reference frequency 128 Divide Ratio Specified by SWP and SWT 1 0 Timeout Period The following equation calculates the timeout period for an exte
454. ture BR1116 D for a complete list of documentation to supplement this manual MOTOROLA INTRODUCTION MC68HC16R1 916R1 1 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc SECTION 2 NOMENCLATURE The following tables show the nomenclature used throughout the MC68HC16R1 916R1 user s manual 2 1 Symbols and Operators Symbol Function Addition Subtraction two s complement or negation Multiplication Division Greater Less Equa Equal or greater Equal or less Not equal AND Inclusive OR OR Exclusive OR EOR Complementation z Concatenation Transferred Exchanged Sign bit also used to show tolerance Sign extension Binary value Hexadecimal value MC68HC16R1 916R1 NOMENCLATURE MOTOROLA USER S MANUAL For More Information On This Product 2 1 Go to www freescale com Freescale Semiconductor Inc 2 2 CPU16 Register Mnemonics MOTOROLA 2 2 Mnemonic Register A Accumulator A AM Accumulator M B Accumulator B CCR Condition code register D Accumulator D E Accumulator E EK Extended addressing extension field HR MAC multiplier register IR MAC multiplicand register IX Index register X IY Index register Y IZ Index register Z K Address extension register PC Progra
455. uct 5 5 Go to www freescale com Freescale Semiconductor Inc 22 pF XTAL R2 10M EXTAL C2 22 pF RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX 38 32 768 KHZ CRYSTAL SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT 32 OSCILLATOR Figure 5 3 Slow Reference Crystal Circuit A 4 194 MHz crystal is typically used for a fast reference but the frequency may vary between 1 MHz to 6 MHz Figure 5 4 shows a typical circuit XTAL gt EXTAL 7 RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A KDS041 18 4 194 MHz CRYSTAL SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT 16 OSCILLATOR 4M Figure 5 4 Fast Reference Crystal Circuit If a fast or slow reference frequency is provided to the PLL from a source other than a crystal or an external system clock signal is applied through the EXTAL pin the XTAL pin must be left floating 5 3 2 Clock Synthesizer Operation Vppsyn is used to power the clock circuits when the system clock is synthesized from either a crystal or an externally supplied reference frequency A separate power source increases MCU noise immunity and can be used to run the clock when the MCU is powered down A quiet power supply must be used as the Vppsyw source Adequate external bypass capacitors should
456. ud frequency e Start Bit One bit time of logic zero that indicates the beginning of a data frame A start bit must begin with a one to zero transition and be preceded by at least three receive time samples of logic one e Stop Bit One bit time of logic one that indicates the end of a data frame Frame A complete unit of serial information The SCI can use 10 bit or 11 bit frames Data Frame A start bit a specified number of data or information bits and at least one stop bit e Idle Frame A frame that consists of consecutive ones An idle frame has no start bit Break Frame A frame that consists of consecutive zeros A break frame has no stop bits MC68HC16R1 916R1 MULTICHANNEL COMMUNICATION INTERFACE MOTOROLA USER S MANUAL 11 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 11 4 5 2 Serial Formats All data frames must have a start bit and at least one stop bit Receiving and transmit ting devices must use the same data frame format The SCI provides hardware sup port for both 10 bit and 11 bit frames The M bit in SCCR1 specifies the number of bits per frame The most common data frame format for NRZ serial interfaces is one start bit eight data bits LSB first and one stop bit a total of ten bits The most common 11 bit data frame contains one start bit eight data bits a parity or control bit and one stop bit Ten bit and eleven bit frames ar
457. ule Configuration Register MMCR YFFCO2 MCCI Test Register MTEST YFFC04 SCI Interrupt Level Register ILSCI MCCI Interrupt Vector Register MIVR YFFCOG SPI Interrupt Level Register ILSPI Not Used YFFCO8 Not Used MCCI Pin Assignment Register MPAR YFFCOA Not Used MCCI Data Direction Register MDDR YFFCOC Not Used MCCI Port Data Register PORTMC YFFCOE Not Used MCCI Port Pin State Register PORTMCP ECT Not Used YFFC18 SCIA Control Register 0 SCCROA YFFC1A SCIA Control Register 1 SCCR1A YFFC1C SCIA Status Register SCSRA YFFC1E SCIA Data Register SCDRA Not Used YFFC28 SCIB Control Register 0 SCCROB YFFC2A SCIB Control Register 1 SCCR1B YFFC2C SCIB Status Register SCSRB YFFC2E SCIB Data Register SCDRB pie a Not Used YFFC38 SPI Control Register SPCR YFFC3A Not Used YFFC3C SPI Status Register SPSR YFFC3E SPI Data Register SPDR NOTES 1 Y M111 where M is the logic state of the module mapping MM bit in the SCIMCR D 6 1 MCCI Module Configuration Register MMCR MCCI Module Configuration Register YFFCOO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STOP NOT USED SUPV NOT USED IARB 3 0 RESET 0 1 0 0 0 0 MMCR bits enable stop mode establish the privilege level required to access certain MCCI registers and determine the arbitration priority of MCCI interrupt requests MC68HC16R1 916R1 MOTOROLA USER S MANUAL For More Information On This Produc
458. unchanged state of the PWMSM output flip flop will remain unchanged If the IMB FREEZE signal is asserted and FRZ 0 the freeze condition is ignored and all CTM7 submodules will continue to operate normally 12 4 3 LPSTOP Effect on the BIUSM When the CPU16 LPSTOP instruction is executed the system clock is stopped All de pendent modules including the CTM7 are shut down until low power STOP mode is exited 12 4 4 BIUSM Registers The BIUSM contains a module configuration register a time base register and a test register The BIUSM register block occupies the first four register locations in the CTM7 register space All unused bits and reserved address locations return zero when read Writes to unused bits and reserved address locations have no effect Refer to D 7 1 BIU Module Configuration Register D 7 2 BIUSM Test Configuration Reg ister and D 7 3 BIUSM Time Base Register for information concerning BIUSM reg ister and bit descriptions 12 5 Counter Prescaler Submodule CPSM The counter prescaler submodule CPSM is a programmable divider system that pro vides the CTM7 counters with a choice of six clock signals PCLK 1 6 derived from the main MCU system clock Five of these frequencies are derived from a fixed divider chain The divide ratio of the last clock frequency is software selectable from a choice of four divide ratios The CPSM is part of the BIUSM Figure 12 2 shows a block diagram of the CPSM M
459. upts 4 13 2 Exception Stack Frame During exception processing the contents of the program counter and condition code register are stacked at a location pointed to by SK SP Unless it is altered during ex ception processing the stacked PK PC value is the address of the next instruction in the current instruction stream plus 0006 Figure 4 6 shows the exception stack frame Low Address lt SP After Exception Stacking Condition Code Register High Address Program Counter lt SP Before Exception Stacking Figure 4 6 Exception Stack Frame Format MOTOROLA MC68HC16R1 916R1 4 38 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc 4 13 3 Exception Processing Sequence Exception processing is performed in four phases Priority of all pending exceptions is evaluated and the highest priority exception is processed first Processor state is stacked then the CCR PK extension field is cleared An exception vector number is acquired and converted to a vector address The content of the vector address is load ed into the PC and the processor jumps to the exception handler routine There are variations within each phase for differing types of exceptions However all vectors except RESET are 16 bit addresses and the field is cleared during excep tion processing Consequently exception handlers must be located within bank 0 or vectors must point to a jump table i
460. urces are internal and eight are external Multiplexer operation is controlled by channel selection field CD CA in register ADCTL1 Table 10 2 shows the different multiplexer channel sourc es The multiplexer contains positive and negative stress protection circuitry This cir cuitry prevents voltages on other input channels from affecting the current conversion Table 10 2 Multiplexer Channel Sources CD CA Value Input Source 0000 ANO 0001 AN1 0010 AN2 0011 0100 4 0101 5 0110 6 0111 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 1101 1110 Vn 2 1111 Test Reserved 10 6 2 Sample Capacitor and Buffer Amplifier Each of the eight external input channels is associated with a sample capacitor and share a single sample buffer amplifier After a conversion is initiated the multiplexer output is connected to the sample capacitor at the input of the sample buffer amplifier for the first two ADC clock cycles of the sampling period The sample amplifier buffers the input channel from the relatively large capacitance of the RC DAC array During the second two clock cycles of a sampling period the sample capacitor is dis connected from the multiplexer and the sample buffer amplifier charges the RC DAC array with the value stored in the sample capacitor During the third portion of a sampling period both sample capaci
461. ved address locations return zero when read Writes to unused bits and reserved address locations have no effect The CTM7 contains four DASMs each with its own set of registers Refer to D 7 11 DASM Status Interrupt Control Registers D 7 12 DASM Data Register A and D 7 13 DASM Data Register B for information concerning DASM register and bit descriptions 12 10 Pulse Width Modulation Submodule PWMSM The PWMSM allows pulse width modulated signals to be generated over a wide range of frequencies independently of other CTM7 output signals The output pulse width duty cycle can vary from 0 to 100 with 16 bits of resolution The minimum pulse width is twice the MCU system clock period For example the minimum pulse width is 119 ns when using a 16 78 MHz clock The PWMSM is composed of output flip flop with output polarity control Clock prescaler and selection logic A 16 bit up counter Two registers to hold the current and next pulse width values Two registers to hold the current and next pulse period values A pulse width comparator A system state sequencer Logic to create 0 and 100 pulses Interrupt logic status interrupt and control register A submodule bus interface The PWMSM includes its own time base counter and does not use the CTM7 time base buses however it does use the prescaled clock signal PCLK1 generated by the CPSM Refer to 12 5 Counter Prescaler Submodule CPSM and Figure 12
462. wer on reset It shows the relationships between RESET Vpp and bus signals uU N vco LOCK 2 5 lt gt 4 lt 512 CLOCKS 1 10 CLOCKS gt RESET IL gg MI ADDRESS AND CONTROL SIGNALS gt a 2 THREE STATED BUS STATE UNKNOWN NOTES 1 INTERNAL START UP TIME 2 FIRST INSTRUCTION FETCHED 16 POR TIM Figure 5 19 Power On Reset 5 7 8 Use of the Three State Control Pin Asserting the three state control TSC input causes the MCU to put all output drivers in a disabled high impedance state The signal must remain asserted for approxi mately ten clock cycles in order for drivers to change state When the internal clock synthesizer is used MODCLK held high during reset synthe sizer ramp up time affects how long the ten cycles take Worst case is approximately 20 milliseconds from TSC assertion When an external clock signal is applied MODCLK held low during reset pins go to high impedance state as soon after TSC assertion as approximately ten clock pulses have been applied to the EXTAL pin MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 55 Go to www freescale com Freescale Semiconductor Inc NOTE When TSC assertion takes effect internal signals are forced to val ues that can cause inadvertent mode selection Once the output driv ers change sta
463. xception of SCK are used by the SPI and which pins are available for general purpose I O The MCCI data direction register DDRM configures each pins as an input or output 11 2 1 1 Low Power Stop Mode When the STOP bit in the MMCR is set the IMB clock signal to most of the MCCI module is disabled This places the module in an idle state and minimizes power consumption MOTOROLA MULTICHANNEL COMMUNICATION INTERFACE MC68HC16R1 916R1 11 2 For More Information On This Product USER S MANUAL Go to www freescale com Freescale Semiconductor Inc To ensure that the MCCI stops in a known state assert the STOP bit before executing the CPU LPSTOP instruction Before asserting the STOP bit disable the SPI clear the SPE bit and disable the SCI receivers and transmitters clear the RE and TE bits Complete transfers in progress before disabling the SPI and SCI interfaces Once the STOP bit is asserted it can be cleared by system software or by reset 11 2 1 2 Privilege Levels The supervisor bit SUPV in the MMCR has no effect since the CPU16 operates only in the supervisor mode 11 2 1 3 MCCI Interrupts The interrupt request level of each of the three MCCI interfaces can be programmed to a value of 0 interrupts disabled through 7 highest priority These levels are se lected by the ILSCIA and ILSCIB fields in the SCI interrupt level register ILSCI and the ILSPI field in the SPI interrupt level register ILSPI In case two
464. y exception processing or reaches an instruction boundary Processor state is stacked then the CCR PK extension field is cleared The interrupt acknowledge cycle begins 1 FC 2 0 are driven to 111 CPU space encoding 2 The address bus is driven as follows ADDR 23 20 1111 ADDR 19 16 961111 which indicates that the cycle is an interrupt acknowledge CPU space cycle ADDR 15 4 111111111111 ADDR 3 1 the priority of the interrupt request being acknowledged and ADDRO 1 3 Request priority is latched into the CCR IP field from the address bus Modules or external peripherals that have requested interrupt service decode the priority value in ADDR 3 1 If request priority is the same as acknowledged priority arbitration by IARB contention takes place After arbitration the interrupt acknowledge cycle is completed in one of the fol lowing ways 1 When there is no contention IARB 960000 the spurious interrupt monitor asserts BERR and the CPU16 generates the spurious interrupt vector number 2 The dominant interrupt source supplies a vector number and DSACK sig nals appropriate to the access The CPU16 acquires the vector number 3 The AVEC signal is asserted the signal can be asserted by the dominant interrupt source or the pin can be tied low and the CPU16 generates an autovector number corresponding to interrupt priority 4 The bus monitor asserts BERR and the CPU16 generates the spurious int
465. ycle tswow 40 ns 15 AS DS CS Width Negated ton 40 ns 16 Clock High to AS DS RAN High Impedance tcusz 59 ns 17 AS DS CS Negated to R W High teNRN 15 ns 18 Clock High to R W High tcunH 0 29 ns 20 High to RAN Low tCHRL 0 29 ns 21 RAN High to AS CS Asserted tRAAA 15 ns 22 R Low to DS CS Asserted Write tRASA 70 ns 23 Clock High to Data Out Valid tcHDo 29 ns 24 Data Out Valid to Negating Edge of AS CS Fast Write Cycle tpyAsN 15 ns 25 DS CS Negated to Data Out Invalid Data Out Hold teNDOI 15 ns 26 Data Out Valid to DS CS Asserted Write tpvsa 15 ns 27 In Valid to Clock Low Data Setup tpicL 5 ns MC68HC16R1 916R1 ELECTRICAL CHARACTERISTICS MOTOROLA USER S MANUAL A 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table A 6 AC Timing Continued Vg and VbpsyN 5 0 Vdc 10 Vos 0 Vdc T to Characteristic Symbol Min Max Unit 27A Late BERR HALT Asserted to Clock Low Setup Time tBELCL 20 ns 28 AS DS Negated to DSACK 1 0 BERR HALT AVEC Negated tsnpn 0 80 ns 29 DS CS Negated to Data In Invalid Data In Hold tsNDI 0 ns 29A 55 CS Negated to Data In High Impedance 8 tsHDI 55 ns 30 CLKOUT Low to Data In Invalid Fast Cycle Hold tci DI 15 ns 30A CLKOUT Low to Data In H
466. yn supply pin An alternate filter can be used in high stability operating environments to reduce PLL jitter under noisy system conditions Current systems that are operating correctly may not require this filter If the PLL is not enabled MODCLK 0 at reset the XFC filter is not required Versions of the SCIM that are configured for either slow or fast reference use the same filter component values An external filter network connected to the XFC pin is not required when an external system clock signal is applied and the PLL is disabled MODCLK 0 at reset The XFC pin must be left floating in this case VppsyN NORMAL OPERATING ENVIRONMENT HIGH STABILITY OPERATING ENVIRONMENT 1 MAINTAIN LOW LEAKAGE ON THE NODE REFER TO APPENDIX A ELECTRICAL CHARACTERISTICS FOR MORE INFORMATION 2 RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW FREQUENCY NOISE NORMAL HIGH STABILITY XFC CONN Figure 5 5 System Clock Filter Networks MC68HC16R1 916R1 SINGLE CHIP INTEGRATION MODULE 2 MOTOROLA USER S MANUAL For More Information On This Product 5 7 Go to www freescale com Freescale Semiconductor Inc The synthesizer locks when the VCO frequency is equal to fre Lock time is affected by the filter time constant and by the amount of difference between the two comparator inputs Whenever a comparator input changes the synthesizer must relock Lock status is shown by the SLOCK bit in SYNCR During power up the

MC68HC16R1/ MC68HC916R1 USER`S MANUAL

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